Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1755	1			T2	28		T4	8		T5	3
all_values[1]	1804	1			T1	1		T2	28		T4	10
all_values[2]	1729	1			T2	28		T4	9		T5	4
all_values[3]	1704	1			T2	29		T4	7		T5	2
all_values[4]	1754	1			T2	35		T4	13		T5	5
all_values[5]	1803	1			T1	1		T2	29		T4	10
all_values[6]	1723	1			T1	1		T2	23		T4	12
all_values[7]	1807	1			T2	31		T4	13		T5	3
all_values[8]	1823	1			T2	37		T4	12		T5	2
all_values[9]	1748	1			T1	2		T2	39		T4	18
all_values[10]	1826	1			T1	1		T2	34		T4	18
all_values[11]	1783	1			T1	1		T2	32		T4	11
all_values[12]	1818	1			T1	1		T2	30		T4	15
all_values[13]	1747	1			T2	40		T4	18		T5	4
all_values[14]	1735	1			T2	29		T4	13		T5	2
all_values[15]	1738	1			T2	40		T4	17		T5	4
all_values[16]	1775	1			T1	1		T2	33		T4	14
all_values[17]	1759	1			T2	19		T4	14		T5	3
all_values[18]	1667	1			T1	3		T2	26		T4	12
all_values[19]	1761	1			T1	3		T2	33		T4	11
all_values[20]	1727	1			T2	29		T4	6		T5	3
all_values[21]	1768	1			T1	1		T2	35		T4	14
all_values[22]	1797	1			T1	1		T2	36		T4	7
all_values[23]	1765	1			T1	2		T2	31		T4	14
all_values[24]	1820	1			T2	37		T4	12		T5	4
all_values[25]	1694	1			T1	3		T2	25		T4	9
all_values[26]	1733	1			T1	1		T2	19		T4	9
all_values[27]	1670	1			T2	27		T4	14		T5	5
all_values[28]	1820	1			T2	23		T4	8		T5	3
all_values[29]	1844	1			T2	37		T4	10		T5	9
all_values[30]	1780	1			T1	1		T2	29		T4	13
all_values[31]	1832	1			T1	1		T2	22		T4	14
all_values[32]	1729	1			T1	1		T2	24		T4	10
all_values[33]	1749	1			T1	2		T2	24		T4	9
all_values[34]	1798	1			T1	1		T2	21		T4	10
all_values[35]	1764	1			T2	30		T4	21		T5	8
all_values[36]	1766	1			T1	1		T2	37		T4	13
all_values[37]	1705	1			T1	2		T2	36		T4	12
all_values[38]	1710	1			T2	29		T4	7		T5	7
all_values[39]	1808	1			T2	43		T4	12		T5	5
all_values[40]	1803	1			T2	28		T4	9		T5	4
all_values[41]	1774	1			T2	31		T4	16		T5	7
all_values[42]	1743	1			T2	35		T4	19		T5	8
all_values[43]	1815	1			T1	2		T2	23		T4	13
all_values[44]	1749	1			T2	37		T4	16		T5	6
all_values[45]	1839	1			T1	1		T2	43		T4	10
all_values[46]	1768	1			T2	31		T4	17		T5	6
all_values[47]	1730	1			T1	1		T2	29		T4	11
all_values[48]	1771	1			T2	32		T4	4		T5	5
all_values[49]	1878	1			T2	47		T4	11		T5	3
all_values[50]	1718	1			T1	1		T2	30		T4	10
all_values[51]	1729	1			T2	27		T4	15		T5	8
all_values[52]	1792	1			T1	1		T2	37		T4	9
all_values[53]	1565	1			T1	2		T2	22		T4	16
all_values[54]	1714	1			T2	21		T4	9		T5	1
all_values[55]	1763	1			T1	2		T2	35		T4	9
all_values[56]	1755	1			T1	1		T2	24		T4	12
all_values[57]	1797	1			T1	1		T2	43		T4	6
all_values[58]	1849	1			T2	28		T4	11		T5	5
all_values[59]	1766	1			T2	35		T4	9		T5	4
all_values[60]	1743	1			T1	2		T2	29		T4	12
all_values[61]	1734	1			T1	1		T2	27		T4	10
all_values[62]	1803	1			T2	31		T4	16		T5	5
all_values[63]	1725	1			T1	1		T2	38		T4	5