Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 99.26 90.10 98.80 95.82 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T759 /workspace/coverage/xbar_build_mode/10.xbar_error_random.2538214487 Mar 17 02:03:31 PM PDT 24 Mar 17 02:03:41 PM PDT 24 432820856 ps
T760 /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3665578879 Mar 17 02:04:36 PM PDT 24 Mar 17 02:04:39 PM PDT 24 62464337 ps
T761 /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2012408630 Mar 17 02:04:22 PM PDT 24 Mar 17 02:05:00 PM PDT 24 7563563973 ps
T106 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3775391918 Mar 17 02:08:57 PM PDT 24 Mar 17 02:15:47 PM PDT 24 85361372348 ps
T762 /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.494355308 Mar 17 02:10:06 PM PDT 24 Mar 17 02:11:44 PM PDT 24 14847093295 ps
T763 /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3608939613 Mar 17 02:04:52 PM PDT 24 Mar 17 02:16:39 PM PDT 24 165398198217 ps
T764 /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1844848195 Mar 17 02:08:41 PM PDT 24 Mar 17 02:09:14 PM PDT 24 5716944584 ps
T765 /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3501485736 Mar 17 02:06:03 PM PDT 24 Mar 17 02:17:05 PM PDT 24 214019154751 ps
T766 /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.469328802 Mar 17 02:02:16 PM PDT 24 Mar 17 02:02:35 PM PDT 24 382252836 ps
T767 /workspace/coverage/xbar_build_mode/15.xbar_same_source.1642159542 Mar 17 02:04:51 PM PDT 24 Mar 17 02:05:05 PM PDT 24 670818352 ps
T768 /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3545129955 Mar 17 02:04:16 PM PDT 24 Mar 17 02:05:51 PM PDT 24 3347999117 ps
T769 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.899585618 Mar 17 02:04:17 PM PDT 24 Mar 17 02:07:53 PM PDT 24 2449150648 ps
T770 /workspace/coverage/xbar_build_mode/18.xbar_random.1220164992 Mar 17 02:05:23 PM PDT 24 Mar 17 02:05:28 PM PDT 24 41082122 ps
T771 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4119897932 Mar 17 02:05:06 PM PDT 24 Mar 17 02:09:34 PM PDT 24 663666898 ps
T772 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3999629456 Mar 17 02:02:44 PM PDT 24 Mar 17 02:03:11 PM PDT 24 176344144 ps
T107 /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1335132563 Mar 17 02:01:34 PM PDT 24 Mar 17 02:04:50 PM PDT 24 5037919881 ps
T173 /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.783081484 Mar 17 02:10:39 PM PDT 24 Mar 17 02:11:15 PM PDT 24 19991431820 ps
T773 /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1452575406 Mar 17 02:06:58 PM PDT 24 Mar 17 02:08:28 PM PDT 24 9161888219 ps
T774 /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1897883756 Mar 17 02:11:09 PM PDT 24 Mar 17 02:11:27 PM PDT 24 503829620 ps
T775 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.4042476040 Mar 17 02:05:06 PM PDT 24 Mar 17 02:05:14 PM PDT 24 63165326 ps
T776 /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2359020346 Mar 17 02:09:07 PM PDT 24 Mar 17 02:09:25 PM PDT 24 114224817 ps
T777 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1490535568 Mar 17 02:11:28 PM PDT 24 Mar 17 02:22:08 PM PDT 24 154126122577 ps
T778 /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3703056128 Mar 17 02:07:23 PM PDT 24 Mar 17 02:07:51 PM PDT 24 1191879154 ps
T779 /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1651194094 Mar 17 02:08:38 PM PDT 24 Mar 17 02:09:02 PM PDT 24 118251723 ps
T780 /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.4212907004 Mar 17 02:10:43 PM PDT 24 Mar 17 02:10:59 PM PDT 24 210680873 ps
T781 /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1633200791 Mar 17 02:02:32 PM PDT 24 Mar 17 02:02:47 PM PDT 24 418451639 ps
T782 /workspace/coverage/xbar_build_mode/34.xbar_smoke.2810176879 Mar 17 02:09:20 PM PDT 24 Mar 17 02:09:23 PM PDT 24 36764892 ps
T783 /workspace/coverage/xbar_build_mode/17.xbar_same_source.3923792559 Mar 17 02:05:24 PM PDT 24 Mar 17 02:05:38 PM PDT 24 217779640 ps
T784 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1782630349 Mar 17 02:10:34 PM PDT 24 Mar 17 02:15:48 PM PDT 24 837126852 ps
T785 /workspace/coverage/xbar_build_mode/9.xbar_stress_all.102348041 Mar 17 02:03:17 PM PDT 24 Mar 17 02:08:39 PM PDT 24 13487214106 ps
T786 /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4160404656 Mar 17 02:02:10 PM PDT 24 Mar 17 02:02:46 PM PDT 24 7083403651 ps
T787 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2028900963 Mar 17 02:10:39 PM PDT 24 Mar 17 02:11:07 PM PDT 24 7826461292 ps
T788 /workspace/coverage/xbar_build_mode/28.xbar_stress_all.4040737948 Mar 17 02:08:13 PM PDT 24 Mar 17 02:10:38 PM PDT 24 9228898758 ps
T789 /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1399346825 Mar 17 02:03:06 PM PDT 24 Mar 17 02:03:39 PM PDT 24 3703596094 ps
T790 /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.861397921 Mar 17 02:11:51 PM PDT 24 Mar 17 02:12:08 PM PDT 24 166016674 ps
T791 /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.877050687 Mar 17 02:05:46 PM PDT 24 Mar 17 02:06:15 PM PDT 24 4260030417 ps
T792 /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1188928068 Mar 17 02:01:20 PM PDT 24 Mar 17 02:01:53 PM PDT 24 3705195221 ps
T793 /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2609571493 Mar 17 02:01:43 PM PDT 24 Mar 17 02:03:06 PM PDT 24 2975499542 ps
T794 /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1029388843 Mar 17 02:05:23 PM PDT 24 Mar 17 02:05:42 PM PDT 24 445153138 ps
T795 /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1568008759 Mar 17 02:10:22 PM PDT 24 Mar 17 02:10:25 PM PDT 24 45759887 ps
T796 /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3924798991 Mar 17 02:09:49 PM PDT 24 Mar 17 02:13:45 PM PDT 24 114231464486 ps
T797 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1162002839 Mar 17 02:05:52 PM PDT 24 Mar 17 02:07:44 PM PDT 24 3230767356 ps
T798 /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.32708762 Mar 17 02:11:45 PM PDT 24 Mar 17 02:16:13 PM PDT 24 214233033081 ps
T799 /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2049530268 Mar 17 02:11:17 PM PDT 24 Mar 17 02:11:44 PM PDT 24 288711196 ps
T800 /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3243463361 Mar 17 02:07:10 PM PDT 24 Mar 17 02:07:25 PM PDT 24 670488174 ps
T801 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.613758855 Mar 17 02:01:36 PM PDT 24 Mar 17 02:04:00 PM PDT 24 5930464855 ps
T802 /workspace/coverage/xbar_build_mode/35.xbar_random.2865661765 Mar 17 02:09:33 PM PDT 24 Mar 17 02:09:43 PM PDT 24 143686144 ps
T803 /workspace/coverage/xbar_build_mode/44.xbar_error_random.1979564592 Mar 17 02:11:10 PM PDT 24 Mar 17 02:11:16 PM PDT 24 37404192 ps
T804 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1143092394 Mar 17 02:09:48 PM PDT 24 Mar 17 02:11:49 PM PDT 24 12261063375 ps
T805 /workspace/coverage/xbar_build_mode/21.xbar_error_random.1396902373 Mar 17 02:06:21 PM PDT 24 Mar 17 02:06:56 PM PDT 24 767803079 ps
T806 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3408789365 Mar 17 02:07:48 PM PDT 24 Mar 17 02:08:23 PM PDT 24 282311917 ps
T807 /workspace/coverage/xbar_build_mode/47.xbar_smoke.2625435887 Mar 17 02:11:35 PM PDT 24 Mar 17 02:11:40 PM PDT 24 130267862 ps
T808 /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2716896654 Mar 17 02:08:37 PM PDT 24 Mar 17 02:08:40 PM PDT 24 43343991 ps
T809 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1461028130 Mar 17 02:01:28 PM PDT 24 Mar 17 02:05:20 PM PDT 24 8698779070 ps
T810 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1416188781 Mar 17 02:04:15 PM PDT 24 Mar 17 02:06:45 PM PDT 24 2672170332 ps
T811 /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2950192845 Mar 17 02:06:24 PM PDT 24 Mar 17 02:06:55 PM PDT 24 6935926893 ps
T812 /workspace/coverage/xbar_build_mode/6.xbar_smoke.2129360208 Mar 17 02:02:25 PM PDT 24 Mar 17 02:02:29 PM PDT 24 139912555 ps
T813 /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2878234530 Mar 17 02:01:36 PM PDT 24 Mar 17 02:01:40 PM PDT 24 32546415 ps
T814 /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.336576075 Mar 17 02:07:22 PM PDT 24 Mar 17 02:10:53 PM PDT 24 27311805437 ps
T815 /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1138087470 Mar 17 02:08:57 PM PDT 24 Mar 17 02:09:42 PM PDT 24 16429169672 ps
T816 /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2786514203 Mar 17 02:03:38 PM PDT 24 Mar 17 02:04:05 PM PDT 24 4814892360 ps
T817 /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2414115052 Mar 17 02:02:20 PM PDT 24 Mar 17 02:03:31 PM PDT 24 18607435566 ps
T818 /workspace/coverage/xbar_build_mode/4.xbar_error_random.1256051217 Mar 17 02:02:02 PM PDT 24 Mar 17 02:02:10 PM PDT 24 55222596 ps
T819 /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1535597997 Mar 17 02:08:27 PM PDT 24 Mar 17 02:08:59 PM PDT 24 6786786027 ps
T820 /workspace/coverage/xbar_build_mode/16.xbar_error_random.1205961534 Mar 17 02:05:05 PM PDT 24 Mar 17 02:05:29 PM PDT 24 315206764 ps
T821 /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.858669570 Mar 17 02:07:48 PM PDT 24 Mar 17 02:07:50 PM PDT 24 31647683 ps
T129 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2562103301 Mar 17 02:09:35 PM PDT 24 Mar 17 02:13:10 PM PDT 24 4920923355 ps
T822 /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3735720308 Mar 17 02:05:12 PM PDT 24 Mar 17 02:05:44 PM PDT 24 5113293567 ps
T823 /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1263856581 Mar 17 02:07:40 PM PDT 24 Mar 17 02:14:53 PM PDT 24 195620659835 ps
T824 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.4256051321 Mar 17 02:01:41 PM PDT 24 Mar 17 02:06:08 PM PDT 24 878514843 ps
T825 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.486209000 Mar 17 02:11:51 PM PDT 24 Mar 17 02:12:29 PM PDT 24 2613472025 ps
T826 /workspace/coverage/xbar_build_mode/8.xbar_same_source.1808898797 Mar 17 02:03:03 PM PDT 24 Mar 17 02:03:26 PM PDT 24 3369896028 ps
T827 /workspace/coverage/xbar_build_mode/29.xbar_same_source.1252846012 Mar 17 02:08:14 PM PDT 24 Mar 17 02:08:40 PM PDT 24 6493184745 ps
T828 /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1312933670 Mar 17 02:11:03 PM PDT 24 Mar 17 02:15:03 PM PDT 24 54737700226 ps
T829 /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.49814003 Mar 17 02:02:26 PM PDT 24 Mar 17 02:02:55 PM PDT 24 12190251630 ps
T830 /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3495662203 Mar 17 02:09:06 PM PDT 24 Mar 17 02:09:32 PM PDT 24 5632465014 ps
T57 /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2542960229 Mar 17 02:09:03 PM PDT 24 Mar 17 02:09:36 PM PDT 24 1382926450 ps
T831 /workspace/coverage/xbar_build_mode/5.xbar_error_random.3129281184 Mar 17 02:02:20 PM PDT 24 Mar 17 02:02:50 PM PDT 24 1557173987 ps
T832 /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.965553412 Mar 17 02:04:12 PM PDT 24 Mar 17 02:04:42 PM PDT 24 4786364712 ps
T833 /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.546270771 Mar 17 02:07:12 PM PDT 24 Mar 17 02:07:14 PM PDT 24 37521030 ps
T834 /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3630456888 Mar 17 02:09:17 PM PDT 24 Mar 17 02:09:33 PM PDT 24 113483954 ps
T835 /workspace/coverage/xbar_build_mode/37.xbar_same_source.3437710958 Mar 17 02:10:00 PM PDT 24 Mar 17 02:10:18 PM PDT 24 1589105785 ps
T836 /workspace/coverage/xbar_build_mode/23.xbar_same_source.2718200139 Mar 17 02:06:54 PM PDT 24 Mar 17 02:07:11 PM PDT 24 746156379 ps
T837 /workspace/coverage/xbar_build_mode/28.xbar_smoke.2575297756 Mar 17 02:07:58 PM PDT 24 Mar 17 02:08:02 PM PDT 24 317574812 ps
T838 /workspace/coverage/xbar_build_mode/45.xbar_random.1821102754 Mar 17 02:11:17 PM PDT 24 Mar 17 02:11:48 PM PDT 24 224506593 ps
T839 /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2346710143 Mar 17 02:08:09 PM PDT 24 Mar 17 02:08:17 PM PDT 24 55630649 ps
T840 /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3804732507 Mar 17 02:11:03 PM PDT 24 Mar 17 02:11:30 PM PDT 24 4758981242 ps
T841 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2933939337 Mar 17 02:07:01 PM PDT 24 Mar 17 02:09:15 PM PDT 24 5265105060 ps
T842 /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3223643790 Mar 17 02:08:51 PM PDT 24 Mar 17 02:09:22 PM PDT 24 13032006544 ps
T843 /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1791540605 Mar 17 02:12:00 PM PDT 24 Mar 17 02:12:25 PM PDT 24 320240951 ps
T844 /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2466430865 Mar 17 02:10:40 PM PDT 24 Mar 17 02:11:05 PM PDT 24 5437316053 ps
T845 /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.556240398 Mar 17 02:08:17 PM PDT 24 Mar 17 02:08:46 PM PDT 24 4057833418 ps
T846 /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1533724361 Mar 17 02:05:37 PM PDT 24 Mar 17 02:06:07 PM PDT 24 694779642 ps
T847 /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1661888005 Mar 17 02:10:41 PM PDT 24 Mar 17 02:12:54 PM PDT 24 54087714349 ps
T848 /workspace/coverage/xbar_build_mode/6.xbar_random.3549374507 Mar 17 02:02:32 PM PDT 24 Mar 17 02:02:52 PM PDT 24 321879259 ps
T849 /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3954593454 Mar 17 02:09:32 PM PDT 24 Mar 17 02:10:09 PM PDT 24 8623673104 ps
T850 /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3302836446 Mar 17 02:02:00 PM PDT 24 Mar 17 02:02:24 PM PDT 24 198831277 ps
T851 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3562703153 Mar 17 02:03:31 PM PDT 24 Mar 17 02:04:45 PM PDT 24 3073015897 ps
T852 /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.91173858 Mar 17 02:11:21 PM PDT 24 Mar 17 02:11:51 PM PDT 24 9125683232 ps
T853 /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2831472702 Mar 17 02:11:35 PM PDT 24 Mar 17 02:12:08 PM PDT 24 6182848828 ps
T854 /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1607875679 Mar 17 02:05:34 PM PDT 24 Mar 17 02:13:55 PM PDT 24 62120058782 ps
T855 /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3495355112 Mar 17 02:08:03 PM PDT 24 Mar 17 02:12:45 PM PDT 24 28937106656 ps
T856 /workspace/coverage/xbar_build_mode/39.xbar_stress_all.524335588 Mar 17 02:10:22 PM PDT 24 Mar 17 02:10:41 PM PDT 24 1254001118 ps
T857 /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3231941612 Mar 17 02:09:54 PM PDT 24 Mar 17 02:12:50 PM PDT 24 10971725236 ps
T858 /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.245974070 Mar 17 02:10:23 PM PDT 24 Mar 17 02:10:52 PM PDT 24 3185845224 ps
T859 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2784763208 Mar 17 02:07:59 PM PDT 24 Mar 17 02:08:50 PM PDT 24 53477305 ps
T860 /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2918668494 Mar 17 02:06:26 PM PDT 24 Mar 17 02:06:29 PM PDT 24 155839368 ps
T861 /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.4136018944 Mar 17 02:02:53 PM PDT 24 Mar 17 02:03:14 PM PDT 24 692601348 ps
T862 /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1584674364 Mar 17 02:08:51 PM PDT 24 Mar 17 02:09:16 PM PDT 24 706120402 ps
T863 /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1141946219 Mar 17 02:08:22 PM PDT 24 Mar 17 02:08:36 PM PDT 24 116827941 ps
T864 /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.148203322 Mar 17 02:05:20 PM PDT 24 Mar 17 02:05:44 PM PDT 24 162338112 ps
T865 /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2194790199 Mar 17 02:07:03 PM PDT 24 Mar 17 02:07:30 PM PDT 24 5912276154 ps
T866 /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2769952128 Mar 17 02:06:41 PM PDT 24 Mar 17 02:07:05 PM PDT 24 1163178274 ps
T867 /workspace/coverage/xbar_build_mode/49.xbar_error_random.4060705483 Mar 17 02:11:56 PM PDT 24 Mar 17 02:11:59 PM PDT 24 32704273 ps
T868 /workspace/coverage/xbar_build_mode/47.xbar_same_source.661857337 Mar 17 02:11:46 PM PDT 24 Mar 17 02:12:06 PM PDT 24 780868513 ps
T869 /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2655610035 Mar 17 02:07:40 PM PDT 24 Mar 17 02:07:51 PM PDT 24 159862036 ps
T870 /workspace/coverage/xbar_build_mode/18.xbar_same_source.2852183124 Mar 17 02:05:35 PM PDT 24 Mar 17 02:06:15 PM PDT 24 10024051039 ps
T871 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.718231090 Mar 17 02:03:50 PM PDT 24 Mar 17 02:05:35 PM PDT 24 1650012704 ps
T872 /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3970963762 Mar 17 02:09:26 PM PDT 24 Mar 17 02:14:06 PM PDT 24 57098551691 ps
T873 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2665772322 Mar 17 02:06:21 PM PDT 24 Mar 17 02:17:27 PM PDT 24 94933641965 ps
T874 /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1683534450 Mar 17 02:09:48 PM PDT 24 Mar 17 02:10:10 PM PDT 24 434781869 ps
T875 /workspace/coverage/xbar_build_mode/17.xbar_smoke.3196422518 Mar 17 02:05:11 PM PDT 24 Mar 17 02:05:17 PM PDT 24 407280789 ps
T876 /workspace/coverage/xbar_build_mode/24.xbar_stress_all.4159522937 Mar 17 02:07:10 PM PDT 24 Mar 17 02:07:13 PM PDT 24 6493392 ps
T877 /workspace/coverage/xbar_build_mode/0.xbar_smoke.2231172477 Mar 17 02:01:21 PM PDT 24 Mar 17 02:01:24 PM PDT 24 107233793 ps
T878 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1937626367 Mar 17 02:03:31 PM PDT 24 Mar 17 02:10:19 PM PDT 24 1474168250 ps
T879 /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2901590039 Mar 17 02:11:36 PM PDT 24 Mar 17 02:11:44 PM PDT 24 178312397 ps
T880 /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3540105652 Mar 17 02:03:33 PM PDT 24 Mar 17 02:03:48 PM PDT 24 134194478 ps
T881 /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2184916849 Mar 17 02:09:54 PM PDT 24 Mar 17 02:10:12 PM PDT 24 113285794 ps
T882 /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.391758150 Mar 17 02:10:17 PM PDT 24 Mar 17 02:20:25 PM PDT 24 236883555773 ps
T883 /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.4273015709 Mar 17 02:01:43 PM PDT 24 Mar 17 02:05:31 PM PDT 24 42003488341 ps
T24 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1067287750 Mar 17 02:09:33 PM PDT 24 Mar 17 02:15:25 PM PDT 24 8670133640 ps
T884 /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3941346761 Mar 17 02:02:32 PM PDT 24 Mar 17 02:04:47 PM PDT 24 28905620551 ps
T885 /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.630101930 Mar 17 02:02:26 PM PDT 24 Mar 17 02:02:52 PM PDT 24 3136417508 ps
T886 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1935533525 Mar 17 02:02:37 PM PDT 24 Mar 17 02:05:01 PM PDT 24 3502251246 ps
T887 /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.995215642 Mar 17 02:03:37 PM PDT 24 Mar 17 02:04:12 PM PDT 24 8286475354 ps
T888 /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1332678313 Mar 17 02:01:48 PM PDT 24 Mar 17 02:02:18 PM PDT 24 4791490426 ps
T889 /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1726434972 Mar 17 02:03:24 PM PDT 24 Mar 17 02:03:51 PM PDT 24 19169752259 ps
T890 /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1730611702 Mar 17 02:09:42 PM PDT 24 Mar 17 02:10:17 PM PDT 24 15623410519 ps
T891 /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1375635960 Mar 17 02:02:48 PM PDT 24 Mar 17 02:02:58 PM PDT 24 320856599 ps
T892 /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1793864120 Mar 17 02:03:38 PM PDT 24 Mar 17 02:07:56 PM PDT 24 72224648870 ps
T893 /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3788689367 Mar 17 02:05:47 PM PDT 24 Mar 17 02:06:23 PM PDT 24 15695347917 ps
T894 /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3603976799 Mar 17 02:03:24 PM PDT 24 Mar 17 02:04:01 PM PDT 24 15326358968 ps
T190 /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3386293105 Mar 17 02:01:51 PM PDT 24 Mar 17 02:05:29 PM PDT 24 50336534998 ps
T895 /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1490401116 Mar 17 02:02:52 PM PDT 24 Mar 17 02:02:55 PM PDT 24 32497098 ps
T896 /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.689432814 Mar 17 02:09:14 PM PDT 24 Mar 17 02:16:15 PM PDT 24 136428513484 ps
T897 /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1043014224 Mar 17 02:04:11 PM PDT 24 Mar 17 02:04:13 PM PDT 24 32145592 ps
T898 /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4078701885 Mar 17 02:09:42 PM PDT 24 Mar 17 02:10:13 PM PDT 24 5017675955 ps
T899 /workspace/coverage/xbar_build_mode/2.xbar_error_random.3883760376 Mar 17 02:01:42 PM PDT 24 Mar 17 02:02:19 PM PDT 24 1490399192 ps
T900 /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4056300612 Mar 17 02:08:54 PM PDT 24 Mar 17 02:09:21 PM PDT 24 835806327 ps
T185 /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.287144493 Mar 17 02:03:56 PM PDT 24 Mar 17 02:05:55 PM PDT 24 34447367596 ps

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1118617742
Short name T1
Test name
Test status
Simulation time 3664274571 ps
CPU time 122.99 seconds
Started Mar 17 02:10:49 PM PDT 24
Finished Mar 17 02:12:53 PM PDT 24
Peak memory 208864 kb
Host smart-b54cd5d2-e96c-4bde-8277-e0d9e5abebdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1118617742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1118617742
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2858824577
Short name T124
Test name
Test status
Simulation time 242576377820 ps
CPU time 785.92 seconds
Started Mar 17 02:01:21 PM PDT 24
Finished Mar 17 02:14:27 PM PDT 24
Peak memory 206376 kb
Host smart-cb75a7fb-9e29-401d-b2c0-4f1b7c0797b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2858824577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2858824577
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.39618943
Short name T212
Test name
Test status
Simulation time 94789632548 ps
CPU time 587.7 seconds
Started Mar 17 02:02:33 PM PDT 24
Finished Mar 17 02:12:20 PM PDT 24
Peak memory 207516 kb
Host smart-c5f139df-f297-45be-ae32-9d3a1473b987
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=39618943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.39618943
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.97556540
Short name T16
Test name
Test status
Simulation time 1775267603 ps
CPU time 129.79 seconds
Started Mar 17 02:10:34 PM PDT 24
Finished Mar 17 02:12:44 PM PDT 24
Peak memory 211332 kb
Host smart-bed68e58-9647-4fdd-a61d-010db760b9c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97556540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rese
t_error.97556540
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.945129984
Short name T60
Test name
Test status
Simulation time 416631902494 ps
CPU time 756.07 seconds
Started Mar 17 02:10:27 PM PDT 24
Finished Mar 17 02:23:03 PM PDT 24
Peak memory 211976 kb
Host smart-90565c8b-77c2-427c-acbb-098d8d61eee6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=945129984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.945129984
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.475791756
Short name T67
Test name
Test status
Simulation time 57078957317 ps
CPU time 441.46 seconds
Started Mar 17 02:06:54 PM PDT 24
Finished Mar 17 02:14:16 PM PDT 24
Peak memory 206368 kb
Host smart-d1f03f16-5448-4120-8e6a-c2b49714ad21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=475791756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo
w_rsp.475791756
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2557451912
Short name T10
Test name
Test status
Simulation time 5415754135 ps
CPU time 29.85 seconds
Started Mar 17 02:01:28 PM PDT 24
Finished Mar 17 02:01:58 PM PDT 24
Peak memory 203796 kb
Host smart-76bacca0-385d-4832-b954-1db663e4318c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557451912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2557451912
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4086844686
Short name T2
Test name
Test status
Simulation time 5866920758 ps
CPU time 409.69 seconds
Started Mar 17 02:08:10 PM PDT 24
Finished Mar 17 02:15:00 PM PDT 24
Peak memory 209260 kb
Host smart-31d05ce0-70af-4a91-a7b9-8a71c9fb2507
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4086844686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.4086844686
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1919336961
Short name T75
Test name
Test status
Simulation time 46748506566 ps
CPU time 405.6 seconds
Started Mar 17 02:09:36 PM PDT 24
Finished Mar 17 02:16:22 PM PDT 24
Peak memory 211944 kb
Host smart-1cd65c6c-21d9-4dc0-b045-448f2afa3ae0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1919336961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.1919336961
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1655470367
Short name T4
Test name
Test status
Simulation time 275429527 ps
CPU time 169.47 seconds
Started Mar 17 02:11:10 PM PDT 24
Finished Mar 17 02:14:00 PM PDT 24
Peak memory 208660 kb
Host smart-500bbeb7-33df-4cd6-94e8-e34858500c14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1655470367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.1655470367
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2681474963
Short name T145
Test name
Test status
Simulation time 6880835257 ps
CPU time 233.62 seconds
Started Mar 17 02:11:34 PM PDT 24
Finished Mar 17 02:15:28 PM PDT 24
Peak memory 210056 kb
Host smart-1f6901cc-6b4a-4e85-a0f7-e81c22a47003
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2681474963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.2681474963
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3863974866
Short name T26
Test name
Test status
Simulation time 792534668 ps
CPU time 145.97 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:09:08 PM PDT 24
Peak memory 211032 kb
Host smart-12213b17-13fd-41b0-8ec0-00c23aa4bc50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3863974866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.3863974866
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1067287750
Short name T24
Test name
Test status
Simulation time 8670133640 ps
CPU time 351.77 seconds
Started Mar 17 02:09:33 PM PDT 24
Finished Mar 17 02:15:25 PM PDT 24
Peak memory 211568 kb
Host smart-ca98ddb0-d5e2-49c2-9a8d-6e45d30b5382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1067287750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1067287750
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.4118039338
Short name T90
Test name
Test status
Simulation time 1327880340 ps
CPU time 51.72 seconds
Started Mar 17 02:11:16 PM PDT 24
Finished Mar 17 02:12:08 PM PDT 24
Peak memory 205664 kb
Host smart-27d47abe-a943-4805-a05b-1cc817c29aeb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4118039338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.4118039338
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3926847341
Short name T452
Test name
Test status
Simulation time 12921937269 ps
CPU time 350.74 seconds
Started Mar 17 02:06:21 PM PDT 24
Finished Mar 17 02:12:12 PM PDT 24
Peak memory 209988 kb
Host smart-239a47ec-0e52-41a6-baaa-89507246d88e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3926847341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.3926847341
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3341290222
Short name T18
Test name
Test status
Simulation time 8250275805 ps
CPU time 195.27 seconds
Started Mar 17 02:04:37 PM PDT 24
Finished Mar 17 02:07:52 PM PDT 24
Peak memory 210236 kb
Host smart-3ca6e4f8-5537-411e-a6f4-38dce852328a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3341290222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3341290222
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3870889247
Short name T29
Test name
Test status
Simulation time 3507843146 ps
CPU time 698.62 seconds
Started Mar 17 02:04:56 PM PDT 24
Finished Mar 17 02:16:36 PM PDT 24
Peak memory 209784 kb
Host smart-7af219c9-178e-43fe-a3e6-58ccbe5a02ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3870889247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.3870889247
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2756553543
Short name T31
Test name
Test status
Simulation time 397296180 ps
CPU time 188.52 seconds
Started Mar 17 02:01:49 PM PDT 24
Finished Mar 17 02:04:59 PM PDT 24
Peak memory 209292 kb
Host smart-38fa48ee-137b-4cae-b590-57530d2a999f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2756553543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.2756553543
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.899585618
Short name T769
Test name
Test status
Simulation time 2449150648 ps
CPU time 216.52 seconds
Started Mar 17 02:04:17 PM PDT 24
Finished Mar 17 02:07:53 PM PDT 24
Peak memory 209304 kb
Host smart-b4255c2f-207c-49ee-b6d4-8e80c6f5be90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=899585618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand
_reset.899585618
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2652503318
Short name T105
Test name
Test status
Simulation time 15370438556 ps
CPU time 198.26 seconds
Started Mar 17 02:04:04 PM PDT 24
Finished Mar 17 02:07:22 PM PDT 24
Peak memory 210420 kb
Host smart-2de9e4a5-5cc6-4cd6-858d-66e5e7ba6a1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2652503318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2652503318
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2789529628
Short name T611
Test name
Test status
Simulation time 493873438 ps
CPU time 37.69 seconds
Started Mar 17 02:01:20 PM PDT 24
Finished Mar 17 02:01:58 PM PDT 24
Peak memory 204492 kb
Host smart-3bd6acb7-8b55-4aaf-80a5-82e9cd364da8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2789529628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2789529628
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.773840470
Short name T695
Test name
Test status
Simulation time 135824873 ps
CPU time 16.85 seconds
Started Mar 17 02:01:29 PM PDT 24
Finished Mar 17 02:01:46 PM PDT 24
Peak memory 203912 kb
Host smart-95e89347-523b-435f-9d9c-94b6614c1a4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=773840470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.773840470
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.328060090
Short name T754
Test name
Test status
Simulation time 393047497 ps
CPU time 10.96 seconds
Started Mar 17 02:01:27 PM PDT 24
Finished Mar 17 02:01:38 PM PDT 24
Peak memory 203724 kb
Host smart-23f053fc-4cf2-4708-833a-02c568741189
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328060090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.328060090
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.1875158382
Short name T11
Test name
Test status
Simulation time 76579760 ps
CPU time 6.07 seconds
Started Mar 17 02:01:22 PM PDT 24
Finished Mar 17 02:01:28 PM PDT 24
Peak memory 204868 kb
Host smart-953195ab-03a2-4ad7-9464-f4e41845aa1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1875158382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1875158382
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.761091255
Short name T722
Test name
Test status
Simulation time 33316867033 ps
CPU time 171.93 seconds
Started Mar 17 02:01:21 PM PDT 24
Finished Mar 17 02:04:13 PM PDT 24
Peak memory 205528 kb
Host smart-e836649e-dae1-479a-a3d2-19cf574f268c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=761091255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.761091255
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1636309377
Short name T524
Test name
Test status
Simulation time 14321516906 ps
CPU time 51.3 seconds
Started Mar 17 02:01:19 PM PDT 24
Finished Mar 17 02:02:11 PM PDT 24
Peak memory 211944 kb
Host smart-a9ee48da-e047-4ae6-9ecc-06fb5222c94c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1636309377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1636309377
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1779890159
Short name T632
Test name
Test status
Simulation time 64395045 ps
CPU time 9.51 seconds
Started Mar 17 02:01:20 PM PDT 24
Finished Mar 17 02:01:29 PM PDT 24
Peak memory 204860 kb
Host smart-84ed1d12-e9b5-47d3-9089-ff149c0f07b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779890159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1779890159
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.4060471085
Short name T277
Test name
Test status
Simulation time 432975137 ps
CPU time 5.39 seconds
Started Mar 17 02:01:28 PM PDT 24
Finished Mar 17 02:01:34 PM PDT 24
Peak memory 203760 kb
Host smart-02784d9a-94e8-49bf-bb24-aaa532c938e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4060471085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4060471085
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.2231172477
Short name T877
Test name
Test status
Simulation time 107233793 ps
CPU time 2.29 seconds
Started Mar 17 02:01:21 PM PDT 24
Finished Mar 17 02:01:24 PM PDT 24
Peak memory 203668 kb
Host smart-32b236db-cf7a-47e5-b236-595c1c832990
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2231172477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2231172477
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2559344453
Short name T511
Test name
Test status
Simulation time 9212219152 ps
CPU time 27.73 seconds
Started Mar 17 02:01:19 PM PDT 24
Finished Mar 17 02:01:47 PM PDT 24
Peak memory 203792 kb
Host smart-cf1a04ef-b982-400d-9b01-5a2689bebcd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559344453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2559344453
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1188928068
Short name T792
Test name
Test status
Simulation time 3705195221 ps
CPU time 33.31 seconds
Started Mar 17 02:01:20 PM PDT 24
Finished Mar 17 02:01:53 PM PDT 24
Peak memory 203736 kb
Host smart-913e6611-ed06-4184-b28b-3bd953ea303f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1188928068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1188928068
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2033652301
Short name T203
Test name
Test status
Simulation time 69858835 ps
CPU time 2.56 seconds
Started Mar 17 02:01:19 PM PDT 24
Finished Mar 17 02:01:22 PM PDT 24
Peak memory 203700 kb
Host smart-87f73730-d0ab-446c-a480-b71f25dae896
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033652301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2033652301
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2794408836
Short name T450
Test name
Test status
Simulation time 12513299678 ps
CPU time 200.08 seconds
Started Mar 17 02:01:27 PM PDT 24
Finished Mar 17 02:04:47 PM PDT 24
Peak memory 207528 kb
Host smart-b4008fe5-a765-4aeb-9b0d-badaa7894541
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2794408836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2794408836
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1461028130
Short name T809
Test name
Test status
Simulation time 8698779070 ps
CPU time 232.47 seconds
Started Mar 17 02:01:28 PM PDT 24
Finished Mar 17 02:05:20 PM PDT 24
Peak memory 209216 kb
Host smart-8bd2eea1-6c99-4765-8295-916832ffa1b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1461028130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1461028130
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3276557161
Short name T492
Test name
Test status
Simulation time 15996515417 ps
CPU time 464.28 seconds
Started Mar 17 02:01:28 PM PDT 24
Finished Mar 17 02:09:13 PM PDT 24
Peak memory 211908 kb
Host smart-a64bbdcd-5478-4a35-9f75-546fc67cd0a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3276557161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.3276557161
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1454267689
Short name T661
Test name
Test status
Simulation time 178851353 ps
CPU time 40.24 seconds
Started Mar 17 02:01:28 PM PDT 24
Finished Mar 17 02:02:09 PM PDT 24
Peak memory 206500 kb
Host smart-e5c2b34e-c884-495c-a57e-65a1cf0751ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1454267689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.1454267689
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1527307823
Short name T728
Test name
Test status
Simulation time 3140034393 ps
CPU time 21.5 seconds
Started Mar 17 02:01:26 PM PDT 24
Finished Mar 17 02:01:48 PM PDT 24
Peak memory 211968 kb
Host smart-1bec67e6-424d-4fb8-833a-062c85dcfb7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1527307823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1527307823
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.653460397
Short name T179
Test name
Test status
Simulation time 949002035 ps
CPU time 50.71 seconds
Started Mar 17 02:01:33 PM PDT 24
Finished Mar 17 02:02:24 PM PDT 24
Peak memory 206268 kb
Host smart-6a13773c-6353-4771-bc4e-14ffdb78bc62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=653460397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.653460397
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3151406651
Short name T138
Test name
Test status
Simulation time 15981517990 ps
CPU time 35.64 seconds
Started Mar 17 02:01:34 PM PDT 24
Finished Mar 17 02:02:10 PM PDT 24
Peak memory 204464 kb
Host smart-15c111eb-5fe4-409d-bf23-96fb653eeb70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3151406651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.3151406651
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2120295602
Short name T415
Test name
Test status
Simulation time 663449509 ps
CPU time 17.78 seconds
Started Mar 17 02:01:35 PM PDT 24
Finished Mar 17 02:01:53 PM PDT 24
Peak memory 203744 kb
Host smart-3253bc86-ec5d-44a1-af5a-392249ebee98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2120295602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2120295602
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.2843542046
Short name T406
Test name
Test status
Simulation time 553262986 ps
CPU time 15.11 seconds
Started Mar 17 02:01:35 PM PDT 24
Finished Mar 17 02:01:50 PM PDT 24
Peak memory 203612 kb
Host smart-e8ccc698-8c2c-4f27-8f7a-3131599c1969
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2843542046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2843542046
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.460138178
Short name T758
Test name
Test status
Simulation time 111646805 ps
CPU time 10.21 seconds
Started Mar 17 02:01:36 PM PDT 24
Finished Mar 17 02:01:47 PM PDT 24
Peak memory 204776 kb
Host smart-b1ee83d0-b215-4072-b623-5317196afa82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=460138178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.460138178
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2282183329
Short name T304
Test name
Test status
Simulation time 27944557355 ps
CPU time 167.28 seconds
Started Mar 17 02:01:33 PM PDT 24
Finished Mar 17 02:04:21 PM PDT 24
Peak memory 204960 kb
Host smart-4ec59ed9-f8e1-4435-b1c2-b66e474c3f86
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282183329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2282183329
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1596204923
Short name T614
Test name
Test status
Simulation time 18264753606 ps
CPU time 131.84 seconds
Started Mar 17 02:01:35 PM PDT 24
Finished Mar 17 02:03:47 PM PDT 24
Peak memory 211884 kb
Host smart-0b02b22c-8a64-4464-a9e2-e1228b8d57ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1596204923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1596204923
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.954178462
Short name T371
Test name
Test status
Simulation time 304873586 ps
CPU time 32.09 seconds
Started Mar 17 02:01:27 PM PDT 24
Finished Mar 17 02:01:59 PM PDT 24
Peak memory 211916 kb
Host smart-69a509b8-83c3-496a-a1dc-f05712ee1175
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954178462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.954178462
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.2083363030
Short name T468
Test name
Test status
Simulation time 466737870 ps
CPU time 11.54 seconds
Started Mar 17 02:01:36 PM PDT 24
Finished Mar 17 02:01:48 PM PDT 24
Peak memory 204180 kb
Host smart-84596ef1-58e0-4619-99f8-0ae9437364f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2083363030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2083363030
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.3178656427
Short name T422
Test name
Test status
Simulation time 52237299 ps
CPU time 2.42 seconds
Started Mar 17 02:01:36 PM PDT 24
Finished Mar 17 02:01:39 PM PDT 24
Peak memory 203732 kb
Host smart-68190ff1-78bd-4715-85a4-9f182e6a794a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3178656427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3178656427
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2943588790
Short name T56
Test name
Test status
Simulation time 9335682975 ps
CPU time 28.69 seconds
Started Mar 17 02:01:28 PM PDT 24
Finished Mar 17 02:01:57 PM PDT 24
Peak memory 203768 kb
Host smart-47b8cbdf-83a8-4c23-88c5-9b58fe557c7e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2943588790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2943588790
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2060549501
Short name T702
Test name
Test status
Simulation time 30612370 ps
CPU time 2.45 seconds
Started Mar 17 02:01:30 PM PDT 24
Finished Mar 17 02:01:32 PM PDT 24
Peak memory 203692 kb
Host smart-c86cbf61-dd30-47ed-83ad-df6da56a9137
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060549501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2060549501
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1335132563
Short name T107
Test name
Test status
Simulation time 5037919881 ps
CPU time 196.33 seconds
Started Mar 17 02:01:34 PM PDT 24
Finished Mar 17 02:04:50 PM PDT 24
Peak memory 206628 kb
Host smart-d4369fdc-a9c6-4027-899b-d66991753d96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1335132563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1335132563
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.613758855
Short name T801
Test name
Test status
Simulation time 5930464855 ps
CPU time 143.78 seconds
Started Mar 17 02:01:36 PM PDT 24
Finished Mar 17 02:04:00 PM PDT 24
Peak memory 210592 kb
Host smart-5e08ab6c-6623-4078-9171-c4bb3c6572af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=613758855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.613758855
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2663775907
Short name T627
Test name
Test status
Simulation time 558264821 ps
CPU time 153.62 seconds
Started Mar 17 02:01:34 PM PDT 24
Finished Mar 17 02:04:09 PM PDT 24
Peak memory 207992 kb
Host smart-374f26e2-1671-417c-ad5e-b0c5ec8b7828
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2663775907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.2663775907
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.238811937
Short name T442
Test name
Test status
Simulation time 5362731526 ps
CPU time 328.58 seconds
Started Mar 17 02:01:35 PM PDT 24
Finished Mar 17 02:07:04 PM PDT 24
Peak memory 220228 kb
Host smart-b8301b74-580b-400a-bd21-62df4ab614d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=238811937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese
t_error.238811937
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3572719520
Short name T191
Test name
Test status
Simulation time 2387296618 ps
CPU time 27.24 seconds
Started Mar 17 02:01:35 PM PDT 24
Finished Mar 17 02:02:02 PM PDT 24
Peak memory 211996 kb
Host smart-f78eea69-fef5-450b-8a65-d812c21a7ffa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3572719520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3572719520
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3437013149
Short name T721
Test name
Test status
Simulation time 3749508372 ps
CPU time 61.23 seconds
Started Mar 17 02:03:24 PM PDT 24
Finished Mar 17 02:04:26 PM PDT 24
Peak memory 205736 kb
Host smart-09ca5741-8fb4-480e-98e8-eab5f2566025
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437013149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3437013149
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2139704305
Short name T86
Test name
Test status
Simulation time 108343871443 ps
CPU time 482.82 seconds
Started Mar 17 02:03:25 PM PDT 24
Finished Mar 17 02:11:31 PM PDT 24
Peak memory 207156 kb
Host smart-05e087f3-e2b2-41eb-a7f5-a658fef08e02
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2139704305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.2139704305
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3540105652
Short name T880
Test name
Test status
Simulation time 134194478 ps
CPU time 15.37 seconds
Started Mar 17 02:03:33 PM PDT 24
Finished Mar 17 02:03:48 PM PDT 24
Peak memory 204204 kb
Host smart-817ca3b9-1830-402d-8b09-70183306c56c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3540105652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3540105652
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.2538214487
Short name T759
Test name
Test status
Simulation time 432820856 ps
CPU time 9.96 seconds
Started Mar 17 02:03:31 PM PDT 24
Finished Mar 17 02:03:41 PM PDT 24
Peak memory 203628 kb
Host smart-5dd5e537-6b1b-46e5-9c86-d6dc7114e4fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2538214487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2538214487
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.431434123
Short name T483
Test name
Test status
Simulation time 6207957848 ps
CPU time 40.38 seconds
Started Mar 17 02:03:26 PM PDT 24
Finished Mar 17 02:04:09 PM PDT 24
Peak memory 204896 kb
Host smart-0261a956-c121-4067-9514-deda071e3a54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=431434123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.431434123
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1726434972
Short name T889
Test name
Test status
Simulation time 19169752259 ps
CPU time 26.52 seconds
Started Mar 17 02:03:24 PM PDT 24
Finished Mar 17 02:03:51 PM PDT 24
Peak memory 203728 kb
Host smart-1112c402-4508-449f-9003-a2bbbfa549ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726434972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1726434972
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3214952906
Short name T448
Test name
Test status
Simulation time 47903148553 ps
CPU time 196.86 seconds
Started Mar 17 02:03:25 PM PDT 24
Finished Mar 17 02:06:45 PM PDT 24
Peak memory 205472 kb
Host smart-e4e4cc67-c921-4f63-a38e-15c8b9d6d701
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3214952906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3214952906
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3724704103
Short name T618
Test name
Test status
Simulation time 1067105471 ps
CPU time 34.12 seconds
Started Mar 17 02:03:24 PM PDT 24
Finished Mar 17 02:03:58 PM PDT 24
Peak memory 204992 kb
Host smart-b80b6e6e-92e0-4a6b-9912-ebff58cfb994
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724704103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3724704103
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.1530778034
Short name T164
Test name
Test status
Simulation time 355585454 ps
CPU time 8.41 seconds
Started Mar 17 02:03:32 PM PDT 24
Finished Mar 17 02:03:41 PM PDT 24
Peak memory 204108 kb
Host smart-67ef228b-c950-49ab-a0a2-038268bc2baa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1530778034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1530778034
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.547912845
Short name T313
Test name
Test status
Simulation time 35033396 ps
CPU time 1.89 seconds
Started Mar 17 02:03:19 PM PDT 24
Finished Mar 17 02:03:21 PM PDT 24
Peak memory 203716 kb
Host smart-2f216ec0-3500-46c8-b85b-50621e25b179
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547912845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.547912845
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3603976799
Short name T894
Test name
Test status
Simulation time 15326358968 ps
CPU time 36.62 seconds
Started Mar 17 02:03:24 PM PDT 24
Finished Mar 17 02:04:01 PM PDT 24
Peak memory 203804 kb
Host smart-2bf5d672-f888-4d34-89c1-dad88d8dc2e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603976799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3603976799
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3686645429
Short name T183
Test name
Test status
Simulation time 2491959462 ps
CPU time 23.28 seconds
Started Mar 17 02:03:25 PM PDT 24
Finished Mar 17 02:03:52 PM PDT 24
Peak memory 203820 kb
Host smart-57d1d4a1-78cc-44bd-bde9-304bf053c97e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3686645429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3686645429
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.800383142
Short name T217
Test name
Test status
Simulation time 27856602 ps
CPU time 2.24 seconds
Started Mar 17 02:03:20 PM PDT 24
Finished Mar 17 02:03:22 PM PDT 24
Peak memory 203704 kb
Host smart-2646757f-ce3e-4d66-9b36-e5713b1d0a7d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800383142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.800383142
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1784306902
Short name T71
Test name
Test status
Simulation time 960701105 ps
CPU time 27.83 seconds
Started Mar 17 02:03:33 PM PDT 24
Finished Mar 17 02:04:01 PM PDT 24
Peak memory 205260 kb
Host smart-74c7e0c3-d479-4bac-a859-12c1e972d72b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1784306902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1784306902
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3562703153
Short name T851
Test name
Test status
Simulation time 3073015897 ps
CPU time 73.74 seconds
Started Mar 17 02:03:31 PM PDT 24
Finished Mar 17 02:04:45 PM PDT 24
Peak memory 204948 kb
Host smart-a9bafa5d-97ab-43c2-acf9-6d3075d8475f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3562703153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3562703153
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1937626367
Short name T878
Test name
Test status
Simulation time 1474168250 ps
CPU time 407.88 seconds
Started Mar 17 02:03:31 PM PDT 24
Finished Mar 17 02:10:19 PM PDT 24
Peak memory 211336 kb
Host smart-dfed9237-aa64-4228-a405-0835685ca4ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1937626367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.1937626367
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1646015420
Short name T743
Test name
Test status
Simulation time 470196773 ps
CPU time 147.6 seconds
Started Mar 17 02:03:31 PM PDT 24
Finished Mar 17 02:06:00 PM PDT 24
Peak memory 211608 kb
Host smart-2c0d99b6-1a2e-4516-9f28-4acfbc712034
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1646015420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.1646015420
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2265233152
Short name T691
Test name
Test status
Simulation time 349150202 ps
CPU time 14.72 seconds
Started Mar 17 02:03:32 PM PDT 24
Finished Mar 17 02:03:48 PM PDT 24
Peak memory 205008 kb
Host smart-7860828f-789c-4bb5-ae3d-9b9eae9ad847
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2265233152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2265233152
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.838371658
Short name T88
Test name
Test status
Simulation time 1251293020 ps
CPU time 62.29 seconds
Started Mar 17 02:03:36 PM PDT 24
Finished Mar 17 02:04:39 PM PDT 24
Peak memory 206580 kb
Host smart-b72ad420-3801-40a3-a19b-f6b2ebf9d312
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=838371658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.838371658
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1275963402
Short name T707
Test name
Test status
Simulation time 50093237967 ps
CPU time 452.22 seconds
Started Mar 17 02:03:38 PM PDT 24
Finished Mar 17 02:11:11 PM PDT 24
Peak memory 211996 kb
Host smart-1ece68ac-ca82-4eab-adf6-d5a6b8eb060a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1275963402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.1275963402
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.466328737
Short name T625
Test name
Test status
Simulation time 1118831503 ps
CPU time 32.55 seconds
Started Mar 17 02:03:43 PM PDT 24
Finished Mar 17 02:04:16 PM PDT 24
Peak memory 203904 kb
Host smart-f9ad4cee-3d04-4765-9720-8c1409c27cd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=466328737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.466328737
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.3007553946
Short name T300
Test name
Test status
Simulation time 50183920 ps
CPU time 2.64 seconds
Started Mar 17 02:03:44 PM PDT 24
Finished Mar 17 02:03:47 PM PDT 24
Peak memory 203692 kb
Host smart-8795e773-1156-44a2-8d1d-0a1f34e25a43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3007553946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3007553946
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.1103298860
Short name T520
Test name
Test status
Simulation time 15959646 ps
CPU time 2.24 seconds
Started Mar 17 02:03:37 PM PDT 24
Finished Mar 17 02:03:40 PM PDT 24
Peak memory 203624 kb
Host smart-f199d68b-e1ad-44ab-86d9-11be8c9a46fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1103298860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1103298860
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2076657979
Short name T570
Test name
Test status
Simulation time 99284803732 ps
CPU time 179.88 seconds
Started Mar 17 02:03:38 PM PDT 24
Finished Mar 17 02:06:38 PM PDT 24
Peak memory 205000 kb
Host smart-f87d10be-f728-4cb3-94e9-26822c1e6c19
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076657979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2076657979
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1793864120
Short name T892
Test name
Test status
Simulation time 72224648870 ps
CPU time 258.18 seconds
Started Mar 17 02:03:38 PM PDT 24
Finished Mar 17 02:07:56 PM PDT 24
Peak memory 211928 kb
Host smart-9291351f-e9a8-4edf-96a9-4cf130364262
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1793864120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1793864120
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2312322234
Short name T739
Test name
Test status
Simulation time 280601804 ps
CPU time 28.87 seconds
Started Mar 17 02:03:38 PM PDT 24
Finished Mar 17 02:04:08 PM PDT 24
Peak memory 205048 kb
Host smart-1a570647-01ec-4e90-8924-1fef014c943c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312322234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2312322234
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.686408418
Short name T677
Test name
Test status
Simulation time 232265373 ps
CPU time 11.3 seconds
Started Mar 17 02:03:42 PM PDT 24
Finished Mar 17 02:03:54 PM PDT 24
Peak memory 204208 kb
Host smart-163fd620-976d-4028-83c5-4362ae1b3f51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=686408418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.686408418
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.2075858667
Short name T435
Test name
Test status
Simulation time 322551826 ps
CPU time 3.88 seconds
Started Mar 17 02:03:31 PM PDT 24
Finished Mar 17 02:03:36 PM PDT 24
Peak memory 203712 kb
Host smart-3a28909d-86e1-4c52-b97b-76105e4c4998
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2075858667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2075858667
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.995215642
Short name T887
Test name
Test status
Simulation time 8286475354 ps
CPU time 34.67 seconds
Started Mar 17 02:03:37 PM PDT 24
Finished Mar 17 02:04:12 PM PDT 24
Peak memory 203700 kb
Host smart-6aae6f1d-d1d8-43a3-a116-aaa6df5ae68c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=995215642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.995215642
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2786514203
Short name T816
Test name
Test status
Simulation time 4814892360 ps
CPU time 26.53 seconds
Started Mar 17 02:03:38 PM PDT 24
Finished Mar 17 02:04:05 PM PDT 24
Peak memory 203760 kb
Host smart-a6ea1e9b-78d8-46fc-beef-fdc50986b06a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2786514203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2786514203
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3757850773
Short name T680
Test name
Test status
Simulation time 35752818 ps
CPU time 2.9 seconds
Started Mar 17 02:03:37 PM PDT 24
Finished Mar 17 02:03:40 PM PDT 24
Peak memory 203684 kb
Host smart-bd92fafc-348a-4313-8d3c-6f3ef48a72f2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757850773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3757850773
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1547257971
Short name T79
Test name
Test status
Simulation time 18646024228 ps
CPU time 254.59 seconds
Started Mar 17 02:03:50 PM PDT 24
Finished Mar 17 02:08:05 PM PDT 24
Peak memory 206740 kb
Host smart-c07dd947-cbfa-41ba-8625-a67e91421669
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1547257971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1547257971
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.718231090
Short name T871
Test name
Test status
Simulation time 1650012704 ps
CPU time 104.89 seconds
Started Mar 17 02:03:50 PM PDT 24
Finished Mar 17 02:05:35 PM PDT 24
Peak memory 205588 kb
Host smart-956f8cf5-72b1-456b-a108-f2973c22aabd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=718231090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.718231090
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1765248641
Short name T80
Test name
Test status
Simulation time 528221528 ps
CPU time 219.04 seconds
Started Mar 17 02:03:51 PM PDT 24
Finished Mar 17 02:07:30 PM PDT 24
Peak memory 208860 kb
Host smart-12198e52-85ef-445f-8298-7a95b56521bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1765248641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.1765248641
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.280583217
Short name T684
Test name
Test status
Simulation time 869527392 ps
CPU time 147.97 seconds
Started Mar 17 02:03:50 PM PDT 24
Finished Mar 17 02:06:18 PM PDT 24
Peak memory 208996 kb
Host smart-7d4b8e68-bbc8-4b98-89db-85b3cae019e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=280583217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res
et_error.280583217
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2334264492
Short name T17
Test name
Test status
Simulation time 105163134 ps
CPU time 9.83 seconds
Started Mar 17 02:03:43 PM PDT 24
Finished Mar 17 02:03:53 PM PDT 24
Peak memory 211888 kb
Host smart-615630e8-10b2-460d-aced-70ba3fdc77f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2334264492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2334264492
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1066697815
Short name T523
Test name
Test status
Simulation time 36977104 ps
CPU time 3.06 seconds
Started Mar 17 02:03:55 PM PDT 24
Finished Mar 17 02:03:59 PM PDT 24
Peak memory 203736 kb
Host smart-32b1511b-557d-45af-9184-27068d2be930
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1066697815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1066697815
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3004943309
Short name T85
Test name
Test status
Simulation time 52162232702 ps
CPU time 505.69 seconds
Started Mar 17 02:03:57 PM PDT 24
Finished Mar 17 02:12:23 PM PDT 24
Peak memory 211944 kb
Host smart-33fb5d5a-6832-44a3-8ff4-506d12e8b3c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3004943309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.3004943309
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.581549945
Short name T487
Test name
Test status
Simulation time 410191446 ps
CPU time 13.18 seconds
Started Mar 17 02:04:04 PM PDT 24
Finished Mar 17 02:04:18 PM PDT 24
Peak memory 204116 kb
Host smart-15453064-ef7f-45c3-8ca6-655f88f960b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=581549945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.581549945
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.3973103346
Short name T459
Test name
Test status
Simulation time 2894922727 ps
CPU time 40.53 seconds
Started Mar 17 02:04:02 PM PDT 24
Finished Mar 17 02:04:42 PM PDT 24
Peak memory 203792 kb
Host smart-8e81bdea-7b3c-4109-bb46-42e09d3576ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3973103346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3973103346
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.3108684050
Short name T463
Test name
Test status
Simulation time 162291206 ps
CPU time 14.12 seconds
Started Mar 17 02:03:56 PM PDT 24
Finished Mar 17 02:04:10 PM PDT 24
Peak memory 204880 kb
Host smart-9defef43-7b6e-4488-896e-7f96bd4fa48a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3108684050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3108684050
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3830887870
Short name T509
Test name
Test status
Simulation time 244152037293 ps
CPU time 332.15 seconds
Started Mar 17 02:03:58 PM PDT 24
Finished Mar 17 02:09:30 PM PDT 24
Peak memory 204928 kb
Host smart-d94d8e48-f896-4a4c-9727-5eeefc2397dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830887870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3830887870
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.287144493
Short name T185
Test name
Test status
Simulation time 34447367596 ps
CPU time 118.88 seconds
Started Mar 17 02:03:56 PM PDT 24
Finished Mar 17 02:05:55 PM PDT 24
Peak memory 205168 kb
Host smart-50e11e7b-fcf9-4398-be45-3ca1252fe2fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=287144493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.287144493
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.925779794
Short name T607
Test name
Test status
Simulation time 79797876 ps
CPU time 7.97 seconds
Started Mar 17 02:03:55 PM PDT 24
Finished Mar 17 02:04:04 PM PDT 24
Peak memory 211880 kb
Host smart-131c9e49-cbf3-4aef-aeb6-f261760d5da1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925779794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.925779794
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1826928943
Short name T306
Test name
Test status
Simulation time 315401016 ps
CPU time 17.74 seconds
Started Mar 17 02:04:03 PM PDT 24
Finished Mar 17 02:04:20 PM PDT 24
Peak memory 204440 kb
Host smart-bee1a691-81fb-4cc1-a55d-51f02e954517
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1826928943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1826928943
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.709557602
Short name T676
Test name
Test status
Simulation time 67660134 ps
CPU time 2.45 seconds
Started Mar 17 02:03:51 PM PDT 24
Finished Mar 17 02:03:54 PM PDT 24
Peak memory 203660 kb
Host smart-4230dbeb-a49a-4892-a524-88bafe65efc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=709557602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.709557602
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3992439129
Short name T451
Test name
Test status
Simulation time 4740129349 ps
CPU time 28.29 seconds
Started Mar 17 02:03:50 PM PDT 24
Finished Mar 17 02:04:19 PM PDT 24
Peak memory 203744 kb
Host smart-9aea4f9b-54c3-4622-832f-edf2c32c7e5f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992439129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3992439129
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.929468140
Short name T51
Test name
Test status
Simulation time 6582683483 ps
CPU time 24.84 seconds
Started Mar 17 02:03:56 PM PDT 24
Finished Mar 17 02:04:21 PM PDT 24
Peak memory 203752 kb
Host smart-419a4e2a-3742-4d7f-a592-fb065dab1c5a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=929468140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.929468140
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.4373351
Short name T465
Test name
Test status
Simulation time 31442039 ps
CPU time 2.18 seconds
Started Mar 17 02:03:51 PM PDT 24
Finished Mar 17 02:03:53 PM PDT 24
Peak memory 203704 kb
Host smart-3e9d2277-c31a-4353-b218-8f3c45c10c4c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4373351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.4373351
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2724857172
Short name T211
Test name
Test status
Simulation time 4002262881 ps
CPU time 151.05 seconds
Started Mar 17 02:04:03 PM PDT 24
Finished Mar 17 02:06:34 PM PDT 24
Peak memory 208740 kb
Host smart-18d0f095-0791-450a-9756-72faf4090beb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2724857172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2724857172
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2954232019
Short name T72
Test name
Test status
Simulation time 1309088976 ps
CPU time 256.84 seconds
Started Mar 17 02:04:05 PM PDT 24
Finished Mar 17 02:08:21 PM PDT 24
Peak memory 210344 kb
Host smart-c435cbf8-d4ef-4fd1-838c-3cc85231dc68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2954232019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.2954232019
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.734008272
Short name T653
Test name
Test status
Simulation time 2258345714 ps
CPU time 265.04 seconds
Started Mar 17 02:04:03 PM PDT 24
Finished Mar 17 02:08:28 PM PDT 24
Peak memory 210600 kb
Host smart-76f2d20b-538e-45e5-9be4-329697addcc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=734008272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res
et_error.734008272
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.487403037
Short name T555
Test name
Test status
Simulation time 861147266 ps
CPU time 31.79 seconds
Started Mar 17 02:04:02 PM PDT 24
Finished Mar 17 02:04:34 PM PDT 24
Peak memory 211944 kb
Host smart-27e3712b-8599-4809-a520-92da27c1fcdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=487403037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.487403037
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.4014279315
Short name T599
Test name
Test status
Simulation time 1754059562 ps
CPU time 24.46 seconds
Started Mar 17 02:04:15 PM PDT 24
Finished Mar 17 02:04:40 PM PDT 24
Peak memory 204812 kb
Host smart-7f12c89d-569c-4d34-8262-cc093897fbef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4014279315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.4014279315
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.4011749871
Short name T317
Test name
Test status
Simulation time 76012770061 ps
CPU time 372.52 seconds
Started Mar 17 02:04:17 PM PDT 24
Finished Mar 17 02:10:30 PM PDT 24
Peak memory 211932 kb
Host smart-49cf0c56-3515-46f4-a562-93ad1a0f98d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4011749871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.4011749871
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2129285880
Short name T204
Test name
Test status
Simulation time 70750803 ps
CPU time 6.19 seconds
Started Mar 17 02:04:16 PM PDT 24
Finished Mar 17 02:04:22 PM PDT 24
Peak memory 203884 kb
Host smart-60250548-230e-4b7a-af84-f96fdcb4272d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2129285880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2129285880
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.496069725
Short name T497
Test name
Test status
Simulation time 654995293 ps
CPU time 17.38 seconds
Started Mar 17 02:04:17 PM PDT 24
Finished Mar 17 02:04:34 PM PDT 24
Peak memory 203720 kb
Host smart-fb11d312-3cb9-4f63-b05a-5ab7824e9f72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=496069725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.496069725
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.1186453422
Short name T615
Test name
Test status
Simulation time 125047655 ps
CPU time 14.4 seconds
Started Mar 17 02:04:13 PM PDT 24
Finished Mar 17 02:04:27 PM PDT 24
Peak memory 204824 kb
Host smart-f7b931bf-70e1-4258-99b6-bdd874e295a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1186453422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1186453422
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2458212260
Short name T726
Test name
Test status
Simulation time 65023541311 ps
CPU time 199.59 seconds
Started Mar 17 02:04:14 PM PDT 24
Finished Mar 17 02:07:34 PM PDT 24
Peak memory 205072 kb
Host smart-ff4eb9a9-9bb2-4f97-a75d-f7d2d58dd527
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458212260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2458212260
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1643466801
Short name T99
Test name
Test status
Simulation time 3838661080 ps
CPU time 37.39 seconds
Started Mar 17 02:04:10 PM PDT 24
Finished Mar 17 02:04:48 PM PDT 24
Peak memory 203848 kb
Host smart-2f09a934-e7e9-4a7d-b9c7-299084d27854
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1643466801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1643466801
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1147212327
Short name T399
Test name
Test status
Simulation time 394438986 ps
CPU time 24.74 seconds
Started Mar 17 02:04:11 PM PDT 24
Finished Mar 17 02:04:36 PM PDT 24
Peak memory 205120 kb
Host smart-6e16f4ec-df33-403c-a365-cacff91ba296
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147212327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1147212327
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.1667288101
Short name T255
Test name
Test status
Simulation time 2296464405 ps
CPU time 13.35 seconds
Started Mar 17 02:04:18 PM PDT 24
Finished Mar 17 02:04:32 PM PDT 24
Peak memory 204304 kb
Host smart-1ab62b3d-a098-4e9c-8c93-d564cd29a650
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1667288101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1667288101
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.1588037271
Short name T158
Test name
Test status
Simulation time 53023391 ps
CPU time 2.45 seconds
Started Mar 17 02:04:05 PM PDT 24
Finished Mar 17 02:04:08 PM PDT 24
Peak memory 203696 kb
Host smart-0008ac40-8447-4ed8-bde9-35dccb4ac447
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1588037271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1588037271
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2398663791
Short name T367
Test name
Test status
Simulation time 8516395859 ps
CPU time 32.5 seconds
Started Mar 17 02:04:11 PM PDT 24
Finished Mar 17 02:04:43 PM PDT 24
Peak memory 203796 kb
Host smart-4b4d0c9f-29ac-4b36-9f29-252e09f32e63
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398663791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2398663791
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.965553412
Short name T832
Test name
Test status
Simulation time 4786364712 ps
CPU time 30.19 seconds
Started Mar 17 02:04:12 PM PDT 24
Finished Mar 17 02:04:42 PM PDT 24
Peak memory 203732 kb
Host smart-1f8097ed-37a7-4c22-b0ff-71dd12664546
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=965553412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.965553412
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1043014224
Short name T897
Test name
Test status
Simulation time 32145592 ps
CPU time 2.2 seconds
Started Mar 17 02:04:11 PM PDT 24
Finished Mar 17 02:04:13 PM PDT 24
Peak memory 203708 kb
Host smart-b6292774-a153-4b24-a108-5b1649658d89
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043014224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1043014224
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3545129955
Short name T768
Test name
Test status
Simulation time 3347999117 ps
CPU time 94.94 seconds
Started Mar 17 02:04:16 PM PDT 24
Finished Mar 17 02:05:51 PM PDT 24
Peak memory 206716 kb
Host smart-695df6ff-7fb5-428b-bf26-bfe36f0d8cdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3545129955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3545129955
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1416188781
Short name T810
Test name
Test status
Simulation time 2672170332 ps
CPU time 149.4 seconds
Started Mar 17 02:04:15 PM PDT 24
Finished Mar 17 02:06:45 PM PDT 24
Peak memory 205812 kb
Host smart-c32f2651-11a4-4f94-a0d8-299d207be452
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1416188781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1416188781
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2845172893
Short name T587
Test name
Test status
Simulation time 230521540 ps
CPU time 74.21 seconds
Started Mar 17 02:04:23 PM PDT 24
Finished Mar 17 02:05:37 PM PDT 24
Peak memory 208824 kb
Host smart-fe143966-f58a-452d-b005-9eabcdbcff3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2845172893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.2845172893
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1296395956
Short name T729
Test name
Test status
Simulation time 1149373011 ps
CPU time 16.17 seconds
Started Mar 17 02:04:18 PM PDT 24
Finished Mar 17 02:04:34 PM PDT 24
Peak memory 211884 kb
Host smart-882e9158-ddf4-47dd-a500-ab7fd3118817
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1296395956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1296395956
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.4206123410
Short name T215
Test name
Test status
Simulation time 930593716 ps
CPU time 40.18 seconds
Started Mar 17 02:04:31 PM PDT 24
Finished Mar 17 02:05:12 PM PDT 24
Peak memory 206296 kb
Host smart-13f39ea6-561d-4f01-bc19-e8d10424965d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4206123410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.4206123410
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2377865114
Short name T77
Test name
Test status
Simulation time 6993521786 ps
CPU time 39.35 seconds
Started Mar 17 02:04:31 PM PDT 24
Finished Mar 17 02:05:11 PM PDT 24
Peak memory 204328 kb
Host smart-f561e3f5-939e-4e61-aa05-87ae69584e84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2377865114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2377865114
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1758123789
Short name T395
Test name
Test status
Simulation time 624730499 ps
CPU time 25.27 seconds
Started Mar 17 02:04:38 PM PDT 24
Finished Mar 17 02:05:03 PM PDT 24
Peak memory 204032 kb
Host smart-0c1795cb-f4bb-43cc-b3cd-864cb0fbe1f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1758123789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1758123789
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.2218602351
Short name T430
Test name
Test status
Simulation time 246285014 ps
CPU time 16.2 seconds
Started Mar 17 02:04:31 PM PDT 24
Finished Mar 17 02:04:47 PM PDT 24
Peak memory 203700 kb
Host smart-51d7694c-72ec-420a-a0d4-8bfba8f21294
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2218602351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2218602351
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.3771095263
Short name T512
Test name
Test status
Simulation time 600649753 ps
CPU time 24.91 seconds
Started Mar 17 02:04:32 PM PDT 24
Finished Mar 17 02:04:57 PM PDT 24
Peak memory 205028 kb
Host smart-4162a0bd-4ce6-44f8-9d5c-cccdfb62b0e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3771095263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3771095263
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.838485529
Short name T692
Test name
Test status
Simulation time 26485129963 ps
CPU time 150.96 seconds
Started Mar 17 02:04:32 PM PDT 24
Finished Mar 17 02:07:03 PM PDT 24
Peak memory 205352 kb
Host smart-d9a8a58c-a887-4412-a468-09b9dba6ba65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=838485529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.838485529
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1767731276
Short name T53
Test name
Test status
Simulation time 3433098134 ps
CPU time 26.38 seconds
Started Mar 17 02:04:32 PM PDT 24
Finished Mar 17 02:04:59 PM PDT 24
Peak memory 204332 kb
Host smart-c81e49c5-da03-465c-8473-5d281e53208d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1767731276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1767731276
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.752591173
Short name T699
Test name
Test status
Simulation time 119652028 ps
CPU time 13.2 seconds
Started Mar 17 02:04:30 PM PDT 24
Finished Mar 17 02:04:44 PM PDT 24
Peak memory 211848 kb
Host smart-b403a932-1ae0-4ae0-b5bc-c265920ed6ba
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752591173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.752591173
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1248241443
Short name T545
Test name
Test status
Simulation time 205686142 ps
CPU time 5.16 seconds
Started Mar 17 02:04:33 PM PDT 24
Finished Mar 17 02:04:38 PM PDT 24
Peak memory 203676 kb
Host smart-2bcf57d6-16bf-4523-84b9-604ca518889e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1248241443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1248241443
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.2371107180
Short name T513
Test name
Test status
Simulation time 29554172 ps
CPU time 2.58 seconds
Started Mar 17 02:04:23 PM PDT 24
Finished Mar 17 02:04:26 PM PDT 24
Peak memory 203680 kb
Host smart-eb9f96f7-399b-4e83-b186-7b4b7ca81ef7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2371107180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2371107180
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2012408630
Short name T761
Test name
Test status
Simulation time 7563563973 ps
CPU time 36.93 seconds
Started Mar 17 02:04:22 PM PDT 24
Finished Mar 17 02:05:00 PM PDT 24
Peak memory 203736 kb
Host smart-cc0884dd-bb71-4aab-9bce-bb91ac051e3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012408630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2012408630
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3276114316
Short name T383
Test name
Test status
Simulation time 3951877434 ps
CPU time 21.58 seconds
Started Mar 17 02:04:22 PM PDT 24
Finished Mar 17 02:04:44 PM PDT 24
Peak memory 203696 kb
Host smart-10791e00-9a1d-4e01-a953-cfea5748557d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3276114316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3276114316
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4156432013
Short name T363
Test name
Test status
Simulation time 39636305 ps
CPU time 2.45 seconds
Started Mar 17 02:04:24 PM PDT 24
Finished Mar 17 02:04:27 PM PDT 24
Peak memory 203676 kb
Host smart-406e7bd5-8032-4c14-8b33-7e971dca8866
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156432013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4156432013
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1436656094
Short name T604
Test name
Test status
Simulation time 5659381706 ps
CPU time 179.82 seconds
Started Mar 17 02:04:39 PM PDT 24
Finished Mar 17 02:07:39 PM PDT 24
Peak memory 209172 kb
Host smart-c3947cf3-aafb-4f8e-b7f0-2c50a360d095
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1436656094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1436656094
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3156381907
Short name T116
Test name
Test status
Simulation time 2428332782 ps
CPU time 213.95 seconds
Started Mar 17 02:04:37 PM PDT 24
Finished Mar 17 02:08:11 PM PDT 24
Peak memory 208684 kb
Host smart-11eae7e8-2efa-45a7-a4ea-92c17a925044
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3156381907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.3156381907
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2088899481
Short name T21
Test name
Test status
Simulation time 397051696 ps
CPU time 84.52 seconds
Started Mar 17 02:04:38 PM PDT 24
Finished Mar 17 02:06:03 PM PDT 24
Peak memory 209220 kb
Host smart-3cd7971d-c344-42d4-9cfc-6fd0958a7642
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2088899481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.2088899481
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3850662474
Short name T701
Test name
Test status
Simulation time 42243587 ps
CPU time 8.98 seconds
Started Mar 17 02:04:32 PM PDT 24
Finished Mar 17 02:04:41 PM PDT 24
Peak memory 205300 kb
Host smart-848bba36-18a7-4525-896b-d55b89975ba8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3850662474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3850662474
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2830237920
Short name T718
Test name
Test status
Simulation time 800840738 ps
CPU time 31.56 seconds
Started Mar 17 02:04:44 PM PDT 24
Finished Mar 17 02:05:17 PM PDT 24
Peak memory 205188 kb
Host smart-5b8a1be7-bbc6-4f88-ace2-c328290f9bbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2830237920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2830237920
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3608939613
Short name T763
Test name
Test status
Simulation time 165398198217 ps
CPU time 706.02 seconds
Started Mar 17 02:04:52 PM PDT 24
Finished Mar 17 02:16:39 PM PDT 24
Peak memory 207648 kb
Host smart-2790019c-f574-4b9d-bc62-03e7f006bdba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3608939613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.3608939613
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3884235633
Short name T608
Test name
Test status
Simulation time 565781922 ps
CPU time 12.59 seconds
Started Mar 17 02:04:50 PM PDT 24
Finished Mar 17 02:05:03 PM PDT 24
Peak memory 203728 kb
Host smart-fa865129-9b79-42f1-857d-8f3dd492461b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3884235633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3884235633
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.3127255964
Short name T548
Test name
Test status
Simulation time 1474944250 ps
CPU time 15.82 seconds
Started Mar 17 02:04:51 PM PDT 24
Finished Mar 17 02:05:09 PM PDT 24
Peak memory 203616 kb
Host smart-d0e7ea96-4249-4131-94ba-5c1f9c649d9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3127255964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3127255964
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.1983865357
Short name T647
Test name
Test status
Simulation time 2224704175 ps
CPU time 43.19 seconds
Started Mar 17 02:04:42 PM PDT 24
Finished Mar 17 02:05:29 PM PDT 24
Peak memory 211936 kb
Host smart-63204f43-2a00-470f-b296-7416502b7f7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1983865357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1983865357
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.295374231
Short name T394
Test name
Test status
Simulation time 14979807138 ps
CPU time 34.7 seconds
Started Mar 17 02:04:43 PM PDT 24
Finished Mar 17 02:05:21 PM PDT 24
Peak memory 204864 kb
Host smart-2155f161-0d1a-48e4-bdd3-764287237d28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=295374231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.295374231
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3247998295
Short name T593
Test name
Test status
Simulation time 42910205588 ps
CPU time 247.11 seconds
Started Mar 17 02:04:43 PM PDT 24
Finished Mar 17 02:08:53 PM PDT 24
Peak memory 205080 kb
Host smart-4738d202-1caf-4998-af2d-d44babb87220
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3247998295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3247998295
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.4116637492
Short name T251
Test name
Test status
Simulation time 179583454 ps
CPU time 22 seconds
Started Mar 17 02:04:43 PM PDT 24
Finished Mar 17 02:05:08 PM PDT 24
Peak memory 205332 kb
Host smart-0776890e-4c6e-4e2f-95b3-b7d762dbf94c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116637492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.4116637492
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.1642159542
Short name T767
Test name
Test status
Simulation time 670818352 ps
CPU time 12.27 seconds
Started Mar 17 02:04:51 PM PDT 24
Finished Mar 17 02:05:05 PM PDT 24
Peak memory 204176 kb
Host smart-9ad932df-a739-49cc-ba5d-9f58c2b3f2b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1642159542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1642159542
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.485674747
Short name T401
Test name
Test status
Simulation time 219376612 ps
CPU time 3.53 seconds
Started Mar 17 02:04:38 PM PDT 24
Finished Mar 17 02:04:42 PM PDT 24
Peak memory 203712 kb
Host smart-80115220-59c9-48df-9465-2fdab5d9db5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485674747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.485674747
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.569693931
Short name T724
Test name
Test status
Simulation time 8089638440 ps
CPU time 28.17 seconds
Started Mar 17 02:04:42 PM PDT 24
Finished Mar 17 02:05:14 PM PDT 24
Peak memory 203816 kb
Host smart-d9634c9d-e4aa-4b36-8e06-466620adfa3e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=569693931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.569693931
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1509607194
Short name T46
Test name
Test status
Simulation time 2716370051 ps
CPU time 24.69 seconds
Started Mar 17 02:04:43 PM PDT 24
Finished Mar 17 02:05:11 PM PDT 24
Peak memory 203760 kb
Host smart-278dcc54-b953-4e86-96d0-3ab0fc95c16e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1509607194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1509607194
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3665578879
Short name T760
Test name
Test status
Simulation time 62464337 ps
CPU time 2.54 seconds
Started Mar 17 02:04:36 PM PDT 24
Finished Mar 17 02:04:39 PM PDT 24
Peak memory 203732 kb
Host smart-49b64a03-bedd-467f-9ed4-d3e2b72046f0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665578879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3665578879
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.66259238
Short name T566
Test name
Test status
Simulation time 648605592 ps
CPU time 74.02 seconds
Started Mar 17 02:04:50 PM PDT 24
Finished Mar 17 02:06:05 PM PDT 24
Peak memory 206980 kb
Host smart-ad288c9d-4737-4996-81c2-f22a507616b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66259238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.66259238
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1865422018
Short name T595
Test name
Test status
Simulation time 9290364614 ps
CPU time 109.87 seconds
Started Mar 17 02:04:54 PM PDT 24
Finished Mar 17 02:06:44 PM PDT 24
Peak memory 208448 kb
Host smart-2f8c8dea-b205-4dcf-b5fa-b37c9cdf7224
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1865422018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1865422018
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1345821513
Short name T654
Test name
Test status
Simulation time 9841735641 ps
CPU time 392.66 seconds
Started Mar 17 02:04:55 PM PDT 24
Finished Mar 17 02:11:28 PM PDT 24
Peak memory 220152 kb
Host smart-4ff0a1a3-b0d3-4c67-82d7-bd56605969cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1345821513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.1345821513
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1374541303
Short name T76
Test name
Test status
Simulation time 706592764 ps
CPU time 35.65 seconds
Started Mar 17 02:04:51 PM PDT 24
Finished Mar 17 02:05:27 PM PDT 24
Peak memory 205240 kb
Host smart-c2597cae-9a2e-48f4-b353-e83907a373c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1374541303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1374541303
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3637763123
Short name T134
Test name
Test status
Simulation time 306322773 ps
CPU time 36 seconds
Started Mar 17 02:04:58 PM PDT 24
Finished Mar 17 02:05:34 PM PDT 24
Peak memory 211956 kb
Host smart-30ef030b-ba0f-43a4-a8dc-ca6e697baa3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3637763123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3637763123
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1685643117
Short name T427
Test name
Test status
Simulation time 86463874663 ps
CPU time 602.85 seconds
Started Mar 17 02:05:00 PM PDT 24
Finished Mar 17 02:15:03 PM PDT 24
Peak memory 207588 kb
Host smart-b4a5235a-0872-4ead-ae08-62fef2c1ad52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1685643117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.1685643117
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.4042476040
Short name T775
Test name
Test status
Simulation time 63165326 ps
CPU time 8.01 seconds
Started Mar 17 02:05:06 PM PDT 24
Finished Mar 17 02:05:14 PM PDT 24
Peak memory 203908 kb
Host smart-cc67a688-844e-4e26-869b-b2a4be3abfd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4042476040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.4042476040
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.1205961534
Short name T820
Test name
Test status
Simulation time 315206764 ps
CPU time 23.85 seconds
Started Mar 17 02:05:05 PM PDT 24
Finished Mar 17 02:05:29 PM PDT 24
Peak memory 203660 kb
Host smart-73e6758f-3e4c-4e7f-ad76-5c395dd6241c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1205961534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1205961534
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.3900445534
Short name T405
Test name
Test status
Simulation time 3661747714 ps
CPU time 36.87 seconds
Started Mar 17 02:04:54 PM PDT 24
Finished Mar 17 02:05:31 PM PDT 24
Peak memory 205000 kb
Host smart-ae29b87b-e20f-41eb-81cb-48a37947f5d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3900445534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3900445534
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.727292210
Short name T423
Test name
Test status
Simulation time 39265662426 ps
CPU time 220.78 seconds
Started Mar 17 02:05:00 PM PDT 24
Finished Mar 17 02:08:41 PM PDT 24
Peak memory 205584 kb
Host smart-5bf189b2-e20b-4c15-aa63-700f0bbcf68b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=727292210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.727292210
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3140231821
Short name T380
Test name
Test status
Simulation time 5097759467 ps
CPU time 34.17 seconds
Started Mar 17 02:04:59 PM PDT 24
Finished Mar 17 02:05:33 PM PDT 24
Peak memory 204860 kb
Host smart-e6afb278-4d2a-44ba-8001-8beccf343523
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3140231821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3140231821
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3832499716
Short name T171
Test name
Test status
Simulation time 291204057 ps
CPU time 23.49 seconds
Started Mar 17 02:04:54 PM PDT 24
Finished Mar 17 02:05:18 PM PDT 24
Peak memory 205064 kb
Host smart-ec5d36bd-7ee4-4d12-bacf-d59191b11b61
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832499716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3832499716
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.529652002
Short name T349
Test name
Test status
Simulation time 851313711 ps
CPU time 10.9 seconds
Started Mar 17 02:05:01 PM PDT 24
Finished Mar 17 02:05:13 PM PDT 24
Peak memory 203712 kb
Host smart-62ddb27c-bdc1-44c4-aa23-c9497bf1b270
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=529652002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.529652002
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.3868709702
Short name T130
Test name
Test status
Simulation time 129968608 ps
CPU time 3.72 seconds
Started Mar 17 02:04:54 PM PDT 24
Finished Mar 17 02:04:58 PM PDT 24
Peak memory 203700 kb
Host smart-5799a35d-b841-443f-90a9-4ae6d86c171f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3868709702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3868709702
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3885365217
Short name T648
Test name
Test status
Simulation time 7269793222 ps
CPU time 30.92 seconds
Started Mar 17 02:04:58 PM PDT 24
Finished Mar 17 02:05:29 PM PDT 24
Peak memory 203732 kb
Host smart-fdf97a13-f47f-4081-b738-cd17e7674bf8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885365217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3885365217
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1107051897
Short name T59
Test name
Test status
Simulation time 12490701758 ps
CPU time 33.6 seconds
Started Mar 17 02:04:54 PM PDT 24
Finished Mar 17 02:05:28 PM PDT 24
Peak memory 203756 kb
Host smart-22cd7cc5-200c-4a56-8f51-5352a397d9cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1107051897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1107051897
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.44421288
Short name T280
Test name
Test status
Simulation time 34015257 ps
CPU time 2.17 seconds
Started Mar 17 02:04:54 PM PDT 24
Finished Mar 17 02:04:57 PM PDT 24
Peak memory 203648 kb
Host smart-18e2fa0f-40a6-4f56-9bc9-738171b7921c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44421288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.44421288
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3994197140
Short name T556
Test name
Test status
Simulation time 3522395674 ps
CPU time 132.48 seconds
Started Mar 17 02:05:06 PM PDT 24
Finished Mar 17 02:07:19 PM PDT 24
Peak memory 209140 kb
Host smart-533eabd1-6e8f-4f30-8820-6d5447df4d83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3994197140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3994197140
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2846613068
Short name T575
Test name
Test status
Simulation time 4603967010 ps
CPU time 150.12 seconds
Started Mar 17 02:05:08 PM PDT 24
Finished Mar 17 02:07:38 PM PDT 24
Peak memory 208972 kb
Host smart-27d8f297-71d5-418d-ba5c-2a94927d64be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2846613068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2846613068
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4119897932
Short name T771
Test name
Test status
Simulation time 663666898 ps
CPU time 267.35 seconds
Started Mar 17 02:05:06 PM PDT 24
Finished Mar 17 02:09:34 PM PDT 24
Peak memory 209032 kb
Host smart-dd1071e4-d516-4bbf-9483-346305d9fc1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4119897932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.4119897932
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3445264856
Short name T23
Test name
Test status
Simulation time 1288639538 ps
CPU time 226.42 seconds
Started Mar 17 02:05:11 PM PDT 24
Finished Mar 17 02:08:59 PM PDT 24
Peak memory 211892 kb
Host smart-2bbdee44-2943-42db-abe5-793d755d7ec3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3445264856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.3445264856
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.4189143871
Short name T144
Test name
Test status
Simulation time 208548578 ps
CPU time 7.91 seconds
Started Mar 17 02:05:07 PM PDT 24
Finished Mar 17 02:05:15 PM PDT 24
Peak memory 205100 kb
Host smart-2e251c07-63b1-4692-8f02-737835035d13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4189143871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4189143871
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1476065715
Short name T596
Test name
Test status
Simulation time 1217527508 ps
CPU time 45.47 seconds
Started Mar 17 02:05:18 PM PDT 24
Finished Mar 17 02:06:03 PM PDT 24
Peak memory 205008 kb
Host smart-a6362f5a-de54-4fd6-ae56-b0e4faaaab36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1476065715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1476065715
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2726972980
Short name T333
Test name
Test status
Simulation time 50814265144 ps
CPU time 448.51 seconds
Started Mar 17 02:05:19 PM PDT 24
Finished Mar 17 02:12:47 PM PDT 24
Peak memory 211992 kb
Host smart-8eed1316-aba7-4b4f-8750-bcac9346d492
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2726972980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.2726972980
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.602433896
Short name T603
Test name
Test status
Simulation time 544005557 ps
CPU time 20.6 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:05:44 PM PDT 24
Peak memory 203700 kb
Host smart-fb9da2d8-88bc-47a2-abd2-cf4f600f837a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=602433896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.602433896
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.51584155
Short name T359
Test name
Test status
Simulation time 162703494 ps
CPU time 25.76 seconds
Started Mar 17 02:05:24 PM PDT 24
Finished Mar 17 02:05:50 PM PDT 24
Peak memory 203916 kb
Host smart-99c2e1ec-db79-41ce-92ad-04cb57b2efed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51584155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.51584155
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.1709060194
Short name T340
Test name
Test status
Simulation time 187485799 ps
CPU time 6.7 seconds
Started Mar 17 02:05:10 PM PDT 24
Finished Mar 17 02:05:19 PM PDT 24
Peak memory 204332 kb
Host smart-1bf41d74-54ae-4a32-8078-7da694dc8b92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1709060194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1709060194
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.4214439717
Short name T714
Test name
Test status
Simulation time 151085426829 ps
CPU time 249.67 seconds
Started Mar 17 02:05:19 PM PDT 24
Finished Mar 17 02:09:29 PM PDT 24
Peak memory 205032 kb
Host smart-1e56ad02-b7aa-4d5d-84c9-e7206f4cfffc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214439717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4214439717
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2035615230
Short name T102
Test name
Test status
Simulation time 31232588823 ps
CPU time 176.36 seconds
Started Mar 17 02:05:22 PM PDT 24
Finished Mar 17 02:08:18 PM PDT 24
Peak memory 205344 kb
Host smart-6d82e72e-3b31-459e-b562-5a2e61467aa1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2035615230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2035615230
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.148203322
Short name T864
Test name
Test status
Simulation time 162338112 ps
CPU time 24.3 seconds
Started Mar 17 02:05:20 PM PDT 24
Finished Mar 17 02:05:44 PM PDT 24
Peak memory 204856 kb
Host smart-4ae124e5-7655-40f8-a832-07315ea43897
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148203322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.148203322
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.3923792559
Short name T783
Test name
Test status
Simulation time 217779640 ps
CPU time 13.98 seconds
Started Mar 17 02:05:24 PM PDT 24
Finished Mar 17 02:05:38 PM PDT 24
Peak memory 204132 kb
Host smart-a9798e81-b2e2-4efb-a17e-600383a7649f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3923792559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3923792559
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.3196422518
Short name T875
Test name
Test status
Simulation time 407280789 ps
CPU time 4.6 seconds
Started Mar 17 02:05:11 PM PDT 24
Finished Mar 17 02:05:17 PM PDT 24
Peak memory 203692 kb
Host smart-38f37a59-8640-4d32-87b4-324687a22351
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3196422518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3196422518
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2504538439
Short name T515
Test name
Test status
Simulation time 7059610264 ps
CPU time 35.04 seconds
Started Mar 17 02:05:12 PM PDT 24
Finished Mar 17 02:05:48 PM PDT 24
Peak memory 203752 kb
Host smart-8b1bc825-6be6-4afe-bfaa-5675e5472ee5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504538439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2504538439
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3735720308
Short name T822
Test name
Test status
Simulation time 5113293567 ps
CPU time 30.44 seconds
Started Mar 17 02:05:12 PM PDT 24
Finished Mar 17 02:05:44 PM PDT 24
Peak memory 203732 kb
Host smart-2042eb66-0806-4037-befc-2b31be5151a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3735720308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3735720308
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1077491066
Short name T35
Test name
Test status
Simulation time 29963273 ps
CPU time 2.67 seconds
Started Mar 17 02:05:12 PM PDT 24
Finished Mar 17 02:05:17 PM PDT 24
Peak memory 203688 kb
Host smart-a609b524-fa0c-4616-8eb2-a218e47cb0c8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077491066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1077491066
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2255908655
Short name T402
Test name
Test status
Simulation time 1291274702 ps
CPU time 114.51 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:07:17 PM PDT 24
Peak memory 208712 kb
Host smart-d910df4b-5986-4588-ada4-7dbb57b25530
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2255908655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2255908655
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2351116286
Short name T601
Test name
Test status
Simulation time 10135569166 ps
CPU time 239.73 seconds
Started Mar 17 02:05:22 PM PDT 24
Finished Mar 17 02:09:22 PM PDT 24
Peak memory 207052 kb
Host smart-0433e735-91f9-4a8b-b8e5-c1cbc7611a72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2351116286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2351116286
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.93312189
Short name T150
Test name
Test status
Simulation time 2164076928 ps
CPU time 313.16 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:10:36 PM PDT 24
Peak memory 209868 kb
Host smart-e040f5a4-8610-40be-86c1-e7ac70a6c296
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93312189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_
reset.93312189
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.4115683474
Short name T276
Test name
Test status
Simulation time 206655326 ps
CPU time 62.53 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:06:25 PM PDT 24
Peak memory 208204 kb
Host smart-c3575ec0-8935-4054-ac06-3eae44408fa6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115683474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.4115683474
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3451509935
Short name T342
Test name
Test status
Simulation time 39537983 ps
CPU time 6.35 seconds
Started Mar 17 02:05:24 PM PDT 24
Finished Mar 17 02:05:31 PM PDT 24
Peak memory 211792 kb
Host smart-356224a8-b1c0-4b0d-ba5b-54e68955c11b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3451509935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3451509935
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3541603076
Short name T424
Test name
Test status
Simulation time 404067290 ps
CPU time 23.84 seconds
Started Mar 17 02:05:36 PM PDT 24
Finished Mar 17 02:06:01 PM PDT 24
Peak memory 211912 kb
Host smart-835f5db5-a4cf-465d-8101-ab091df33321
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3541603076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3541603076
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1607875679
Short name T854
Test name
Test status
Simulation time 62120058782 ps
CPU time 500.95 seconds
Started Mar 17 02:05:34 PM PDT 24
Finished Mar 17 02:13:55 PM PDT 24
Peak memory 207196 kb
Host smart-7087f696-3be3-4b94-b2c5-2e70986ee466
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1607875679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.1607875679
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.740850515
Short name T165
Test name
Test status
Simulation time 396323485 ps
CPU time 12.98 seconds
Started Mar 17 02:05:35 PM PDT 24
Finished Mar 17 02:05:48 PM PDT 24
Peak memory 203636 kb
Host smart-f597adb7-33be-4a72-a3ce-c0c69468b08f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=740850515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.740850515
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.3945528919
Short name T323
Test name
Test status
Simulation time 41218430 ps
CPU time 3.73 seconds
Started Mar 17 02:05:36 PM PDT 24
Finished Mar 17 02:05:40 PM PDT 24
Peak memory 203716 kb
Host smart-9adf6063-779b-479a-9ee7-f34f557243ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3945528919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3945528919
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.1220164992
Short name T770
Test name
Test status
Simulation time 41082122 ps
CPU time 5.21 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:05:28 PM PDT 24
Peak memory 204788 kb
Host smart-edd6f0de-3d05-4c7a-8ab2-f7b2f7c20469
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1220164992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1220164992
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1935219555
Short name T163
Test name
Test status
Simulation time 85519567210 ps
CPU time 243.8 seconds
Started Mar 17 02:05:30 PM PDT 24
Finished Mar 17 02:09:34 PM PDT 24
Peak memory 205372 kb
Host smart-1c2bb5d1-c592-4ade-a1fe-d47fe484b767
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935219555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1935219555
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3859899496
Short name T303
Test name
Test status
Simulation time 12681586328 ps
CPU time 81.96 seconds
Started Mar 17 02:05:29 PM PDT 24
Finished Mar 17 02:06:51 PM PDT 24
Peak memory 205184 kb
Host smart-27dbf02e-d6b2-478b-93de-e64b3f6065b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3859899496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3859899496
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1029388843
Short name T794
Test name
Test status
Simulation time 445153138 ps
CPU time 18.87 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:05:42 PM PDT 24
Peak memory 211900 kb
Host smart-cc4e1b13-6e9c-4306-8d5f-afb2c8c79f51
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029388843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1029388843
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.2852183124
Short name T870
Test name
Test status
Simulation time 10024051039 ps
CPU time 38.38 seconds
Started Mar 17 02:05:35 PM PDT 24
Finished Mar 17 02:06:15 PM PDT 24
Peak memory 204792 kb
Host smart-40ead70d-78ab-43c1-86e6-192d0cac85a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2852183124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2852183124
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.392131330
Short name T658
Test name
Test status
Simulation time 96279944 ps
CPU time 2.23 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:05:26 PM PDT 24
Peak memory 203712 kb
Host smart-072e9f07-2626-4fa7-926f-f1c8acc69239
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=392131330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.392131330
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3109571798
Short name T330
Test name
Test status
Simulation time 10654463168 ps
CPU time 33.75 seconds
Started Mar 17 02:05:23 PM PDT 24
Finished Mar 17 02:05:58 PM PDT 24
Peak memory 203820 kb
Host smart-c790cac7-696c-41ad-93b7-dc2acf479426
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109571798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3109571798
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4056813548
Short name T477
Test name
Test status
Simulation time 3378981757 ps
CPU time 24.47 seconds
Started Mar 17 02:05:24 PM PDT 24
Finished Mar 17 02:05:49 PM PDT 24
Peak memory 203780 kb
Host smart-109a43f3-bdc1-485f-92fc-e5406ff0ea57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4056813548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4056813548
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3357578771
Short name T268
Test name
Test status
Simulation time 60702784 ps
CPU time 2.43 seconds
Started Mar 17 02:05:27 PM PDT 24
Finished Mar 17 02:05:30 PM PDT 24
Peak memory 203704 kb
Host smart-c5f921a5-55a3-478d-8810-00140b54fd4a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357578771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3357578771
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1543266062
Short name T58
Test name
Test status
Simulation time 4509749319 ps
CPU time 106.16 seconds
Started Mar 17 02:05:35 PM PDT 24
Finished Mar 17 02:07:21 PM PDT 24
Peak memory 206512 kb
Host smart-4c56716e-5eeb-4914-b2d5-4cb144c43cee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1543266062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1543266062
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3956017625
Short name T730
Test name
Test status
Simulation time 21127422584 ps
CPU time 150.26 seconds
Started Mar 17 02:05:41 PM PDT 24
Finished Mar 17 02:08:11 PM PDT 24
Peak memory 206180 kb
Host smart-e19766ef-8fc9-478b-938a-af7ecffa8764
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3956017625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3956017625
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.4214910082
Short name T175
Test name
Test status
Simulation time 752433654 ps
CPU time 293.84 seconds
Started Mar 17 02:05:34 PM PDT 24
Finished Mar 17 02:10:28 PM PDT 24
Peak memory 209012 kb
Host smart-e0c03c19-c43f-480e-bae7-8a278347e685
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4214910082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.4214910082
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3371673950
Short name T481
Test name
Test status
Simulation time 12352861869 ps
CPU time 202.54 seconds
Started Mar 17 02:05:41 PM PDT 24
Finished Mar 17 02:09:04 PM PDT 24
Peak memory 211980 kb
Host smart-cc0271ac-3ef7-4aab-b9aa-4e8647d17206
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3371673950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.3371673950
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1533724361
Short name T846
Test name
Test status
Simulation time 694779642 ps
CPU time 29.91 seconds
Started Mar 17 02:05:37 PM PDT 24
Finished Mar 17 02:06:07 PM PDT 24
Peak memory 205372 kb
Host smart-8753e26e-b83f-494c-ab75-9609f5180bf6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1533724361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1533724361
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1168187576
Short name T417
Test name
Test status
Simulation time 659685301 ps
CPU time 24.65 seconds
Started Mar 17 02:05:46 PM PDT 24
Finished Mar 17 02:06:10 PM PDT 24
Peak memory 205420 kb
Host smart-331817d2-7024-4536-8660-62f01d115de8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1168187576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1168187576
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1931559221
Short name T484
Test name
Test status
Simulation time 118456355408 ps
CPU time 671.67 seconds
Started Mar 17 02:05:53 PM PDT 24
Finished Mar 17 02:17:05 PM PDT 24
Peak memory 206308 kb
Host smart-2dc60f49-24ff-4481-ae9c-ae0ca7c37977
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1931559221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.1931559221
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2069766066
Short name T725
Test name
Test status
Simulation time 168291942 ps
CPU time 13.66 seconds
Started Mar 17 02:05:52 PM PDT 24
Finished Mar 17 02:06:06 PM PDT 24
Peak memory 203992 kb
Host smart-10406e2a-5262-42c4-a70a-8c46b8f4541d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2069766066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2069766066
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.3567670211
Short name T283
Test name
Test status
Simulation time 375954479 ps
CPU time 24.62 seconds
Started Mar 17 02:05:53 PM PDT 24
Finished Mar 17 02:06:18 PM PDT 24
Peak memory 203708 kb
Host smart-4d72b922-42bb-43d7-b47c-efd1f87aed51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3567670211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3567670211
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.2632395679
Short name T140
Test name
Test status
Simulation time 983520330 ps
CPU time 31.81 seconds
Started Mar 17 02:05:47 PM PDT 24
Finished Mar 17 02:06:19 PM PDT 24
Peak memory 211928 kb
Host smart-17c935fc-f57a-452b-82f2-8f5dcd96744c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2632395679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2632395679
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2500904072
Short name T479
Test name
Test status
Simulation time 31393419862 ps
CPU time 133.65 seconds
Started Mar 17 02:05:46 PM PDT 24
Finished Mar 17 02:08:00 PM PDT 24
Peak memory 205296 kb
Host smart-dd0d4d43-b0f8-4149-b459-80cf37d1e406
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500904072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2500904072
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2019100496
Short name T142
Test name
Test status
Simulation time 69300410689 ps
CPU time 189.73 seconds
Started Mar 17 02:05:46 PM PDT 24
Finished Mar 17 02:08:56 PM PDT 24
Peak memory 205248 kb
Host smart-670579ba-a87d-40ce-af0d-627bc3a374bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2019100496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2019100496
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.976818776
Short name T13
Test name
Test status
Simulation time 43386187 ps
CPU time 5.39 seconds
Started Mar 17 02:05:47 PM PDT 24
Finished Mar 17 02:05:53 PM PDT 24
Peak memory 211924 kb
Host smart-5c0ea988-c9a0-437a-9df4-42d3722e888c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976818776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.976818776
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.194065118
Short name T266
Test name
Test status
Simulation time 2208514352 ps
CPU time 19.04 seconds
Started Mar 17 02:05:52 PM PDT 24
Finished Mar 17 02:06:11 PM PDT 24
Peak memory 204224 kb
Host smart-40fa82c9-a92a-408a-aadc-b5134f632017
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=194065118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.194065118
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2315248247
Short name T553
Test name
Test status
Simulation time 362786896 ps
CPU time 3.34 seconds
Started Mar 17 02:05:42 PM PDT 24
Finished Mar 17 02:05:46 PM PDT 24
Peak memory 203672 kb
Host smart-a1db99fa-24bf-4fc5-95fe-72bfa9d122f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2315248247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2315248247
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3788689367
Short name T893
Test name
Test status
Simulation time 15695347917 ps
CPU time 35.95 seconds
Started Mar 17 02:05:47 PM PDT 24
Finished Mar 17 02:06:23 PM PDT 24
Peak memory 203728 kb
Host smart-c04eca6b-46c9-4028-9879-380ef561f465
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788689367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3788689367
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.877050687
Short name T791
Test name
Test status
Simulation time 4260030417 ps
CPU time 29.58 seconds
Started Mar 17 02:05:46 PM PDT 24
Finished Mar 17 02:06:15 PM PDT 24
Peak memory 203752 kb
Host smart-22a4e5be-711e-42d2-a3e1-88428f96290b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=877050687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.877050687
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.4254484016
Short name T409
Test name
Test status
Simulation time 50416998 ps
CPU time 2.23 seconds
Started Mar 17 02:05:41 PM PDT 24
Finished Mar 17 02:05:43 PM PDT 24
Peak memory 203708 kb
Host smart-bb1f43a5-8109-4e8c-8e94-8277530c8f20
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254484016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.4254484016
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1576732981
Short name T126
Test name
Test status
Simulation time 2996304229 ps
CPU time 130.49 seconds
Started Mar 17 02:05:52 PM PDT 24
Finished Mar 17 02:08:02 PM PDT 24
Peak memory 209108 kb
Host smart-2a518bd3-036a-468c-9ddc-28ff1ab786b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1576732981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1576732981
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1162002839
Short name T797
Test name
Test status
Simulation time 3230767356 ps
CPU time 111.68 seconds
Started Mar 17 02:05:52 PM PDT 24
Finished Mar 17 02:07:44 PM PDT 24
Peak memory 206960 kb
Host smart-f5d4b23e-54c8-4689-adb2-93e3370c1e1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1162002839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1162002839
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1648521510
Short name T447
Test name
Test status
Simulation time 5398077297 ps
CPU time 304.89 seconds
Started Mar 17 02:05:52 PM PDT 24
Finished Mar 17 02:10:57 PM PDT 24
Peak memory 210556 kb
Host smart-b898ac32-e5e3-43fe-b36a-ce9391873147
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1648521510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.1648521510
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3412496945
Short name T495
Test name
Test status
Simulation time 1252460782 ps
CPU time 211.87 seconds
Started Mar 17 02:05:57 PM PDT 24
Finished Mar 17 02:09:29 PM PDT 24
Peak memory 211916 kb
Host smart-8d433754-ffde-418a-b804-56ef884ce28c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3412496945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.3412496945
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.970949011
Short name T390
Test name
Test status
Simulation time 376795031 ps
CPU time 12.76 seconds
Started Mar 17 02:05:52 PM PDT 24
Finished Mar 17 02:06:05 PM PDT 24
Peak memory 204916 kb
Host smart-4621f1c4-69e6-468a-bee0-85515644ddf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=970949011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.970949011
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2206750519
Short name T436
Test name
Test status
Simulation time 1902357283 ps
CPU time 49.48 seconds
Started Mar 17 02:01:42 PM PDT 24
Finished Mar 17 02:02:31 PM PDT 24
Peak memory 205452 kb
Host smart-c8ec5d3c-3dbf-4db8-af90-3c1601c733d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2206750519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2206750519
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1463573441
Short name T396
Test name
Test status
Simulation time 48154090015 ps
CPU time 154.38 seconds
Started Mar 17 02:01:43 PM PDT 24
Finished Mar 17 02:04:17 PM PDT 24
Peak memory 211904 kb
Host smart-c7bd8b42-90ff-40e3-b6a2-404d14dbb929
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1463573441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.1463573441
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1788485513
Short name T526
Test name
Test status
Simulation time 1919541144 ps
CPU time 19.53 seconds
Started Mar 17 02:01:44 PM PDT 24
Finished Mar 17 02:02:04 PM PDT 24
Peak memory 204064 kb
Host smart-ce3fbe21-08af-4d75-8770-a98fdf8784cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1788485513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1788485513
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.3883760376
Short name T899
Test name
Test status
Simulation time 1490399192 ps
CPU time 36.52 seconds
Started Mar 17 02:01:42 PM PDT 24
Finished Mar 17 02:02:19 PM PDT 24
Peak memory 203804 kb
Host smart-c1b80027-4d01-411b-88e0-624a92ee3a66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3883760376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3883760376
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.2935211047
Short name T207
Test name
Test status
Simulation time 86160750 ps
CPU time 4.95 seconds
Started Mar 17 02:01:35 PM PDT 24
Finished Mar 17 02:01:40 PM PDT 24
Peak memory 204392 kb
Host smart-c6e3fd1b-d207-4e17-b56d-c89866cd1465
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2935211047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2935211047
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.4273015709
Short name T883
Test name
Test status
Simulation time 42003488341 ps
CPU time 227.55 seconds
Started Mar 17 02:01:43 PM PDT 24
Finished Mar 17 02:05:31 PM PDT 24
Peak memory 205068 kb
Host smart-ee096310-88bc-4134-8aaf-f9725e0d3b75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273015709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4273015709
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1760411416
Short name T345
Test name
Test status
Simulation time 25866599648 ps
CPU time 94.66 seconds
Started Mar 17 02:01:41 PM PDT 24
Finished Mar 17 02:03:15 PM PDT 24
Peak memory 205232 kb
Host smart-f4d7b481-f63f-4f4b-9707-a191804fae80
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1760411416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1760411416
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2878234530
Short name T813
Test name
Test status
Simulation time 32546415 ps
CPU time 3.77 seconds
Started Mar 17 02:01:36 PM PDT 24
Finished Mar 17 02:01:40 PM PDT 24
Peak memory 204340 kb
Host smart-6bfbf238-c0a7-48f4-abd0-220602dec826
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878234530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2878234530
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.53983907
Short name T476
Test name
Test status
Simulation time 181366278 ps
CPU time 5.53 seconds
Started Mar 17 02:01:41 PM PDT 24
Finished Mar 17 02:01:47 PM PDT 24
Peak memory 204000 kb
Host smart-48f27c00-b539-4d31-968d-0060b08d5fdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53983907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.53983907
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.3393415231
Short name T678
Test name
Test status
Simulation time 217967055 ps
CPU time 3.72 seconds
Started Mar 17 02:01:36 PM PDT 24
Finished Mar 17 02:01:40 PM PDT 24
Peak memory 203664 kb
Host smart-f592c538-3310-4655-a922-f2d0a4ab86c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3393415231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3393415231
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3566338403
Short name T572
Test name
Test status
Simulation time 28220667274 ps
CPU time 48.93 seconds
Started Mar 17 02:01:34 PM PDT 24
Finished Mar 17 02:02:23 PM PDT 24
Peak memory 203752 kb
Host smart-2e00153a-8cb4-4647-bbd5-1f32102e6024
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566338403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3566338403
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1317941088
Short name T655
Test name
Test status
Simulation time 11766414266 ps
CPU time 42.35 seconds
Started Mar 17 02:01:35 PM PDT 24
Finished Mar 17 02:02:17 PM PDT 24
Peak memory 203816 kb
Host smart-6d47a09b-58eb-4f6a-93e4-7d7bc8845e05
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1317941088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1317941088
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2665441723
Short name T160
Test name
Test status
Simulation time 26107826 ps
CPU time 2.39 seconds
Started Mar 17 02:01:34 PM PDT 24
Finished Mar 17 02:01:36 PM PDT 24
Peak memory 203632 kb
Host smart-1742a43b-943f-43e4-bea6-30f19670cfa6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665441723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2665441723
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2609571493
Short name T793
Test name
Test status
Simulation time 2975499542 ps
CPU time 83.32 seconds
Started Mar 17 02:01:43 PM PDT 24
Finished Mar 17 02:03:06 PM PDT 24
Peak memory 207196 kb
Host smart-7b07f721-1fae-40cd-b77a-a8b03a44bb6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2609571493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2609571493
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2388178794
Short name T250
Test name
Test status
Simulation time 550820650 ps
CPU time 29.26 seconds
Started Mar 17 02:01:41 PM PDT 24
Finished Mar 17 02:02:10 PM PDT 24
Peak memory 204424 kb
Host smart-b1d099a3-121d-4e12-a7e2-629593747626
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2388178794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2388178794
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.4256051321
Short name T824
Test name
Test status
Simulation time 878514843 ps
CPU time 267.01 seconds
Started Mar 17 02:01:41 PM PDT 24
Finished Mar 17 02:06:08 PM PDT 24
Peak memory 208336 kb
Host smart-9fd1e00a-a35e-4906-ab46-5666f9dcb252
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4256051321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.4256051321
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3546343337
Short name T358
Test name
Test status
Simulation time 3093850085 ps
CPU time 111.5 seconds
Started Mar 17 02:01:51 PM PDT 24
Finished Mar 17 02:03:43 PM PDT 24
Peak memory 209468 kb
Host smart-01336b1a-b692-4d31-8a40-fd742abbd43a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3546343337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.3546343337
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.211082788
Short name T262
Test name
Test status
Simulation time 90201854 ps
CPU time 13.1 seconds
Started Mar 17 02:01:44 PM PDT 24
Finished Mar 17 02:01:57 PM PDT 24
Peak memory 211884 kb
Host smart-8bc0e8ac-3ffe-4f26-a7e1-b0d2e8fad3cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=211082788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.211082788
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3623670966
Short name T344
Test name
Test status
Simulation time 733920038 ps
CPU time 21.94 seconds
Started Mar 17 02:06:03 PM PDT 24
Finished Mar 17 02:06:26 PM PDT 24
Peak memory 204872 kb
Host smart-620e7d0a-8c93-4da2-a0ce-11b6062593fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3623670966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3623670966
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3501485736
Short name T765
Test name
Test status
Simulation time 214019154751 ps
CPU time 661.44 seconds
Started Mar 17 02:06:03 PM PDT 24
Finished Mar 17 02:17:05 PM PDT 24
Peak memory 211976 kb
Host smart-f5d9b6c3-d986-4daa-b090-1316e99548ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3501485736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3501485736
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.595244534
Short name T488
Test name
Test status
Simulation time 188252124 ps
CPU time 9.2 seconds
Started Mar 17 02:06:03 PM PDT 24
Finished Mar 17 02:06:13 PM PDT 24
Peak memory 203864 kb
Host smart-ea2c1b65-3702-4d8e-8331-4a2af335a607
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=595244534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.595244534
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.1581795589
Short name T223
Test name
Test status
Simulation time 65341169 ps
CPU time 8.4 seconds
Started Mar 17 02:06:05 PM PDT 24
Finished Mar 17 02:06:13 PM PDT 24
Peak memory 203708 kb
Host smart-39bee739-39a1-4b26-9552-4ab7aa5fd967
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1581795589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1581795589
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.1325706758
Short name T341
Test name
Test status
Simulation time 494506761 ps
CPU time 17.76 seconds
Started Mar 17 02:06:05 PM PDT 24
Finished Mar 17 02:06:23 PM PDT 24
Peak memory 211872 kb
Host smart-cb1e54a6-2911-4c70-b2a8-f0efa9f81b51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1325706758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1325706758
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.92277664
Short name T91
Test name
Test status
Simulation time 175927982396 ps
CPU time 264.55 seconds
Started Mar 17 02:06:05 PM PDT 24
Finished Mar 17 02:10:30 PM PDT 24
Peak memory 205008 kb
Host smart-d0d22e59-58b6-487d-b144-42303b081091
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=92277664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.92277664
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3996155657
Short name T348
Test name
Test status
Simulation time 21145363095 ps
CPU time 171.53 seconds
Started Mar 17 02:06:04 PM PDT 24
Finished Mar 17 02:08:56 PM PDT 24
Peak memory 211932 kb
Host smart-5bb11b27-ba87-4185-ab23-e201245caf04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3996155657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3996155657
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2478150501
Short name T731
Test name
Test status
Simulation time 322901569 ps
CPU time 18.09 seconds
Started Mar 17 02:06:04 PM PDT 24
Finished Mar 17 02:06:23 PM PDT 24
Peak memory 204844 kb
Host smart-c25dd97d-ba84-4903-8593-791d9da02de8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478150501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2478150501
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.1062014808
Short name T567
Test name
Test status
Simulation time 1760288374 ps
CPU time 20.95 seconds
Started Mar 17 02:06:04 PM PDT 24
Finished Mar 17 02:06:26 PM PDT 24
Peak memory 204148 kb
Host smart-b97d9ad7-9d65-4392-8f53-94e3333c9879
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1062014808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1062014808
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.3946724056
Short name T48
Test name
Test status
Simulation time 364424176 ps
CPU time 4.13 seconds
Started Mar 17 02:05:58 PM PDT 24
Finished Mar 17 02:06:02 PM PDT 24
Peak memory 203692 kb
Host smart-aeb97110-eb27-4564-94f3-68bafba6486a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3946724056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3946724056
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3683498520
Short name T634
Test name
Test status
Simulation time 6437702752 ps
CPU time 30.27 seconds
Started Mar 17 02:06:04 PM PDT 24
Finished Mar 17 02:06:34 PM PDT 24
Peak memory 203784 kb
Host smart-958c66e0-d11c-4fc7-8e04-40e29ebe9130
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683498520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3683498520
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.185877794
Short name T631
Test name
Test status
Simulation time 3294092156 ps
CPU time 30.66 seconds
Started Mar 17 02:06:06 PM PDT 24
Finished Mar 17 02:06:37 PM PDT 24
Peak memory 203780 kb
Host smart-4d3b1376-0c6b-4cdf-8b84-95f7486d8d80
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=185877794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.185877794
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3198756281
Short name T379
Test name
Test status
Simulation time 39433046 ps
CPU time 2.58 seconds
Started Mar 17 02:05:57 PM PDT 24
Finished Mar 17 02:06:00 PM PDT 24
Peak memory 203752 kb
Host smart-2230babb-8b2c-4585-85aa-7ac62d1b01c5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198756281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3198756281
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1945425702
Short name T265
Test name
Test status
Simulation time 30353753 ps
CPU time 2.85 seconds
Started Mar 17 02:06:08 PM PDT 24
Finished Mar 17 02:06:11 PM PDT 24
Peak memory 203724 kb
Host smart-8a9eb759-66bd-4ce7-a8bc-e02c3298aaf4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1945425702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1945425702
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3920738396
Short name T671
Test name
Test status
Simulation time 163288530 ps
CPU time 3.77 seconds
Started Mar 17 02:06:09 PM PDT 24
Finished Mar 17 02:06:13 PM PDT 24
Peak memory 203604 kb
Host smart-1a8fd15b-85ff-4a2d-ae9a-e21e9b37ce17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3920738396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3920738396
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2651411122
Short name T641
Test name
Test status
Simulation time 94632846 ps
CPU time 6.63 seconds
Started Mar 17 02:06:04 PM PDT 24
Finished Mar 17 02:06:11 PM PDT 24
Peak memory 206092 kb
Host smart-b2e173dd-af34-4d11-8ace-774b2ee0afd3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2651411122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.2651411122
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2239374105
Short name T500
Test name
Test status
Simulation time 3483152445 ps
CPU time 208.71 seconds
Started Mar 17 02:06:09 PM PDT 24
Finished Mar 17 02:09:38 PM PDT 24
Peak memory 211920 kb
Host smart-33671e56-c83b-4ef1-8aa8-ad3a5a69b93c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2239374105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.2239374105
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1883630268
Short name T202
Test name
Test status
Simulation time 768252432 ps
CPU time 22.26 seconds
Started Mar 17 02:06:04 PM PDT 24
Finished Mar 17 02:06:27 PM PDT 24
Peak memory 205204 kb
Host smart-63abb887-bac8-4dd3-bda0-dd9bf90756c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1883630268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1883630268
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.888827589
Short name T78
Test name
Test status
Simulation time 1259722265 ps
CPU time 37.57 seconds
Started Mar 17 02:06:21 PM PDT 24
Finished Mar 17 02:06:59 PM PDT 24
Peak memory 206164 kb
Host smart-62e3676c-b802-4d32-99a8-8a60be2e9abe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=888827589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.888827589
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2665772322
Short name T873
Test name
Test status
Simulation time 94933641965 ps
CPU time 665.52 seconds
Started Mar 17 02:06:21 PM PDT 24
Finished Mar 17 02:17:27 PM PDT 24
Peak memory 206296 kb
Host smart-cbeae3d7-5c38-4deb-b600-2995a5d32322
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2665772322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.2665772322
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2348670578
Short name T538
Test name
Test status
Simulation time 243300850 ps
CPU time 4.04 seconds
Started Mar 17 02:06:21 PM PDT 24
Finished Mar 17 02:06:25 PM PDT 24
Peak memory 203720 kb
Host smart-36280000-a1ac-41b7-9512-b5a2bc2f3ebf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2348670578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2348670578
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.1396902373
Short name T805
Test name
Test status
Simulation time 767803079 ps
CPU time 34.41 seconds
Started Mar 17 02:06:21 PM PDT 24
Finished Mar 17 02:06:56 PM PDT 24
Peak memory 203736 kb
Host smart-f1f6284a-207e-4103-8e98-6ad522d56622
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1396902373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1396902373
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.3367801450
Short name T292
Test name
Test status
Simulation time 494096953 ps
CPU time 18.63 seconds
Started Mar 17 02:06:16 PM PDT 24
Finished Mar 17 02:06:35 PM PDT 24
Peak memory 205132 kb
Host smart-464763c3-c592-46ea-b4b4-c70a7414d81c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3367801450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3367801450
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4073395955
Short name T445
Test name
Test status
Simulation time 37823446544 ps
CPU time 154.59 seconds
Started Mar 17 02:06:15 PM PDT 24
Finished Mar 17 02:08:49 PM PDT 24
Peak memory 205348 kb
Host smart-d3ce5eae-5303-46cb-a0e7-618051666986
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073395955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4073395955
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3656371718
Short name T527
Test name
Test status
Simulation time 85188430213 ps
CPU time 284.15 seconds
Started Mar 17 02:06:16 PM PDT 24
Finished Mar 17 02:11:00 PM PDT 24
Peak memory 211980 kb
Host smart-0f7fd5e6-6064-4424-b407-858d0241c6ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3656371718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3656371718
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.783634028
Short name T161
Test name
Test status
Simulation time 152609251 ps
CPU time 18.4 seconds
Started Mar 17 02:06:17 PM PDT 24
Finished Mar 17 02:06:36 PM PDT 24
Peak memory 204744 kb
Host smart-37fe80cc-8bcc-4f5e-86e3-6c8aec639fa3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783634028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.783634028
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.223381154
Short name T186
Test name
Test status
Simulation time 1194792690 ps
CPU time 24.68 seconds
Started Mar 17 02:06:21 PM PDT 24
Finished Mar 17 02:06:46 PM PDT 24
Peak memory 203680 kb
Host smart-06e7add5-1d15-459b-914e-a97f8199f7a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=223381154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.223381154
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.903192448
Short name T270
Test name
Test status
Simulation time 24049877 ps
CPU time 2.63 seconds
Started Mar 17 02:06:10 PM PDT 24
Finished Mar 17 02:06:12 PM PDT 24
Peak memory 203708 kb
Host smart-9d66a6a6-21a4-4a08-be6b-780ca9927dfa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903192448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.903192448
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1419869520
Short name T61
Test name
Test status
Simulation time 6086125457 ps
CPU time 27.94 seconds
Started Mar 17 02:06:09 PM PDT 24
Finished Mar 17 02:06:38 PM PDT 24
Peak memory 203752 kb
Host smart-4fc57ca6-0517-4336-9be9-531860f42413
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419869520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1419869520
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2639207775
Short name T621
Test name
Test status
Simulation time 4103261241 ps
CPU time 35.91 seconds
Started Mar 17 02:06:15 PM PDT 24
Finished Mar 17 02:06:51 PM PDT 24
Peak memory 203672 kb
Host smart-73ef8f6a-882c-4d68-9ac1-cb66e9edfbaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2639207775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2639207775
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.432910401
Short name T630
Test name
Test status
Simulation time 41358895 ps
CPU time 2.18 seconds
Started Mar 17 02:06:09 PM PDT 24
Finished Mar 17 02:06:11 PM PDT 24
Peak memory 203744 kb
Host smart-0090c690-1523-422f-8272-971bacef12c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432910401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.432910401
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1125648848
Short name T361
Test name
Test status
Simulation time 4541079942 ps
CPU time 178.7 seconds
Started Mar 17 02:06:22 PM PDT 24
Finished Mar 17 02:09:20 PM PDT 24
Peak memory 207732 kb
Host smart-3d5228e2-b86f-4e4e-a1c5-ba91cc3c5bec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1125648848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1125648848
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.57354092
Short name T746
Test name
Test status
Simulation time 511757769 ps
CPU time 63.81 seconds
Started Mar 17 02:06:20 PM PDT 24
Finished Mar 17 02:07:24 PM PDT 24
Peak memory 211924 kb
Host smart-46d4d8e6-c5b8-4efd-bbc5-976d78940dac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57354092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.57354092
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1158575979
Short name T311
Test name
Test status
Simulation time 207087721 ps
CPU time 43.63 seconds
Started Mar 17 02:06:21 PM PDT 24
Finished Mar 17 02:07:05 PM PDT 24
Peak memory 206924 kb
Host smart-4da38e65-4bff-491e-b645-4fec06fe6ec5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1158575979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.1158575979
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3749008215
Short name T254
Test name
Test status
Simulation time 1245363369 ps
CPU time 32.14 seconds
Started Mar 17 02:06:22 PM PDT 24
Finished Mar 17 02:06:54 PM PDT 24
Peak memory 205856 kb
Host smart-fd87a51d-ba9d-41a3-a38f-654dcb4d7204
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3749008215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3749008215
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3200206119
Short name T690
Test name
Test status
Simulation time 2197304169 ps
CPU time 56.39 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:07:39 PM PDT 24
Peak memory 205716 kb
Host smart-0d825fd7-bb30-4dc4-bd65-72faffcd2170
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3200206119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3200206119
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3057920488
Short name T547
Test name
Test status
Simulation time 63930574864 ps
CPU time 562.31 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:16:05 PM PDT 24
Peak memory 206244 kb
Host smart-94504ba3-a255-43cc-8b69-d49b8ff1b19e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3057920488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3057920488
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2769952128
Short name T866
Test name
Test status
Simulation time 1163178274 ps
CPU time 22.59 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:07:05 PM PDT 24
Peak memory 204136 kb
Host smart-af8b6619-e366-40cf-8236-2649b7c58f4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2769952128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2769952128
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.2183999557
Short name T155
Test name
Test status
Simulation time 141044125 ps
CPU time 21.8 seconds
Started Mar 17 02:06:43 PM PDT 24
Finished Mar 17 02:07:07 PM PDT 24
Peak memory 203716 kb
Host smart-05c3a199-d6e3-479c-8d5d-8487efbebafb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2183999557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2183999557
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.1738453449
Short name T258
Test name
Test status
Simulation time 127987112 ps
CPU time 15.31 seconds
Started Mar 17 02:06:36 PM PDT 24
Finished Mar 17 02:06:51 PM PDT 24
Peak memory 211932 kb
Host smart-b65dab9f-a418-4123-a381-4541fbf6c59e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1738453449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1738453449
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3914525457
Short name T97
Test name
Test status
Simulation time 25320268677 ps
CPU time 159.78 seconds
Started Mar 17 02:06:36 PM PDT 24
Finished Mar 17 02:09:16 PM PDT 24
Peak memory 205116 kb
Host smart-03915449-4edf-46fc-996e-0b05e2062ea9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914525457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3914525457
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2430738627
Short name T687
Test name
Test status
Simulation time 40968036872 ps
CPU time 141.94 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:09:04 PM PDT 24
Peak memory 205180 kb
Host smart-4cbd4842-2080-41dd-b26c-c3983ff01180
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2430738627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2430738627
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3603911444
Short name T416
Test name
Test status
Simulation time 76286349 ps
CPU time 10.37 seconds
Started Mar 17 02:06:35 PM PDT 24
Finished Mar 17 02:06:46 PM PDT 24
Peak memory 204832 kb
Host smart-b6f4cecd-dd91-4835-bc04-923fd0ca78fb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603911444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3603911444
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.2442689157
Short name T736
Test name
Test status
Simulation time 61156408 ps
CPU time 5.44 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:06:48 PM PDT 24
Peak memory 203732 kb
Host smart-e4af1284-eefd-4cbd-91cd-98cdd60455c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2442689157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2442689157
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.343714011
Short name T525
Test name
Test status
Simulation time 210865896 ps
CPU time 3.18 seconds
Started Mar 17 02:06:26 PM PDT 24
Finished Mar 17 02:06:30 PM PDT 24
Peak memory 203684 kb
Host smart-9f64c607-c21e-4c90-a1da-cd9636fa99a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=343714011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.343714011
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2950192845
Short name T811
Test name
Test status
Simulation time 6935926893 ps
CPU time 30.48 seconds
Started Mar 17 02:06:24 PM PDT 24
Finished Mar 17 02:06:55 PM PDT 24
Peak memory 203748 kb
Host smart-e35388be-01b4-4c1b-acb6-a6369bacfc12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950192845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2950192845
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3721605801
Short name T669
Test name
Test status
Simulation time 20553245958 ps
CPU time 37.8 seconds
Started Mar 17 02:06:26 PM PDT 24
Finished Mar 17 02:07:04 PM PDT 24
Peak memory 203744 kb
Host smart-184eb575-4999-4ffd-b0b8-a8b5ca788459
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3721605801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3721605801
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2918668494
Short name T860
Test name
Test status
Simulation time 155839368 ps
CPU time 2.63 seconds
Started Mar 17 02:06:26 PM PDT 24
Finished Mar 17 02:06:29 PM PDT 24
Peak memory 203644 kb
Host smart-9b1e88a2-3d61-4614-889b-db8c4dd17268
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918668494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2918668494
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.382523920
Short name T87
Test name
Test status
Simulation time 6347751466 ps
CPU time 161.52 seconds
Started Mar 17 02:06:42 PM PDT 24
Finished Mar 17 02:09:26 PM PDT 24
Peak memory 207660 kb
Host smart-d3532517-f67a-4aac-a921-d1abcf2acaf3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=382523920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.382523920
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1295990637
Short name T286
Test name
Test status
Simulation time 23174103766 ps
CPU time 146.36 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:09:09 PM PDT 24
Peak memory 206896 kb
Host smart-46a06c6b-5f94-4396-9762-7ea4c358f71e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1295990637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1295990637
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.369521720
Short name T710
Test name
Test status
Simulation time 123537287 ps
CPU time 38.97 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:07:21 PM PDT 24
Peak memory 207104 kb
Host smart-ae3bb228-a491-4b09-b9cf-eedede771fa2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=369521720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand
_reset.369521720
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.825289569
Short name T414
Test name
Test status
Simulation time 78491055 ps
CPU time 11.2 seconds
Started Mar 17 02:06:41 PM PDT 24
Finished Mar 17 02:06:55 PM PDT 24
Peak memory 205352 kb
Host smart-c695d908-90f8-4f23-a7d8-e5d85eeb1371
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=825289569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.825289569
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1659997247
Short name T352
Test name
Test status
Simulation time 799605032 ps
CPU time 25.95 seconds
Started Mar 17 02:06:47 PM PDT 24
Finished Mar 17 02:07:13 PM PDT 24
Peak memory 204760 kb
Host smart-3e79cd0a-ce29-4fce-8909-d409e2afc315
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1659997247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1659997247
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2324722129
Short name T581
Test name
Test status
Simulation time 972670378 ps
CPU time 14.16 seconds
Started Mar 17 02:06:53 PM PDT 24
Finished Mar 17 02:07:08 PM PDT 24
Peak memory 203800 kb
Host smart-b4b8dea3-2883-43e3-8798-888e54d69c26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2324722129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2324722129
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.2978883240
Short name T114
Test name
Test status
Simulation time 641186524 ps
CPU time 28.66 seconds
Started Mar 17 02:06:54 PM PDT 24
Finished Mar 17 02:07:23 PM PDT 24
Peak memory 203684 kb
Host smart-a380bbb8-7d5b-4ede-86c7-b35ab8f2f55a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2978883240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2978883240
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.997380433
Short name T434
Test name
Test status
Simulation time 1282122031 ps
CPU time 12.99 seconds
Started Mar 17 02:06:46 PM PDT 24
Finished Mar 17 02:06:59 PM PDT 24
Peak memory 204840 kb
Host smart-13aa70b1-92e7-4811-a1b1-accb0f8cbf5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=997380433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.997380433
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3908263716
Short name T206
Test name
Test status
Simulation time 18164609075 ps
CPU time 52.08 seconds
Started Mar 17 02:06:47 PM PDT 24
Finished Mar 17 02:07:39 PM PDT 24
Peak memory 211932 kb
Host smart-2005e6d1-d737-483d-86ab-75ab2b270846
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908263716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3908263716
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3428253454
Short name T486
Test name
Test status
Simulation time 53845089831 ps
CPU time 145.75 seconds
Started Mar 17 02:06:51 PM PDT 24
Finished Mar 17 02:09:17 PM PDT 24
Peak memory 205248 kb
Host smart-e5879992-466c-432c-b6e8-b3826a9d2587
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3428253454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3428253454
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3331368082
Short name T316
Test name
Test status
Simulation time 193443749 ps
CPU time 25.78 seconds
Started Mar 17 02:06:46 PM PDT 24
Finished Mar 17 02:07:12 PM PDT 24
Peak memory 211952 kb
Host smart-055b929d-fd81-4dd3-9afd-cf0a580e2191
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331368082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3331368082
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.2718200139
Short name T836
Test name
Test status
Simulation time 746156379 ps
CPU time 16.89 seconds
Started Mar 17 02:06:54 PM PDT 24
Finished Mar 17 02:07:11 PM PDT 24
Peak memory 203644 kb
Host smart-2f2cef2f-d185-4222-9042-7cae86529d48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2718200139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2718200139
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.823365326
Short name T199
Test name
Test status
Simulation time 204518077 ps
CPU time 3.5 seconds
Started Mar 17 02:06:51 PM PDT 24
Finished Mar 17 02:06:55 PM PDT 24
Peak memory 203688 kb
Host smart-10d6001b-6578-4af8-8146-3f980e743581
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=823365326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.823365326
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1729173084
Short name T278
Test name
Test status
Simulation time 6714102560 ps
CPU time 29.52 seconds
Started Mar 17 02:06:49 PM PDT 24
Finished Mar 17 02:07:18 PM PDT 24
Peak memory 203800 kb
Host smart-756d10b0-3e5d-4c9c-adff-8a1d17246ab8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729173084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1729173084
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2211233543
Short name T745
Test name
Test status
Simulation time 8524077955 ps
CPU time 33.52 seconds
Started Mar 17 02:06:47 PM PDT 24
Finished Mar 17 02:07:21 PM PDT 24
Peak memory 203704 kb
Host smart-c22eb985-9538-4662-9397-ceabf1b24408
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2211233543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2211233543
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.313968982
Short name T657
Test name
Test status
Simulation time 79973046 ps
CPU time 2.62 seconds
Started Mar 17 02:06:47 PM PDT 24
Finished Mar 17 02:06:49 PM PDT 24
Peak memory 203676 kb
Host smart-850a3589-c2e1-4951-bce5-827f219c517f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313968982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.313968982
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2851251944
Short name T101
Test name
Test status
Simulation time 7204662922 ps
CPU time 150.19 seconds
Started Mar 17 02:06:53 PM PDT 24
Finished Mar 17 02:09:23 PM PDT 24
Peak memory 210280 kb
Host smart-b2ef5bee-0534-4a9f-ac5f-dafaa974643e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2851251944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2851251944
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1284864639
Short name T446
Test name
Test status
Simulation time 1828263695 ps
CPU time 158.34 seconds
Started Mar 17 02:06:59 PM PDT 24
Finished Mar 17 02:09:37 PM PDT 24
Peak memory 206824 kb
Host smart-a1787dd5-3a80-4982-93fa-bf36b7bebcfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1284864639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1284864639
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2933939337
Short name T841
Test name
Test status
Simulation time 5265105060 ps
CPU time 133.9 seconds
Started Mar 17 02:07:01 PM PDT 24
Finished Mar 17 02:09:15 PM PDT 24
Peak memory 208508 kb
Host smart-ea1ab5da-46f8-42bf-a3f8-2d7f063d55d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2933939337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.2933939337
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3850648586
Short name T649
Test name
Test status
Simulation time 4666649506 ps
CPU time 137.31 seconds
Started Mar 17 02:06:58 PM PDT 24
Finished Mar 17 02:09:15 PM PDT 24
Peak memory 210268 kb
Host smart-013a88e4-3b0e-4b88-a076-257230eba6bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3850648586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.3850648586
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.4013598725
Short name T334
Test name
Test status
Simulation time 52453635 ps
CPU time 5.28 seconds
Started Mar 17 02:06:53 PM PDT 24
Finished Mar 17 02:06:59 PM PDT 24
Peak memory 205152 kb
Host smart-a3992e1c-ee54-4e03-b64a-755a9e181e13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4013598725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.4013598725
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3793181254
Short name T437
Test name
Test status
Simulation time 1672305125 ps
CPU time 58.74 seconds
Started Mar 17 02:07:02 PM PDT 24
Finished Mar 17 02:08:00 PM PDT 24
Peak memory 205712 kb
Host smart-dfe4a39b-6487-4fd9-a1a9-74ea41c5d769
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3793181254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3793181254
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1191757360
Short name T287
Test name
Test status
Simulation time 147831188968 ps
CPU time 508.37 seconds
Started Mar 17 02:07:05 PM PDT 24
Finished Mar 17 02:15:34 PM PDT 24
Peak memory 211976 kb
Host smart-795d7a37-3472-4ca5-90f1-2ee0ea2d1c89
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1191757360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.1191757360
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3243463361
Short name T800
Test name
Test status
Simulation time 670488174 ps
CPU time 14.65 seconds
Started Mar 17 02:07:10 PM PDT 24
Finished Mar 17 02:07:25 PM PDT 24
Peak memory 203744 kb
Host smart-f842f968-735a-4841-a65c-8aae3aecac92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3243463361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3243463361
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1553846694
Short name T582
Test name
Test status
Simulation time 1363848907 ps
CPU time 36.68 seconds
Started Mar 17 02:07:03 PM PDT 24
Finished Mar 17 02:07:40 PM PDT 24
Peak memory 203640 kb
Host smart-6a046f4b-aaf8-4c73-97da-cb19d3261a2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1553846694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1553846694
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.4049849743
Short name T552
Test name
Test status
Simulation time 1177589422 ps
CPU time 30.34 seconds
Started Mar 17 02:06:59 PM PDT 24
Finished Mar 17 02:07:29 PM PDT 24
Peak memory 204832 kb
Host smart-e4151e9b-1911-4771-9bc8-0b2b0af6c2ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4049849743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.4049849743
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.80240372
Short name T141
Test name
Test status
Simulation time 51807399220 ps
CPU time 68.62 seconds
Started Mar 17 02:07:02 PM PDT 24
Finished Mar 17 02:08:11 PM PDT 24
Peak memory 205048 kb
Host smart-eee67be9-47f7-45e0-b65d-5494dece5c15
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80240372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.80240372
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1452575406
Short name T773
Test name
Test status
Simulation time 9161888219 ps
CPU time 90.19 seconds
Started Mar 17 02:06:58 PM PDT 24
Finished Mar 17 02:08:28 PM PDT 24
Peak memory 205128 kb
Host smart-f47486ef-1c65-463b-b1d3-f13810260026
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1452575406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1452575406
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.205820610
Short name T397
Test name
Test status
Simulation time 152641140 ps
CPU time 12.1 seconds
Started Mar 17 02:07:01 PM PDT 24
Finished Mar 17 02:07:13 PM PDT 24
Peak memory 204884 kb
Host smart-8a9b31ad-52b5-463d-a4da-5893a95c9603
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205820610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.205820610
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.3568736339
Short name T563
Test name
Test status
Simulation time 377434578 ps
CPU time 11.02 seconds
Started Mar 17 02:07:03 PM PDT 24
Finished Mar 17 02:07:14 PM PDT 24
Peak memory 203704 kb
Host smart-a631195a-5167-4863-b25d-bfa4a8a70fae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3568736339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3568736339
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.1141391071
Short name T583
Test name
Test status
Simulation time 28883909 ps
CPU time 2.58 seconds
Started Mar 17 02:06:58 PM PDT 24
Finished Mar 17 02:07:01 PM PDT 24
Peak memory 203696 kb
Host smart-1dc532cf-1e90-41be-9209-b8c3f134bffe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1141391071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1141391071
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2953815806
Short name T419
Test name
Test status
Simulation time 6172184257 ps
CPU time 31.77 seconds
Started Mar 17 02:06:58 PM PDT 24
Finished Mar 17 02:07:30 PM PDT 24
Peak memory 203732 kb
Host smart-4ece55a2-2e4e-4000-b255-9ff2ad788896
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953815806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2953815806
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2194790199
Short name T865
Test name
Test status
Simulation time 5912276154 ps
CPU time 26.92 seconds
Started Mar 17 02:07:03 PM PDT 24
Finished Mar 17 02:07:30 PM PDT 24
Peak memory 203800 kb
Host smart-dcd78b18-1647-4bb1-97d7-dfeefe549b13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2194790199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2194790199
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1878344494
Short name T612
Test name
Test status
Simulation time 52253337 ps
CPU time 2.34 seconds
Started Mar 17 02:07:01 PM PDT 24
Finished Mar 17 02:07:03 PM PDT 24
Peak memory 203660 kb
Host smart-fd2d4e87-42ca-422e-8e92-f30a6ee9e92a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878344494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1878344494
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.4159522937
Short name T876
Test name
Test status
Simulation time 6493392 ps
CPU time 0.81 seconds
Started Mar 17 02:07:10 PM PDT 24
Finished Mar 17 02:07:13 PM PDT 24
Peak memory 195416 kb
Host smart-2f0f643a-f72e-455f-a54c-90132a49bfe3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4159522937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4159522937
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2738988408
Short name T543
Test name
Test status
Simulation time 24884527298 ps
CPU time 147.41 seconds
Started Mar 17 02:07:11 PM PDT 24
Finished Mar 17 02:09:39 PM PDT 24
Peak memory 208228 kb
Host smart-e513a3e2-4207-4830-ad30-4c075a110ff0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2738988408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2738988408
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1100163996
Short name T166
Test name
Test status
Simulation time 5938340964 ps
CPU time 304.62 seconds
Started Mar 17 02:07:12 PM PDT 24
Finished Mar 17 02:12:17 PM PDT 24
Peak memory 211372 kb
Host smart-e5c64d83-2cf1-4b8b-9480-fc46fa8a2bcf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1100163996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.1100163996
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1597562466
Short name T27
Test name
Test status
Simulation time 1974973904 ps
CPU time 328.76 seconds
Started Mar 17 02:07:12 PM PDT 24
Finished Mar 17 02:12:41 PM PDT 24
Peak memory 224536 kb
Host smart-ef32d728-8303-46c6-842b-fb32ba4a316f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1597562466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.1597562466
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2623058280
Short name T70
Test name
Test status
Simulation time 135107535 ps
CPU time 7.04 seconds
Started Mar 17 02:07:02 PM PDT 24
Finished Mar 17 02:07:09 PM PDT 24
Peak memory 204932 kb
Host smart-fc037fec-bfe0-43dc-90fa-85369f047b8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2623058280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2623058280
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.85007683
Short name T152
Test name
Test status
Simulation time 458863862 ps
CPU time 23.54 seconds
Started Mar 17 02:07:22 PM PDT 24
Finished Mar 17 02:07:45 PM PDT 24
Peak memory 204844 kb
Host smart-c3363b94-1eba-478e-a8c7-140baff4ec86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85007683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.85007683
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2159284126
Short name T489
Test name
Test status
Simulation time 56624713828 ps
CPU time 322.25 seconds
Started Mar 17 02:07:23 PM PDT 24
Finished Mar 17 02:12:45 PM PDT 24
Peak memory 206276 kb
Host smart-2a14a31b-30bb-403f-8ee6-3dac07365890
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2159284126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.2159284126
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.675255948
Short name T636
Test name
Test status
Simulation time 1045234600 ps
CPU time 32.72 seconds
Started Mar 17 02:07:27 PM PDT 24
Finished Mar 17 02:08:00 PM PDT 24
Peak memory 204300 kb
Host smart-b34391dd-a1bd-442a-91b9-72c9ddfa9c1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=675255948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.675255948
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.546056880
Short name T610
Test name
Test status
Simulation time 862790784 ps
CPU time 27.06 seconds
Started Mar 17 02:07:22 PM PDT 24
Finished Mar 17 02:07:50 PM PDT 24
Peak memory 203628 kb
Host smart-6400b77a-0a97-4a05-9b3b-d055b4ab9f9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=546056880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.546056880
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.3575938413
Short name T700
Test name
Test status
Simulation time 774477629 ps
CPU time 35.51 seconds
Started Mar 17 02:07:16 PM PDT 24
Finished Mar 17 02:07:51 PM PDT 24
Peak memory 211828 kb
Host smart-ee08f059-d69f-40ab-934b-bec8db7b476f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3575938413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3575938413
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2346749500
Short name T703
Test name
Test status
Simulation time 40333472257 ps
CPU time 92.3 seconds
Started Mar 17 02:07:22 PM PDT 24
Finished Mar 17 02:08:54 PM PDT 24
Peak memory 211896 kb
Host smart-16a78f7d-776f-4ce8-ac75-bb7c02d6707a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346749500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2346749500
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.336576075
Short name T814
Test name
Test status
Simulation time 27311805437 ps
CPU time 211.6 seconds
Started Mar 17 02:07:22 PM PDT 24
Finished Mar 17 02:10:53 PM PDT 24
Peak memory 205616 kb
Host smart-397cc3f1-9dd5-4b4e-97ee-9b149ad7f1f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=336576075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.336576075
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1485780138
Short name T218
Test name
Test status
Simulation time 65252780 ps
CPU time 6.94 seconds
Started Mar 17 02:07:15 PM PDT 24
Finished Mar 17 02:07:22 PM PDT 24
Peak memory 211928 kb
Host smart-6e100978-ce99-4bfe-b603-8baa28e6e096
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485780138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1485780138
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.2255638480
Short name T192
Test name
Test status
Simulation time 1440106308 ps
CPU time 10.7 seconds
Started Mar 17 02:07:22 PM PDT 24
Finished Mar 17 02:07:33 PM PDT 24
Peak memory 204440 kb
Host smart-96d1e329-7f08-4099-8646-8eb394c41fe3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2255638480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2255638480
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.302221823
Short name T558
Test name
Test status
Simulation time 131419155 ps
CPU time 3.84 seconds
Started Mar 17 02:07:10 PM PDT 24
Finished Mar 17 02:07:14 PM PDT 24
Peak memory 203724 kb
Host smart-80572f1f-d15c-4c4f-a26f-7c0d23c8241c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=302221823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.302221823
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.606922477
Short name T200
Test name
Test status
Simulation time 9209600950 ps
CPU time 29.97 seconds
Started Mar 17 02:07:16 PM PDT 24
Finished Mar 17 02:07:46 PM PDT 24
Peak memory 203796 kb
Host smart-883b036d-4382-4997-8a61-7239cb32e74b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=606922477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.606922477
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2776043907
Short name T327
Test name
Test status
Simulation time 4657563500 ps
CPU time 27.83 seconds
Started Mar 17 02:07:15 PM PDT 24
Finished Mar 17 02:07:43 PM PDT 24
Peak memory 203748 kb
Host smart-979287fe-00af-405f-af3c-e8d5b226599c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2776043907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2776043907
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.546270771
Short name T833
Test name
Test status
Simulation time 37521030 ps
CPU time 2.25 seconds
Started Mar 17 02:07:12 PM PDT 24
Finished Mar 17 02:07:14 PM PDT 24
Peak memory 203644 kb
Host smart-db248e67-55ad-4559-ad5a-43b0491282fe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546270771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.546270771
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1423181017
Short name T74
Test name
Test status
Simulation time 2199782112 ps
CPU time 47.95 seconds
Started Mar 17 02:07:29 PM PDT 24
Finished Mar 17 02:08:18 PM PDT 24
Peak memory 206548 kb
Host smart-713b80ed-efdc-4113-aa4c-217dab9860b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1423181017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1423181017
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.18433756
Short name T713
Test name
Test status
Simulation time 1169300600 ps
CPU time 103.63 seconds
Started Mar 17 02:07:29 PM PDT 24
Finished Mar 17 02:09:13 PM PDT 24
Peak memory 206692 kb
Host smart-91f0648b-2495-4238-b15b-fad11dfb1aa6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18433756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.18433756
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.913025562
Short name T428
Test name
Test status
Simulation time 356837613 ps
CPU time 164.87 seconds
Started Mar 17 02:07:27 PM PDT 24
Finished Mar 17 02:10:12 PM PDT 24
Peak memory 209168 kb
Host smart-6d6c2834-7cf0-4566-9880-94d5dddb9eb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=913025562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand
_reset.913025562
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1712052467
Short name T696
Test name
Test status
Simulation time 8377159938 ps
CPU time 337.03 seconds
Started Mar 17 02:07:28 PM PDT 24
Finished Mar 17 02:13:05 PM PDT 24
Peak memory 220208 kb
Host smart-5f8d0a03-c29e-4543-9f6f-4bcb516cd43a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1712052467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.1712052467
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3703056128
Short name T778
Test name
Test status
Simulation time 1191879154 ps
CPU time 28.05 seconds
Started Mar 17 02:07:23 PM PDT 24
Finished Mar 17 02:07:51 PM PDT 24
Peak memory 204936 kb
Host smart-ba07bce8-b7d9-4413-ba1b-f6a1e4e2ffdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3703056128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3703056128
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4111387822
Short name T103
Test name
Test status
Simulation time 5892646769 ps
CPU time 70.57 seconds
Started Mar 17 02:07:41 PM PDT 24
Finished Mar 17 02:08:53 PM PDT 24
Peak memory 207364 kb
Host smart-2bab9990-8c32-40a1-a98a-c271f0be8b75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111387822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4111387822
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1263856581
Short name T823
Test name
Test status
Simulation time 195620659835 ps
CPU time 432.65 seconds
Started Mar 17 02:07:40 PM PDT 24
Finished Mar 17 02:14:53 PM PDT 24
Peak memory 211972 kb
Host smart-85a3052a-670a-4333-bbf1-dafefb8622ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1263856581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.1263856581
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.649838757
Short name T619
Test name
Test status
Simulation time 151978470 ps
CPU time 19.01 seconds
Started Mar 17 02:07:40 PM PDT 24
Finished Mar 17 02:08:00 PM PDT 24
Peak memory 203964 kb
Host smart-37e5e0ab-aafc-4e6a-b813-019c97951743
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=649838757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.649838757
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.79186209
Short name T569
Test name
Test status
Simulation time 1345388104 ps
CPU time 37.89 seconds
Started Mar 17 02:07:40 PM PDT 24
Finished Mar 17 02:08:18 PM PDT 24
Peak memory 203700 kb
Host smart-20e943bc-08b7-4eb1-b305-362dea7fbe24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79186209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.79186209
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3815096399
Short name T245
Test name
Test status
Simulation time 63301266 ps
CPU time 2.62 seconds
Started Mar 17 02:07:36 PM PDT 24
Finished Mar 17 02:07:39 PM PDT 24
Peak memory 203620 kb
Host smart-0f9d2dd4-b79e-4541-92dd-aa6476b74a9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3815096399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3815096399
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1810811060
Short name T132
Test name
Test status
Simulation time 180436989576 ps
CPU time 255.93 seconds
Started Mar 17 02:07:33 PM PDT 24
Finished Mar 17 02:11:50 PM PDT 24
Peak memory 205280 kb
Host smart-f1969f92-054a-47a8-8c55-1982a4dc7638
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810811060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1810811060
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2829843109
Short name T54
Test name
Test status
Simulation time 29412867831 ps
CPU time 221.43 seconds
Started Mar 17 02:07:36 PM PDT 24
Finished Mar 17 02:11:17 PM PDT 24
Peak memory 204968 kb
Host smart-dd60b2e7-73e6-433a-b0f0-b74396f653ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2829843109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2829843109
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3187016192
Short name T585
Test name
Test status
Simulation time 17769883 ps
CPU time 2.09 seconds
Started Mar 17 02:07:37 PM PDT 24
Finished Mar 17 02:07:39 PM PDT 24
Peak memory 203640 kb
Host smart-5e4f8822-5449-4735-bf1a-4af344e2a2d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187016192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3187016192
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.490792472
Short name T239
Test name
Test status
Simulation time 534864377 ps
CPU time 7.82 seconds
Started Mar 17 02:07:41 PM PDT 24
Finished Mar 17 02:07:51 PM PDT 24
Peak memory 204048 kb
Host smart-52d878b2-c863-49ba-93d5-5f96e349618b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=490792472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.490792472
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.2873012023
Short name T565
Test name
Test status
Simulation time 39961949 ps
CPU time 2.56 seconds
Started Mar 17 02:07:27 PM PDT 24
Finished Mar 17 02:07:30 PM PDT 24
Peak memory 203596 kb
Host smart-bd7180e0-8742-4a84-8eb3-27864c6e7f95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2873012023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2873012023
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1024031764
Short name T294
Test name
Test status
Simulation time 26378738698 ps
CPU time 41.95 seconds
Started Mar 17 02:07:35 PM PDT 24
Finished Mar 17 02:08:17 PM PDT 24
Peak memory 203752 kb
Host smart-8d9adc49-8cc1-470f-b698-2ad6ea884948
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024031764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1024031764
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1133930539
Short name T715
Test name
Test status
Simulation time 3823896519 ps
CPU time 27.06 seconds
Started Mar 17 02:07:33 PM PDT 24
Finished Mar 17 02:08:01 PM PDT 24
Peak memory 203796 kb
Host smart-85ecea6e-70d5-4630-8e72-b693ebc5b148
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1133930539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1133930539
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1603498171
Short name T288
Test name
Test status
Simulation time 114208499 ps
CPU time 2.83 seconds
Started Mar 17 02:07:34 PM PDT 24
Finished Mar 17 02:07:37 PM PDT 24
Peak memory 203668 kb
Host smart-3b98c9c2-bd1f-4582-ae5c-1ac23aa5759f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603498171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1603498171
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3987377235
Short name T377
Test name
Test status
Simulation time 7641518634 ps
CPU time 142.05 seconds
Started Mar 17 02:07:40 PM PDT 24
Finished Mar 17 02:10:02 PM PDT 24
Peak memory 209396 kb
Host smart-e36f398f-448d-48d1-a012-f3b4a8099721
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3987377235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3987377235
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4164748103
Short name T706
Test name
Test status
Simulation time 301025153 ps
CPU time 24.15 seconds
Started Mar 17 02:07:48 PM PDT 24
Finished Mar 17 02:08:12 PM PDT 24
Peak memory 205952 kb
Host smart-77f2ec18-d6b9-4d4f-be58-3f7f4ae5b790
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4164748103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4164748103
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2437252856
Short name T22
Test name
Test status
Simulation time 484506964 ps
CPU time 168.8 seconds
Started Mar 17 02:07:48 PM PDT 24
Finished Mar 17 02:10:37 PM PDT 24
Peak memory 208500 kb
Host smart-3dd140c8-2879-4142-b67b-5c595fb113a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2437252856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.2437252856
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3408789365
Short name T806
Test name
Test status
Simulation time 282311917 ps
CPU time 35.17 seconds
Started Mar 17 02:07:48 PM PDT 24
Finished Mar 17 02:08:23 PM PDT 24
Peak memory 206160 kb
Host smart-f0ed7a4c-3330-4758-b7cd-18cb59c0b144
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3408789365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.3408789365
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2655610035
Short name T869
Test name
Test status
Simulation time 159862036 ps
CPU time 10.75 seconds
Started Mar 17 02:07:40 PM PDT 24
Finished Mar 17 02:07:51 PM PDT 24
Peak memory 205404 kb
Host smart-3c6747cd-6e0a-42aa-a2c2-967b3c26402b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2655610035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2655610035
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1298033173
Short name T125
Test name
Test status
Simulation time 2605108071 ps
CPU time 29.15 seconds
Started Mar 17 02:07:52 PM PDT 24
Finished Mar 17 02:08:21 PM PDT 24
Peak memory 204812 kb
Host smart-a8c7d138-22f1-47fd-b46c-92feffc80821
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1298033173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1298033173
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2295999223
Short name T508
Test name
Test status
Simulation time 56012091327 ps
CPU time 446.58 seconds
Started Mar 17 02:07:53 PM PDT 24
Finished Mar 17 02:15:20 PM PDT 24
Peak memory 211928 kb
Host smart-d41aa039-7e2b-4407-bf53-8cf6915a316c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2295999223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.2295999223
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3178303337
Short name T336
Test name
Test status
Simulation time 93246080 ps
CPU time 10.53 seconds
Started Mar 17 02:07:58 PM PDT 24
Finished Mar 17 02:08:09 PM PDT 24
Peak memory 203624 kb
Host smart-75262c86-8605-4d75-bec3-56e94aecac24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3178303337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3178303337
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.3378111676
Short name T364
Test name
Test status
Simulation time 1166093199 ps
CPU time 18.01 seconds
Started Mar 17 02:07:58 PM PDT 24
Finished Mar 17 02:08:16 PM PDT 24
Peak memory 203720 kb
Host smart-7fe5bb6d-1feb-4a84-9dcb-1a5c3ccd5950
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3378111676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3378111676
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.3690565809
Short name T574
Test name
Test status
Simulation time 86134986 ps
CPU time 13.02 seconds
Started Mar 17 02:07:52 PM PDT 24
Finished Mar 17 02:08:05 PM PDT 24
Peak memory 204848 kb
Host smart-0aab54b6-6b8e-4428-8b8c-e19d65244fb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3690565809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3690565809
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3744783073
Short name T170
Test name
Test status
Simulation time 39447995609 ps
CPU time 154.19 seconds
Started Mar 17 02:07:51 PM PDT 24
Finished Mar 17 02:10:25 PM PDT 24
Peak memory 212008 kb
Host smart-c78996a6-8ad4-4b08-bfcc-75d17f3cdcc7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744783073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3744783073
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2993536159
Short name T375
Test name
Test status
Simulation time 24290075103 ps
CPU time 126.91 seconds
Started Mar 17 02:07:53 PM PDT 24
Finished Mar 17 02:10:00 PM PDT 24
Peak memory 211956 kb
Host smart-6d21d5a0-5c84-46ef-bb63-de064e9e5cee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2993536159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2993536159
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.650499444
Short name T225
Test name
Test status
Simulation time 207960380 ps
CPU time 24.99 seconds
Started Mar 17 02:07:53 PM PDT 24
Finished Mar 17 02:08:18 PM PDT 24
Peak memory 204920 kb
Host smart-c4d70aea-fca1-4f5c-9eba-caecde4a2190
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650499444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.650499444
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.1032934002
Short name T474
Test name
Test status
Simulation time 313743523 ps
CPU time 8.62 seconds
Started Mar 17 02:07:52 PM PDT 24
Finished Mar 17 02:08:01 PM PDT 24
Peak memory 203700 kb
Host smart-7567eabe-38b9-4beb-b4f9-17de34e99eb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1032934002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1032934002
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.188974476
Short name T613
Test name
Test status
Simulation time 156061454 ps
CPU time 3.93 seconds
Started Mar 17 02:07:48 PM PDT 24
Finished Mar 17 02:07:52 PM PDT 24
Peak memory 203692 kb
Host smart-4b9e0ac2-d2e4-4d2b-9df3-fcae353523cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=188974476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.188974476
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.686242214
Short name T750
Test name
Test status
Simulation time 5067099693 ps
CPU time 28.91 seconds
Started Mar 17 02:07:48 PM PDT 24
Finished Mar 17 02:08:17 PM PDT 24
Peak memory 203752 kb
Host smart-a838af5f-6e82-4294-86f9-38ad7bbdde4b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=686242214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.686242214
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1307036513
Short name T369
Test name
Test status
Simulation time 2821981170 ps
CPU time 25.77 seconds
Started Mar 17 02:07:53 PM PDT 24
Finished Mar 17 02:08:19 PM PDT 24
Peak memory 203800 kb
Host smart-068d5def-a68b-4d86-b25d-7c19d1d352b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1307036513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1307036513
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.858669570
Short name T821
Test name
Test status
Simulation time 31647683 ps
CPU time 2.28 seconds
Started Mar 17 02:07:48 PM PDT 24
Finished Mar 17 02:07:50 PM PDT 24
Peak memory 203696 kb
Host smart-91d7cfe3-aa10-4e97-87e7-da0e0a9a230f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858669570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.858669570
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.4095043173
Short name T69
Test name
Test status
Simulation time 3726482704 ps
CPU time 65.52 seconds
Started Mar 17 02:07:59 PM PDT 24
Finished Mar 17 02:09:05 PM PDT 24
Peak memory 206588 kb
Host smart-1a6acd07-9125-437c-93cf-31f6cd55969e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4095043173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4095043173
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.869668853
Short name T659
Test name
Test status
Simulation time 7062560832 ps
CPU time 121.63 seconds
Started Mar 17 02:08:00 PM PDT 24
Finished Mar 17 02:10:01 PM PDT 24
Peak memory 208100 kb
Host smart-8abb8e05-e87a-4e6d-b5f8-dd6078d9aa9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=869668853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.869668853
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2784763208
Short name T859
Test name
Test status
Simulation time 53477305 ps
CPU time 51.03 seconds
Started Mar 17 02:07:59 PM PDT 24
Finished Mar 17 02:08:50 PM PDT 24
Peak memory 207364 kb
Host smart-3d5acb1f-1bf4-4e7b-809d-64b45c76cedf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2784763208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.2784763208
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.35287170
Short name T388
Test name
Test status
Simulation time 553563114 ps
CPU time 76.25 seconds
Started Mar 17 02:07:59 PM PDT 24
Finished Mar 17 02:09:16 PM PDT 24
Peak memory 208960 kb
Host smart-de445d7d-26ba-4239-848c-2065207368e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35287170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rese
t_error.35287170
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1274192251
Short name T668
Test name
Test status
Simulation time 889884149 ps
CPU time 15.49 seconds
Started Mar 17 02:07:58 PM PDT 24
Finished Mar 17 02:08:14 PM PDT 24
Peak memory 211912 kb
Host smart-3c8a2fa4-81c4-465b-b6e7-65270b6f55cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1274192251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1274192251
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3279025401
Short name T177
Test name
Test status
Simulation time 1525221438 ps
CPU time 74.22 seconds
Started Mar 17 02:08:06 PM PDT 24
Finished Mar 17 02:09:21 PM PDT 24
Peak memory 211872 kb
Host smart-ede2e035-87af-40c2-ade9-5e82d919b989
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3279025401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3279025401
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3495355112
Short name T855
Test name
Test status
Simulation time 28937106656 ps
CPU time 281.79 seconds
Started Mar 17 02:08:03 PM PDT 24
Finished Mar 17 02:12:45 PM PDT 24
Peak memory 212000 kb
Host smart-95bc7a6e-f098-422b-a1be-f52f7843ada7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3495355112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.3495355112
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2346710143
Short name T839
Test name
Test status
Simulation time 55630649 ps
CPU time 8.11 seconds
Started Mar 17 02:08:09 PM PDT 24
Finished Mar 17 02:08:17 PM PDT 24
Peak memory 203724 kb
Host smart-7eabe7ef-1b69-4590-b895-b3bd03c50ac6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2346710143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2346710143
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.629855695
Short name T236
Test name
Test status
Simulation time 966621931 ps
CPU time 28.03 seconds
Started Mar 17 02:08:04 PM PDT 24
Finished Mar 17 02:08:33 PM PDT 24
Peak memory 203696 kb
Host smart-a7d3c9c1-136e-410c-aed3-cfa2d84a7392
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=629855695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.629855695
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.2632917512
Short name T193
Test name
Test status
Simulation time 1957062371 ps
CPU time 39.77 seconds
Started Mar 17 02:08:03 PM PDT 24
Finished Mar 17 02:08:43 PM PDT 24
Peak memory 205068 kb
Host smart-d4c15e91-2c59-4713-85c1-4270071430a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2632917512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2632917512
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2798750152
Short name T674
Test name
Test status
Simulation time 85583656907 ps
CPU time 259.24 seconds
Started Mar 17 02:08:03 PM PDT 24
Finished Mar 17 02:12:23 PM PDT 24
Peak memory 205500 kb
Host smart-6a0938ed-b377-425e-bbbe-9781ef779ab8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798750152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2798750152
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3895580287
Short name T50
Test name
Test status
Simulation time 145167459123 ps
CPU time 276.01 seconds
Started Mar 17 02:08:05 PM PDT 24
Finished Mar 17 02:12:42 PM PDT 24
Peak memory 205264 kb
Host smart-d0dcb1ba-8edc-4083-9284-9d6ea5818de1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3895580287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3895580287
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3465996262
Short name T6
Test name
Test status
Simulation time 41995363 ps
CPU time 7.5 seconds
Started Mar 17 02:08:04 PM PDT 24
Finished Mar 17 02:08:11 PM PDT 24
Peak memory 204980 kb
Host smart-316ae441-6571-4667-a77b-def68c44bced
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465996262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3465996262
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.3659440543
Short name T307
Test name
Test status
Simulation time 1291176050 ps
CPU time 27.78 seconds
Started Mar 17 02:08:04 PM PDT 24
Finished Mar 17 02:08:32 PM PDT 24
Peak memory 204332 kb
Host smart-450c300d-2bd4-4a15-9e72-b1e94c034135
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3659440543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3659440543
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.2575297756
Short name T837
Test name
Test status
Simulation time 317574812 ps
CPU time 3.75 seconds
Started Mar 17 02:07:58 PM PDT 24
Finished Mar 17 02:08:02 PM PDT 24
Peak memory 203652 kb
Host smart-9779501f-bb8b-4475-8760-42f18b0d3c70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2575297756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2575297756
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3495928582
Short name T337
Test name
Test status
Simulation time 5913094103 ps
CPU time 27.57 seconds
Started Mar 17 02:08:03 PM PDT 24
Finished Mar 17 02:08:31 PM PDT 24
Peak memory 203796 kb
Host smart-1427e66e-1b93-45d0-955b-8e71022d0b9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495928582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3495928582
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4056492132
Short name T121
Test name
Test status
Simulation time 4071698661 ps
CPU time 23.74 seconds
Started Mar 17 02:08:05 PM PDT 24
Finished Mar 17 02:08:29 PM PDT 24
Peak memory 203760 kb
Host smart-71e8dede-b511-4565-b636-110c05e3ad27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4056492132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4056492132
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.287254508
Short name T531
Test name
Test status
Simulation time 43080235 ps
CPU time 2.66 seconds
Started Mar 17 02:07:59 PM PDT 24
Finished Mar 17 02:08:03 PM PDT 24
Peak memory 203612 kb
Host smart-6609558a-03ef-485f-bae8-7751eed7fc56
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287254508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.287254508
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.4040737948
Short name T788
Test name
Test status
Simulation time 9228898758 ps
CPU time 144.94 seconds
Started Mar 17 02:08:13 PM PDT 24
Finished Mar 17 02:10:38 PM PDT 24
Peak memory 205880 kb
Host smart-f9fe4885-7e78-457c-bc8a-ca9c6b371e5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4040737948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4040737948
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3990995541
Short name T295
Test name
Test status
Simulation time 5241854140 ps
CPU time 179.81 seconds
Started Mar 17 02:08:13 PM PDT 24
Finished Mar 17 02:11:13 PM PDT 24
Peak memory 209464 kb
Host smart-90c509d7-a06c-4286-91d9-461cf263ebc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3990995541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3990995541
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.462894392
Short name T34
Test name
Test status
Simulation time 6261751087 ps
CPU time 266.95 seconds
Started Mar 17 02:08:10 PM PDT 24
Finished Mar 17 02:12:37 PM PDT 24
Peak memory 221640 kb
Host smart-19056983-b076-45c9-b7b3-4719284c2235
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=462894392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res
et_error.462894392
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1775392697
Short name T112
Test name
Test status
Simulation time 623160547 ps
CPU time 18.32 seconds
Started Mar 17 02:08:12 PM PDT 24
Finished Mar 17 02:08:30 PM PDT 24
Peak memory 211860 kb
Host smart-962cf277-89c2-4563-b5bb-d42346ae946d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1775392697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1775392697
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2422769086
Short name T590
Test name
Test status
Simulation time 2827512387 ps
CPU time 28.4 seconds
Started Mar 17 02:08:15 PM PDT 24
Finished Mar 17 02:08:43 PM PDT 24
Peak memory 204488 kb
Host smart-27aeb766-4575-49c6-a391-e9fa825c0523
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2422769086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2422769086
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3192551405
Short name T591
Test name
Test status
Simulation time 66984044101 ps
CPU time 451.5 seconds
Started Mar 17 02:08:16 PM PDT 24
Finished Mar 17 02:15:47 PM PDT 24
Peak memory 207024 kb
Host smart-a7b62dd7-2e46-47dc-b54a-e29784f81c19
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3192551405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.3192551405
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1141946219
Short name T863
Test name
Test status
Simulation time 116827941 ps
CPU time 14.51 seconds
Started Mar 17 02:08:22 PM PDT 24
Finished Mar 17 02:08:36 PM PDT 24
Peak memory 203836 kb
Host smart-a10ce33c-c76c-4c79-ad18-b91f4ecae22b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1141946219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1141946219
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.3555629631
Short name T182
Test name
Test status
Simulation time 644135320 ps
CPU time 16.95 seconds
Started Mar 17 02:08:22 PM PDT 24
Finished Mar 17 02:08:39 PM PDT 24
Peak memory 203748 kb
Host smart-2f613fc2-d541-4aea-8fb7-7569ca8e7bf0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3555629631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3555629631
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.2226033524
Short name T640
Test name
Test status
Simulation time 114377037 ps
CPU time 20.51 seconds
Started Mar 17 02:08:16 PM PDT 24
Finished Mar 17 02:08:36 PM PDT 24
Peak memory 211800 kb
Host smart-68e214b9-363b-44db-932b-c22adecb7da7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2226033524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2226033524
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3569139853
Short name T174
Test name
Test status
Simulation time 21675108790 ps
CPU time 132.12 seconds
Started Mar 17 02:08:16 PM PDT 24
Finished Mar 17 02:10:28 PM PDT 24
Peak memory 205004 kb
Host smart-ab6e90b0-1445-4416-99b6-d44fbd9458e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569139853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3569139853
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.4022382541
Short name T52
Test name
Test status
Simulation time 12676241248 ps
CPU time 111.2 seconds
Started Mar 17 02:08:15 PM PDT 24
Finished Mar 17 02:10:06 PM PDT 24
Peak memory 211988 kb
Host smart-0ff2450b-19f5-4f33-bd4d-f3d945411974
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4022382541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.4022382541
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3734795874
Short name T411
Test name
Test status
Simulation time 166834103 ps
CPU time 23.61 seconds
Started Mar 17 02:08:15 PM PDT 24
Finished Mar 17 02:08:39 PM PDT 24
Peak memory 204908 kb
Host smart-de90b998-5b9a-415f-847a-7e6336fbe9bc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734795874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3734795874
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1252846012
Short name T827
Test name
Test status
Simulation time 6493184745 ps
CPU time 25.94 seconds
Started Mar 17 02:08:14 PM PDT 24
Finished Mar 17 02:08:40 PM PDT 24
Peak memory 204848 kb
Host smart-4732e4b2-af97-46dd-9c47-b8ef42a01219
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1252846012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1252846012
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.3176961891
Short name T675
Test name
Test status
Simulation time 185599658 ps
CPU time 4.44 seconds
Started Mar 17 02:08:13 PM PDT 24
Finished Mar 17 02:08:17 PM PDT 24
Peak memory 203712 kb
Host smart-90dfa4f8-b0e5-4591-ac92-c6638d28dc19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3176961891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3176961891
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2145721151
Short name T554
Test name
Test status
Simulation time 8767013438 ps
CPU time 30.12 seconds
Started Mar 17 02:08:15 PM PDT 24
Finished Mar 17 02:08:45 PM PDT 24
Peak memory 203788 kb
Host smart-c2b3ea8e-ee83-4d92-8dac-b1b719e71c9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145721151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2145721151
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.556240398
Short name T845
Test name
Test status
Simulation time 4057833418 ps
CPU time 29.64 seconds
Started Mar 17 02:08:17 PM PDT 24
Finished Mar 17 02:08:46 PM PDT 24
Peak memory 203692 kb
Host smart-f74280bd-de9d-4125-94d1-ebe20fe54b9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=556240398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.556240398
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1493942112
Short name T491
Test name
Test status
Simulation time 94362837 ps
CPU time 2.25 seconds
Started Mar 17 02:08:16 PM PDT 24
Finished Mar 17 02:08:19 PM PDT 24
Peak memory 203628 kb
Host smart-5736944e-fbad-4417-942b-824e7976fa33
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493942112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1493942112
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3180928368
Short name T475
Test name
Test status
Simulation time 54201802 ps
CPU time 4.1 seconds
Started Mar 17 02:08:23 PM PDT 24
Finished Mar 17 02:08:27 PM PDT 24
Peak memory 203872 kb
Host smart-676d49b3-878f-4848-9eb3-63dbd1db92da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3180928368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3180928368
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.4191396582
Short name T325
Test name
Test status
Simulation time 15958867876 ps
CPU time 204.59 seconds
Started Mar 17 02:08:26 PM PDT 24
Finished Mar 17 02:11:51 PM PDT 24
Peak memory 208560 kb
Host smart-2b255601-388d-4b01-8172-68daea9133e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4191396582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.4191396582
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.224336549
Short name T208
Test name
Test status
Simulation time 4942590828 ps
CPU time 204.33 seconds
Started Mar 17 02:08:29 PM PDT 24
Finished Mar 17 02:11:53 PM PDT 24
Peak memory 209908 kb
Host smart-f05b3203-be93-4a63-ba39-1459ae0484b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=224336549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand
_reset.224336549
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1605589637
Short name T541
Test name
Test status
Simulation time 4609831047 ps
CPU time 156.75 seconds
Started Mar 17 02:08:27 PM PDT 24
Finished Mar 17 02:11:04 PM PDT 24
Peak memory 211080 kb
Host smart-a9553e28-5dce-4a55-b190-6c1e67e39a87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1605589637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.1605589637
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3830265653
Short name T453
Test name
Test status
Simulation time 76144024 ps
CPU time 5.12 seconds
Started Mar 17 02:08:23 PM PDT 24
Finished Mar 17 02:08:28 PM PDT 24
Peak memory 211900 kb
Host smart-e170198f-3ecb-49e4-b4f4-6ba1b52f74f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3830265653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3830265653
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3901199080
Short name T605
Test name
Test status
Simulation time 355272084 ps
CPU time 52.28 seconds
Started Mar 17 02:01:48 PM PDT 24
Finished Mar 17 02:02:41 PM PDT 24
Peak memory 206476 kb
Host smart-8d62a7da-bc5c-4d5d-9347-6422d38a4119
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3901199080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3901199080
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.471744868
Short name T635
Test name
Test status
Simulation time 53748176556 ps
CPU time 272.45 seconds
Started Mar 17 02:01:50 PM PDT 24
Finished Mar 17 02:06:24 PM PDT 24
Peak memory 211960 kb
Host smart-06b6494e-f1d0-47b3-a32f-de63e502e947
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=471744868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow
_rsp.471744868
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2187713817
Short name T308
Test name
Test status
Simulation time 40460366 ps
CPU time 2.14 seconds
Started Mar 17 02:01:49 PM PDT 24
Finished Mar 17 02:01:52 PM PDT 24
Peak memory 203700 kb
Host smart-13522613-1287-4009-b4d2-c0ef4f275a1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2187713817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2187713817
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.3988429014
Short name T19
Test name
Test status
Simulation time 2028378649 ps
CPU time 16.02 seconds
Started Mar 17 02:01:51 PM PDT 24
Finished Mar 17 02:02:08 PM PDT 24
Peak memory 203604 kb
Host smart-b868bc64-337b-464f-a71a-17760410da72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3988429014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3988429014
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.3731118044
Short name T38
Test name
Test status
Simulation time 771467840 ps
CPU time 25.52 seconds
Started Mar 17 02:01:49 PM PDT 24
Finished Mar 17 02:02:15 PM PDT 24
Peak memory 204728 kb
Host smart-e2322b44-fb0a-47c6-a9a8-1b71c5318922
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3731118044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3731118044
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3386293105
Short name T190
Test name
Test status
Simulation time 50336534998 ps
CPU time 215.65 seconds
Started Mar 17 02:01:51 PM PDT 24
Finished Mar 17 02:05:29 PM PDT 24
Peak memory 211976 kb
Host smart-8943ea88-6088-4198-8eca-ee740376d703
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386293105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3386293105
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.379530085
Short name T332
Test name
Test status
Simulation time 34763841416 ps
CPU time 287.26 seconds
Started Mar 17 02:01:49 PM PDT 24
Finished Mar 17 02:06:37 PM PDT 24
Peak memory 205308 kb
Host smart-44c58eed-de24-4cf5-a244-f4d0acb0e205
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=379530085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.379530085
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3597699887
Short name T504
Test name
Test status
Simulation time 675804258 ps
CPU time 26.34 seconds
Started Mar 17 02:01:47 PM PDT 24
Finished Mar 17 02:02:15 PM PDT 24
Peak memory 204908 kb
Host smart-1143c5bd-0f7c-48aa-b9ed-ab7efe01c66b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597699887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3597699887
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.2596792245
Short name T181
Test name
Test status
Simulation time 100287920 ps
CPU time 8.69 seconds
Started Mar 17 02:01:51 PM PDT 24
Finished Mar 17 02:02:00 PM PDT 24
Peak memory 204156 kb
Host smart-00c84db6-a2f1-4648-8982-9d8026965805
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2596792245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2596792245
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.3352803254
Short name T629
Test name
Test status
Simulation time 114149664 ps
CPU time 3.45 seconds
Started Mar 17 02:01:51 PM PDT 24
Finished Mar 17 02:01:56 PM PDT 24
Peak memory 203644 kb
Host smart-cbba954b-a487-4dc5-9b68-3e8da45bbd63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3352803254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3352803254
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2440428949
Short name T221
Test name
Test status
Simulation time 25637709267 ps
CPU time 31.69 seconds
Started Mar 17 02:01:47 PM PDT 24
Finished Mar 17 02:02:20 PM PDT 24
Peak memory 203800 kb
Host smart-44405596-0f34-49d9-96e0-183f03c7b9d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440428949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2440428949
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1332678313
Short name T888
Test name
Test status
Simulation time 4791490426 ps
CPU time 29.37 seconds
Started Mar 17 02:01:48 PM PDT 24
Finished Mar 17 02:02:18 PM PDT 24
Peak memory 203688 kb
Host smart-db61afa0-78df-4afb-a28e-2ffe218c2534
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1332678313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1332678313
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.613216432
Short name T460
Test name
Test status
Simulation time 77889639 ps
CPU time 2.16 seconds
Started Mar 17 02:01:50 PM PDT 24
Finished Mar 17 02:01:53 PM PDT 24
Peak memory 203696 kb
Host smart-c1118f11-dbb9-44d1-93d7-24bcfd28b47d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613216432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.613216432
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1065706205
Short name T94
Test name
Test status
Simulation time 6494891270 ps
CPU time 169.04 seconds
Started Mar 17 02:01:50 PM PDT 24
Finished Mar 17 02:04:40 PM PDT 24
Peak memory 207944 kb
Host smart-30d048f0-44dd-4b47-a575-941c3924a852
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1065706205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1065706205
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.306067106
Short name T14
Test name
Test status
Simulation time 390159734 ps
CPU time 44.52 seconds
Started Mar 17 02:01:51 PM PDT 24
Finished Mar 17 02:02:36 PM PDT 24
Peak memory 205740 kb
Host smart-0b156a10-ed1b-4a2b-ba03-fab291c705b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=306067106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.306067106
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3278779379
Short name T213
Test name
Test status
Simulation time 9241079252 ps
CPU time 258.78 seconds
Started Mar 17 02:01:48 PM PDT 24
Finished Mar 17 02:06:07 PM PDT 24
Peak memory 220128 kb
Host smart-7f72228c-91e7-4570-ad95-1a2820ddd0bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3278779379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.3278779379
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.670662155
Short name T227
Test name
Test status
Simulation time 202343582 ps
CPU time 12.77 seconds
Started Mar 17 02:01:49 PM PDT 24
Finished Mar 17 02:02:02 PM PDT 24
Peak memory 211924 kb
Host smart-6853dcad-e0d1-4c57-9c23-13fc47e48a9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=670662155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.670662155
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1182265561
Short name T551
Test name
Test status
Simulation time 1136269180 ps
CPU time 33.29 seconds
Started Mar 17 02:08:32 PM PDT 24
Finished Mar 17 02:09:05 PM PDT 24
Peak memory 206008 kb
Host smart-8e78dfa5-b332-49ea-9c13-2d73916e5d8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1182265561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1182265561
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3884072932
Short name T146
Test name
Test status
Simulation time 46837431163 ps
CPU time 119.76 seconds
Started Mar 17 02:08:38 PM PDT 24
Finished Mar 17 02:10:39 PM PDT 24
Peak memory 206068 kb
Host smart-cce390f4-185f-4eaf-a0dc-a9ae8e98c248
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3884072932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.3884072932
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3257165687
Short name T717
Test name
Test status
Simulation time 16198919 ps
CPU time 1.88 seconds
Started Mar 17 02:08:40 PM PDT 24
Finished Mar 17 02:08:42 PM PDT 24
Peak memory 203716 kb
Host smart-50d32ad9-b54b-4555-956c-9b3ded7d0b80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3257165687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3257165687
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.3437497984
Short name T528
Test name
Test status
Simulation time 108278003 ps
CPU time 11.3 seconds
Started Mar 17 02:08:41 PM PDT 24
Finished Mar 17 02:08:52 PM PDT 24
Peak memory 203672 kb
Host smart-ba00beff-bf00-4fdc-8fc9-2a17c4514f44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437497984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3437497984
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.467065507
Short name T230
Test name
Test status
Simulation time 79072059 ps
CPU time 5.48 seconds
Started Mar 17 02:08:26 PM PDT 24
Finished Mar 17 02:08:32 PM PDT 24
Peak memory 203712 kb
Host smart-03226c62-c1f7-4f67-a616-12339671111c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=467065507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.467065507
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2254011061
Short name T472
Test name
Test status
Simulation time 18918027775 ps
CPU time 98.44 seconds
Started Mar 17 02:08:29 PM PDT 24
Finished Mar 17 02:10:08 PM PDT 24
Peak memory 211932 kb
Host smart-b7c91bfe-19c3-45cd-91b0-ee1a8ccd83bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254011061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2254011061
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1114731102
Short name T122
Test name
Test status
Simulation time 15308844333 ps
CPU time 107.4 seconds
Started Mar 17 02:08:31 PM PDT 24
Finished Mar 17 02:10:19 PM PDT 24
Peak memory 204992 kb
Host smart-44944584-4864-4aca-80e6-40e8dc951f47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1114731102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1114731102
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.464715518
Short name T673
Test name
Test status
Simulation time 42819139 ps
CPU time 8.56 seconds
Started Mar 17 02:08:26 PM PDT 24
Finished Mar 17 02:08:35 PM PDT 24
Peak memory 204864 kb
Host smart-ec1ced88-06c2-4e5a-95f6-ce18ad06c36c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464715518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.464715518
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.1293196994
Short name T408
Test name
Test status
Simulation time 349630177 ps
CPU time 22.02 seconds
Started Mar 17 02:08:39 PM PDT 24
Finished Mar 17 02:09:01 PM PDT 24
Peak memory 204320 kb
Host smart-8b51d299-b24f-4ae3-a1f0-6ddb830cdb69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1293196994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1293196994
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.19441140
Short name T291
Test name
Test status
Simulation time 146128391 ps
CPU time 2.85 seconds
Started Mar 17 02:08:26 PM PDT 24
Finished Mar 17 02:08:29 PM PDT 24
Peak memory 203700 kb
Host smart-b6a8059d-8c5b-4723-b7be-f178ab88e957
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19441140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.19441140
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1535597997
Short name T819
Test name
Test status
Simulation time 6786786027 ps
CPU time 31.24 seconds
Started Mar 17 02:08:27 PM PDT 24
Finished Mar 17 02:08:59 PM PDT 24
Peak memory 203748 kb
Host smart-e0666525-e771-472b-b557-7dcd52edc25c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535597997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1535597997
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1044503241
Short name T387
Test name
Test status
Simulation time 4161596339 ps
CPU time 31.17 seconds
Started Mar 17 02:08:26 PM PDT 24
Finished Mar 17 02:08:57 PM PDT 24
Peak memory 203756 kb
Host smart-186f3482-81b8-4e20-8213-b3e9ba3d29f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1044503241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1044503241
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3524424986
Short name T378
Test name
Test status
Simulation time 80287483 ps
CPU time 2.26 seconds
Started Mar 17 02:08:28 PM PDT 24
Finished Mar 17 02:08:30 PM PDT 24
Peak memory 203640 kb
Host smart-7544e212-7822-4d47-b729-8dbfa6128204
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524424986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3524424986
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2778247391
Short name T81
Test name
Test status
Simulation time 3490778890 ps
CPU time 67.67 seconds
Started Mar 17 02:08:39 PM PDT 24
Finished Mar 17 02:09:47 PM PDT 24
Peak memory 207548 kb
Host smart-0b4e9960-28fc-4e23-a845-30808164229e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2778247391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2778247391
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.278594252
Short name T464
Test name
Test status
Simulation time 1624589504 ps
CPU time 121.63 seconds
Started Mar 17 02:08:40 PM PDT 24
Finished Mar 17 02:10:42 PM PDT 24
Peak memory 207380 kb
Host smart-4ff575de-62a4-4988-aff6-a1d11aee70f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=278594252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.278594252
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1322614221
Short name T373
Test name
Test status
Simulation time 4309628455 ps
CPU time 344.73 seconds
Started Mar 17 02:08:39 PM PDT 24
Finished Mar 17 02:14:25 PM PDT 24
Peak memory 209760 kb
Host smart-bd7b446e-3556-42c8-bf29-5ab00e399aa0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1322614221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.1322614221
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1303088829
Short name T244
Test name
Test status
Simulation time 1603155309 ps
CPU time 205.66 seconds
Started Mar 17 02:08:39 PM PDT 24
Finished Mar 17 02:12:05 PM PDT 24
Peak memory 210196 kb
Host smart-2c5c92ce-7777-4dfd-acfc-3509e6622b76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1303088829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.1303088829
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1651194094
Short name T779
Test name
Test status
Simulation time 118251723 ps
CPU time 23.56 seconds
Started Mar 17 02:08:38 PM PDT 24
Finished Mar 17 02:09:02 PM PDT 24
Peak memory 211900 kb
Host smart-b73b504e-eaef-4c1b-828c-bda86ef29f12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1651194094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1651194094
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.144588432
Short name T646
Test name
Test status
Simulation time 2468285954 ps
CPU time 58.76 seconds
Started Mar 17 02:08:46 PM PDT 24
Finished Mar 17 02:09:45 PM PDT 24
Peak memory 206440 kb
Host smart-ba46315b-721d-45d8-b117-d386af91a001
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=144588432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.144588432
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.135000924
Short name T738
Test name
Test status
Simulation time 57208845826 ps
CPU time 211.82 seconds
Started Mar 17 02:08:53 PM PDT 24
Finished Mar 17 02:12:25 PM PDT 24
Peak memory 211952 kb
Host smart-83a5a899-646a-4d32-9f6e-47ab397d4a6d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=135000924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo
w_rsp.135000924
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1584674364
Short name T862
Test name
Test status
Simulation time 706120402 ps
CPU time 25.25 seconds
Started Mar 17 02:08:51 PM PDT 24
Finished Mar 17 02:09:16 PM PDT 24
Peak memory 203700 kb
Host smart-eb535ff7-f174-479b-b990-66bde30e85f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1584674364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1584674364
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.3885646303
Short name T293
Test name
Test status
Simulation time 2528375418 ps
CPU time 20.87 seconds
Started Mar 17 02:08:50 PM PDT 24
Finished Mar 17 02:09:12 PM PDT 24
Peak memory 203744 kb
Host smart-e28cc202-2c06-4004-8f6f-c62cdd8e143b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3885646303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3885646303
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.1543253954
Short name T602
Test name
Test status
Simulation time 46461824 ps
CPU time 5.06 seconds
Started Mar 17 02:08:45 PM PDT 24
Finished Mar 17 02:08:50 PM PDT 24
Peak memory 204204 kb
Host smart-ec50ec44-7c80-4ab5-b56b-35e6b763325d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1543253954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1543253954
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.4223334553
Short name T365
Test name
Test status
Simulation time 4513376111 ps
CPU time 24.55 seconds
Started Mar 17 02:08:48 PM PDT 24
Finished Mar 17 02:09:13 PM PDT 24
Peak memory 204596 kb
Host smart-249a0103-97e3-467b-a0ce-dbf03989cda4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223334553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4223334553
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3817046315
Short name T493
Test name
Test status
Simulation time 2785791232 ps
CPU time 12.61 seconds
Started Mar 17 02:08:47 PM PDT 24
Finished Mar 17 02:09:00 PM PDT 24
Peak memory 203836 kb
Host smart-998994fa-2c00-4444-b81b-2f8f3fa67822
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3817046315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3817046315
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1499685497
Short name T347
Test name
Test status
Simulation time 138642307 ps
CPU time 23.36 seconds
Started Mar 17 02:08:45 PM PDT 24
Finished Mar 17 02:09:08 PM PDT 24
Peak memory 204740 kb
Host smart-e2abd816-e53c-4577-949a-a235d4611718
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499685497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1499685497
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.4266328864
Short name T412
Test name
Test status
Simulation time 170967628 ps
CPU time 14.16 seconds
Started Mar 17 02:08:52 PM PDT 24
Finished Mar 17 02:09:06 PM PDT 24
Peak memory 204304 kb
Host smart-8e188bef-94ac-4ac6-b44c-5d87509d8cdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4266328864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4266328864
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.3805424460
Short name T39
Test name
Test status
Simulation time 33637024 ps
CPU time 2.16 seconds
Started Mar 17 02:08:40 PM PDT 24
Finished Mar 17 02:08:42 PM PDT 24
Peak memory 203672 kb
Host smart-cecf966b-741a-45c6-8b66-f1d0f51b76df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3805424460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3805424460
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1844848195
Short name T764
Test name
Test status
Simulation time 5716944584 ps
CPU time 33.13 seconds
Started Mar 17 02:08:41 PM PDT 24
Finished Mar 17 02:09:14 PM PDT 24
Peak memory 203732 kb
Host smart-487c1f74-225b-4ccd-8780-78a25c384f33
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844848195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1844848195
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.171580271
Short name T339
Test name
Test status
Simulation time 3290775337 ps
CPU time 29.4 seconds
Started Mar 17 02:08:40 PM PDT 24
Finished Mar 17 02:09:10 PM PDT 24
Peak memory 203800 kb
Host smart-5e06f42c-fad4-41d1-bcbe-a4ca0cc6083a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=171580271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.171580271
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2716896654
Short name T808
Test name
Test status
Simulation time 43343991 ps
CPU time 2.53 seconds
Started Mar 17 02:08:37 PM PDT 24
Finished Mar 17 02:08:40 PM PDT 24
Peak memory 203756 kb
Host smart-67934177-c951-4861-959d-0fd0508c4c50
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716896654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2716896654
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3938582829
Short name T473
Test name
Test status
Simulation time 9236522974 ps
CPU time 241.87 seconds
Started Mar 17 02:08:51 PM PDT 24
Finished Mar 17 02:12:53 PM PDT 24
Peak memory 210568 kb
Host smart-4c69cc51-d89b-4894-bbcb-155be3239ba0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3938582829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3938582829
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.69498029
Short name T697
Test name
Test status
Simulation time 388721598 ps
CPU time 57.51 seconds
Started Mar 17 02:08:50 PM PDT 24
Finished Mar 17 02:09:49 PM PDT 24
Peak memory 205240 kb
Host smart-790386d2-23bd-4bad-a7b0-5a67de85e218
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69498029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.69498029
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2172712751
Short name T188
Test name
Test status
Simulation time 614102560 ps
CPU time 195.24 seconds
Started Mar 17 02:08:51 PM PDT 24
Finished Mar 17 02:12:06 PM PDT 24
Peak memory 208712 kb
Host smart-d23a73c9-4d20-4ed8-b12e-36ce78f0a448
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2172712751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.2172712751
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1637468319
Short name T741
Test name
Test status
Simulation time 900248747 ps
CPU time 170.59 seconds
Started Mar 17 02:08:50 PM PDT 24
Finished Mar 17 02:11:41 PM PDT 24
Peak memory 220032 kb
Host smart-0253448a-74a9-41bf-a272-e3a254a60c9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1637468319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.1637468319
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4056300612
Short name T900
Test name
Test status
Simulation time 835806327 ps
CPU time 26.4 seconds
Started Mar 17 02:08:54 PM PDT 24
Finished Mar 17 02:09:21 PM PDT 24
Peak memory 205112 kb
Host smart-a3193bd3-8782-4ce2-bc42-03e8f2bae124
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4056300612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4056300612
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.941159094
Short name T305
Test name
Test status
Simulation time 785319197 ps
CPU time 46.24 seconds
Started Mar 17 02:08:57 PM PDT 24
Finished Mar 17 02:09:43 PM PDT 24
Peak memory 211896 kb
Host smart-279d8b39-7dc1-444b-ab00-5086f8003fb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=941159094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.941159094
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3775391918
Short name T106
Test name
Test status
Simulation time 85361372348 ps
CPU time 409.67 seconds
Started Mar 17 02:08:57 PM PDT 24
Finished Mar 17 02:15:47 PM PDT 24
Peak memory 206148 kb
Host smart-e663aa84-7bc3-440b-ae2e-5673dc17f00b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3775391918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.3775391918
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2825718254
Short name T28
Test name
Test status
Simulation time 1631559290 ps
CPU time 25.03 seconds
Started Mar 17 02:09:02 PM PDT 24
Finished Mar 17 02:09:27 PM PDT 24
Peak memory 203700 kb
Host smart-c2f5592b-0b32-4be2-a319-7ed783080b16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2825718254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2825718254
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.2077160524
Short name T259
Test name
Test status
Simulation time 1158412122 ps
CPU time 39.27 seconds
Started Mar 17 02:09:02 PM PDT 24
Finished Mar 17 02:09:42 PM PDT 24
Peak memory 203884 kb
Host smart-dcf9a7dd-0884-4eb9-9c3d-63d07724d1ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2077160524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2077160524
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.2617134420
Short name T667
Test name
Test status
Simulation time 215271900 ps
CPU time 32.25 seconds
Started Mar 17 02:08:56 PM PDT 24
Finished Mar 17 02:09:28 PM PDT 24
Peak memory 205076 kb
Host smart-bee4fbd9-4501-4007-84b0-9fca43580244
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2617134420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2617134420
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1138087470
Short name T815
Test name
Test status
Simulation time 16429169672 ps
CPU time 44.51 seconds
Started Mar 17 02:08:57 PM PDT 24
Finished Mar 17 02:09:42 PM PDT 24
Peak memory 204848 kb
Host smart-9453f0ea-822d-4d1d-ba90-7e88e824079d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138087470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1138087470
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3040428229
Short name T560
Test name
Test status
Simulation time 77635443476 ps
CPU time 244.38 seconds
Started Mar 17 02:08:58 PM PDT 24
Finished Mar 17 02:13:03 PM PDT 24
Peak memory 211952 kb
Host smart-e397d68f-f67f-43d0-8033-14e3a65e511d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3040428229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3040428229
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3274409662
Short name T482
Test name
Test status
Simulation time 241008321 ps
CPU time 10.4 seconds
Started Mar 17 02:08:57 PM PDT 24
Finished Mar 17 02:09:07 PM PDT 24
Peak memory 204812 kb
Host smart-639322cd-1a57-4819-85d7-86f67355ca17
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274409662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3274409662
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.1355396214
Short name T110
Test name
Test status
Simulation time 2092902639 ps
CPU time 30.28 seconds
Started Mar 17 02:09:03 PM PDT 24
Finished Mar 17 02:09:34 PM PDT 24
Peak memory 204148 kb
Host smart-c4ff9fc3-6b76-4e8c-8d9e-4c597ed8d523
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1355396214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1355396214
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.3566705925
Short name T36
Test name
Test status
Simulation time 190288247 ps
CPU time 3.88 seconds
Started Mar 17 02:08:51 PM PDT 24
Finished Mar 17 02:08:55 PM PDT 24
Peak memory 203632 kb
Host smart-b20ebe78-c2b5-48bf-8e01-90f92059bf2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3566705925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3566705925
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3223643790
Short name T842
Test name
Test status
Simulation time 13032006544 ps
CPU time 30.39 seconds
Started Mar 17 02:08:51 PM PDT 24
Finished Mar 17 02:09:22 PM PDT 24
Peak memory 203740 kb
Host smart-9db1cd24-4554-4cb6-9e54-2caf8f8c40c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223643790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3223643790
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1012291210
Short name T260
Test name
Test status
Simulation time 3151979526 ps
CPU time 27.49 seconds
Started Mar 17 02:08:54 PM PDT 24
Finished Mar 17 02:09:22 PM PDT 24
Peak memory 203756 kb
Host smart-6c897a49-fe1c-43b4-8608-997224992dd3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1012291210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1012291210
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2988499908
Short name T732
Test name
Test status
Simulation time 100386694 ps
CPU time 2.29 seconds
Started Mar 17 02:08:51 PM PDT 24
Finished Mar 17 02:08:53 PM PDT 24
Peak memory 203736 kb
Host smart-c0fc4027-d097-41f3-90d7-4e409d345134
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988499908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2988499908
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.553360133
Short name T82
Test name
Test status
Simulation time 7835898677 ps
CPU time 178.97 seconds
Started Mar 17 02:09:07 PM PDT 24
Finished Mar 17 02:12:06 PM PDT 24
Peak memory 207628 kb
Host smart-1ad2361c-737b-44b7-b8be-564c4e9df6e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=553360133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.553360133
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2302831048
Short name T296
Test name
Test status
Simulation time 747529360 ps
CPU time 85.38 seconds
Started Mar 17 02:09:02 PM PDT 24
Finished Mar 17 02:10:28 PM PDT 24
Peak memory 208244 kb
Host smart-cb4b94c2-29ac-4462-a4af-385411d20b50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2302831048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2302831048
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2915548539
Short name T172
Test name
Test status
Simulation time 3312158978 ps
CPU time 280.26 seconds
Started Mar 17 02:09:05 PM PDT 24
Finished Mar 17 02:13:46 PM PDT 24
Peak memory 210152 kb
Host smart-d529c229-0835-4daf-9f3a-b98ca8a2f9a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2915548539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.2915548539
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.40368833
Short name T712
Test name
Test status
Simulation time 60754224 ps
CPU time 12.67 seconds
Started Mar 17 02:09:05 PM PDT 24
Finished Mar 17 02:09:18 PM PDT 24
Peak memory 205172 kb
Host smart-416f189e-4783-4b97-9a6e-be404a40532d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40368833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rese
t_error.40368833
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2542960229
Short name T57
Test name
Test status
Simulation time 1382926450 ps
CPU time 32.79 seconds
Started Mar 17 02:09:03 PM PDT 24
Finished Mar 17 02:09:36 PM PDT 24
Peak memory 205284 kb
Host smart-1f173e8b-3f76-443f-973c-4fb3b25b017c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2542960229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2542960229
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1913559502
Short name T98
Test name
Test status
Simulation time 2550603410 ps
CPU time 45.15 seconds
Started Mar 17 02:09:16 PM PDT 24
Finished Mar 17 02:10:01 PM PDT 24
Peak memory 211952 kb
Host smart-149539ca-5d9d-46d3-a942-176541fa896c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1913559502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1913559502
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.689432814
Short name T896
Test name
Test status
Simulation time 136428513484 ps
CPU time 421.56 seconds
Started Mar 17 02:09:14 PM PDT 24
Finished Mar 17 02:16:15 PM PDT 24
Peak memory 206900 kb
Host smart-19579516-6e04-4d4d-9a0e-fa9f273d14ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=689432814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo
w_rsp.689432814
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3198709812
Short name T228
Test name
Test status
Simulation time 642530103 ps
CPU time 13.07 seconds
Started Mar 17 02:09:17 PM PDT 24
Finished Mar 17 02:09:30 PM PDT 24
Peak memory 203912 kb
Host smart-ec2c8e98-8fb1-4563-8f4a-8204ca2a1408
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3198709812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3198709812
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.1320096504
Short name T284
Test name
Test status
Simulation time 1254892343 ps
CPU time 18.07 seconds
Started Mar 17 02:09:14 PM PDT 24
Finished Mar 17 02:09:33 PM PDT 24
Peak memory 203684 kb
Host smart-db282c28-abc3-4ac4-9351-24110f6cd066
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1320096504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1320096504
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.3919436067
Short name T43
Test name
Test status
Simulation time 408226288 ps
CPU time 19.02 seconds
Started Mar 17 02:09:07 PM PDT 24
Finished Mar 17 02:09:26 PM PDT 24
Peak memory 204812 kb
Host smart-cb7d65fe-d567-498a-a0f3-77e6598a0adb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3919436067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3919436067
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2573228450
Short name T407
Test name
Test status
Simulation time 31197331645 ps
CPU time 195.86 seconds
Started Mar 17 02:09:07 PM PDT 24
Finished Mar 17 02:12:23 PM PDT 24
Peak memory 205000 kb
Host smart-b23c99c1-54b1-4324-a198-e7f29801c3e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573228450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2573228450
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1152705030
Short name T651
Test name
Test status
Simulation time 10573841468 ps
CPU time 88.13 seconds
Started Mar 17 02:09:07 PM PDT 24
Finished Mar 17 02:10:35 PM PDT 24
Peak memory 205100 kb
Host smart-30422e74-7b96-4063-a744-6480ded6fed4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1152705030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1152705030
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2359020346
Short name T776
Test name
Test status
Simulation time 114224817 ps
CPU time 17.32 seconds
Started Mar 17 02:09:07 PM PDT 24
Finished Mar 17 02:09:25 PM PDT 24
Peak memory 204756 kb
Host smart-50638393-8d81-41ef-80f9-d4f16ebdbb73
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359020346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2359020346
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.774024406
Short name T248
Test name
Test status
Simulation time 30832185 ps
CPU time 2.83 seconds
Started Mar 17 02:09:14 PM PDT 24
Finished Mar 17 02:09:17 PM PDT 24
Peak memory 203608 kb
Host smart-66a28bc1-7861-42eb-9af2-2b6be61af553
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=774024406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.774024406
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.2714820991
Short name T113
Test name
Test status
Simulation time 529578469 ps
CPU time 3.62 seconds
Started Mar 17 02:09:09 PM PDT 24
Finished Mar 17 02:09:13 PM PDT 24
Peak memory 203676 kb
Host smart-68627eb6-32d4-4c57-9aeb-781510dd5bb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2714820991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2714820991
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3495662203
Short name T830
Test name
Test status
Simulation time 5632465014 ps
CPU time 25.01 seconds
Started Mar 17 02:09:06 PM PDT 24
Finished Mar 17 02:09:32 PM PDT 24
Peak memory 203796 kb
Host smart-f49a8f7c-7500-48ee-931e-0498a572a5e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495662203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3495662203
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3376369321
Short name T549
Test name
Test status
Simulation time 4170182672 ps
CPU time 30.84 seconds
Started Mar 17 02:09:07 PM PDT 24
Finished Mar 17 02:09:38 PM PDT 24
Peak memory 203788 kb
Host smart-84801131-b5d9-4662-ab0b-e33e6b51534e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3376369321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3376369321
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.4148672714
Short name T672
Test name
Test status
Simulation time 31582129 ps
CPU time 2.36 seconds
Started Mar 17 02:09:07 PM PDT 24
Finished Mar 17 02:09:10 PM PDT 24
Peak memory 203632 kb
Host smart-7c2475a5-f664-4002-9b69-681b7535817f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148672714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4148672714
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2680034502
Short name T662
Test name
Test status
Simulation time 1094614438 ps
CPU time 80.55 seconds
Started Mar 17 02:09:14 PM PDT 24
Finished Mar 17 02:10:35 PM PDT 24
Peak memory 208172 kb
Host smart-143520a2-79d5-458a-b9ad-8715849d1e88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2680034502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2680034502
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.4115425310
Short name T496
Test name
Test status
Simulation time 7735781185 ps
CPU time 208.89 seconds
Started Mar 17 02:09:14 PM PDT 24
Finished Mar 17 02:12:43 PM PDT 24
Peak memory 207124 kb
Host smart-1fd41d61-5a4b-4a5c-8e4d-4c362b9fa0a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115425310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4115425310
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1230310559
Short name T7
Test name
Test status
Simulation time 512470096 ps
CPU time 155.2 seconds
Started Mar 17 02:09:17 PM PDT 24
Finished Mar 17 02:11:52 PM PDT 24
Peak memory 208652 kb
Host smart-e2fc263f-2bd3-401a-8743-e58bc6b7b9c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1230310559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1230310559
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3473186335
Short name T466
Test name
Test status
Simulation time 221874280 ps
CPU time 51.2 seconds
Started Mar 17 02:09:19 PM PDT 24
Finished Mar 17 02:10:10 PM PDT 24
Peak memory 207144 kb
Host smart-b7009159-fdf1-40d8-840c-6b2bc2609d5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3473186335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.3473186335
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3630456888
Short name T834
Test name
Test status
Simulation time 113483954 ps
CPU time 15.79 seconds
Started Mar 17 02:09:17 PM PDT 24
Finished Mar 17 02:09:33 PM PDT 24
Peak memory 205268 kb
Host smart-07e802e8-d156-45fe-aaec-445ea07dc5c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3630456888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3630456888
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.4141151922
Short name T624
Test name
Test status
Simulation time 148746393 ps
CPU time 4.75 seconds
Started Mar 17 02:09:26 PM PDT 24
Finished Mar 17 02:09:30 PM PDT 24
Peak memory 203680 kb
Host smart-df183054-4c6a-4b46-a1fc-f31a4fb46a1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4141151922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.4141151922
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.27767451
Short name T143
Test name
Test status
Simulation time 30578557397 ps
CPU time 246.57 seconds
Started Mar 17 02:09:27 PM PDT 24
Finished Mar 17 02:13:34 PM PDT 24
Peak memory 206280 kb
Host smart-daccbeb9-25bd-489c-b88e-fc21278ffaf6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=27767451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow
_rsp.27767451
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4191429812
Short name T576
Test name
Test status
Simulation time 396904589 ps
CPU time 12.79 seconds
Started Mar 17 02:09:32 PM PDT 24
Finished Mar 17 02:09:44 PM PDT 24
Peak memory 203708 kb
Host smart-86b8bef5-080b-45eb-af4d-3115076e672b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4191429812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.4191429812
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.2357703713
Short name T224
Test name
Test status
Simulation time 171425633 ps
CPU time 5.56 seconds
Started Mar 17 02:09:32 PM PDT 24
Finished Mar 17 02:09:38 PM PDT 24
Peak memory 203676 kb
Host smart-8b71e03f-be27-40dd-ae55-baadf7e75b17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2357703713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2357703713
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.1772232961
Short name T350
Test name
Test status
Simulation time 123521703 ps
CPU time 6.12 seconds
Started Mar 17 02:09:20 PM PDT 24
Finished Mar 17 02:09:26 PM PDT 24
Peak memory 203732 kb
Host smart-9c2d74ff-1715-452c-8d52-dfb79e2f292a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1772232961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1772232961
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3970963762
Short name T872
Test name
Test status
Simulation time 57098551691 ps
CPU time 279.41 seconds
Started Mar 17 02:09:26 PM PDT 24
Finished Mar 17 02:14:06 PM PDT 24
Peak memory 205376 kb
Host smart-a0804e57-c51b-43bf-b579-5df882b3b295
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970963762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3970963762
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2761668042
Short name T650
Test name
Test status
Simulation time 45587152775 ps
CPU time 193.38 seconds
Started Mar 17 02:09:25 PM PDT 24
Finished Mar 17 02:12:39 PM PDT 24
Peak memory 212008 kb
Host smart-77ebc6ca-c60c-452c-ba13-a0bb7cf8f918
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2761668042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2761668042
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.183317033
Short name T279
Test name
Test status
Simulation time 57952022 ps
CPU time 8.22 seconds
Started Mar 17 02:09:20 PM PDT 24
Finished Mar 17 02:09:28 PM PDT 24
Peak memory 211856 kb
Host smart-f44c8297-6b9d-4e61-8812-6a764137eb85
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183317033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.183317033
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.2578628092
Short name T421
Test name
Test status
Simulation time 254718337 ps
CPU time 19.3 seconds
Started Mar 17 02:09:34 PM PDT 24
Finished Mar 17 02:09:53 PM PDT 24
Peak memory 203712 kb
Host smart-e2b7fb61-7c04-480f-a02a-1eb6a6b61ba4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2578628092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2578628092
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.2810176879
Short name T782
Test name
Test status
Simulation time 36764892 ps
CPU time 2.89 seconds
Started Mar 17 02:09:20 PM PDT 24
Finished Mar 17 02:09:23 PM PDT 24
Peak memory 203712 kb
Host smart-665aba8e-24fa-419d-aa1c-221833edaf9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2810176879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2810176879
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.4125898989
Short name T501
Test name
Test status
Simulation time 12138741692 ps
CPU time 35.79 seconds
Started Mar 17 02:09:19 PM PDT 24
Finished Mar 17 02:09:55 PM PDT 24
Peak memory 203792 kb
Host smart-bbae4086-8c03-4987-b984-6da607ba000c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125898989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4125898989
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3064697779
Short name T8
Test name
Test status
Simulation time 6411220940 ps
CPU time 32.29 seconds
Started Mar 17 02:09:20 PM PDT 24
Finished Mar 17 02:09:53 PM PDT 24
Peak memory 203768 kb
Host smart-b9f45c62-699b-4ac2-8ddf-0e3110bd39d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3064697779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3064697779
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1641466108
Short name T449
Test name
Test status
Simulation time 25089424 ps
CPU time 2.26 seconds
Started Mar 17 02:09:20 PM PDT 24
Finished Mar 17 02:09:22 PM PDT 24
Peak memory 203712 kb
Host smart-30c3bbbc-fa3f-40d4-9715-1732fb6e5b69
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641466108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1641466108
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1939862305
Short name T15
Test name
Test status
Simulation time 655379115 ps
CPU time 53.92 seconds
Started Mar 17 02:09:33 PM PDT 24
Finished Mar 17 02:10:27 PM PDT 24
Peak memory 207380 kb
Host smart-fb57634a-1b37-47de-b958-c45b50061aed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1939862305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1939862305
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1732916910
Short name T25
Test name
Test status
Simulation time 763620467 ps
CPU time 71.94 seconds
Started Mar 17 02:09:31 PM PDT 24
Finished Mar 17 02:10:44 PM PDT 24
Peak memory 206112 kb
Host smart-dae087c6-15af-4645-b987-abf653c82f13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1732916910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1732916910
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2562103301
Short name T129
Test name
Test status
Simulation time 4920923355 ps
CPU time 214.98 seconds
Started Mar 17 02:09:35 PM PDT 24
Finished Mar 17 02:13:10 PM PDT 24
Peak memory 208472 kb
Host smart-3026d8e1-f0d4-4042-aa88-36096a8668a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2562103301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.2562103301
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.4182236000
Short name T539
Test name
Test status
Simulation time 259983994 ps
CPU time 9.84 seconds
Started Mar 17 02:09:31 PM PDT 24
Finished Mar 17 02:09:41 PM PDT 24
Peak memory 205036 kb
Host smart-0c00d3d4-2448-4529-8bc6-c789cd6aa909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4182236000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.4182236000
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1143606912
Short name T41
Test name
Test status
Simulation time 583912576 ps
CPU time 26.4 seconds
Started Mar 17 02:09:36 PM PDT 24
Finished Mar 17 02:10:03 PM PDT 24
Peak memory 205476 kb
Host smart-9957c2e2-98c0-4e5b-a6eb-1c27c870c7f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1143606912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1143606912
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2772944997
Short name T456
Test name
Test status
Simulation time 148344223 ps
CPU time 15.58 seconds
Started Mar 17 02:09:47 PM PDT 24
Finished Mar 17 02:10:03 PM PDT 24
Peak memory 204220 kb
Host smart-535b20eb-6480-40c7-8d43-9f5afbae465c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2772944997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2772944997
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3746972567
Short name T281
Test name
Test status
Simulation time 162991309 ps
CPU time 6.88 seconds
Started Mar 17 02:09:44 PM PDT 24
Finished Mar 17 02:09:51 PM PDT 24
Peak memory 203732 kb
Host smart-c7559089-a4bd-499b-ad46-b1d959bde2d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3746972567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3746972567
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.2865661765
Short name T802
Test name
Test status
Simulation time 143686144 ps
CPU time 10.29 seconds
Started Mar 17 02:09:33 PM PDT 24
Finished Mar 17 02:09:43 PM PDT 24
Peak memory 211932 kb
Host smart-d6c8450f-8336-4ae6-be82-a407f5782015
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2865661765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2865661765
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1960015598
Short name T689
Test name
Test status
Simulation time 35827313257 ps
CPU time 132.31 seconds
Started Mar 17 02:09:38 PM PDT 24
Finished Mar 17 02:11:50 PM PDT 24
Peak memory 205304 kb
Host smart-cdfe0167-6aad-406f-8fd3-97141629ea34
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960015598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1960015598
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.53093248
Short name T55
Test name
Test status
Simulation time 13883581771 ps
CPU time 127.19 seconds
Started Mar 17 02:09:36 PM PDT 24
Finished Mar 17 02:11:43 PM PDT 24
Peak memory 204932 kb
Host smart-5d2fc344-f11b-4a16-94e1-d9d94efb5470
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=53093248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.53093248
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1541000295
Short name T309
Test name
Test status
Simulation time 183431984 ps
CPU time 24.69 seconds
Started Mar 17 02:09:37 PM PDT 24
Finished Mar 17 02:10:02 PM PDT 24
Peak memory 205000 kb
Host smart-be968d95-40bb-478b-b26c-7c376c88192c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541000295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1541000295
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.4085448224
Short name T633
Test name
Test status
Simulation time 3959029274 ps
CPU time 32.57 seconds
Started Mar 17 02:09:42 PM PDT 24
Finished Mar 17 02:10:15 PM PDT 24
Peak memory 204480 kb
Host smart-aa8d266a-9aae-42fb-8310-fe8ed1ae5a8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4085448224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4085448224
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.4249379549
Short name T546
Test name
Test status
Simulation time 177185652 ps
CPU time 4.39 seconds
Started Mar 17 02:09:34 PM PDT 24
Finished Mar 17 02:09:39 PM PDT 24
Peak memory 203696 kb
Host smart-222c1502-59f8-4e5d-a74f-3db00138539f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4249379549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.4249379549
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1170173076
Short name T666
Test name
Test status
Simulation time 4524132774 ps
CPU time 27.93 seconds
Started Mar 17 02:09:35 PM PDT 24
Finished Mar 17 02:10:03 PM PDT 24
Peak memory 203772 kb
Host smart-d9085d0b-208d-415f-817b-ca91a98aedd4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170173076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1170173076
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3954593454
Short name T849
Test name
Test status
Simulation time 8623673104 ps
CPU time 36.48 seconds
Started Mar 17 02:09:32 PM PDT 24
Finished Mar 17 02:10:09 PM PDT 24
Peak memory 203776 kb
Host smart-7a80b06a-ccae-431b-a6f6-c686d8eb5b65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3954593454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3954593454
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3808569904
Short name T755
Test name
Test status
Simulation time 28056680 ps
CPU time 2.22 seconds
Started Mar 17 02:09:33 PM PDT 24
Finished Mar 17 02:09:35 PM PDT 24
Peak memory 203640 kb
Host smart-1b95a642-09b5-4b8a-b72f-657305806ca3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808569904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3808569904
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1079805204
Short name T180
Test name
Test status
Simulation time 646041949 ps
CPU time 15.42 seconds
Started Mar 17 02:09:41 PM PDT 24
Finished Mar 17 02:09:57 PM PDT 24
Peak memory 205552 kb
Host smart-b14a777a-3ef9-4285-81ee-2df91a7da43f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1079805204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1079805204
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1143092394
Short name T804
Test name
Test status
Simulation time 12261063375 ps
CPU time 121.2 seconds
Started Mar 17 02:09:48 PM PDT 24
Finished Mar 17 02:11:49 PM PDT 24
Peak memory 205964 kb
Host smart-e987eab2-8d42-4a6a-97e8-6ca35e5f2460
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1143092394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1143092394
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2106549776
Short name T392
Test name
Test status
Simulation time 663474828 ps
CPU time 360.54 seconds
Started Mar 17 02:09:41 PM PDT 24
Finished Mar 17 02:15:42 PM PDT 24
Peak memory 208760 kb
Host smart-d9ba1c56-ba6e-43b9-8bb7-230cf3af7f58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2106549776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.2106549776
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2713895478
Short name T592
Test name
Test status
Simulation time 132298123 ps
CPU time 40.62 seconds
Started Mar 17 02:09:42 PM PDT 24
Finished Mar 17 02:10:23 PM PDT 24
Peak memory 207744 kb
Host smart-ba40f18e-63f2-4eae-a3ab-5937627c807a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2713895478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.2713895478
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.410142748
Short name T578
Test name
Test status
Simulation time 1061245291 ps
CPU time 39.78 seconds
Started Mar 17 02:09:43 PM PDT 24
Finished Mar 17 02:10:23 PM PDT 24
Peak memory 205548 kb
Host smart-571de53f-fa55-40c4-978e-49813055cad5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=410142748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.410142748
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2827172470
Short name T95
Test name
Test status
Simulation time 892634926 ps
CPU time 15.66 seconds
Started Mar 17 02:09:55 PM PDT 24
Finished Mar 17 02:10:11 PM PDT 24
Peak memory 204760 kb
Host smart-c056cfe8-b7d1-49a2-985d-12fe796e4d6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2827172470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2827172470
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.145342859
Short name T118
Test name
Test status
Simulation time 33017406800 ps
CPU time 192.59 seconds
Started Mar 17 02:09:49 PM PDT 24
Finished Mar 17 02:13:02 PM PDT 24
Peak memory 206580 kb
Host smart-ae4456ec-ce49-48de-bde5-4d291609f97a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=145342859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo
w_rsp.145342859
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2184916849
Short name T881
Test name
Test status
Simulation time 113285794 ps
CPU time 18.28 seconds
Started Mar 17 02:09:54 PM PDT 24
Finished Mar 17 02:10:12 PM PDT 24
Peak memory 204184 kb
Host smart-70ce5452-f72e-4779-9543-cb47dfd3a073
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2184916849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2184916849
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.1744267838
Short name T606
Test name
Test status
Simulation time 1113475346 ps
CPU time 26.84 seconds
Started Mar 17 02:09:50 PM PDT 24
Finished Mar 17 02:10:17 PM PDT 24
Peak memory 203692 kb
Host smart-92b9ffe9-6dbc-46ae-bec4-7853cd667193
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1744267838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1744267838
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.2045958708
Short name T127
Test name
Test status
Simulation time 1249646976 ps
CPU time 30.45 seconds
Started Mar 17 02:09:48 PM PDT 24
Finished Mar 17 02:10:19 PM PDT 24
Peak memory 211880 kb
Host smart-7ccd389d-a4a7-4b05-a814-4fbd437315fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2045958708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2045958708
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3924798991
Short name T796
Test name
Test status
Simulation time 114231464486 ps
CPU time 235.86 seconds
Started Mar 17 02:09:49 PM PDT 24
Finished Mar 17 02:13:45 PM PDT 24
Peak memory 205368 kb
Host smart-150e962b-b616-4557-8aaa-c748107d3763
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924798991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3924798991
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.485525781
Short name T698
Test name
Test status
Simulation time 32313082908 ps
CPU time 223.52 seconds
Started Mar 17 02:09:55 PM PDT 24
Finished Mar 17 02:13:38 PM PDT 24
Peak memory 205488 kb
Host smart-1e7ea1fa-ed8c-41ae-8bfe-6785e9b87291
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=485525781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.485525781
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1683534450
Short name T874
Test name
Test status
Simulation time 434781869 ps
CPU time 22.3 seconds
Started Mar 17 02:09:48 PM PDT 24
Finished Mar 17 02:10:10 PM PDT 24
Peak memory 204812 kb
Host smart-82344929-784e-4343-beec-6da811069526
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683534450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1683534450
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.225123858
Short name T234
Test name
Test status
Simulation time 138535273 ps
CPU time 9.81 seconds
Started Mar 17 02:09:55 PM PDT 24
Finished Mar 17 02:10:05 PM PDT 24
Peak memory 204448 kb
Host smart-7ae16ce6-e228-4bca-95b3-a1920c96346b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=225123858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.225123858
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.1094792207
Short name T550
Test name
Test status
Simulation time 174397997 ps
CPU time 3.84 seconds
Started Mar 17 02:09:47 PM PDT 24
Finished Mar 17 02:09:51 PM PDT 24
Peak memory 203724 kb
Host smart-a9000e2f-af11-4673-9b71-a203caf60673
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1094792207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1094792207
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1730611702
Short name T890
Test name
Test status
Simulation time 15623410519 ps
CPU time 34.89 seconds
Started Mar 17 02:09:42 PM PDT 24
Finished Mar 17 02:10:17 PM PDT 24
Peak memory 203800 kb
Host smart-fda65c7d-7708-4bf7-881e-1ae827bb29b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730611702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1730611702
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4078701885
Short name T898
Test name
Test status
Simulation time 5017675955 ps
CPU time 30.43 seconds
Started Mar 17 02:09:42 PM PDT 24
Finished Mar 17 02:10:13 PM PDT 24
Peak memory 203720 kb
Host smart-e2495564-6e2a-44a6-a5e1-2ddb91d16656
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4078701885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4078701885
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2753185644
Short name T471
Test name
Test status
Simulation time 138267596 ps
CPU time 2.51 seconds
Started Mar 17 02:09:43 PM PDT 24
Finished Mar 17 02:09:45 PM PDT 24
Peak memory 203720 kb
Host smart-c697add8-d4d3-49d1-8516-55125cf5df4d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753185644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2753185644
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3231941612
Short name T857
Test name
Test status
Simulation time 10971725236 ps
CPU time 175.18 seconds
Started Mar 17 02:09:54 PM PDT 24
Finished Mar 17 02:12:50 PM PDT 24
Peak memory 207472 kb
Host smart-afe56346-c679-4e3f-a2fc-52cdb6a6c642
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3231941612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3231941612
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3681009063
Short name T410
Test name
Test status
Simulation time 986488056 ps
CPU time 107.62 seconds
Started Mar 17 02:09:53 PM PDT 24
Finished Mar 17 02:11:40 PM PDT 24
Peak memory 206224 kb
Host smart-2291313e-925a-4e0b-b538-e7254cd45fbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3681009063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3681009063
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1340830218
Short name T149
Test name
Test status
Simulation time 1540007607 ps
CPU time 438.01 seconds
Started Mar 17 02:09:55 PM PDT 24
Finished Mar 17 02:17:13 PM PDT 24
Peak memory 220080 kb
Host smart-110d8419-91ad-42a2-8c3b-54a1ce3bb101
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1340830218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.1340830218
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3030411662
Short name T229
Test name
Test status
Simulation time 73373046 ps
CPU time 6.67 seconds
Started Mar 17 02:09:57 PM PDT 24
Finished Mar 17 02:10:04 PM PDT 24
Peak memory 204824 kb
Host smart-5e0fc1eb-07b2-4f4c-b326-1b3dd9b93678
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3030411662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.3030411662
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3801399195
Short name T510
Test name
Test status
Simulation time 64929227 ps
CPU time 12.61 seconds
Started Mar 17 02:09:49 PM PDT 24
Finished Mar 17 02:10:01 PM PDT 24
Peak memory 211908 kb
Host smart-8bf3b230-ce70-4564-98fa-f73c550eea99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3801399195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3801399195
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3562142085
Short name T184
Test name
Test status
Simulation time 342340082 ps
CPU time 9.65 seconds
Started Mar 17 02:09:59 PM PDT 24
Finished Mar 17 02:10:09 PM PDT 24
Peak memory 203924 kb
Host smart-2af94ccd-c717-4aa1-8f1e-45e62e921f12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3562142085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3562142085
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2611815970
Short name T503
Test name
Test status
Simulation time 91739680724 ps
CPU time 270.62 seconds
Started Mar 17 02:09:58 PM PDT 24
Finished Mar 17 02:14:29 PM PDT 24
Peak memory 206840 kb
Host smart-b246de63-cc2a-4282-9e8e-ea15c168efd3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2611815970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.2611815970
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1247689561
Short name T64
Test name
Test status
Simulation time 348415017 ps
CPU time 11.41 seconds
Started Mar 17 02:10:00 PM PDT 24
Finished Mar 17 02:10:11 PM PDT 24
Peak memory 203724 kb
Host smart-eabea892-4988-4327-b643-1c3366b13609
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1247689561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1247689561
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.995601212
Short name T663
Test name
Test status
Simulation time 1527163019 ps
CPU time 28.25 seconds
Started Mar 17 02:09:59 PM PDT 24
Finished Mar 17 02:10:28 PM PDT 24
Peak memory 203712 kb
Host smart-78fffe6f-ffa9-4ed4-bc5a-66d8c255e021
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=995601212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.995601212
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.487616792
Short name T197
Test name
Test status
Simulation time 131831710 ps
CPU time 5.09 seconds
Started Mar 17 02:09:54 PM PDT 24
Finished Mar 17 02:09:59 PM PDT 24
Peak memory 204024 kb
Host smart-0528346a-fab3-4c62-98d7-3b6a0fce1a60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=487616792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.487616792
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2949898701
Short name T210
Test name
Test status
Simulation time 63693330632 ps
CPU time 280.91 seconds
Started Mar 17 02:09:53 PM PDT 24
Finished Mar 17 02:14:34 PM PDT 24
Peak memory 211956 kb
Host smart-38296142-b6ef-468a-ae07-b9a6a9cbf07b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949898701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2949898701
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2922957484
Short name T335
Test name
Test status
Simulation time 20314693273 ps
CPU time 180.72 seconds
Started Mar 17 02:09:55 PM PDT 24
Finished Mar 17 02:12:56 PM PDT 24
Peak memory 205048 kb
Host smart-ab57039a-3a7a-4266-8b5d-38f875715a93
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2922957484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2922957484
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1485557730
Short name T485
Test name
Test status
Simulation time 250336044 ps
CPU time 17.27 seconds
Started Mar 17 02:09:54 PM PDT 24
Finished Mar 17 02:10:12 PM PDT 24
Peak memory 204860 kb
Host smart-c99aec19-946d-4609-8135-b16164c49747
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485557730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1485557730
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.3437710958
Short name T835
Test name
Test status
Simulation time 1589105785 ps
CPU time 17.91 seconds
Started Mar 17 02:10:00 PM PDT 24
Finished Mar 17 02:10:18 PM PDT 24
Peak memory 204252 kb
Host smart-788fd5e8-d78a-4c32-9ece-b829101942f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437710958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3437710958
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.2308378700
Short name T376
Test name
Test status
Simulation time 304264307 ps
CPU time 3.83 seconds
Started Mar 17 02:09:54 PM PDT 24
Finished Mar 17 02:09:58 PM PDT 24
Peak memory 203696 kb
Host smart-84af211a-572b-468c-a9db-c98d2ea61667
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2308378700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2308378700
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.979355693
Short name T540
Test name
Test status
Simulation time 6353182939 ps
CPU time 26.54 seconds
Started Mar 17 02:09:54 PM PDT 24
Finished Mar 17 02:10:21 PM PDT 24
Peak memory 203720 kb
Host smart-180ea210-b69a-4dcf-ae21-531250fdfc31
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=979355693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.979355693
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1531596738
Short name T644
Test name
Test status
Simulation time 4776572680 ps
CPU time 32.44 seconds
Started Mar 17 02:09:54 PM PDT 24
Finished Mar 17 02:10:27 PM PDT 24
Peak memory 203752 kb
Host smart-c46cf70a-e8b1-4b40-898c-59683129499c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1531596738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1531596738
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1388551580
Short name T233
Test name
Test status
Simulation time 40252530 ps
CPU time 2.44 seconds
Started Mar 17 02:09:53 PM PDT 24
Finished Mar 17 02:09:55 PM PDT 24
Peak memory 203688 kb
Host smart-dba7ecc7-4053-470d-8be8-e8361f8f0156
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388551580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1388551580
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3854170319
Short name T62
Test name
Test status
Simulation time 532746459 ps
CPU time 47.07 seconds
Started Mar 17 02:10:00 PM PDT 24
Finished Mar 17 02:10:48 PM PDT 24
Peak memory 207204 kb
Host smart-029094fc-6469-4680-83a5-c8e01fc7e372
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3854170319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3854170319
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1718598000
Short name T740
Test name
Test status
Simulation time 8030910276 ps
CPU time 192.35 seconds
Started Mar 17 02:09:59 PM PDT 24
Finished Mar 17 02:13:11 PM PDT 24
Peak memory 207508 kb
Host smart-c4232286-f379-44b7-ba2d-5b5a8296b594
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1718598000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1718598000
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1533184426
Short name T5
Test name
Test status
Simulation time 169904831 ps
CPU time 27.03 seconds
Started Mar 17 02:09:59 PM PDT 24
Finished Mar 17 02:10:26 PM PDT 24
Peak memory 206692 kb
Host smart-b2a704e5-76f0-4790-8cf2-362e31ac1590
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1533184426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.1533184426
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3871019891
Short name T522
Test name
Test status
Simulation time 761155878 ps
CPU time 270.92 seconds
Started Mar 17 02:09:58 PM PDT 24
Finished Mar 17 02:14:30 PM PDT 24
Peak memory 220012 kb
Host smart-a208524c-a0c2-4eb1-9b7c-5f0f848dd696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3871019891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.3871019891
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.4246829642
Short name T20
Test name
Test status
Simulation time 750278148 ps
CPU time 9.71 seconds
Started Mar 17 02:10:01 PM PDT 24
Finished Mar 17 02:10:11 PM PDT 24
Peak memory 211884 kb
Host smart-f38a6dba-edd3-4fff-8b24-cdccbd7c6d04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4246829642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4246829642
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1961028897
Short name T331
Test name
Test status
Simulation time 260456652 ps
CPU time 36.67 seconds
Started Mar 17 02:10:05 PM PDT 24
Finished Mar 17 02:10:42 PM PDT 24
Peak memory 205432 kb
Host smart-02dcac2c-772d-4f32-8dc2-67f6e1586067
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1961028897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1961028897
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.191238129
Short name T426
Test name
Test status
Simulation time 31276971626 ps
CPU time 302.38 seconds
Started Mar 17 02:10:04 PM PDT 24
Finished Mar 17 02:15:07 PM PDT 24
Peak memory 207040 kb
Host smart-cbf1f707-32f8-4ecd-8307-dd0c367d7460
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=191238129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slo
w_rsp.191238129
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.216227363
Short name T756
Test name
Test status
Simulation time 77878736 ps
CPU time 7.71 seconds
Started Mar 17 02:10:12 PM PDT 24
Finished Mar 17 02:10:20 PM PDT 24
Peak memory 203988 kb
Host smart-dff9643e-e926-4742-908a-1058e1508e62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=216227363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.216227363
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2521795104
Short name T670
Test name
Test status
Simulation time 54805010 ps
CPU time 7.17 seconds
Started Mar 17 02:10:05 PM PDT 24
Finished Mar 17 02:10:13 PM PDT 24
Peak memory 203744 kb
Host smart-bbcacdd9-4538-4605-83cd-d6ebaf3199a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2521795104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2521795104
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.2371886131
Short name T469
Test name
Test status
Simulation time 2622429940 ps
CPU time 29.86 seconds
Started Mar 17 02:10:05 PM PDT 24
Finished Mar 17 02:10:35 PM PDT 24
Peak memory 211968 kb
Host smart-41b7d2ee-441c-4c69-ba03-96cb321c23bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2371886131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2371886131
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.494355308
Short name T762
Test name
Test status
Simulation time 14847093295 ps
CPU time 98.74 seconds
Started Mar 17 02:10:06 PM PDT 24
Finished Mar 17 02:11:44 PM PDT 24
Peak memory 205024 kb
Host smart-b3f6f36d-df22-44a7-986e-ba075baf8376
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=494355308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.494355308
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2031588720
Short name T438
Test name
Test status
Simulation time 20403817776 ps
CPU time 85.4 seconds
Started Mar 17 02:10:06 PM PDT 24
Finished Mar 17 02:11:32 PM PDT 24
Peak memory 211908 kb
Host smart-17b1c070-da81-4899-9d92-17c909c9b1b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2031588720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2031588720
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3756775749
Short name T562
Test name
Test status
Simulation time 187358653 ps
CPU time 26.36 seconds
Started Mar 17 02:10:05 PM PDT 24
Finished Mar 17 02:10:31 PM PDT 24
Peak memory 204820 kb
Host smart-2fc302c4-eb18-49d1-95ee-13c7c6d8b7bc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756775749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3756775749
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.362658450
Short name T162
Test name
Test status
Simulation time 770632460 ps
CPU time 19.28 seconds
Started Mar 17 02:10:05 PM PDT 24
Finished Mar 17 02:10:25 PM PDT 24
Peak memory 204344 kb
Host smart-4552be95-b077-400d-acd3-69a6c0c4f4e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=362658450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.362658450
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.299171161
Short name T584
Test name
Test status
Simulation time 377012141 ps
CPU time 3.46 seconds
Started Mar 17 02:09:59 PM PDT 24
Finished Mar 17 02:10:02 PM PDT 24
Peak memory 203652 kb
Host smart-0e7f5a7a-bb8c-4ee9-a29d-0d7db38d6af5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=299171161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.299171161
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2164579189
Short name T617
Test name
Test status
Simulation time 9590493539 ps
CPU time 29.02 seconds
Started Mar 17 02:09:59 PM PDT 24
Finished Mar 17 02:10:29 PM PDT 24
Peak memory 203776 kb
Host smart-1ea7a4ba-3de1-4fd2-aa97-9b7672cdae3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164579189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2164579189
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3433767245
Short name T418
Test name
Test status
Simulation time 5465462902 ps
CPU time 27.36 seconds
Started Mar 17 02:10:05 PM PDT 24
Finished Mar 17 02:10:33 PM PDT 24
Peak memory 203756 kb
Host smart-5622ab70-603f-4cd9-9491-385a7d197c65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3433767245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3433767245
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1860513277
Short name T290
Test name
Test status
Simulation time 38988671 ps
CPU time 2.19 seconds
Started Mar 17 02:09:58 PM PDT 24
Finished Mar 17 02:10:00 PM PDT 24
Peak memory 203720 kb
Host smart-01a0dd2b-48b0-4ee4-b383-91675953602d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860513277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1860513277
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.126970828
Short name T628
Test name
Test status
Simulation time 2475075952 ps
CPU time 106.41 seconds
Started Mar 17 02:10:10 PM PDT 24
Finished Mar 17 02:11:57 PM PDT 24
Peak memory 207200 kb
Host smart-bba9a969-4ac5-4ec9-917c-2fcd1b3ebc6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=126970828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.126970828
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2337041384
Short name T362
Test name
Test status
Simulation time 980069085 ps
CPU time 71.26 seconds
Started Mar 17 02:10:13 PM PDT 24
Finished Mar 17 02:11:24 PM PDT 24
Peak memory 205716 kb
Host smart-6e904da2-1633-4fa7-b8d8-6608719833d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2337041384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2337041384
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.957277734
Short name T385
Test name
Test status
Simulation time 8092000532 ps
CPU time 377.07 seconds
Started Mar 17 02:10:10 PM PDT 24
Finished Mar 17 02:16:27 PM PDT 24
Peak memory 211064 kb
Host smart-5f3d0c94-d72e-4b25-b7d1-fbf3670ee695
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=957277734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand
_reset.957277734
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3580121824
Short name T343
Test name
Test status
Simulation time 710600119 ps
CPU time 125.22 seconds
Started Mar 17 02:10:11 PM PDT 24
Finished Mar 17 02:12:17 PM PDT 24
Peak memory 208844 kb
Host smart-42778e77-7520-4e15-acec-ed269cdc0041
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3580121824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3580121824
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1275017852
Short name T443
Test name
Test status
Simulation time 135988949 ps
CPU time 16.61 seconds
Started Mar 17 02:10:13 PM PDT 24
Finished Mar 17 02:10:29 PM PDT 24
Peak memory 205388 kb
Host smart-df154f13-9210-4bbe-a7a2-c489d77a3f75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1275017852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1275017852
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.571031111
Short name T167
Test name
Test status
Simulation time 363103848 ps
CPU time 4.64 seconds
Started Mar 17 02:10:17 PM PDT 24
Finished Mar 17 02:10:22 PM PDT 24
Peak memory 203784 kb
Host smart-701173c9-5ce8-4d6f-9edf-32c360ed3e3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=571031111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.571031111
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.391758150
Short name T882
Test name
Test status
Simulation time 236883555773 ps
CPU time 607.89 seconds
Started Mar 17 02:10:17 PM PDT 24
Finished Mar 17 02:20:25 PM PDT 24
Peak memory 211988 kb
Host smart-7ea63ae9-0bd9-4be0-a6f9-699d31500d47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=391758150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo
w_rsp.391758150
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2567351835
Short name T462
Test name
Test status
Simulation time 939103189 ps
CPU time 25.97 seconds
Started Mar 17 02:10:22 PM PDT 24
Finished Mar 17 02:10:48 PM PDT 24
Peak memory 203972 kb
Host smart-66ed25a1-07ac-43dc-9270-f6e9b73bb51a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2567351835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2567351835
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.535589552
Short name T748
Test name
Test status
Simulation time 1606121257 ps
CPU time 28.49 seconds
Started Mar 17 02:10:17 PM PDT 24
Finished Mar 17 02:10:45 PM PDT 24
Peak memory 203680 kb
Host smart-96a254d5-730e-442b-bb94-a4fac2c76329
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=535589552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.535589552
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.1958545678
Short name T461
Test name
Test status
Simulation time 4993033850 ps
CPU time 45.16 seconds
Started Mar 17 02:10:10 PM PDT 24
Finished Mar 17 02:10:56 PM PDT 24
Peak memory 205516 kb
Host smart-c2f3d9d0-4b13-4e71-87b0-19d9ab327c5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1958545678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1958545678
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.380795171
Short name T594
Test name
Test status
Simulation time 94697587043 ps
CPU time 226.13 seconds
Started Mar 17 02:10:17 PM PDT 24
Finished Mar 17 02:14:04 PM PDT 24
Peak memory 211924 kb
Host smart-bffc5f06-b167-408c-ae93-a26c9470689d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=380795171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.380795171
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.712801478
Short name T389
Test name
Test status
Simulation time 94887079971 ps
CPU time 274.82 seconds
Started Mar 17 02:10:18 PM PDT 24
Finished Mar 17 02:14:53 PM PDT 24
Peak memory 205724 kb
Host smart-b4fa305d-72aa-4460-ae68-fd9db5c9774d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=712801478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.712801478
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.715704978
Short name T384
Test name
Test status
Simulation time 49434108 ps
CPU time 5.41 seconds
Started Mar 17 02:10:16 PM PDT 24
Finished Mar 17 02:10:21 PM PDT 24
Peak memory 204836 kb
Host smart-0f39d2f3-20f8-46f7-93e3-f4d34d061c33
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715704978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.715704978
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.25033742
Short name T63
Test name
Test status
Simulation time 1252937446 ps
CPU time 11.47 seconds
Started Mar 17 02:10:17 PM PDT 24
Finished Mar 17 02:10:28 PM PDT 24
Peak memory 204316 kb
Host smart-733516c9-b7bf-4fc4-86ee-5096894cbcf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25033742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.25033742
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.373660996
Short name T156
Test name
Test status
Simulation time 48789442 ps
CPU time 2.4 seconds
Started Mar 17 02:10:10 PM PDT 24
Finished Mar 17 02:10:13 PM PDT 24
Peak memory 203660 kb
Host smart-1f9317fe-1af5-45af-9e79-3ce2f702fed1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=373660996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.373660996
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2270646387
Short name T664
Test name
Test status
Simulation time 7991369079 ps
CPU time 30.76 seconds
Started Mar 17 02:10:10 PM PDT 24
Finished Mar 17 02:10:41 PM PDT 24
Peak memory 203792 kb
Host smart-18d8ddad-c964-4ce2-88cc-e290c0031286
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270646387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2270646387
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1074783771
Short name T237
Test name
Test status
Simulation time 8022123373 ps
CPU time 27.99 seconds
Started Mar 17 02:10:13 PM PDT 24
Finished Mar 17 02:10:42 PM PDT 24
Peak memory 203756 kb
Host smart-865cc83a-c957-40e2-90f3-bfb6e804aad6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1074783771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1074783771
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1350700546
Short name T264
Test name
Test status
Simulation time 55025883 ps
CPU time 2.62 seconds
Started Mar 17 02:10:10 PM PDT 24
Finished Mar 17 02:10:13 PM PDT 24
Peak memory 203644 kb
Host smart-456b332b-48a2-4ea1-b80f-51be8cb871c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350700546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1350700546
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.524335588
Short name T856
Test name
Test status
Simulation time 1254001118 ps
CPU time 19.09 seconds
Started Mar 17 02:10:22 PM PDT 24
Finished Mar 17 02:10:41 PM PDT 24
Peak memory 205044 kb
Host smart-96ab4a38-6f19-4b8d-a8a8-fd72c2103278
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=524335588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.524335588
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1377095720
Short name T480
Test name
Test status
Simulation time 333168684 ps
CPU time 12.74 seconds
Started Mar 17 02:10:23 PM PDT 24
Finished Mar 17 02:10:36 PM PDT 24
Peak memory 204024 kb
Host smart-7b8c43f7-ced8-4665-b372-a70f52206657
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1377095720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1377095720
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1797730407
Short name T137
Test name
Test status
Simulation time 4288358082 ps
CPU time 607.78 seconds
Started Mar 17 02:10:20 PM PDT 24
Finished Mar 17 02:20:29 PM PDT 24
Peak memory 225288 kb
Host smart-81c7730e-8360-4ac7-85ce-93cefc8a3f0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1797730407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.1797730407
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3302959907
Short name T534
Test name
Test status
Simulation time 4613498873 ps
CPU time 280.35 seconds
Started Mar 17 02:10:22 PM PDT 24
Finished Mar 17 02:15:03 PM PDT 24
Peak memory 220092 kb
Host smart-0912a0cd-5438-43af-b477-369098009a3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3302959907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.3302959907
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1082315329
Short name T403
Test name
Test status
Simulation time 167835715 ps
CPU time 20.38 seconds
Started Mar 17 02:10:18 PM PDT 24
Finished Mar 17 02:10:39 PM PDT 24
Peak memory 204996 kb
Host smart-390f39f0-5321-4dfe-b02c-611345b181bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1082315329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1082315329
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3302836446
Short name T850
Test name
Test status
Simulation time 198831277 ps
CPU time 24.15 seconds
Started Mar 17 02:02:00 PM PDT 24
Finished Mar 17 02:02:24 PM PDT 24
Peak memory 211784 kb
Host smart-f012d55c-5830-4fa5-bdd9-d47456d5c48b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3302836446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3302836446
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.496394695
Short name T111
Test name
Test status
Simulation time 5451419632 ps
CPU time 55.9 seconds
Started Mar 17 02:02:01 PM PDT 24
Finished Mar 17 02:02:57 PM PDT 24
Peak memory 204856 kb
Host smart-cd69e9b7-d689-4bd3-b8cc-3c6c04f6098b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=496394695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow
_rsp.496394695
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.33551078
Short name T319
Test name
Test status
Simulation time 94563740 ps
CPU time 11.93 seconds
Started Mar 17 02:02:01 PM PDT 24
Finished Mar 17 02:02:13 PM PDT 24
Peak memory 203816 kb
Host smart-b6382c7f-8960-47ef-bbf5-74724916619a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33551078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.33551078
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.1256051217
Short name T818
Test name
Test status
Simulation time 55222596 ps
CPU time 6.95 seconds
Started Mar 17 02:02:02 PM PDT 24
Finished Mar 17 02:02:10 PM PDT 24
Peak memory 203692 kb
Host smart-5c378557-9ddb-49e4-826c-989926913174
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1256051217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1256051217
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.3536042482
Short name T716
Test name
Test status
Simulation time 1194074230 ps
CPU time 24.97 seconds
Started Mar 17 02:01:55 PM PDT 24
Finished Mar 17 02:02:20 PM PDT 24
Peak memory 204856 kb
Host smart-b22e76c4-67ed-4a50-97c4-f6714bbf9f9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3536042482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3536042482
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.623535273
Short name T261
Test name
Test status
Simulation time 49674931894 ps
CPU time 132.13 seconds
Started Mar 17 02:02:01 PM PDT 24
Finished Mar 17 02:04:13 PM PDT 24
Peak memory 211948 kb
Host smart-11d13454-f5dc-4a00-b7d3-95e92e6ae52c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=623535273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.623535273
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2766096850
Short name T639
Test name
Test status
Simulation time 15345973598 ps
CPU time 150.68 seconds
Started Mar 17 02:02:01 PM PDT 24
Finished Mar 17 02:04:32 PM PDT 24
Peak memory 204892 kb
Host smart-d7280ed3-8203-40b0-9c23-47b93ab5e2eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2766096850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2766096850
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3979413436
Short name T314
Test name
Test status
Simulation time 40315846 ps
CPU time 3.67 seconds
Started Mar 17 02:02:02 PM PDT 24
Finished Mar 17 02:02:06 PM PDT 24
Peak memory 204132 kb
Host smart-2c1c4eef-f8e0-4dce-83f7-a64ecaa34b4c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979413436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3979413436
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.2760365704
Short name T285
Test name
Test status
Simulation time 629166588 ps
CPU time 12.39 seconds
Started Mar 17 02:02:00 PM PDT 24
Finished Mar 17 02:02:12 PM PDT 24
Peak memory 204116 kb
Host smart-671d6255-90e8-465b-a454-a4355eddb382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2760365704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2760365704
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1798039712
Short name T478
Test name
Test status
Simulation time 171719232 ps
CPU time 3.92 seconds
Started Mar 17 02:01:51 PM PDT 24
Finished Mar 17 02:01:56 PM PDT 24
Peak memory 203712 kb
Host smart-ff162a75-701c-45a2-9a59-4496e00c7452
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1798039712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1798039712
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3001016971
Short name T282
Test name
Test status
Simulation time 8903957474 ps
CPU time 30.01 seconds
Started Mar 17 02:01:55 PM PDT 24
Finished Mar 17 02:02:25 PM PDT 24
Peak memory 203772 kb
Host smart-a6158c90-45bd-47a4-a1a2-4de7646e8ccd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001016971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3001016971
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2184614678
Short name T623
Test name
Test status
Simulation time 5807714956 ps
CPU time 28.3 seconds
Started Mar 17 02:01:55 PM PDT 24
Finished Mar 17 02:02:24 PM PDT 24
Peak memory 203816 kb
Host smart-08053bcc-8c33-47a2-864b-c4a8640ef0d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2184614678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2184614678
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3278069227
Short name T557
Test name
Test status
Simulation time 25291271 ps
CPU time 2.37 seconds
Started Mar 17 02:01:47 PM PDT 24
Finished Mar 17 02:01:51 PM PDT 24
Peak memory 203684 kb
Host smart-fc099049-63a6-4073-9ec9-d25cd75d6b6c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278069227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3278069227
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1774863776
Short name T346
Test name
Test status
Simulation time 539394318 ps
CPU time 67.79 seconds
Started Mar 17 02:02:00 PM PDT 24
Finished Mar 17 02:03:08 PM PDT 24
Peak memory 206700 kb
Host smart-97dca9b0-e116-42af-b963-202cf7ea107c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1774863776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1774863776
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2173016145
Short name T749
Test name
Test status
Simulation time 11340917746 ps
CPU time 363.96 seconds
Started Mar 17 02:02:00 PM PDT 24
Finished Mar 17 02:08:05 PM PDT 24
Peak memory 207680 kb
Host smart-f44a4534-c1ca-42bd-993c-e6c603f3bbf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2173016145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2173016145
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4015779231
Short name T73
Test name
Test status
Simulation time 7003682119 ps
CPU time 437.43 seconds
Started Mar 17 02:02:02 PM PDT 24
Finished Mar 17 02:09:19 PM PDT 24
Peak memory 208852 kb
Host smart-d451d15d-43dc-404e-8dd8-f6c685204b8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4015779231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.4015779231
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3179687655
Short name T391
Test name
Test status
Simulation time 93379262 ps
CPU time 25.8 seconds
Started Mar 17 02:02:04 PM PDT 24
Finished Mar 17 02:02:30 PM PDT 24
Peak memory 206364 kb
Host smart-76255c9e-e0ea-48bc-b325-43deba3d5426
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3179687655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.3179687655
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1775523137
Short name T109
Test name
Test status
Simulation time 462648653 ps
CPU time 6.7 seconds
Started Mar 17 02:02:00 PM PDT 24
Finished Mar 17 02:02:07 PM PDT 24
Peak memory 204912 kb
Host smart-f1ade37b-59a8-4686-a07c-80720ec0f10b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1775523137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1775523137
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.388522419
Short name T139
Test name
Test status
Simulation time 381840034 ps
CPU time 40.18 seconds
Started Mar 17 02:10:27 PM PDT 24
Finished Mar 17 02:11:07 PM PDT 24
Peak memory 206016 kb
Host smart-7f991c6d-41d8-42cc-a085-d461980f622e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=388522419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.388522419
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1712418268
Short name T242
Test name
Test status
Simulation time 474554406 ps
CPU time 12.01 seconds
Started Mar 17 02:10:33 PM PDT 24
Finished Mar 17 02:10:45 PM PDT 24
Peak memory 204096 kb
Host smart-f16928d5-877b-4cde-af7b-bfb1471bcce9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1712418268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1712418268
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.917685767
Short name T159
Test name
Test status
Simulation time 575873694 ps
CPU time 22.15 seconds
Started Mar 17 02:10:35 PM PDT 24
Finished Mar 17 02:10:57 PM PDT 24
Peak memory 203724 kb
Host smart-f98d7dc3-04d2-4331-81a1-52387993d6e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=917685767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.917685767
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.2877967211
Short name T751
Test name
Test status
Simulation time 1074416698 ps
CPU time 22.97 seconds
Started Mar 17 02:10:28 PM PDT 24
Finished Mar 17 02:10:52 PM PDT 24
Peak memory 211892 kb
Host smart-3c434830-5bf4-4924-b0c1-f7bf394eb954
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2877967211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2877967211
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1500691514
Short name T232
Test name
Test status
Simulation time 14227523383 ps
CPU time 92.34 seconds
Started Mar 17 02:10:28 PM PDT 24
Finished Mar 17 02:12:01 PM PDT 24
Peak memory 204888 kb
Host smart-f3b2cfc8-7372-49e5-a6fb-3c46dfb6a544
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500691514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1500691514
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3356587240
Short name T246
Test name
Test status
Simulation time 4509739066 ps
CPU time 40.23 seconds
Started Mar 17 02:10:28 PM PDT 24
Finished Mar 17 02:11:08 PM PDT 24
Peak memory 204924 kb
Host smart-4bcdee32-250f-4ceb-be01-8960a6fd4c52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3356587240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3356587240
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3986301382
Short name T360
Test name
Test status
Simulation time 276356863 ps
CPU time 30.45 seconds
Started Mar 17 02:10:26 PM PDT 24
Finished Mar 17 02:10:57 PM PDT 24
Peak memory 204820 kb
Host smart-452540b7-f7da-4073-bdfb-bd6332221b2d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986301382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3986301382
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.4215193605
Short name T219
Test name
Test status
Simulation time 113409041 ps
CPU time 9.47 seconds
Started Mar 17 02:10:36 PM PDT 24
Finished Mar 17 02:10:45 PM PDT 24
Peak memory 204232 kb
Host smart-12a62711-919c-4d52-8387-c9b3a6b97633
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4215193605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.4215193605
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.1425890285
Short name T351
Test name
Test status
Simulation time 394897144 ps
CPU time 3.87 seconds
Started Mar 17 02:10:21 PM PDT 24
Finished Mar 17 02:10:26 PM PDT 24
Peak memory 203736 kb
Host smart-e1520260-abb8-4824-a825-4afef4ae0801
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1425890285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1425890285
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2032236641
Short name T168
Test name
Test status
Simulation time 6875969168 ps
CPU time 32.65 seconds
Started Mar 17 02:10:21 PM PDT 24
Finished Mar 17 02:10:54 PM PDT 24
Peak memory 203784 kb
Host smart-7f9415c9-db63-4953-821b-59abbd7b5bfb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032236641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2032236641
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.245974070
Short name T858
Test name
Test status
Simulation time 3185845224 ps
CPU time 28.8 seconds
Started Mar 17 02:10:23 PM PDT 24
Finished Mar 17 02:10:52 PM PDT 24
Peak memory 203780 kb
Host smart-7b32fa23-c409-48d2-8df0-d5d1bfd904c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=245974070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.245974070
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1568008759
Short name T795
Test name
Test status
Simulation time 45759887 ps
CPU time 2.9 seconds
Started Mar 17 02:10:22 PM PDT 24
Finished Mar 17 02:10:25 PM PDT 24
Peak memory 203692 kb
Host smart-631ed712-18e1-412e-a422-35e777d300e0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568008759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1568008759
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3397837536
Short name T425
Test name
Test status
Simulation time 2171572506 ps
CPU time 222.25 seconds
Started Mar 17 02:10:33 PM PDT 24
Finished Mar 17 02:14:16 PM PDT 24
Peak memory 207368 kb
Host smart-3b9dca25-40b7-4ef3-bce0-fd115f6a7af0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3397837536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3397837536
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2977194463
Short name T517
Test name
Test status
Simulation time 185765798 ps
CPU time 27.47 seconds
Started Mar 17 02:10:33 PM PDT 24
Finished Mar 17 02:11:01 PM PDT 24
Peak memory 204876 kb
Host smart-80165a91-a59d-4e4b-99cd-50b6acbec2d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2977194463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2977194463
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1782630349
Short name T784
Test name
Test status
Simulation time 837126852 ps
CPU time 313.67 seconds
Started Mar 17 02:10:34 PM PDT 24
Finished Mar 17 02:15:48 PM PDT 24
Peak memory 210376 kb
Host smart-60e3fc54-101b-4652-8d48-bb0ac927d7a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1782630349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.1782630349
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1747170184
Short name T220
Test name
Test status
Simulation time 34562005 ps
CPU time 6.97 seconds
Started Mar 17 02:10:35 PM PDT 24
Finished Mar 17 02:10:42 PM PDT 24
Peak memory 205212 kb
Host smart-af56a7ba-53d3-4aea-ac73-c6cb92714b85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1747170184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1747170184
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1813745866
Short name T420
Test name
Test status
Simulation time 4094327471 ps
CPU time 81.18 seconds
Started Mar 17 02:10:39 PM PDT 24
Finished Mar 17 02:12:01 PM PDT 24
Peak memory 211908 kb
Host smart-3f8682d4-4320-4a18-ad98-2c131cd91106
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1813745866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1813745866
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.783081484
Short name T173
Test name
Test status
Simulation time 19991431820 ps
CPU time 36.08 seconds
Started Mar 17 02:10:39 PM PDT 24
Finished Mar 17 02:11:15 PM PDT 24
Peak memory 204028 kb
Host smart-8756a569-c123-4e01-980f-417c6ba97c41
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=783081484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo
w_rsp.783081484
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.160731728
Short name T240
Test name
Test status
Simulation time 1949447378 ps
CPU time 19.74 seconds
Started Mar 17 02:10:45 PM PDT 24
Finished Mar 17 02:11:05 PM PDT 24
Peak memory 203692 kb
Host smart-4aaf072e-2ddb-4b0b-97d8-990584db83dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=160731728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.160731728
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.2454117759
Short name T609
Test name
Test status
Simulation time 19583651 ps
CPU time 2.11 seconds
Started Mar 17 02:10:41 PM PDT 24
Finished Mar 17 02:10:43 PM PDT 24
Peak memory 203672 kb
Host smart-1150adc7-acf3-4303-ba0b-556c894b5187
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2454117759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2454117759
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.1978899399
Short name T652
Test name
Test status
Simulation time 305811642 ps
CPU time 32.56 seconds
Started Mar 17 02:10:39 PM PDT 24
Finished Mar 17 02:11:12 PM PDT 24
Peak memory 205116 kb
Host smart-4ab82ccf-25d3-4d26-81bb-acac20140f49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1978899399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1978899399
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2058150424
Short name T49
Test name
Test status
Simulation time 123343965008 ps
CPU time 302.67 seconds
Started Mar 17 02:10:39 PM PDT 24
Finished Mar 17 02:15:42 PM PDT 24
Peak memory 211980 kb
Host smart-a74e9d1c-858b-48e3-88a8-b9e32834bb98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058150424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2058150424
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1661888005
Short name T847
Test name
Test status
Simulation time 54087714349 ps
CPU time 132.33 seconds
Started Mar 17 02:10:41 PM PDT 24
Finished Mar 17 02:12:54 PM PDT 24
Peak memory 211992 kb
Host smart-8206ddb6-3944-494e-9d40-e8f0e1fc98b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1661888005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1661888005
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.4212907004
Short name T780
Test name
Test status
Simulation time 210680873 ps
CPU time 15.78 seconds
Started Mar 17 02:10:43 PM PDT 24
Finished Mar 17 02:10:59 PM PDT 24
Peak memory 204996 kb
Host smart-25bb7e71-172c-475e-a921-f99c36cfc714
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212907004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.4212907004
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.3228990320
Short name T176
Test name
Test status
Simulation time 1823334567 ps
CPU time 31.67 seconds
Started Mar 17 02:10:40 PM PDT 24
Finished Mar 17 02:11:11 PM PDT 24
Peak memory 204228 kb
Host smart-8fbbc192-cb1b-4c17-be8a-92780ec3c8e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3228990320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3228990320
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1595155150
Short name T252
Test name
Test status
Simulation time 311209820 ps
CPU time 3.41 seconds
Started Mar 17 02:10:38 PM PDT 24
Finished Mar 17 02:10:42 PM PDT 24
Peak memory 203668 kb
Host smart-e3e688b4-309b-4a31-a293-36ed8ed21cd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1595155150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1595155150
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2028900963
Short name T787
Test name
Test status
Simulation time 7826461292 ps
CPU time 27.09 seconds
Started Mar 17 02:10:39 PM PDT 24
Finished Mar 17 02:11:07 PM PDT 24
Peak memory 203784 kb
Host smart-f245485c-703e-48e6-a213-d15bdef1fcea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028900963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2028900963
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2466430865
Short name T844
Test name
Test status
Simulation time 5437316053 ps
CPU time 24.94 seconds
Started Mar 17 02:10:40 PM PDT 24
Finished Mar 17 02:11:05 PM PDT 24
Peak memory 203800 kb
Host smart-60481c35-52cc-4f24-bdb9-c80fe2a9ec3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2466430865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2466430865
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2927286018
Short name T198
Test name
Test status
Simulation time 57095532 ps
CPU time 2.84 seconds
Started Mar 17 02:10:43 PM PDT 24
Finished Mar 17 02:10:46 PM PDT 24
Peak memory 203708 kb
Host smart-bcc6b1e6-be4e-417f-ac53-02dd36240487
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927286018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2927286018
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1903195821
Short name T735
Test name
Test status
Simulation time 8656496486 ps
CPU time 162.52 seconds
Started Mar 17 02:10:47 PM PDT 24
Finished Mar 17 02:13:30 PM PDT 24
Peak memory 206776 kb
Host smart-ea0e3dbb-9ad9-4aff-8828-31501320b8cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1903195821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1903195821
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.277042793
Short name T169
Test name
Test status
Simulation time 95232346 ps
CPU time 25.98 seconds
Started Mar 17 02:10:45 PM PDT 24
Finished Mar 17 02:11:12 PM PDT 24
Peak memory 206784 kb
Host smart-9bd62e9e-6807-4419-bcaa-48174489b3b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277042793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand
_reset.277042793
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1485909878
Short name T499
Test name
Test status
Simulation time 3361416434 ps
CPU time 227.35 seconds
Started Mar 17 02:10:46 PM PDT 24
Finished Mar 17 02:14:34 PM PDT 24
Peak memory 211920 kb
Host smart-d2924f6a-4d0a-484a-aa7a-fb81b7b24ce6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1485909878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.1485909878
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3325303768
Short name T312
Test name
Test status
Simulation time 344070407 ps
CPU time 3.69 seconds
Started Mar 17 02:10:49 PM PDT 24
Finished Mar 17 02:10:53 PM PDT 24
Peak memory 211908 kb
Host smart-1d3bcbdc-04a5-4511-9524-8934cacf739c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3325303768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3325303768
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3259405108
Short name T432
Test name
Test status
Simulation time 9395386594 ps
CPU time 75.27 seconds
Started Mar 17 02:10:52 PM PDT 24
Finished Mar 17 02:12:07 PM PDT 24
Peak memory 206124 kb
Host smart-41069b6b-b18b-4fee-9057-3b796a341a86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3259405108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3259405108
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1327721039
Short name T297
Test name
Test status
Simulation time 291403086954 ps
CPU time 497.41 seconds
Started Mar 17 02:10:54 PM PDT 24
Finished Mar 17 02:19:12 PM PDT 24
Peak memory 207280 kb
Host smart-b122c2f6-6479-4c7f-a4e6-2ad61a892655
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1327721039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.1327721039
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1855271881
Short name T400
Test name
Test status
Simulation time 305633360 ps
CPU time 16.76 seconds
Started Mar 17 02:10:53 PM PDT 24
Finished Mar 17 02:11:10 PM PDT 24
Peak memory 203972 kb
Host smart-461fee1a-0466-4241-b775-9c452eccb551
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1855271881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1855271881
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.770874826
Short name T705
Test name
Test status
Simulation time 445026149 ps
CPU time 29.06 seconds
Started Mar 17 02:10:52 PM PDT 24
Finished Mar 17 02:11:21 PM PDT 24
Peak memory 203748 kb
Host smart-d96ce173-441b-45f1-afb2-0a044a2eaa05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=770874826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.770874826
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.250194296
Short name T318
Test name
Test status
Simulation time 287411869 ps
CPU time 11.33 seconds
Started Mar 17 02:10:53 PM PDT 24
Finished Mar 17 02:11:05 PM PDT 24
Peak memory 211844 kb
Host smart-280d59d7-d216-4326-910c-6b5cfa1a3b05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=250194296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.250194296
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.499901928
Short name T123
Test name
Test status
Simulation time 93590586297 ps
CPU time 285.21 seconds
Started Mar 17 02:10:53 PM PDT 24
Finished Mar 17 02:15:38 PM PDT 24
Peak memory 205880 kb
Host smart-cbade72c-4540-4e1d-81c0-76b262321142
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=499901928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.499901928
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1515592168
Short name T357
Test name
Test status
Simulation time 31299584726 ps
CPU time 238.28 seconds
Started Mar 17 02:10:53 PM PDT 24
Finished Mar 17 02:14:51 PM PDT 24
Peak memory 205680 kb
Host smart-48bba442-71cd-4969-9fa8-9a7d90257f96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1515592168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1515592168
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2485804784
Short name T231
Test name
Test status
Simulation time 32650721 ps
CPU time 5.06 seconds
Started Mar 17 02:10:52 PM PDT 24
Finished Mar 17 02:10:57 PM PDT 24
Peak memory 204384 kb
Host smart-51792881-39a9-42c1-ace2-8adbedc0a2b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485804784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2485804784
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.2872806950
Short name T209
Test name
Test status
Simulation time 136869232 ps
CPU time 3.98 seconds
Started Mar 17 02:10:53 PM PDT 24
Finished Mar 17 02:10:57 PM PDT 24
Peak memory 203848 kb
Host smart-cf39dbb9-951a-43fd-b12b-cd7fc982926f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2872806950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2872806950
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.1436788920
Short name T709
Test name
Test status
Simulation time 154527946 ps
CPU time 2.81 seconds
Started Mar 17 02:10:46 PM PDT 24
Finished Mar 17 02:10:49 PM PDT 24
Peak memory 203700 kb
Host smart-0c07e3bc-529d-4025-807d-3e1ea1838416
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1436788920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1436788920
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3200627521
Short name T518
Test name
Test status
Simulation time 7958118053 ps
CPU time 31.09 seconds
Started Mar 17 02:10:49 PM PDT 24
Finished Mar 17 02:11:21 PM PDT 24
Peak memory 203804 kb
Host smart-90b7ce9f-f763-49a6-b49c-085f43c426cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200627521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3200627521
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3590534668
Short name T506
Test name
Test status
Simulation time 4774267550 ps
CPU time 28.69 seconds
Started Mar 17 02:10:44 PM PDT 24
Finished Mar 17 02:11:13 PM PDT 24
Peak memory 203784 kb
Host smart-ccb0d9e7-37d2-47a7-bacf-6878dfcd0f55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3590534668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3590534668
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1803763644
Short name T686
Test name
Test status
Simulation time 28277960 ps
CPU time 1.97 seconds
Started Mar 17 02:10:46 PM PDT 24
Finished Mar 17 02:10:49 PM PDT 24
Peak memory 203740 kb
Host smart-d88edef5-150d-4add-bb19-e3f17552a6b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803763644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1803763644
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.3522375432
Short name T454
Test name
Test status
Simulation time 2614626804 ps
CPU time 86.9 seconds
Started Mar 17 02:10:59 PM PDT 24
Finished Mar 17 02:12:26 PM PDT 24
Peak memory 207600 kb
Host smart-e1492f79-b815-4917-8a21-62bb528fd40f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3522375432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3522375432
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3942749625
Short name T372
Test name
Test status
Simulation time 5555169753 ps
CPU time 96.75 seconds
Started Mar 17 02:10:58 PM PDT 24
Finished Mar 17 02:12:35 PM PDT 24
Peak memory 206484 kb
Host smart-e8f8987b-1061-46ca-8a8e-b2a793367302
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3942749625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3942749625
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2276135353
Short name T734
Test name
Test status
Simulation time 1345659186 ps
CPU time 347.58 seconds
Started Mar 17 02:10:58 PM PDT 24
Finished Mar 17 02:16:46 PM PDT 24
Peak memory 210836 kb
Host smart-f994d921-ebe7-4e3d-9d6c-6e1c0c9c6767
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2276135353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.2276135353
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.4261764878
Short name T368
Test name
Test status
Simulation time 6045343960 ps
CPU time 361.01 seconds
Started Mar 17 02:10:58 PM PDT 24
Finished Mar 17 02:16:59 PM PDT 24
Peak memory 220172 kb
Host smart-2d4a8941-4e13-473b-808c-46c147e84dea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4261764878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.4261764878
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2901716679
Short name T92
Test name
Test status
Simulation time 329598924 ps
CPU time 18 seconds
Started Mar 17 02:10:53 PM PDT 24
Finished Mar 17 02:11:11 PM PDT 24
Peak memory 205356 kb
Host smart-509685e6-39e2-4a84-ba68-8c2f3d8f9063
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2901716679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2901716679
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.363132319
Short name T12
Test name
Test status
Simulation time 1112576133 ps
CPU time 25.47 seconds
Started Mar 17 02:10:59 PM PDT 24
Finished Mar 17 02:11:25 PM PDT 24
Peak memory 205320 kb
Host smart-b7304e39-032f-45d0-8243-d0fb2597bbe2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=363132319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.363132319
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2197315849
Short name T693
Test name
Test status
Simulation time 74414960540 ps
CPU time 647.92 seconds
Started Mar 17 02:10:58 PM PDT 24
Finished Mar 17 02:21:46 PM PDT 24
Peak memory 206232 kb
Host smart-55d16829-e458-4b6b-84e4-9d609d34dcb6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2197315849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.2197315849
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2861976298
Short name T267
Test name
Test status
Simulation time 1715409474 ps
CPU time 26.63 seconds
Started Mar 17 02:11:04 PM PDT 24
Finished Mar 17 02:11:31 PM PDT 24
Peak memory 203988 kb
Host smart-4d8e69f3-3dbe-447a-bf71-b4aac603cbdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2861976298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2861976298
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.2931528043
Short name T457
Test name
Test status
Simulation time 73372759 ps
CPU time 2.62 seconds
Started Mar 17 02:11:03 PM PDT 24
Finished Mar 17 02:11:06 PM PDT 24
Peak memory 203664 kb
Host smart-1bae5945-0b36-4712-8fcd-ee0c2d5f054a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2931528043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2931528043
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.1871435268
Short name T571
Test name
Test status
Simulation time 71695929 ps
CPU time 9.4 seconds
Started Mar 17 02:10:59 PM PDT 24
Finished Mar 17 02:11:09 PM PDT 24
Peak memory 204828 kb
Host smart-2ccdca02-08c5-4526-9ce1-109a5922efc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1871435268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1871435268
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2346210548
Short name T542
Test name
Test status
Simulation time 21029496131 ps
CPU time 45.2 seconds
Started Mar 17 02:10:59 PM PDT 24
Finished Mar 17 02:11:44 PM PDT 24
Peak memory 211932 kb
Host smart-05444569-a3ab-4b65-a009-1ae3e407144f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346210548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2346210548
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2969090522
Short name T568
Test name
Test status
Simulation time 27988133859 ps
CPU time 252.52 seconds
Started Mar 17 02:10:58 PM PDT 24
Finished Mar 17 02:15:11 PM PDT 24
Peak memory 212008 kb
Host smart-42554254-52e6-499a-9b03-3241b91b70ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2969090522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2969090522
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2466420958
Short name T147
Test name
Test status
Simulation time 122160196 ps
CPU time 18.24 seconds
Started Mar 17 02:11:00 PM PDT 24
Finished Mar 17 02:11:18 PM PDT 24
Peak memory 211884 kb
Host smart-426bdcf3-0b25-484a-bdce-bc26b6998002
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466420958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2466420958
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.571566808
Short name T433
Test name
Test status
Simulation time 134152330 ps
CPU time 10.14 seconds
Started Mar 17 02:11:05 PM PDT 24
Finished Mar 17 02:11:15 PM PDT 24
Peak memory 204356 kb
Host smart-545a121f-f2ba-4ab6-9dd0-2870d7e72c0e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=571566808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.571566808
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.585854215
Short name T120
Test name
Test status
Simulation time 947984124 ps
CPU time 5.02 seconds
Started Mar 17 02:10:59 PM PDT 24
Finished Mar 17 02:11:04 PM PDT 24
Peak memory 203748 kb
Host smart-8aeb505a-90f3-4336-b276-0a44d254b910
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=585854215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.585854215
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.4182632401
Short name T40
Test name
Test status
Simulation time 15009528825 ps
CPU time 35.82 seconds
Started Mar 17 02:10:58 PM PDT 24
Finished Mar 17 02:11:33 PM PDT 24
Peak memory 203752 kb
Host smart-092d149b-3565-40a6-aaf0-d7824153b12c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182632401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.4182632401
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3292886596
Short name T535
Test name
Test status
Simulation time 2785988051 ps
CPU time 26.51 seconds
Started Mar 17 02:10:59 PM PDT 24
Finished Mar 17 02:11:25 PM PDT 24
Peak memory 203744 kb
Host smart-c42d8797-7b9c-4581-adad-acd7e335324c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3292886596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3292886596
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1362613449
Short name T660
Test name
Test status
Simulation time 57701419 ps
CPU time 2.43 seconds
Started Mar 17 02:10:59 PM PDT 24
Finished Mar 17 02:11:02 PM PDT 24
Peak memory 203728 kb
Host smart-24504597-7bc7-4649-bda5-af18dbc321ca
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362613449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1362613449
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2654257008
Short name T588
Test name
Test status
Simulation time 4136270535 ps
CPU time 103.18 seconds
Started Mar 17 02:11:04 PM PDT 24
Finished Mar 17 02:12:47 PM PDT 24
Peak memory 208504 kb
Host smart-21fd987d-3cb5-4cdb-b10e-372f2687220d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2654257008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2654257008
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3969468618
Short name T404
Test name
Test status
Simulation time 3773579655 ps
CPU time 46.04 seconds
Started Mar 17 02:11:05 PM PDT 24
Finished Mar 17 02:11:51 PM PDT 24
Peak memory 204860 kb
Host smart-ffab973e-5f95-420a-bb37-d65abb689608
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3969468618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3969468618
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2486071885
Short name T353
Test name
Test status
Simulation time 192210186 ps
CPU time 75.55 seconds
Started Mar 17 02:11:06 PM PDT 24
Finished Mar 17 02:12:21 PM PDT 24
Peak memory 207296 kb
Host smart-ae992c47-ce7a-41ef-be87-a1fe5ffc5e50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2486071885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.2486071885
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1230454386
Short name T665
Test name
Test status
Simulation time 207261519 ps
CPU time 80.76 seconds
Started Mar 17 02:11:05 PM PDT 24
Finished Mar 17 02:12:26 PM PDT 24
Peak memory 208952 kb
Host smart-c153521e-17b1-4779-88d0-db5c50dcf7de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1230454386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1230454386
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3372770254
Short name T681
Test name
Test status
Simulation time 401357438 ps
CPU time 13.48 seconds
Started Mar 17 02:11:03 PM PDT 24
Finished Mar 17 02:11:17 PM PDT 24
Peak memory 205164 kb
Host smart-c734f7a6-315a-417c-aafc-f8f79b14f7a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3372770254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3372770254
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1662950769
Short name T620
Test name
Test status
Simulation time 264294284 ps
CPU time 13.81 seconds
Started Mar 17 02:11:04 PM PDT 24
Finished Mar 17 02:11:18 PM PDT 24
Peak memory 204352 kb
Host smart-97e5f3ce-2f42-4344-99ac-0fe9212bf604
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1662950769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1662950769
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2625126260
Short name T753
Test name
Test status
Simulation time 64103049047 ps
CPU time 353.31 seconds
Started Mar 17 02:11:05 PM PDT 24
Finished Mar 17 02:16:59 PM PDT 24
Peak memory 212008 kb
Host smart-b3876771-bc08-4030-9a58-f8a75357c1e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2625126260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.2625126260
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2754479523
Short name T9
Test name
Test status
Simulation time 92928249 ps
CPU time 3.84 seconds
Started Mar 17 02:11:14 PM PDT 24
Finished Mar 17 02:11:17 PM PDT 24
Peak memory 203612 kb
Host smart-5fc5292b-4d89-430b-8b60-97b588aca7df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2754479523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2754479523
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.1979564592
Short name T803
Test name
Test status
Simulation time 37404192 ps
CPU time 5.9 seconds
Started Mar 17 02:11:10 PM PDT 24
Finished Mar 17 02:11:16 PM PDT 24
Peak memory 203680 kb
Host smart-bd20685b-874a-4dda-9fc0-305de7e186a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1979564592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1979564592
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.3358001139
Short name T431
Test name
Test status
Simulation time 46187932 ps
CPU time 2.1 seconds
Started Mar 17 02:11:06 PM PDT 24
Finished Mar 17 02:11:09 PM PDT 24
Peak memory 203740 kb
Host smart-c314ad7a-c4dd-4ef2-8371-1f6e8dca067c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3358001139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3358001139
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1312933670
Short name T828
Test name
Test status
Simulation time 54737700226 ps
CPU time 239.35 seconds
Started Mar 17 02:11:03 PM PDT 24
Finished Mar 17 02:15:03 PM PDT 24
Peak memory 211940 kb
Host smart-f515730b-13c3-47de-b1cc-1f63dac4adc1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312933670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1312933670
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2558528172
Short name T45
Test name
Test status
Simulation time 4429976107 ps
CPU time 33.74 seconds
Started Mar 17 02:11:07 PM PDT 24
Finished Mar 17 02:11:41 PM PDT 24
Peak memory 204588 kb
Host smart-af061828-fa2e-47fb-ab5c-c05d8f1c2000
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2558528172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2558528172
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1306194200
Short name T719
Test name
Test status
Simulation time 125770517 ps
CPU time 15.29 seconds
Started Mar 17 02:11:04 PM PDT 24
Finished Mar 17 02:11:19 PM PDT 24
Peak memory 205136 kb
Host smart-e865ad69-d887-4bb1-9520-a3615766a781
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306194200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1306194200
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.533004756
Short name T241
Test name
Test status
Simulation time 1508360313 ps
CPU time 21.33 seconds
Started Mar 17 02:11:11 PM PDT 24
Finished Mar 17 02:11:33 PM PDT 24
Peak memory 203680 kb
Host smart-1fe98f7f-d936-4e0b-bb4b-9d95d50e405b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=533004756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.533004756
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1460176530
Short name T243
Test name
Test status
Simulation time 24843062 ps
CPU time 2.39 seconds
Started Mar 17 02:11:05 PM PDT 24
Finished Mar 17 02:11:07 PM PDT 24
Peak memory 203684 kb
Host smart-1089478f-345a-4fd6-a23a-348f34b4bf5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1460176530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1460176530
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.520203438
Short name T597
Test name
Test status
Simulation time 5121206425 ps
CPU time 28.35 seconds
Started Mar 17 02:11:06 PM PDT 24
Finished Mar 17 02:11:34 PM PDT 24
Peak memory 203808 kb
Host smart-a6cc20fd-36e1-4d34-b17d-f9f87f3ee04c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=520203438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.520203438
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3804732507
Short name T840
Test name
Test status
Simulation time 4758981242 ps
CPU time 27.48 seconds
Started Mar 17 02:11:03 PM PDT 24
Finished Mar 17 02:11:30 PM PDT 24
Peak memory 203752 kb
Host smart-97f658f9-734e-4781-953e-dc1e85f186c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3804732507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3804732507
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2861783099
Short name T247
Test name
Test status
Simulation time 27402496 ps
CPU time 2.42 seconds
Started Mar 17 02:11:04 PM PDT 24
Finished Mar 17 02:11:06 PM PDT 24
Peak memory 203668 kb
Host smart-b19e34cd-7668-4ee7-89ad-9482aefcf1ba
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861783099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2861783099
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.4068747857
Short name T263
Test name
Test status
Simulation time 592604532 ps
CPU time 70.33 seconds
Started Mar 17 02:11:13 PM PDT 24
Finished Mar 17 02:12:24 PM PDT 24
Peak memory 207092 kb
Host smart-6048eaad-593c-455f-8565-98745a07cdc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4068747857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4068747857
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.372648473
Short name T238
Test name
Test status
Simulation time 160646943 ps
CPU time 20.43 seconds
Started Mar 17 02:11:10 PM PDT 24
Finished Mar 17 02:11:31 PM PDT 24
Peak memory 203692 kb
Host smart-a1a5fb1b-4640-437b-a67d-43daba1ee9d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=372648473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.372648473
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3828670534
Short name T356
Test name
Test status
Simulation time 671037688 ps
CPU time 248.81 seconds
Started Mar 17 02:11:14 PM PDT 24
Finished Mar 17 02:15:23 PM PDT 24
Peak memory 220576 kb
Host smart-ada88004-771c-447e-832b-fc4be889fe55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3828670534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.3828670534
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1897883756
Short name T774
Test name
Test status
Simulation time 503829620 ps
CPU time 17.83 seconds
Started Mar 17 02:11:09 PM PDT 24
Finished Mar 17 02:11:27 PM PDT 24
Peak memory 204900 kb
Host smart-42e792b2-81e1-4baa-85c8-f36d260d9af6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1897883756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1897883756
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2343122255
Short name T157
Test name
Test status
Simulation time 21293985081 ps
CPU time 105.13 seconds
Started Mar 17 02:11:16 PM PDT 24
Finished Mar 17 02:13:02 PM PDT 24
Peak memory 204916 kb
Host smart-8d0e7e02-96c1-471a-a9a5-a0132b465354
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2343122255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.2343122255
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.302303135
Short name T757
Test name
Test status
Simulation time 598657258 ps
CPU time 16.18 seconds
Started Mar 17 02:11:20 PM PDT 24
Finished Mar 17 02:11:37 PM PDT 24
Peak memory 204212 kb
Host smart-84b70921-037b-44c9-9720-2c9a22f6267d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=302303135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.302303135
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.3257671664
Short name T310
Test name
Test status
Simulation time 257919059 ps
CPU time 21.94 seconds
Started Mar 17 02:11:16 PM PDT 24
Finished Mar 17 02:11:38 PM PDT 24
Peak memory 203656 kb
Host smart-1917961b-8742-4a2c-b07b-e4bf45ae965d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3257671664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3257671664
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.1821102754
Short name T838
Test name
Test status
Simulation time 224506593 ps
CPU time 30.52 seconds
Started Mar 17 02:11:17 PM PDT 24
Finished Mar 17 02:11:48 PM PDT 24
Peak memory 211912 kb
Host smart-7338fbf5-e845-4d91-ae91-63792b7a1042
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1821102754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1821102754
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3330032928
Short name T115
Test name
Test status
Simulation time 116353520916 ps
CPU time 254.73 seconds
Started Mar 17 02:11:18 PM PDT 24
Finished Mar 17 02:15:33 PM PDT 24
Peak memory 205376 kb
Host smart-5b2a2bf3-ba64-4f18-b183-a06cf123ff5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330032928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3330032928
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.857658444
Short name T119
Test name
Test status
Simulation time 6671194709 ps
CPU time 37.97 seconds
Started Mar 17 02:11:16 PM PDT 24
Finished Mar 17 02:11:54 PM PDT 24
Peak memory 204840 kb
Host smart-b174e9c5-0628-4062-93e4-ff95b1e625ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=857658444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.857658444
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2049530268
Short name T799
Test name
Test status
Simulation time 288711196 ps
CPU time 26.93 seconds
Started Mar 17 02:11:17 PM PDT 24
Finished Mar 17 02:11:44 PM PDT 24
Peak memory 204948 kb
Host smart-f32e9c67-7473-4c08-b311-84b0865dddb3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049530268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2049530268
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.998561989
Short name T742
Test name
Test status
Simulation time 841647551 ps
CPU time 19.62 seconds
Started Mar 17 02:11:18 PM PDT 24
Finished Mar 17 02:11:38 PM PDT 24
Peak memory 204228 kb
Host smart-6fc7e023-8f2d-48c0-856c-165e58d68e1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=998561989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.998561989
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.3982029452
Short name T439
Test name
Test status
Simulation time 129658709 ps
CPU time 3.8 seconds
Started Mar 17 02:11:13 PM PDT 24
Finished Mar 17 02:11:17 PM PDT 24
Peak memory 203612 kb
Host smart-8f42411b-006d-4a5d-baae-e26e0d8f87e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3982029452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3982029452
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.126328874
Short name T195
Test name
Test status
Simulation time 26815023453 ps
CPU time 45.15 seconds
Started Mar 17 02:11:17 PM PDT 24
Finished Mar 17 02:12:02 PM PDT 24
Peak memory 203784 kb
Host smart-309da194-9f21-4358-abee-b33e217b751c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=126328874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.126328874
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1693312475
Short name T257
Test name
Test status
Simulation time 5497975882 ps
CPU time 31.04 seconds
Started Mar 17 02:11:16 PM PDT 24
Finished Mar 17 02:11:47 PM PDT 24
Peak memory 203768 kb
Host smart-8d3be46a-df19-4ce1-9764-adb8de99a1d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1693312475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1693312475
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2624970209
Short name T196
Test name
Test status
Simulation time 33630145 ps
CPU time 2.65 seconds
Started Mar 17 02:11:10 PM PDT 24
Finished Mar 17 02:11:13 PM PDT 24
Peak memory 203712 kb
Host smart-ff6c1806-8e84-4004-99fd-4154fbebda57
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624970209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2624970209
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3523249819
Short name T440
Test name
Test status
Simulation time 6137499116 ps
CPU time 186.57 seconds
Started Mar 17 02:11:22 PM PDT 24
Finished Mar 17 02:14:29 PM PDT 24
Peak memory 207740 kb
Host smart-da2a56bd-09d9-4119-b224-a41cc7a42d4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3523249819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3523249819
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.146695515
Short name T274
Test name
Test status
Simulation time 1719197670 ps
CPU time 17.75 seconds
Started Mar 17 02:11:20 PM PDT 24
Finished Mar 17 02:11:38 PM PDT 24
Peak memory 203864 kb
Host smart-dd2e28fb-0411-49b4-b80f-eb419af837c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=146695515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.146695515
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2101117966
Short name T413
Test name
Test status
Simulation time 5958455264 ps
CPU time 102.59 seconds
Started Mar 17 02:11:23 PM PDT 24
Finished Mar 17 02:13:05 PM PDT 24
Peak memory 208404 kb
Host smart-292a0139-d519-4c33-beec-b8cfe5f4185b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2101117966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.2101117966
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3029251698
Short name T32
Test name
Test status
Simulation time 455043307 ps
CPU time 128.71 seconds
Started Mar 17 02:11:21 PM PDT 24
Finished Mar 17 02:13:30 PM PDT 24
Peak memory 209564 kb
Host smart-330e3948-9d5a-46fb-9363-cd84af7eecc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3029251698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.3029251698
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.791732993
Short name T494
Test name
Test status
Simulation time 61997087 ps
CPU time 2.39 seconds
Started Mar 17 02:11:15 PM PDT 24
Finished Mar 17 02:11:18 PM PDT 24
Peak memory 203708 kb
Host smart-69924842-1bc5-413c-a3c9-12348588dfae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=791732993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.791732993
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3486735121
Short name T559
Test name
Test status
Simulation time 206498334 ps
CPU time 10.09 seconds
Started Mar 17 02:11:30 PM PDT 24
Finished Mar 17 02:11:40 PM PDT 24
Peak memory 204428 kb
Host smart-28bae2ab-2d97-45f7-953e-cff10dbac881
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3486735121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3486735121
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1490535568
Short name T777
Test name
Test status
Simulation time 154126122577 ps
CPU time 640.15 seconds
Started Mar 17 02:11:28 PM PDT 24
Finished Mar 17 02:22:08 PM PDT 24
Peak memory 206252 kb
Host smart-568c8e80-ef1b-4f72-a46a-a034ee45b724
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1490535568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.1490535568
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2821060114
Short name T645
Test name
Test status
Simulation time 380592733 ps
CPU time 8.73 seconds
Started Mar 17 02:11:34 PM PDT 24
Finished Mar 17 02:11:43 PM PDT 24
Peak memory 203964 kb
Host smart-c789be7a-cef3-4ccc-a945-bf9754343b31
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2821060114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2821060114
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.2155848108
Short name T249
Test name
Test status
Simulation time 616088469 ps
CPU time 15.83 seconds
Started Mar 17 02:11:28 PM PDT 24
Finished Mar 17 02:11:44 PM PDT 24
Peak memory 203720 kb
Host smart-bf4bf839-4dda-4861-b809-d0709ac69d25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2155848108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2155848108
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.3558120333
Short name T537
Test name
Test status
Simulation time 288645991 ps
CPU time 9.07 seconds
Started Mar 17 02:11:22 PM PDT 24
Finished Mar 17 02:11:31 PM PDT 24
Peak memory 211924 kb
Host smart-03272fc4-6167-4f55-9752-8bf53ee5a246
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558120333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3558120333
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2203076799
Short name T328
Test name
Test status
Simulation time 72605503212 ps
CPU time 164.74 seconds
Started Mar 17 02:11:28 PM PDT 24
Finished Mar 17 02:14:13 PM PDT 24
Peak memory 205152 kb
Host smart-56ae0e6d-ff22-4d9d-8afa-68c985c480fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203076799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2203076799
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3527555752
Short name T727
Test name
Test status
Simulation time 90233513747 ps
CPU time 170.93 seconds
Started Mar 17 02:11:28 PM PDT 24
Finished Mar 17 02:14:19 PM PDT 24
Peak memory 205116 kb
Host smart-178c0172-b53d-4e09-b78f-cab10c4e9aed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3527555752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3527555752
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2648190661
Short name T44
Test name
Test status
Simulation time 203528956 ps
CPU time 12.37 seconds
Started Mar 17 02:11:28 PM PDT 24
Finished Mar 17 02:11:41 PM PDT 24
Peak memory 205060 kb
Host smart-34e13238-730e-47ab-b77b-4f475cc7452b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648190661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2648190661
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.3732654264
Short name T577
Test name
Test status
Simulation time 762368035 ps
CPU time 7.96 seconds
Started Mar 17 02:11:28 PM PDT 24
Finished Mar 17 02:11:36 PM PDT 24
Peak memory 204708 kb
Host smart-e7ac5fb0-882e-4edd-a74c-c7192d206a3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3732654264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3732654264
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.3569676485
Short name T131
Test name
Test status
Simulation time 246509300 ps
CPU time 3.86 seconds
Started Mar 17 02:11:23 PM PDT 24
Finished Mar 17 02:11:27 PM PDT 24
Peak memory 203704 kb
Host smart-2e3ddcfc-f408-485c-8f01-f2ecbb04b8a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3569676485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3569676485
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.91173858
Short name T852
Test name
Test status
Simulation time 9125683232 ps
CPU time 30.69 seconds
Started Mar 17 02:11:21 PM PDT 24
Finished Mar 17 02:11:51 PM PDT 24
Peak memory 203808 kb
Host smart-4d2a6a9c-2230-40dd-af68-b9992bb7479b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=91173858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.91173858
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1299435487
Short name T37
Test name
Test status
Simulation time 14135134297 ps
CPU time 32.3 seconds
Started Mar 17 02:11:19 PM PDT 24
Finished Mar 17 02:11:51 PM PDT 24
Peak memory 203688 kb
Host smart-704f34bc-028d-4665-b1c1-9a357e8f846a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1299435487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1299435487
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.4218232732
Short name T42
Test name
Test status
Simulation time 45150517 ps
CPU time 2.11 seconds
Started Mar 17 02:11:20 PM PDT 24
Finished Mar 17 02:11:22 PM PDT 24
Peak memory 203692 kb
Host smart-a04e85be-c651-4828-b06c-51865e9d99ae
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218232732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.4218232732
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.6491023
Short name T467
Test name
Test status
Simulation time 6137439794 ps
CPU time 221.54 seconds
Started Mar 17 02:11:35 PM PDT 24
Finished Mar 17 02:15:16 PM PDT 24
Peak memory 207692 kb
Host smart-515fe822-dec5-498a-a648-abfe651dc5a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6491023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.6491023
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3251254701
Short name T205
Test name
Test status
Simulation time 249077155 ps
CPU time 10.49 seconds
Started Mar 17 02:11:34 PM PDT 24
Finished Mar 17 02:11:45 PM PDT 24
Peak memory 203800 kb
Host smart-a53b637f-bc36-4289-b4af-ae63c085c956
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3251254701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3251254701
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.966012919
Short name T458
Test name
Test status
Simulation time 125068795 ps
CPU time 22.76 seconds
Started Mar 17 02:11:37 PM PDT 24
Finished Mar 17 02:12:00 PM PDT 24
Peak memory 206296 kb
Host smart-3c816183-b5a0-4a78-9e44-95f71bc347b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=966012919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res
et_error.966012919
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2901590039
Short name T879
Test name
Test status
Simulation time 178312397 ps
CPU time 7.21 seconds
Started Mar 17 02:11:36 PM PDT 24
Finished Mar 17 02:11:44 PM PDT 24
Peak memory 211884 kb
Host smart-cf2d7aec-edbc-41ae-b378-db90b5275949
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2901590039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2901590039
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3763597617
Short name T108
Test name
Test status
Simulation time 481415751 ps
CPU time 40.09 seconds
Started Mar 17 02:11:41 PM PDT 24
Finished Mar 17 02:12:21 PM PDT 24
Peak memory 204868 kb
Host smart-bf54fb64-627b-4aa6-a84d-3aae77b308a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3763597617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3763597617
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2989661510
Short name T84
Test name
Test status
Simulation time 78206994908 ps
CPU time 489.52 seconds
Started Mar 17 02:11:46 PM PDT 24
Finished Mar 17 02:19:56 PM PDT 24
Peak memory 206132 kb
Host smart-cf5a4090-87d0-475e-930f-6baad9521002
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2989661510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.2989661510
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1543973347
Short name T366
Test name
Test status
Simulation time 67384335 ps
CPU time 10.16 seconds
Started Mar 17 02:11:39 PM PDT 24
Finished Mar 17 02:11:49 PM PDT 24
Peak memory 204120 kb
Host smart-208b34e8-0059-4fbd-9f28-093867e319ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1543973347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1543973347
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.768478974
Short name T66
Test name
Test status
Simulation time 265188482 ps
CPU time 22.77 seconds
Started Mar 17 02:11:46 PM PDT 24
Finished Mar 17 02:12:09 PM PDT 24
Peak memory 203592 kb
Host smart-4d32c646-f5f9-44e0-a19d-e1656a25971f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=768478974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.768478974
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.2921035279
Short name T194
Test name
Test status
Simulation time 1401219690 ps
CPU time 38.38 seconds
Started Mar 17 02:11:40 PM PDT 24
Finished Mar 17 02:12:18 PM PDT 24
Peak memory 204988 kb
Host smart-7267d6be-c9dd-4cff-80d3-bacaaba2ecf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2921035279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2921035279
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1295227271
Short name T324
Test name
Test status
Simulation time 58564284751 ps
CPU time 207.74 seconds
Started Mar 17 02:11:40 PM PDT 24
Finished Mar 17 02:15:07 PM PDT 24
Peak memory 205392 kb
Host smart-cf858dcf-b1de-4fa6-acfc-f1fa84d1ab41
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295227271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1295227271
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1832905652
Short name T637
Test name
Test status
Simulation time 10263557117 ps
CPU time 89.54 seconds
Started Mar 17 02:11:46 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 211928 kb
Host smart-9a1979b8-ff1c-4674-9180-b47a1a41ec42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1832905652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1832905652
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3370772502
Short name T744
Test name
Test status
Simulation time 80582428 ps
CPU time 8.25 seconds
Started Mar 17 02:11:40 PM PDT 24
Finished Mar 17 02:11:49 PM PDT 24
Peak memory 204824 kb
Host smart-1cf6cf09-9f0a-473e-be09-45d44e142caa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370772502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3370772502
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.661857337
Short name T868
Test name
Test status
Simulation time 780868513 ps
CPU time 19.9 seconds
Started Mar 17 02:11:46 PM PDT 24
Finished Mar 17 02:12:06 PM PDT 24
Peak memory 204288 kb
Host smart-2ebd3601-8daf-49b7-b8c9-1ae7e5b4d848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=661857337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.661857337
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.2625435887
Short name T807
Test name
Test status
Simulation time 130267862 ps
CPU time 3.28 seconds
Started Mar 17 02:11:35 PM PDT 24
Finished Mar 17 02:11:40 PM PDT 24
Peak memory 203696 kb
Host smart-13c1e99c-9e5a-48de-a93b-407248b8aee9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2625435887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2625435887
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3506667041
Short name T530
Test name
Test status
Simulation time 4249481402 ps
CPU time 26.35 seconds
Started Mar 17 02:11:36 PM PDT 24
Finished Mar 17 02:12:03 PM PDT 24
Peak memory 203788 kb
Host smart-e3894fe1-5170-4cea-b2e1-b69c879b6625
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506667041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3506667041
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2831472702
Short name T853
Test name
Test status
Simulation time 6182848828 ps
CPU time 33.53 seconds
Started Mar 17 02:11:35 PM PDT 24
Finished Mar 17 02:12:08 PM PDT 24
Peak memory 203748 kb
Host smart-e4b30d3a-7f9a-406b-91b2-12048b4ffef0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2831472702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2831472702
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1232336709
Short name T289
Test name
Test status
Simulation time 26433055 ps
CPU time 2.63 seconds
Started Mar 17 02:11:36 PM PDT 24
Finished Mar 17 02:11:39 PM PDT 24
Peak memory 203708 kb
Host smart-125e0e74-71f3-4944-b66e-d12205d43331
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232336709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1232336709
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2835591353
Short name T533
Test name
Test status
Simulation time 1987518441 ps
CPU time 186.94 seconds
Started Mar 17 02:11:39 PM PDT 24
Finished Mar 17 02:14:47 PM PDT 24
Peak memory 208960 kb
Host smart-aaf3d5d5-cc13-440c-9733-2cd6fb5675ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2835591353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2835591353
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3770616717
Short name T370
Test name
Test status
Simulation time 4707045728 ps
CPU time 154.72 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:14:20 PM PDT 24
Peak memory 209068 kb
Host smart-0de3cdb5-78a3-494a-956d-242622e8e2e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3770616717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3770616717
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.647655441
Short name T96
Test name
Test status
Simulation time 3196052016 ps
CPU time 157.83 seconds
Started Mar 17 02:11:38 PM PDT 24
Finished Mar 17 02:14:17 PM PDT 24
Peak memory 209492 kb
Host smart-33c3df3a-1639-4c36-8646-8e4e1c22d5bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=647655441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand
_reset.647655441
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1725194472
Short name T688
Test name
Test status
Simulation time 58835808 ps
CPU time 12.12 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:11:58 PM PDT 24
Peak memory 204652 kb
Host smart-b510f98f-9c85-4c62-b1e5-865a69cf66cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1725194472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.1725194472
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2382229023
Short name T89
Test name
Test status
Simulation time 2862562778 ps
CPU time 26.83 seconds
Started Mar 17 02:11:38 PM PDT 24
Finished Mar 17 02:12:05 PM PDT 24
Peak memory 205296 kb
Host smart-eb8d1b65-69b1-4faa-bb10-99995bfe714e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2382229023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2382229023
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1580047645
Short name T187
Test name
Test status
Simulation time 836267850 ps
CPU time 30.98 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:12:17 PM PDT 24
Peak memory 205464 kb
Host smart-3fd35159-186c-4bbb-9310-fdfb71b8ac86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1580047645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1580047645
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3010662178
Short name T216
Test name
Test status
Simulation time 56700761072 ps
CPU time 231.76 seconds
Started Mar 17 02:11:44 PM PDT 24
Finished Mar 17 02:15:37 PM PDT 24
Peak memory 206588 kb
Host smart-368a1273-985c-41de-bada-f9e8edf2d2bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3010662178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.3010662178
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3519190720
Short name T656
Test name
Test status
Simulation time 180559378 ps
CPU time 16.73 seconds
Started Mar 17 02:11:50 PM PDT 24
Finished Mar 17 02:12:07 PM PDT 24
Peak memory 203872 kb
Host smart-53347bd7-1b22-49c1-a4c6-78764c7dbf65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3519190720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3519190720
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.3760557649
Short name T235
Test name
Test status
Simulation time 321310933 ps
CPU time 23.49 seconds
Started Mar 17 02:11:51 PM PDT 24
Finished Mar 17 02:12:14 PM PDT 24
Peak memory 203688 kb
Host smart-dd237e80-2a66-43ca-b72a-a345aece7d7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3760557649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3760557649
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.4206470443
Short name T272
Test name
Test status
Simulation time 85209414 ps
CPU time 9.58 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:11:55 PM PDT 24
Peak memory 211852 kb
Host smart-2535d895-d022-441a-89c9-8a5346b0071e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4206470443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.4206470443
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.32708762
Short name T798
Test name
Test status
Simulation time 214233033081 ps
CPU time 266.84 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:16:13 PM PDT 24
Peak memory 211980 kb
Host smart-0a61aa23-8620-4886-8efb-20d4c12a8bad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=32708762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.32708762
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2615300880
Short name T498
Test name
Test status
Simulation time 26240585474 ps
CPU time 50.31 seconds
Started Mar 17 02:11:46 PM PDT 24
Finished Mar 17 02:12:37 PM PDT 24
Peak memory 211980 kb
Host smart-51438d56-8ee9-4916-8d03-cdb007e166f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2615300880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2615300880
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1453927773
Short name T320
Test name
Test status
Simulation time 442722166 ps
CPU time 26.03 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:12:12 PM PDT 24
Peak memory 204868 kb
Host smart-6dbe6136-ef95-4b31-8409-72e546f324f6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453927773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1453927773
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.118223102
Short name T521
Test name
Test status
Simulation time 436199660 ps
CPU time 15.35 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:12:01 PM PDT 24
Peak memory 204160 kb
Host smart-916abee3-7f46-404a-849f-284b2b7d888a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=118223102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.118223102
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.2962248507
Short name T47
Test name
Test status
Simulation time 393060563 ps
CPU time 3.82 seconds
Started Mar 17 02:11:44 PM PDT 24
Finished Mar 17 02:11:49 PM PDT 24
Peak memory 203652 kb
Host smart-f49cef68-91dc-4203-8828-4b3efee365db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2962248507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2962248507
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1552697668
Short name T301
Test name
Test status
Simulation time 9040600005 ps
CPU time 33.82 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:12:20 PM PDT 24
Peak memory 203700 kb
Host smart-c782b067-088e-4658-b399-e064e254aef5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552697668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1552697668
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4147305102
Short name T723
Test name
Test status
Simulation time 6456490574 ps
CPU time 36.92 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:12:23 PM PDT 24
Peak memory 203760 kb
Host smart-f08fbf21-c19e-4b97-8d6d-4302f3d474dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4147305102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4147305102
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1331353854
Short name T626
Test name
Test status
Simulation time 182093609 ps
CPU time 2.64 seconds
Started Mar 17 02:11:45 PM PDT 24
Finished Mar 17 02:11:48 PM PDT 24
Peak memory 203672 kb
Host smart-519bcd04-9300-4ed6-b2fa-48922e8f4dfd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331353854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1331353854
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2510813374
Short name T733
Test name
Test status
Simulation time 5651490214 ps
CPU time 268.02 seconds
Started Mar 17 02:11:53 PM PDT 24
Finished Mar 17 02:16:21 PM PDT 24
Peak memory 211120 kb
Host smart-bb549610-b8d1-4702-9f9c-bf15678dff74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2510813374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2510813374
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2256071917
Short name T273
Test name
Test status
Simulation time 188764384 ps
CPU time 25.58 seconds
Started Mar 17 02:11:53 PM PDT 24
Finished Mar 17 02:12:19 PM PDT 24
Peak memory 203868 kb
Host smart-c01a48bd-4047-4950-b843-3e89e0f7c2a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2256071917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2256071917
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3422582059
Short name T133
Test name
Test status
Simulation time 1843681637 ps
CPU time 264.15 seconds
Started Mar 17 02:11:52 PM PDT 24
Finished Mar 17 02:16:16 PM PDT 24
Peak memory 208724 kb
Host smart-5233dd57-012b-4786-b0ea-cb01ee62659c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3422582059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.3422582059
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1196759426
Short name T643
Test name
Test status
Simulation time 4421908931 ps
CPU time 177.46 seconds
Started Mar 17 02:11:51 PM PDT 24
Finished Mar 17 02:14:48 PM PDT 24
Peak memory 211492 kb
Host smart-80fd60d4-5fcc-45a8-8e8e-1d2d28323dc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196759426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.1196759426
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.486209000
Short name T825
Test name
Test status
Simulation time 2613472025 ps
CPU time 37.88 seconds
Started Mar 17 02:11:51 PM PDT 24
Finished Mar 17 02:12:29 PM PDT 24
Peak memory 205156 kb
Host smart-1f348958-59d5-4c01-8e43-66f26db231bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=486209000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.486209000
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.4123839629
Short name T189
Test name
Test status
Simulation time 1642364469 ps
CPU time 43.77 seconds
Started Mar 17 02:11:56 PM PDT 24
Finished Mar 17 02:12:39 PM PDT 24
Peak memory 205504 kb
Host smart-acbf648d-b9a9-4adc-a931-2a0c809e6445
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4123839629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4123839629
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3713101950
Short name T148
Test name
Test status
Simulation time 32925129139 ps
CPU time 229.06 seconds
Started Mar 17 02:12:01 PM PDT 24
Finished Mar 17 02:15:51 PM PDT 24
Peak memory 206724 kb
Host smart-3c722bb7-dc04-434b-96f8-44d61618dac2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3713101950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.3713101950
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1612523813
Short name T201
Test name
Test status
Simulation time 115572369 ps
CPU time 2.82 seconds
Started Mar 17 02:12:01 PM PDT 24
Finished Mar 17 02:12:04 PM PDT 24
Peak memory 203616 kb
Host smart-c8458246-68e5-4cb6-b12f-0a8c0c00e344
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1612523813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1612523813
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.4060705483
Short name T867
Test name
Test status
Simulation time 32704273 ps
CPU time 2.45 seconds
Started Mar 17 02:11:56 PM PDT 24
Finished Mar 17 02:11:59 PM PDT 24
Peak memory 203784 kb
Host smart-769cf59c-e2fd-4856-9996-49051f987be3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4060705483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4060705483
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.145587450
Short name T68
Test name
Test status
Simulation time 936473163 ps
CPU time 40.22 seconds
Started Mar 17 02:11:50 PM PDT 24
Finished Mar 17 02:12:31 PM PDT 24
Peak memory 204700 kb
Host smart-913744eb-011a-4fd7-8657-1b3a7ab842b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=145587450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.145587450
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3242155485
Short name T638
Test name
Test status
Simulation time 20515161717 ps
CPU time 115.25 seconds
Started Mar 17 02:11:58 PM PDT 24
Finished Mar 17 02:13:53 PM PDT 24
Peak memory 205100 kb
Host smart-d2902f7b-e46e-4057-8bdf-6980f43eb5d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242155485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3242155485
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3288532093
Short name T83
Test name
Test status
Simulation time 18050226913 ps
CPU time 77.59 seconds
Started Mar 17 02:11:56 PM PDT 24
Finished Mar 17 02:13:14 PM PDT 24
Peak memory 211992 kb
Host smart-b2425047-e94c-4540-ae78-607e31c0a78f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3288532093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3288532093
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.861397921
Short name T790
Test name
Test status
Simulation time 166016674 ps
CPU time 16.5 seconds
Started Mar 17 02:11:51 PM PDT 24
Finished Mar 17 02:12:08 PM PDT 24
Peak memory 211932 kb
Host smart-7225be69-9504-4fb1-9d04-3530231b78e1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861397921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.861397921
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.2752194955
Short name T519
Test name
Test status
Simulation time 1973225178 ps
CPU time 30.9 seconds
Started Mar 17 02:11:57 PM PDT 24
Finished Mar 17 02:12:28 PM PDT 24
Peak memory 204300 kb
Host smart-2050eaff-5415-430b-91de-bd76a6a740e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2752194955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2752194955
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.3899952887
Short name T505
Test name
Test status
Simulation time 184254587 ps
CPU time 3.83 seconds
Started Mar 17 02:11:52 PM PDT 24
Finished Mar 17 02:11:56 PM PDT 24
Peak memory 203700 kb
Host smart-74680d75-fb02-40ca-8c1e-5a1d1ac2f32c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3899952887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3899952887
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3949783419
Short name T752
Test name
Test status
Simulation time 4634922955 ps
CPU time 27 seconds
Started Mar 17 02:11:51 PM PDT 24
Finished Mar 17 02:12:18 PM PDT 24
Peak memory 203800 kb
Host smart-6b58e9e0-57bb-47db-878d-ba975839442e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949783419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3949783419
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.4057236496
Short name T321
Test name
Test status
Simulation time 13421743153 ps
CPU time 25.08 seconds
Started Mar 17 02:11:52 PM PDT 24
Finished Mar 17 02:12:18 PM PDT 24
Peak memory 203804 kb
Host smart-0b3ed4ba-b169-455b-89ba-8b415e618c3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4057236496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.4057236496
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.137244851
Short name T598
Test name
Test status
Simulation time 26141163 ps
CPU time 2.28 seconds
Started Mar 17 02:11:51 PM PDT 24
Finished Mar 17 02:11:53 PM PDT 24
Peak memory 203744 kb
Host smart-ffea8f2d-176e-45c2-8fc3-4f1b910134ae
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137244851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.137244851
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3903141530
Short name T338
Test name
Test status
Simulation time 903039875 ps
CPU time 117.12 seconds
Started Mar 17 02:12:01 PM PDT 24
Finished Mar 17 02:13:58 PM PDT 24
Peak memory 207508 kb
Host smart-45742890-842e-419b-a6cc-0f895463beba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3903141530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3903141530
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2704526775
Short name T470
Test name
Test status
Simulation time 1929095702 ps
CPU time 92.18 seconds
Started Mar 17 02:12:01 PM PDT 24
Finished Mar 17 02:13:33 PM PDT 24
Peak memory 207932 kb
Host smart-ba10f73f-9daa-42fc-b8b9-b8e4246d6f08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2704526775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2704526775
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.162145516
Short name T30
Test name
Test status
Simulation time 16580055452 ps
CPU time 301.79 seconds
Started Mar 17 02:12:00 PM PDT 24
Finished Mar 17 02:17:02 PM PDT 24
Peak memory 210584 kb
Host smart-24bb91e7-533d-48f1-b027-610da94d08b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=162145516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand
_reset.162145516
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.59984305
Short name T326
Test name
Test status
Simulation time 1370499860 ps
CPU time 269.43 seconds
Started Mar 17 02:12:02 PM PDT 24
Finished Mar 17 02:16:32 PM PDT 24
Peak memory 220140 kb
Host smart-3606e469-2420-4ecf-8c5c-86a5fc8bcfa9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59984305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rese
t_error.59984305
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1791540605
Short name T843
Test name
Test status
Simulation time 320240951 ps
CPU time 24.43 seconds
Started Mar 17 02:12:00 PM PDT 24
Finished Mar 17 02:12:25 PM PDT 24
Peak memory 211836 kb
Host smart-898314bd-5ace-4c0b-ada9-f0bcd2028bbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1791540605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1791540605
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.469328802
Short name T766
Test name
Test status
Simulation time 382252836 ps
CPU time 18.88 seconds
Started Mar 17 02:02:16 PM PDT 24
Finished Mar 17 02:02:35 PM PDT 24
Peak memory 211888 kb
Host smart-8bf824dc-544e-4aee-9570-5447f90e68da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=469328802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.469328802
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2836150170
Short name T100
Test name
Test status
Simulation time 292952798971 ps
CPU time 505.06 seconds
Started Mar 17 02:02:20 PM PDT 24
Finished Mar 17 02:10:45 PM PDT 24
Peak memory 211996 kb
Host smart-bd76df41-301b-40af-b127-aec327c29311
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2836150170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.2836150170
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3625317006
Short name T616
Test name
Test status
Simulation time 44361408 ps
CPU time 4.16 seconds
Started Mar 17 02:02:15 PM PDT 24
Finished Mar 17 02:02:19 PM PDT 24
Peak memory 203720 kb
Host smart-162364bf-865e-4dfe-8c66-73f38c21f630
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3625317006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3625317006
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.3129281184
Short name T831
Test name
Test status
Simulation time 1557173987 ps
CPU time 30.31 seconds
Started Mar 17 02:02:20 PM PDT 24
Finished Mar 17 02:02:50 PM PDT 24
Peak memory 203740 kb
Host smart-b76ff040-c3ab-42c9-b404-13014041f206
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3129281184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3129281184
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.1011410381
Short name T573
Test name
Test status
Simulation time 46107526 ps
CPU time 5.35 seconds
Started Mar 17 02:02:10 PM PDT 24
Finished Mar 17 02:02:15 PM PDT 24
Peak memory 204460 kb
Host smart-840c3982-f752-4800-bb55-e7bb875b09a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1011410381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1011410381
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1428494550
Short name T226
Test name
Test status
Simulation time 22157706022 ps
CPU time 135.09 seconds
Started Mar 17 02:02:10 PM PDT 24
Finished Mar 17 02:04:25 PM PDT 24
Peak memory 205268 kb
Host smart-3804e0cb-d4ba-41e2-b936-9ff68bf3b75d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428494550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1428494550
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2414115052
Short name T817
Test name
Test status
Simulation time 18607435566 ps
CPU time 70.45 seconds
Started Mar 17 02:02:20 PM PDT 24
Finished Mar 17 02:03:31 PM PDT 24
Peak memory 205016 kb
Host smart-71021127-13d1-4e72-a353-e70ec7f8f98c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2414115052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2414115052
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3076246641
Short name T398
Test name
Test status
Simulation time 88893246 ps
CPU time 11.89 seconds
Started Mar 17 02:02:10 PM PDT 24
Finished Mar 17 02:02:22 PM PDT 24
Peak memory 204804 kb
Host smart-2be0d948-c775-42c4-bfc1-69737eea0d45
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076246641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3076246641
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.752425980
Short name T490
Test name
Test status
Simulation time 1340423319 ps
CPU time 25.28 seconds
Started Mar 17 02:02:16 PM PDT 24
Finished Mar 17 02:02:41 PM PDT 24
Peak memory 204260 kb
Host smart-b744556f-525e-4241-b6a7-e2f745a232fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=752425980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.752425980
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.1019682660
Short name T600
Test name
Test status
Simulation time 25971516 ps
CPU time 2.4 seconds
Started Mar 17 02:02:02 PM PDT 24
Finished Mar 17 02:02:04 PM PDT 24
Peak memory 203704 kb
Host smart-1adae3ae-8f99-49fb-9da5-c2b83d57ae48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1019682660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1019682660
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4160404656
Short name T786
Test name
Test status
Simulation time 7083403651 ps
CPU time 35.83 seconds
Started Mar 17 02:02:10 PM PDT 24
Finished Mar 17 02:02:46 PM PDT 24
Peak memory 203728 kb
Host smart-9cf86d83-4d2a-46d5-a0d5-dcd54bfe6364
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160404656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4160404656
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2024936932
Short name T429
Test name
Test status
Simulation time 7866848607 ps
CPU time 31.56 seconds
Started Mar 17 02:02:09 PM PDT 24
Finished Mar 17 02:02:41 PM PDT 24
Peak memory 203800 kb
Host smart-3bad0d59-75fe-4056-8483-83652b912695
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2024936932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2024936932
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1402419838
Short name T516
Test name
Test status
Simulation time 42213174 ps
CPU time 2.58 seconds
Started Mar 17 02:02:09 PM PDT 24
Finished Mar 17 02:02:12 PM PDT 24
Peak memory 203692 kb
Host smart-fc33944f-4445-4712-a017-de5b97acd2af
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402419838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1402419838
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1975600507
Short name T271
Test name
Test status
Simulation time 1247992450 ps
CPU time 127.5 seconds
Started Mar 17 02:02:14 PM PDT 24
Finished Mar 17 02:04:22 PM PDT 24
Peak memory 207744 kb
Host smart-852cdaf2-6ca2-4be1-9845-8de27e370b41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1975600507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1975600507
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3755072715
Short name T315
Test name
Test status
Simulation time 1917479788 ps
CPU time 164.34 seconds
Started Mar 17 02:02:26 PM PDT 24
Finished Mar 17 02:05:10 PM PDT 24
Peak memory 209368 kb
Host smart-d7accf5a-93a7-4a57-83a3-f955325972c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3755072715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3755072715
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3199389897
Short name T561
Test name
Test status
Simulation time 3712425831 ps
CPU time 337.17 seconds
Started Mar 17 02:02:26 PM PDT 24
Finished Mar 17 02:08:03 PM PDT 24
Peak memory 209712 kb
Host smart-71963627-8649-4175-88fe-421ad4ed3789
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3199389897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.3199389897
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1156688374
Short name T382
Test name
Test status
Simulation time 1352673736 ps
CPU time 133.46 seconds
Started Mar 17 02:02:25 PM PDT 24
Finished Mar 17 02:04:39 PM PDT 24
Peak memory 208708 kb
Host smart-207db066-68b9-4ae2-8650-25641a195595
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1156688374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.1156688374
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3364600266
Short name T65
Test name
Test status
Simulation time 281025997 ps
CPU time 25.27 seconds
Started Mar 17 02:02:14 PM PDT 24
Finished Mar 17 02:02:40 PM PDT 24
Peak memory 205024 kb
Host smart-4ada9785-63bf-478b-a0f5-f61481dd7bf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364600266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3364600266
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2248783665
Short name T737
Test name
Test status
Simulation time 1001156380 ps
CPU time 34.49 seconds
Started Mar 17 02:02:32 PM PDT 24
Finished Mar 17 02:03:07 PM PDT 24
Peak memory 204740 kb
Host smart-9539b48c-8808-415b-80e8-8830afe563a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2248783665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2248783665
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1633200791
Short name T781
Test name
Test status
Simulation time 418451639 ps
CPU time 14.9 seconds
Started Mar 17 02:02:32 PM PDT 24
Finished Mar 17 02:02:47 PM PDT 24
Peak memory 203740 kb
Host smart-31893459-2555-4ee9-a510-2e02f397abfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1633200791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1633200791
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.377434297
Short name T222
Test name
Test status
Simulation time 556727797 ps
CPU time 16.86 seconds
Started Mar 17 02:02:34 PM PDT 24
Finished Mar 17 02:02:51 PM PDT 24
Peak memory 203712 kb
Host smart-63e5ac27-1d8b-43ae-9dac-0f75b51e9ed7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=377434297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.377434297
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.3549374507
Short name T848
Test name
Test status
Simulation time 321879259 ps
CPU time 20.88 seconds
Started Mar 17 02:02:32 PM PDT 24
Finished Mar 17 02:02:52 PM PDT 24
Peak memory 205184 kb
Host smart-f7bd4b3c-4044-454d-bb00-5c93201632cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549374507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3549374507
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.4205340840
Short name T455
Test name
Test status
Simulation time 36116313346 ps
CPU time 104.91 seconds
Started Mar 17 02:02:32 PM PDT 24
Finished Mar 17 02:04:17 PM PDT 24
Peak memory 205032 kb
Host smart-928e0219-29b4-475d-9b11-7ab0634623b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205340840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4205340840
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3941346761
Short name T884
Test name
Test status
Simulation time 28905620551 ps
CPU time 134.43 seconds
Started Mar 17 02:02:32 PM PDT 24
Finished Mar 17 02:04:47 PM PDT 24
Peak memory 204816 kb
Host smart-682fdc35-3ab0-4b65-96d5-c99fcee12de0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3941346761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3941346761
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1572379801
Short name T589
Test name
Test status
Simulation time 200443334 ps
CPU time 20.76 seconds
Started Mar 17 02:02:33 PM PDT 24
Finished Mar 17 02:02:53 PM PDT 24
Peak memory 205036 kb
Host smart-95d75394-52e2-48a0-ab6a-d0a775400dfa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572379801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1572379801
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.2717624713
Short name T178
Test name
Test status
Simulation time 331091187 ps
CPU time 6.46 seconds
Started Mar 17 02:02:34 PM PDT 24
Finished Mar 17 02:02:40 PM PDT 24
Peak memory 203712 kb
Host smart-26b45d83-7a8f-4cad-9a39-01068c07633c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2717624713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2717624713
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.2129360208
Short name T812
Test name
Test status
Simulation time 139912555 ps
CPU time 3.52 seconds
Started Mar 17 02:02:25 PM PDT 24
Finished Mar 17 02:02:29 PM PDT 24
Peak memory 203732 kb
Host smart-c41b24a3-087f-4edc-afc5-72749107cb0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2129360208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2129360208
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.49814003
Short name T829
Test name
Test status
Simulation time 12190251630 ps
CPU time 29.04 seconds
Started Mar 17 02:02:26 PM PDT 24
Finished Mar 17 02:02:55 PM PDT 24
Peak memory 203808 kb
Host smart-0c288720-0c63-419d-b554-b6315b4ea9f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=49814003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.49814003
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.630101930
Short name T885
Test name
Test status
Simulation time 3136417508 ps
CPU time 25.66 seconds
Started Mar 17 02:02:26 PM PDT 24
Finished Mar 17 02:02:52 PM PDT 24
Peak memory 203752 kb
Host smart-b13ea47b-2f5c-44d4-9bed-566882c07ae7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=630101930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.630101930
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2420625141
Short name T529
Test name
Test status
Simulation time 27217805 ps
CPU time 2.2 seconds
Started Mar 17 02:02:23 PM PDT 24
Finished Mar 17 02:02:25 PM PDT 24
Peak memory 203692 kb
Host smart-f147078d-0b4a-4130-aed6-3f00b8f357da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420625141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2420625141
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.985273952
Short name T694
Test name
Test status
Simulation time 11403519354 ps
CPU time 243.91 seconds
Started Mar 17 02:02:32 PM PDT 24
Finished Mar 17 02:06:36 PM PDT 24
Peak memory 207724 kb
Host smart-53efc961-bdf0-4c27-9bcf-50b7fb0011fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=985273952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.985273952
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2926398416
Short name T298
Test name
Test status
Simulation time 9695238319 ps
CPU time 228.3 seconds
Started Mar 17 02:02:32 PM PDT 24
Finished Mar 17 02:06:20 PM PDT 24
Peak memory 211920 kb
Host smart-ab530c58-f712-435f-9c8b-3da0d27459a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2926398416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2926398416
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4226403546
Short name T33
Test name
Test status
Simulation time 659900587 ps
CPU time 229.33 seconds
Started Mar 17 02:02:34 PM PDT 24
Finished Mar 17 02:06:23 PM PDT 24
Peak memory 208920 kb
Host smart-1c0edc1f-c5e9-4e83-9974-05ea195c58ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4226403546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.4226403546
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1935533525
Short name T886
Test name
Test status
Simulation time 3502251246 ps
CPU time 144.44 seconds
Started Mar 17 02:02:37 PM PDT 24
Finished Mar 17 02:05:01 PM PDT 24
Peak memory 209784 kb
Host smart-f885d585-cb83-4f4c-9553-9211a618c124
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1935533525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.1935533525
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2072817946
Short name T93
Test name
Test status
Simulation time 2086125713 ps
CPU time 27.31 seconds
Started Mar 17 02:02:34 PM PDT 24
Finished Mar 17 02:03:01 PM PDT 24
Peak memory 205328 kb
Host smart-5544902a-29f8-4dcb-9483-8ab5b2533035
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2072817946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2072817946
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3999629456
Short name T772
Test name
Test status
Simulation time 176344144 ps
CPU time 26.49 seconds
Started Mar 17 02:02:44 PM PDT 24
Finished Mar 17 02:03:11 PM PDT 24
Peak memory 204424 kb
Host smart-983d9741-1d1f-4253-a2bb-cecbae916e7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3999629456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3999629456
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1153552713
Short name T117
Test name
Test status
Simulation time 42970739566 ps
CPU time 102.64 seconds
Started Mar 17 02:02:44 PM PDT 24
Finished Mar 17 02:04:28 PM PDT 24
Peak memory 205764 kb
Host smart-cb913710-37cb-4f76-a0c8-fc562fc9eab6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1153552713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.1153552713
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1375635960
Short name T891
Test name
Test status
Simulation time 320856599 ps
CPU time 9.21 seconds
Started Mar 17 02:02:48 PM PDT 24
Finished Mar 17 02:02:58 PM PDT 24
Peak memory 203916 kb
Host smart-fb91d96c-1ee4-4f3a-ae63-4c37fec46be0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1375635960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1375635960
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.3519748494
Short name T683
Test name
Test status
Simulation time 551621380 ps
CPU time 20.08 seconds
Started Mar 17 02:02:44 PM PDT 24
Finished Mar 17 02:03:04 PM PDT 24
Peak memory 203712 kb
Host smart-b30fb003-91b5-4e09-9d32-4d054dd647d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3519748494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3519748494
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.2480193585
Short name T685
Test name
Test status
Simulation time 198084994 ps
CPU time 19.58 seconds
Started Mar 17 02:02:39 PM PDT 24
Finished Mar 17 02:02:58 PM PDT 24
Peak memory 211912 kb
Host smart-fb84eb12-72e8-48c6-adac-38bb425172a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2480193585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2480193585
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3597692663
Short name T386
Test name
Test status
Simulation time 43797337108 ps
CPU time 124.43 seconds
Started Mar 17 02:02:43 PM PDT 24
Finished Mar 17 02:04:48 PM PDT 24
Peak memory 205352 kb
Host smart-9071d174-f13e-4d46-b7ee-744f668fad35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597692663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3597692663
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1589519031
Short name T622
Test name
Test status
Simulation time 25377271159 ps
CPU time 220.59 seconds
Started Mar 17 02:02:43 PM PDT 24
Finished Mar 17 02:06:24 PM PDT 24
Peak memory 205164 kb
Host smart-d18e4477-a7bd-47f8-b222-f5d8a11fec55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1589519031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1589519031
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2215070997
Short name T135
Test name
Test status
Simulation time 74756379 ps
CPU time 8.59 seconds
Started Mar 17 02:02:38 PM PDT 24
Finished Mar 17 02:02:47 PM PDT 24
Peak memory 204844 kb
Host smart-ffb9e590-b418-4078-9baa-54c5fc0c4a0c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215070997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2215070997
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2867804201
Short name T128
Test name
Test status
Simulation time 1589405649 ps
CPU time 40.66 seconds
Started Mar 17 02:02:44 PM PDT 24
Finished Mar 17 02:03:25 PM PDT 24
Peak memory 204160 kb
Host smart-08b8668f-4b66-42b8-823c-a992f91ebcd0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2867804201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2867804201
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.714492489
Short name T536
Test name
Test status
Simulation time 150960848 ps
CPU time 3.98 seconds
Started Mar 17 02:02:33 PM PDT 24
Finished Mar 17 02:02:37 PM PDT 24
Peak memory 203692 kb
Host smart-9a65d0a9-931b-4422-8ded-203259c8a472
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=714492489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.714492489
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3440936372
Short name T322
Test name
Test status
Simulation time 5947044977 ps
CPU time 29.13 seconds
Started Mar 17 02:02:43 PM PDT 24
Finished Mar 17 02:03:12 PM PDT 24
Peak memory 203804 kb
Host smart-d5c0cc9b-8c54-4d91-a6cc-87730849923c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440936372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3440936372
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2921529027
Short name T253
Test name
Test status
Simulation time 11997583493 ps
CPU time 34.86 seconds
Started Mar 17 02:02:39 PM PDT 24
Finished Mar 17 02:03:14 PM PDT 24
Peak memory 203768 kb
Host smart-54514a35-e603-4b52-9ff1-fea3c8c27d98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2921529027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2921529027
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1612500439
Short name T586
Test name
Test status
Simulation time 28459327 ps
CPU time 2.43 seconds
Started Mar 17 02:02:38 PM PDT 24
Finished Mar 17 02:02:41 PM PDT 24
Peak memory 203684 kb
Host smart-8268289b-89a4-48f4-9f61-1fba0da54ce8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612500439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1612500439
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2697111392
Short name T711
Test name
Test status
Simulation time 875075712 ps
CPU time 39.43 seconds
Started Mar 17 02:02:46 PM PDT 24
Finished Mar 17 02:03:26 PM PDT 24
Peak memory 206704 kb
Host smart-46fe4e3c-e666-4ccc-bf83-8070963a8e80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2697111392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2697111392
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2731411298
Short name T269
Test name
Test status
Simulation time 3189047264 ps
CPU time 81.64 seconds
Started Mar 17 02:02:52 PM PDT 24
Finished Mar 17 02:04:14 PM PDT 24
Peak memory 207544 kb
Host smart-0f29e27b-e19e-4f37-aa1f-c53d0f8a729b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2731411298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2731411298
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.4013460382
Short name T381
Test name
Test status
Simulation time 1213454081 ps
CPU time 367.84 seconds
Started Mar 17 02:02:46 PM PDT 24
Finished Mar 17 02:08:54 PM PDT 24
Peak memory 208580 kb
Host smart-59dd3451-82cb-47f2-884c-bd9c96b6e29f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4013460382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.4013460382
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.158223005
Short name T502
Test name
Test status
Simulation time 477823748 ps
CPU time 154.81 seconds
Started Mar 17 02:02:52 PM PDT 24
Finished Mar 17 02:05:27 PM PDT 24
Peak memory 211488 kb
Host smart-a5ef0f9d-c8dc-48a9-836d-7115eb4b39bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=158223005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rese
t_error.158223005
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1549600317
Short name T532
Test name
Test status
Simulation time 771764555 ps
CPU time 14.98 seconds
Started Mar 17 02:02:45 PM PDT 24
Finished Mar 17 02:03:00 PM PDT 24
Peak memory 205348 kb
Host smart-76323a2c-0a88-47c3-b672-34ade61eadfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1549600317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1549600317
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.4136018944
Short name T861
Test name
Test status
Simulation time 692601348 ps
CPU time 20.3 seconds
Started Mar 17 02:02:53 PM PDT 24
Finished Mar 17 02:03:14 PM PDT 24
Peak memory 205916 kb
Host smart-8be4d7d6-0951-4318-9b0f-f01bbc53d006
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4136018944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.4136018944
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.4031418931
Short name T507
Test name
Test status
Simulation time 56830930243 ps
CPU time 454.68 seconds
Started Mar 17 02:02:53 PM PDT 24
Finished Mar 17 02:10:28 PM PDT 24
Peak memory 211996 kb
Host smart-2ec9223b-55f5-472b-82e4-9169d1aa8138
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4031418931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.4031418931
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.882329555
Short name T720
Test name
Test status
Simulation time 2420111014 ps
CPU time 23.02 seconds
Started Mar 17 02:03:05 PM PDT 24
Finished Mar 17 02:03:28 PM PDT 24
Peak memory 204184 kb
Host smart-c8cfc530-07fa-4b4d-a5eb-ef58613fb92a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=882329555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.882329555
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.2745891880
Short name T374
Test name
Test status
Simulation time 259784506 ps
CPU time 16.05 seconds
Started Mar 17 02:03:00 PM PDT 24
Finished Mar 17 02:03:19 PM PDT 24
Peak memory 203692 kb
Host smart-690cc81c-e6bd-4720-8579-7451ca0bd1c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2745891880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2745891880
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.3406636695
Short name T544
Test name
Test status
Simulation time 1176474118 ps
CPU time 29.78 seconds
Started Mar 17 02:02:51 PM PDT 24
Finished Mar 17 02:03:22 PM PDT 24
Peak memory 204880 kb
Host smart-45d1b667-a95d-4c34-b4e8-0cfb96443fb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3406636695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3406636695
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.935951459
Short name T329
Test name
Test status
Simulation time 39003460852 ps
CPU time 221.66 seconds
Started Mar 17 02:02:52 PM PDT 24
Finished Mar 17 02:06:34 PM PDT 24
Peak memory 211936 kb
Host smart-99b5ab11-4bbd-4fb5-ad74-aae2dcf7d2ea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=935951459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.935951459
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.4016446250
Short name T642
Test name
Test status
Simulation time 33758328800 ps
CPU time 273.61 seconds
Started Mar 17 02:02:53 PM PDT 24
Finished Mar 17 02:07:27 PM PDT 24
Peak memory 205108 kb
Host smart-79ddac88-712e-4a76-b8ea-6469c9c57553
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4016446250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.4016446250
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2492797479
Short name T136
Test name
Test status
Simulation time 228810072 ps
CPU time 30.68 seconds
Started Mar 17 02:02:52 PM PDT 24
Finished Mar 17 02:03:23 PM PDT 24
Peak memory 205012 kb
Host smart-97ab3e97-7931-4a22-a1e3-ea442dfe079a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492797479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2492797479
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.1808898797
Short name T826
Test name
Test status
Simulation time 3369896028 ps
CPU time 23.02 seconds
Started Mar 17 02:03:03 PM PDT 24
Finished Mar 17 02:03:26 PM PDT 24
Peak memory 204356 kb
Host smart-008d5f29-9be9-4467-92e5-633c65d79d91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1808898797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1808898797
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.84634279
Short name T704
Test name
Test status
Simulation time 557246650 ps
CPU time 4.02 seconds
Started Mar 17 02:02:53 PM PDT 24
Finished Mar 17 02:02:57 PM PDT 24
Peak memory 203684 kb
Host smart-561652e0-53a2-45f8-911b-52ef92906f58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84634279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.84634279
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3393014899
Short name T682
Test name
Test status
Simulation time 9089768334 ps
CPU time 34.97 seconds
Started Mar 17 02:02:53 PM PDT 24
Finished Mar 17 02:03:28 PM PDT 24
Peak memory 203784 kb
Host smart-91be488f-b708-45ad-b8cd-a87ff1376c49
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393014899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3393014899
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2847549985
Short name T275
Test name
Test status
Simulation time 2440910427 ps
CPU time 21.66 seconds
Started Mar 17 02:02:52 PM PDT 24
Finished Mar 17 02:03:14 PM PDT 24
Peak memory 203748 kb
Host smart-bda160a0-4df4-4e8d-8293-99f59afbdce1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2847549985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2847549985
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1490401116
Short name T895
Test name
Test status
Simulation time 32497098 ps
CPU time 2.56 seconds
Started Mar 17 02:02:52 PM PDT 24
Finished Mar 17 02:02:55 PM PDT 24
Peak memory 203708 kb
Host smart-af3b5be4-18af-4f6d-a305-35f1b7365aba
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490401116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1490401116
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1596767651
Short name T514
Test name
Test status
Simulation time 2232617622 ps
CPU time 44.94 seconds
Started Mar 17 02:03:01 PM PDT 24
Finished Mar 17 02:03:48 PM PDT 24
Peak memory 207272 kb
Host smart-4a0cf867-eea9-4ef0-b878-30715c2fff8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1596767651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1596767651
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.455693861
Short name T302
Test name
Test status
Simulation time 3570646965 ps
CPU time 196.23 seconds
Started Mar 17 02:02:59 PM PDT 24
Finished Mar 17 02:06:15 PM PDT 24
Peak memory 206940 kb
Host smart-f015a547-86c7-480c-86e1-fa29d1593e00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=455693861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.455693861
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.839017836
Short name T104
Test name
Test status
Simulation time 7490862157 ps
CPU time 398.23 seconds
Started Mar 17 02:02:58 PM PDT 24
Finished Mar 17 02:09:37 PM PDT 24
Peak memory 212288 kb
Host smart-e58541b0-23bc-4938-80c1-c1a3ef1a8c7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=839017836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_
reset.839017836
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3730594611
Short name T708
Test name
Test status
Simulation time 5463512097 ps
CPU time 303.47 seconds
Started Mar 17 02:03:03 PM PDT 24
Finished Mar 17 02:08:07 PM PDT 24
Peak memory 220204 kb
Host smart-d862c25f-7e8f-4f87-be6b-ea3ee2e84960
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3730594611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.3730594611
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2034936203
Short name T299
Test name
Test status
Simulation time 1414444308 ps
CPU time 17.82 seconds
Started Mar 17 02:02:59 PM PDT 24
Finished Mar 17 02:03:17 PM PDT 24
Peak memory 205116 kb
Host smart-2a0144aa-bbc5-4f94-bb49-f4dbcd47b2ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2034936203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2034936203
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2089819972
Short name T153
Test name
Test status
Simulation time 312270924 ps
CPU time 8.82 seconds
Started Mar 17 02:03:07 PM PDT 24
Finished Mar 17 02:03:16 PM PDT 24
Peak memory 203844 kb
Host smart-8e7f2d4e-cddc-44bc-8b1c-d0bdcd040fb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2089819972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2089819972
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3138756990
Short name T151
Test name
Test status
Simulation time 115910393834 ps
CPU time 252.83 seconds
Started Mar 17 02:03:14 PM PDT 24
Finished Mar 17 02:07:28 PM PDT 24
Peak memory 205988 kb
Host smart-8030c335-b883-4e2e-af07-4486ead17440
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3138756990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.3138756990
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2371678672
Short name T354
Test name
Test status
Simulation time 39515013 ps
CPU time 5.4 seconds
Started Mar 17 02:03:20 PM PDT 24
Finished Mar 17 02:03:25 PM PDT 24
Peak memory 203864 kb
Host smart-8ebfee09-ec82-4a8d-b4d5-d43dad43d4be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2371678672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2371678672
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2825845362
Short name T256
Test name
Test status
Simulation time 105988727 ps
CPU time 14.92 seconds
Started Mar 17 02:03:12 PM PDT 24
Finished Mar 17 02:03:27 PM PDT 24
Peak memory 203716 kb
Host smart-838c39ff-5050-42f9-9ae6-0a02a5e58d73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2825845362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2825845362
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.1449200893
Short name T747
Test name
Test status
Simulation time 844185773 ps
CPU time 38.91 seconds
Started Mar 17 02:02:59 PM PDT 24
Finished Mar 17 02:03:38 PM PDT 24
Peak memory 211884 kb
Host smart-6c7765f6-3f42-4301-afbf-c4b011ca6d69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449200893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1449200893
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3612689259
Short name T154
Test name
Test status
Simulation time 16790674510 ps
CPU time 44.7 seconds
Started Mar 17 02:03:05 PM PDT 24
Finished Mar 17 02:03:50 PM PDT 24
Peak memory 212016 kb
Host smart-2a358d68-2409-4de3-aa81-afa8660861d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612689259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3612689259
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1399346825
Short name T789
Test name
Test status
Simulation time 3703596094 ps
CPU time 32.76 seconds
Started Mar 17 02:03:06 PM PDT 24
Finished Mar 17 02:03:39 PM PDT 24
Peak memory 204188 kb
Host smart-8ca57277-24e3-454d-adaf-e9fb2c5876cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1399346825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1399346825
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.234585470
Short name T441
Test name
Test status
Simulation time 242797586 ps
CPU time 27.22 seconds
Started Mar 17 02:03:06 PM PDT 24
Finished Mar 17 02:03:33 PM PDT 24
Peak memory 204780 kb
Host smart-0ffe309d-c770-4b83-b516-1870d105bd23
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234585470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.234585470
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.1589869868
Short name T679
Test name
Test status
Simulation time 66896699 ps
CPU time 4.92 seconds
Started Mar 17 02:03:12 PM PDT 24
Finished Mar 17 02:03:17 PM PDT 24
Peak memory 203680 kb
Host smart-3f3f5b93-5ff6-40cd-a55e-db2e1ae79147
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1589869868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1589869868
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.2441109072
Short name T393
Test name
Test status
Simulation time 200037686 ps
CPU time 3.91 seconds
Started Mar 17 02:02:59 PM PDT 24
Finished Mar 17 02:03:03 PM PDT 24
Peak memory 203624 kb
Host smart-9730ef19-2be6-4fc7-b51b-9b4414c19273
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2441109072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2441109072
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2742303488
Short name T3
Test name
Test status
Simulation time 5780421649 ps
CPU time 28.27 seconds
Started Mar 17 02:03:00 PM PDT 24
Finished Mar 17 02:03:31 PM PDT 24
Peak memory 203756 kb
Host smart-fcf3d8c4-29f0-403e-b44a-0512a7cbf3c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742303488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2742303488
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2132343367
Short name T579
Test name
Test status
Simulation time 6101800206 ps
CPU time 38.09 seconds
Started Mar 17 02:02:59 PM PDT 24
Finished Mar 17 02:03:37 PM PDT 24
Peak memory 203764 kb
Host smart-15114a6e-0b18-465f-b169-8151036d09f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2132343367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2132343367
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3669371206
Short name T355
Test name
Test status
Simulation time 152390070 ps
CPU time 2.52 seconds
Started Mar 17 02:02:59 PM PDT 24
Finished Mar 17 02:03:02 PM PDT 24
Peak memory 203688 kb
Host smart-e07fe955-dfca-48e4-a4a2-436e453762c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669371206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3669371206
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.102348041
Short name T785
Test name
Test status
Simulation time 13487214106 ps
CPU time 321.36 seconds
Started Mar 17 02:03:17 PM PDT 24
Finished Mar 17 02:08:39 PM PDT 24
Peak memory 210812 kb
Host smart-79ec06d4-a98a-43c8-a1fc-9f1e9d72586a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102348041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.102348041
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2902102650
Short name T214
Test name
Test status
Simulation time 4397455933 ps
CPU time 144.87 seconds
Started Mar 17 02:03:18 PM PDT 24
Finished Mar 17 02:05:43 PM PDT 24
Peak memory 208656 kb
Host smart-238e8d86-1a93-46c2-bb74-f73a409a7696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2902102650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2902102650
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.812849837
Short name T564
Test name
Test status
Simulation time 1847313823 ps
CPU time 309.11 seconds
Started Mar 17 02:03:16 PM PDT 24
Finished Mar 17 02:08:26 PM PDT 24
Peak memory 209920 kb
Host smart-3ceee02e-0f4f-444c-98e8-6e645ed13e77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=812849837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_
reset.812849837
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1449130972
Short name T444
Test name
Test status
Simulation time 111016656 ps
CPU time 58.33 seconds
Started Mar 17 02:03:19 PM PDT 24
Finished Mar 17 02:04:18 PM PDT 24
Peak memory 207976 kb
Host smart-2d561365-a608-4a46-a648-6a9f8cdfacbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449130972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.1449130972
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.756433268
Short name T580
Test name
Test status
Simulation time 428373201 ps
CPU time 20.6 seconds
Started Mar 17 02:03:11 PM PDT 24
Finished Mar 17 02:03:33 PM PDT 24
Peak memory 205364 kb
Host smart-1f90a93e-e41d-410b-b3bc-de22ea699236
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=756433268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.756433268
Directory /workspace/9.xbar_unmapped_addr/latest
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