Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1588	1			T12	3		T13	2		T33	1
all_values[1]	1600	1			T12	2		T13	1		T33	1
all_values[2]	1625	1			T12	3		T13	3		T33	1
all_values[3]	1665	1			T12	4		T13	2		T33	1
all_values[4]	1607	1			T13	3		T33	1		T21	1
all_values[5]	1623	1			T12	5		T49	1		T33	1
all_values[6]	1637	1			T13	1		T33	2		T21	9
all_values[7]	1618	1			T12	2		T13	2		T33	1
all_values[8]	1587	1			T12	5		T13	3		T21	2
all_values[9]	1592	1			T12	2		T49	1		T33	2
all_values[10]	1622	1			T12	4		T21	6		T19	1
all_values[11]	1647	1			T12	2		T33	2		T21	4
all_values[12]	1701	1			T12	5		T13	1		T33	1
all_values[13]	1626	1			T12	4		T13	1		T33	2
all_values[14]	1665	1			T33	1		T21	1		T23	1
all_values[15]	1513	1			T12	2		T13	1		T21	3
all_values[16]	1637	1			T12	1		T13	2		T33	1
all_values[17]	1592	1			T12	2		T33	1		T21	5
all_values[18]	1657	1			T12	4		T21	6		T19	4
all_values[19]	1642	1			T12	1		T13	1		T21	6
all_values[20]	1578	1			T12	1		T13	1		T21	3
all_values[21]	1582	1			T12	4		T33	2		T21	4
all_values[22]	1694	1			T12	2		T21	4		T19	2
all_values[23]	1581	1			T12	2		T49	1		T13	1
all_values[24]	1617	1			T12	4		T13	3		T21	5
all_values[25]	1570	1			T12	3		T33	1		T21	1
all_values[26]	1640	1			T13	2		T21	1		T71	1
all_values[27]	1600	1			T12	2		T13	3		T33	1
all_values[28]	1617	1			T12	2		T13	1		T33	1
all_values[29]	1628	1			T12	4		T13	3		T21	4
all_values[30]	1532	1			T12	1		T13	3		T19	2
all_values[31]	1650	1			T12	2		T13	3		T21	6
all_values[32]	1614	1			T13	1		T33	1		T21	2
all_values[33]	1687	1			T12	4		T21	5		T23	2
all_values[34]	1590	1			T13	3		T33	1		T21	9
all_values[35]	1672	1			T12	4		T13	2		T33	2
all_values[36]	1589	1			T12	2		T13	1		T21	5
all_values[37]	1643	1			T12	3		T13	2		T21	8
all_values[38]	1596	1			T12	8		T13	1		T33	1
all_values[39]	1620	1			T12	1		T33	1		T21	7
all_values[40]	1578	1			T49	1		T13	4		T33	2
all_values[41]	1533	1			T12	3		T49	1		T13	2
all_values[42]	1679	1			T12	3		T49	1		T21	2
all_values[43]	1633	1			T12	3		T49	1		T13	1
all_values[44]	1642	1			T12	3		T49	2		T13	1
all_values[45]	1644	1			T12	6		T49	1		T33	1
all_values[46]	1673	1			T12	2		T13	3		T33	4
all_values[47]	1599	1			T12	2		T13	4		T33	1
all_values[48]	1627	1			T12	2		T13	3		T33	1
all_values[49]	1644	1			T12	2		T13	2		T19	3
all_values[50]	1612	1			T12	1		T49	1		T13	1
all_values[51]	1575	1			T12	1		T49	1		T13	2
all_values[52]	1652	1			T12	2		T49	1		T13	2
all_values[53]	1605	1			T12	3		T13	1		T21	5
all_values[54]	1646	1			T12	6		T13	2		T21	5
all_values[55]	1653	1			T12	3		T13	3		T33	1
all_values[56]	1643	1			T12	1		T13	2		T33	1
all_values[57]	1643	1			T12	1		T13	1		T21	2
all_values[58]	1572	1			T12	3		T13	1		T21	7
all_values[59]	1633	1			T12	1		T13	1		T21	3
all_values[60]	1556	1			T12	1		T13	3		T21	4
all_values[61]	1621	1			T12	1		T13	1		T21	2
all_values[62]	1697	1			T12	3		T13	1		T33	1
all_values[63]	1626	1			T12	1		T13	2		T33	1