Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1757	1			T5	23		T10	2		T11	5
all_values[1]	1710	1			T5	11		T11	4		T15	6
all_values[2]	1787	1			T5	23		T11	10		T15	7
all_values[3]	1724	1			T5	16		T11	3		T15	6
all_values[4]	1759	1			T5	13		T11	9		T15	8
all_values[5]	1678	1			T5	17		T11	9		T15	7
all_values[6]	1793	1			T5	18		T10	1		T11	5
all_values[7]	1723	1			T5	13		T11	1		T15	4
all_values[8]	1662	1			T5	12		T10	1		T11	4
all_values[9]	1694	1			T5	18		T11	5		T15	6
all_values[10]	1695	1			T5	18		T11	9		T15	7
all_values[11]	1723	1			T5	18		T11	8		T15	7
all_values[12]	1779	1			T5	20		T11	5		T15	4
all_values[13]	1670	1			T5	17		T11	7		T15	6
all_values[14]	1631	1			T5	13		T10	1		T11	6
all_values[15]	1701	1			T5	13		T10	1		T11	3
all_values[16]	1747	1			T5	10		T10	1		T11	6
all_values[17]	1703	1			T5	19		T11	6		T15	6
all_values[18]	1663	1			T5	12		T10	1		T11	10
all_values[19]	1678	1			T5	17		T11	5		T15	2
all_values[20]	1750	1			T5	15		T10	1		T11	4
all_values[21]	1722	1			T5	16		T11	8		T15	5
all_values[22]	1700	1			T5	16		T11	5		T15	2
all_values[23]	1802	1			T5	14		T11	3		T15	6
all_values[24]	1677	1			T5	14		T10	1		T11	7
all_values[25]	1719	1			T5	14		T10	1		T11	5
all_values[26]	1749	1			T5	10		T11	8		T15	3
all_values[27]	1737	1			T5	13		T10	1		T11	10
all_values[28]	1728	1			T5	18		T10	1		T11	8
all_values[29]	1660	1			T5	14		T11	1		T15	6
all_values[30]	1671	1			T5	14		T10	1		T11	6
all_values[31]	1699	1			T5	21		T10	2		T11	3
all_values[32]	1686	1			T5	21		T10	1		T11	4
all_values[33]	1686	1			T5	23		T11	9		T15	2
all_values[34]	1624	1			T5	12		T11	4		T15	7
all_values[35]	1685	1			T5	16		T11	5		T15	3
all_values[36]	1703	1			T5	16		T10	1		T11	7
all_values[37]	1737	1			T5	24		T11	6		T15	9
all_values[38]	1659	1			T5	20		T11	3		T15	6
all_values[39]	1756	1			T5	22		T10	2		T11	5
all_values[40]	1753	1			T5	23		T10	1		T11	11
all_values[41]	1736	1			T5	13		T11	9		T15	7
all_values[42]	1780	1			T5	17		T10	1		T11	3
all_values[43]	1795	1			T5	14		T11	5		T15	8
all_values[44]	1780	1			T5	21		T10	5		T11	3
all_values[45]	1686	1			T5	13		T11	9		T15	7
all_values[46]	1736	1			T5	21		T10	1		T11	4
all_values[47]	1705	1			T5	17		T11	6		T15	6
all_values[48]	1724	1			T5	9		T11	7		T15	4
all_values[49]	1718	1			T5	24		T11	3		T15	3
all_values[50]	1658	1			T5	14		T11	8		T15	7
all_values[51]	1734	1			T5	23		T10	1		T11	4
all_values[52]	1727	1			T5	21		T11	6		T15	4
all_values[53]	1679	1			T5	16		T11	11		T15	8
all_values[54]	1727	1			T5	25		T10	1		T11	8
all_values[55]	1766	1			T5	18		T10	1		T11	8
all_values[56]	1727	1			T5	14		T10	1		T11	2
all_values[57]	1750	1			T5	7		T10	2		T11	4
all_values[58]	1700	1			T5	20		T11	4		T15	3
all_values[59]	1646	1			T5	15		T11	3		T15	7
all_values[60]	1760	1			T5	17		T10	1		T11	4
all_values[61]	1710	1			T5	18		T10	2		T11	3
all_values[62]	1711	1			T5	13		T11	4		T15	4
all_values[63]	1689	1			T5	15		T10	2		T11	4