Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 99.26 90.07 98.80 95.90 99.26 100.00


Total test records in report: 900
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T764 /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.15872215 Mar 24 01:20:37 PM PDT 24 Mar 24 01:21:01 PM PDT 24 282334112 ps
T765 /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3722855660 Mar 24 01:21:20 PM PDT 24 Mar 24 01:23:39 PM PDT 24 15498332476 ps
T157 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2662453654 Mar 24 01:24:48 PM PDT 24 Mar 24 01:25:41 PM PDT 24 1906560203 ps
T766 /workspace/coverage/xbar_build_mode/49.xbar_error_random.3127501575 Mar 24 01:24:59 PM PDT 24 Mar 24 01:25:23 PM PDT 24 2801031893 ps
T767 /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.952914793 Mar 24 01:23:28 PM PDT 24 Mar 24 01:24:13 PM PDT 24 23842651026 ps
T768 /workspace/coverage/xbar_build_mode/14.xbar_random.841999543 Mar 24 01:21:44 PM PDT 24 Mar 24 01:21:47 PM PDT 24 98080190 ps
T769 /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3964848584 Mar 24 01:22:45 PM PDT 24 Mar 24 01:23:06 PM PDT 24 727153429 ps
T770 /workspace/coverage/xbar_build_mode/47.xbar_error_random.3286030608 Mar 24 01:24:56 PM PDT 24 Mar 24 01:25:18 PM PDT 24 1268356613 ps
T771 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3948936687 Mar 24 01:21:28 PM PDT 24 Mar 24 01:22:32 PM PDT 24 86898204 ps
T772 /workspace/coverage/xbar_build_mode/15.xbar_error_random.3507681303 Mar 24 01:21:54 PM PDT 24 Mar 24 01:22:19 PM PDT 24 318575218 ps
T773 /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.939125747 Mar 24 01:24:12 PM PDT 24 Mar 24 01:24:36 PM PDT 24 675037565 ps
T774 /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3443496644 Mar 24 01:21:44 PM PDT 24 Mar 24 01:22:02 PM PDT 24 917209040 ps
T775 /workspace/coverage/xbar_build_mode/22.xbar_random.3388813758 Mar 24 01:22:35 PM PDT 24 Mar 24 01:22:52 PM PDT 24 339294052 ps
T776 /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2968466382 Mar 24 01:25:00 PM PDT 24 Mar 24 01:25:20 PM PDT 24 818023545 ps
T777 /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1944806124 Mar 24 01:22:26 PM PDT 24 Mar 24 01:22:48 PM PDT 24 735376957 ps
T778 /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2454279216 Mar 24 01:23:32 PM PDT 24 Mar 24 01:23:44 PM PDT 24 75693390 ps
T779 /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1860482341 Mar 24 01:23:04 PM PDT 24 Mar 24 01:23:27 PM PDT 24 571351388 ps
T780 /workspace/coverage/xbar_build_mode/6.xbar_error_random.3017608692 Mar 24 01:20:53 PM PDT 24 Mar 24 01:21:14 PM PDT 24 653542268 ps
T781 /workspace/coverage/xbar_build_mode/49.xbar_random.744286313 Mar 24 01:25:00 PM PDT 24 Mar 24 01:25:12 PM PDT 24 318804925 ps
T782 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3143460483 Mar 24 01:20:51 PM PDT 24 Mar 24 01:24:34 PM PDT 24 22840871223 ps
T783 /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1944075273 Mar 24 01:22:44 PM PDT 24 Mar 24 01:23:21 PM PDT 24 506308334 ps
T784 /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2320991971 Mar 24 01:24:01 PM PDT 24 Mar 24 01:24:25 PM PDT 24 3103685143 ps
T785 /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.211666964 Mar 24 01:22:40 PM PDT 24 Mar 24 01:23:06 PM PDT 24 9778453658 ps
T786 /workspace/coverage/xbar_build_mode/47.xbar_same_source.245072686 Mar 24 01:24:58 PM PDT 24 Mar 24 01:25:02 PM PDT 24 96370509 ps
T787 /workspace/coverage/xbar_build_mode/3.xbar_same_source.3744664681 Mar 24 01:20:29 PM PDT 24 Mar 24 01:20:32 PM PDT 24 118101369 ps
T788 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1699133690 Mar 24 01:22:56 PM PDT 24 Mar 24 01:26:03 PM PDT 24 496600600 ps
T789 /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.485801957 Mar 24 01:21:20 PM PDT 24 Mar 24 01:25:11 PM PDT 24 9087124939 ps
T790 /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2275208519 Mar 24 01:23:01 PM PDT 24 Mar 24 01:23:17 PM PDT 24 129416648 ps
T791 /workspace/coverage/xbar_build_mode/20.xbar_same_source.3191118257 Mar 24 01:22:24 PM PDT 24 Mar 24 01:22:39 PM PDT 24 746786801 ps
T792 /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.4149057229 Mar 24 01:23:19 PM PDT 24 Mar 24 01:23:53 PM PDT 24 1242671543 ps
T793 /workspace/coverage/xbar_build_mode/33.xbar_same_source.613422901 Mar 24 01:23:34 PM PDT 24 Mar 24 01:23:51 PM PDT 24 669127885 ps
T794 /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2120697598 Mar 24 01:24:01 PM PDT 24 Mar 24 01:24:20 PM PDT 24 186758660 ps
T795 /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1186002988 Mar 24 01:22:23 PM PDT 24 Mar 24 01:24:37 PM PDT 24 459743432 ps
T796 /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2814017966 Mar 24 01:21:55 PM PDT 24 Mar 24 01:21:58 PM PDT 24 26272599 ps
T797 /workspace/coverage/xbar_build_mode/3.xbar_smoke.3427357420 Mar 24 01:20:23 PM PDT 24 Mar 24 01:20:25 PM PDT 24 24394650 ps
T798 /workspace/coverage/xbar_build_mode/34.xbar_random.3345155092 Mar 24 01:23:39 PM PDT 24 Mar 24 01:24:02 PM PDT 24 1214388205 ps
T799 /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.168674142 Mar 24 01:22:10 PM PDT 24 Mar 24 01:22:12 PM PDT 24 17157916 ps
T800 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3257968471 Mar 24 01:22:53 PM PDT 24 Mar 24 01:30:30 PM PDT 24 70085620925 ps
T801 /workspace/coverage/xbar_build_mode/48.xbar_same_source.736914625 Mar 24 01:25:02 PM PDT 24 Mar 24 01:25:09 PM PDT 24 494486376 ps
T802 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2192585314 Mar 24 01:23:23 PM PDT 24 Mar 24 01:26:23 PM PDT 24 6249865530 ps
T803 /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3002715777 Mar 24 01:23:34 PM PDT 24 Mar 24 01:23:48 PM PDT 24 122362648 ps
T804 /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2331359051 Mar 24 01:22:08 PM PDT 24 Mar 24 01:26:31 PM PDT 24 50721522034 ps
T805 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3834375693 Mar 24 01:23:06 PM PDT 24 Mar 24 01:23:53 PM PDT 24 625692171 ps
T806 /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2798958567 Mar 24 01:25:00 PM PDT 24 Mar 24 01:26:23 PM PDT 24 24696431390 ps
T261 /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.163518786 Mar 24 01:21:38 PM PDT 24 Mar 24 01:25:02 PM PDT 24 54775959614 ps
T807 /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3144045267 Mar 24 01:21:25 PM PDT 24 Mar 24 01:21:44 PM PDT 24 202155924 ps
T808 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3038986577 Mar 24 01:24:30 PM PDT 24 Mar 24 01:24:54 PM PDT 24 5882611961 ps
T809 /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2148269420 Mar 24 01:24:01 PM PDT 24 Mar 24 01:24:33 PM PDT 24 9905999877 ps
T810 /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.4214582352 Mar 24 01:23:54 PM PDT 24 Mar 24 01:24:39 PM PDT 24 1108535381 ps
T811 /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2745502727 Mar 24 01:21:43 PM PDT 24 Mar 24 01:24:57 PM PDT 24 36223876385 ps
T812 /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2034894257 Mar 24 01:24:52 PM PDT 24 Mar 24 01:25:23 PM PDT 24 767273638 ps
T813 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1903177654 Mar 24 01:24:03 PM PDT 24 Mar 24 01:24:28 PM PDT 24 758033308 ps
T814 /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1563827909 Mar 24 01:22:57 PM PDT 24 Mar 24 01:24:10 PM PDT 24 16177800605 ps
T815 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.733915777 Mar 24 01:22:38 PM PDT 24 Mar 24 01:26:40 PM PDT 24 1793767552 ps
T816 /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1809516967 Mar 24 01:20:27 PM PDT 24 Mar 24 01:20:30 PM PDT 24 56522543 ps
T817 /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3143423009 Mar 24 01:22:40 PM PDT 24 Mar 24 01:22:56 PM PDT 24 5462119718 ps
T139 /workspace/coverage/xbar_build_mode/5.xbar_smoke.3246256534 Mar 24 01:20:38 PM PDT 24 Mar 24 01:20:42 PM PDT 24 151068517 ps
T818 /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3243062386 Mar 24 01:25:00 PM PDT 24 Mar 24 01:25:33 PM PDT 24 6988390095 ps
T133 /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3846874018 Mar 24 01:20:06 PM PDT 24 Mar 24 01:25:32 PM PDT 24 75573455952 ps
T819 /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1048014954 Mar 24 01:24:20 PM PDT 24 Mar 24 01:24:43 PM PDT 24 392757066 ps
T820 /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.832123466 Mar 24 01:24:29 PM PDT 24 Mar 24 01:24:40 PM PDT 24 1674782298 ps
T177 /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3405789556 Mar 24 01:24:03 PM PDT 24 Mar 24 01:29:19 PM PDT 24 91407896962 ps
T134 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2314386918 Mar 24 01:24:45 PM PDT 24 Mar 24 01:35:57 PM PDT 24 273870826142 ps
T821 /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.753483014 Mar 24 01:20:05 PM PDT 24 Mar 24 01:20:37 PM PDT 24 5743447867 ps
T822 /workspace/coverage/xbar_build_mode/17.xbar_same_source.3195984669 Mar 24 01:22:12 PM PDT 24 Mar 24 01:22:23 PM PDT 24 108454040 ps
T823 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2379124025 Mar 24 01:22:20 PM PDT 24 Mar 24 01:22:24 PM PDT 24 27409593 ps
T824 /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3407875529 Mar 24 01:22:39 PM PDT 24 Mar 24 01:23:10 PM PDT 24 457347432 ps
T825 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1986498103 Mar 24 01:23:56 PM PDT 24 Mar 24 01:25:43 PM PDT 24 396615196 ps
T826 /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.576401988 Mar 24 01:22:26 PM PDT 24 Mar 24 01:22:31 PM PDT 24 43649350 ps
T827 /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2681341956 Mar 24 01:22:40 PM PDT 24 Mar 24 01:23:11 PM PDT 24 1723826824 ps
T828 /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2551750339 Mar 24 01:23:28 PM PDT 24 Mar 24 01:26:14 PM PDT 24 128950908897 ps
T829 /workspace/coverage/xbar_build_mode/28.xbar_smoke.1448119337 Mar 24 01:23:05 PM PDT 24 Mar 24 01:23:09 PM PDT 24 132960263 ps
T830 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.4174001336 Mar 24 01:24:36 PM PDT 24 Mar 24 01:27:01 PM PDT 24 419640362 ps
T831 /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1541218517 Mar 24 01:21:25 PM PDT 24 Mar 24 01:21:51 PM PDT 24 4876232106 ps
T832 /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2594538833 Mar 24 01:21:59 PM PDT 24 Mar 24 01:24:45 PM PDT 24 23388917486 ps
T218 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2648782439 Mar 24 01:22:07 PM PDT 24 Mar 24 01:22:24 PM PDT 24 166640038 ps
T833 /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1779336882 Mar 24 01:24:28 PM PDT 24 Mar 24 01:26:33 PM PDT 24 38514536954 ps
T834 /workspace/coverage/xbar_build_mode/14.xbar_error_random.4128878113 Mar 24 01:21:44 PM PDT 24 Mar 24 01:22:04 PM PDT 24 278705265 ps
T835 /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1584176842 Mar 24 01:24:14 PM PDT 24 Mar 24 01:24:20 PM PDT 24 144603966 ps
T836 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1964966142 Mar 24 01:23:27 PM PDT 24 Mar 24 01:27:02 PM PDT 24 25200504177 ps
T837 /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3237816179 Mar 24 01:21:43 PM PDT 24 Mar 24 01:22:00 PM PDT 24 1607280699 ps
T838 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2715058781 Mar 24 01:23:35 PM PDT 24 Mar 24 01:23:39 PM PDT 24 7692277 ps
T839 /workspace/coverage/xbar_build_mode/11.xbar_random.4266328027 Mar 24 01:21:25 PM PDT 24 Mar 24 01:21:52 PM PDT 24 273138144 ps
T840 /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1458161304 Mar 24 01:22:04 PM PDT 24 Mar 24 01:22:35 PM PDT 24 7934652434 ps
T841 /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2693061949 Mar 24 01:21:18 PM PDT 24 Mar 24 01:22:11 PM PDT 24 1349230476 ps
T842 /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.959226475 Mar 24 01:24:18 PM PDT 24 Mar 24 01:24:41 PM PDT 24 2512314021 ps
T843 /workspace/coverage/xbar_build_mode/12.xbar_error_random.3001224871 Mar 24 01:21:33 PM PDT 24 Mar 24 01:21:57 PM PDT 24 177211388 ps
T844 /workspace/coverage/xbar_build_mode/6.xbar_smoke.2070164836 Mar 24 01:20:46 PM PDT 24 Mar 24 01:20:49 PM PDT 24 309930313 ps
T845 /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1410987254 Mar 24 01:23:22 PM PDT 24 Mar 24 01:23:27 PM PDT 24 67680174 ps
T846 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3739309582 Mar 24 01:20:56 PM PDT 24 Mar 24 01:21:54 PM PDT 24 178779263 ps
T847 /workspace/coverage/xbar_build_mode/20.xbar_error_random.181076382 Mar 24 01:22:24 PM PDT 24 Mar 24 01:22:48 PM PDT 24 470281537 ps
T848 /workspace/coverage/xbar_build_mode/13.xbar_random.2164232785 Mar 24 01:21:33 PM PDT 24 Mar 24 01:21:48 PM PDT 24 2647641162 ps
T849 /workspace/coverage/xbar_build_mode/6.xbar_same_source.692237077 Mar 24 01:20:51 PM PDT 24 Mar 24 01:20:56 PM PDT 24 74699375 ps
T219 /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2924435886 Mar 24 01:23:24 PM PDT 24 Mar 24 01:24:26 PM PDT 24 492895983 ps
T850 /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.109739475 Mar 24 01:22:51 PM PDT 24 Mar 24 01:23:18 PM PDT 24 943183809 ps
T851 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1067845764 Mar 24 01:22:20 PM PDT 24 Mar 24 01:27:40 PM PDT 24 3053007350 ps
T852 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2256139876 Mar 24 01:22:28 PM PDT 24 Mar 24 01:32:57 PM PDT 24 75664317936 ps
T853 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1468979355 Mar 24 01:24:36 PM PDT 24 Mar 24 01:27:16 PM PDT 24 692637112 ps
T135 /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3030526635 Mar 24 01:23:58 PM PDT 24 Mar 24 01:26:52 PM PDT 24 4311274567 ps
T854 /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1563409526 Mar 24 01:24:41 PM PDT 24 Mar 24 01:24:44 PM PDT 24 31655326 ps
T855 /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.748896146 Mar 24 01:24:59 PM PDT 24 Mar 24 01:37:41 PM PDT 24 160473518096 ps
T856 /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.499169206 Mar 24 01:20:38 PM PDT 24 Mar 24 01:21:09 PM PDT 24 9051606469 ps
T857 /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.695460282 Mar 24 01:23:22 PM PDT 24 Mar 24 01:23:48 PM PDT 24 4780645806 ps
T858 /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4264009035 Mar 24 01:24:18 PM PDT 24 Mar 24 01:24:20 PM PDT 24 59537565 ps
T859 /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1457923176 Mar 24 01:24:29 PM PDT 24 Mar 24 01:24:53 PM PDT 24 3390830534 ps
T860 /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1119777533 Mar 24 01:21:17 PM PDT 24 Mar 24 01:21:20 PM PDT 24 66891932 ps
T861 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.687219987 Mar 24 01:21:01 PM PDT 24 Mar 24 01:22:41 PM PDT 24 512797745 ps
T862 /workspace/coverage/xbar_build_mode/48.xbar_smoke.1003426209 Mar 24 01:24:57 PM PDT 24 Mar 24 01:25:00 PM PDT 24 190108021 ps
T863 /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2028213142 Mar 24 01:21:57 PM PDT 24 Mar 24 01:22:28 PM PDT 24 3343982429 ps
T864 /workspace/coverage/xbar_build_mode/23.xbar_error_random.67734808 Mar 24 01:22:38 PM PDT 24 Mar 24 01:22:47 PM PDT 24 74132560 ps
T865 /workspace/coverage/xbar_build_mode/0.xbar_random.3271346887 Mar 24 01:20:09 PM PDT 24 Mar 24 01:20:36 PM PDT 24 1576865988 ps
T866 /workspace/coverage/xbar_build_mode/14.xbar_same_source.1393070545 Mar 24 01:21:45 PM PDT 24 Mar 24 01:22:12 PM PDT 24 1410643104 ps
T867 /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2646462449 Mar 24 01:20:42 PM PDT 24 Mar 24 01:21:06 PM PDT 24 206130896 ps
T868 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3003767821 Mar 24 01:21:33 PM PDT 24 Mar 24 01:26:05 PM PDT 24 14684815431 ps
T869 /workspace/coverage/xbar_build_mode/39.xbar_same_source.1528953554 Mar 24 01:24:14 PM PDT 24 Mar 24 01:24:31 PM PDT 24 1815663061 ps
T870 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1887104644 Mar 24 01:20:11 PM PDT 24 Mar 24 01:21:22 PM PDT 24 219434680 ps
T871 /workspace/coverage/xbar_build_mode/31.xbar_smoke.3004494836 Mar 24 01:23:27 PM PDT 24 Mar 24 01:23:31 PM PDT 24 196633927 ps
T872 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1582102062 Mar 24 01:21:41 PM PDT 24 Mar 24 01:24:36 PM PDT 24 8798342125 ps
T873 /workspace/coverage/xbar_build_mode/45.xbar_random.3423868307 Mar 24 01:24:44 PM PDT 24 Mar 24 01:25:24 PM PDT 24 3246840708 ps
T874 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1879835578 Mar 24 01:22:30 PM PDT 24 Mar 24 01:26:07 PM PDT 24 5408883382 ps
T158 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3446233523 Mar 24 01:24:41 PM PDT 24 Mar 24 01:25:17 PM PDT 24 892869745 ps
T875 /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.751245830 Mar 24 01:22:42 PM PDT 24 Mar 24 01:23:36 PM PDT 24 22378254714 ps
T876 /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1276533255 Mar 24 01:22:24 PM PDT 24 Mar 24 01:22:39 PM PDT 24 202019503 ps
T877 /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2671733326 Mar 24 01:20:19 PM PDT 24 Mar 24 01:20:47 PM PDT 24 7250517014 ps
T878 /workspace/coverage/xbar_build_mode/17.xbar_random.1832207042 Mar 24 01:22:07 PM PDT 24 Mar 24 01:22:25 PM PDT 24 587380072 ps
T879 /workspace/coverage/xbar_build_mode/35.xbar_error_random.2952613931 Mar 24 01:23:46 PM PDT 24 Mar 24 01:24:09 PM PDT 24 706526496 ps
T880 /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.654323505 Mar 24 01:23:52 PM PDT 24 Mar 24 01:25:17 PM PDT 24 23600025869 ps
T881 /workspace/coverage/xbar_build_mode/38.xbar_error_random.3841502385 Mar 24 01:24:01 PM PDT 24 Mar 24 01:24:18 PM PDT 24 163741464 ps
T882 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2092456232 Mar 24 01:21:58 PM PDT 24 Mar 24 01:22:06 PM PDT 24 193271940 ps
T205 /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3071890480 Mar 24 01:20:51 PM PDT 24 Mar 24 01:21:20 PM PDT 24 6833918803 ps
T883 /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1748049148 Mar 24 01:22:58 PM PDT 24 Mar 24 01:23:21 PM PDT 24 4555143697 ps
T884 /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2939424645 Mar 24 01:24:56 PM PDT 24 Mar 24 01:25:00 PM PDT 24 101256877 ps
T885 /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1694260643 Mar 24 01:20:07 PM PDT 24 Mar 24 01:21:21 PM PDT 24 2325028202 ps
T886 /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1658207255 Mar 24 01:23:09 PM PDT 24 Mar 24 01:26:37 PM PDT 24 106722868507 ps
T887 /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3422960965 Mar 24 01:23:38 PM PDT 24 Mar 24 01:23:40 PM PDT 24 34263681 ps
T34 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.8649391 Mar 24 01:20:15 PM PDT 24 Mar 24 01:29:28 PM PDT 24 6740281158 ps
T888 /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1328417872 Mar 24 01:24:45 PM PDT 24 Mar 24 01:25:12 PM PDT 24 210612951 ps
T889 /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3666248324 Mar 24 01:23:09 PM PDT 24 Mar 24 01:23:37 PM PDT 24 5959741871 ps
T890 /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1031066909 Mar 24 01:21:53 PM PDT 24 Mar 24 01:24:20 PM PDT 24 19028306184 ps
T891 /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1614582621 Mar 24 01:21:22 PM PDT 24 Mar 24 01:24:36 PM PDT 24 36503830244 ps
T302 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2622113367 Mar 24 01:24:17 PM PDT 24 Mar 24 01:28:00 PM PDT 24 4496704291 ps
T892 /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.150325443 Mar 24 01:21:59 PM PDT 24 Mar 24 01:22:10 PM PDT 24 257430401 ps
T893 /workspace/coverage/xbar_build_mode/0.xbar_smoke.2949110087 Mar 24 01:20:08 PM PDT 24 Mar 24 01:20:12 PM PDT 24 183888590 ps
T894 /workspace/coverage/xbar_build_mode/4.xbar_smoke.3767807979 Mar 24 01:20:33 PM PDT 24 Mar 24 01:20:38 PM PDT 24 180997352 ps
T895 /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2876969150 Mar 24 01:21:23 PM PDT 24 Mar 24 01:21:34 PM PDT 24 182078575 ps
T896 /workspace/coverage/xbar_build_mode/20.xbar_stress_all.836849613 Mar 24 01:22:25 PM PDT 24 Mar 24 01:26:05 PM PDT 24 10574744195 ps
T897 /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3452688249 Mar 24 01:23:30 PM PDT 24 Mar 24 01:23:33 PM PDT 24 31299692 ps
T898 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2013548959 Mar 24 01:24:28 PM PDT 24 Mar 24 01:25:13 PM PDT 24 6678706866 ps
T899 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2995517910 Mar 24 01:23:00 PM PDT 24 Mar 24 01:23:08 PM PDT 24 176667195 ps
T900 /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1403518423 Mar 24 01:22:28 PM PDT 24 Mar 24 01:25:56 PM PDT 24 27092664465 ps

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1077363192
Short name T3
Test name
Test status
Simulation time 32150176860 ps
CPU time 271.74 seconds
Started Mar 24 01:24:36 PM PDT 24
Finished Mar 24 01:29:08 PM PDT 24
Peak memory 207276 kb
Host smart-19857f68-3204-4f75-a243-d3b8714deb70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1077363192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1077363192
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.400029404
Short name T80
Test name
Test status
Simulation time 164780126480 ps
CPU time 996.22 seconds
Started Mar 24 01:21:36 PM PDT 24
Finished Mar 24 01:38:13 PM PDT 24
Peak memory 206124 kb
Host smart-b4ce57bc-5ee6-4ba8-a509-078b59d288ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=400029404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slo
w_rsp.400029404
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.836518253
Short name T82
Test name
Test status
Simulation time 74245708990 ps
CPU time 436.74 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:31:30 PM PDT 24
Peak memory 206156 kb
Host smart-fb3bad18-d9af-4bf3-93b2-85109d620fb6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=836518253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo
w_rsp.836518253
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2617009780
Short name T15
Test name
Test status
Simulation time 70952247650 ps
CPU time 349.53 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:30:19 PM PDT 24
Peak memory 206796 kb
Host smart-015a6ab9-0b0e-4d3c-8ad7-33da9b1ebd80
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2617009780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.2617009780
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.130672528
Short name T93
Test name
Test status
Simulation time 4106064097 ps
CPU time 143.47 seconds
Started Mar 24 01:21:24 PM PDT 24
Finished Mar 24 01:23:49 PM PDT 24
Peak memory 208152 kb
Host smart-b3427512-fd20-45fb-9fe4-0e61152eae1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=130672528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.130672528
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.806683938
Short name T25
Test name
Test status
Simulation time 18699470876 ps
CPU time 645.35 seconds
Started Mar 24 01:20:38 PM PDT 24
Finished Mar 24 01:31:23 PM PDT 24
Peak memory 228140 kb
Host smart-d1b3957e-385f-4078-8bee-090691149a57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=806683938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese
t_error.806683938
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3096798608
Short name T14
Test name
Test status
Simulation time 21810691 ps
CPU time 2.55 seconds
Started Mar 24 01:20:51 PM PDT 24
Finished Mar 24 01:20:53 PM PDT 24
Peak memory 203732 kb
Host smart-b26e23eb-d818-4cbe-a377-f61118cc744e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096798608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3096798608
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.700086629
Short name T45
Test name
Test status
Simulation time 19499230927 ps
CPU time 46.28 seconds
Started Mar 24 01:23:18 PM PDT 24
Finished Mar 24 01:24:05 PM PDT 24
Peak memory 204720 kb
Host smart-4df99273-8008-4562-9452-9fbe03579293
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=700086629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.700086629
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1178821083
Short name T122
Test name
Test status
Simulation time 90160908226 ps
CPU time 551.11 seconds
Started Mar 24 01:24:01 PM PDT 24
Finished Mar 24 01:33:13 PM PDT 24
Peak memory 207468 kb
Host smart-bbb5feda-a0f1-4902-a3b1-ccc7aea0b291
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1178821083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.1178821083
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1698393185
Short name T38
Test name
Test status
Simulation time 7484212931 ps
CPU time 375.81 seconds
Started Mar 24 01:23:24 PM PDT 24
Finished Mar 24 01:29:40 PM PDT 24
Peak memory 222152 kb
Host smart-f724ca6e-381c-40a6-bad2-dbc11ba1e01a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698393185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.1698393185
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2314386918
Short name T134
Test name
Test status
Simulation time 273870826142 ps
CPU time 671.47 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:35:57 PM PDT 24
Peak memory 207564 kb
Host smart-4daafbb3-3419-403b-9769-f554a5da3354
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2314386918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.2314386918
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3028502068
Short name T22
Test name
Test status
Simulation time 665224641 ps
CPU time 21 seconds
Started Mar 24 01:23:52 PM PDT 24
Finished Mar 24 01:24:13 PM PDT 24
Peak memory 211904 kb
Host smart-027a42c8-b1b5-4fef-92f4-b12c227c362a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3028502068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3028502068
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1491437304
Short name T76
Test name
Test status
Simulation time 1906095086 ps
CPU time 36.78 seconds
Started Mar 24 01:22:47 PM PDT 24
Finished Mar 24 01:23:24 PM PDT 24
Peak memory 206016 kb
Host smart-35755968-ea32-452f-a1b4-bdbd9f892d4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1491437304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1491437304
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2929704078
Short name T35
Test name
Test status
Simulation time 497661309 ps
CPU time 215.17 seconds
Started Mar 24 01:24:11 PM PDT 24
Finished Mar 24 01:27:46 PM PDT 24
Peak memory 208312 kb
Host smart-518d4239-b572-4e0a-a79d-81b5d137dbbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2929704078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.2929704078
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3562741592
Short name T16
Test name
Test status
Simulation time 16838996385 ps
CPU time 339.86 seconds
Started Mar 24 01:21:15 PM PDT 24
Finished Mar 24 01:26:55 PM PDT 24
Peak memory 224108 kb
Host smart-cde80572-3975-4881-bdda-52478e0a8333
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3562741592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.3562741592
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3803376380
Short name T81
Test name
Test status
Simulation time 3243979400 ps
CPU time 60.23 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:22:33 PM PDT 24
Peak memory 211732 kb
Host smart-c5d5cac8-5bb4-44f8-ab0f-f5feaf0dba96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3803376380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3803376380
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2686224526
Short name T171
Test name
Test status
Simulation time 45784032803 ps
CPU time 364.59 seconds
Started Mar 24 01:22:56 PM PDT 24
Finished Mar 24 01:29:01 PM PDT 24
Peak memory 207016 kb
Host smart-c0042e61-a9a6-4932-bed8-b3d4ece964b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2686224526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.2686224526
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.905115472
Short name T28
Test name
Test status
Simulation time 397307417 ps
CPU time 140.28 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:23:53 PM PDT 24
Peak memory 208560 kb
Host smart-d11250e4-309d-4d14-bbfe-f14828b19d49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=905115472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand
_reset.905115472
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1755039337
Short name T242
Test name
Test status
Simulation time 216206461 ps
CPU time 117.71 seconds
Started Mar 24 01:21:40 PM PDT 24
Finished Mar 24 01:23:38 PM PDT 24
Peak memory 208408 kb
Host smart-d6b28ad5-2e6d-499a-be13-ed45faa5996d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1755039337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.1755039337
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3828071182
Short name T97
Test name
Test status
Simulation time 4107601684 ps
CPU time 60.44 seconds
Started Mar 24 01:20:41 PM PDT 24
Finished Mar 24 01:21:41 PM PDT 24
Peak memory 206372 kb
Host smart-873c3e68-6a43-4b38-90cb-8cf8a03bebac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3828071182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3828071182
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3921415075
Short name T126
Test name
Test status
Simulation time 88231541278 ps
CPU time 468.51 seconds
Started Mar 24 01:24:44 PM PDT 24
Finished Mar 24 01:32:33 PM PDT 24
Peak memory 206112 kb
Host smart-816ce9a9-2b48-4b61-903d-e2d67d6be99d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3921415075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.3921415075
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1694260643
Short name T885
Test name
Test status
Simulation time 2325028202 ps
CPU time 74.12 seconds
Started Mar 24 01:20:07 PM PDT 24
Finished Mar 24 01:21:21 PM PDT 24
Peak memory 205828 kb
Host smart-be7fb767-802d-4e8d-b58a-bb6b87b3e04e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1694260643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1694260643
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3846874018
Short name T133
Test name
Test status
Simulation time 75573455952 ps
CPU time 325.44 seconds
Started Mar 24 01:20:06 PM PDT 24
Finished Mar 24 01:25:32 PM PDT 24
Peak memory 206824 kb
Host smart-302174c3-3526-4730-878e-6f20dddc05ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3846874018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.3846874018
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3809465531
Short name T434
Test name
Test status
Simulation time 42078912 ps
CPU time 2.64 seconds
Started Mar 24 01:20:12 PM PDT 24
Finished Mar 24 01:20:14 PM PDT 24
Peak memory 203492 kb
Host smart-086e6a8a-5679-42b3-b25c-98010a09adb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3809465531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3809465531
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.3936166351
Short name T315
Test name
Test status
Simulation time 237052738 ps
CPU time 7.89 seconds
Started Mar 24 01:20:13 PM PDT 24
Finished Mar 24 01:20:21 PM PDT 24
Peak memory 203500 kb
Host smart-e68ba9ad-8c86-46d2-afb4-60bbc87b82ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3936166351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3936166351
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3271346887
Short name T865
Test name
Test status
Simulation time 1576865988 ps
CPU time 27.54 seconds
Started Mar 24 01:20:09 PM PDT 24
Finished Mar 24 01:20:36 PM PDT 24
Peak memory 204776 kb
Host smart-92283373-0ed5-4407-88c7-a559679a50e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3271346887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3271346887
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2176657835
Short name T579
Test name
Test status
Simulation time 33292060235 ps
CPU time 197.48 seconds
Started Mar 24 01:20:05 PM PDT 24
Finished Mar 24 01:23:23 PM PDT 24
Peak memory 205360 kb
Host smart-52a46d0a-fd41-4684-a247-6cf7f310ccc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176657835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2176657835
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3884310872
Short name T709
Test name
Test status
Simulation time 22446019277 ps
CPU time 212.33 seconds
Started Mar 24 01:20:06 PM PDT 24
Finished Mar 24 01:23:39 PM PDT 24
Peak memory 205392 kb
Host smart-6ad3ae87-f658-4148-a006-79e8ea626458
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3884310872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3884310872
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.644614661
Short name T604
Test name
Test status
Simulation time 91782188 ps
CPU time 13.87 seconds
Started Mar 24 01:20:08 PM PDT 24
Finished Mar 24 01:20:22 PM PDT 24
Peak memory 204640 kb
Host smart-459caa0b-6ab0-4c0b-81dd-184e130d3a44
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644614661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.644614661
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.1683609952
Short name T744
Test name
Test status
Simulation time 111854767 ps
CPU time 6.87 seconds
Started Mar 24 01:20:06 PM PDT 24
Finished Mar 24 01:20:14 PM PDT 24
Peak memory 203500 kb
Host smart-07b6e4c6-55ed-40d2-971f-2af909949b8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1683609952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1683609952
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.2949110087
Short name T893
Test name
Test status
Simulation time 183888590 ps
CPU time 3.79 seconds
Started Mar 24 01:20:08 PM PDT 24
Finished Mar 24 01:20:12 PM PDT 24
Peak memory 203492 kb
Host smart-b49dc878-07e3-499e-b9de-1737c27d50ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2949110087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2949110087
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.753483014
Short name T821
Test name
Test status
Simulation time 5743447867 ps
CPU time 31.39 seconds
Started Mar 24 01:20:05 PM PDT 24
Finished Mar 24 01:20:37 PM PDT 24
Peak memory 203568 kb
Host smart-53b117c7-0e40-4c41-9389-70b3a2da635e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=753483014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.753483014
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2865971119
Short name T584
Test name
Test status
Simulation time 11048454769 ps
CPU time 41.3 seconds
Started Mar 24 01:20:06 PM PDT 24
Finished Mar 24 01:20:47 PM PDT 24
Peak memory 203564 kb
Host smart-fe8b0504-0eec-4c8a-9a28-b0ccb414415b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2865971119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2865971119
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.4000089929
Short name T11
Test name
Test status
Simulation time 54917452 ps
CPU time 2.37 seconds
Started Mar 24 01:20:00 PM PDT 24
Finished Mar 24 01:20:02 PM PDT 24
Peak memory 203492 kb
Host smart-d1e410b3-c34a-42ad-955b-fe05f2844dc0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000089929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.4000089929
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3647585489
Short name T386
Test name
Test status
Simulation time 4158590148 ps
CPU time 82.63 seconds
Started Mar 24 01:20:08 PM PDT 24
Finished Mar 24 01:21:31 PM PDT 24
Peak memory 206988 kb
Host smart-75004601-5328-42e5-a3bf-a83dd517a950
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3647585489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3647585489
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1711669480
Short name T338
Test name
Test status
Simulation time 24273339644 ps
CPU time 157.79 seconds
Started Mar 24 01:20:13 PM PDT 24
Finished Mar 24 01:22:51 PM PDT 24
Peak memory 208116 kb
Host smart-d0f7a155-31e7-4b97-8410-bae229efcea7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1711669480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1711669480
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.944156691
Short name T369
Test name
Test status
Simulation time 2219010089 ps
CPU time 316.99 seconds
Started Mar 24 01:20:10 PM PDT 24
Finished Mar 24 01:25:28 PM PDT 24
Peak memory 210500 kb
Host smart-c6f33196-9ba0-4db7-9d74-00332c770376
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=944156691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_
reset.944156691
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1887104644
Short name T870
Test name
Test status
Simulation time 219434680 ps
CPU time 70.26 seconds
Started Mar 24 01:20:11 PM PDT 24
Finished Mar 24 01:21:22 PM PDT 24
Peak memory 208040 kb
Host smart-3149b342-9fac-426e-9834-800457791d83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1887104644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.1887104644
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2703273851
Short name T589
Test name
Test status
Simulation time 2287624715 ps
CPU time 30.45 seconds
Started Mar 24 01:20:13 PM PDT 24
Finished Mar 24 01:20:43 PM PDT 24
Peak memory 211676 kb
Host smart-ad5019d1-7e8e-496e-b817-aac53f21d07d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2703273851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2703273851
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.997327458
Short name T606
Test name
Test status
Simulation time 82699655 ps
CPU time 5.89 seconds
Started Mar 24 01:20:14 PM PDT 24
Finished Mar 24 01:20:20 PM PDT 24
Peak memory 203652 kb
Host smart-8e47591c-a4b5-4b46-9f87-31c9078a4d02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=997327458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.997327458
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.168619363
Short name T368
Test name
Test status
Simulation time 68468138226 ps
CPU time 593.1 seconds
Started Mar 24 01:20:17 PM PDT 24
Finished Mar 24 01:30:11 PM PDT 24
Peak memory 206984 kb
Host smart-217ac08f-5514-40c6-a18b-8a206fb44aa0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=168619363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow
_rsp.168619363
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3020673547
Short name T423
Test name
Test status
Simulation time 689781817 ps
CPU time 12.04 seconds
Started Mar 24 01:20:18 PM PDT 24
Finished Mar 24 01:20:30 PM PDT 24
Peak memory 203776 kb
Host smart-d5a84288-fc98-4455-ad5d-93e28f9f711e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3020673547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3020673547
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.2046429745
Short name T280
Test name
Test status
Simulation time 478833986 ps
CPU time 8.7 seconds
Started Mar 24 01:20:15 PM PDT 24
Finished Mar 24 01:20:24 PM PDT 24
Peak memory 203508 kb
Host smart-af4f59ff-17a0-4dda-bda8-49841bccf39f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2046429745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2046429745
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.104828563
Short name T607
Test name
Test status
Simulation time 884950332 ps
CPU time 29.8 seconds
Started Mar 24 01:20:14 PM PDT 24
Finished Mar 24 01:20:44 PM PDT 24
Peak memory 211680 kb
Host smart-cd2d89d1-d84c-4122-b36c-52e73878a5a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104828563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.104828563
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.765846676
Short name T160
Test name
Test status
Simulation time 41200408449 ps
CPU time 251.85 seconds
Started Mar 24 01:20:18 PM PDT 24
Finished Mar 24 01:24:30 PM PDT 24
Peak memory 205760 kb
Host smart-9a3a3f7d-0cf6-42e3-8bdb-d80512a215fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=765846676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.765846676
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2841618168
Short name T48
Test name
Test status
Simulation time 24967593777 ps
CPU time 103.8 seconds
Started Mar 24 01:20:15 PM PDT 24
Finished Mar 24 01:21:59 PM PDT 24
Peak memory 211672 kb
Host smart-80261f32-3d7a-45ec-b1d0-3cd1f059ae9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2841618168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2841618168
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1888428800
Short name T713
Test name
Test status
Simulation time 306979413 ps
CPU time 22.23 seconds
Started Mar 24 01:20:15 PM PDT 24
Finished Mar 24 01:20:38 PM PDT 24
Peak memory 211708 kb
Host smart-61717a5b-8613-4b6e-8516-95e45cfa7423
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888428800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1888428800
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.847184744
Short name T470
Test name
Test status
Simulation time 1169703518 ps
CPU time 19.93 seconds
Started Mar 24 01:20:15 PM PDT 24
Finished Mar 24 01:20:35 PM PDT 24
Peak memory 203444 kb
Host smart-2c5056b9-4c4c-4c47-9bce-396ae2fae6ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=847184744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.847184744
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.4181251188
Short name T557
Test name
Test status
Simulation time 37752345 ps
CPU time 2.43 seconds
Started Mar 24 01:20:13 PM PDT 24
Finished Mar 24 01:20:15 PM PDT 24
Peak memory 203468 kb
Host smart-bf5f0865-5fd7-41ef-95b7-5b04da2ea4c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4181251188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4181251188
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1307282858
Short name T287
Test name
Test status
Simulation time 6526926427 ps
CPU time 32.17 seconds
Started Mar 24 01:20:10 PM PDT 24
Finished Mar 24 01:20:42 PM PDT 24
Peak memory 203572 kb
Host smart-d46372bd-67a7-4436-af5e-4dd3849137b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307282858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1307282858
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.699648292
Short name T517
Test name
Test status
Simulation time 4991050249 ps
CPU time 30.87 seconds
Started Mar 24 01:20:13 PM PDT 24
Finished Mar 24 01:20:44 PM PDT 24
Peak memory 203540 kb
Host smart-e38a1e97-18c3-41d5-8ec6-f56cf85c6b7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=699648292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.699648292
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3346466682
Short name T73
Test name
Test status
Simulation time 44113966 ps
CPU time 2.04 seconds
Started Mar 24 01:20:12 PM PDT 24
Finished Mar 24 01:20:14 PM PDT 24
Peak memory 203496 kb
Host smart-13a049a3-72d0-40a2-8b0a-5aabb0d95c3c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346466682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3346466682
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.907935155
Short name T591
Test name
Test status
Simulation time 1050798133 ps
CPU time 186.4 seconds
Started Mar 24 01:20:15 PM PDT 24
Finished Mar 24 01:23:22 PM PDT 24
Peak memory 206044 kb
Host smart-ade0a096-3990-4bc9-a09e-084d19706242
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=907935155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.907935155
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1462533052
Short name T401
Test name
Test status
Simulation time 903215414 ps
CPU time 26.99 seconds
Started Mar 24 01:20:14 PM PDT 24
Finished Mar 24 01:20:42 PM PDT 24
Peak memory 204920 kb
Host smart-e0b6c4c5-0f38-48f6-ba9b-772c33fc406f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1462533052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1462533052
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2228140504
Short name T380
Test name
Test status
Simulation time 283458339 ps
CPU time 80.78 seconds
Started Mar 24 01:20:14 PM PDT 24
Finished Mar 24 01:21:35 PM PDT 24
Peak memory 207600 kb
Host smart-965edc30-b019-44ef-8370-4dc1613baf01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2228140504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.2228140504
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.8649391
Short name T34
Test name
Test status
Simulation time 6740281158 ps
CPU time 552.28 seconds
Started Mar 24 01:20:15 PM PDT 24
Finished Mar 24 01:29:28 PM PDT 24
Peak memory 221064 kb
Host smart-ec74e1dc-a4a6-421c-94d9-985242c68dee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8649391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_
error.8649391
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2618528150
Short name T140
Test name
Test status
Simulation time 365071792 ps
CPU time 16.95 seconds
Started Mar 24 01:20:14 PM PDT 24
Finished Mar 24 01:20:31 PM PDT 24
Peak memory 205040 kb
Host smart-ca2e7a78-8f45-40a5-b752-6580073cfa1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2618528150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2618528150
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3297883806
Short name T503
Test name
Test status
Simulation time 2733223703 ps
CPU time 56.21 seconds
Started Mar 24 01:21:19 PM PDT 24
Finished Mar 24 01:22:16 PM PDT 24
Peak memory 206836 kb
Host smart-4d1a37a7-8a4f-4e1e-aab0-b64548096bfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3297883806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3297883806
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3722855660
Short name T765
Test name
Test status
Simulation time 15498332476 ps
CPU time 138.17 seconds
Started Mar 24 01:21:20 PM PDT 24
Finished Mar 24 01:23:39 PM PDT 24
Peak memory 206144 kb
Host smart-867d80fb-3d0b-4563-bad8-63db521e38c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3722855660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.3722855660
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3144045267
Short name T807
Test name
Test status
Simulation time 202155924 ps
CPU time 18.89 seconds
Started Mar 24 01:21:25 PM PDT 24
Finished Mar 24 01:21:44 PM PDT 24
Peak memory 204296 kb
Host smart-cb80e191-583e-4fa3-bdcb-091aa4f4e970
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3144045267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3144045267
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.502385454
Short name T610
Test name
Test status
Simulation time 317308284 ps
CPU time 21.74 seconds
Started Mar 24 01:21:19 PM PDT 24
Finished Mar 24 01:21:41 PM PDT 24
Peak memory 203424 kb
Host smart-1966a5ec-4756-474e-b247-918152d73fc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502385454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.502385454
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.3162340201
Short name T208
Test name
Test status
Simulation time 178126501 ps
CPU time 18.48 seconds
Started Mar 24 01:21:19 PM PDT 24
Finished Mar 24 01:21:37 PM PDT 24
Peak memory 204596 kb
Host smart-6d595e78-bb03-4fe8-b1e8-baa085650d1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3162340201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3162340201
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3378006169
Short name T547
Test name
Test status
Simulation time 208806027847 ps
CPU time 239.58 seconds
Started Mar 24 01:21:18 PM PDT 24
Finished Mar 24 01:25:18 PM PDT 24
Peak memory 205176 kb
Host smart-5d28cab9-cacb-450d-b15d-a060ece4906a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378006169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3378006169
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1442236678
Short name T758
Test name
Test status
Simulation time 48839620952 ps
CPU time 232.07 seconds
Started Mar 24 01:21:20 PM PDT 24
Finished Mar 24 01:25:12 PM PDT 24
Peak memory 204896 kb
Host smart-2311b1aa-0e95-4b19-bded-fb63ae65af90
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1442236678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1442236678
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.4132120923
Short name T183
Test name
Test status
Simulation time 639548787 ps
CPU time 24.08 seconds
Started Mar 24 01:21:18 PM PDT 24
Finished Mar 24 01:21:42 PM PDT 24
Peak memory 204636 kb
Host smart-6abb0607-b6e8-45ee-b83e-0903698f52a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132120923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.4132120923
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.1474427846
Short name T172
Test name
Test status
Simulation time 628057773 ps
CPU time 13.66 seconds
Started Mar 24 01:21:19 PM PDT 24
Finished Mar 24 01:21:33 PM PDT 24
Peak memory 211688 kb
Host smart-de033c75-4462-42de-b611-229b5e3e2c88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1474427846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1474427846
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.3218241954
Short name T443
Test name
Test status
Simulation time 28022416 ps
CPU time 2.49 seconds
Started Mar 24 01:21:20 PM PDT 24
Finished Mar 24 01:21:23 PM PDT 24
Peak memory 203488 kb
Host smart-3207999e-43eb-4850-9b5f-62522bc32ced
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3218241954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3218241954
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2054109877
Short name T293
Test name
Test status
Simulation time 18939761296 ps
CPU time 30.1 seconds
Started Mar 24 01:21:19 PM PDT 24
Finished Mar 24 01:21:49 PM PDT 24
Peak memory 203572 kb
Host smart-050dbd29-2e5e-4228-9608-ca2f5455ed05
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054109877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2054109877
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1401808171
Short name T351
Test name
Test status
Simulation time 3649005925 ps
CPU time 31.55 seconds
Started Mar 24 01:21:18 PM PDT 24
Finished Mar 24 01:21:50 PM PDT 24
Peak memory 203552 kb
Host smart-f6ebc08b-68e8-4453-92f5-12830971dcf1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1401808171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1401808171
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1119777533
Short name T860
Test name
Test status
Simulation time 66891932 ps
CPU time 2.13 seconds
Started Mar 24 01:21:17 PM PDT 24
Finished Mar 24 01:21:20 PM PDT 24
Peak memory 203512 kb
Host smart-c0dfcf5d-7cd5-4240-b91d-b3ece0f491c2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119777533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1119777533
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2201367850
Short name T343
Test name
Test status
Simulation time 12143923765 ps
CPU time 214.56 seconds
Started Mar 24 01:21:24 PM PDT 24
Finished Mar 24 01:24:59 PM PDT 24
Peak memory 208452 kb
Host smart-ceb1144e-a821-4967-82a5-3eb7a4bed4af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2201367850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2201367850
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3265783632
Short name T431
Test name
Test status
Simulation time 513120794 ps
CPU time 155.52 seconds
Started Mar 24 01:21:24 PM PDT 24
Finished Mar 24 01:24:00 PM PDT 24
Peak memory 208344 kb
Host smart-7915b63d-7f02-41ec-9daf-c032bc604b05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3265783632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.3265783632
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2530036386
Short name T533
Test name
Test status
Simulation time 113026712 ps
CPU time 77.29 seconds
Started Mar 24 01:21:23 PM PDT 24
Finished Mar 24 01:22:40 PM PDT 24
Peak memory 207956 kb
Host smart-7ccfaefb-c970-46ae-a034-a46b62ac9dd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2530036386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.2530036386
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.3765734147
Short name T598
Test name
Test status
Simulation time 1102825972 ps
CPU time 21.16 seconds
Started Mar 24 01:21:22 PM PDT 24
Finished Mar 24 01:21:44 PM PDT 24
Peak memory 204944 kb
Host smart-dc545660-3044-495e-b283-50c233c03805
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3765734147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3765734147
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2876969150
Short name T895
Test name
Test status
Simulation time 182078575 ps
CPU time 11.01 seconds
Started Mar 24 01:21:23 PM PDT 24
Finished Mar 24 01:21:34 PM PDT 24
Peak memory 204224 kb
Host smart-dd990d61-7251-46df-8a2e-2959a576539c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2876969150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2876969150
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3854760739
Short name T445
Test name
Test status
Simulation time 2772915501 ps
CPU time 28.86 seconds
Started Mar 24 01:21:28 PM PDT 24
Finished Mar 24 01:21:58 PM PDT 24
Peak memory 203756 kb
Host smart-a133eb8e-46f2-4a3c-8426-be05e0ddfff0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3854760739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.3854760739
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3152798148
Short name T290
Test name
Test status
Simulation time 46688110 ps
CPU time 5.78 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:21:40 PM PDT 24
Peak memory 203464 kb
Host smart-ed862b00-ed4c-4761-9695-1fab5eb3ed8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3152798148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3152798148
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.4147772036
Short name T522
Test name
Test status
Simulation time 37176984 ps
CPU time 3.25 seconds
Started Mar 24 01:21:30 PM PDT 24
Finished Mar 24 01:21:34 PM PDT 24
Peak memory 203516 kb
Host smart-2e5f00e5-3e27-4908-8a95-41a3761750f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4147772036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.4147772036
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.4266328027
Short name T839
Test name
Test status
Simulation time 273138144 ps
CPU time 24.87 seconds
Started Mar 24 01:21:25 PM PDT 24
Finished Mar 24 01:21:52 PM PDT 24
Peak memory 205276 kb
Host smart-d2862556-9445-4650-8e8c-24b08ecdbcac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4266328027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.4266328027
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1614582621
Short name T891
Test name
Test status
Simulation time 36503830244 ps
CPU time 193.44 seconds
Started Mar 24 01:21:22 PM PDT 24
Finished Mar 24 01:24:36 PM PDT 24
Peak memory 205264 kb
Host smart-e4630f53-6b98-434e-8333-b921b728be0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614582621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1614582621
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3225667600
Short name T543
Test name
Test status
Simulation time 16695265525 ps
CPU time 139.28 seconds
Started Mar 24 01:21:26 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 204804 kb
Host smart-5212dfab-e7c5-4e95-9932-23f6047f47c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3225667600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3225667600
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.317594181
Short name T298
Test name
Test status
Simulation time 166154616 ps
CPU time 23.26 seconds
Started Mar 24 01:21:22 PM PDT 24
Finished Mar 24 01:21:45 PM PDT 24
Peak memory 204540 kb
Host smart-7a2d45c7-3cb4-4d4d-97e2-a01daf712a89
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317594181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.317594181
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.522554964
Short name T666
Test name
Test status
Simulation time 7634248169 ps
CPU time 36.16 seconds
Started Mar 24 01:21:28 PM PDT 24
Finished Mar 24 01:22:06 PM PDT 24
Peak memory 204624 kb
Host smart-2688c7f7-a84d-484d-95da-0c27c33554ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=522554964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.522554964
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.3630149963
Short name T392
Test name
Test status
Simulation time 38853974 ps
CPU time 2.17 seconds
Started Mar 24 01:21:26 PM PDT 24
Finished Mar 24 01:21:31 PM PDT 24
Peak memory 203804 kb
Host smart-2ca6410e-4781-4114-83b9-010f4ee746db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3630149963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3630149963
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.221558916
Short name T535
Test name
Test status
Simulation time 13735401683 ps
CPU time 28.14 seconds
Started Mar 24 01:21:25 PM PDT 24
Finished Mar 24 01:21:53 PM PDT 24
Peak memory 203880 kb
Host smart-d8de4d33-0caa-4d8d-8ad7-d14ebd6ab836
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=221558916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.221558916
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1541218517
Short name T831
Test name
Test status
Simulation time 4876232106 ps
CPU time 25.92 seconds
Started Mar 24 01:21:25 PM PDT 24
Finished Mar 24 01:21:51 PM PDT 24
Peak memory 203368 kb
Host smart-e99d7314-766c-457c-8cf6-1b1d24a8d8ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1541218517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1541218517
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2235735997
Short name T187
Test name
Test status
Simulation time 32716294 ps
CPU time 2.53 seconds
Started Mar 24 01:21:21 PM PDT 24
Finished Mar 24 01:21:24 PM PDT 24
Peak memory 203472 kb
Host smart-25f8c625-fb01-4f8c-a6c8-ea02ce034a29
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235735997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2235735997
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.4154428855
Short name T189
Test name
Test status
Simulation time 353785909 ps
CPU time 35.66 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:22:10 PM PDT 24
Peak memory 205312 kb
Host smart-762a36c3-d274-41d8-95fa-32c18c853e71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4154428855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4154428855
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3588993438
Short name T385
Test name
Test status
Simulation time 5622691626 ps
CPU time 170.82 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:24:25 PM PDT 24
Peak memory 208596 kb
Host smart-58de0e7e-d31c-45fd-994c-2a24db09bfb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3588993438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3588993438
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3948936687
Short name T771
Test name
Test status
Simulation time 86898204 ps
CPU time 61.99 seconds
Started Mar 24 01:21:28 PM PDT 24
Finished Mar 24 01:22:32 PM PDT 24
Peak memory 206656 kb
Host smart-114cb332-3987-4282-8096-cc49402c9b2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3948936687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.3948936687
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2101368367
Short name T473
Test name
Test status
Simulation time 2616311646 ps
CPU time 456.64 seconds
Started Mar 24 01:21:30 PM PDT 24
Finished Mar 24 01:29:07 PM PDT 24
Peak memory 219952 kb
Host smart-f58e33bd-b566-44be-b67d-5f64a48b0714
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2101368367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.2101368367
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1077414213
Short name T653
Test name
Test status
Simulation time 23613592 ps
CPU time 3.45 seconds
Started Mar 24 01:21:30 PM PDT 24
Finished Mar 24 01:21:34 PM PDT 24
Peak memory 204652 kb
Host smart-bed0ddf9-ec21-4c70-a50f-52a72a04bb9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1077414213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1077414213
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2132461475
Short name T238
Test name
Test status
Simulation time 420368043 ps
CPU time 14.3 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:21:47 PM PDT 24
Peak memory 204768 kb
Host smart-13900970-9ebc-4ccc-9542-da7a7e6e105f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2132461475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2132461475
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3215414740
Short name T760
Test name
Test status
Simulation time 40624603 ps
CPU time 1.71 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:21:36 PM PDT 24
Peak memory 203556 kb
Host smart-d84c45f8-a033-4c04-bedf-92e9f1f8eacd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3215414740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3215414740
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.3001224871
Short name T843
Test name
Test status
Simulation time 177211388 ps
CPU time 23.75 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:21:57 PM PDT 24
Peak memory 203768 kb
Host smart-65dee2d3-ad7f-4070-885d-8147b63ff881
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3001224871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3001224871
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.726872833
Short name T222
Test name
Test status
Simulation time 1275212941 ps
CPU time 10.02 seconds
Started Mar 24 01:21:28 PM PDT 24
Finished Mar 24 01:21:40 PM PDT 24
Peak memory 204700 kb
Host smart-0c1a4a5d-2204-47c0-b8c2-0f073c3d4a59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=726872833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.726872833
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3764062219
Short name T105
Test name
Test status
Simulation time 50497394193 ps
CPU time 205.44 seconds
Started Mar 24 01:21:35 PM PDT 24
Finished Mar 24 01:25:01 PM PDT 24
Peak memory 211788 kb
Host smart-c39bdba4-1d76-4827-bf43-2562168b4e6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764062219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3764062219
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.130863763
Short name T161
Test name
Test status
Simulation time 144509393859 ps
CPU time 328.68 seconds
Started Mar 24 01:21:36 PM PDT 24
Finished Mar 24 01:27:05 PM PDT 24
Peak memory 211724 kb
Host smart-b738c25c-60fe-4df3-869d-e859bdf53df8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=130863763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.130863763
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2882565926
Short name T426
Test name
Test status
Simulation time 37761689 ps
CPU time 4.95 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:21:38 PM PDT 24
Peak memory 203528 kb
Host smart-c867c4d3-5efd-4c34-8177-5bb9972539f5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882565926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2882565926
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1223659074
Short name T545
Test name
Test status
Simulation time 426325299 ps
CPU time 20.64 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:21:55 PM PDT 24
Peak memory 204092 kb
Host smart-dcac3d5f-ba7e-4f49-90e4-7d57fe77cb5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1223659074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1223659074
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.838134816
Short name T144
Test name
Test status
Simulation time 122530484 ps
CPU time 3.74 seconds
Started Mar 24 01:21:31 PM PDT 24
Finished Mar 24 01:21:35 PM PDT 24
Peak memory 203508 kb
Host smart-399d3ae5-e8a2-4c9b-a8fc-c0da7f41bd8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=838134816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.838134816
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3843825306
Short name T634
Test name
Test status
Simulation time 16729066167 ps
CPU time 39.42 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:22:13 PM PDT 24
Peak memory 203536 kb
Host smart-86d49a66-110c-45a2-832b-10bd7807970d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843825306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3843825306
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2631724614
Short name T749
Test name
Test status
Simulation time 2646507578 ps
CPU time 21.17 seconds
Started Mar 24 01:21:30 PM PDT 24
Finished Mar 24 01:21:52 PM PDT 24
Peak memory 203552 kb
Host smart-e7131350-d5c4-4ede-931b-372a67e2e64c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2631724614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2631724614
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.4038024272
Short name T94
Test name
Test status
Simulation time 100978605 ps
CPU time 2.06 seconds
Started Mar 24 01:21:29 PM PDT 24
Finished Mar 24 01:21:32 PM PDT 24
Peak memory 203468 kb
Host smart-a4c6c36a-4784-4dc7-8a76-76c63be41967
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038024272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.4038024272
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3003767821
Short name T868
Test name
Test status
Simulation time 14684815431 ps
CPU time 271.49 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:26:05 PM PDT 24
Peak memory 209352 kb
Host smart-b1eff923-92f1-425a-95ac-d21e143b6efe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3003767821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3003767821
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2624162455
Short name T633
Test name
Test status
Simulation time 9425020224 ps
CPU time 391.42 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:28:05 PM PDT 24
Peak memory 220064 kb
Host smart-4b7f63f0-35fb-4c67-8b8d-a32c0e3edf20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2624162455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.2624162455
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2288839291
Short name T745
Test name
Test status
Simulation time 66171135 ps
CPU time 8.27 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:21:42 PM PDT 24
Peak memory 204864 kb
Host smart-3dcfc1b9-db46-4ced-be77-3f6f50bf56f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2288839291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2288839291
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1656694490
Short name T24
Test name
Test status
Simulation time 3583791297 ps
CPU time 51.03 seconds
Started Mar 24 01:21:39 PM PDT 24
Finished Mar 24 01:22:30 PM PDT 24
Peak memory 205500 kb
Host smart-4e76e4a9-0022-430d-82fa-f50cb0ba6630
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1656694490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1656694490
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1114036924
Short name T128
Test name
Test status
Simulation time 102179497985 ps
CPU time 235.32 seconds
Started Mar 24 01:21:42 PM PDT 24
Finished Mar 24 01:25:37 PM PDT 24
Peak memory 205956 kb
Host smart-229c61a7-6173-4efe-8d3b-556ee0330536
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1114036924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.1114036924
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2868574243
Short name T198
Test name
Test status
Simulation time 444603823 ps
CPU time 17.3 seconds
Started Mar 24 01:21:38 PM PDT 24
Finished Mar 24 01:21:55 PM PDT 24
Peak memory 203432 kb
Host smart-470d52fc-5d22-46cf-bacc-29767ea85f89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2868574243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2868574243
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.1826807796
Short name T10
Test name
Test status
Simulation time 182650100 ps
CPU time 15.71 seconds
Started Mar 24 01:21:38 PM PDT 24
Finished Mar 24 01:21:53 PM PDT 24
Peak memory 203512 kb
Host smart-1d4a2d46-ac72-4940-b794-bf04f85905a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1826807796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1826807796
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.2164232785
Short name T848
Test name
Test status
Simulation time 2647641162 ps
CPU time 15.39 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:21:48 PM PDT 24
Peak memory 204632 kb
Host smart-1f7b23e8-7d26-4dc0-96f7-d2c9af87c92a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2164232785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2164232785
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.163518786
Short name T261
Test name
Test status
Simulation time 54775959614 ps
CPU time 204.51 seconds
Started Mar 24 01:21:38 PM PDT 24
Finished Mar 24 01:25:02 PM PDT 24
Peak memory 211748 kb
Host smart-58289849-782a-4812-b5b7-0de2872a9a79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=163518786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.163518786
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.407896696
Short name T282
Test name
Test status
Simulation time 50073572057 ps
CPU time 163.55 seconds
Started Mar 24 01:21:39 PM PDT 24
Finished Mar 24 01:24:23 PM PDT 24
Peak memory 204928 kb
Host smart-31845315-e166-4535-9ee9-b63ed4f257bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=407896696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.407896696
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1830693930
Short name T651
Test name
Test status
Simulation time 208061798 ps
CPU time 22.8 seconds
Started Mar 24 01:21:41 PM PDT 24
Finished Mar 24 01:22:04 PM PDT 24
Peak memory 204632 kb
Host smart-08ff0af7-01ef-4153-9724-dcdcbbf059ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830693930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1830693930
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.3585447178
Short name T762
Test name
Test status
Simulation time 898460635 ps
CPU time 8.25 seconds
Started Mar 24 01:21:37 PM PDT 24
Finished Mar 24 01:21:45 PM PDT 24
Peak memory 203852 kb
Host smart-f82d28b1-bff3-4b70-a287-0db4b5a9909b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585447178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3585447178
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.917022397
Short name T504
Test name
Test status
Simulation time 59000667 ps
CPU time 2.34 seconds
Started Mar 24 01:21:32 PM PDT 24
Finished Mar 24 01:21:35 PM PDT 24
Peak memory 203468 kb
Host smart-8991a136-8082-4ebe-99ec-39ed4bf8f130
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=917022397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.917022397
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2332636613
Short name T742
Test name
Test status
Simulation time 14752173942 ps
CPU time 34.61 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:22:09 PM PDT 24
Peak memory 203568 kb
Host smart-37a9f295-d577-4f4d-b977-2ddbecad33ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332636613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2332636613
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1413599986
Short name T464
Test name
Test status
Simulation time 3689862899 ps
CPU time 26.27 seconds
Started Mar 24 01:21:34 PM PDT 24
Finished Mar 24 01:22:00 PM PDT 24
Peak memory 203560 kb
Host smart-79fa625c-81a1-4ee8-be4c-e1c1752b7751
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1413599986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1413599986
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2328754467
Short name T294
Test name
Test status
Simulation time 111410237 ps
CPU time 2.35 seconds
Started Mar 24 01:21:33 PM PDT 24
Finished Mar 24 01:21:36 PM PDT 24
Peak memory 203520 kb
Host smart-f0f83b52-f93a-4e93-a244-900fbdda7aa7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328754467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2328754467
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3513222787
Short name T87
Test name
Test status
Simulation time 3526056826 ps
CPU time 125.78 seconds
Started Mar 24 01:21:38 PM PDT 24
Finished Mar 24 01:23:44 PM PDT 24
Peak memory 207264 kb
Host smart-d3b782bd-9eac-4b91-8ea7-ff6f1b8e65fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3513222787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3513222787
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2931778226
Short name T113
Test name
Test status
Simulation time 2284585309 ps
CPU time 95.84 seconds
Started Mar 24 01:21:39 PM PDT 24
Finished Mar 24 01:23:15 PM PDT 24
Peak memory 206996 kb
Host smart-c27248ae-5d81-4f2f-b999-c33a41d6646e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2931778226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2931778226
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1582102062
Short name T872
Test name
Test status
Simulation time 8798342125 ps
CPU time 174.92 seconds
Started Mar 24 01:21:41 PM PDT 24
Finished Mar 24 01:24:36 PM PDT 24
Peak memory 211656 kb
Host smart-6c163014-61c0-4cc4-8278-d6ff75801e38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1582102062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.1582102062
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1686189720
Short name T221
Test name
Test status
Simulation time 74928692 ps
CPU time 12.38 seconds
Started Mar 24 01:21:37 PM PDT 24
Finished Mar 24 01:21:50 PM PDT 24
Peak memory 205132 kb
Host smart-3404d753-0c94-4c68-a467-f53e5e58b1a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1686189720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1686189720
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.4110259061
Short name T663
Test name
Test status
Simulation time 13077917735 ps
CPU time 77 seconds
Started Mar 24 01:21:42 PM PDT 24
Finished Mar 24 01:22:59 PM PDT 24
Peak memory 205732 kb
Host smart-6e5de4d5-e6b3-4b1a-b339-b57e3d3a6db8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4110259061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.4110259061
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2260811181
Short name T741
Test name
Test status
Simulation time 11001489253 ps
CPU time 46.01 seconds
Started Mar 24 01:21:42 PM PDT 24
Finished Mar 24 01:22:29 PM PDT 24
Peak memory 205180 kb
Host smart-c38b5479-9b2a-4291-8cb7-90e8d3ad6ddf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2260811181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2260811181
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3443496644
Short name T774
Test name
Test status
Simulation time 917209040 ps
CPU time 17.84 seconds
Started Mar 24 01:21:44 PM PDT 24
Finished Mar 24 01:22:02 PM PDT 24
Peak memory 203444 kb
Host smart-5ed6afab-26ab-4713-be46-cd8632eb8680
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3443496644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3443496644
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.4128878113
Short name T834
Test name
Test status
Simulation time 278705265 ps
CPU time 19.71 seconds
Started Mar 24 01:21:44 PM PDT 24
Finished Mar 24 01:22:04 PM PDT 24
Peak memory 203508 kb
Host smart-b7bda657-5afe-4257-bf3f-7b56f941c763
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4128878113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4128878113
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.841999543
Short name T768
Test name
Test status
Simulation time 98080190 ps
CPU time 2.75 seconds
Started Mar 24 01:21:44 PM PDT 24
Finished Mar 24 01:21:47 PM PDT 24
Peak memory 203500 kb
Host smart-7cc5d1ff-c49f-4834-9a36-95c513057b6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=841999543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.841999543
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2745502727
Short name T811
Test name
Test status
Simulation time 36223876385 ps
CPU time 193.16 seconds
Started Mar 24 01:21:43 PM PDT 24
Finished Mar 24 01:24:57 PM PDT 24
Peak memory 205020 kb
Host smart-675f6189-f974-42c9-ae0a-de7de24f64b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745502727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2745502727
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3874474591
Short name T428
Test name
Test status
Simulation time 24188439481 ps
CPU time 64.2 seconds
Started Mar 24 01:21:43 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 204816 kb
Host smart-e6e66b9f-26f2-4a3a-9238-b6822d57390b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3874474591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3874474591
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.921337381
Short name T78
Test name
Test status
Simulation time 109544163 ps
CPU time 9.44 seconds
Started Mar 24 01:21:42 PM PDT 24
Finished Mar 24 01:21:51 PM PDT 24
Peak memory 204576 kb
Host smart-6cfbba1c-c352-40e0-ba6b-105a7c2f551c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921337381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.921337381
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1393070545
Short name T866
Test name
Test status
Simulation time 1410643104 ps
CPU time 26.91 seconds
Started Mar 24 01:21:45 PM PDT 24
Finished Mar 24 01:22:12 PM PDT 24
Peak memory 203164 kb
Host smart-1b3c3474-a898-4589-92f2-51f438b75ea4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1393070545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1393070545
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.1473645028
Short name T378
Test name
Test status
Simulation time 135813165 ps
CPU time 3.71 seconds
Started Mar 24 01:21:38 PM PDT 24
Finished Mar 24 01:21:41 PM PDT 24
Peak memory 203452 kb
Host smart-b4610b5c-6432-4385-9bd4-f69eec66ed4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1473645028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1473645028
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2606856871
Short name T747
Test name
Test status
Simulation time 9270934190 ps
CPU time 29.87 seconds
Started Mar 24 01:21:45 PM PDT 24
Finished Mar 24 01:22:15 PM PDT 24
Peak memory 203556 kb
Host smart-f51fd26f-27ef-4656-978d-4fb8a70d1d4f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606856871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2606856871
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3670570707
Short name T546
Test name
Test status
Simulation time 11392986104 ps
CPU time 32.25 seconds
Started Mar 24 01:21:45 PM PDT 24
Finished Mar 24 01:22:18 PM PDT 24
Peak memory 203532 kb
Host smart-c9dcb6e9-3063-4357-a4f6-2816ab72aa39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3670570707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3670570707
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4218430096
Short name T285
Test name
Test status
Simulation time 43761032 ps
CPU time 2.33 seconds
Started Mar 24 01:21:42 PM PDT 24
Finished Mar 24 01:21:44 PM PDT 24
Peak memory 203456 kb
Host smart-70f502a7-c999-48e6-95e4-93078fd34447
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218430096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4218430096
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.998222603
Short name T571
Test name
Test status
Simulation time 917184491 ps
CPU time 25.76 seconds
Started Mar 24 01:21:45 PM PDT 24
Finished Mar 24 01:22:11 PM PDT 24
Peak memory 205628 kb
Host smart-d20ffd91-c9f9-4459-956d-ca799e460f68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=998222603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.998222603
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2231671632
Short name T371
Test name
Test status
Simulation time 4113097201 ps
CPU time 115.5 seconds
Started Mar 24 01:21:43 PM PDT 24
Finished Mar 24 01:23:38 PM PDT 24
Peak memory 205156 kb
Host smart-2820949a-a18f-4d7e-a4f8-c798153cbc4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2231671632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2231671632
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.4252855720
Short name T245
Test name
Test status
Simulation time 42544373 ps
CPU time 18.43 seconds
Started Mar 24 01:21:42 PM PDT 24
Finished Mar 24 01:22:01 PM PDT 24
Peak memory 206468 kb
Host smart-0683f208-e577-4174-b337-74687cd0b5d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4252855720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.4252855720
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3871266189
Short name T312
Test name
Test status
Simulation time 3387155353 ps
CPU time 203.51 seconds
Started Mar 24 01:21:44 PM PDT 24
Finished Mar 24 01:25:07 PM PDT 24
Peak memory 211544 kb
Host smart-06ec0ba1-c3f7-473d-86a5-711a770daf1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3871266189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.3871266189
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3237816179
Short name T837
Test name
Test status
Simulation time 1607280699 ps
CPU time 16.87 seconds
Started Mar 24 01:21:43 PM PDT 24
Finished Mar 24 01:22:00 PM PDT 24
Peak memory 204808 kb
Host smart-cd49c439-93e8-4ab1-a493-b01e1791c7f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3237816179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3237816179
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3861332313
Short name T712
Test name
Test status
Simulation time 669901720 ps
CPU time 27.11 seconds
Started Mar 24 01:21:52 PM PDT 24
Finished Mar 24 01:22:19 PM PDT 24
Peak memory 211580 kb
Host smart-d9850128-9dfb-4d41-b0d7-a1268fc9cb37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3861332313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3861332313
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3980545030
Short name T152
Test name
Test status
Simulation time 47002804549 ps
CPU time 385.69 seconds
Started Mar 24 01:21:56 PM PDT 24
Finished Mar 24 01:28:22 PM PDT 24
Peak memory 206528 kb
Host smart-6a70629d-ab55-4d5a-aa68-412c6258170c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3980545030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.3980545030
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.4156930810
Short name T521
Test name
Test status
Simulation time 79278439 ps
CPU time 3.99 seconds
Started Mar 24 01:21:54 PM PDT 24
Finished Mar 24 01:21:59 PM PDT 24
Peak memory 203500 kb
Host smart-6b2ae6a6-7315-4c29-add1-c364aa4ab011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4156930810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4156930810
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.3507681303
Short name T772
Test name
Test status
Simulation time 318575218 ps
CPU time 23.53 seconds
Started Mar 24 01:21:54 PM PDT 24
Finished Mar 24 01:22:19 PM PDT 24
Peak memory 203552 kb
Host smart-90d4b7e3-7f32-4b0b-9282-4c31d1d3764e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3507681303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3507681303
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.2353164495
Short name T418
Test name
Test status
Simulation time 502212946 ps
CPU time 4.43 seconds
Started Mar 24 01:21:49 PM PDT 24
Finished Mar 24 01:21:53 PM PDT 24
Peak memory 203908 kb
Host smart-ac05989f-f621-4d5e-bacb-cb5688986f03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2353164495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2353164495
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2971287150
Short name T645
Test name
Test status
Simulation time 32148086754 ps
CPU time 190.02 seconds
Started Mar 24 01:21:53 PM PDT 24
Finished Mar 24 01:25:04 PM PDT 24
Peak memory 211768 kb
Host smart-59ed448d-6c0e-433a-8031-70d72337f347
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971287150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2971287150
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1031066909
Short name T890
Test name
Test status
Simulation time 19028306184 ps
CPU time 146.57 seconds
Started Mar 24 01:21:53 PM PDT 24
Finished Mar 24 01:24:20 PM PDT 24
Peak memory 204808 kb
Host smart-1b2ebe74-b501-4fc4-af69-0e45d766ca67
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1031066909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1031066909
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1836862683
Short name T717
Test name
Test status
Simulation time 65972294 ps
CPU time 8.04 seconds
Started Mar 24 01:21:53 PM PDT 24
Finished Mar 24 01:22:02 PM PDT 24
Peak memory 204496 kb
Host smart-e2c2a3c9-ef68-41ea-a3db-d35181ef2c4c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836862683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1836862683
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.3549634419
Short name T583
Test name
Test status
Simulation time 192187957 ps
CPU time 14.83 seconds
Started Mar 24 01:21:54 PM PDT 24
Finished Mar 24 01:22:10 PM PDT 24
Peak memory 204144 kb
Host smart-396e0575-293b-4af1-ad34-b83796715d7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549634419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3549634419
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.2283864969
Short name T375
Test name
Test status
Simulation time 158639221 ps
CPU time 3.36 seconds
Started Mar 24 01:21:45 PM PDT 24
Finished Mar 24 01:21:49 PM PDT 24
Peak memory 203464 kb
Host smart-c74f563e-9102-4d5e-bd97-8deefe40898a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2283864969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2283864969
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1826718441
Short name T572
Test name
Test status
Simulation time 4579389416 ps
CPU time 26.7 seconds
Started Mar 24 01:21:48 PM PDT 24
Finished Mar 24 01:22:15 PM PDT 24
Peak memory 203548 kb
Host smart-3b4a8e6b-6b72-4aa8-8dbb-efe7c4c9d3e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826718441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1826718441
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3493582137
Short name T673
Test name
Test status
Simulation time 9356544514 ps
CPU time 33.09 seconds
Started Mar 24 01:21:48 PM PDT 24
Finished Mar 24 01:22:22 PM PDT 24
Peak memory 203556 kb
Host smart-59112c53-6b81-446d-8b46-79ee7dc4393a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3493582137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3493582137
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.4271684278
Short name T244
Test name
Test status
Simulation time 136968380 ps
CPU time 2.59 seconds
Started Mar 24 01:21:47 PM PDT 24
Finished Mar 24 01:21:50 PM PDT 24
Peak memory 203472 kb
Host smart-881560b9-8295-460c-89f9-714f158c8709
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271684278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.4271684278
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1648689933
Short name T269
Test name
Test status
Simulation time 1295238540 ps
CPU time 52.01 seconds
Started Mar 24 01:21:54 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 206008 kb
Host smart-243fcef5-0112-4d9c-ae86-da0da88f23d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1648689933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1648689933
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1167550570
Short name T483
Test name
Test status
Simulation time 5042308909 ps
CPU time 202.53 seconds
Started Mar 24 01:21:56 PM PDT 24
Finished Mar 24 01:25:19 PM PDT 24
Peak memory 210060 kb
Host smart-46388d0e-ee53-42a1-93d8-77546d04fb62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1167550570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1167550570
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.419120343
Short name T318
Test name
Test status
Simulation time 6835145 ps
CPU time 0.81 seconds
Started Mar 24 01:21:55 PM PDT 24
Finished Mar 24 01:21:56 PM PDT 24
Peak memory 195212 kb
Host smart-d2fe7725-cdc3-4889-908c-53817644ec66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=419120343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand
_reset.419120343
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3437416868
Short name T519
Test name
Test status
Simulation time 220478537 ps
CPU time 66.72 seconds
Started Mar 24 01:21:52 PM PDT 24
Finished Mar 24 01:22:59 PM PDT 24
Peak memory 208032 kb
Host smart-ee521680-5f15-4999-b611-69017c794f8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437416868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.3437416868
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.4087354639
Short name T511
Test name
Test status
Simulation time 126529953 ps
CPU time 22.3 seconds
Started Mar 24 01:21:52 PM PDT 24
Finished Mar 24 01:22:14 PM PDT 24
Peak memory 204912 kb
Host smart-a171d583-cb82-419d-88bd-be73aeb04526
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4087354639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.4087354639
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1164470072
Short name T692
Test name
Test status
Simulation time 1021011796 ps
CPU time 41.02 seconds
Started Mar 24 01:21:58 PM PDT 24
Finished Mar 24 01:22:40 PM PDT 24
Peak memory 206212 kb
Host smart-30aab23b-0b31-4acb-b8b3-4966de1ac970
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1164470072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1164470072
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2298459023
Short name T234
Test name
Test status
Simulation time 27831523186 ps
CPU time 174.15 seconds
Started Mar 24 01:21:59 PM PDT 24
Finished Mar 24 01:24:54 PM PDT 24
Peak memory 206304 kb
Host smart-c08987d0-6b61-4b0c-b9ca-e60f9f2029a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2298459023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.2298459023
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2092456232
Short name T882
Test name
Test status
Simulation time 193271940 ps
CPU time 7.02 seconds
Started Mar 24 01:21:58 PM PDT 24
Finished Mar 24 01:22:06 PM PDT 24
Peak memory 203696 kb
Host smart-0c5cbb31-a450-495a-959c-1c09267d7614
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2092456232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2092456232
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.2212215597
Short name T275
Test name
Test status
Simulation time 144761395 ps
CPU time 15.13 seconds
Started Mar 24 01:21:56 PM PDT 24
Finished Mar 24 01:22:12 PM PDT 24
Peak memory 203500 kb
Host smart-799900c2-a983-4122-ba3e-729d78b344ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2212215597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2212215597
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.3030609004
Short name T469
Test name
Test status
Simulation time 129917631 ps
CPU time 5.68 seconds
Started Mar 24 01:22:00 PM PDT 24
Finished Mar 24 01:22:06 PM PDT 24
Peak memory 203520 kb
Host smart-a1711102-00da-4e17-a640-adc221806800
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3030609004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3030609004
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3078553712
Short name T163
Test name
Test status
Simulation time 24807198578 ps
CPU time 105.36 seconds
Started Mar 24 01:21:57 PM PDT 24
Finished Mar 24 01:23:42 PM PDT 24
Peak memory 211712 kb
Host smart-6e8d4af7-ddc5-4276-8ed2-cf21981039ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078553712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3078553712
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2594538833
Short name T832
Test name
Test status
Simulation time 23388917486 ps
CPU time 165.73 seconds
Started Mar 24 01:21:59 PM PDT 24
Finished Mar 24 01:24:45 PM PDT 24
Peak memory 204684 kb
Host smart-7b50fea8-3d24-4507-9de6-8aec8448a053
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2594538833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2594538833
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.1628942469
Short name T99
Test name
Test status
Simulation time 19356040 ps
CPU time 2.26 seconds
Started Mar 24 01:21:59 PM PDT 24
Finished Mar 24 01:22:02 PM PDT 24
Peak memory 203508 kb
Host smart-a94ec29a-a7e6-4ee3-8a93-b9236a7fc3ae
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628942469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1628942469
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.1582366596
Short name T95
Test name
Test status
Simulation time 550051370 ps
CPU time 6.66 seconds
Started Mar 24 01:22:00 PM PDT 24
Finished Mar 24 01:22:07 PM PDT 24
Peak memory 203680 kb
Host smart-4ee78720-ee7f-4cf8-8801-21292be29909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1582366596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1582366596
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.4153607776
Short name T648
Test name
Test status
Simulation time 132476710 ps
CPU time 3.18 seconds
Started Mar 24 01:21:54 PM PDT 24
Finished Mar 24 01:21:58 PM PDT 24
Peak memory 203472 kb
Host smart-9332b77c-c2ba-4561-8be4-cc8e38a1313e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4153607776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.4153607776
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1466237002
Short name T96
Test name
Test status
Simulation time 10417142996 ps
CPU time 26.79 seconds
Started Mar 24 01:21:58 PM PDT 24
Finished Mar 24 01:22:26 PM PDT 24
Peak memory 203556 kb
Host smart-a249fd17-6294-4682-9125-c8f64769cc71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466237002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1466237002
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2028213142
Short name T863
Test name
Test status
Simulation time 3343982429 ps
CPU time 29.82 seconds
Started Mar 24 01:21:57 PM PDT 24
Finished Mar 24 01:22:28 PM PDT 24
Peak memory 203796 kb
Host smart-562684e1-9066-4fde-a49d-d76c645f122e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2028213142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2028213142
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2814017966
Short name T796
Test name
Test status
Simulation time 26272599 ps
CPU time 2.18 seconds
Started Mar 24 01:21:55 PM PDT 24
Finished Mar 24 01:21:58 PM PDT 24
Peak memory 203444 kb
Host smart-64ceaf69-7461-4eb2-8cb4-d85b9d26f79f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814017966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2814017966
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.110025800
Short name T212
Test name
Test status
Simulation time 734130148 ps
CPU time 9.98 seconds
Started Mar 24 01:21:59 PM PDT 24
Finished Mar 24 01:22:09 PM PDT 24
Peak memory 204996 kb
Host smart-cffb4f58-f0d3-4c12-941a-96e2d3a74136
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110025800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.110025800
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.708488398
Short name T523
Test name
Test status
Simulation time 1200446409 ps
CPU time 88.69 seconds
Started Mar 24 01:22:03 PM PDT 24
Finished Mar 24 01:23:32 PM PDT 24
Peak memory 205852 kb
Host smart-60d6b48e-55fe-4bfa-a23f-09f2b7655381
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=708488398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.708488398
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3463729979
Short name T350
Test name
Test status
Simulation time 1484445576 ps
CPU time 406.61 seconds
Started Mar 24 01:21:59 PM PDT 24
Finished Mar 24 01:28:46 PM PDT 24
Peak memory 210208 kb
Host smart-1713f87e-8129-46c9-ac6c-7cf29ebf4cc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3463729979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.3463729979
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3387517838
Short name T258
Test name
Test status
Simulation time 3747100309 ps
CPU time 247.2 seconds
Started Mar 24 01:22:03 PM PDT 24
Finished Mar 24 01:26:11 PM PDT 24
Peak memory 219952 kb
Host smart-d3feb292-bbc8-4898-8c6a-8970828ee0d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3387517838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.3387517838
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.150325443
Short name T892
Test name
Test status
Simulation time 257430401 ps
CPU time 10.2 seconds
Started Mar 24 01:21:59 PM PDT 24
Finished Mar 24 01:22:10 PM PDT 24
Peak memory 211716 kb
Host smart-eb18cd15-c989-4ab5-b831-64c1517c125d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=150325443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.150325443
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2648782439
Short name T218
Test name
Test status
Simulation time 166640038 ps
CPU time 17.39 seconds
Started Mar 24 01:22:07 PM PDT 24
Finished Mar 24 01:22:24 PM PDT 24
Peak memory 211676 kb
Host smart-1a199f2e-5f40-43ae-818f-16c2d6a58dd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2648782439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2648782439
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3942405884
Short name T675
Test name
Test status
Simulation time 38093511873 ps
CPU time 238.99 seconds
Started Mar 24 01:22:09 PM PDT 24
Finished Mar 24 01:26:08 PM PDT 24
Peak memory 211720 kb
Host smart-3f0f8015-fb96-42c6-90d3-d0157da2cfb0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3942405884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.3942405884
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3495419827
Short name T534
Test name
Test status
Simulation time 102592176 ps
CPU time 13.64 seconds
Started Mar 24 01:22:11 PM PDT 24
Finished Mar 24 01:22:25 PM PDT 24
Peak memory 203804 kb
Host smart-0737c3ff-8a2e-446c-961e-d26e5ffa3be2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3495419827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3495419827
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.1291568803
Short name T642
Test name
Test status
Simulation time 402462066 ps
CPU time 18.45 seconds
Started Mar 24 01:22:10 PM PDT 24
Finished Mar 24 01:22:29 PM PDT 24
Peak memory 203564 kb
Host smart-f8135539-e8b4-4e0d-91e7-bce98d09653e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1291568803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1291568803
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.1832207042
Short name T878
Test name
Test status
Simulation time 587380072 ps
CPU time 17.61 seconds
Started Mar 24 01:22:07 PM PDT 24
Finished Mar 24 01:22:25 PM PDT 24
Peak memory 204596 kb
Host smart-004e6ad5-6e0d-4aeb-9923-173b7eb0eb04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1832207042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1832207042
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1565576137
Short name T475
Test name
Test status
Simulation time 136306445999 ps
CPU time 245.51 seconds
Started Mar 24 01:22:07 PM PDT 24
Finished Mar 24 01:26:13 PM PDT 24
Peak memory 204956 kb
Host smart-f0ad0f54-08a1-437d-8d7d-240bb3273179
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565576137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1565576137
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2344046039
Short name T348
Test name
Test status
Simulation time 24806781365 ps
CPU time 152.31 seconds
Started Mar 24 01:22:04 PM PDT 24
Finished Mar 24 01:24:37 PM PDT 24
Peak memory 211616 kb
Host smart-30f176eb-eafa-45af-9723-dd9fae91cce1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2344046039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2344046039
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.4203365695
Short name T565
Test name
Test status
Simulation time 560827574 ps
CPU time 19.93 seconds
Started Mar 24 01:22:04 PM PDT 24
Finished Mar 24 01:22:24 PM PDT 24
Peak memory 204848 kb
Host smart-b405c446-f551-449e-ad1b-f3a613a977c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203365695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.4203365695
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.3195984669
Short name T822
Test name
Test status
Simulation time 108454040 ps
CPU time 10.55 seconds
Started Mar 24 01:22:12 PM PDT 24
Finished Mar 24 01:22:23 PM PDT 24
Peak memory 204012 kb
Host smart-5f82fe73-fadc-4262-813d-091339950584
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3195984669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3195984669
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.3717815260
Short name T164
Test name
Test status
Simulation time 50788377 ps
CPU time 2.08 seconds
Started Mar 24 01:22:07 PM PDT 24
Finished Mar 24 01:22:10 PM PDT 24
Peak memory 203452 kb
Host smart-95ba1bc6-84d9-42a4-a8c4-2277ee960e23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3717815260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3717815260
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1458161304
Short name T840
Test name
Test status
Simulation time 7934652434 ps
CPU time 30.83 seconds
Started Mar 24 01:22:04 PM PDT 24
Finished Mar 24 01:22:35 PM PDT 24
Peak memory 203540 kb
Host smart-e4823e64-b55c-4aba-84f1-c6ca938639cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458161304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1458161304
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1910260203
Short name T56
Test name
Test status
Simulation time 6836901734 ps
CPU time 29.35 seconds
Started Mar 24 01:22:04 PM PDT 24
Finished Mar 24 01:22:34 PM PDT 24
Peak memory 203572 kb
Host smart-a2c1f081-6acf-44b2-9f3d-e8e9ce4f0923
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1910260203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1910260203
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3172311290
Short name T538
Test name
Test status
Simulation time 24053555 ps
CPU time 2.21 seconds
Started Mar 24 01:22:04 PM PDT 24
Finished Mar 24 01:22:06 PM PDT 24
Peak memory 203484 kb
Host smart-25d7f7cc-a7ad-4c41-b77e-e4da50cc6a56
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172311290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3172311290
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1561780409
Short name T84
Test name
Test status
Simulation time 9926121214 ps
CPU time 199.25 seconds
Started Mar 24 01:22:11 PM PDT 24
Finished Mar 24 01:25:31 PM PDT 24
Peak memory 211768 kb
Host smart-cb77fe09-9ebe-490b-9092-48b741033729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1561780409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1561780409
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2838988599
Short name T319
Test name
Test status
Simulation time 1612306811 ps
CPU time 37.72 seconds
Started Mar 24 01:22:09 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 204724 kb
Host smart-a76996d3-6b24-4aae-a927-cf42303b7ee9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2838988599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2838988599
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1123421427
Short name T214
Test name
Test status
Simulation time 135959596 ps
CPU time 29.73 seconds
Started Mar 24 01:22:13 PM PDT 24
Finished Mar 24 01:22:43 PM PDT 24
Peak memory 205744 kb
Host smart-af3d18e4-b0f4-4b14-b002-9f3a1c921332
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1123421427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.1123421427
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.301252934
Short name T681
Test name
Test status
Simulation time 68146431 ps
CPU time 37.09 seconds
Started Mar 24 01:22:12 PM PDT 24
Finished Mar 24 01:22:50 PM PDT 24
Peak memory 206240 kb
Host smart-9666cd59-f714-44e1-8138-f8df0aacae1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=301252934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res
et_error.301252934
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1129087711
Short name T467
Test name
Test status
Simulation time 854237087 ps
CPU time 11.73 seconds
Started Mar 24 01:22:12 PM PDT 24
Finished Mar 24 01:22:24 PM PDT 24
Peak memory 211640 kb
Host smart-12cfffa6-a727-40af-a6bc-d6fd097f3f26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1129087711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1129087711
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1465333000
Short name T192
Test name
Test status
Simulation time 382731475 ps
CPU time 34.21 seconds
Started Mar 24 01:22:12 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 206108 kb
Host smart-97b0f813-aac5-4db6-aa02-f13e738f0a27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1465333000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1465333000
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1651628644
Short name T564
Test name
Test status
Simulation time 20041757542 ps
CPU time 182.87 seconds
Started Mar 24 01:22:13 PM PDT 24
Finished Mar 24 01:25:16 PM PDT 24
Peak memory 205932 kb
Host smart-d1eccd49-2f27-4c25-98f3-5994da31e9de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1651628644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.1651628644
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3934920945
Short name T486
Test name
Test status
Simulation time 740023226 ps
CPU time 13.6 seconds
Started Mar 24 01:22:13 PM PDT 24
Finished Mar 24 01:22:27 PM PDT 24
Peak memory 203860 kb
Host smart-0229b6d6-8fa2-45b6-9d75-85044acddfda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934920945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3934920945
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.2625016237
Short name T574
Test name
Test status
Simulation time 716198363 ps
CPU time 23.81 seconds
Started Mar 24 01:22:09 PM PDT 24
Finished Mar 24 01:22:33 PM PDT 24
Peak memory 203432 kb
Host smart-a1a5fa05-5df5-45f2-9535-448e98e08aec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2625016237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2625016237
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.598361916
Short name T54
Test name
Test status
Simulation time 1714637157 ps
CPU time 34.28 seconds
Started Mar 24 01:22:09 PM PDT 24
Finished Mar 24 01:22:44 PM PDT 24
Peak memory 204572 kb
Host smart-1d52512a-d7ff-4684-afff-941a8f3ad64c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=598361916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.598361916
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1808530216
Short name T316
Test name
Test status
Simulation time 14345620036 ps
CPU time 73.78 seconds
Started Mar 24 01:22:09 PM PDT 24
Finished Mar 24 01:23:23 PM PDT 24
Peak memory 204940 kb
Host smart-65319a83-8c01-4179-9c7a-bc0230330e45
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808530216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1808530216
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2331359051
Short name T804
Test name
Test status
Simulation time 50721522034 ps
CPU time 263.13 seconds
Started Mar 24 01:22:08 PM PDT 24
Finished Mar 24 01:26:31 PM PDT 24
Peak memory 211732 kb
Host smart-c6d54315-5cde-47f3-86ad-2c1ba326f1a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2331359051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2331359051
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.168674142
Short name T799
Test name
Test status
Simulation time 17157916 ps
CPU time 2.06 seconds
Started Mar 24 01:22:10 PM PDT 24
Finished Mar 24 01:22:12 PM PDT 24
Peak memory 203480 kb
Host smart-331cadb5-9aa3-4e0e-8b3a-48fe762278ef
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168674142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.168674142
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.3538140213
Short name T17
Test name
Test status
Simulation time 3299575117 ps
CPU time 28.54 seconds
Started Mar 24 01:22:08 PM PDT 24
Finished Mar 24 01:22:37 PM PDT 24
Peak memory 204188 kb
Host smart-c139b9d0-1fa5-4eda-91af-51839d005dd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3538140213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3538140213
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.1320593601
Short name T90
Test name
Test status
Simulation time 151280316 ps
CPU time 3.37 seconds
Started Mar 24 01:22:10 PM PDT 24
Finished Mar 24 01:22:13 PM PDT 24
Peak memory 203520 kb
Host smart-62452674-8818-45f9-bb73-2c040dc8131a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1320593601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1320593601
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.141318021
Short name T324
Test name
Test status
Simulation time 18477412055 ps
CPU time 36.51 seconds
Started Mar 24 01:22:10 PM PDT 24
Finished Mar 24 01:22:46 PM PDT 24
Peak memory 203536 kb
Host smart-7552d360-7487-4bf7-8cfd-d13ed5797466
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=141318021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.141318021
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2802884
Short name T728
Test name
Test status
Simulation time 5453522545 ps
CPU time 33.03 seconds
Started Mar 24 01:22:08 PM PDT 24
Finished Mar 24 01:22:41 PM PDT 24
Peak memory 203568 kb
Host smart-8ed0b8d0-e273-4fa7-9c71-4e0d6fc22eb0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2802884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2802884
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.915000483
Short name T446
Test name
Test status
Simulation time 32207894 ps
CPU time 2.85 seconds
Started Mar 24 01:22:13 PM PDT 24
Finished Mar 24 01:22:15 PM PDT 24
Peak memory 203492 kb
Host smart-e5ef748a-c067-4c21-badf-4ceaef4ae1c2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915000483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.915000483
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.227883893
Short name T85
Test name
Test status
Simulation time 10838093404 ps
CPU time 109.01 seconds
Started Mar 24 01:22:16 PM PDT 24
Finished Mar 24 01:24:05 PM PDT 24
Peak memory 207180 kb
Host smart-dacc8a79-ca5e-4f4b-9296-3b631f69de41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=227883893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.227883893
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1880529216
Short name T757
Test name
Test status
Simulation time 1409994108 ps
CPU time 114.65 seconds
Started Mar 24 01:22:14 PM PDT 24
Finished Mar 24 01:24:09 PM PDT 24
Peak memory 206720 kb
Host smart-4e2c3de6-56c4-4428-a25d-173d438acb19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1880529216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1880529216
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.409986344
Short name T346
Test name
Test status
Simulation time 297055651 ps
CPU time 157.94 seconds
Started Mar 24 01:22:13 PM PDT 24
Finished Mar 24 01:24:51 PM PDT 24
Peak memory 208304 kb
Host smart-b258e908-10f0-4d0d-b91b-5eca82587473
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=409986344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand
_reset.409986344
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3876159697
Short name T425
Test name
Test status
Simulation time 2411938864 ps
CPU time 362.04 seconds
Started Mar 24 01:22:14 PM PDT 24
Finished Mar 24 01:28:16 PM PDT 24
Peak memory 211364 kb
Host smart-d6b3c15a-f043-4345-96a3-86d0e5ae36d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3876159697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.3876159697
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3254872931
Short name T145
Test name
Test status
Simulation time 311980665 ps
CPU time 14.82 seconds
Started Mar 24 01:22:10 PM PDT 24
Finished Mar 24 01:22:25 PM PDT 24
Peak memory 205064 kb
Host smart-6972507e-482a-4c3e-903d-e9d895839cc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3254872931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3254872931
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2628591955
Short name T341
Test name
Test status
Simulation time 223986863 ps
CPU time 11 seconds
Started Mar 24 01:22:19 PM PDT 24
Finished Mar 24 01:22:32 PM PDT 24
Peak memory 204088 kb
Host smart-15e813e5-cba7-4464-a244-35a90bcc7dea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2628591955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2628591955
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1491271183
Short name T150
Test name
Test status
Simulation time 3749637078 ps
CPU time 28.21 seconds
Started Mar 24 01:22:21 PM PDT 24
Finished Mar 24 01:22:49 PM PDT 24
Peak memory 203780 kb
Host smart-edeab722-afaa-4545-87b3-da47857716c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1491271183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.1491271183
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1186527221
Short name T202
Test name
Test status
Simulation time 94005910 ps
CPU time 4.63 seconds
Started Mar 24 01:22:21 PM PDT 24
Finished Mar 24 01:22:26 PM PDT 24
Peak memory 203656 kb
Host smart-e87bb544-4d10-4bd9-af5a-c24bacbdd800
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1186527221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1186527221
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.1488382347
Short name T721
Test name
Test status
Simulation time 791563490 ps
CPU time 23.27 seconds
Started Mar 24 01:22:20 PM PDT 24
Finished Mar 24 01:22:44 PM PDT 24
Peak memory 203520 kb
Host smart-eb20ac74-caf7-4fd7-bcdc-3cb97f623cfb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1488382347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1488382347
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.469562181
Short name T167
Test name
Test status
Simulation time 909173091 ps
CPU time 16.57 seconds
Started Mar 24 01:22:13 PM PDT 24
Finished Mar 24 01:22:30 PM PDT 24
Peak memory 204564 kb
Host smart-50c6a2bd-105c-4515-a5a7-e4c61d3441f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=469562181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.469562181
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2573644549
Short name T432
Test name
Test status
Simulation time 55987897716 ps
CPU time 141.58 seconds
Started Mar 24 01:22:15 PM PDT 24
Finished Mar 24 01:24:36 PM PDT 24
Peak memory 204920 kb
Host smart-b520ba58-2fee-4e89-b5c3-ea64aaba5ddc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573644549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2573644549
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.540961617
Short name T463
Test name
Test status
Simulation time 136899637126 ps
CPU time 334.24 seconds
Started Mar 24 01:22:16 PM PDT 24
Finished Mar 24 01:27:50 PM PDT 24
Peak memory 204684 kb
Host smart-46c4e652-f3c5-4a9e-a4a7-9d4bd25be5be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=540961617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.540961617
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.437628037
Short name T278
Test name
Test status
Simulation time 103757941 ps
CPU time 11.74 seconds
Started Mar 24 01:22:15 PM PDT 24
Finished Mar 24 01:22:26 PM PDT 24
Peak memory 204652 kb
Host smart-b1b11959-d615-471e-a735-20d340a33e86
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437628037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.437628037
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.2862725198
Short name T411
Test name
Test status
Simulation time 30440324 ps
CPU time 2.49 seconds
Started Mar 24 01:22:21 PM PDT 24
Finished Mar 24 01:22:23 PM PDT 24
Peak memory 203752 kb
Host smart-187338a4-d132-49a4-9f7d-e6265d4075bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2862725198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2862725198
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2383710355
Short name T494
Test name
Test status
Simulation time 271509637 ps
CPU time 2.95 seconds
Started Mar 24 01:22:16 PM PDT 24
Finished Mar 24 01:22:19 PM PDT 24
Peak memory 203480 kb
Host smart-32c54f96-68c9-4bf1-b102-ba98b35bcf8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2383710355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2383710355
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2423180388
Short name T409
Test name
Test status
Simulation time 4863133000 ps
CPU time 28.99 seconds
Started Mar 24 01:22:15 PM PDT 24
Finished Mar 24 01:22:44 PM PDT 24
Peak memory 203556 kb
Host smart-a8bb7368-d0f9-42fe-8063-dc1f8cd36a25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423180388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2423180388
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1407051799
Short name T360
Test name
Test status
Simulation time 6055747065 ps
CPU time 35.52 seconds
Started Mar 24 01:22:21 PM PDT 24
Finished Mar 24 01:22:56 PM PDT 24
Peak memory 203552 kb
Host smart-1963de28-ee42-4423-b32c-b6b450c341da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1407051799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1407051799
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3008400087
Short name T596
Test name
Test status
Simulation time 34804276 ps
CPU time 2.56 seconds
Started Mar 24 01:22:15 PM PDT 24
Finished Mar 24 01:22:18 PM PDT 24
Peak memory 203500 kb
Host smart-0d194d43-316e-454c-958f-6719a721aa30
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008400087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3008400087
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1727943647
Short name T30
Test name
Test status
Simulation time 1961221497 ps
CPU time 174 seconds
Started Mar 24 01:22:22 PM PDT 24
Finished Mar 24 01:25:16 PM PDT 24
Peak memory 209604 kb
Host smart-71daccc1-86a1-41a8-b7d6-1f3b2492a542
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1727943647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1727943647
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2877504305
Short name T561
Test name
Test status
Simulation time 19886719598 ps
CPU time 256.3 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:26:41 PM PDT 24
Peak memory 210068 kb
Host smart-c6451624-a489-49c0-86de-079c6708a2f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2877504305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2877504305
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1067845764
Short name T851
Test name
Test status
Simulation time 3053007350 ps
CPU time 319.08 seconds
Started Mar 24 01:22:20 PM PDT 24
Finished Mar 24 01:27:40 PM PDT 24
Peak memory 211772 kb
Host smart-3e7858e3-486d-47b7-8d08-c9ed924d064a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1067845764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.1067845764
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.657570307
Short name T77
Test name
Test status
Simulation time 68376275 ps
CPU time 22.16 seconds
Started Mar 24 01:22:21 PM PDT 24
Finished Mar 24 01:22:43 PM PDT 24
Peak memory 205764 kb
Host smart-13e11ea7-25e0-4172-836d-93f06c6b2dbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=657570307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res
et_error.657570307
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2379124025
Short name T823
Test name
Test status
Simulation time 27409593 ps
CPU time 3.43 seconds
Started Mar 24 01:22:20 PM PDT 24
Finished Mar 24 01:22:24 PM PDT 24
Peak memory 204552 kb
Host smart-eb1f6616-abea-40f1-bac1-c60bcb467be0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2379124025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2379124025
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1824973266
Short name T373
Test name
Test status
Simulation time 900617819 ps
CPU time 20.13 seconds
Started Mar 24 01:20:19 PM PDT 24
Finished Mar 24 01:20:39 PM PDT 24
Peak memory 211696 kb
Host smart-0c23223f-1ef8-4455-9c3f-a7af37ae392e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1824973266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1824973266
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.118939986
Short name T727
Test name
Test status
Simulation time 27286217749 ps
CPU time 153.57 seconds
Started Mar 24 01:20:20 PM PDT 24
Finished Mar 24 01:22:54 PM PDT 24
Peak memory 205848 kb
Host smart-a06421e1-599d-43ce-8216-a4675840b5bd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=118939986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow
_rsp.118939986
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4114066557
Short name T548
Test name
Test status
Simulation time 18049352 ps
CPU time 1.78 seconds
Started Mar 24 01:20:24 PM PDT 24
Finished Mar 24 01:20:26 PM PDT 24
Peak memory 203492 kb
Host smart-175ad4bd-6ac7-4a3e-98dd-51459ed403b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4114066557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4114066557
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.306889
Short name T250
Test name
Test status
Simulation time 50412080 ps
CPU time 2.33 seconds
Started Mar 24 01:20:25 PM PDT 24
Finished Mar 24 01:20:28 PM PDT 24
Peak memory 203484 kb
Host smart-2d2a2c28-99fa-4079-a9e6-268e9f379404
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=306889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.306889
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.2232149983
Short name T419
Test name
Test status
Simulation time 166246488 ps
CPU time 5.73 seconds
Started Mar 24 01:20:23 PM PDT 24
Finished Mar 24 01:20:29 PM PDT 24
Peak memory 204020 kb
Host smart-32842a54-13a5-4a6f-8102-d064a73b5de8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2232149983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2232149983
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3037944585
Short name T124
Test name
Test status
Simulation time 44898830405 ps
CPU time 245.05 seconds
Started Mar 24 01:20:20 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 204724 kb
Host smart-43e0bea7-1910-471c-acc9-9098f493d821
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037944585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3037944585
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2642312859
Short name T334
Test name
Test status
Simulation time 18489468762 ps
CPU time 75.86 seconds
Started Mar 24 01:20:20 PM PDT 24
Finished Mar 24 01:21:36 PM PDT 24
Peak memory 204848 kb
Host smart-b00e3cb4-4695-428b-8f83-a924ddff77a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2642312859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2642312859
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3411789239
Short name T224
Test name
Test status
Simulation time 214112255 ps
CPU time 24.77 seconds
Started Mar 24 01:20:20 PM PDT 24
Finished Mar 24 01:20:45 PM PDT 24
Peak memory 211648 kb
Host smart-daf62cd7-36fb-41a1-8ebb-16d432440765
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411789239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3411789239
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.2768452159
Short name T362
Test name
Test status
Simulation time 374143898 ps
CPU time 18.53 seconds
Started Mar 24 01:20:27 PM PDT 24
Finished Mar 24 01:20:46 PM PDT 24
Peak memory 203512 kb
Host smart-453bd3a9-77af-42b7-9967-e512af86b444
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2768452159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2768452159
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.3685882433
Short name T444
Test name
Test status
Simulation time 35592937 ps
CPU time 2.47 seconds
Started Mar 24 01:20:15 PM PDT 24
Finished Mar 24 01:20:18 PM PDT 24
Peak memory 203472 kb
Host smart-007e4dda-ca26-4663-99db-ed494355e197
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3685882433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3685882433
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2671733326
Short name T877
Test name
Test status
Simulation time 7250517014 ps
CPU time 27.91 seconds
Started Mar 24 01:20:19 PM PDT 24
Finished Mar 24 01:20:47 PM PDT 24
Peak memory 203548 kb
Host smart-46895e85-9c14-4da5-bc4e-640bfcd8c95d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671733326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2671733326
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1118122018
Short name T103
Test name
Test status
Simulation time 4974828628 ps
CPU time 32.33 seconds
Started Mar 24 01:20:20 PM PDT 24
Finished Mar 24 01:20:53 PM PDT 24
Peak memory 203580 kb
Host smart-f55a506d-f317-4e04-985a-ac14357719f1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1118122018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1118122018
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.126973943
Short name T489
Test name
Test status
Simulation time 105594251 ps
CPU time 2.31 seconds
Started Mar 24 01:20:19 PM PDT 24
Finished Mar 24 01:20:22 PM PDT 24
Peak memory 203524 kb
Host smart-c73d05b2-1b33-4ff8-9e7e-9aa072155942
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126973943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.126973943
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3014666782
Short name T356
Test name
Test status
Simulation time 1525601413 ps
CPU time 124.71 seconds
Started Mar 24 01:20:26 PM PDT 24
Finished Mar 24 01:22:32 PM PDT 24
Peak memory 207696 kb
Host smart-c7c9bcfe-799b-4801-b8ca-d578879d7b9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3014666782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3014666782
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1696784438
Short name T333
Test name
Test status
Simulation time 4399579598 ps
CPU time 40.24 seconds
Started Mar 24 01:20:27 PM PDT 24
Finished Mar 24 01:21:08 PM PDT 24
Peak memory 205372 kb
Host smart-0143b723-222b-4837-bf0f-d5960b0ce7e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1696784438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1696784438
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3574167122
Short name T131
Test name
Test status
Simulation time 11586510764 ps
CPU time 288.08 seconds
Started Mar 24 01:20:27 PM PDT 24
Finished Mar 24 01:25:16 PM PDT 24
Peak memory 210664 kb
Host smart-22e742f9-5c38-47ca-a832-0264a6b395e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3574167122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.3574167122
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.945165854
Short name T306
Test name
Test status
Simulation time 3238287850 ps
CPU time 460.71 seconds
Started Mar 24 01:20:24 PM PDT 24
Finished Mar 24 01:28:05 PM PDT 24
Peak memory 219908 kb
Host smart-6833a344-5e1b-4ccf-bd0b-c660e1b0bc6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=945165854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese
t_error.945165854
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2511295805
Short name T406
Test name
Test status
Simulation time 609762740 ps
CPU time 17.91 seconds
Started Mar 24 01:20:25 PM PDT 24
Finished Mar 24 01:20:44 PM PDT 24
Peak memory 204848 kb
Host smart-e89cddfb-3add-4db5-a76c-3ee9cfcdf2bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2511295805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2511295805
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1944806124
Short name T777
Test name
Test status
Simulation time 735376957 ps
CPU time 19.29 seconds
Started Mar 24 01:22:26 PM PDT 24
Finished Mar 24 01:22:48 PM PDT 24
Peak memory 204896 kb
Host smart-d9b00627-1c8a-4dbd-98f3-c67fb3bf272e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1944806124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1944806124
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3547411843
Short name T491
Test name
Test status
Simulation time 90546059976 ps
CPU time 453.13 seconds
Started Mar 24 01:22:23 PM PDT 24
Finished Mar 24 01:29:57 PM PDT 24
Peak memory 206876 kb
Host smart-9400bcd1-7c73-4ef4-a4fc-6a7ccc8d5ecb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3547411843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3547411843
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1276533255
Short name T876
Test name
Test status
Simulation time 202019503 ps
CPU time 15.04 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:39 PM PDT 24
Peak memory 203832 kb
Host smart-25b0d62c-08e3-4b16-b359-2680c0c5c8e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1276533255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1276533255
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.181076382
Short name T847
Test name
Test status
Simulation time 470281537 ps
CPU time 23.8 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:48 PM PDT 24
Peak memory 203504 kb
Host smart-cfec69e0-7966-4ebc-9445-b19b6c74717d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=181076382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.181076382
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.4086917854
Short name T399
Test name
Test status
Simulation time 536496719 ps
CPU time 17.18 seconds
Started Mar 24 01:22:20 PM PDT 24
Finished Mar 24 01:22:38 PM PDT 24
Peak memory 211648 kb
Host smart-2e6c9e3b-2fe5-49b2-b767-5b14a9e4c686
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4086917854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.4086917854
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.4017841652
Short name T53
Test name
Test status
Simulation time 39763173878 ps
CPU time 185.74 seconds
Started Mar 24 01:22:23 PM PDT 24
Finished Mar 24 01:25:29 PM PDT 24
Peak memory 204696 kb
Host smart-1f8db3a8-cbf3-4c27-8839-7582509149e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017841652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4017841652
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1022783889
Short name T79
Test name
Test status
Simulation time 43605901885 ps
CPU time 266.41 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:26:50 PM PDT 24
Peak memory 205328 kb
Host smart-422bcc58-63aa-49ef-8429-725b5d7e8be9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1022783889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1022783889
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2906522561
Short name T321
Test name
Test status
Simulation time 289779908 ps
CPU time 14.81 seconds
Started Mar 24 01:22:22 PM PDT 24
Finished Mar 24 01:22:37 PM PDT 24
Peak memory 204600 kb
Host smart-61f1e214-d912-4235-8a8d-ada66688c43b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906522561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2906522561
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.3191118257
Short name T791
Test name
Test status
Simulation time 746786801 ps
CPU time 14.75 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:39 PM PDT 24
Peak memory 203948 kb
Host smart-609930fc-94be-4fa5-8ddf-6597bb983baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3191118257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3191118257
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.597494198
Short name T339
Test name
Test status
Simulation time 33970913 ps
CPU time 2.05 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:26 PM PDT 24
Peak memory 203484 kb
Host smart-ae6601b3-18fe-44ca-9f64-8289bc94fbcd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=597494198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.597494198
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.239511684
Short name T613
Test name
Test status
Simulation time 9053574139 ps
CPU time 36.56 seconds
Started Mar 24 01:22:20 PM PDT 24
Finished Mar 24 01:22:58 PM PDT 24
Peak memory 203572 kb
Host smart-89021e40-9aee-4674-9406-15691a588d94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=239511684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.239511684
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3017242348
Short name T702
Test name
Test status
Simulation time 11249594229 ps
CPU time 30.4 seconds
Started Mar 24 01:22:21 PM PDT 24
Finished Mar 24 01:22:51 PM PDT 24
Peak memory 203536 kb
Host smart-df8bff25-a976-4faa-8510-29dbaa9432f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3017242348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3017242348
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.447490299
Short name T649
Test name
Test status
Simulation time 38219124 ps
CPU time 2.58 seconds
Started Mar 24 01:22:19 PM PDT 24
Finished Mar 24 01:22:24 PM PDT 24
Peak memory 203480 kb
Host smart-de696b1f-f289-4af4-9d3f-7b89172bd10f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447490299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.447490299
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.836849613
Short name T896
Test name
Test status
Simulation time 10574744195 ps
CPU time 216.41 seconds
Started Mar 24 01:22:25 PM PDT 24
Finished Mar 24 01:26:05 PM PDT 24
Peak memory 210248 kb
Host smart-c598698f-ac70-4ffb-96ff-b3d105d19283
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=836849613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.836849613
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2664267760
Short name T12
Test name
Test status
Simulation time 992916598 ps
CPU time 107.5 seconds
Started Mar 24 01:22:23 PM PDT 24
Finished Mar 24 01:24:11 PM PDT 24
Peak memory 206232 kb
Host smart-8decd9ec-7a8d-4052-b304-8140fcdb9b7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2664267760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2664267760
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.394437256
Short name T107
Test name
Test status
Simulation time 8084804172 ps
CPU time 473.88 seconds
Started Mar 24 01:22:25 PM PDT 24
Finished Mar 24 01:30:22 PM PDT 24
Peak memory 208912 kb
Host smart-9084f7e0-16da-4afe-841a-86265d623152
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=394437256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand
_reset.394437256
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1186002988
Short name T795
Test name
Test status
Simulation time 459743432 ps
CPU time 134.1 seconds
Started Mar 24 01:22:23 PM PDT 24
Finished Mar 24 01:24:37 PM PDT 24
Peak memory 210408 kb
Host smart-53a7b9bd-bbc2-4f43-8a5f-42afa21f283b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1186002988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.1186002988
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2297351965
Short name T510
Test name
Test status
Simulation time 28470623 ps
CPU time 3.84 seconds
Started Mar 24 01:22:23 PM PDT 24
Finished Mar 24 01:22:27 PM PDT 24
Peak memory 204544 kb
Host smart-e10d41cc-25a3-45db-a287-e824c17605d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2297351965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2297351965
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.457726065
Short name T166
Test name
Test status
Simulation time 1522572539 ps
CPU time 51.63 seconds
Started Mar 24 01:22:28 PM PDT 24
Finished Mar 24 01:23:20 PM PDT 24
Peak memory 205316 kb
Host smart-cad0ba15-a442-4e14-b938-e097cba4221e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=457726065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.457726065
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2256139876
Short name T852
Test name
Test status
Simulation time 75664317936 ps
CPU time 628.76 seconds
Started Mar 24 01:22:28 PM PDT 24
Finished Mar 24 01:32:57 PM PDT 24
Peak memory 207504 kb
Host smart-315b06c6-15fe-4497-8351-2597fd23eefe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2256139876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.2256139876
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1598368071
Short name T722
Test name
Test status
Simulation time 96858991 ps
CPU time 3.51 seconds
Started Mar 24 01:22:27 PM PDT 24
Finished Mar 24 01:22:32 PM PDT 24
Peak memory 203596 kb
Host smart-56429a68-7a6e-4b5b-9653-4564b9a9d040
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1598368071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1598368071
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.1017653879
Short name T732
Test name
Test status
Simulation time 286098076 ps
CPU time 18.49 seconds
Started Mar 24 01:22:29 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 203568 kb
Host smart-a6146d8f-6adc-4178-93e1-b31e49e0d7d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1017653879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1017653879
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.2680399398
Short name T241
Test name
Test status
Simulation time 181374841 ps
CPU time 14 seconds
Started Mar 24 01:22:26 PM PDT 24
Finished Mar 24 01:22:42 PM PDT 24
Peak memory 204584 kb
Host smart-d58393ba-1579-4208-84f7-e5ed3e5e6d3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2680399398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2680399398
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.388750452
Short name T457
Test name
Test status
Simulation time 161827537324 ps
CPU time 286.49 seconds
Started Mar 24 01:22:29 PM PDT 24
Finished Mar 24 01:27:16 PM PDT 24
Peak memory 204888 kb
Host smart-25bc1faf-8123-4a45-82cc-04465c520d3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=388750452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.388750452
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1403518423
Short name T900
Test name
Test status
Simulation time 27092664465 ps
CPU time 207.83 seconds
Started Mar 24 01:22:28 PM PDT 24
Finished Mar 24 01:25:56 PM PDT 24
Peak memory 205356 kb
Host smart-a0e77940-9d50-42e5-872b-405b1a2021b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1403518423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1403518423
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3860466472
Short name T361
Test name
Test status
Simulation time 53578014 ps
CPU time 4.5 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:28 PM PDT 24
Peak memory 204616 kb
Host smart-a449804d-273e-4911-b5a9-b2c6444d615b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860466472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3860466472
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.2850588612
Short name T635
Test name
Test status
Simulation time 1376023722 ps
CPU time 29.42 seconds
Started Mar 24 01:22:30 PM PDT 24
Finished Mar 24 01:22:59 PM PDT 24
Peak memory 204068 kb
Host smart-75d42bb3-ade4-4311-91a3-776e433edfa7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2850588612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2850588612
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.1761089752
Short name T236
Test name
Test status
Simulation time 146915973 ps
CPU time 3.2 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:27 PM PDT 24
Peak memory 203464 kb
Host smart-e8ac4f28-8409-457f-9eb0-ff88c74e7dcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1761089752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1761089752
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4100567592
Short name T300
Test name
Test status
Simulation time 6006941665 ps
CPU time 28.31 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:52 PM PDT 24
Peak memory 203556 kb
Host smart-2d8a9c3c-ce60-4964-b9a4-ab8f19912098
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100567592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4100567592
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.859772955
Short name T516
Test name
Test status
Simulation time 6690868198 ps
CPU time 30.92 seconds
Started Mar 24 01:22:24 PM PDT 24
Finished Mar 24 01:22:55 PM PDT 24
Peak memory 203564 kb
Host smart-02998182-0fe5-4fa9-8bfd-21280fc0f7e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=859772955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.859772955
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.576401988
Short name T826
Test name
Test status
Simulation time 43649350 ps
CPU time 2.37 seconds
Started Mar 24 01:22:26 PM PDT 24
Finished Mar 24 01:22:31 PM PDT 24
Peak memory 203492 kb
Host smart-2c750157-96b3-4b98-ac1e-e54a7a11258f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576401988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.576401988
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3011733370
Short name T595
Test name
Test status
Simulation time 980641917 ps
CPU time 93.99 seconds
Started Mar 24 01:22:31 PM PDT 24
Finished Mar 24 01:24:05 PM PDT 24
Peak memory 207740 kb
Host smart-9e84402f-281d-4138-8794-368c1850ff04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3011733370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3011733370
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1904045080
Short name T678
Test name
Test status
Simulation time 7567365864 ps
CPU time 102.38 seconds
Started Mar 24 01:22:27 PM PDT 24
Finished Mar 24 01:24:11 PM PDT 24
Peak memory 205416 kb
Host smart-2669ae51-a7c1-4ef3-888f-2140dbc70920
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1904045080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1904045080
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1445168702
Short name T724
Test name
Test status
Simulation time 1974760005 ps
CPU time 134.13 seconds
Started Mar 24 01:22:28 PM PDT 24
Finished Mar 24 01:24:43 PM PDT 24
Peak memory 208128 kb
Host smart-c3a80cf8-37e0-4494-a1ee-2c7aa777b181
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1445168702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.1445168702
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1879835578
Short name T874
Test name
Test status
Simulation time 5408883382 ps
CPU time 216.58 seconds
Started Mar 24 01:22:30 PM PDT 24
Finished Mar 24 01:26:07 PM PDT 24
Peak memory 209048 kb
Host smart-1c10c2b0-10c6-4292-b3ea-604b172d301c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1879835578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.1879835578
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.44970644
Short name T42
Test name
Test status
Simulation time 202337319 ps
CPU time 7.94 seconds
Started Mar 24 01:22:29 PM PDT 24
Finished Mar 24 01:22:37 PM PDT 24
Peak memory 211652 kb
Host smart-44e451ed-7a93-42c2-a044-c550d1f225a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44970644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.44970644
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1704025629
Short name T468
Test name
Test status
Simulation time 1074102380 ps
CPU time 49.9 seconds
Started Mar 24 01:22:32 PM PDT 24
Finished Mar 24 01:23:22 PM PDT 24
Peak memory 205648 kb
Host smart-4b64ad7e-3465-45ca-b39a-b03e4e16a92c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1704025629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1704025629
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.738555917
Short name T405
Test name
Test status
Simulation time 69442413949 ps
CPU time 581.33 seconds
Started Mar 24 01:22:32 PM PDT 24
Finished Mar 24 01:32:14 PM PDT 24
Peak memory 207516 kb
Host smart-67d474c1-b558-48d3-9a80-61dd98ed4b66
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=738555917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slo
w_rsp.738555917
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.292699652
Short name T357
Test name
Test status
Simulation time 97757788 ps
CPU time 11.74 seconds
Started Mar 24 01:22:44 PM PDT 24
Finished Mar 24 01:22:56 PM PDT 24
Peak memory 203928 kb
Host smart-3a3c37b6-4ee0-4d86-8f48-86c9cd3db588
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=292699652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.292699652
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.2949358102
Short name T505
Test name
Test status
Simulation time 1156243740 ps
CPU time 39.41 seconds
Started Mar 24 01:22:33 PM PDT 24
Finished Mar 24 01:23:13 PM PDT 24
Peak memory 203500 kb
Host smart-9b997c8f-120e-4299-93c3-fd208643b9ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2949358102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2949358102
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.3388813758
Short name T775
Test name
Test status
Simulation time 339294052 ps
CPU time 16.29 seconds
Started Mar 24 01:22:35 PM PDT 24
Finished Mar 24 01:22:52 PM PDT 24
Peak memory 204748 kb
Host smart-fd902f79-087d-4b6f-bf14-d508a86173a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3388813758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3388813758
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2810404944
Short name T688
Test name
Test status
Simulation time 3754551458 ps
CPU time 26.86 seconds
Started Mar 24 01:22:33 PM PDT 24
Finished Mar 24 01:23:00 PM PDT 24
Peak memory 203484 kb
Host smart-0a33cfb9-de4e-4bc0-b9de-870b8e45dcbb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810404944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2810404944
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.821430816
Short name T47
Test name
Test status
Simulation time 21790954730 ps
CPU time 140.79 seconds
Started Mar 24 01:22:33 PM PDT 24
Finished Mar 24 01:24:54 PM PDT 24
Peak memory 205116 kb
Host smart-246c9c9e-cd87-4533-adea-7cc67f59e3a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=821430816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.821430816
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.245106683
Short name T690
Test name
Test status
Simulation time 28069227 ps
CPU time 3.01 seconds
Started Mar 24 01:22:34 PM PDT 24
Finished Mar 24 01:22:37 PM PDT 24
Peak memory 204168 kb
Host smart-0edb3b33-8b11-4ca7-8711-c8e2c3269a95
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245106683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.245106683
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.181992402
Short name T657
Test name
Test status
Simulation time 2153731410 ps
CPU time 29.32 seconds
Started Mar 24 01:22:34 PM PDT 24
Finished Mar 24 01:23:03 PM PDT 24
Peak memory 204220 kb
Host smart-8c732e54-534e-4d93-b113-31af18f5b9bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=181992402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.181992402
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.3198449474
Short name T102
Test name
Test status
Simulation time 258158966 ps
CPU time 4.34 seconds
Started Mar 24 01:22:33 PM PDT 24
Finished Mar 24 01:22:38 PM PDT 24
Peak memory 203732 kb
Host smart-328524d4-3e91-4011-82a4-ef69dc21d8e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3198449474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3198449474
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3499901615
Short name T466
Test name
Test status
Simulation time 11972186630 ps
CPU time 31.57 seconds
Started Mar 24 01:22:34 PM PDT 24
Finished Mar 24 01:23:05 PM PDT 24
Peak memory 203556 kb
Host smart-905bed99-1d5c-4d0a-a509-549e700ca363
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499901615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3499901615
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2952322161
Short name T283
Test name
Test status
Simulation time 3893668595 ps
CPU time 33.91 seconds
Started Mar 24 01:22:34 PM PDT 24
Finished Mar 24 01:23:08 PM PDT 24
Peak memory 203584 kb
Host smart-d577e64e-d93e-4484-95e1-d28dc1cf8ccf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2952322161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2952322161
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2925936297
Short name T257
Test name
Test status
Simulation time 27139068 ps
CPU time 2.59 seconds
Started Mar 24 01:22:34 PM PDT 24
Finished Mar 24 01:22:37 PM PDT 24
Peak memory 203520 kb
Host smart-86b97d5c-86ca-4151-91c9-2ad63c6acae6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925936297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2925936297
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.138163095
Short name T5
Test name
Test status
Simulation time 876630700 ps
CPU time 117.79 seconds
Started Mar 24 01:22:40 PM PDT 24
Finished Mar 24 01:24:38 PM PDT 24
Peak memory 208188 kb
Host smart-577ce792-ada2-49ea-98d5-9160a3ce671f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=138163095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.138163095
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.969228103
Short name T330
Test name
Test status
Simulation time 13124347330 ps
CPU time 176.82 seconds
Started Mar 24 01:22:39 PM PDT 24
Finished Mar 24 01:25:36 PM PDT 24
Peak memory 206628 kb
Host smart-e5335637-d20d-4094-aa14-72775926f019
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=969228103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.969228103
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.219843947
Short name T230
Test name
Test status
Simulation time 120184271 ps
CPU time 28.54 seconds
Started Mar 24 01:22:39 PM PDT 24
Finished Mar 24 01:23:08 PM PDT 24
Peak memory 206024 kb
Host smart-a27a11d9-1f17-479f-b986-f7523800f20a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=219843947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand
_reset.219843947
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.733915777
Short name T815
Test name
Test status
Simulation time 1793767552 ps
CPU time 241.14 seconds
Started Mar 24 01:22:38 PM PDT 24
Finished Mar 24 01:26:40 PM PDT 24
Peak memory 219844 kb
Host smart-ad1882e1-7b8b-4f40-88d0-a1388369490c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=733915777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res
et_error.733915777
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2681341956
Short name T827
Test name
Test status
Simulation time 1723826824 ps
CPU time 31.2 seconds
Started Mar 24 01:22:40 PM PDT 24
Finished Mar 24 01:23:11 PM PDT 24
Peak memory 204724 kb
Host smart-f91ee906-d210-4297-945f-1c92d0d35c76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2681341956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2681341956
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1729900320
Short name T176
Test name
Test status
Simulation time 448114518 ps
CPU time 19.67 seconds
Started Mar 24 01:22:38 PM PDT 24
Finished Mar 24 01:22:58 PM PDT 24
Peak memory 204212 kb
Host smart-39a5d312-0475-431e-9b5e-daa6372af7f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1729900320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1729900320
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.4271769937
Short name T263
Test name
Test status
Simulation time 8939562849 ps
CPU time 47.25 seconds
Started Mar 24 01:22:42 PM PDT 24
Finished Mar 24 01:23:29 PM PDT 24
Peak memory 211700 kb
Host smart-61b4d100-b7d2-4622-92c7-80bfe43219c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4271769937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.4271769937
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3964848584
Short name T769
Test name
Test status
Simulation time 727153429 ps
CPU time 20.7 seconds
Started Mar 24 01:22:45 PM PDT 24
Finished Mar 24 01:23:06 PM PDT 24
Peak memory 204024 kb
Host smart-a89a86d6-dbad-444d-9866-9d75ae486461
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3964848584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3964848584
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.67734808
Short name T864
Test name
Test status
Simulation time 74132560 ps
CPU time 9.51 seconds
Started Mar 24 01:22:38 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 203484 kb
Host smart-3033a8e7-31e0-4535-9a3d-4a8f2e89c729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67734808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.67734808
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.3549213298
Short name T141
Test name
Test status
Simulation time 245570749 ps
CPU time 10.3 seconds
Started Mar 24 01:22:37 PM PDT 24
Finished Mar 24 01:22:48 PM PDT 24
Peak memory 204604 kb
Host smart-1ea69e00-c405-491b-aa6f-147f1565309a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549213298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3549213298
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2721225385
Short name T345
Test name
Test status
Simulation time 40062025280 ps
CPU time 203.26 seconds
Started Mar 24 01:22:40 PM PDT 24
Finished Mar 24 01:26:03 PM PDT 24
Peak memory 204788 kb
Host smart-3766b959-4925-4c3a-b6fa-29da7e34cda9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721225385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2721225385
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3143423009
Short name T817
Test name
Test status
Simulation time 5462119718 ps
CPU time 15.32 seconds
Started Mar 24 01:22:40 PM PDT 24
Finished Mar 24 01:22:56 PM PDT 24
Peak memory 203812 kb
Host smart-a14cdaa1-386a-423a-b85b-029e335a1b75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3143423009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3143423009
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3407875529
Short name T824
Test name
Test status
Simulation time 457347432 ps
CPU time 30.84 seconds
Started Mar 24 01:22:39 PM PDT 24
Finished Mar 24 01:23:10 PM PDT 24
Peak memory 211680 kb
Host smart-85cef55b-3d62-4e3a-9e06-917132d99448
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407875529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3407875529
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.3937119021
Short name T184
Test name
Test status
Simulation time 288723677 ps
CPU time 7.79 seconds
Started Mar 24 01:22:38 PM PDT 24
Finished Mar 24 01:22:46 PM PDT 24
Peak memory 203760 kb
Host smart-96b3c289-476c-44f7-9021-2fd62d2f8939
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3937119021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3937119021
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.2845224965
Short name T668
Test name
Test status
Simulation time 186803550 ps
CPU time 4.01 seconds
Started Mar 24 01:22:39 PM PDT 24
Finished Mar 24 01:22:43 PM PDT 24
Peak memory 203424 kb
Host smart-253be276-6ae5-4474-b6c6-f88b857c6dab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2845224965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2845224965
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.211666964
Short name T785
Test name
Test status
Simulation time 9778453658 ps
CPU time 26.02 seconds
Started Mar 24 01:22:40 PM PDT 24
Finished Mar 24 01:23:06 PM PDT 24
Peak memory 203560 kb
Host smart-702204c8-b715-45bc-a47b-b57f9892f89d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=211666964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.211666964
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.751245830
Short name T875
Test name
Test status
Simulation time 22378254714 ps
CPU time 53.76 seconds
Started Mar 24 01:22:42 PM PDT 24
Finished Mar 24 01:23:36 PM PDT 24
Peak memory 203532 kb
Host smart-63db541c-3001-46c6-9005-3bfee69ba563
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=751245830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.751245830
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1541718373
Short name T733
Test name
Test status
Simulation time 68487947 ps
CPU time 2.29 seconds
Started Mar 24 01:22:39 PM PDT 24
Finished Mar 24 01:22:42 PM PDT 24
Peak memory 203512 kb
Host smart-2cfa08b2-4e8f-45db-ba42-50e57be7b17f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541718373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1541718373
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1944075273
Short name T783
Test name
Test status
Simulation time 506308334 ps
CPU time 36.29 seconds
Started Mar 24 01:22:44 PM PDT 24
Finished Mar 24 01:23:21 PM PDT 24
Peak memory 205868 kb
Host smart-7d9880b9-a4b7-4027-9fb1-d46405b7a941
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1944075273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1944075273
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3750902551
Short name T711
Test name
Test status
Simulation time 2239916324 ps
CPU time 20.26 seconds
Started Mar 24 01:22:45 PM PDT 24
Finished Mar 24 01:23:05 PM PDT 24
Peak memory 203564 kb
Host smart-46b1db10-2f0d-4784-83fc-877c35615e20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3750902551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3750902551
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1965153761
Short name T243
Test name
Test status
Simulation time 467663698 ps
CPU time 220.5 seconds
Started Mar 24 01:22:45 PM PDT 24
Finished Mar 24 01:26:25 PM PDT 24
Peak memory 208412 kb
Host smart-f0268417-cccd-480c-834c-2e60bfb4d9d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1965153761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.1965153761
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2281482946
Short name T723
Test name
Test status
Simulation time 4523409124 ps
CPU time 153.36 seconds
Started Mar 24 01:22:45 PM PDT 24
Finished Mar 24 01:25:19 PM PDT 24
Peak memory 211748 kb
Host smart-b45ccd31-aee5-4934-b0e3-7fb689eb880e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281482946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.2281482946
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.78067029
Short name T577
Test name
Test status
Simulation time 261723388 ps
CPU time 7.53 seconds
Started Mar 24 01:22:40 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 204892 kb
Host smart-2679c4de-6dcd-483c-a3dd-58c21f1df6c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78067029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.78067029
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.966875384
Short name T581
Test name
Test status
Simulation time 2440548151 ps
CPU time 47.17 seconds
Started Mar 24 01:22:43 PM PDT 24
Finished Mar 24 01:23:30 PM PDT 24
Peak memory 206172 kb
Host smart-5ffb3a47-3936-4fb6-9e47-b23604ca0531
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=966875384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.966875384
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3907370544
Short name T86
Test name
Test status
Simulation time 31385270508 ps
CPU time 217.03 seconds
Started Mar 24 01:22:42 PM PDT 24
Finished Mar 24 01:26:20 PM PDT 24
Peak memory 206032 kb
Host smart-cb1a9f1d-5c25-48a3-b4a3-33d9a4d38577
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3907370544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.3907370544
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2596606117
Short name T478
Test name
Test status
Simulation time 159091941 ps
CPU time 11.8 seconds
Started Mar 24 01:22:49 PM PDT 24
Finished Mar 24 01:23:01 PM PDT 24
Peak memory 203796 kb
Host smart-f4c9b071-2088-4528-8f7f-7c882bc4d523
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2596606117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2596606117
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.94117518
Short name T254
Test name
Test status
Simulation time 110042601 ps
CPU time 2.69 seconds
Started Mar 24 01:22:44 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 203512 kb
Host smart-e46e5395-aab6-460e-b74d-601a7116ec88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94117518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.94117518
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.2052099290
Short name T41
Test name
Test status
Simulation time 856346775 ps
CPU time 30.84 seconds
Started Mar 24 01:22:44 PM PDT 24
Finished Mar 24 01:23:16 PM PDT 24
Peak memory 204964 kb
Host smart-88894def-c968-4e4b-ab0e-2639edf4bf48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2052099290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2052099290
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2843479390
Short name T524
Test name
Test status
Simulation time 16440715803 ps
CPU time 101.6 seconds
Started Mar 24 01:22:42 PM PDT 24
Finished Mar 24 01:24:24 PM PDT 24
Peak memory 205108 kb
Host smart-4ebe874f-a8f3-4cbc-a09c-f8de063d01bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843479390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2843479390
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.956660304
Short name T266
Test name
Test status
Simulation time 20064236574 ps
CPU time 177.32 seconds
Started Mar 24 01:22:43 PM PDT 24
Finished Mar 24 01:25:41 PM PDT 24
Peak memory 205028 kb
Host smart-f1cd4df7-9c93-455f-a9b2-dc5dd7ce92c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=956660304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.956660304
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2853868658
Short name T743
Test name
Test status
Simulation time 41894573 ps
CPU time 6.73 seconds
Started Mar 24 01:22:45 PM PDT 24
Finished Mar 24 01:22:52 PM PDT 24
Peak memory 204588 kb
Host smart-fcd19f19-7622-42bd-ab7a-dbd6f17af43c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853868658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2853868658
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.3117114729
Short name T487
Test name
Test status
Simulation time 2975728635 ps
CPU time 33.14 seconds
Started Mar 24 01:22:42 PM PDT 24
Finished Mar 24 01:23:16 PM PDT 24
Peak memory 204184 kb
Host smart-39fbe6d9-02db-4d88-b5f5-7b1f98ab544b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3117114729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3117114729
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.1804094707
Short name T554
Test name
Test status
Simulation time 25272305 ps
CPU time 2.38 seconds
Started Mar 24 01:22:43 PM PDT 24
Finished Mar 24 01:22:46 PM PDT 24
Peak memory 203468 kb
Host smart-b5ac28b9-a597-4840-82ce-301641c2e46e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804094707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1804094707
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3974171673
Short name T232
Test name
Test status
Simulation time 11417706439 ps
CPU time 33.05 seconds
Started Mar 24 01:22:42 PM PDT 24
Finished Mar 24 01:23:15 PM PDT 24
Peak memory 203560 kb
Host smart-b1868d8b-2a15-40d0-a708-8910c45356ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974171673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3974171673
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3730786703
Short name T44
Test name
Test status
Simulation time 4306049128 ps
CPU time 34.49 seconds
Started Mar 24 01:22:44 PM PDT 24
Finished Mar 24 01:23:19 PM PDT 24
Peak memory 203556 kb
Host smart-06034fbf-fb2f-4063-b357-7a901167b00a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3730786703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3730786703
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3238440486
Short name T490
Test name
Test status
Simulation time 50883549 ps
CPU time 2.13 seconds
Started Mar 24 01:22:43 PM PDT 24
Finished Mar 24 01:22:46 PM PDT 24
Peak memory 203496 kb
Host smart-d5b003f3-c71e-42dd-ac1d-524edd712e2b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238440486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3238440486
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1785542011
Short name T174
Test name
Test status
Simulation time 11291517380 ps
CPU time 88.79 seconds
Started Mar 24 01:22:49 PM PDT 24
Finished Mar 24 01:24:17 PM PDT 24
Peak memory 206920 kb
Host smart-8aed748a-ce37-4ad2-a8c0-ba3ea02cd50b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1785542011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1785542011
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2696813515
Short name T650
Test name
Test status
Simulation time 7987070584 ps
CPU time 191.97 seconds
Started Mar 24 01:22:48 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 209704 kb
Host smart-3b8d47f6-f9aa-40f9-adbf-94f49bbb1b8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2696813515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2696813515
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3732119253
Short name T179
Test name
Test status
Simulation time 542107472 ps
CPU time 174.83 seconds
Started Mar 24 01:22:47 PM PDT 24
Finished Mar 24 01:25:42 PM PDT 24
Peak memory 208636 kb
Host smart-3d832707-b96f-403b-9bf7-b62a2e4c2088
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3732119253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.3732119253
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3537138929
Short name T615
Test name
Test status
Simulation time 5931532311 ps
CPU time 368.53 seconds
Started Mar 24 01:22:48 PM PDT 24
Finished Mar 24 01:28:57 PM PDT 24
Peak memory 219932 kb
Host smart-84a7447b-cfc0-4b16-8dd9-b49bceda0969
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3537138929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.3537138929
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.109739475
Short name T850
Test name
Test status
Simulation time 943183809 ps
CPU time 26.82 seconds
Started Mar 24 01:22:51 PM PDT 24
Finished Mar 24 01:23:18 PM PDT 24
Peak memory 204772 kb
Host smart-0de62af8-13c8-4c4e-b3f3-f52356a2edf3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109739475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.109739475
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3257968471
Short name T800
Test name
Test status
Simulation time 70085620925 ps
CPU time 457.37 seconds
Started Mar 24 01:22:53 PM PDT 24
Finished Mar 24 01:30:30 PM PDT 24
Peak memory 211700 kb
Host smart-2b564ca6-a9a1-4bd2-89ca-f8cc5563a08c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3257968471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.3257968471
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1697638515
Short name T501
Test name
Test status
Simulation time 637360047 ps
CPU time 18.84 seconds
Started Mar 24 01:22:52 PM PDT 24
Finished Mar 24 01:23:11 PM PDT 24
Peak memory 204084 kb
Host smart-0776e3f1-9cd0-4fc2-84b7-dabaaf341745
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1697638515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1697638515
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.1011853876
Short name T292
Test name
Test status
Simulation time 1754871246 ps
CPU time 21.56 seconds
Started Mar 24 01:22:53 PM PDT 24
Finished Mar 24 01:23:15 PM PDT 24
Peak memory 203500 kb
Host smart-b1797526-7c2b-4949-8299-1113d6e46ae0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1011853876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1011853876
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.2486766249
Short name T518
Test name
Test status
Simulation time 52954377 ps
CPU time 7.41 seconds
Started Mar 24 01:22:50 PM PDT 24
Finished Mar 24 01:22:57 PM PDT 24
Peak memory 204696 kb
Host smart-632f0e0e-79ff-4450-bd7b-6e3e73d2d955
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2486766249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2486766249
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3696360866
Short name T65
Test name
Test status
Simulation time 11737785571 ps
CPU time 73.71 seconds
Started Mar 24 01:22:48 PM PDT 24
Finished Mar 24 01:24:02 PM PDT 24
Peak memory 204852 kb
Host smart-ca13b1f3-1fde-436c-bf3d-1e1d2683cec2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696360866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3696360866
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2046268460
Short name T46
Test name
Test status
Simulation time 4278515847 ps
CPU time 30.72 seconds
Started Mar 24 01:22:50 PM PDT 24
Finished Mar 24 01:23:20 PM PDT 24
Peak memory 203604 kb
Host smart-1c9d2368-233f-4f59-9ff4-a614cea906dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2046268460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2046268460
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2453236568
Short name T68
Test name
Test status
Simulation time 60155275 ps
CPU time 7.98 seconds
Started Mar 24 01:22:49 PM PDT 24
Finished Mar 24 01:22:57 PM PDT 24
Peak memory 204636 kb
Host smart-41c9f28c-2723-44ae-a9e2-d09d15cabe28
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453236568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2453236568
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.2374943865
Short name T301
Test name
Test status
Simulation time 108503152 ps
CPU time 3.2 seconds
Started Mar 24 01:22:53 PM PDT 24
Finished Mar 24 01:22:56 PM PDT 24
Peak memory 203464 kb
Host smart-4726441e-691a-4f03-b743-7417e53301a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2374943865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2374943865
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.522507353
Short name T706
Test name
Test status
Simulation time 41278141 ps
CPU time 2.25 seconds
Started Mar 24 01:22:48 PM PDT 24
Finished Mar 24 01:22:51 PM PDT 24
Peak memory 203472 kb
Host smart-80d31e66-82a0-4ed8-a520-5572912e7197
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=522507353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.522507353
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3862160194
Short name T416
Test name
Test status
Simulation time 17012783168 ps
CPU time 38.03 seconds
Started Mar 24 01:22:48 PM PDT 24
Finished Mar 24 01:23:26 PM PDT 24
Peak memory 203536 kb
Host smart-adba4c49-8ff6-451d-9f13-a50c2ee701ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862160194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3862160194
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3814853828
Short name T748
Test name
Test status
Simulation time 9298024301 ps
CPU time 32.22 seconds
Started Mar 24 01:22:47 PM PDT 24
Finished Mar 24 01:23:19 PM PDT 24
Peak memory 203564 kb
Host smart-e3682e8a-e394-4f34-b431-98949d7ed915
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3814853828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3814853828
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.4029430393
Short name T173
Test name
Test status
Simulation time 87865959 ps
CPU time 2.56 seconds
Started Mar 24 01:22:50 PM PDT 24
Finished Mar 24 01:22:53 PM PDT 24
Peak memory 203520 kb
Host smart-127ca71e-8398-4ec6-bc1a-364af466a77e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029430393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.4029430393
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.954481604
Short name T237
Test name
Test status
Simulation time 713947756 ps
CPU time 80.29 seconds
Started Mar 24 01:23:00 PM PDT 24
Finished Mar 24 01:24:21 PM PDT 24
Peak memory 205356 kb
Host smart-dcdef2c8-5531-460f-8b76-be59160b6cb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=954481604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.954481604
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.4091188975
Short name T551
Test name
Test status
Simulation time 9003706215 ps
CPU time 212.75 seconds
Started Mar 24 01:22:58 PM PDT 24
Finished Mar 24 01:26:31 PM PDT 24
Peak memory 210764 kb
Host smart-174c33e2-ca0e-452a-8d8b-f2ca3d807996
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4091188975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.4091188975
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.525436515
Short name T27
Test name
Test status
Simulation time 549998317 ps
CPU time 189.32 seconds
Started Mar 24 01:22:51 PM PDT 24
Finished Mar 24 01:26:01 PM PDT 24
Peak memory 208336 kb
Host smart-b7257743-73b6-4edc-a652-e9a3dc9fb509
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=525436515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand
_reset.525436515
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1380229116
Short name T460
Test name
Test status
Simulation time 599666947 ps
CPU time 105.96 seconds
Started Mar 24 01:22:57 PM PDT 24
Finished Mar 24 01:24:43 PM PDT 24
Peak memory 209664 kb
Host smart-22f9367a-9562-4d57-b874-9a04015eeaad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1380229116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.1380229116
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1343608327
Short name T359
Test name
Test status
Simulation time 686973090 ps
CPU time 22.56 seconds
Started Mar 24 01:22:53 PM PDT 24
Finished Mar 24 01:23:15 PM PDT 24
Peak memory 205412 kb
Host smart-b4214daa-436f-46ef-88aa-2c5506d732ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1343608327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1343608327
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.942588506
Short name T659
Test name
Test status
Simulation time 26762400 ps
CPU time 2.85 seconds
Started Mar 24 01:23:01 PM PDT 24
Finished Mar 24 01:23:04 PM PDT 24
Peak memory 203528 kb
Host smart-0531c48d-6912-4b64-9f04-daedb09353fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=942588506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.942588506
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1632559295
Short name T752
Test name
Test status
Simulation time 39910667 ps
CPU time 4.74 seconds
Started Mar 24 01:23:01 PM PDT 24
Finished Mar 24 01:23:06 PM PDT 24
Peak memory 203600 kb
Host smart-a4ee5d0b-a940-40fc-97e3-8005ea776fc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1632559295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1632559295
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.2827438796
Short name T537
Test name
Test status
Simulation time 1347637434 ps
CPU time 36.91 seconds
Started Mar 24 01:22:58 PM PDT 24
Finished Mar 24 01:23:36 PM PDT 24
Peak memory 203840 kb
Host smart-380ecd04-f884-4944-8f0f-cfe20fb0eb4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2827438796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2827438796
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3005164731
Short name T49
Test name
Test status
Simulation time 101167086 ps
CPU time 2.21 seconds
Started Mar 24 01:22:58 PM PDT 24
Finished Mar 24 01:23:00 PM PDT 24
Peak memory 203480 kb
Host smart-8483f2d6-890e-4d27-b3cd-e0ee2c3e395b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3005164731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3005164731
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1563827909
Short name T814
Test name
Test status
Simulation time 16177800605 ps
CPU time 72.55 seconds
Started Mar 24 01:22:57 PM PDT 24
Finished Mar 24 01:24:10 PM PDT 24
Peak memory 204736 kb
Host smart-c8a59a83-3538-4cbf-b0d1-73f349ba9a32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563827909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1563827909
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3270357018
Short name T110
Test name
Test status
Simulation time 23208014274 ps
CPU time 182.91 seconds
Started Mar 24 01:22:57 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 205492 kb
Host smart-dcceb995-d666-4b92-8cf3-18ca53395513
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3270357018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3270357018
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2995517910
Short name T899
Test name
Test status
Simulation time 176667195 ps
CPU time 7.8 seconds
Started Mar 24 01:23:00 PM PDT 24
Finished Mar 24 01:23:08 PM PDT 24
Peak memory 204616 kb
Host smart-f2da910b-bab5-465f-bbca-d0c40205e3d7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995517910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2995517910
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.290594021
Short name T279
Test name
Test status
Simulation time 389883602 ps
CPU time 18.2 seconds
Started Mar 24 01:22:57 PM PDT 24
Finished Mar 24 01:23:15 PM PDT 24
Peak memory 203416 kb
Host smart-9cd6566e-a7ca-45e3-b8f0-806a926aebb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=290594021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.290594021
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.2494557170
Short name T4
Test name
Test status
Simulation time 128084416 ps
CPU time 4.02 seconds
Started Mar 24 01:22:59 PM PDT 24
Finished Mar 24 01:23:04 PM PDT 24
Peak memory 203480 kb
Host smart-021be2f3-253e-453e-acb1-339ede081438
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2494557170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2494557170
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1748049148
Short name T883
Test name
Test status
Simulation time 4555143697 ps
CPU time 23.3 seconds
Started Mar 24 01:22:58 PM PDT 24
Finished Mar 24 01:23:21 PM PDT 24
Peak memory 203568 kb
Host smart-ec06544a-3a64-4bfc-940a-67b8680e94d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748049148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1748049148
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2745136861
Short name T262
Test name
Test status
Simulation time 5867358273 ps
CPU time 27.23 seconds
Started Mar 24 01:22:55 PM PDT 24
Finished Mar 24 01:23:22 PM PDT 24
Peak memory 203540 kb
Host smart-f6f78121-42bc-480e-8295-99153a09fb71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2745136861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2745136861
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2248280731
Short name T66
Test name
Test status
Simulation time 32612058 ps
CPU time 2.28 seconds
Started Mar 24 01:22:59 PM PDT 24
Finished Mar 24 01:23:02 PM PDT 24
Peak memory 203500 kb
Host smart-59e469ed-3c6a-4bad-89c4-dccf7a80d709
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248280731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2248280731
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.1006156669
Short name T404
Test name
Test status
Simulation time 6867892914 ps
CPU time 228.24 seconds
Started Mar 24 01:22:59 PM PDT 24
Finished Mar 24 01:26:47 PM PDT 24
Peak memory 206388 kb
Host smart-9e76df38-10e2-4b1e-a36c-6fcf8b65a5f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1006156669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1006156669
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.942884921
Short name T454
Test name
Test status
Simulation time 6535620978 ps
CPU time 192.32 seconds
Started Mar 24 01:23:02 PM PDT 24
Finished Mar 24 01:26:14 PM PDT 24
Peak memory 211744 kb
Host smart-3173566e-b035-4582-87bb-892342b1fa39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=942884921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.942884921
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1699133690
Short name T788
Test name
Test status
Simulation time 496600600 ps
CPU time 186.36 seconds
Started Mar 24 01:22:56 PM PDT 24
Finished Mar 24 01:26:03 PM PDT 24
Peak memory 208836 kb
Host smart-4d854f77-e1f1-4f20-9e2a-e815862e4f56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1699133690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1699133690
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1806860919
Short name T39
Test name
Test status
Simulation time 1447399722 ps
CPU time 201.96 seconds
Started Mar 24 01:23:04 PM PDT 24
Finished Mar 24 01:26:26 PM PDT 24
Peak memory 211708 kb
Host smart-ace1f3a1-3efa-4cf5-aeb5-d6b3b85d9dfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1806860919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.1806860919
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2275208519
Short name T790
Test name
Test status
Simulation time 129416648 ps
CPU time 15.45 seconds
Started Mar 24 01:23:01 PM PDT 24
Finished Mar 24 01:23:17 PM PDT 24
Peak memory 204752 kb
Host smart-fe747eda-24b7-42f9-81e6-cf88613e68fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2275208519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2275208519
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1212259584
Short name T296
Test name
Test status
Simulation time 818235350 ps
CPU time 19.26 seconds
Started Mar 24 01:23:04 PM PDT 24
Finished Mar 24 01:23:25 PM PDT 24
Peak memory 204132 kb
Host smart-395799cf-0188-4223-b8e1-5662d821ffcb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1212259584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1212259584
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1772977778
Short name T639
Test name
Test status
Simulation time 44573326068 ps
CPU time 189.2 seconds
Started Mar 24 01:23:03 PM PDT 24
Finished Mar 24 01:26:13 PM PDT 24
Peak memory 206308 kb
Host smart-eddccea3-eed9-49dc-95f8-29518252b6c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1772977778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.1772977778
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2345766457
Short name T684
Test name
Test status
Simulation time 325929030 ps
CPU time 12.95 seconds
Started Mar 24 01:23:04 PM PDT 24
Finished Mar 24 01:23:17 PM PDT 24
Peak memory 203756 kb
Host smart-68f6ccf4-6e98-47fb-a911-8a8406699298
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2345766457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2345766457
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.206115277
Short name T112
Test name
Test status
Simulation time 32605096 ps
CPU time 3.69 seconds
Started Mar 24 01:23:06 PM PDT 24
Finished Mar 24 01:23:10 PM PDT 24
Peak memory 203496 kb
Host smart-58900458-cd2b-4f0e-9c95-51e6e41a8c37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=206115277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.206115277
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.1677286340
Short name T376
Test name
Test status
Simulation time 1877087631 ps
CPU time 19.52 seconds
Started Mar 24 01:23:03 PM PDT 24
Finished Mar 24 01:23:23 PM PDT 24
Peak memory 204712 kb
Host smart-752cb956-4d15-47b4-9d11-aacb58d18a93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1677286340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1677286340
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1216720971
Short name T398
Test name
Test status
Simulation time 14406770841 ps
CPU time 49.13 seconds
Started Mar 24 01:23:04 PM PDT 24
Finished Mar 24 01:23:53 PM PDT 24
Peak memory 204924 kb
Host smart-cc76cdc5-8aba-4666-abd9-28883b5b3c92
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216720971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1216720971
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.806643093
Short name T655
Test name
Test status
Simulation time 15172477693 ps
CPU time 37.16 seconds
Started Mar 24 01:23:02 PM PDT 24
Finished Mar 24 01:23:40 PM PDT 24
Peak memory 211712 kb
Host smart-8efe31a5-df32-48d9-a747-c02ea062cfc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=806643093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.806643093
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1616501098
Short name T621
Test name
Test status
Simulation time 301216066 ps
CPU time 13.52 seconds
Started Mar 24 01:23:07 PM PDT 24
Finished Mar 24 01:23:21 PM PDT 24
Peak memory 211676 kb
Host smart-c6127de3-3c39-46ae-abfd-1b5e7ec30d82
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616501098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1616501098
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.4078508656
Short name T223
Test name
Test status
Simulation time 1508849930 ps
CPU time 31.9 seconds
Started Mar 24 01:23:02 PM PDT 24
Finished Mar 24 01:23:35 PM PDT 24
Peak memory 203548 kb
Host smart-4cf514c1-3fed-4d86-8580-c9d37f84b0a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4078508656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.4078508656
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.2285570823
Short name T256
Test name
Test status
Simulation time 157690733 ps
CPU time 2.86 seconds
Started Mar 24 01:23:02 PM PDT 24
Finished Mar 24 01:23:05 PM PDT 24
Peak memory 203480 kb
Host smart-d61edaa7-259c-499d-a5f4-1db6340de573
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2285570823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2285570823
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4184345082
Short name T374
Test name
Test status
Simulation time 8957482711 ps
CPU time 27.81 seconds
Started Mar 24 01:23:01 PM PDT 24
Finished Mar 24 01:23:29 PM PDT 24
Peak memory 203588 kb
Host smart-5eb0de0a-8fdc-40c1-b69e-5ccc509270d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184345082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4184345082
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.883916032
Short name T156
Test name
Test status
Simulation time 6627166505 ps
CPU time 31.45 seconds
Started Mar 24 01:23:03 PM PDT 24
Finished Mar 24 01:23:35 PM PDT 24
Peak memory 203532 kb
Host smart-d14fc387-1770-406b-aaa2-99128aae009e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=883916032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.883916032
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.4046940940
Short name T450
Test name
Test status
Simulation time 42189378 ps
CPU time 2.47 seconds
Started Mar 24 01:23:02 PM PDT 24
Finished Mar 24 01:23:05 PM PDT 24
Peak memory 203720 kb
Host smart-8f8d6fa1-351b-45f8-bf12-b31bc0a2993a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046940940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.4046940940
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1429019594
Short name T108
Test name
Test status
Simulation time 13545189376 ps
CPU time 258.81 seconds
Started Mar 24 01:23:03 PM PDT 24
Finished Mar 24 01:27:22 PM PDT 24
Peak memory 210368 kb
Host smart-80764452-1988-41a9-8c4e-0e56499b7840
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1429019594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1429019594
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3834375693
Short name T805
Test name
Test status
Simulation time 625692171 ps
CPU time 46.26 seconds
Started Mar 24 01:23:06 PM PDT 24
Finished Mar 24 01:23:53 PM PDT 24
Peak memory 204792 kb
Host smart-8175414c-d583-431d-9c2e-5633e4594f4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3834375693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3834375693
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.682934620
Short name T151
Test name
Test status
Simulation time 7421408103 ps
CPU time 270.3 seconds
Started Mar 24 01:23:06 PM PDT 24
Finished Mar 24 01:27:37 PM PDT 24
Peak memory 210308 kb
Host smart-8ab3028e-259b-4797-8b47-c9a439d55be9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=682934620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand
_reset.682934620
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2570822213
Short name T21
Test name
Test status
Simulation time 197847644 ps
CPU time 20.65 seconds
Started Mar 24 01:23:06 PM PDT 24
Finished Mar 24 01:23:27 PM PDT 24
Peak memory 204128 kb
Host smart-1dbd2c28-5e59-4bea-abd9-b673ccd0fc76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2570822213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.2570822213
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1860482341
Short name T779
Test name
Test status
Simulation time 571351388 ps
CPU time 22.42 seconds
Started Mar 24 01:23:04 PM PDT 24
Finished Mar 24 01:23:27 PM PDT 24
Peak memory 205112 kb
Host smart-5a800427-bb2a-44d0-b931-695a42e349f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1860482341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1860482341
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1897750549
Short name T115
Test name
Test status
Simulation time 383731175 ps
CPU time 39.5 seconds
Started Mar 24 01:23:08 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 206012 kb
Host smart-bb8349c6-b100-4ad4-9aa2-2dab43d767e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1897750549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1897750549
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.209871189
Short name T130
Test name
Test status
Simulation time 27654140831 ps
CPU time 98.07 seconds
Started Mar 24 01:23:16 PM PDT 24
Finished Mar 24 01:24:54 PM PDT 24
Peak memory 211760 kb
Host smart-8001ff7f-b58f-4634-b1b5-50b3a75572bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=209871189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo
w_rsp.209871189
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4117372471
Short name T448
Test name
Test status
Simulation time 164460050 ps
CPU time 10.98 seconds
Started Mar 24 01:23:14 PM PDT 24
Finished Mar 24 01:23:25 PM PDT 24
Peak memory 203736 kb
Host smart-3fed1532-b688-4ade-860c-3079ecfee97e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4117372471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4117372471
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.460768992
Short name T322
Test name
Test status
Simulation time 1255808292 ps
CPU time 27.19 seconds
Started Mar 24 01:23:15 PM PDT 24
Finished Mar 24 01:23:42 PM PDT 24
Peak memory 203560 kb
Host smart-c9524962-8950-4824-9386-91d2e7d1d9bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=460768992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.460768992
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.3375217167
Short name T670
Test name
Test status
Simulation time 212665412 ps
CPU time 6.54 seconds
Started Mar 24 01:23:07 PM PDT 24
Finished Mar 24 01:23:14 PM PDT 24
Peak memory 211640 kb
Host smart-87312c3f-c7c9-4322-a6b1-6196fe523bd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3375217167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3375217167
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1658207255
Short name T886
Test name
Test status
Simulation time 106722868507 ps
CPU time 207.93 seconds
Started Mar 24 01:23:09 PM PDT 24
Finished Mar 24 01:26:37 PM PDT 24
Peak memory 205236 kb
Host smart-784b706e-2a38-49df-89fb-4a86a5eb33e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658207255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1658207255
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2086980864
Short name T59
Test name
Test status
Simulation time 7899737728 ps
CPU time 75.66 seconds
Started Mar 24 01:23:06 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 204708 kb
Host smart-852089a8-95c5-4816-8ac3-69b716361eeb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2086980864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2086980864
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3624809258
Short name T683
Test name
Test status
Simulation time 36848154 ps
CPU time 4.04 seconds
Started Mar 24 01:23:07 PM PDT 24
Finished Mar 24 01:23:11 PM PDT 24
Peak memory 204108 kb
Host smart-4a0fdb1e-bcfa-48f9-a0ba-c6a406ea3d1f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624809258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3624809258
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.1074210203
Short name T297
Test name
Test status
Simulation time 167517657 ps
CPU time 12.91 seconds
Started Mar 24 01:23:15 PM PDT 24
Finished Mar 24 01:23:28 PM PDT 24
Peak memory 203528 kb
Host smart-1f55123b-f35e-477f-9c9f-f98719e59f6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1074210203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1074210203
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.1448119337
Short name T829
Test name
Test status
Simulation time 132960263 ps
CPU time 3.26 seconds
Started Mar 24 01:23:05 PM PDT 24
Finished Mar 24 01:23:09 PM PDT 24
Peak memory 203468 kb
Host smart-07de482f-f203-4c9a-9ccf-27ce7063ef7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1448119337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1448119337
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3545926628
Short name T379
Test name
Test status
Simulation time 13143364510 ps
CPU time 31.59 seconds
Started Mar 24 01:23:06 PM PDT 24
Finished Mar 24 01:23:38 PM PDT 24
Peak memory 203576 kb
Host smart-9c39a042-1275-4831-b41f-c4933a314260
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545926628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3545926628
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3666248324
Short name T889
Test name
Test status
Simulation time 5959741871 ps
CPU time 28.29 seconds
Started Mar 24 01:23:09 PM PDT 24
Finished Mar 24 01:23:37 PM PDT 24
Peak memory 203544 kb
Host smart-d4777468-c88c-4513-8cba-c778855e6751
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3666248324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3666248324
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1296578339
Short name T691
Test name
Test status
Simulation time 50634240 ps
CPU time 2.73 seconds
Started Mar 24 01:23:12 PM PDT 24
Finished Mar 24 01:23:16 PM PDT 24
Peak memory 203728 kb
Host smart-d31293c2-58cc-45fa-9442-2a8853580876
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296578339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1296578339
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.923350496
Short name T109
Test name
Test status
Simulation time 3471830532 ps
CPU time 94.74 seconds
Started Mar 24 01:23:13 PM PDT 24
Finished Mar 24 01:24:48 PM PDT 24
Peak memory 205796 kb
Host smart-9c50e80d-23dc-4a26-baa7-be29d22a3068
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=923350496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.923350496
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3731974605
Short name T327
Test name
Test status
Simulation time 5565656130 ps
CPU time 221.38 seconds
Started Mar 24 01:23:15 PM PDT 24
Finished Mar 24 01:26:56 PM PDT 24
Peak memory 209064 kb
Host smart-aa0d62e2-0202-45d0-8d6e-3c13d52e9b6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3731974605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3731974605
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1938788304
Short name T665
Test name
Test status
Simulation time 6764814547 ps
CPU time 382.81 seconds
Started Mar 24 01:23:16 PM PDT 24
Finished Mar 24 01:29:39 PM PDT 24
Peak memory 208852 kb
Host smart-5964be1d-7c28-4d6f-94c4-a6b0283402ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1938788304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.1938788304
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1243343677
Short name T23
Test name
Test status
Simulation time 239546994 ps
CPU time 67.05 seconds
Started Mar 24 01:23:14 PM PDT 24
Finished Mar 24 01:24:21 PM PDT 24
Peak memory 207948 kb
Host smart-e1fbe9b6-9fc6-4291-a645-de7ac7774ba5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1243343677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.1243343677
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2779226980
Short name T20
Test name
Test status
Simulation time 26674431 ps
CPU time 1.91 seconds
Started Mar 24 01:23:16 PM PDT 24
Finished Mar 24 01:23:18 PM PDT 24
Peak memory 203484 kb
Host smart-445cd545-18b4-48aa-a50a-a976fb04e0e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2779226980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2779226980
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.552711218
Short name T442
Test name
Test status
Simulation time 4234895285 ps
CPU time 50.99 seconds
Started Mar 24 01:23:18 PM PDT 24
Finished Mar 24 01:24:09 PM PDT 24
Peak memory 211744 kb
Host smart-37828ad4-7af4-4686-a152-32c1c3d1151d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=552711218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.552711218
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.4095702229
Short name T207
Test name
Test status
Simulation time 43352954075 ps
CPU time 297.4 seconds
Started Mar 24 01:23:15 PM PDT 24
Finished Mar 24 01:28:12 PM PDT 24
Peak memory 206564 kb
Host smart-cffa6d32-c64d-426c-8d54-6afc9e97c488
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4095702229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.4095702229
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.401295301
Short name T344
Test name
Test status
Simulation time 129223820 ps
CPU time 20.83 seconds
Started Mar 24 01:23:18 PM PDT 24
Finished Mar 24 01:23:39 PM PDT 24
Peak memory 203480 kb
Host smart-e7fdc15b-11a4-4b8c-8289-d704cfd14abb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=401295301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.401295301
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.3224372186
Short name T753
Test name
Test status
Simulation time 121432063 ps
CPU time 14.6 seconds
Started Mar 24 01:23:18 PM PDT 24
Finished Mar 24 01:23:33 PM PDT 24
Peak memory 203512 kb
Host smart-4b870aff-3fa0-4965-a39e-f0a5194bff9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3224372186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3224372186
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.2830878974
Short name T169
Test name
Test status
Simulation time 1714202071 ps
CPU time 31.47 seconds
Started Mar 24 01:23:17 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 211696 kb
Host smart-344368fb-374d-4db6-8cc4-9595fd38823c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2830878974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2830878974
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2729963858
Short name T627
Test name
Test status
Simulation time 78038482894 ps
CPU time 155.02 seconds
Started Mar 24 01:23:13 PM PDT 24
Finished Mar 24 01:25:48 PM PDT 24
Peak memory 204828 kb
Host smart-cc4afc68-2fea-4a3c-9416-6777b374cb54
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729963858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2729963858
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3428732342
Short name T265
Test name
Test status
Simulation time 32679774621 ps
CPU time 180.41 seconds
Started Mar 24 01:23:15 PM PDT 24
Finished Mar 24 01:26:16 PM PDT 24
Peak memory 211728 kb
Host smart-b05ea309-eed3-4fad-a1ab-11eb9684e1af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3428732342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3428732342
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.887968282
Short name T484
Test name
Test status
Simulation time 175310548 ps
CPU time 20.76 seconds
Started Mar 24 01:23:13 PM PDT 24
Finished Mar 24 01:23:34 PM PDT 24
Peak memory 204620 kb
Host smart-86d0324c-5266-4778-97ea-91d4a45696a0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887968282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.887968282
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1382957511
Short name T562
Test name
Test status
Simulation time 495637160 ps
CPU time 10.17 seconds
Started Mar 24 01:23:17 PM PDT 24
Finished Mar 24 01:23:27 PM PDT 24
Peak memory 203960 kb
Host smart-1078e488-f514-401e-a1e7-20e8c617b44e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1382957511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1382957511
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.3347452212
Short name T353
Test name
Test status
Simulation time 290354759 ps
CPU time 3.38 seconds
Started Mar 24 01:23:13 PM PDT 24
Finished Mar 24 01:23:16 PM PDT 24
Peak memory 203480 kb
Host smart-bc897f25-3cff-4086-bed9-2cadcb183621
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3347452212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3347452212
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3094148235
Short name T363
Test name
Test status
Simulation time 5073107601 ps
CPU time 26.43 seconds
Started Mar 24 01:23:15 PM PDT 24
Finished Mar 24 01:23:42 PM PDT 24
Peak memory 203520 kb
Host smart-8064d7e3-c7d7-41eb-8df8-b53704fa0ce6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094148235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3094148235
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1411187515
Short name T412
Test name
Test status
Simulation time 9536768949 ps
CPU time 33.4 seconds
Started Mar 24 01:23:15 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 203796 kb
Host smart-f678d995-307f-462f-8820-72c126039a0e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1411187515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1411187515
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1402779523
Short name T520
Test name
Test status
Simulation time 46953042 ps
CPU time 2.26 seconds
Started Mar 24 01:23:18 PM PDT 24
Finished Mar 24 01:23:20 PM PDT 24
Peak memory 203488 kb
Host smart-67639b88-0c02-4237-bf67-549c2e3463ca
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402779523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1402779523
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2975462026
Short name T268
Test name
Test status
Simulation time 4423881067 ps
CPU time 123.54 seconds
Started Mar 24 01:23:19 PM PDT 24
Finished Mar 24 01:25:23 PM PDT 24
Peak memory 208844 kb
Host smart-112edd86-81d2-44c9-b5bd-24c05e9b7448
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2975462026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2975462026
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1371489155
Short name T101
Test name
Test status
Simulation time 5809337782 ps
CPU time 140.9 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:25:44 PM PDT 24
Peak memory 207932 kb
Host smart-95497a41-0456-42b3-b699-34ac295451ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1371489155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1371489155
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.939605791
Short name T40
Test name
Test status
Simulation time 539181519 ps
CPU time 214.2 seconds
Started Mar 24 01:23:19 PM PDT 24
Finished Mar 24 01:26:53 PM PDT 24
Peak memory 208344 kb
Host smart-cb69054f-2472-42e7-8654-98ec7b65cae4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=939605791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand
_reset.939605791
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.778270368
Short name T703
Test name
Test status
Simulation time 445898166 ps
CPU time 123.97 seconds
Started Mar 24 01:23:21 PM PDT 24
Finished Mar 24 01:25:25 PM PDT 24
Peak memory 209664 kb
Host smart-579d4343-7d52-4bc5-9a13-af042caa2e10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=778270368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res
et_error.778270368
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3976925672
Short name T390
Test name
Test status
Simulation time 205590175 ps
CPU time 7.24 seconds
Started Mar 24 01:23:20 PM PDT 24
Finished Mar 24 01:23:27 PM PDT 24
Peak memory 204848 kb
Host smart-0b824e73-3bf5-4e9a-a20b-9389812f9bc1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3976925672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3976925672
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2553398056
Short name T531
Test name
Test status
Simulation time 1579603819 ps
CPU time 43.84 seconds
Started Mar 24 01:20:26 PM PDT 24
Finished Mar 24 01:21:10 PM PDT 24
Peak memory 205604 kb
Host smart-41443d7e-fb09-4b4d-9e8d-aef49588ec4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2553398056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2553398056
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2972705763
Short name T739
Test name
Test status
Simulation time 128669887888 ps
CPU time 428.36 seconds
Started Mar 24 01:20:33 PM PDT 24
Finished Mar 24 01:27:41 PM PDT 24
Peak memory 211768 kb
Host smart-6b9b8252-1b03-49bf-8e5c-03759c7e49dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2972705763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.2972705763
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.539173616
Short name T451
Test name
Test status
Simulation time 1392170713 ps
CPU time 26.44 seconds
Started Mar 24 01:20:28 PM PDT 24
Finished Mar 24 01:20:55 PM PDT 24
Peak memory 203740 kb
Host smart-ad4417eb-9f95-4e4a-af35-e86473a023f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=539173616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.539173616
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.1446940010
Short name T507
Test name
Test status
Simulation time 247376447 ps
CPU time 17.95 seconds
Started Mar 24 01:20:30 PM PDT 24
Finished Mar 24 01:20:48 PM PDT 24
Peak memory 203592 kb
Host smart-99c351a3-b581-45bc-9e86-0bb656102e11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1446940010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1446940010
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.617435114
Short name T477
Test name
Test status
Simulation time 94523164 ps
CPU time 8.46 seconds
Started Mar 24 01:20:25 PM PDT 24
Finished Mar 24 01:20:34 PM PDT 24
Peak memory 204568 kb
Host smart-aaecb77d-61f6-4ecb-a9f2-dc13f06c7f38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=617435114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.617435114
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1166162622
Short name T260
Test name
Test status
Simulation time 40895360192 ps
CPU time 202.49 seconds
Started Mar 24 01:20:26 PM PDT 24
Finished Mar 24 01:23:49 PM PDT 24
Peak memory 205388 kb
Host smart-a44f6b46-30b1-4a7f-a615-744ee58d30d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166162622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1166162622
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3171269410
Short name T64
Test name
Test status
Simulation time 52649938242 ps
CPU time 148.2 seconds
Started Mar 24 01:20:24 PM PDT 24
Finished Mar 24 01:22:53 PM PDT 24
Peak memory 205092 kb
Host smart-20e79f07-5b34-419b-9be0-52f75b2117b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3171269410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3171269410
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3495529789
Short name T693
Test name
Test status
Simulation time 711150164 ps
CPU time 25.73 seconds
Started Mar 24 01:20:27 PM PDT 24
Finished Mar 24 01:20:53 PM PDT 24
Peak memory 204868 kb
Host smart-145be7db-989b-474b-965f-818b07bd6e74
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495529789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3495529789
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3744664681
Short name T787
Test name
Test status
Simulation time 118101369 ps
CPU time 2.87 seconds
Started Mar 24 01:20:29 PM PDT 24
Finished Mar 24 01:20:32 PM PDT 24
Peak memory 203544 kb
Host smart-c1b988a4-2982-4ad1-83c9-2b20c7bb67ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3744664681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3744664681
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.3427357420
Short name T797
Test name
Test status
Simulation time 24394650 ps
CPU time 2.04 seconds
Started Mar 24 01:20:23 PM PDT 24
Finished Mar 24 01:20:25 PM PDT 24
Peak memory 203484 kb
Host smart-811779db-581d-4c21-8516-d7068f521b30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3427357420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3427357420
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1004286289
Short name T568
Test name
Test status
Simulation time 9408689487 ps
CPU time 25.05 seconds
Started Mar 24 01:20:24 PM PDT 24
Finished Mar 24 01:20:50 PM PDT 24
Peak memory 203536 kb
Host smart-d4ed73c4-28b7-49dd-ba7f-c594bc3f6c9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004286289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1004286289
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1082049708
Short name T631
Test name
Test status
Simulation time 14679965140 ps
CPU time 47.03 seconds
Started Mar 24 01:20:26 PM PDT 24
Finished Mar 24 01:21:13 PM PDT 24
Peak memory 203524 kb
Host smart-eaec6468-d9a7-4291-b478-5cd2947f4aff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1082049708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1082049708
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1809516967
Short name T816
Test name
Test status
Simulation time 56522543 ps
CPU time 2.62 seconds
Started Mar 24 01:20:27 PM PDT 24
Finished Mar 24 01:20:30 PM PDT 24
Peak memory 203504 kb
Host smart-d7b424a9-d6bf-4e5a-95b6-9f498e6d97c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809516967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1809516967
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3089406050
Short name T731
Test name
Test status
Simulation time 9093409119 ps
CPU time 83.08 seconds
Started Mar 24 01:20:30 PM PDT 24
Finished Mar 24 01:21:53 PM PDT 24
Peak memory 208528 kb
Host smart-5e02a667-187c-4827-9e2b-25a9488a7632
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3089406050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3089406050
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1772091967
Short name T349
Test name
Test status
Simulation time 488989401 ps
CPU time 23.92 seconds
Started Mar 24 01:20:31 PM PDT 24
Finished Mar 24 01:20:55 PM PDT 24
Peak memory 204560 kb
Host smart-4c87dc3d-687d-4063-acfb-e6dded3a4026
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1772091967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1772091967
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1655594286
Short name T570
Test name
Test status
Simulation time 2178888326 ps
CPU time 399.42 seconds
Started Mar 24 01:20:29 PM PDT 24
Finished Mar 24 01:27:09 PM PDT 24
Peak memory 209104 kb
Host smart-05975dae-d5ca-485d-8bf3-5f80ede8d8d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1655594286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.1655594286
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.109782208
Short name T310
Test name
Test status
Simulation time 6305503267 ps
CPU time 109.79 seconds
Started Mar 24 01:20:30 PM PDT 24
Finished Mar 24 01:22:20 PM PDT 24
Peak memory 208640 kb
Host smart-f26a2bdc-3705-4234-a911-895d58fe4420
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109782208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese
t_error.109782208
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.543541400
Short name T367
Test name
Test status
Simulation time 21240771 ps
CPU time 1.86 seconds
Started Mar 24 01:20:30 PM PDT 24
Finished Mar 24 01:20:32 PM PDT 24
Peak memory 203484 kb
Host smart-af8b3f1e-11d6-4908-ade6-cc997ca7ea1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=543541400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.543541400
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.4149057229
Short name T792
Test name
Test status
Simulation time 1242671543 ps
CPU time 33.9 seconds
Started Mar 24 01:23:19 PM PDT 24
Finished Mar 24 01:23:53 PM PDT 24
Peak memory 204296 kb
Host smart-70fca8c4-ea31-42a7-a259-8ef5c55365e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4149057229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.4149057229
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.491398315
Short name T119
Test name
Test status
Simulation time 33617918332 ps
CPU time 191.84 seconds
Started Mar 24 01:23:19 PM PDT 24
Finished Mar 24 01:26:31 PM PDT 24
Peak memory 206048 kb
Host smart-51fef054-182f-42d2-ad25-15ee4b4842df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=491398315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo
w_rsp.491398315
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3584912667
Short name T18
Test name
Test status
Simulation time 71477084 ps
CPU time 10.13 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:23:34 PM PDT 24
Peak memory 203684 kb
Host smart-7a338c39-4661-483a-93bc-7b04a03f8166
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3584912667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3584912667
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.1017798713
Short name T682
Test name
Test status
Simulation time 1335247296 ps
CPU time 35.07 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:23:58 PM PDT 24
Peak memory 203572 kb
Host smart-e226d3f1-f4af-4061-98e2-d6148d14a19f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1017798713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1017798713
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.636143031
Short name T71
Test name
Test status
Simulation time 1190173528 ps
CPU time 22.02 seconds
Started Mar 24 01:23:17 PM PDT 24
Finished Mar 24 01:23:40 PM PDT 24
Peak memory 204600 kb
Host smart-686d050b-829b-48f0-94a2-03a940ab8916
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=636143031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.636143031
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2403904194
Short name T590
Test name
Test status
Simulation time 1831298751 ps
CPU time 14.12 seconds
Started Mar 24 01:23:19 PM PDT 24
Finished Mar 24 01:23:34 PM PDT 24
Peak memory 203452 kb
Host smart-f851f09d-ff7d-4dc7-8d68-4658fc1e3214
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2403904194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2403904194
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3798247423
Short name T750
Test name
Test status
Simulation time 96117284 ps
CPU time 14.67 seconds
Started Mar 24 01:23:21 PM PDT 24
Finished Mar 24 01:23:36 PM PDT 24
Peak memory 204580 kb
Host smart-6b72f36c-2101-4d52-8d68-e8e03eae0736
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798247423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3798247423
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.852903630
Short name T75
Test name
Test status
Simulation time 960780784 ps
CPU time 23.56 seconds
Started Mar 24 01:23:19 PM PDT 24
Finished Mar 24 01:23:43 PM PDT 24
Peak memory 204028 kb
Host smart-b8f89b75-57c2-48a6-b148-0ad05e6431b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=852903630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.852903630
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.2609383603
Short name T229
Test name
Test status
Simulation time 186010112 ps
CPU time 3.98 seconds
Started Mar 24 01:23:18 PM PDT 24
Finished Mar 24 01:23:22 PM PDT 24
Peak memory 203464 kb
Host smart-9433a786-1e0d-4fea-806b-839870a02bae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2609383603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2609383603
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1731430090
Short name T246
Test name
Test status
Simulation time 5768037080 ps
CPU time 31.7 seconds
Started Mar 24 01:23:19 PM PDT 24
Finished Mar 24 01:23:51 PM PDT 24
Peak memory 203508 kb
Host smart-3c27bd03-1dac-47a9-b67e-d65c564cb919
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731430090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1731430090
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2573769422
Short name T476
Test name
Test status
Simulation time 7542945926 ps
CPU time 39.49 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:24:03 PM PDT 24
Peak memory 203552 kb
Host smart-190f67f3-36a2-40d6-9475-0f9447d37e3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2573769422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2573769422
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3458042472
Short name T295
Test name
Test status
Simulation time 32477772 ps
CPU time 2.06 seconds
Started Mar 24 01:23:18 PM PDT 24
Finished Mar 24 01:23:21 PM PDT 24
Peak memory 203468 kb
Host smart-3155963e-e895-45d8-a13a-fdca1f640b4a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458042472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3458042472
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2924435886
Short name T219
Test name
Test status
Simulation time 492895983 ps
CPU time 61.39 seconds
Started Mar 24 01:23:24 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 206204 kb
Host smart-1c92f86a-3bfe-49b5-85bc-20f391c2284d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2924435886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2924435886
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1900151594
Short name T608
Test name
Test status
Simulation time 2326631183 ps
CPU time 141.97 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:25:49 PM PDT 24
Peak memory 208492 kb
Host smart-ae791bc1-23c1-4318-91b6-05f2f5ef3056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1900151594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1900151594
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.668244694
Short name T515
Test name
Test status
Simulation time 9591379558 ps
CPU time 250.53 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:27:34 PM PDT 24
Peak memory 220184 kb
Host smart-a18727b4-97c3-4cbf-b339-ee7a219cd227
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=668244694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res
et_error.668244694
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1272443816
Short name T170
Test name
Test status
Simulation time 555778684 ps
CPU time 14 seconds
Started Mar 24 01:23:21 PM PDT 24
Finished Mar 24 01:23:36 PM PDT 24
Peak memory 204940 kb
Host smart-bc932578-9124-4be6-b23e-97655bab275e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1272443816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1272443816
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.204880651
Short name T142
Test name
Test status
Simulation time 121650858 ps
CPU time 12.91 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:23:40 PM PDT 24
Peak memory 211572 kb
Host smart-6f640be5-7d0d-491b-b205-c9bd5c9d2a22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=204880651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.204880651
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1983771392
Short name T536
Test name
Test status
Simulation time 28157228270 ps
CPU time 155.2 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:26:02 PM PDT 24
Peak memory 206200 kb
Host smart-ead7b893-dc84-4c12-8f26-f79272d38d07
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1983771392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.1983771392
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1410987254
Short name T845
Test name
Test status
Simulation time 67680174 ps
CPU time 4.93 seconds
Started Mar 24 01:23:22 PM PDT 24
Finished Mar 24 01:23:27 PM PDT 24
Peak memory 203620 kb
Host smart-f81c54ab-a50e-48b4-966a-f99031aeec7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1410987254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1410987254
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.1771609612
Short name T672
Test name
Test status
Simulation time 128783762 ps
CPU time 4.09 seconds
Started Mar 24 01:23:24 PM PDT 24
Finished Mar 24 01:23:28 PM PDT 24
Peak memory 203512 kb
Host smart-2ee41e84-052e-4f61-91d3-2800315e0d6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1771609612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1771609612
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.2440743735
Short name T674
Test name
Test status
Simulation time 96463713 ps
CPU time 4.49 seconds
Started Mar 24 01:23:26 PM PDT 24
Finished Mar 24 01:23:30 PM PDT 24
Peak memory 202932 kb
Host smart-e498348a-9bda-4082-a6dd-5bbeede2603a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2440743735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2440743735
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.207248501
Short name T756
Test name
Test status
Simulation time 46314491940 ps
CPU time 229.25 seconds
Started Mar 24 01:23:26 PM PDT 24
Finished Mar 24 01:27:15 PM PDT 24
Peak memory 210620 kb
Host smart-af6f3d53-66cb-4e3e-b8e5-c9e694fbebdb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=207248501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.207248501
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3723270886
Short name T225
Test name
Test status
Simulation time 91661310096 ps
CPU time 246.86 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:27:34 PM PDT 24
Peak memory 205032 kb
Host smart-c8ae0762-88d2-4368-a44c-cd6a7b21b5d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3723270886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3723270886
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.326303763
Short name T555
Test name
Test status
Simulation time 462399956 ps
CPU time 24.34 seconds
Started Mar 24 01:23:24 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 204640 kb
Host smart-70b9c2a8-bda6-41cb-acb2-aad44d602ca6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326303763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.326303763
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.1680151071
Short name T605
Test name
Test status
Simulation time 90939456 ps
CPU time 4.85 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:23:32 PM PDT 24
Peak memory 203912 kb
Host smart-06c74d3d-48b5-4c68-b600-3d46a31226e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1680151071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1680151071
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.3004494836
Short name T871
Test name
Test status
Simulation time 196633927 ps
CPU time 3.59 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:23:31 PM PDT 24
Peak memory 203488 kb
Host smart-f626cfa2-4358-4933-ac92-cc09a1de099a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3004494836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3004494836
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.695460282
Short name T857
Test name
Test status
Simulation time 4780645806 ps
CPU time 25.51 seconds
Started Mar 24 01:23:22 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 203600 kb
Host smart-3282036c-553b-42ec-9a2f-f74e33726b8c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=695460282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.695460282
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1396211278
Short name T63
Test name
Test status
Simulation time 3786971739 ps
CPU time 32.85 seconds
Started Mar 24 01:23:25 PM PDT 24
Finished Mar 24 01:23:58 PM PDT 24
Peak memory 203572 kb
Host smart-fec38f2f-f008-462e-bf4d-f60d33fb1fc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1396211278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1396211278
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2756895791
Short name T481
Test name
Test status
Simulation time 38600368 ps
CPU time 2.4 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:23:25 PM PDT 24
Peak memory 203496 kb
Host smart-1a1502c4-4014-40df-a27b-84cd2d6115b5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756895791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2756895791
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3417525876
Short name T480
Test name
Test status
Simulation time 3757207155 ps
CPU time 144.45 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:25:48 PM PDT 24
Peak memory 208064 kb
Host smart-d45a7ac1-f17a-42b6-908b-24bc9e0b1f4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3417525876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3417525876
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2192585314
Short name T802
Test name
Test status
Simulation time 6249865530 ps
CPU time 179.93 seconds
Started Mar 24 01:23:23 PM PDT 24
Finished Mar 24 01:26:23 PM PDT 24
Peak memory 209344 kb
Host smart-8600faf4-02af-4b17-9330-6bade93565fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2192585314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2192585314
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4219979944
Short name T194
Test name
Test status
Simulation time 1132620724 ps
CPU time 296.44 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:28:23 PM PDT 24
Peak memory 211784 kb
Host smart-adb5bf92-6d85-4b4c-b9ce-ec603faacebd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4219979944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.4219979944
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4023847727
Short name T307
Test name
Test status
Simulation time 261077607 ps
CPU time 88.46 seconds
Started Mar 24 01:23:29 PM PDT 24
Finished Mar 24 01:24:57 PM PDT 24
Peak memory 209296 kb
Host smart-6dd09975-5bc1-4b5f-82db-c45dcc870f13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4023847727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.4023847727
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.138826450
Short name T358
Test name
Test status
Simulation time 170609706 ps
CPU time 16.62 seconds
Started Mar 24 01:23:25 PM PDT 24
Finished Mar 24 01:23:42 PM PDT 24
Peak memory 205084 kb
Host smart-57a75780-b37d-4744-b607-c84afd4334de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=138826450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.138826450
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2057074201
Short name T402
Test name
Test status
Simulation time 413268797 ps
CPU time 40.08 seconds
Started Mar 24 01:23:28 PM PDT 24
Finished Mar 24 01:24:08 PM PDT 24
Peak memory 205648 kb
Host smart-2d597603-fcb6-42f8-bada-a8fbfe647349
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2057074201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2057074201
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1964966142
Short name T836
Test name
Test status
Simulation time 25200504177 ps
CPU time 214.5 seconds
Started Mar 24 01:23:27 PM PDT 24
Finished Mar 24 01:27:02 PM PDT 24
Peak memory 206396 kb
Host smart-e1b6ebc4-9cc4-422c-b396-1f6076444bad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1964966142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1964966142
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3002715777
Short name T803
Test name
Test status
Simulation time 122362648 ps
CPU time 13.14 seconds
Started Mar 24 01:23:34 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 204164 kb
Host smart-f13b18e7-063d-40a4-bc23-b3fb201bc0c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3002715777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3002715777
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.2015927745
Short name T336
Test name
Test status
Simulation time 407269340 ps
CPU time 21.11 seconds
Started Mar 24 01:23:29 PM PDT 24
Finished Mar 24 01:23:51 PM PDT 24
Peak memory 203508 kb
Host smart-1615a222-aca3-45a5-9d05-d2f8334fccba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2015927745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2015927745
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.3776196992
Short name T188
Test name
Test status
Simulation time 167126349 ps
CPU time 6.88 seconds
Started Mar 24 01:23:31 PM PDT 24
Finished Mar 24 01:23:38 PM PDT 24
Peak memory 204608 kb
Host smart-b4cdabb6-93a7-47e4-bb77-a182dc5807e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3776196992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3776196992
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2551750339
Short name T828
Test name
Test status
Simulation time 128950908897 ps
CPU time 165.85 seconds
Started Mar 24 01:23:28 PM PDT 24
Finished Mar 24 01:26:14 PM PDT 24
Peak memory 205196 kb
Host smart-90d1fee7-f7bd-4020-9281-9e1a66956ab7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551750339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2551750339
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3049660197
Short name T342
Test name
Test status
Simulation time 22148016003 ps
CPU time 161.52 seconds
Started Mar 24 01:23:28 PM PDT 24
Finished Mar 24 01:26:10 PM PDT 24
Peak memory 211752 kb
Host smart-89b7c88f-628d-447f-8dd3-870fe74644ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3049660197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3049660197
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3452688249
Short name T897
Test name
Test status
Simulation time 31299692 ps
CPU time 2.37 seconds
Started Mar 24 01:23:30 PM PDT 24
Finished Mar 24 01:23:33 PM PDT 24
Peak memory 203468 kb
Host smart-efbb2a9c-62a4-48ef-b03d-26115a373d98
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452688249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3452688249
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.4038666365
Short name T526
Test name
Test status
Simulation time 2741306641 ps
CPU time 9.61 seconds
Started Mar 24 01:23:28 PM PDT 24
Finished Mar 24 01:23:38 PM PDT 24
Peak memory 203976 kb
Host smart-b4d084e5-8d94-4b06-9853-0a16b33a322e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4038666365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4038666365
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.1559957008
Short name T705
Test name
Test status
Simulation time 124604824 ps
CPU time 3.21 seconds
Started Mar 24 01:23:31 PM PDT 24
Finished Mar 24 01:23:34 PM PDT 24
Peak memory 203452 kb
Host smart-dbc998e0-ab0e-46be-b21f-ffdce68e7876
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1559957008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1559957008
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.800764041
Short name T270
Test name
Test status
Simulation time 4874515805 ps
CPU time 27.69 seconds
Started Mar 24 01:23:28 PM PDT 24
Finished Mar 24 01:23:55 PM PDT 24
Peak memory 203576 kb
Host smart-194e7698-6a56-4043-b500-f4814e7b91f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=800764041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.800764041
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.952914793
Short name T767
Test name
Test status
Simulation time 23842651026 ps
CPU time 45.2 seconds
Started Mar 24 01:23:28 PM PDT 24
Finished Mar 24 01:24:13 PM PDT 24
Peak memory 203564 kb
Host smart-672ce424-a3f8-4e9e-9ac7-b535549bfac7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=952914793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.952914793
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1324068088
Short name T498
Test name
Test status
Simulation time 47743884 ps
CPU time 1.92 seconds
Started Mar 24 01:23:29 PM PDT 24
Finished Mar 24 01:23:31 PM PDT 24
Peak memory 203472 kb
Host smart-ba47e1b4-0a06-4d8d-b2f1-a5648880e906
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324068088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1324068088
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.4226834242
Short name T441
Test name
Test status
Simulation time 290418249 ps
CPU time 30.59 seconds
Started Mar 24 01:23:32 PM PDT 24
Finished Mar 24 01:24:03 PM PDT 24
Peak memory 211628 kb
Host smart-4c2b591b-d99b-48af-8e80-e390fb6fa64b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4226834242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.4226834242
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3321387819
Short name T233
Test name
Test status
Simulation time 668305163 ps
CPU time 67.71 seconds
Started Mar 24 01:23:32 PM PDT 24
Finished Mar 24 01:24:40 PM PDT 24
Peak memory 204888 kb
Host smart-14560ba2-bbea-4e39-a1f6-273de54140e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3321387819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3321387819
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1085746836
Short name T597
Test name
Test status
Simulation time 2477843412 ps
CPU time 240.36 seconds
Started Mar 24 01:23:33 PM PDT 24
Finished Mar 24 01:27:34 PM PDT 24
Peak memory 208768 kb
Host smart-2e51cc97-fdd9-44bc-863c-7571b2dc393b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1085746836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.1085746836
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2715058781
Short name T838
Test name
Test status
Simulation time 7692277 ps
CPU time 3.51 seconds
Started Mar 24 01:23:35 PM PDT 24
Finished Mar 24 01:23:39 PM PDT 24
Peak memory 203412 kb
Host smart-88350a0d-31fc-4364-bf7d-48dc1bc3377e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2715058781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.2715058781
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3650300278
Short name T354
Test name
Test status
Simulation time 5192407957 ps
CPU time 35.6 seconds
Started Mar 24 01:23:28 PM PDT 24
Finished Mar 24 01:24:04 PM PDT 24
Peak memory 211748 kb
Host smart-26373bf2-28be-4828-9230-21d0b03ef71c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3650300278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3650300278
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3437071975
Short name T288
Test name
Test status
Simulation time 201697510 ps
CPU time 5.65 seconds
Started Mar 24 01:23:34 PM PDT 24
Finished Mar 24 01:23:40 PM PDT 24
Peak memory 203496 kb
Host smart-bf0892ad-3b09-49fb-8c62-957a65cb1a7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437071975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3437071975
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3924962229
Short name T686
Test name
Test status
Simulation time 38069108379 ps
CPU time 302.92 seconds
Started Mar 24 01:23:31 PM PDT 24
Finished Mar 24 01:28:34 PM PDT 24
Peak memory 206004 kb
Host smart-f6a5114e-7f70-4d3b-b3b1-e43e8af1e78b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3924962229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.3924962229
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.88050437
Short name T611
Test name
Test status
Simulation time 178604776 ps
CPU time 5.95 seconds
Started Mar 24 01:23:40 PM PDT 24
Finished Mar 24 01:23:46 PM PDT 24
Peak memory 203680 kb
Host smart-93e0e836-54f2-4168-862b-0ef49013f815
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88050437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.88050437
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.654224270
Short name T98
Test name
Test status
Simulation time 699414898 ps
CPU time 18.09 seconds
Started Mar 24 01:23:40 PM PDT 24
Finished Mar 24 01:23:58 PM PDT 24
Peak memory 203496 kb
Host smart-c6047636-14a4-4503-bcb3-cb32fcb45bec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=654224270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.654224270
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.515291393
Short name T622
Test name
Test status
Simulation time 642517242 ps
CPU time 23.99 seconds
Started Mar 24 01:23:35 PM PDT 24
Finished Mar 24 01:23:59 PM PDT 24
Peak memory 211676 kb
Host smart-20278e05-2421-47c9-b239-2313a8391c52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=515291393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.515291393
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2863439534
Short name T699
Test name
Test status
Simulation time 24220568746 ps
CPU time 80.08 seconds
Started Mar 24 01:23:35 PM PDT 24
Finished Mar 24 01:24:55 PM PDT 24
Peak memory 211724 kb
Host smart-746a4747-ba1e-43f8-bd41-f44ac6a7a960
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863439534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2863439534
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2945411044
Short name T196
Test name
Test status
Simulation time 21795629040 ps
CPU time 59.31 seconds
Started Mar 24 01:23:32 PM PDT 24
Finished Mar 24 01:24:32 PM PDT 24
Peak memory 205032 kb
Host smart-03b2a502-fd31-457b-981a-c802e228f7b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2945411044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2945411044
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2454279216
Short name T778
Test name
Test status
Simulation time 75693390 ps
CPU time 11.95 seconds
Started Mar 24 01:23:32 PM PDT 24
Finished Mar 24 01:23:44 PM PDT 24
Peak memory 204664 kb
Host smart-dfca5a93-83ff-4004-875a-85c6f3c456b4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454279216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2454279216
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.613422901
Short name T793
Test name
Test status
Simulation time 669127885 ps
CPU time 17.54 seconds
Started Mar 24 01:23:34 PM PDT 24
Finished Mar 24 01:23:51 PM PDT 24
Peak memory 204196 kb
Host smart-67c7d3e7-48bf-4ca1-8173-0ca3849dc690
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=613422901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.613422901
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.2686244094
Short name T331
Test name
Test status
Simulation time 112460202 ps
CPU time 3.77 seconds
Started Mar 24 01:23:34 PM PDT 24
Finished Mar 24 01:23:37 PM PDT 24
Peak memory 203484 kb
Host smart-3d7e2f2f-07b0-4ff8-8b60-33f171d55bdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2686244094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2686244094
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4132968596
Short name T436
Test name
Test status
Simulation time 20759678281 ps
CPU time 35.74 seconds
Started Mar 24 01:23:33 PM PDT 24
Finished Mar 24 01:24:09 PM PDT 24
Peak memory 203532 kb
Host smart-45879814-0d36-4c17-adae-77fbc23596b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132968596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4132968596
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3809972125
Short name T74
Test name
Test status
Simulation time 5824845920 ps
CPU time 40.94 seconds
Started Mar 24 01:23:32 PM PDT 24
Finished Mar 24 01:24:13 PM PDT 24
Peak memory 203560 kb
Host smart-6b851ae5-63ce-4cba-ae73-cfa4a677e2dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3809972125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3809972125
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2204141231
Short name T592
Test name
Test status
Simulation time 48393779 ps
CPU time 2.56 seconds
Started Mar 24 01:23:33 PM PDT 24
Finished Mar 24 01:23:35 PM PDT 24
Peak memory 203444 kb
Host smart-8f92650a-29dd-4af5-ab79-7d0011f28a31
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204141231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2204141231
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1970906835
Short name T479
Test name
Test status
Simulation time 13402696980 ps
CPU time 175.26 seconds
Started Mar 24 01:23:37 PM PDT 24
Finished Mar 24 01:26:32 PM PDT 24
Peak memory 207324 kb
Host smart-655a0cf4-2928-4247-bb59-9021018a837e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1970906835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1970906835
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1671103614
Short name T249
Test name
Test status
Simulation time 317517135 ps
CPU time 46 seconds
Started Mar 24 01:23:37 PM PDT 24
Finished Mar 24 01:24:23 PM PDT 24
Peak memory 205036 kb
Host smart-c448c24b-1246-401d-a4ec-8c0faed87a19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1671103614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1671103614
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1187271628
Short name T755
Test name
Test status
Simulation time 258835506 ps
CPU time 70.64 seconds
Started Mar 24 01:23:38 PM PDT 24
Finished Mar 24 01:24:49 PM PDT 24
Peak memory 207756 kb
Host smart-c895f939-000d-4fbd-867c-02162ed2671d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1187271628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1187271628
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3941375220
Short name T274
Test name
Test status
Simulation time 557667722 ps
CPU time 150.73 seconds
Started Mar 24 01:23:37 PM PDT 24
Finished Mar 24 01:26:08 PM PDT 24
Peak memory 211332 kb
Host smart-3d054e0a-6346-4597-98e2-8bf6384d6b34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3941375220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.3941375220
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.571049978
Short name T159
Test name
Test status
Simulation time 831687233 ps
CPU time 24.83 seconds
Started Mar 24 01:23:37 PM PDT 24
Finished Mar 24 01:24:02 PM PDT 24
Peak memory 204972 kb
Host smart-1c986adc-e241-46d7-afd1-26f3da51affd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=571049978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.571049978
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1063129792
Short name T138
Test name
Test status
Simulation time 2311916438 ps
CPU time 41.29 seconds
Started Mar 24 01:23:42 PM PDT 24
Finished Mar 24 01:24:24 PM PDT 24
Peak memory 211752 kb
Host smart-7a4c1f35-2cee-4cee-854a-a09b1f29f8ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1063129792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1063129792
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3679596124
Short name T136
Test name
Test status
Simulation time 55670547595 ps
CPU time 385.9 seconds
Started Mar 24 01:23:44 PM PDT 24
Finished Mar 24 01:30:10 PM PDT 24
Peak memory 207056 kb
Host smart-8c87943c-0a9a-47ea-9052-74b824e7158d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3679596124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.3679596124
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1307934101
Short name T707
Test name
Test status
Simulation time 2766564934 ps
CPU time 18.36 seconds
Started Mar 24 01:23:41 PM PDT 24
Finished Mar 24 01:23:59 PM PDT 24
Peak memory 203572 kb
Host smart-38667229-2309-4071-99ca-297740038772
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1307934101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1307934101
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.4265123187
Short name T612
Test name
Test status
Simulation time 102007737 ps
CPU time 7.85 seconds
Started Mar 24 01:23:43 PM PDT 24
Finished Mar 24 01:23:51 PM PDT 24
Peak memory 203752 kb
Host smart-3a9eef09-7b8b-4707-962f-f54cfec99561
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4265123187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.4265123187
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.3345155092
Short name T798
Test name
Test status
Simulation time 1214388205 ps
CPU time 22.85 seconds
Started Mar 24 01:23:39 PM PDT 24
Finished Mar 24 01:24:02 PM PDT 24
Peak memory 204636 kb
Host smart-b62b6ce9-69fb-4a72-8958-3675e4d746cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3345155092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3345155092
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4253206448
Short name T566
Test name
Test status
Simulation time 51625387302 ps
CPU time 233.37 seconds
Started Mar 24 01:23:44 PM PDT 24
Finished Mar 24 01:27:37 PM PDT 24
Peak memory 205412 kb
Host smart-85944283-1e75-41fa-8501-4011b2bd0a76
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253206448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4253206448
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1996402535
Short name T636
Test name
Test status
Simulation time 13892685807 ps
CPU time 79.95 seconds
Started Mar 24 01:23:44 PM PDT 24
Finished Mar 24 01:25:04 PM PDT 24
Peak memory 211752 kb
Host smart-94ee0336-6945-4d30-82de-97024ce4ed5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1996402535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1996402535
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.4024091919
Short name T640
Test name
Test status
Simulation time 122149486 ps
CPU time 20.42 seconds
Started Mar 24 01:23:44 PM PDT 24
Finished Mar 24 01:24:05 PM PDT 24
Peak memory 204756 kb
Host smart-4d0f93c8-2513-466f-b55d-7c92c4d67374
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024091919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.4024091919
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.4029273152
Short name T456
Test name
Test status
Simulation time 519475073 ps
CPU time 9.36 seconds
Started Mar 24 01:23:44 PM PDT 24
Finished Mar 24 01:23:54 PM PDT 24
Peak memory 203488 kb
Host smart-969df1a2-8787-4a45-b674-39de786dfd26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4029273152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4029273152
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.1231401708
Short name T614
Test name
Test status
Simulation time 571230311 ps
CPU time 3.41 seconds
Started Mar 24 01:23:39 PM PDT 24
Finished Mar 24 01:23:42 PM PDT 24
Peak memory 203468 kb
Host smart-65cc6ea3-6cc8-4275-b65e-f0494058ce22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1231401708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1231401708
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.531477552
Short name T628
Test name
Test status
Simulation time 6320093093 ps
CPU time 32.77 seconds
Started Mar 24 01:23:38 PM PDT 24
Finished Mar 24 01:24:11 PM PDT 24
Peak memory 203556 kb
Host smart-43124c92-50a1-405b-8ab7-8468684360be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=531477552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.531477552
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1981486453
Short name T738
Test name
Test status
Simulation time 3102886304 ps
CPU time 29.59 seconds
Started Mar 24 01:23:38 PM PDT 24
Finished Mar 24 01:24:08 PM PDT 24
Peak memory 203572 kb
Host smart-d61a2257-6eae-42a2-b37e-a298845cc815
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1981486453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1981486453
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3422960965
Short name T887
Test name
Test status
Simulation time 34263681 ps
CPU time 2.53 seconds
Started Mar 24 01:23:38 PM PDT 24
Finished Mar 24 01:23:40 PM PDT 24
Peak memory 203476 kb
Host smart-d575722a-96ea-43db-a670-92514f858f13
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422960965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3422960965
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2119669295
Short name T578
Test name
Test status
Simulation time 2058833753 ps
CPU time 111.75 seconds
Started Mar 24 01:23:45 PM PDT 24
Finished Mar 24 01:25:37 PM PDT 24
Peak memory 205860 kb
Host smart-3296e0fb-f9ff-4aec-b740-13b8f4d28a28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2119669295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2119669295
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.547600012
Short name T539
Test name
Test status
Simulation time 1889974480 ps
CPU time 104.35 seconds
Started Mar 24 01:23:45 PM PDT 24
Finished Mar 24 01:25:30 PM PDT 24
Peak memory 205996 kb
Host smart-b9504aa1-1df2-4577-bdbb-3158861d4875
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547600012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.547600012
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3090797790
Short name T751
Test name
Test status
Simulation time 2509149192 ps
CPU time 314.49 seconds
Started Mar 24 01:23:43 PM PDT 24
Finished Mar 24 01:28:57 PM PDT 24
Peak memory 211768 kb
Host smart-219cdfd3-2939-4802-9dbd-bc3b3a9ba9c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3090797790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.3090797790
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.4053948499
Short name T253
Test name
Test status
Simulation time 104444015 ps
CPU time 32.77 seconds
Started Mar 24 01:23:42 PM PDT 24
Finished Mar 24 01:24:14 PM PDT 24
Peak memory 205908 kb
Host smart-e77186d2-9138-4689-9a68-20b1a8a0ce5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4053948499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.4053948499
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.698822044
Short name T433
Test name
Test status
Simulation time 151681644 ps
CPU time 18.89 seconds
Started Mar 24 01:23:45 PM PDT 24
Finished Mar 24 01:24:04 PM PDT 24
Peak memory 204888 kb
Host smart-47dd0b3d-dfff-4414-9527-cf434240b7f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=698822044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.698822044
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1901882474
Short name T276
Test name
Test status
Simulation time 1714518377 ps
CPU time 56.88 seconds
Started Mar 24 01:23:48 PM PDT 24
Finished Mar 24 01:24:45 PM PDT 24
Peak memory 206292 kb
Host smart-ebb42346-657c-44c2-abc4-da1ee13be083
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1901882474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1901882474
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1563486857
Short name T440
Test name
Test status
Simulation time 16826323969 ps
CPU time 143.91 seconds
Started Mar 24 01:23:48 PM PDT 24
Finished Mar 24 01:26:12 PM PDT 24
Peak memory 206324 kb
Host smart-67511a22-04f4-4325-af26-02379d74bfec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1563486857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.1563486857
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2052015280
Short name T508
Test name
Test status
Simulation time 32789053 ps
CPU time 4.77 seconds
Started Mar 24 01:23:52 PM PDT 24
Finished Mar 24 01:23:57 PM PDT 24
Peak memory 203504 kb
Host smart-f0cb3d77-d51a-40b5-a1e1-57c6a6efdd87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2052015280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2052015280
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.2952613931
Short name T879
Test name
Test status
Simulation time 706526496 ps
CPU time 22.43 seconds
Started Mar 24 01:23:46 PM PDT 24
Finished Mar 24 01:24:09 PM PDT 24
Peak memory 203520 kb
Host smart-cd31cb7c-e194-49aa-8ae4-d8b39f41cf3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2952613931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2952613931
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.2994862812
Short name T147
Test name
Test status
Simulation time 500625607 ps
CPU time 11.26 seconds
Started Mar 24 01:23:47 PM PDT 24
Finished Mar 24 01:23:58 PM PDT 24
Peak memory 204604 kb
Host smart-2bf04f2d-2fe5-4c3c-9a38-2a8a28cd00e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2994862812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2994862812
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1210926414
Short name T381
Test name
Test status
Simulation time 31661068357 ps
CPU time 151.56 seconds
Started Mar 24 01:23:49 PM PDT 24
Finished Mar 24 01:26:21 PM PDT 24
Peak memory 211776 kb
Host smart-71b57631-5813-423a-8df3-b1826b009f4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210926414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1210926414
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.177585643
Short name T127
Test name
Test status
Simulation time 123738225377 ps
CPU time 243.31 seconds
Started Mar 24 01:23:47 PM PDT 24
Finished Mar 24 01:27:51 PM PDT 24
Peak memory 205028 kb
Host smart-e78516fc-8fe7-4ad2-b9ee-3282b043ed43
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=177585643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.177585643
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1040482005
Short name T708
Test name
Test status
Simulation time 13587187 ps
CPU time 2.1 seconds
Started Mar 24 01:23:48 PM PDT 24
Finished Mar 24 01:23:50 PM PDT 24
Peak memory 203488 kb
Host smart-5a2b254d-13c3-4177-a27e-0f1c3dee1ae8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040482005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1040482005
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.3062039733
Short name T227
Test name
Test status
Simulation time 1345684458 ps
CPU time 16.27 seconds
Started Mar 24 01:23:48 PM PDT 24
Finished Mar 24 01:24:04 PM PDT 24
Peak memory 203516 kb
Host smart-0ee630d3-fd9c-426f-9da6-f992b5a7e579
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3062039733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3062039733
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.4241882710
Short name T586
Test name
Test status
Simulation time 125840509 ps
CPU time 3.23 seconds
Started Mar 24 01:23:46 PM PDT 24
Finished Mar 24 01:23:49 PM PDT 24
Peak memory 203436 kb
Host smart-8892b8f6-1ee2-410e-9ee6-42d3b73bd8e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4241882710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.4241882710
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3563491585
Short name T736
Test name
Test status
Simulation time 11547414049 ps
CPU time 35.4 seconds
Started Mar 24 01:23:48 PM PDT 24
Finished Mar 24 01:24:23 PM PDT 24
Peak memory 203584 kb
Host smart-eceaa5b6-be2a-458f-ab74-3d8338476043
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563491585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3563491585
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.373733584
Short name T718
Test name
Test status
Simulation time 5092794775 ps
CPU time 33.73 seconds
Started Mar 24 01:23:47 PM PDT 24
Finished Mar 24 01:24:21 PM PDT 24
Peak memory 203532 kb
Host smart-289fbe38-b51b-464d-9c66-51ffe7e0ed38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=373733584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.373733584
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3707180536
Short name T623
Test name
Test status
Simulation time 26277140 ps
CPU time 2.38 seconds
Started Mar 24 01:23:47 PM PDT 24
Finished Mar 24 01:23:50 PM PDT 24
Peak memory 203516 kb
Host smart-38d3bda0-0cea-4ea9-8582-659d61c62f63
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707180536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3707180536
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3424990900
Short name T410
Test name
Test status
Simulation time 2558514635 ps
CPU time 194.04 seconds
Started Mar 24 01:23:52 PM PDT 24
Finished Mar 24 01:27:06 PM PDT 24
Peak memory 209980 kb
Host smart-076d10ce-b042-4acd-ac97-ef9f75545b27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3424990900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3424990900
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.4201628606
Short name T585
Test name
Test status
Simulation time 6299148198 ps
CPU time 172.44 seconds
Started Mar 24 01:23:53 PM PDT 24
Finished Mar 24 01:26:46 PM PDT 24
Peak memory 208008 kb
Host smart-30a3b0d5-160d-4e2f-98de-52a7faa44cf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4201628606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4201628606
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1986498103
Short name T825
Test name
Test status
Simulation time 396615196 ps
CPU time 106.95 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:25:43 PM PDT 24
Peak memory 206816 kb
Host smart-cbc4ac73-e36d-492a-b921-fcb2701e0598
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1986498103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.1986498103
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1857040655
Short name T529
Test name
Test status
Simulation time 3302420617 ps
CPU time 234.66 seconds
Started Mar 24 01:23:54 PM PDT 24
Finished Mar 24 01:27:49 PM PDT 24
Peak memory 220196 kb
Host smart-5389baae-feee-443d-ab55-73212c6422f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1857040655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.1857040655
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.4214582352
Short name T810
Test name
Test status
Simulation time 1108535381 ps
CPU time 44.85 seconds
Started Mar 24 01:23:54 PM PDT 24
Finished Mar 24 01:24:39 PM PDT 24
Peak memory 206092 kb
Host smart-859aad66-6ba0-4dff-a5e2-fc61cbdae155
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4214582352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.4214582352
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2359346424
Short name T132
Test name
Test status
Simulation time 49514669847 ps
CPU time 360.76 seconds
Started Mar 24 01:23:52 PM PDT 24
Finished Mar 24 01:29:53 PM PDT 24
Peak memory 211732 kb
Host smart-b774ff3f-ca1f-40b8-a0d2-fe0752ea148b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2359346424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.2359346424
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3478665095
Short name T549
Test name
Test status
Simulation time 460778278 ps
CPU time 16.97 seconds
Started Mar 24 01:23:57 PM PDT 24
Finished Mar 24 01:24:14 PM PDT 24
Peak memory 203504 kb
Host smart-3cebef85-b1b7-45f1-980e-fc83964677b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3478665095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3478665095
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2087078878
Short name T761
Test name
Test status
Simulation time 43560239 ps
CPU time 1.73 seconds
Started Mar 24 01:23:52 PM PDT 24
Finished Mar 24 01:23:54 PM PDT 24
Peak memory 203480 kb
Host smart-ce6efcd3-cfbd-4643-b766-8211a5260a52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2087078878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2087078878
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.3031111411
Short name T471
Test name
Test status
Simulation time 356154513 ps
CPU time 17.45 seconds
Started Mar 24 01:23:53 PM PDT 24
Finished Mar 24 01:24:11 PM PDT 24
Peak memory 204692 kb
Host smart-131ee762-cc98-47d8-b22d-7aacb56f5864
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3031111411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3031111411
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3726244744
Short name T117
Test name
Test status
Simulation time 63968906299 ps
CPU time 193.85 seconds
Started Mar 24 01:23:53 PM PDT 24
Finished Mar 24 01:27:08 PM PDT 24
Peak memory 205124 kb
Host smart-482fdc32-ccb4-42e9-b4f1-a524640a535a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726244744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3726244744
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.654323505
Short name T880
Test name
Test status
Simulation time 23600025869 ps
CPU time 85.18 seconds
Started Mar 24 01:23:52 PM PDT 24
Finished Mar 24 01:25:17 PM PDT 24
Peak memory 204992 kb
Host smart-9a93043d-2568-4d11-bcb7-a567ca08c550
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=654323505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.654323505
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2974111620
Short name T532
Test name
Test status
Simulation time 120996278 ps
CPU time 19.52 seconds
Started Mar 24 01:23:52 PM PDT 24
Finished Mar 24 01:24:12 PM PDT 24
Peak memory 205060 kb
Host smart-e2959243-3cd4-48d6-ba87-97a2a7656bd6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974111620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2974111620
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.1248120805
Short name T377
Test name
Test status
Simulation time 334647194 ps
CPU time 16.6 seconds
Started Mar 24 01:23:51 PM PDT 24
Finished Mar 24 01:24:08 PM PDT 24
Peak memory 203532 kb
Host smart-55ad58e0-0c61-41d1-a79f-161d9904c647
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1248120805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1248120805
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.4269596608
Short name T240
Test name
Test status
Simulation time 47431915 ps
CPU time 2.36 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:23:58 PM PDT 24
Peak memory 203436 kb
Host smart-9335f63e-3087-4e32-8f97-50fb402abb4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4269596608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4269596608
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2113838383
Short name T303
Test name
Test status
Simulation time 5783321465 ps
CPU time 21.75 seconds
Started Mar 24 01:23:54 PM PDT 24
Finished Mar 24 01:24:16 PM PDT 24
Peak memory 203544 kb
Host smart-da1f0d65-4797-4ba6-8996-33a56f4e9f65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113838383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2113838383
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2548454824
Short name T1
Test name
Test status
Simulation time 3075060332 ps
CPU time 29.6 seconds
Started Mar 24 01:23:54 PM PDT 24
Finished Mar 24 01:24:24 PM PDT 24
Peak memory 203584 kb
Host smart-e3ecdd0e-a83d-412b-9752-9a437a12d4f5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2548454824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2548454824
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1325147214
Short name T215
Test name
Test status
Simulation time 43002261 ps
CPU time 2.27 seconds
Started Mar 24 01:23:51 PM PDT 24
Finished Mar 24 01:23:54 PM PDT 24
Peak memory 203488 kb
Host smart-ec4801c0-8328-4628-b6ef-ffa56f1b8739
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325147214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1325147214
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3434066100
Short name T400
Test name
Test status
Simulation time 424738896 ps
CPU time 52.21 seconds
Started Mar 24 01:23:59 PM PDT 24
Finished Mar 24 01:24:51 PM PDT 24
Peak memory 206472 kb
Host smart-a824e945-d0d7-45b1-bd35-1583a6e28f3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3434066100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3434066100
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3856542783
Short name T696
Test name
Test status
Simulation time 1569074582 ps
CPU time 153.28 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:26:30 PM PDT 24
Peak memory 208396 kb
Host smart-827e5d54-3ac0-46b7-b7ae-e17af6b2b646
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3856542783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3856542783
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.104409036
Short name T213
Test name
Test status
Simulation time 290373238 ps
CPU time 64.92 seconds
Started Mar 24 01:23:58 PM PDT 24
Finished Mar 24 01:25:04 PM PDT 24
Peak memory 206664 kb
Host smart-b4ad4cc9-f0e9-451f-be46-c34ca54da52d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104409036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand
_reset.104409036
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2276274668
Short name T305
Test name
Test status
Simulation time 4526608739 ps
CPU time 180.7 seconds
Started Mar 24 01:23:57 PM PDT 24
Finished Mar 24 01:26:58 PM PDT 24
Peak memory 209996 kb
Host smart-026d5f5a-56a6-4bb0-98f8-a03ba40d8ad4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2276274668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.2276274668
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1961704280
Short name T729
Test name
Test status
Simulation time 175005668 ps
CPU time 5.44 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:24:02 PM PDT 24
Peak memory 204704 kb
Host smart-df620070-7791-43e9-a47b-2b74becfe65e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1961704280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1961704280
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2049408380
Short name T541
Test name
Test status
Simulation time 188201342 ps
CPU time 14.21 seconds
Started Mar 24 01:23:59 PM PDT 24
Finished Mar 24 01:24:13 PM PDT 24
Peak memory 205500 kb
Host smart-6a7cb858-f59c-4af7-9715-bf1eb98689fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2049408380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2049408380
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1240599996
Short name T632
Test name
Test status
Simulation time 64018403179 ps
CPU time 283.48 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:28:40 PM PDT 24
Peak memory 206592 kb
Host smart-1e1ee54b-0107-4b8d-b808-a114c2c0dae6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1240599996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1240599996
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2120697598
Short name T794
Test name
Test status
Simulation time 186758660 ps
CPU time 17.87 seconds
Started Mar 24 01:24:01 PM PDT 24
Finished Mar 24 01:24:20 PM PDT 24
Peak memory 203516 kb
Host smart-5c2327b5-1d68-495f-9bbf-f2c485689e54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2120697598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2120697598
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.1808676914
Short name T553
Test name
Test status
Simulation time 948971970 ps
CPU time 29.23 seconds
Started Mar 24 01:23:57 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 203532 kb
Host smart-2df38812-f40a-4d07-a008-b30c357442cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1808676914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1808676914
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.263649292
Short name T148
Test name
Test status
Simulation time 712319109 ps
CPU time 29.4 seconds
Started Mar 24 01:23:59 PM PDT 24
Finished Mar 24 01:24:28 PM PDT 24
Peak memory 204592 kb
Host smart-570eadae-d66f-4543-a695-6a7f91d049a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=263649292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.263649292
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3551526822
Short name T602
Test name
Test status
Simulation time 13190500573 ps
CPU time 75.35 seconds
Started Mar 24 01:23:57 PM PDT 24
Finished Mar 24 01:25:13 PM PDT 24
Peak memory 211760 kb
Host smart-9c73bd91-9c6b-4c5e-a4b5-4e24e88f3802
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551526822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3551526822
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.528456994
Short name T50
Test name
Test status
Simulation time 1014619040 ps
CPU time 9.78 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:24:07 PM PDT 24
Peak memory 203520 kb
Host smart-b5968748-ac2b-4983-a243-8ee8478de69e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=528456994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.528456994
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1353991587
Short name T299
Test name
Test status
Simulation time 65846802 ps
CPU time 5.96 seconds
Started Mar 24 01:23:58 PM PDT 24
Finished Mar 24 01:24:05 PM PDT 24
Peak memory 211712 kb
Host smart-b4344391-dda2-4797-ac99-b36df10d6830
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353991587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1353991587
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.741170350
Short name T165
Test name
Test status
Simulation time 8318340745 ps
CPU time 40.57 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:24:36 PM PDT 24
Peak memory 211724 kb
Host smart-b1209826-c14e-4d42-a60e-247874f2080c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=741170350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.741170350
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.3823041889
Short name T619
Test name
Test status
Simulation time 429062560 ps
CPU time 3.34 seconds
Started Mar 24 01:24:00 PM PDT 24
Finished Mar 24 01:24:03 PM PDT 24
Peak memory 203472 kb
Host smart-ba9aa21d-b848-4369-857e-be7da6541a36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3823041889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3823041889
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2148269420
Short name T809
Test name
Test status
Simulation time 9905999877 ps
CPU time 31.54 seconds
Started Mar 24 01:24:01 PM PDT 24
Finished Mar 24 01:24:33 PM PDT 24
Peak memory 203568 kb
Host smart-53566ea8-df20-4088-8d87-df7a4b54da7c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148269420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2148269420
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.977452607
Short name T716
Test name
Test status
Simulation time 11918525127 ps
CPU time 43.22 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:24:40 PM PDT 24
Peak memory 203548 kb
Host smart-bc103fd0-f796-430f-9e96-328fe1be8baa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=977452607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.977452607
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.997147555
Short name T8
Test name
Test status
Simulation time 25374854 ps
CPU time 2.18 seconds
Started Mar 24 01:23:56 PM PDT 24
Finished Mar 24 01:23:59 PM PDT 24
Peak memory 203492 kb
Host smart-503083a6-d483-474d-a24b-9654b2275e9f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997147555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.997147555
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3030526635
Short name T135
Test name
Test status
Simulation time 4311274567 ps
CPU time 173.46 seconds
Started Mar 24 01:23:58 PM PDT 24
Finished Mar 24 01:26:52 PM PDT 24
Peak memory 209480 kb
Host smart-5dacc1c0-2c83-4845-b229-2acf9dfaadef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3030526635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3030526635
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1903177654
Short name T813
Test name
Test status
Simulation time 758033308 ps
CPU time 24.74 seconds
Started Mar 24 01:24:03 PM PDT 24
Finished Mar 24 01:24:28 PM PDT 24
Peak memory 204348 kb
Host smart-d485cbbe-8fe2-46b4-bc64-a221f738cce6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1903177654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1903177654
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2019363824
Short name T550
Test name
Test status
Simulation time 1865260157 ps
CPU time 269.49 seconds
Started Mar 24 01:23:57 PM PDT 24
Finished Mar 24 01:28:26 PM PDT 24
Peak memory 208064 kb
Host smart-4c3879e9-f789-49c1-901e-f4137ac6dbab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2019363824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.2019363824
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2030456187
Short name T414
Test name
Test status
Simulation time 1488320469 ps
CPU time 310.39 seconds
Started Mar 24 01:24:03 PM PDT 24
Finished Mar 24 01:29:13 PM PDT 24
Peak memory 219884 kb
Host smart-03e66537-857c-4afd-bbe1-4f2e1cf5a05c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2030456187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.2030456187
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.526249712
Short name T191
Test name
Test status
Simulation time 420182672 ps
CPU time 23.13 seconds
Started Mar 24 01:23:58 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 204948 kb
Host smart-c9a8671c-d8b6-40c7-930b-112c5c9fbfc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=526249712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.526249712
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.236939248
Short name T641
Test name
Test status
Simulation time 304434971 ps
CPU time 26.77 seconds
Started Mar 24 01:24:02 PM PDT 24
Finished Mar 24 01:24:29 PM PDT 24
Peak memory 211572 kb
Host smart-6d16f7bc-c64b-4645-9a35-b8dc7e4b1c90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=236939248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.236939248
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2637854260
Short name T9
Test name
Test status
Simulation time 97598026 ps
CPU time 12.78 seconds
Started Mar 24 01:24:08 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 203808 kb
Host smart-3387c7f9-f87f-4729-b05a-215f880d7d26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2637854260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2637854260
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.3841502385
Short name T881
Test name
Test status
Simulation time 163741464 ps
CPU time 16.48 seconds
Started Mar 24 01:24:01 PM PDT 24
Finished Mar 24 01:24:18 PM PDT 24
Peak memory 203584 kb
Host smart-b9a3c3f8-afcd-4866-ae43-11f64d6921ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3841502385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3841502385
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3022997414
Short name T575
Test name
Test status
Simulation time 45481751 ps
CPU time 4.95 seconds
Started Mar 24 01:24:03 PM PDT 24
Finished Mar 24 01:24:08 PM PDT 24
Peak memory 204568 kb
Host smart-ff875469-c89b-4adf-88b1-5c5f982cdcbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3022997414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3022997414
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.828597831
Short name T146
Test name
Test status
Simulation time 122259872292 ps
CPU time 221.13 seconds
Started Mar 24 01:24:02 PM PDT 24
Finished Mar 24 01:27:43 PM PDT 24
Peak memory 204740 kb
Host smart-8b42ac53-5b73-4fcb-93b5-f7996e0065db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=828597831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.828597831
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3405789556
Short name T177
Test name
Test status
Simulation time 91407896962 ps
CPU time 315.72 seconds
Started Mar 24 01:24:03 PM PDT 24
Finished Mar 24 01:29:19 PM PDT 24
Peak memory 204812 kb
Host smart-a8c26a5f-aa2e-401c-b18a-591f057b9329
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3405789556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3405789556
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.374629777
Short name T340
Test name
Test status
Simulation time 101228850 ps
CPU time 4.75 seconds
Started Mar 24 01:24:02 PM PDT 24
Finished Mar 24 01:24:07 PM PDT 24
Peak memory 204588 kb
Host smart-e2c75942-2ec4-4ccb-8793-eeb08840f185
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374629777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.374629777
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.3811238407
Short name T462
Test name
Test status
Simulation time 2207311044 ps
CPU time 26.6 seconds
Started Mar 24 01:24:03 PM PDT 24
Finished Mar 24 01:24:30 PM PDT 24
Peak memory 204136 kb
Host smart-722d7ab1-471e-423b-b17d-cabeeacbce75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3811238407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3811238407
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.3515769904
Short name T7
Test name
Test status
Simulation time 138568760 ps
CPU time 3.53 seconds
Started Mar 24 01:24:02 PM PDT 24
Finished Mar 24 01:24:06 PM PDT 24
Peak memory 203492 kb
Host smart-9aabdd06-3114-4058-93b4-1cd887f44198
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3515769904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3515769904
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1666126224
Short name T60
Test name
Test status
Simulation time 4646531091 ps
CPU time 22.11 seconds
Started Mar 24 01:24:03 PM PDT 24
Finished Mar 24 01:24:25 PM PDT 24
Peak memory 203544 kb
Host smart-ebba3182-5664-4721-ba2c-1b776c8d9955
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666126224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1666126224
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2320991971
Short name T784
Test name
Test status
Simulation time 3103685143 ps
CPU time 23.16 seconds
Started Mar 24 01:24:01 PM PDT 24
Finished Mar 24 01:24:25 PM PDT 24
Peak memory 203520 kb
Host smart-08d4068a-b410-42a1-bad9-2ffe150b3688
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2320991971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2320991971
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.218936095
Short name T143
Test name
Test status
Simulation time 37792331 ps
CPU time 2.8 seconds
Started Mar 24 01:24:01 PM PDT 24
Finished Mar 24 01:24:05 PM PDT 24
Peak memory 203488 kb
Host smart-002c6887-2bb7-4d8d-84aa-8165a802d0ec
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218936095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.218936095
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.992502035
Short name T382
Test name
Test status
Simulation time 191832736 ps
CPU time 13.69 seconds
Started Mar 24 01:24:07 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 205584 kb
Host smart-61ffc2f6-d529-410d-b247-25b13755fb51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=992502035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.992502035
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3997977670
Short name T320
Test name
Test status
Simulation time 2845472483 ps
CPU time 46.29 seconds
Started Mar 24 01:24:08 PM PDT 24
Finished Mar 24 01:24:54 PM PDT 24
Peak memory 204668 kb
Host smart-12bef117-7ff8-4203-aec7-362780af5433
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3997977670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3997977670
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1194625954
Short name T694
Test name
Test status
Simulation time 92386330 ps
CPU time 21.86 seconds
Started Mar 24 01:24:07 PM PDT 24
Finished Mar 24 01:24:29 PM PDT 24
Peak memory 206428 kb
Host smart-ec907603-daf7-44c0-92d1-0f8d0dbc4404
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1194625954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.1194625954
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1249987827
Short name T309
Test name
Test status
Simulation time 41244422 ps
CPU time 9.55 seconds
Started Mar 24 01:24:08 PM PDT 24
Finished Mar 24 01:24:18 PM PDT 24
Peak memory 204940 kb
Host smart-eb0af1c4-a702-427c-be7d-151878917a48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1249987827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.1249987827
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1590805834
Short name T417
Test name
Test status
Simulation time 816649671 ps
CPU time 19 seconds
Started Mar 24 01:24:06 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 204868 kb
Host smart-cbf89dac-ddf2-42e5-8e8e-aa31f5fe629d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1590805834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1590805834
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1900578605
Short name T149
Test name
Test status
Simulation time 231670979 ps
CPU time 8.53 seconds
Started Mar 24 01:24:07 PM PDT 24
Finished Mar 24 01:24:16 PM PDT 24
Peak memory 205080 kb
Host smart-51e74a13-108c-455b-8f03-961ec0f5f9e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1900578605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1900578605
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.939125747
Short name T773
Test name
Test status
Simulation time 675037565 ps
CPU time 24.39 seconds
Started Mar 24 01:24:12 PM PDT 24
Finished Mar 24 01:24:36 PM PDT 24
Peak memory 203788 kb
Host smart-fe50f103-49cd-43c8-8dd8-2985294cded5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=939125747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.939125747
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.820588153
Short name T317
Test name
Test status
Simulation time 783722828 ps
CPU time 25.9 seconds
Started Mar 24 01:24:12 PM PDT 24
Finished Mar 24 01:24:38 PM PDT 24
Peak memory 203468 kb
Host smart-6f476364-ddd1-4b85-8fa2-9553a070c898
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=820588153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.820588153
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.1557317432
Short name T120
Test name
Test status
Simulation time 166207516 ps
CPU time 10.9 seconds
Started Mar 24 01:24:07 PM PDT 24
Finished Mar 24 01:24:19 PM PDT 24
Peak memory 204548 kb
Host smart-0f1015ab-b198-4eb5-9361-c98d67f510b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1557317432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1557317432
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3388367409
Short name T314
Test name
Test status
Simulation time 6522280251 ps
CPU time 39.57 seconds
Started Mar 24 01:24:07 PM PDT 24
Finished Mar 24 01:24:47 PM PDT 24
Peak memory 204712 kb
Host smart-9049ce4f-3e7d-4b87-82cc-dba6225406a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388367409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3388367409
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.265301551
Short name T544
Test name
Test status
Simulation time 14407836277 ps
CPU time 119.36 seconds
Started Mar 24 01:24:08 PM PDT 24
Finished Mar 24 01:26:08 PM PDT 24
Peak memory 205080 kb
Host smart-3b72e22f-c530-42dc-9cec-043f66e4194a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=265301551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.265301551
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3514261140
Short name T197
Test name
Test status
Simulation time 178896422 ps
CPU time 13.89 seconds
Started Mar 24 01:24:08 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 204572 kb
Host smart-9546f4d4-f303-441b-a883-ac5c1e6b96c0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514261140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3514261140
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.1528953554
Short name T869
Test name
Test status
Simulation time 1815663061 ps
CPU time 16.04 seconds
Started Mar 24 01:24:14 PM PDT 24
Finished Mar 24 01:24:31 PM PDT 24
Peak memory 204056 kb
Host smart-d3206dda-7c12-423b-99dd-0d8d01e7643f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1528953554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1528953554
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.1600048949
Short name T488
Test name
Test status
Simulation time 183843756 ps
CPU time 3.22 seconds
Started Mar 24 01:24:07 PM PDT 24
Finished Mar 24 01:24:10 PM PDT 24
Peak memory 203476 kb
Host smart-0df70c8b-9e01-40f3-acc3-e2d36946395c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1600048949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1600048949
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3518073542
Short name T121
Test name
Test status
Simulation time 7142998444 ps
CPU time 30.85 seconds
Started Mar 24 01:24:07 PM PDT 24
Finished Mar 24 01:24:38 PM PDT 24
Peak memory 203556 kb
Host smart-4206dcad-16dd-4060-a0ca-f20496e13958
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518073542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3518073542
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3539580472
Short name T427
Test name
Test status
Simulation time 4186428417 ps
CPU time 25.74 seconds
Started Mar 24 01:24:09 PM PDT 24
Finished Mar 24 01:24:35 PM PDT 24
Peak memory 203584 kb
Host smart-59f9e36a-1457-46eb-a90f-02b6cc8eeee8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3539580472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3539580472
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.286616456
Short name T458
Test name
Test status
Simulation time 34131558 ps
CPU time 2.48 seconds
Started Mar 24 01:24:06 PM PDT 24
Finished Mar 24 01:24:09 PM PDT 24
Peak memory 203508 kb
Host smart-7b913e92-fc73-41e5-838f-137e6f271e5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286616456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.286616456
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1246540271
Short name T111
Test name
Test status
Simulation time 10510332947 ps
CPU time 224.44 seconds
Started Mar 24 01:24:10 PM PDT 24
Finished Mar 24 01:27:55 PM PDT 24
Peak memory 207116 kb
Host smart-4badea5f-296a-4e82-a7fe-244d259a472e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1246540271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1246540271
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1232661399
Short name T337
Test name
Test status
Simulation time 5578492943 ps
CPU time 159.59 seconds
Started Mar 24 01:24:11 PM PDT 24
Finished Mar 24 01:26:51 PM PDT 24
Peak memory 206504 kb
Host smart-d92b2d3c-622b-49b6-aff6-aea0bb660303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1232661399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1232661399
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.742991197
Short name T32
Test name
Test status
Simulation time 880712643 ps
CPU time 263.73 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:28:37 PM PDT 24
Peak memory 219888 kb
Host smart-9ca79271-dddd-44cc-b933-ae588452b3b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=742991197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.742991197
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.252840012
Short name T669
Test name
Test status
Simulation time 27793656 ps
CPU time 3.51 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:24:17 PM PDT 24
Peak memory 204648 kb
Host smart-acf7b1c2-df2e-4b4f-8730-0a2519f898f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=252840012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.252840012
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1047950549
Short name T355
Test name
Test status
Simulation time 1042963424 ps
CPU time 24.12 seconds
Started Mar 24 01:20:34 PM PDT 24
Finished Mar 24 01:20:59 PM PDT 24
Peak memory 204592 kb
Host smart-b423b527-bd0c-49a6-a8a1-09494b4156b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1047950549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1047950549
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1627063611
Short name T62
Test name
Test status
Simulation time 87591756235 ps
CPU time 342.95 seconds
Started Mar 24 01:20:38 PM PDT 24
Finished Mar 24 01:26:21 PM PDT 24
Peak memory 206648 kb
Host smart-6f56256e-00fc-4de7-9919-d6fa03cf7cf0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1627063611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.1627063611
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2546784597
Short name T587
Test name
Test status
Simulation time 43591962 ps
CPU time 5.24 seconds
Started Mar 24 01:20:35 PM PDT 24
Finished Mar 24 01:20:41 PM PDT 24
Peak memory 203564 kb
Host smart-5d53023d-5cc6-4929-8464-dff4c5d05a3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2546784597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2546784597
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.1428418001
Short name T203
Test name
Test status
Simulation time 232483907 ps
CPU time 14.78 seconds
Started Mar 24 01:20:35 PM PDT 24
Finished Mar 24 01:20:50 PM PDT 24
Peak memory 203508 kb
Host smart-a9407a1d-1749-42a1-afc9-092c24a54c2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1428418001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1428418001
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.1971052941
Short name T178
Test name
Test status
Simulation time 579052813 ps
CPU time 26.36 seconds
Started Mar 24 01:20:31 PM PDT 24
Finished Mar 24 01:20:57 PM PDT 24
Peak memory 211684 kb
Host smart-dbbdb153-e9a5-4f20-a444-ebe29fb80399
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1971052941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1971052941
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.617716220
Short name T679
Test name
Test status
Simulation time 43533808849 ps
CPU time 111.17 seconds
Started Mar 24 01:20:37 PM PDT 24
Finished Mar 24 01:22:28 PM PDT 24
Peak memory 205184 kb
Host smart-377b7722-2e9c-41bd-adac-446a97a18336
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=617716220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.617716220
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.822107714
Short name T421
Test name
Test status
Simulation time 23457913646 ps
CPU time 86.3 seconds
Started Mar 24 01:20:35 PM PDT 24
Finished Mar 24 01:22:01 PM PDT 24
Peak memory 205008 kb
Host smart-70923cd4-7ace-4aef-9fb0-020d0e918423
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=822107714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.822107714
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.15872215
Short name T764
Test name
Test status
Simulation time 282334112 ps
CPU time 24.33 seconds
Started Mar 24 01:20:37 PM PDT 24
Finished Mar 24 01:21:01 PM PDT 24
Peak memory 205012 kb
Host smart-90ec30da-afd2-4b9f-8266-f494a4083105
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15872215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.15872215
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.3084688385
Short name T408
Test name
Test status
Simulation time 1825025755 ps
CPU time 34.49 seconds
Started Mar 24 01:20:36 PM PDT 24
Finished Mar 24 01:21:10 PM PDT 24
Peak memory 203520 kb
Host smart-05e51b44-a926-4122-8a07-bedaf978d693
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3084688385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3084688385
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.3767807979
Short name T894
Test name
Test status
Simulation time 180997352 ps
CPU time 4.75 seconds
Started Mar 24 01:20:33 PM PDT 24
Finished Mar 24 01:20:38 PM PDT 24
Peak memory 203512 kb
Host smart-99829e36-05b4-4f77-8092-e466e0453a38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3767807979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3767807979
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1835931209
Short name T304
Test name
Test status
Simulation time 4478116500 ps
CPU time 27.89 seconds
Started Mar 24 01:20:30 PM PDT 24
Finished Mar 24 01:20:58 PM PDT 24
Peak memory 203792 kb
Host smart-461a753e-e433-47f9-b0c1-7118c88191b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835931209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1835931209
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1630242197
Short name T530
Test name
Test status
Simulation time 4574366507 ps
CPU time 26.43 seconds
Started Mar 24 01:20:28 PM PDT 24
Finished Mar 24 01:20:55 PM PDT 24
Peak memory 203540 kb
Host smart-66187158-4c7d-4dd7-964f-87f81e9cf813
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1630242197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1630242197
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2791647251
Short name T624
Test name
Test status
Simulation time 30297323 ps
CPU time 2.76 seconds
Started Mar 24 01:20:34 PM PDT 24
Finished Mar 24 01:20:36 PM PDT 24
Peak memory 203508 kb
Host smart-deb0675e-1319-4a1d-b9e8-e68f3fabe441
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791647251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2791647251
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1203623122
Short name T593
Test name
Test status
Simulation time 280970572 ps
CPU time 23.04 seconds
Started Mar 24 01:20:35 PM PDT 24
Finished Mar 24 01:20:58 PM PDT 24
Peak memory 211664 kb
Host smart-cb2c38ca-ecd1-40fa-b879-66bd92531972
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1203623122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1203623122
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.567309673
Short name T116
Test name
Test status
Simulation time 574891810 ps
CPU time 34.44 seconds
Started Mar 24 01:20:35 PM PDT 24
Finished Mar 24 01:21:09 PM PDT 24
Peak memory 204572 kb
Host smart-7edacafe-d231-498f-8f93-791535721b32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=567309673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.567309673
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.189181205
Short name T754
Test name
Test status
Simulation time 6315659854 ps
CPU time 312.86 seconds
Started Mar 24 01:20:38 PM PDT 24
Finished Mar 24 01:25:51 PM PDT 24
Peak memory 211156 kb
Host smart-b1c9e3f6-b507-4e10-9f65-7da689e84827
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=189181205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_
reset.189181205
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3160173358
Short name T502
Test name
Test status
Simulation time 126142728 ps
CPU time 17.4 seconds
Started Mar 24 01:20:36 PM PDT 24
Finished Mar 24 01:20:53 PM PDT 24
Peak memory 204948 kb
Host smart-98db0d2d-1a2b-4b59-877e-237422b3f731
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3160173358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3160173358
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4059991111
Short name T495
Test name
Test status
Simulation time 7316950842 ps
CPU time 61.78 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:25:15 PM PDT 24
Peak memory 205872 kb
Host smart-d0e5f501-130a-4de9-9944-96dc093f2d77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4059991111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4059991111
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.29923075
Short name T630
Test name
Test status
Simulation time 96772379242 ps
CPU time 606.39 seconds
Started Mar 24 01:24:14 PM PDT 24
Finished Mar 24 01:34:21 PM PDT 24
Peak memory 207632 kb
Host smart-6c574747-c785-4c69-840b-38c2843cc872
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=29923075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow
_rsp.29923075
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2442216723
Short name T552
Test name
Test status
Simulation time 651937624 ps
CPU time 20.26 seconds
Started Mar 24 01:24:15 PM PDT 24
Finished Mar 24 01:24:35 PM PDT 24
Peak memory 203760 kb
Host smart-a548031d-ef1e-4a8d-8d75-30762fd5777e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2442216723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2442216723
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.3619164987
Short name T393
Test name
Test status
Simulation time 960925538 ps
CPU time 23.21 seconds
Started Mar 24 01:24:11 PM PDT 24
Finished Mar 24 01:24:34 PM PDT 24
Peak memory 203448 kb
Host smart-898651b8-5857-4488-b481-604ca88b53fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3619164987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3619164987
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.880461606
Short name T175
Test name
Test status
Simulation time 2184740932 ps
CPU time 27.1 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:24:40 PM PDT 24
Peak memory 204768 kb
Host smart-a83c7e12-22fe-4464-abfb-147d6220f1c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=880461606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.880461606
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3948913348
Short name T277
Test name
Test status
Simulation time 13633744913 ps
CPU time 54.35 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:25:07 PM PDT 24
Peak memory 204872 kb
Host smart-3918b908-a9bd-42e1-b1de-52b4f9b530ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948913348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3948913348
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.4196184422
Short name T435
Test name
Test status
Simulation time 66886543200 ps
CPU time 133.51 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:26:27 PM PDT 24
Peak memory 204828 kb
Host smart-ba4cbd24-0e00-4ce5-a7ba-402ce2a7d550
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4196184422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4196184422
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1584176842
Short name T835
Test name
Test status
Simulation time 144603966 ps
CPU time 5.93 seconds
Started Mar 24 01:24:14 PM PDT 24
Finished Mar 24 01:24:20 PM PDT 24
Peak memory 204640 kb
Host smart-c2264ac9-0ed7-4891-a57a-09fcfad2a8a7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584176842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1584176842
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2301430013
Short name T313
Test name
Test status
Simulation time 290580763 ps
CPU time 16.64 seconds
Started Mar 24 01:24:15 PM PDT 24
Finished Mar 24 01:24:32 PM PDT 24
Peak memory 203472 kb
Host smart-d138f9a0-1023-44dc-a765-b02760cf8a7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2301430013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2301430013
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.783821066
Short name T715
Test name
Test status
Simulation time 185605191 ps
CPU time 3.67 seconds
Started Mar 24 01:24:11 PM PDT 24
Finished Mar 24 01:24:15 PM PDT 24
Peak memory 203468 kb
Host smart-110647a9-ff2e-4511-ab7b-2b02dc3eeeda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=783821066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.783821066
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1437958080
Short name T697
Test name
Test status
Simulation time 41559372031 ps
CPU time 56.56 seconds
Started Mar 24 01:24:13 PM PDT 24
Finished Mar 24 01:25:10 PM PDT 24
Peak memory 203596 kb
Host smart-595a72de-5eb2-41f7-b308-987800673425
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437958080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1437958080
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1635413981
Short name T560
Test name
Test status
Simulation time 4864562444 ps
CPU time 34.76 seconds
Started Mar 24 01:24:11 PM PDT 24
Finished Mar 24 01:24:46 PM PDT 24
Peak memory 203532 kb
Host smart-6d5fe02c-4538-49f0-9285-28541c582e5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1635413981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1635413981
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1424688386
Short name T719
Test name
Test status
Simulation time 63454536 ps
CPU time 2.53 seconds
Started Mar 24 01:24:12 PM PDT 24
Finished Mar 24 01:24:15 PM PDT 24
Peak memory 203444 kb
Host smart-cb3c15dd-b437-4295-8f05-4505b6a37487
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424688386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1424688386
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2281224561
Short name T91
Test name
Test status
Simulation time 6939188249 ps
CPU time 279.2 seconds
Started Mar 24 01:24:18 PM PDT 24
Finished Mar 24 01:28:57 PM PDT 24
Peak memory 211748 kb
Host smart-89e5cfcb-50c7-4b83-87c9-893a3adbdd3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281224561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2281224561
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2245347375
Short name T667
Test name
Test status
Simulation time 1216993158 ps
CPU time 109.8 seconds
Started Mar 24 01:24:19 PM PDT 24
Finished Mar 24 01:26:09 PM PDT 24
Peak memory 208884 kb
Host smart-49868f28-fb6a-4a3a-9ca0-a0e437716384
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2245347375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2245347375
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2622113367
Short name T302
Test name
Test status
Simulation time 4496704291 ps
CPU time 222.48 seconds
Started Mar 24 01:24:17 PM PDT 24
Finished Mar 24 01:28:00 PM PDT 24
Peak memory 209320 kb
Host smart-2fb98d5e-c1d9-47ea-bd7b-18794a285577
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2622113367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.2622113367
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1513978968
Short name T500
Test name
Test status
Simulation time 8791125642 ps
CPU time 267.37 seconds
Started Mar 24 01:24:16 PM PDT 24
Finished Mar 24 01:28:44 PM PDT 24
Peak memory 220028 kb
Host smart-c4f55e2f-6cc3-4759-a90a-9b1f5bf8dc84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513978968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.1513978968
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1445773472
Short name T226
Test name
Test status
Simulation time 748714938 ps
CPU time 11.22 seconds
Started Mar 24 01:24:15 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 204952 kb
Host smart-8268ed06-b837-480c-8725-ac50dd1fc500
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1445773472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1445773472
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3224707829
Short name T273
Test name
Test status
Simulation time 577227103 ps
CPU time 32.53 seconds
Started Mar 24 01:24:22 PM PDT 24
Finished Mar 24 01:24:55 PM PDT 24
Peak memory 206000 kb
Host smart-63ede32d-1006-445e-888d-9aaf91c773f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3224707829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3224707829
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1048470985
Short name T594
Test name
Test status
Simulation time 74316511988 ps
CPU time 496.99 seconds
Started Mar 24 01:24:22 PM PDT 24
Finished Mar 24 01:32:39 PM PDT 24
Peak memory 206024 kb
Host smart-9eba1818-a0a6-4da5-8c09-ff82801dd816
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1048470985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.1048470985
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.826099663
Short name T660
Test name
Test status
Simulation time 132746184 ps
CPU time 11.65 seconds
Started Mar 24 01:24:24 PM PDT 24
Finished Mar 24 01:24:36 PM PDT 24
Peak memory 203808 kb
Host smart-1132398e-6143-41c9-a88d-b87cd69f02d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=826099663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.826099663
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.1772030460
Short name T397
Test name
Test status
Simulation time 100427632 ps
CPU time 2.67 seconds
Started Mar 24 01:24:22 PM PDT 24
Finished Mar 24 01:24:25 PM PDT 24
Peak memory 203480 kb
Host smart-ca6ad38d-67ed-43b6-8891-dd8160102943
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1772030460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1772030460
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.530799287
Short name T661
Test name
Test status
Simulation time 476111828 ps
CPU time 16.93 seconds
Started Mar 24 01:24:15 PM PDT 24
Finished Mar 24 01:24:33 PM PDT 24
Peak memory 211648 kb
Host smart-8abb779f-6e75-4c8d-91ba-70c6d066eb3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=530799287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.530799287
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2026549099
Short name T689
Test name
Test status
Simulation time 77843659088 ps
CPU time 206.53 seconds
Started Mar 24 01:24:16 PM PDT 24
Finished Mar 24 01:27:42 PM PDT 24
Peak memory 205272 kb
Host smart-ccf8a6b8-f3f2-4754-8097-a1d7b92b7d8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026549099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2026549099
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3131133820
Short name T209
Test name
Test status
Simulation time 73922025835 ps
CPU time 267.91 seconds
Started Mar 24 01:24:22 PM PDT 24
Finished Mar 24 01:28:50 PM PDT 24
Peak memory 204808 kb
Host smart-4e23b5d4-c4d2-42a5-8c6a-97dd7c451b22
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3131133820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3131133820
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1256598292
Short name T394
Test name
Test status
Simulation time 236179895 ps
CPU time 17.55 seconds
Started Mar 24 01:24:17 PM PDT 24
Finished Mar 24 01:24:34 PM PDT 24
Peak memory 204588 kb
Host smart-74f9b7d2-675c-4e3a-b620-1ca8d4a51c59
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256598292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1256598292
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.1842544570
Short name T437
Test name
Test status
Simulation time 269117967 ps
CPU time 20.59 seconds
Started Mar 24 01:24:21 PM PDT 24
Finished Mar 24 01:24:43 PM PDT 24
Peak memory 203524 kb
Host smart-b6765dbd-9a0f-456a-bb14-59d05ea3d672
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1842544570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1842544570
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.258807524
Short name T58
Test name
Test status
Simulation time 151691083 ps
CPU time 3.85 seconds
Started Mar 24 01:24:19 PM PDT 24
Finished Mar 24 01:24:23 PM PDT 24
Peak memory 203456 kb
Host smart-1ce91481-9bbf-425c-8cab-f04552e8155f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=258807524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.258807524
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3134542046
Short name T506
Test name
Test status
Simulation time 10308531454 ps
CPU time 24.64 seconds
Started Mar 24 01:24:18 PM PDT 24
Finished Mar 24 01:24:43 PM PDT 24
Peak memory 203568 kb
Host smart-094f4634-a0d9-401d-a63b-2c4d37f33dae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134542046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3134542046
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.959226475
Short name T842
Test name
Test status
Simulation time 2512314021 ps
CPU time 23.83 seconds
Started Mar 24 01:24:18 PM PDT 24
Finished Mar 24 01:24:41 PM PDT 24
Peak memory 203572 kb
Host smart-d986a3a6-b701-4df9-a03c-437228e4118f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=959226475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.959226475
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4264009035
Short name T858
Test name
Test status
Simulation time 59537565 ps
CPU time 2.38 seconds
Started Mar 24 01:24:18 PM PDT 24
Finished Mar 24 01:24:20 PM PDT 24
Peak memory 203396 kb
Host smart-12cb0b07-b257-4672-adce-dfeaa4621194
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264009035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.4264009035
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1030195474
Short name T129
Test name
Test status
Simulation time 1958888497 ps
CPU time 71.26 seconds
Started Mar 24 01:24:21 PM PDT 24
Finished Mar 24 01:25:33 PM PDT 24
Peak memory 206044 kb
Host smart-c7aa002f-52d2-4afa-846e-a7c214308b1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1030195474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1030195474
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.512147001
Short name T492
Test name
Test status
Simulation time 6510248172 ps
CPU time 99.38 seconds
Started Mar 24 01:24:23 PM PDT 24
Finished Mar 24 01:26:02 PM PDT 24
Peak memory 207392 kb
Host smart-c01e1f7d-0d2e-4d40-85cd-6ee5a100a072
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=512147001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.512147001
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2844436252
Short name T36
Test name
Test status
Simulation time 1288210765 ps
CPU time 327.35 seconds
Started Mar 24 01:24:20 PM PDT 24
Finished Mar 24 01:29:47 PM PDT 24
Peak memory 208644 kb
Host smart-c7df4bd0-7de0-49ae-a593-7a536e6f5945
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2844436252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.2844436252
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3529714398
Short name T485
Test name
Test status
Simulation time 3815486637 ps
CPU time 206.38 seconds
Started Mar 24 01:24:21 PM PDT 24
Finished Mar 24 01:27:48 PM PDT 24
Peak memory 219956 kb
Host smart-7e95b9fb-074a-417e-b2b2-0b0e5aca7a16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3529714398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.3529714398
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1048014954
Short name T819
Test name
Test status
Simulation time 392757066 ps
CPU time 21.68 seconds
Started Mar 24 01:24:20 PM PDT 24
Finished Mar 24 01:24:43 PM PDT 24
Peak memory 205192 kb
Host smart-372166d7-449a-47c8-9044-29dece691894
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1048014954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1048014954
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2013548959
Short name T898
Test name
Test status
Simulation time 6678706866 ps
CPU time 44.01 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:25:13 PM PDT 24
Peak memory 211744 kb
Host smart-3b36fc2d-af9c-4165-b5df-f4019447fb5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2013548959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2013548959
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.211629565
Short name T603
Test name
Test status
Simulation time 182873631 ps
CPU time 15.64 seconds
Started Mar 24 01:24:29 PM PDT 24
Finished Mar 24 01:24:45 PM PDT 24
Peak memory 204016 kb
Host smart-2fcc3a5d-e922-42be-81d4-b7bdce8b3202
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=211629565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.211629565
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.435228931
Short name T180
Test name
Test status
Simulation time 191749495 ps
CPU time 17.08 seconds
Started Mar 24 01:24:26 PM PDT 24
Finished Mar 24 01:24:43 PM PDT 24
Peak memory 203484 kb
Host smart-4eb232b0-ad79-42df-8b76-03903054a44e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=435228931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.435228931
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.1325498097
Short name T118
Test name
Test status
Simulation time 1049414948 ps
CPU time 26.71 seconds
Started Mar 24 01:24:27 PM PDT 24
Finished Mar 24 01:24:55 PM PDT 24
Peak memory 204496 kb
Host smart-4e2e1a46-ae8a-4220-a9cb-ae772585d5ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1325498097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1325498097
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1779336882
Short name T833
Test name
Test status
Simulation time 38514536954 ps
CPU time 124.32 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:26:33 PM PDT 24
Peak memory 205288 kb
Host smart-2e6901f6-dab6-48ef-ab52-b7377aa3d9cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779336882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1779336882
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.832123466
Short name T820
Test name
Test status
Simulation time 1674782298 ps
CPU time 11.03 seconds
Started Mar 24 01:24:29 PM PDT 24
Finished Mar 24 01:24:40 PM PDT 24
Peak memory 203516 kb
Host smart-23a6b181-0513-42c6-8d6e-ba5ba756f252
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=832123466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.832123466
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2618286080
Short name T658
Test name
Test status
Simulation time 152637257 ps
CPU time 20.25 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:24:48 PM PDT 24
Peak memory 205108 kb
Host smart-26ec456b-ab8b-40ee-8d44-e73b9bf7a81a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618286080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2618286080
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.3910421330
Short name T19
Test name
Test status
Simulation time 75899350 ps
CPU time 7.35 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:24:36 PM PDT 24
Peak memory 203756 kb
Host smart-de1164f8-4d9a-4253-bc82-1b0748a8bf48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3910421330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3910421330
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.2421896349
Short name T644
Test name
Test status
Simulation time 317681614 ps
CPU time 3.64 seconds
Started Mar 24 01:24:21 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 203468 kb
Host smart-8b723bd6-8abb-4b81-ab76-61b190dd1189
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2421896349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2421896349
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1578643715
Short name T323
Test name
Test status
Simulation time 10503328683 ps
CPU time 28.29 seconds
Started Mar 24 01:24:27 PM PDT 24
Finished Mar 24 01:24:55 PM PDT 24
Peak memory 203792 kb
Host smart-98e362f7-0ad3-4804-a0bd-945ddee7f806
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578643715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1578643715
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1457923176
Short name T859
Test name
Test status
Simulation time 3390830534 ps
CPU time 23.69 seconds
Started Mar 24 01:24:29 PM PDT 24
Finished Mar 24 01:24:53 PM PDT 24
Peak memory 203564 kb
Host smart-5fb5244f-e16a-4b96-9c99-9c320e5a6236
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1457923176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1457923176
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3826813894
Short name T569
Test name
Test status
Simulation time 26921228 ps
CPU time 2.17 seconds
Started Mar 24 01:24:20 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 203520 kb
Host smart-a0b0e908-20f8-442d-9eb6-772431166020
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826813894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3826813894
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.638647857
Short name T482
Test name
Test status
Simulation time 9375317342 ps
CPU time 87.51 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:25:56 PM PDT 24
Peak memory 208096 kb
Host smart-7538624c-d7be-49d4-a0da-da3d1121b8e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=638647857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.638647857
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1451240456
Short name T415
Test name
Test status
Simulation time 1432986832 ps
CPU time 49.53 seconds
Started Mar 24 01:24:29 PM PDT 24
Finished Mar 24 01:25:19 PM PDT 24
Peak memory 205312 kb
Host smart-274a1eaa-4b33-48fe-a23a-c1c13d3b3272
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1451240456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1451240456
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.190935404
Short name T618
Test name
Test status
Simulation time 1954683793 ps
CPU time 392.61 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:31:01 PM PDT 24
Peak memory 219888 kb
Host smart-58cfe5c9-79c6-4e1d-8cd8-2d06aeebe1b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=190935404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand
_reset.190935404
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.308731686
Short name T308
Test name
Test status
Simulation time 535262440 ps
CPU time 131.23 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:26:40 PM PDT 24
Peak memory 210336 kb
Host smart-106ec812-d94e-49d3-b4ac-3b74a6371da3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=308731686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res
et_error.308731686
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.601452935
Short name T264
Test name
Test status
Simulation time 664610093 ps
CPU time 29.52 seconds
Started Mar 24 01:24:27 PM PDT 24
Finished Mar 24 01:24:57 PM PDT 24
Peak memory 204892 kb
Host smart-3e2b66f7-f245-4f41-8bd5-3eb3a2e338c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=601452935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.601452935
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.599500554
Short name T289
Test name
Test status
Simulation time 915973626 ps
CPU time 25.66 seconds
Started Mar 24 01:24:30 PM PDT 24
Finished Mar 24 01:24:56 PM PDT 24
Peak memory 204376 kb
Host smart-f0c37f7e-4006-4d64-b8df-01344f1f11f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=599500554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.599500554
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.125494926
Short name T89
Test name
Test status
Simulation time 59062422602 ps
CPU time 595.43 seconds
Started Mar 24 01:24:31 PM PDT 24
Finished Mar 24 01:34:27 PM PDT 24
Peak memory 211728 kb
Host smart-57029c9e-9e1e-4eeb-92ec-d61e4882504f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=125494926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo
w_rsp.125494926
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.4263813479
Short name T617
Test name
Test status
Simulation time 385098827 ps
CPU time 6.09 seconds
Started Mar 24 01:24:32 PM PDT 24
Finished Mar 24 01:24:39 PM PDT 24
Peak memory 203480 kb
Host smart-e38359ca-1bd5-440e-90c5-7c0662a3636f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4263813479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.4263813479
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.2332067490
Short name T13
Test name
Test status
Simulation time 117533729 ps
CPU time 9.68 seconds
Started Mar 24 01:24:30 PM PDT 24
Finished Mar 24 01:24:40 PM PDT 24
Peak memory 203504 kb
Host smart-f8c3601b-a26b-4c43-a8f3-e02ceb21e752
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2332067490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2332067490
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.667129171
Short name T601
Test name
Test status
Simulation time 622868915 ps
CPU time 26.16 seconds
Started Mar 24 01:24:32 PM PDT 24
Finished Mar 24 01:24:58 PM PDT 24
Peak memory 204696 kb
Host smart-92aaf433-b42a-4fc3-b912-ebdf0461ae1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=667129171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.667129171
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1905902418
Short name T395
Test name
Test status
Simulation time 1949513990 ps
CPU time 10.69 seconds
Started Mar 24 01:24:31 PM PDT 24
Finished Mar 24 01:24:42 PM PDT 24
Peak memory 203472 kb
Host smart-a563ad58-9377-40f7-9133-68e4e1865fd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905902418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1905902418
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4010326466
Short name T251
Test name
Test status
Simulation time 17250134217 ps
CPU time 128.06 seconds
Started Mar 24 01:24:32 PM PDT 24
Finished Mar 24 01:26:41 PM PDT 24
Peak memory 211752 kb
Host smart-7e001fa1-b785-48a4-9dec-9321040d649d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4010326466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4010326466
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3646554593
Short name T291
Test name
Test status
Simulation time 60611779 ps
CPU time 3.08 seconds
Started Mar 24 01:24:31 PM PDT 24
Finished Mar 24 01:24:35 PM PDT 24
Peak memory 203524 kb
Host smart-6e96741f-c7b2-489e-bec8-55824031898f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646554593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3646554593
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.2148980539
Short name T364
Test name
Test status
Simulation time 614183762 ps
CPU time 14.79 seconds
Started Mar 24 01:24:31 PM PDT 24
Finished Mar 24 01:24:47 PM PDT 24
Peak memory 204068 kb
Host smart-3007fdf9-1008-42aa-b787-a6a30287f45e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2148980539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2148980539
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.3316627515
Short name T67
Test name
Test status
Simulation time 162290414 ps
CPU time 3.71 seconds
Started Mar 24 01:24:28 PM PDT 24
Finished Mar 24 01:24:32 PM PDT 24
Peak memory 203464 kb
Host smart-cb2a8c79-04c9-4735-bf81-a894d0a167c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3316627515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3316627515
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3719290650
Short name T637
Test name
Test status
Simulation time 10373241639 ps
CPU time 32.84 seconds
Started Mar 24 01:24:33 PM PDT 24
Finished Mar 24 01:25:06 PM PDT 24
Peak memory 203520 kb
Host smart-e28335aa-f2b6-46d5-8c67-3a854e393af9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719290650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3719290650
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3038986577
Short name T808
Test name
Test status
Simulation time 5882611961 ps
CPU time 23.56 seconds
Started Mar 24 01:24:30 PM PDT 24
Finished Mar 24 01:24:54 PM PDT 24
Peak memory 203544 kb
Host smart-ee514a63-226b-45c2-a79e-607e61848515
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3038986577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3038986577
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2818614887
Short name T366
Test name
Test status
Simulation time 27468489 ps
CPU time 2.31 seconds
Started Mar 24 01:24:27 PM PDT 24
Finished Mar 24 01:24:29 PM PDT 24
Peak memory 203516 kb
Host smart-47ac5d8c-f857-461b-9030-8b35a971f785
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818614887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2818614887
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3052413541
Short name T620
Test name
Test status
Simulation time 382496032 ps
CPU time 42.8 seconds
Started Mar 24 01:24:36 PM PDT 24
Finished Mar 24 01:25:19 PM PDT 24
Peak memory 206192 kb
Host smart-a76eba94-9f26-4df2-af37-6c7bee1ec08f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3052413541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3052413541
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.4174001336
Short name T830
Test name
Test status
Simulation time 419640362 ps
CPU time 144.8 seconds
Started Mar 24 01:24:36 PM PDT 24
Finished Mar 24 01:27:01 PM PDT 24
Peak memory 209684 kb
Host smart-3cfb142c-476d-4351-941f-1455a5c92af8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4174001336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.4174001336
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1468979355
Short name T853
Test name
Test status
Simulation time 692637112 ps
CPU time 158.59 seconds
Started Mar 24 01:24:36 PM PDT 24
Finished Mar 24 01:27:16 PM PDT 24
Peak memory 211648 kb
Host smart-f265b00b-e805-48e8-a514-04fef8131011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1468979355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1468979355
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1957197778
Short name T725
Test name
Test status
Simulation time 193134645 ps
CPU time 7.44 seconds
Started Mar 24 01:24:33 PM PDT 24
Finished Mar 24 01:24:41 PM PDT 24
Peak memory 204968 kb
Host smart-eaf8f2c8-95b3-4247-b529-49678c8f51bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1957197778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1957197778
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3446233523
Short name T158
Test name
Test status
Simulation time 892869745 ps
CPU time 35.42 seconds
Started Mar 24 01:24:41 PM PDT 24
Finished Mar 24 01:25:17 PM PDT 24
Peak memory 204924 kb
Host smart-c6aacb1e-7b79-457c-a77f-77af39495667
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3446233523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3446233523
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1467755127
Short name T599
Test name
Test status
Simulation time 65077016739 ps
CPU time 453.53 seconds
Started Mar 24 01:24:46 PM PDT 24
Finished Mar 24 01:32:19 PM PDT 24
Peak memory 206944 kb
Host smart-4d27a0f3-36f1-47a8-afa5-58012d3abb32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1467755127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.1467755127
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1889764209
Short name T567
Test name
Test status
Simulation time 1125604342 ps
CPU time 25.66 seconds
Started Mar 24 01:24:40 PM PDT 24
Finished Mar 24 01:25:07 PM PDT 24
Peak memory 204024 kb
Host smart-7835ef6c-de9c-4fe6-9a93-aed4d53162ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1889764209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1889764209
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.2777214639
Short name T626
Test name
Test status
Simulation time 1503326223 ps
CPU time 14.91 seconds
Started Mar 24 01:24:43 PM PDT 24
Finished Mar 24 01:24:58 PM PDT 24
Peak memory 203472 kb
Host smart-a4ee1af4-1f48-4523-9b3c-addcf2375b90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2777214639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2777214639
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.2135320639
Short name T647
Test name
Test status
Simulation time 217045481 ps
CPU time 25.33 seconds
Started Mar 24 01:24:37 PM PDT 24
Finished Mar 24 01:25:03 PM PDT 24
Peak memory 211684 kb
Host smart-9e83f084-9b59-40c0-aa8e-9585c9345fba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2135320639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2135320639
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.202077861
Short name T204
Test name
Test status
Simulation time 11225194689 ps
CPU time 47.05 seconds
Started Mar 24 01:24:42 PM PDT 24
Finished Mar 24 01:25:29 PM PDT 24
Peak memory 204824 kb
Host smart-5823170a-d4aa-457f-9788-a6b11b014011
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=202077861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.202077861
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3101897763
Short name T43
Test name
Test status
Simulation time 8691496743 ps
CPU time 63.73 seconds
Started Mar 24 01:24:43 PM PDT 24
Finished Mar 24 01:25:47 PM PDT 24
Peak memory 204844 kb
Host smart-5f5ec191-86bd-4a38-99ac-cb395b61536d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3101897763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3101897763
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1324795510
Short name T352
Test name
Test status
Simulation time 36571194 ps
CPU time 2.41 seconds
Started Mar 24 01:24:40 PM PDT 24
Finished Mar 24 01:24:43 PM PDT 24
Peak memory 203480 kb
Host smart-da2c4288-d99a-4dac-aa7e-b0d80413214c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324795510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1324795510
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.2156690942
Short name T31
Test name
Test status
Simulation time 1211345409 ps
CPU time 12.81 seconds
Started Mar 24 01:24:43 PM PDT 24
Finished Mar 24 01:24:56 PM PDT 24
Peak memory 204080 kb
Host smart-35a00dfe-7f01-43a8-a8a5-cd6b421a29f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2156690942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2156690942
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.3952900930
Short name T472
Test name
Test status
Simulation time 132980163 ps
CPU time 2.44 seconds
Started Mar 24 01:24:34 PM PDT 24
Finished Mar 24 01:24:37 PM PDT 24
Peak memory 203436 kb
Host smart-80c67532-152c-43d8-a15d-54844f2be74f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3952900930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3952900930
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2529868055
Short name T248
Test name
Test status
Simulation time 5035769932 ps
CPU time 31.6 seconds
Started Mar 24 01:24:35 PM PDT 24
Finished Mar 24 01:25:07 PM PDT 24
Peak memory 203560 kb
Host smart-be2562fe-e0c3-450d-96fe-e24da6c1ddab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529868055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2529868055
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1997991136
Short name T735
Test name
Test status
Simulation time 10253483372 ps
CPU time 28 seconds
Started Mar 24 01:24:35 PM PDT 24
Finished Mar 24 01:25:03 PM PDT 24
Peak memory 203544 kb
Host smart-07b6bd11-cdda-4d1e-b84e-fcb3a5326770
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1997991136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1997991136
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3316854192
Short name T235
Test name
Test status
Simulation time 29635830 ps
CPU time 2.67 seconds
Started Mar 24 01:24:36 PM PDT 24
Finished Mar 24 01:24:39 PM PDT 24
Peak memory 203500 kb
Host smart-2aee1493-17b0-484e-985b-f0beb387788f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316854192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3316854192
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.109439243
Short name T123
Test name
Test status
Simulation time 6036735945 ps
CPU time 256.68 seconds
Started Mar 24 01:24:41 PM PDT 24
Finished Mar 24 01:28:58 PM PDT 24
Peak memory 209432 kb
Host smart-f2146861-0384-437a-b4f0-84a7720bdffa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109439243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.109439243
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3729891316
Short name T201
Test name
Test status
Simulation time 7410786803 ps
CPU time 134.2 seconds
Started Mar 24 01:24:43 PM PDT 24
Finished Mar 24 01:26:57 PM PDT 24
Peak memory 208160 kb
Host smart-0cddc693-24d1-4161-9655-05ca1fd476f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3729891316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3729891316
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3861584240
Short name T104
Test name
Test status
Simulation time 150937126 ps
CPU time 50.24 seconds
Started Mar 24 01:24:43 PM PDT 24
Finished Mar 24 01:25:33 PM PDT 24
Peak memory 206944 kb
Host smart-ac0cebeb-ce63-459c-b3a6-12f3b1c74379
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3861584240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.3861584240
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3163172901
Short name T37
Test name
Test status
Simulation time 1858832950 ps
CPU time 197.74 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:28:03 PM PDT 24
Peak memory 211520 kb
Host smart-f447a0bc-90dc-4f6c-9bf3-e6baf1c49b77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3163172901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.3163172901
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1702067122
Short name T403
Test name
Test status
Simulation time 88407791 ps
CPU time 12.14 seconds
Started Mar 24 01:24:43 PM PDT 24
Finished Mar 24 01:24:56 PM PDT 24
Peak memory 204904 kb
Host smart-69c821fd-bd52-41af-9ee6-5e5cd60cad0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1702067122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1702067122
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3337920556
Short name T413
Test name
Test status
Simulation time 656062201 ps
CPU time 22.06 seconds
Started Mar 24 01:24:46 PM PDT 24
Finished Mar 24 01:25:08 PM PDT 24
Peak memory 204592 kb
Host smart-4e93b21c-219d-4b0e-b5f9-108b4da74598
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3337920556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3337920556
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1159057084
Short name T714
Test name
Test status
Simulation time 67934569 ps
CPU time 2.12 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:24:47 PM PDT 24
Peak memory 203500 kb
Host smart-8647b942-9c0b-4149-94fc-82e7d4128af8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1159057084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1159057084
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.3042935054
Short name T576
Test name
Test status
Simulation time 1092238824 ps
CPU time 31.72 seconds
Started Mar 24 01:24:44 PM PDT 24
Finished Mar 24 01:25:16 PM PDT 24
Peak memory 203484 kb
Host smart-6115497e-8e2d-4000-82f9-af1b548443b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3042935054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3042935054
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.3423868307
Short name T873
Test name
Test status
Simulation time 3246840708 ps
CPU time 40.28 seconds
Started Mar 24 01:24:44 PM PDT 24
Finished Mar 24 01:25:24 PM PDT 24
Peak memory 205272 kb
Host smart-4f298f96-3558-41b9-926d-60790fdbc20f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3423868307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3423868307
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1204787603
Short name T677
Test name
Test status
Simulation time 34218917962 ps
CPU time 170.54 seconds
Started Mar 24 01:24:42 PM PDT 24
Finished Mar 24 01:27:33 PM PDT 24
Peak memory 205124 kb
Host smart-d6ff6a0c-bddb-457b-938f-287d9f983490
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204787603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1204787603
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2061196049
Short name T439
Test name
Test status
Simulation time 47541907037 ps
CPU time 102.48 seconds
Started Mar 24 01:24:40 PM PDT 24
Finished Mar 24 01:26:23 PM PDT 24
Peak memory 204848 kb
Host smart-77d8af20-e375-47b6-9cba-0a92bdf899ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2061196049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2061196049
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.4236999622
Short name T365
Test name
Test status
Simulation time 231900355 ps
CPU time 23.41 seconds
Started Mar 24 01:24:41 PM PDT 24
Finished Mar 24 01:25:05 PM PDT 24
Peak memory 204832 kb
Host smart-15c560c4-c6c7-4048-a39c-d5facc9fed9a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236999622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.4236999622
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.2787469759
Short name T239
Test name
Test status
Simulation time 1303217968 ps
CPU time 20.98 seconds
Started Mar 24 01:24:46 PM PDT 24
Finished Mar 24 01:25:07 PM PDT 24
Peak memory 203508 kb
Host smart-0874c06d-e31d-4458-bdbb-c0c784d1c7eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2787469759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2787469759
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.3978562808
Short name T69
Test name
Test status
Simulation time 24754299 ps
CPU time 2.47 seconds
Started Mar 24 01:24:43 PM PDT 24
Finished Mar 24 01:24:46 PM PDT 24
Peak memory 203456 kb
Host smart-229b76dc-c652-4a2b-a4fe-b4bfb4f4c773
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3978562808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3978562808
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2508709926
Short name T168
Test name
Test status
Simulation time 30257610632 ps
CPU time 42.57 seconds
Started Mar 24 01:24:42 PM PDT 24
Finished Mar 24 01:25:25 PM PDT 24
Peak memory 203552 kb
Host smart-2a15115b-bd58-4740-8af5-45f4ccd9f82e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508709926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2508709926
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1057495314
Short name T153
Test name
Test status
Simulation time 8424404405 ps
CPU time 31.87 seconds
Started Mar 24 01:24:42 PM PDT 24
Finished Mar 24 01:25:15 PM PDT 24
Peak memory 203584 kb
Host smart-f070583a-76f9-4d40-bb1b-af1386fdbad1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1057495314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1057495314
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1563409526
Short name T854
Test name
Test status
Simulation time 31655326 ps
CPU time 2.55 seconds
Started Mar 24 01:24:41 PM PDT 24
Finished Mar 24 01:24:44 PM PDT 24
Peak memory 203512 kb
Host smart-4df54791-9bef-4379-b27f-e95c11804cc3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563409526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1563409526
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.375079684
Short name T347
Test name
Test status
Simulation time 2925355765 ps
CPU time 120.23 seconds
Started Mar 24 01:24:47 PM PDT 24
Finished Mar 24 01:26:47 PM PDT 24
Peak memory 205972 kb
Host smart-b227acfe-350b-49ce-a08d-9ac55320e763
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=375079684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.375079684
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2526673746
Short name T493
Test name
Test status
Simulation time 6055777396 ps
CPU time 160.78 seconds
Started Mar 24 01:24:46 PM PDT 24
Finished Mar 24 01:27:27 PM PDT 24
Peak memory 209132 kb
Host smart-fd7cbe38-ee36-4c10-b3e7-b1fdf25ce257
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2526673746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2526673746
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4134796605
Short name T512
Test name
Test status
Simulation time 7723204 ps
CPU time 8.18 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:24:53 PM PDT 24
Peak memory 203380 kb
Host smart-a5cbd0c7-5069-4c4f-a276-a966a1b8d788
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4134796605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.4134796605
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3102414341
Short name T710
Test name
Test status
Simulation time 14412825375 ps
CPU time 304.23 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:29:50 PM PDT 24
Peak memory 220040 kb
Host smart-de63062d-19ef-472f-817a-4a23c82ae259
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3102414341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.3102414341
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2847038215
Short name T154
Test name
Test status
Simulation time 60272039 ps
CPU time 3.28 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:24:49 PM PDT 24
Peak memory 204536 kb
Host smart-c7491bd3-d434-44b2-97c9-100d6f44883a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2847038215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2847038215
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2662453654
Short name T157
Test name
Test status
Simulation time 1906560203 ps
CPU time 52.91 seconds
Started Mar 24 01:24:48 PM PDT 24
Finished Mar 24 01:25:41 PM PDT 24
Peak memory 206348 kb
Host smart-c3d19514-b5ca-437f-ac6a-b1e596427794
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2662453654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2662453654
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3472336472
Short name T424
Test name
Test status
Simulation time 3220772089 ps
CPU time 27.04 seconds
Started Mar 24 01:24:51 PM PDT 24
Finished Mar 24 01:25:18 PM PDT 24
Peak memory 203924 kb
Host smart-62ed9ec4-4c0e-42ef-a943-bfce6fc67db7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3472336472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3472336472
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.3510749651
Short name T328
Test name
Test status
Simulation time 230702815 ps
CPU time 25.71 seconds
Started Mar 24 01:24:51 PM PDT 24
Finished Mar 24 01:25:17 PM PDT 24
Peak memory 203688 kb
Host smart-cd14ed00-4ecd-461d-9f97-367c59a09bc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3510749651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3510749651
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.740821928
Short name T685
Test name
Test status
Simulation time 698291438 ps
CPU time 20.88 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:25:06 PM PDT 24
Peak memory 204576 kb
Host smart-aa085b33-9102-478a-87d5-509e5ff672fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=740821928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.740821928
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.490244226
Short name T281
Test name
Test status
Simulation time 20086585300 ps
CPU time 63.87 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:25:49 PM PDT 24
Peak memory 204732 kb
Host smart-21a9fbd3-cd4f-472c-a443-5e27aa5a5e71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=490244226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.490244226
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.201185357
Short name T383
Test name
Test status
Simulation time 15253586835 ps
CPU time 146.43 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:27:11 PM PDT 24
Peak memory 204940 kb
Host smart-f00266ca-4686-4292-a9c9-4a2159202d6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=201185357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.201185357
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1328417872
Short name T888
Test name
Test status
Simulation time 210612951 ps
CPU time 26.23 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:25:12 PM PDT 24
Peak memory 204820 kb
Host smart-459e3393-928a-41e1-be13-2be310bd80c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328417872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1328417872
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.3009373044
Short name T701
Test name
Test status
Simulation time 1640962112 ps
CPU time 11.25 seconds
Started Mar 24 01:24:50 PM PDT 24
Finished Mar 24 01:25:01 PM PDT 24
Peak memory 203488 kb
Host smart-13ff66bf-3edb-4e5c-b5f6-086759bec7d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3009373044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3009373044
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.2657651376
Short name T509
Test name
Test status
Simulation time 25798649 ps
CPU time 2.09 seconds
Started Mar 24 01:24:46 PM PDT 24
Finished Mar 24 01:24:48 PM PDT 24
Peak memory 203448 kb
Host smart-d86bc35a-ae80-4df3-82cc-412712e933cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2657651376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2657651376
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1190544203
Short name T387
Test name
Test status
Simulation time 28220021463 ps
CPU time 35.85 seconds
Started Mar 24 01:24:46 PM PDT 24
Finished Mar 24 01:25:22 PM PDT 24
Peak memory 203580 kb
Host smart-df4bce48-c261-4129-9729-1658c4653186
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190544203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1190544203
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1078799528
Short name T61
Test name
Test status
Simulation time 3376894888 ps
CPU time 28.84 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:25:14 PM PDT 24
Peak memory 203488 kb
Host smart-df626dad-0035-4e4b-ad5f-09a72d728492
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1078799528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1078799528
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3748367609
Short name T422
Test name
Test status
Simulation time 31676472 ps
CPU time 2.4 seconds
Started Mar 24 01:24:45 PM PDT 24
Finished Mar 24 01:24:48 PM PDT 24
Peak memory 203520 kb
Host smart-2a93eb12-660d-4178-953d-1cd4cf1c6c49
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748367609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3748367609
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1163526969
Short name T559
Test name
Test status
Simulation time 342982615 ps
CPU time 40.66 seconds
Started Mar 24 01:24:55 PM PDT 24
Finished Mar 24 01:25:35 PM PDT 24
Peak memory 205812 kb
Host smart-8ab73a09-e982-43d6-a8d7-ddf4bf28965f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1163526969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1163526969
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2034894257
Short name T812
Test name
Test status
Simulation time 767273638 ps
CPU time 31.09 seconds
Started Mar 24 01:24:52 PM PDT 24
Finished Mar 24 01:25:23 PM PDT 24
Peak memory 205016 kb
Host smart-d599a891-4548-42a0-bb25-6906bee3ecf4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2034894257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2034894257
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2952467528
Short name T267
Test name
Test status
Simulation time 605692051 ps
CPU time 178.4 seconds
Started Mar 24 01:24:50 PM PDT 24
Finished Mar 24 01:27:48 PM PDT 24
Peak memory 208584 kb
Host smart-18e5568f-d7f3-46a8-ac91-810d2099b1ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2952467528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.2952467528
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2575128268
Short name T664
Test name
Test status
Simulation time 5332381950 ps
CPU time 246.08 seconds
Started Mar 24 01:24:52 PM PDT 24
Finished Mar 24 01:28:58 PM PDT 24
Peak memory 211572 kb
Host smart-768e291a-994f-4670-ae99-da75da1ce49f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2575128268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.2575128268
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.3472937321
Short name T407
Test name
Test status
Simulation time 62767322 ps
CPU time 11.6 seconds
Started Mar 24 01:24:50 PM PDT 24
Finished Mar 24 01:25:02 PM PDT 24
Peak memory 205108 kb
Host smart-69a65109-7b84-4b5d-a32c-45d4b846a2fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3472937321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3472937321
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.159373760
Short name T455
Test name
Test status
Simulation time 1382484689 ps
CPU time 25.22 seconds
Started Mar 24 01:24:56 PM PDT 24
Finished Mar 24 01:25:21 PM PDT 24
Peak memory 204608 kb
Host smart-ef7bf02c-94cc-4373-ab54-3d85831eb108
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=159373760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.159373760
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.748896146
Short name T855
Test name
Test status
Simulation time 160473518096 ps
CPU time 761.64 seconds
Started Mar 24 01:24:59 PM PDT 24
Finished Mar 24 01:37:41 PM PDT 24
Peak memory 206096 kb
Host smart-3bfc0730-0d82-4578-9e71-91ddb8b1191e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=748896146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo
w_rsp.748896146
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2939424645
Short name T884
Test name
Test status
Simulation time 101256877 ps
CPU time 4 seconds
Started Mar 24 01:24:56 PM PDT 24
Finished Mar 24 01:25:00 PM PDT 24
Peak memory 203476 kb
Host smart-00f4634f-5271-4b4c-b5b3-86b93983da8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2939424645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2939424645
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.3286030608
Short name T770
Test name
Test status
Simulation time 1268356613 ps
CPU time 21.94 seconds
Started Mar 24 01:24:56 PM PDT 24
Finished Mar 24 01:25:18 PM PDT 24
Peak memory 203416 kb
Host smart-5152d588-a4c8-477b-bfeb-3b84bb64e2df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3286030608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3286030608
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.2996107544
Short name T396
Test name
Test status
Simulation time 4455815026 ps
CPU time 43.76 seconds
Started Mar 24 01:24:51 PM PDT 24
Finished Mar 24 01:25:35 PM PDT 24
Peak memory 205292 kb
Host smart-c32e9793-57f8-4dfb-b76d-da9c7671fa09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2996107544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2996107544
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.2268576498
Short name T720
Test name
Test status
Simulation time 5273265055 ps
CPU time 33.37 seconds
Started Mar 24 01:24:54 PM PDT 24
Finished Mar 24 01:25:28 PM PDT 24
Peak memory 204860 kb
Host smart-03703b0b-a01c-42ba-85dd-e4d861e3b265
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268576498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2268576498
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1351489870
Short name T430
Test name
Test status
Simulation time 16580153456 ps
CPU time 110.65 seconds
Started Mar 24 01:24:56 PM PDT 24
Finished Mar 24 01:26:46 PM PDT 24
Peak memory 205088 kb
Host smart-dbe53ca3-a481-49f8-81f0-47aafe5d042f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1351489870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1351489870
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1190211962
Short name T461
Test name
Test status
Simulation time 185136077 ps
CPU time 23.37 seconds
Started Mar 24 01:24:51 PM PDT 24
Finished Mar 24 01:25:14 PM PDT 24
Peak memory 205088 kb
Host smart-fbe1418f-a2f7-4286-b98e-91e0d351d2ed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190211962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1190211962
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.245072686
Short name T786
Test name
Test status
Simulation time 96370509 ps
CPU time 3.75 seconds
Started Mar 24 01:24:58 PM PDT 24
Finished Mar 24 01:25:02 PM PDT 24
Peak memory 203560 kb
Host smart-4db07c28-4240-46cc-939e-490e015014dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=245072686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.245072686
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.72840545
Short name T556
Test name
Test status
Simulation time 137876872 ps
CPU time 3.49 seconds
Started Mar 24 01:24:50 PM PDT 24
Finished Mar 24 01:24:54 PM PDT 24
Peak memory 203508 kb
Host smart-ce0b75f0-281a-42df-9439-17c1d6bd1f1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72840545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.72840545
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.328567982
Short name T438
Test name
Test status
Simulation time 6255882358 ps
CPU time 35.68 seconds
Started Mar 24 01:24:50 PM PDT 24
Finished Mar 24 01:25:25 PM PDT 24
Peak memory 203560 kb
Host smart-1e900623-c3cc-432b-ad46-9effe07a5743
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=328567982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.328567982
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3483425053
Short name T759
Test name
Test status
Simulation time 6073680308 ps
CPU time 31.56 seconds
Started Mar 24 01:24:52 PM PDT 24
Finished Mar 24 01:25:23 PM PDT 24
Peak memory 203556 kb
Host smart-97254efd-b300-4fb4-b3cb-fe02024e119d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3483425053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3483425053
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3309155096
Short name T2
Test name
Test status
Simulation time 100163570 ps
CPU time 2.2 seconds
Started Mar 24 01:24:50 PM PDT 24
Finished Mar 24 01:24:52 PM PDT 24
Peak memory 203508 kb
Host smart-ea4b90a7-fa79-4ad6-9af4-d5f0e0f34b7d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309155096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3309155096
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.371184279
Short name T625
Test name
Test status
Simulation time 4490407427 ps
CPU time 132.3 seconds
Started Mar 24 01:24:54 PM PDT 24
Finished Mar 24 01:27:07 PM PDT 24
Peak memory 207364 kb
Host smart-d148593d-2a87-4801-a458-15bc018baf1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=371184279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.371184279
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2112494561
Short name T29
Test name
Test status
Simulation time 6054142235 ps
CPU time 137.28 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:27:17 PM PDT 24
Peak memory 211748 kb
Host smart-59213a0e-d005-406f-b25b-615982a847ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2112494561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2112494561
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.519494687
Short name T33
Test name
Test status
Simulation time 269386798 ps
CPU time 103.96 seconds
Started Mar 24 01:24:55 PM PDT 24
Finished Mar 24 01:26:39 PM PDT 24
Peak memory 208108 kb
Host smart-ae34d7aa-4687-4a24-b6c5-a256ee3f9fc8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=519494687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand
_reset.519494687
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2555391108
Short name T763
Test name
Test status
Simulation time 459059247 ps
CPU time 115.73 seconds
Started Mar 24 01:24:57 PM PDT 24
Finished Mar 24 01:26:53 PM PDT 24
Peak memory 209840 kb
Host smart-8722e98f-4ca5-4aaf-8ea4-f2c3d9d2341a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2555391108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.2555391108
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2569145418
Short name T271
Test name
Test status
Simulation time 170357460 ps
CPU time 23.27 seconds
Started Mar 24 01:24:57 PM PDT 24
Finished Mar 24 01:25:20 PM PDT 24
Peak memory 205612 kb
Host smart-684c395d-539e-4a63-a5b0-f4de2d32fbc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2569145418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2569145418
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1329513102
Short name T106
Test name
Test status
Simulation time 5212728464 ps
CPU time 43.4 seconds
Started Mar 24 01:25:07 PM PDT 24
Finished Mar 24 01:25:51 PM PDT 24
Peak memory 211776 kb
Host smart-aba11f7a-ee5c-41c0-8c52-f6b2d01cc05c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1329513102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1329513102
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2983769719
Short name T6
Test name
Test status
Simulation time 68923859100 ps
CPU time 554.89 seconds
Started Mar 24 01:24:57 PM PDT 24
Finished Mar 24 01:34:12 PM PDT 24
Peak memory 207300 kb
Host smart-4e7a9064-a3c1-4d48-8c97-1cb733993b86
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2983769719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2983769719
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3641600104
Short name T740
Test name
Test status
Simulation time 130463499 ps
CPU time 9.93 seconds
Started Mar 24 01:25:01 PM PDT 24
Finished Mar 24 01:25:11 PM PDT 24
Peak memory 203508 kb
Host smart-ded5cdd4-27fb-4f87-8208-884cdb3c03b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3641600104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3641600104
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.1004028963
Short name T629
Test name
Test status
Simulation time 970944882 ps
CPU time 15.71 seconds
Started Mar 24 01:24:59 PM PDT 24
Finished Mar 24 01:25:15 PM PDT 24
Peak memory 203464 kb
Host smart-32671f3f-ec0b-44a9-b308-322ac1bc6e39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1004028963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1004028963
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.879748359
Short name T746
Test name
Test status
Simulation time 7108401964 ps
CPU time 47.34 seconds
Started Mar 24 01:24:55 PM PDT 24
Finished Mar 24 01:25:42 PM PDT 24
Peak memory 204772 kb
Host smart-d81fc580-6feb-4614-a4e9-6d8791372a25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=879748359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.879748359
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.488296617
Short name T616
Test name
Test status
Simulation time 46587659080 ps
CPU time 258.27 seconds
Started Mar 24 01:24:56 PM PDT 24
Finished Mar 24 01:29:15 PM PDT 24
Peak memory 204636 kb
Host smart-fb57f9b6-8f7e-451a-831d-85a694236f3e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=488296617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.488296617
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.679761720
Short name T137
Test name
Test status
Simulation time 13565812056 ps
CPU time 110.48 seconds
Started Mar 24 01:24:55 PM PDT 24
Finished Mar 24 01:26:46 PM PDT 24
Peak memory 204696 kb
Host smart-9afc4d6a-23bd-41cc-8464-4efbfcacf7e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=679761720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.679761720
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2968466382
Short name T776
Test name
Test status
Simulation time 818023545 ps
CPU time 20.43 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:25:20 PM PDT 24
Peak memory 204644 kb
Host smart-fa22228b-dc8a-4f92-ab5c-1c21c60fb545
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968466382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2968466382
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.736914625
Short name T801
Test name
Test status
Simulation time 494486376 ps
CPU time 6.93 seconds
Started Mar 24 01:25:02 PM PDT 24
Finished Mar 24 01:25:09 PM PDT 24
Peak memory 203484 kb
Host smart-119a94af-2dab-4666-b1b0-889e8a8c8796
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=736914625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.736914625
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.1003426209
Short name T862
Test name
Test status
Simulation time 190108021 ps
CPU time 3.25 seconds
Started Mar 24 01:24:57 PM PDT 24
Finished Mar 24 01:25:00 PM PDT 24
Peak memory 203460 kb
Host smart-63057b89-8101-44e1-aab2-b02a92848b6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1003426209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1003426209
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3243062386
Short name T818
Test name
Test status
Simulation time 6988390095 ps
CPU time 32.95 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:25:33 PM PDT 24
Peak memory 203596 kb
Host smart-d9aff076-e57f-4139-9691-96ad313eed15
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243062386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3243062386
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.139944130
Short name T211
Test name
Test status
Simulation time 6044200563 ps
CPU time 28.59 seconds
Started Mar 24 01:24:56 PM PDT 24
Finished Mar 24 01:25:25 PM PDT 24
Peak memory 203564 kb
Host smart-20e33dc8-3d8b-4544-a0b5-6f58cbd59af5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=139944130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.139944130
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3283497272
Short name T514
Test name
Test status
Simulation time 166644462 ps
CPU time 2.3 seconds
Started Mar 24 01:24:56 PM PDT 24
Finished Mar 24 01:24:59 PM PDT 24
Peak memory 203488 kb
Host smart-5855ca09-5558-4c89-b108-6e0750960ad4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283497272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3283497272
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.277253596
Short name T88
Test name
Test status
Simulation time 8381651901 ps
CPU time 196.91 seconds
Started Mar 24 01:25:02 PM PDT 24
Finished Mar 24 01:28:19 PM PDT 24
Peak memory 207388 kb
Host smart-55523e7a-10e6-4f18-b387-4706d07a2bc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277253596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.277253596
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.500407201
Short name T525
Test name
Test status
Simulation time 6992642889 ps
CPU time 149.29 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:27:29 PM PDT 24
Peak memory 208100 kb
Host smart-93f7c8a6-dd6e-4774-be23-0761086c50bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=500407201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.500407201
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.577703544
Short name T311
Test name
Test status
Simulation time 199855553 ps
CPU time 84.19 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:26:24 PM PDT 24
Peak memory 206940 kb
Host smart-3455a994-7f29-4021-af2f-c51749fc8db3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=577703544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand
_reset.577703544
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4069038505
Short name T676
Test name
Test status
Simulation time 5825201343 ps
CPU time 422.57 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:32:02 PM PDT 24
Peak memory 219952 kb
Host smart-2f6cd361-78b5-4b43-82ef-0c3048d5f185
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4069038505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.4069038505
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3102958048
Short name T391
Test name
Test status
Simulation time 38171237 ps
CPU time 4.09 seconds
Started Mar 24 01:25:02 PM PDT 24
Finished Mar 24 01:25:06 PM PDT 24
Peak memory 211632 kb
Host smart-c9899894-708a-4c08-a15d-ab02280a25ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3102958048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3102958048
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.3867408747
Short name T259
Test name
Test status
Simulation time 2006999098 ps
CPU time 18.76 seconds
Started Mar 24 01:25:08 PM PDT 24
Finished Mar 24 01:25:26 PM PDT 24
Peak memory 211740 kb
Host smart-e7b05e43-15ad-4914-b1b4-69fedb91d4a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3867408747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3867408747
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2147592308
Short name T92
Test name
Test status
Simulation time 79004183624 ps
CPU time 546.86 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:34:07 PM PDT 24
Peak memory 211764 kb
Host smart-3238570b-e536-4f33-9e93-ebc687f8a3a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2147592308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.2147592308
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1291869974
Short name T332
Test name
Test status
Simulation time 145025821 ps
CPU time 2.4 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:25:02 PM PDT 24
Peak memory 203428 kb
Host smart-0dfc4705-92ef-4d4a-9c0a-3d595cbaf784
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1291869974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1291869974
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.3127501575
Short name T766
Test name
Test status
Simulation time 2801031893 ps
CPU time 23.43 seconds
Started Mar 24 01:24:59 PM PDT 24
Finished Mar 24 01:25:23 PM PDT 24
Peak memory 203548 kb
Host smart-9e705b74-e700-4c0a-9f31-f215fa66068d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3127501575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3127501575
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.744286313
Short name T781
Test name
Test status
Simulation time 318804925 ps
CPU time 12.1 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:25:12 PM PDT 24
Peak memory 204720 kb
Host smart-9c5730d6-f662-487a-87aa-dec95bf8ed1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=744286313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.744286313
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2798958567
Short name T806
Test name
Test status
Simulation time 24696431390 ps
CPU time 83.01 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:26:23 PM PDT 24
Peak memory 204988 kb
Host smart-2d79d588-b78b-4b34-97d2-08875b31a085
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798958567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2798958567
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.525629994
Short name T646
Test name
Test status
Simulation time 15264559538 ps
CPU time 72.01 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:26:12 PM PDT 24
Peak memory 211724 kb
Host smart-ba6468f9-9772-4c5b-af34-4b99e1d51526
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=525629994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.525629994
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.4283084598
Short name T255
Test name
Test status
Simulation time 597980221 ps
CPU time 24.1 seconds
Started Mar 24 01:25:00 PM PDT 24
Finished Mar 24 01:25:25 PM PDT 24
Peak memory 204848 kb
Host smart-1ce1a2fd-f4a9-4848-925e-e013da7410da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283084598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.4283084598
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.2456562966
Short name T247
Test name
Test status
Simulation time 259792893 ps
CPU time 15.51 seconds
Started Mar 24 01:25:01 PM PDT 24
Finished Mar 24 01:25:17 PM PDT 24
Peak memory 203968 kb
Host smart-53b282c6-1024-4843-a03d-684cbb9b3788
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2456562966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2456562966
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.101660280
Short name T155
Test name
Test status
Simulation time 285287292 ps
CPU time 3.73 seconds
Started Mar 24 01:25:08 PM PDT 24
Finished Mar 24 01:25:12 PM PDT 24
Peak memory 203544 kb
Host smart-38486480-4858-4973-8c32-afb8f2ed93cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=101660280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.101660280
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1421574377
Short name T734
Test name
Test status
Simulation time 4848823567 ps
CPU time 29.68 seconds
Started Mar 24 01:25:08 PM PDT 24
Finished Mar 24 01:25:37 PM PDT 24
Peak memory 203600 kb
Host smart-ac4ff779-5c36-4672-a863-3b9393e65875
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421574377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1421574377
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3650781624
Short name T447
Test name
Test status
Simulation time 2467963232 ps
CPU time 19.52 seconds
Started Mar 24 01:25:01 PM PDT 24
Finished Mar 24 01:25:20 PM PDT 24
Peak memory 203564 kb
Host smart-1f06d024-61ec-451d-8019-9879c6ed8081
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3650781624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3650781624
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1754579314
Short name T70
Test name
Test status
Simulation time 34625789 ps
CPU time 2.78 seconds
Started Mar 24 01:24:58 PM PDT 24
Finished Mar 24 01:25:01 PM PDT 24
Peak memory 203500 kb
Host smart-29e610e6-eca0-439f-99b0-1a2f692c5d25
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754579314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1754579314
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.385269552
Short name T193
Test name
Test status
Simulation time 1811114839 ps
CPU time 144.86 seconds
Started Mar 24 01:25:09 PM PDT 24
Finished Mar 24 01:27:34 PM PDT 24
Peak memory 208608 kb
Host smart-bd94f4cc-2e74-4b3e-93d4-97b234f80c62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=385269552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.385269552
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.49092169
Short name T588
Test name
Test status
Simulation time 4651278839 ps
CPU time 163.24 seconds
Started Mar 24 01:25:07 PM PDT 24
Finished Mar 24 01:27:50 PM PDT 24
Peak memory 206664 kb
Host smart-5bee3245-cbf2-4658-b7f0-638caf479d14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49092169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.49092169
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.608278574
Short name T652
Test name
Test status
Simulation time 118105572 ps
CPU time 41.99 seconds
Started Mar 24 01:25:05 PM PDT 24
Finished Mar 24 01:25:47 PM PDT 24
Peak memory 206780 kb
Host smart-4f920de4-8f53-410f-bca2-62c615c5590b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=608278574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand
_reset.608278574
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.454010907
Short name T372
Test name
Test status
Simulation time 188120513 ps
CPU time 36.6 seconds
Started Mar 24 01:25:06 PM PDT 24
Finished Mar 24 01:25:42 PM PDT 24
Peak memory 206416 kb
Host smart-5ae3c4f2-df74-4c0c-bdc2-33cdd6367a34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=454010907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res
et_error.454010907
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.931731844
Short name T72
Test name
Test status
Simulation time 40867954 ps
CPU time 4.86 seconds
Started Mar 24 01:25:07 PM PDT 24
Finished Mar 24 01:25:12 PM PDT 24
Peak memory 211732 kb
Host smart-82913c7f-e5ee-49f1-8a73-5e4414f47420
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=931731844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.931731844
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3258187058
Short name T687
Test name
Test status
Simulation time 46390730795 ps
CPU time 374.69 seconds
Started Mar 24 01:20:40 PM PDT 24
Finished Mar 24 01:26:55 PM PDT 24
Peak memory 207204 kb
Host smart-b03cd8ba-f2fb-4a05-9db6-60fa6ee0b5ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3258187058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3258187058
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4067261484
Short name T181
Test name
Test status
Simulation time 223895532 ps
CPU time 7.93 seconds
Started Mar 24 01:20:51 PM PDT 24
Finished Mar 24 01:20:59 PM PDT 24
Peak memory 203660 kb
Host smart-e96b93c0-5e05-4053-90f3-f251da48eddc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4067261484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4067261484
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.4220927923
Short name T497
Test name
Test status
Simulation time 1587556870 ps
CPU time 33.88 seconds
Started Mar 24 01:20:46 PM PDT 24
Finished Mar 24 01:21:20 PM PDT 24
Peak memory 203452 kb
Host smart-2b5045bd-f48e-4eab-be07-c7ca727c0eee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4220927923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4220927923
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.3641949234
Short name T216
Test name
Test status
Simulation time 229706422 ps
CPU time 17.76 seconds
Started Mar 24 01:20:43 PM PDT 24
Finished Mar 24 01:21:01 PM PDT 24
Peak memory 204600 kb
Host smart-f83cd414-1d29-45a8-8130-27c7c693bdd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3641949234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3641949234
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.984654321
Short name T210
Test name
Test status
Simulation time 100705346707 ps
CPU time 246.51 seconds
Started Mar 24 01:20:44 PM PDT 24
Finished Mar 24 01:24:51 PM PDT 24
Peak memory 204820 kb
Host smart-a4998a8c-57e2-44c0-945f-0110ed31984e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=984654321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.984654321
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4255180361
Short name T55
Test name
Test status
Simulation time 6065973337 ps
CPU time 25.57 seconds
Started Mar 24 01:20:40 PM PDT 24
Finished Mar 24 01:21:06 PM PDT 24
Peak memory 204088 kb
Host smart-6492ecd1-c957-4324-be44-fa7b9343d1d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4255180361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4255180361
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2646462449
Short name T867
Test name
Test status
Simulation time 206130896 ps
CPU time 23.68 seconds
Started Mar 24 01:20:42 PM PDT 24
Finished Mar 24 01:21:06 PM PDT 24
Peak memory 204972 kb
Host smart-f460a28e-a689-4f9b-992e-6d2765cf2087
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646462449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2646462449
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.88355759
Short name T217
Test name
Test status
Simulation time 161868428 ps
CPU time 13.45 seconds
Started Mar 24 01:20:42 PM PDT 24
Finished Mar 24 01:20:56 PM PDT 24
Peak memory 203516 kb
Host smart-112f1707-de7c-48fc-968d-31c4df315e06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88355759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.88355759
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.3246256534
Short name T139
Test name
Test status
Simulation time 151068517 ps
CPU time 3.97 seconds
Started Mar 24 01:20:38 PM PDT 24
Finished Mar 24 01:20:42 PM PDT 24
Peak memory 203520 kb
Host smart-0d6475f8-8ce3-47e6-9200-0015abca6967
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3246256534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3246256534
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.499169206
Short name T856
Test name
Test status
Simulation time 9051606469 ps
CPU time 30.79 seconds
Started Mar 24 01:20:38 PM PDT 24
Finished Mar 24 01:21:09 PM PDT 24
Peak memory 203548 kb
Host smart-1485f44f-73a2-432a-be7b-c78120804f21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=499169206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.499169206
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3988152260
Short name T671
Test name
Test status
Simulation time 2811702924 ps
CPU time 28.53 seconds
Started Mar 24 01:20:42 PM PDT 24
Finished Mar 24 01:21:10 PM PDT 24
Peak memory 203576 kb
Host smart-e0221ecf-7f3d-44c5-ab7d-218db61bfb2d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3988152260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3988152260
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.57274978
Short name T325
Test name
Test status
Simulation time 43911394 ps
CPU time 2.06 seconds
Started Mar 24 01:20:40 PM PDT 24
Finished Mar 24 01:20:42 PM PDT 24
Peak memory 203516 kb
Host smart-ad2b22d5-63b1-4e24-81d4-3451407d3659
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57274978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.57274978
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3185962776
Short name T582
Test name
Test status
Simulation time 7266521430 ps
CPU time 222.88 seconds
Started Mar 24 01:20:47 PM PDT 24
Finished Mar 24 01:24:30 PM PDT 24
Peak memory 207412 kb
Host smart-24019ad6-d0a9-48bd-a8e5-03fcee8a8bc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3185962776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3185962776
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1116574470
Short name T231
Test name
Test status
Simulation time 7869382851 ps
CPU time 210.92 seconds
Started Mar 24 01:20:46 PM PDT 24
Finished Mar 24 01:24:17 PM PDT 24
Peak memory 209020 kb
Host smart-04b10486-6e90-4c37-895b-009b976fb174
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1116574470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1116574470
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2753215761
Short name T220
Test name
Test status
Simulation time 9974706702 ps
CPU time 270.08 seconds
Started Mar 24 01:20:46 PM PDT 24
Finished Mar 24 01:25:17 PM PDT 24
Peak memory 211724 kb
Host smart-4f671db9-79bf-4054-8499-fd8a26ce671d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2753215761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.2753215761
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2793409312
Short name T496
Test name
Test status
Simulation time 2566630832 ps
CPU time 347.84 seconds
Started Mar 24 01:20:49 PM PDT 24
Finished Mar 24 01:26:37 PM PDT 24
Peak memory 219976 kb
Host smart-ecaad0c3-7135-48f7-99c6-b1965861a67d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2793409312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.2793409312
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.554648413
Short name T100
Test name
Test status
Simulation time 85628158 ps
CPU time 15.09 seconds
Started Mar 24 01:20:46 PM PDT 24
Finished Mar 24 01:21:01 PM PDT 24
Peak memory 205208 kb
Host smart-a3d21986-d9dd-446f-af1c-0faa4815be3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=554648413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.554648413
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1153227076
Short name T558
Test name
Test status
Simulation time 243960279 ps
CPU time 13.71 seconds
Started Mar 24 01:20:52 PM PDT 24
Finished Mar 24 01:21:06 PM PDT 24
Peak memory 205388 kb
Host smart-c34586fa-c307-4ea9-8cd0-eb1bc33a0722
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1153227076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1153227076
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1783346622
Short name T609
Test name
Test status
Simulation time 393790035582 ps
CPU time 918.15 seconds
Started Mar 24 01:20:53 PM PDT 24
Finished Mar 24 01:36:11 PM PDT 24
Peak memory 207304 kb
Host smart-7c2bd50b-c443-44ed-a06b-5277118ffaf6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1783346622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.1783346622
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.856153679
Short name T185
Test name
Test status
Simulation time 797285479 ps
CPU time 13.22 seconds
Started Mar 24 01:20:50 PM PDT 24
Finished Mar 24 01:21:03 PM PDT 24
Peak memory 203996 kb
Host smart-b76e312c-d1d4-4dd6-a824-4a7267dc398b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856153679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.856153679
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.3017608692
Short name T780
Test name
Test status
Simulation time 653542268 ps
CPU time 21.68 seconds
Started Mar 24 01:20:53 PM PDT 24
Finished Mar 24 01:21:14 PM PDT 24
Peak memory 203596 kb
Host smart-4de25170-19d4-49ab-a88f-e270c0744ebf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3017608692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3017608692
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.197265284
Short name T195
Test name
Test status
Simulation time 593672377 ps
CPU time 7.66 seconds
Started Mar 24 01:20:50 PM PDT 24
Finished Mar 24 01:20:58 PM PDT 24
Peak memory 204648 kb
Host smart-25577472-dfe8-45bd-8e58-f7aeec233c69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=197265284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.197265284
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.3035582129
Short name T284
Test name
Test status
Simulation time 67195374671 ps
CPU time 105.22 seconds
Started Mar 24 01:20:52 PM PDT 24
Finished Mar 24 01:22:38 PM PDT 24
Peak memory 204804 kb
Host smart-a88c6b30-c410-43e3-a029-3d1f0064805f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035582129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3035582129
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.587356897
Short name T643
Test name
Test status
Simulation time 13643439382 ps
CPU time 97.3 seconds
Started Mar 24 01:20:52 PM PDT 24
Finished Mar 24 01:22:29 PM PDT 24
Peak memory 204928 kb
Host smart-9cb4eb2a-4728-4371-bd7a-c7a2f1c76d79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=587356897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.587356897
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.692237077
Short name T849
Test name
Test status
Simulation time 74699375 ps
CPU time 4.32 seconds
Started Mar 24 01:20:51 PM PDT 24
Finished Mar 24 01:20:56 PM PDT 24
Peak memory 203492 kb
Host smart-cff9b21b-fb2d-443c-a8f6-fd272676cdd3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=692237077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.692237077
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.2070164836
Short name T844
Test name
Test status
Simulation time 309930313 ps
CPU time 3.18 seconds
Started Mar 24 01:20:46 PM PDT 24
Finished Mar 24 01:20:49 PM PDT 24
Peak memory 203468 kb
Host smart-d98eed36-698f-4c89-b4b1-da08b797c785
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2070164836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2070164836
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3071890480
Short name T205
Test name
Test status
Simulation time 6833918803 ps
CPU time 29.53 seconds
Started Mar 24 01:20:51 PM PDT 24
Finished Mar 24 01:21:20 PM PDT 24
Peak memory 203544 kb
Host smart-4be4deeb-3bca-41b9-9c19-6a01043d07c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071890480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3071890480
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3134878274
Short name T580
Test name
Test status
Simulation time 4639257523 ps
CPU time 28.2 seconds
Started Mar 24 01:20:51 PM PDT 24
Finished Mar 24 01:21:19 PM PDT 24
Peak memory 203552 kb
Host smart-5b19a594-a3b8-453b-8cdd-4163d71dcded
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3134878274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3134878274
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2048031439
Short name T453
Test name
Test status
Simulation time 32148548 ps
CPU time 2.1 seconds
Started Mar 24 01:20:46 PM PDT 24
Finished Mar 24 01:20:48 PM PDT 24
Peak memory 203500 kb
Host smart-bf21d985-d4d4-4fc8-9acc-e3bf9dfa9d26
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048031439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2048031439
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3463161759
Short name T704
Test name
Test status
Simulation time 4192715721 ps
CPU time 135.52 seconds
Started Mar 24 01:20:50 PM PDT 24
Finished Mar 24 01:23:06 PM PDT 24
Peak memory 207612 kb
Host smart-558ddc78-5bfa-4754-a9fe-de383e9e4565
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3463161759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3463161759
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3143460483
Short name T782
Test name
Test status
Simulation time 22840871223 ps
CPU time 223.6 seconds
Started Mar 24 01:20:51 PM PDT 24
Finished Mar 24 01:24:34 PM PDT 24
Peak memory 209736 kb
Host smart-0f788b15-446c-4a1d-8b19-2879daa0b19f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3143460483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3143460483
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.179678516
Short name T83
Test name
Test status
Simulation time 552825461 ps
CPU time 233.8 seconds
Started Mar 24 01:20:53 PM PDT 24
Finished Mar 24 01:24:47 PM PDT 24
Peak memory 208592 kb
Host smart-62776997-467a-4a1f-a865-015ce6f2028a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=179678516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.179678516
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3739309582
Short name T846
Test name
Test status
Simulation time 178779263 ps
CPU time 58.75 seconds
Started Mar 24 01:20:56 PM PDT 24
Finished Mar 24 01:21:54 PM PDT 24
Peak memory 207000 kb
Host smart-8df63129-0d36-4205-9ece-f8a693744740
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3739309582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.3739309582
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.190883647
Short name T228
Test name
Test status
Simulation time 256401330 ps
CPU time 10.98 seconds
Started Mar 24 01:20:52 PM PDT 24
Finished Mar 24 01:21:03 PM PDT 24
Peak memory 211616 kb
Host smart-67b2ce5a-2859-42cd-bf56-2817a899868c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=190883647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.190883647
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.966135372
Short name T573
Test name
Test status
Simulation time 388175394 ps
CPU time 43.23 seconds
Started Mar 24 01:21:01 PM PDT 24
Finished Mar 24 01:21:44 PM PDT 24
Peak memory 204592 kb
Host smart-3ce98978-4e2a-4298-b459-2e686f9164dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=966135372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.966135372
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2735222756
Short name T389
Test name
Test status
Simulation time 49740395107 ps
CPU time 350.77 seconds
Started Mar 24 01:21:02 PM PDT 24
Finished Mar 24 01:26:53 PM PDT 24
Peak memory 206088 kb
Host smart-bf9fcd7b-9daa-4d59-8846-ed35d1f4a86a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2735222756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.2735222756
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1948570161
Short name T654
Test name
Test status
Simulation time 30966474 ps
CPU time 4.06 seconds
Started Mar 24 01:21:01 PM PDT 24
Finished Mar 24 01:21:05 PM PDT 24
Peak memory 203444 kb
Host smart-bed9ca1c-6941-48a8-8109-2677f31549ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1948570161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1948570161
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.2401580180
Short name T335
Test name
Test status
Simulation time 208146006 ps
CPU time 6.14 seconds
Started Mar 24 01:21:03 PM PDT 24
Finished Mar 24 01:21:09 PM PDT 24
Peak memory 203512 kb
Host smart-61d3d441-c36c-401f-86c3-b9d5ae145e7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2401580180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2401580180
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.2406656148
Short name T26
Test name
Test status
Simulation time 694530790 ps
CPU time 18.46 seconds
Started Mar 24 01:20:58 PM PDT 24
Finished Mar 24 01:21:17 PM PDT 24
Peak memory 204576 kb
Host smart-43ae34fe-111b-43ca-be67-f5d441e31064
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2406656148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2406656148
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.529361620
Short name T51
Test name
Test status
Simulation time 80623808443 ps
CPU time 200.67 seconds
Started Mar 24 01:21:01 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 205332 kb
Host smart-9794012b-3290-4719-aafe-6a9c4b3a8fee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=529361620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.529361620
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.119345313
Short name T638
Test name
Test status
Simulation time 19894279919 ps
CPU time 130.14 seconds
Started Mar 24 01:21:02 PM PDT 24
Finished Mar 24 01:23:12 PM PDT 24
Peak memory 205248 kb
Host smart-e2e85e0a-b795-4d38-b558-264b47ca1869
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=119345313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.119345313
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.869838005
Short name T730
Test name
Test status
Simulation time 102534349 ps
CPU time 12.01 seconds
Started Mar 24 01:20:56 PM PDT 24
Finished Mar 24 01:21:08 PM PDT 24
Peak memory 204560 kb
Host smart-8ae9f5c7-e4ca-4e60-857d-38aaec23abfe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869838005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.869838005
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.3991195284
Short name T700
Test name
Test status
Simulation time 3397838220 ps
CPU time 29.35 seconds
Started Mar 24 01:21:03 PM PDT 24
Finished Mar 24 01:21:32 PM PDT 24
Peak memory 203572 kb
Host smart-76b5a676-af09-4d6a-99d2-46a7c15cdd05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3991195284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3991195284
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.3531477131
Short name T695
Test name
Test status
Simulation time 36828895 ps
CPU time 2.24 seconds
Started Mar 24 01:20:57 PM PDT 24
Finished Mar 24 01:20:59 PM PDT 24
Peak memory 203484 kb
Host smart-fd97d1ea-63d9-4dfc-85ca-2d1485670d66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3531477131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3531477131
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.661691103
Short name T329
Test name
Test status
Simulation time 5485190803 ps
CPU time 28.9 seconds
Started Mar 24 01:20:59 PM PDT 24
Finished Mar 24 01:21:28 PM PDT 24
Peak memory 203556 kb
Host smart-9209d2f0-e650-4e1a-8af0-d49d71d772f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=661691103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.661691103
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1704295911
Short name T499
Test name
Test status
Simulation time 3619331994 ps
CPU time 29.5 seconds
Started Mar 24 01:20:55 PM PDT 24
Finished Mar 24 01:21:25 PM PDT 24
Peak memory 203556 kb
Host smart-11436dbd-4d01-4d99-9165-91e83f65c0ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1704295911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1704295911
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.559585414
Short name T563
Test name
Test status
Simulation time 30730844 ps
CPU time 2.49 seconds
Started Mar 24 01:20:57 PM PDT 24
Finished Mar 24 01:20:59 PM PDT 24
Peak memory 203500 kb
Host smart-37e7a039-c5e6-4692-a03d-404f60e7addb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559585414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.559585414
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.3115549319
Short name T465
Test name
Test status
Simulation time 2568185230 ps
CPU time 157.79 seconds
Started Mar 24 01:21:00 PM PDT 24
Finished Mar 24 01:23:38 PM PDT 24
Peak memory 206204 kb
Host smart-a37c232d-79e4-407d-bb5d-8203b59daa4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3115549319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3115549319
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2421925466
Short name T449
Test name
Test status
Simulation time 13361310823 ps
CPU time 138.9 seconds
Started Mar 24 01:21:06 PM PDT 24
Finished Mar 24 01:23:25 PM PDT 24
Peak memory 206800 kb
Host smart-ee3d82eb-34ea-40c7-9668-351b6d9e38dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2421925466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2421925466
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.687219987
Short name T861
Test name
Test status
Simulation time 512797745 ps
CPU time 99.82 seconds
Started Mar 24 01:21:01 PM PDT 24
Finished Mar 24 01:22:41 PM PDT 24
Peak memory 208224 kb
Host smart-3244f2b7-deb1-42b1-a22a-86f00e58daca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=687219987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_
reset.687219987
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2232981463
Short name T459
Test name
Test status
Simulation time 5236959353 ps
CPU time 146.67 seconds
Started Mar 24 01:21:02 PM PDT 24
Finished Mar 24 01:23:29 PM PDT 24
Peak memory 209736 kb
Host smart-455ee724-54b4-49e0-bfe4-dff4a90e8c3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2232981463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.2232981463
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.4112173316
Short name T737
Test name
Test status
Simulation time 642847039 ps
CPU time 16.83 seconds
Started Mar 24 01:21:03 PM PDT 24
Finished Mar 24 01:21:20 PM PDT 24
Peak memory 205020 kb
Host smart-62c0c176-aa2c-481e-9d99-fcec63b467c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4112173316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4112173316
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2046219445
Short name T384
Test name
Test status
Simulation time 110497847 ps
CPU time 21.24 seconds
Started Mar 24 01:21:07 PM PDT 24
Finished Mar 24 01:21:28 PM PDT 24
Peak memory 204608 kb
Host smart-704541c5-b79b-487d-aaa3-9d52d8be4af6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2046219445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2046219445
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2380481736
Short name T662
Test name
Test status
Simulation time 19655916211 ps
CPU time 162.04 seconds
Started Mar 24 01:21:06 PM PDT 24
Finished Mar 24 01:23:48 PM PDT 24
Peak memory 211712 kb
Host smart-da3cc932-70b5-4574-b135-c0d7fc453c04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2380481736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.2380481736
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1812430045
Short name T528
Test name
Test status
Simulation time 173377787 ps
CPU time 17.49 seconds
Started Mar 24 01:21:07 PM PDT 24
Finished Mar 24 01:21:24 PM PDT 24
Peak memory 203528 kb
Host smart-fda84874-3ea8-4563-b45f-14de02c22a77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1812430045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1812430045
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.1687630468
Short name T370
Test name
Test status
Simulation time 1258486938 ps
CPU time 34.56 seconds
Started Mar 24 01:21:07 PM PDT 24
Finished Mar 24 01:21:42 PM PDT 24
Peak memory 203508 kb
Host smart-311f149e-ba1d-4522-b408-da2b1fb18825
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1687630468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1687630468
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.1995726052
Short name T698
Test name
Test status
Simulation time 665301114 ps
CPU time 10.27 seconds
Started Mar 24 01:21:02 PM PDT 24
Finished Mar 24 01:21:12 PM PDT 24
Peak memory 204600 kb
Host smart-3907f2da-79e3-4e65-a613-763a67ba32a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1995726052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1995726052
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1028301641
Short name T199
Test name
Test status
Simulation time 44348022491 ps
CPU time 170.71 seconds
Started Mar 24 01:21:02 PM PDT 24
Finished Mar 24 01:23:53 PM PDT 24
Peak memory 205044 kb
Host smart-d5cb23db-cfe3-43e7-abd4-c1f8053c691d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028301641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1028301641
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2088527727
Short name T125
Test name
Test status
Simulation time 24736810540 ps
CPU time 135.71 seconds
Started Mar 24 01:21:07 PM PDT 24
Finished Mar 24 01:23:23 PM PDT 24
Peak memory 211764 kb
Host smart-e2a76189-6605-434e-a9dc-6b89d0fe4bfe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2088527727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2088527727
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3212190964
Short name T452
Test name
Test status
Simulation time 156601947 ps
CPU time 20.78 seconds
Started Mar 24 01:21:01 PM PDT 24
Finished Mar 24 01:21:22 PM PDT 24
Peak memory 204728 kb
Host smart-0987c01b-8196-433a-b4c8-f326156fb147
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212190964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3212190964
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2763229622
Short name T474
Test name
Test status
Simulation time 646353644 ps
CPU time 15.11 seconds
Started Mar 24 01:21:07 PM PDT 24
Finished Mar 24 01:21:22 PM PDT 24
Peak memory 203484 kb
Host smart-7418dd34-26ff-4ce0-b4d9-f68bb48627d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2763229622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2763229622
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.2744474015
Short name T527
Test name
Test status
Simulation time 165496301 ps
CPU time 3.8 seconds
Started Mar 24 01:21:06 PM PDT 24
Finished Mar 24 01:21:10 PM PDT 24
Peak memory 203480 kb
Host smart-a6b92758-ac76-4959-ac2e-fb9cc1d2f845
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2744474015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2744474015
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2524911765
Short name T52
Test name
Test status
Simulation time 7894771649 ps
CPU time 29.7 seconds
Started Mar 24 01:21:00 PM PDT 24
Finished Mar 24 01:21:30 PM PDT 24
Peak memory 203584 kb
Host smart-361eb072-ce3a-4f2a-9c67-0de325980201
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524911765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2524911765
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3366544699
Short name T182
Test name
Test status
Simulation time 4881237265 ps
CPU time 21.88 seconds
Started Mar 24 01:21:01 PM PDT 24
Finished Mar 24 01:21:23 PM PDT 24
Peak memory 203552 kb
Host smart-0dd871a3-2379-4de8-93b3-3c78f77bb12b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3366544699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3366544699
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3467461562
Short name T656
Test name
Test status
Simulation time 30773924 ps
CPU time 2.2 seconds
Started Mar 24 01:21:00 PM PDT 24
Finished Mar 24 01:21:03 PM PDT 24
Peak memory 203508 kb
Host smart-05e065fc-63e1-44ed-a042-3d586329769d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467461562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3467461562
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.277061156
Short name T420
Test name
Test status
Simulation time 5462631905 ps
CPU time 76.18 seconds
Started Mar 24 01:21:06 PM PDT 24
Finished Mar 24 01:22:23 PM PDT 24
Peak memory 207576 kb
Host smart-b43af7ef-feb1-424f-b9cf-76535807870d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277061156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.277061156
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1786831181
Short name T272
Test name
Test status
Simulation time 3443032558 ps
CPU time 139.33 seconds
Started Mar 24 01:21:06 PM PDT 24
Finished Mar 24 01:23:26 PM PDT 24
Peak memory 208984 kb
Host smart-b68e71ad-fb92-4708-9b23-aa30419510c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1786831181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1786831181
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3282302392
Short name T200
Test name
Test status
Simulation time 1554389928 ps
CPU time 331.86 seconds
Started Mar 24 01:21:06 PM PDT 24
Finished Mar 24 01:26:38 PM PDT 24
Peak memory 209312 kb
Host smart-aea1830a-c683-446d-8a73-068e741bf436
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3282302392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.3282302392
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1914472776
Short name T726
Test name
Test status
Simulation time 454035980 ps
CPU time 9.55 seconds
Started Mar 24 01:21:08 PM PDT 24
Finished Mar 24 01:21:17 PM PDT 24
Peak memory 204796 kb
Host smart-b6acdf93-6a38-4d32-b052-6e7b65c1f2a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1914472776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1914472776
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3423677324
Short name T680
Test name
Test status
Simulation time 1080416252 ps
CPU time 21.05 seconds
Started Mar 24 01:21:14 PM PDT 24
Finished Mar 24 01:21:36 PM PDT 24
Peak memory 206028 kb
Host smart-899d01bf-7f39-46b7-b5af-d5885d1f2e44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3423677324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3423677324
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1951600308
Short name T513
Test name
Test status
Simulation time 14923843723 ps
CPU time 116.51 seconds
Started Mar 24 01:21:13 PM PDT 24
Finished Mar 24 01:23:09 PM PDT 24
Peak memory 206112 kb
Host smart-9bf7ce4c-19ff-4681-af62-0416cb4c5c7d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1951600308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.1951600308
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1499608475
Short name T252
Test name
Test status
Simulation time 407814391 ps
CPU time 9.42 seconds
Started Mar 24 01:21:19 PM PDT 24
Finished Mar 24 01:21:28 PM PDT 24
Peak memory 203808 kb
Host smart-bab90812-711b-49ee-a79e-1a518302725b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1499608475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1499608475
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.1702107636
Short name T186
Test name
Test status
Simulation time 92911700 ps
CPU time 2.44 seconds
Started Mar 24 01:21:14 PM PDT 24
Finished Mar 24 01:21:16 PM PDT 24
Peak memory 203484 kb
Host smart-060021c3-4e32-42e5-9937-c0be5a593eee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1702107636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1702107636
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.427239938
Short name T600
Test name
Test status
Simulation time 104504987 ps
CPU time 9.51 seconds
Started Mar 24 01:21:16 PM PDT 24
Finished Mar 24 01:21:25 PM PDT 24
Peak memory 211676 kb
Host smart-1430c575-4ee0-4598-b8cf-8131795286a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=427239938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.427239938
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3684297682
Short name T114
Test name
Test status
Simulation time 14209560219 ps
CPU time 51.35 seconds
Started Mar 24 01:21:16 PM PDT 24
Finished Mar 24 01:22:08 PM PDT 24
Peak memory 211724 kb
Host smart-d8615e74-9a29-40a0-a91e-8b80888925e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684297682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3684297682
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3135994126
Short name T57
Test name
Test status
Simulation time 5879649009 ps
CPU time 14.01 seconds
Started Mar 24 01:21:14 PM PDT 24
Finished Mar 24 01:21:29 PM PDT 24
Peak memory 203564 kb
Host smart-5539028c-a536-4a15-ab74-abe557c9e8c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3135994126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3135994126
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.312204317
Short name T206
Test name
Test status
Simulation time 178250538 ps
CPU time 11.07 seconds
Started Mar 24 01:21:14 PM PDT 24
Finished Mar 24 01:21:25 PM PDT 24
Peak memory 204608 kb
Host smart-158d1059-0f4e-4ddb-a2a5-f27c98d17a0c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312204317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.312204317
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.263549277
Short name T540
Test name
Test status
Simulation time 404736558 ps
CPU time 7.66 seconds
Started Mar 24 01:21:12 PM PDT 24
Finished Mar 24 01:21:20 PM PDT 24
Peak memory 203444 kb
Host smart-853faad6-fc49-4a89-96b6-98f273f55913
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=263549277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.263549277
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.3088557181
Short name T542
Test name
Test status
Simulation time 143977817 ps
CPU time 3.59 seconds
Started Mar 24 01:21:12 PM PDT 24
Finished Mar 24 01:21:16 PM PDT 24
Peak memory 203444 kb
Host smart-83f45779-f79b-47e7-9ed6-d45d129fcfcf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3088557181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3088557181
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2433135769
Short name T388
Test name
Test status
Simulation time 10650069765 ps
CPU time 33.02 seconds
Started Mar 24 01:21:14 PM PDT 24
Finished Mar 24 01:21:47 PM PDT 24
Peak memory 203548 kb
Host smart-4dbb7450-210b-4567-9e0b-c60e4c3be521
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433135769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2433135769
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1479721986
Short name T286
Test name
Test status
Simulation time 4632793375 ps
CPU time 38.88 seconds
Started Mar 24 01:21:12 PM PDT 24
Finished Mar 24 01:21:51 PM PDT 24
Peak memory 203796 kb
Host smart-280f282c-3953-4f64-a412-976462e56b96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1479721986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1479721986
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.193791254
Short name T326
Test name
Test status
Simulation time 33978933 ps
CPU time 2.28 seconds
Started Mar 24 01:21:15 PM PDT 24
Finished Mar 24 01:21:18 PM PDT 24
Peak memory 203480 kb
Host smart-8abc6bfe-022c-43c7-bb11-034d4250b8b8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193791254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.193791254
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2693061949
Short name T841
Test name
Test status
Simulation time 1349230476 ps
CPU time 52.47 seconds
Started Mar 24 01:21:18 PM PDT 24
Finished Mar 24 01:22:11 PM PDT 24
Peak memory 205892 kb
Host smart-ae230f5c-35b7-47c8-b484-315c6a8e0556
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2693061949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2693061949
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.485801957
Short name T789
Test name
Test status
Simulation time 9087124939 ps
CPU time 231.61 seconds
Started Mar 24 01:21:20 PM PDT 24
Finished Mar 24 01:25:11 PM PDT 24
Peak memory 211296 kb
Host smart-9e83672a-b0b6-4a47-901d-2c70994f96f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485801957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.485801957
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.994247443
Short name T190
Test name
Test status
Simulation time 566300064 ps
CPU time 200.19 seconds
Started Mar 24 01:21:18 PM PDT 24
Finished Mar 24 01:24:39 PM PDT 24
Peak memory 210620 kb
Host smart-f278b639-1226-4e19-9668-83ed0997a7b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=994247443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_
reset.994247443
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2920114203
Short name T162
Test name
Test status
Simulation time 4266981060 ps
CPU time 187.28 seconds
Started Mar 24 01:21:18 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 221316 kb
Host smart-4ded9514-b380-4ef6-b042-c95782116c62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2920114203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2920114203
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.43451390
Short name T429
Test name
Test status
Simulation time 1442067278 ps
CPU time 27.08 seconds
Started Mar 24 01:21:19 PM PDT 24
Finished Mar 24 01:21:46 PM PDT 24
Peak memory 211616 kb
Host smart-0199cf74-1629-4b58-83b1-0828f511dd15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43451390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.43451390
Directory /workspace/9.xbar_unmapped_addr/latest
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