Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1638	1			T1	22		T3	5		T10	17
all_values[1]	1613	1			T1	10		T3	4		T10	17
all_values[2]	1669	1			T1	16		T3	14		T10	17
all_values[3]	1610	1			T1	13		T3	11		T10	20
all_values[4]	1592	1			T1	12		T3	9		T10	15
all_values[5]	1643	1			T1	8		T3	10		T10	20
all_values[6]	1639	1			T1	8		T3	9		T10	18
all_values[7]	1578	1			T1	15		T3	7		T10	12
all_values[8]	1642	1			T1	8		T3	11		T10	13
all_values[9]	1676	1			T1	13		T3	5		T10	17
all_values[10]	1568	1			T1	6		T3	13		T10	18
all_values[11]	1609	1			T1	13		T3	8		T10	21
all_values[12]	1621	1			T1	11		T3	12		T10	9
all_values[13]	1579	1			T1	11		T3	8		T10	11
all_values[14]	1629	1			T1	5		T3	9		T10	24
all_values[15]	1622	1			T1	12		T3	13		T10	14
all_values[16]	1599	1			T1	11		T3	15		T10	13
all_values[17]	1670	1			T1	16		T3	20		T10	18
all_values[18]	1647	1			T1	13		T3	8		T10	15
all_values[19]	1620	1			T1	15		T3	17		T10	14
all_values[20]	1691	1			T1	8		T3	10		T10	15
all_values[21]	1591	1			T1	10		T3	7		T10	7
all_values[22]	1618	1			T1	11		T3	6		T10	25
all_values[23]	1661	1			T1	11		T3	10		T10	15
all_values[24]	1569	1			T1	12		T3	14		T10	13
all_values[25]	1714	1			T1	6		T3	23		T10	19
all_values[26]	1649	1			T1	16		T3	11		T10	22
all_values[27]	1650	1			T1	12		T3	14		T10	16
all_values[28]	1654	1			T1	9		T3	16		T10	22
all_values[29]	1631	1			T1	12		T3	8		T10	19
all_values[30]	1720	1			T1	20		T3	12		T10	15
all_values[31]	1631	1			T1	14		T3	11		T10	14
all_values[32]	1612	1			T1	11		T3	8		T10	21
all_values[33]	1646	1			T1	11		T3	8		T10	18
all_values[34]	1647	1			T1	15		T3	12		T10	7
all_values[35]	1687	1			T1	12		T3	11		T10	19
all_values[36]	1574	1			T1	12		T3	12		T10	8
all_values[37]	1572	1			T1	11		T3	9		T10	10
all_values[38]	1611	1			T1	13		T3	11		T10	17
all_values[39]	1528	1			T1	8		T3	7		T10	16
all_values[40]	1515	1			T1	16		T3	14		T10	16
all_values[41]	1556	1			T1	12		T3	9		T10	12
all_values[42]	1578	1			T1	12		T3	8		T10	18
all_values[43]	1611	1			T1	12		T3	21		T10	12
all_values[44]	1673	1			T1	13		T3	12		T10	14
all_values[45]	1626	1			T1	9		T3	10		T10	10
all_values[46]	1617	1			T1	11		T3	11		T10	23
all_values[47]	1637	1			T1	14		T3	11		T10	17
all_values[48]	1582	1			T1	15		T3	14		T10	12
all_values[49]	1633	1			T1	17		T3	13		T10	20
all_values[50]	1660	1			T1	9		T3	6		T10	12
all_values[51]	1560	1			T1	8		T3	17		T10	14
all_values[52]	1670	1			T1	11		T3	11		T10	11
all_values[53]	1574	1			T1	18		T3	7		T10	10
all_values[54]	1608	1			T1	6		T3	13		T10	29
all_values[55]	1658	1			T1	13		T3	9		T10	16
all_values[56]	1565	1			T1	13		T3	8		T10	19
all_values[57]	1660	1			T1	12		T3	13		T10	20
all_values[58]	1670	1			T1	3		T3	14		T10	14
all_values[59]	1656	1			T1	17		T3	18		T10	12
all_values[60]	1632	1			T1	6		T3	13		T10	20
all_values[61]	1640	1			T1	15		T3	9		T10	16
all_values[62]	1661	1			T1	16		T3	10		T10	19
all_values[63]	1676	1			T1	12		T3	12		T10	7