Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1693	1			T9	1		T14	2		T16	6
all_values[1]	1708	1			T9	3		T14	2		T16	7
all_values[2]	1729	1			T9	3		T14	1		T16	8
all_values[3]	1652	1			T9	3		T14	1		T16	6
all_values[4]	1660	1			T14	3		T16	7		T19	5
all_values[5]	1701	1			T9	2		T16	10		T19	10
all_values[6]	1698	1			T9	1		T14	3		T16	4
all_values[7]	1668	1			T9	1		T14	3		T16	5
all_values[8]	1611	1			T9	2		T14	2		T16	2
all_values[9]	1608	1			T9	4		T14	3		T16	2
all_values[10]	1685	1			T9	2		T14	8		T16	3
all_values[11]	1641	1			T9	1		T14	1		T16	1
all_values[12]	1602	1			T9	1		T14	2		T16	7
all_values[13]	1725	1			T9	1		T14	2		T16	4
all_values[14]	1683	1			T9	2		T14	2		T16	5
all_values[15]	1679	1			T9	4		T14	1		T16	1
all_values[16]	1603	1			T9	3		T14	2		T16	5
all_values[17]	1623	1			T9	2		T14	1		T16	5
all_values[18]	1634	1			T9	1		T14	1		T16	7
all_values[19]	1717	1			T9	6		T14	2		T16	5
all_values[20]	1658	1			T14	4		T16	6		T19	5
all_values[21]	1668	1			T9	2		T14	2		T16	6
all_values[22]	1602	1			T9	2		T14	1		T16	7
all_values[23]	1662	1			T9	4		T16	6		T19	8
all_values[24]	1682	1			T9	1		T14	2		T16	10
all_values[25]	1689	1			T9	5		T14	3		T16	3
all_values[26]	1687	1			T9	2		T14	2		T16	11
all_values[27]	1648	1			T9	5		T14	5		T16	7
all_values[28]	1672	1			T9	1		T16	9		T19	6
all_values[29]	1671	1			T9	4		T14	3		T16	2
all_values[30]	1642	1			T9	2		T14	2		T16	8
all_values[31]	1657	1			T9	5		T14	2		T16	2
all_values[32]	1697	1			T9	3		T14	6		T16	8
all_values[33]	1702	1			T9	4		T14	2		T16	12
all_values[34]	1676	1			T9	6		T16	6		T19	3
all_values[35]	1674	1			T9	2		T14	2		T16	4
all_values[36]	1595	1			T9	3		T14	1		T16	5
all_values[37]	1714	1			T9	2		T14	1		T16	8
all_values[38]	1731	1			T9	8		T14	4		T16	6
all_values[39]	1721	1			T9	2		T14	3		T16	8
all_values[40]	1645	1			T9	2		T14	4		T16	8
all_values[41]	1719	1			T9	4		T14	2		T16	8
all_values[42]	1617	1			T9	6		T14	4		T16	3
all_values[43]	1576	1			T9	3		T14	4		T16	4
all_values[44]	1650	1			T9	3		T14	5		T16	7
all_values[45]	1676	1			T9	4		T14	4		T16	9
all_values[46]	1611	1			T14	2		T16	8		T19	5
all_values[47]	1702	1			T9	3		T14	2		T16	5
all_values[48]	1654	1			T9	3		T14	8		T16	7
all_values[49]	1611	1			T9	3		T16	6		T19	5
all_values[50]	1672	1			T9	1		T14	2		T16	10
all_values[51]	1626	1			T9	3		T14	1		T16	5
all_values[52]	1702	1			T9	6		T14	6		T16	4
all_values[53]	1702	1			T9	3		T14	7		T16	5
all_values[54]	1694	1			T9	1		T14	3		T16	11
all_values[55]	1645	1			T14	1		T16	6		T19	11
all_values[56]	1612	1			T9	1		T14	1		T16	4
all_values[57]	1687	1			T9	3		T14	3		T16	6
all_values[58]	1732	1			T9	3		T16	1		T19	8
all_values[59]	1692	1			T9	2		T14	4		T16	8
all_values[60]	1676	1			T9	3		T14	4		T16	8
all_values[61]	1671	1			T9	2		T14	1		T16	3
all_values[62]	1713	1			T9	4		T14	2		T16	6
all_values[63]	1662	1			T9	4		T14	2		T16	5