Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1801	1			T18	4		T19	1		T20	1
all_values[1]	1786	1			T18	6		T19	2		T20	3
all_values[2]	1810	1			T18	5		T19	1		T20	1
all_values[3]	1819	1			T18	8		T19	1		T20	3
all_values[4]	1894	1			T18	6		T19	1		T20	3
all_values[5]	1770	1			T18	6		T22	3		T23	19
all_values[6]	1810	1			T18	9		T19	2		T20	2
all_values[7]	1895	1			T18	4		T19	5		T20	2
all_values[8]	1836	1			T18	6		T20	3		T22	1
all_values[9]	1790	1			T18	6		T19	3		T23	16
all_values[10]	1812	1			T18	6		T20	2		T23	23
all_values[11]	1835	1			T18	9		T19	2		T20	2
all_values[12]	1772	1			T18	1		T20	1		T23	22
all_values[13]	1892	1			T18	12		T20	1		T22	1
all_values[14]	1864	1			T18	2		T20	2		T22	2
all_values[15]	1778	1			T18	3		T19	1		T20	2
all_values[16]	1843	1			T18	6		T19	1		T20	1
all_values[17]	1813	1			T18	3		T19	2		T20	1
all_values[18]	1756	1			T18	1		T19	2		T20	1
all_values[19]	1764	1			T18	2		T19	1		T22	2
all_values[20]	1890	1			T18	9		T20	1		T22	1
all_values[21]	1807	1			T18	2		T19	1		T20	1
all_values[22]	1820	1			T18	2		T19	1		T22	1
all_values[23]	1752	1			T18	7		T20	2		T22	1
all_values[24]	1871	1			T18	4		T19	2		T20	2
all_values[25]	1803	1			T18	5		T23	23		T74	17
all_values[26]	1836	1			T18	2		T20	4		T22	2
all_values[27]	1833	1			T18	7		T19	1		T20	2
all_values[28]	1800	1			T18	7		T19	1		T22	1
all_values[29]	1810	1			T18	4		T19	1		T20	3
all_values[30]	1825	1			T18	4		T19	2		T20	1
all_values[31]	1880	1			T18	8		T19	3		T20	2
all_values[32]	1803	1			T18	5		T19	1		T23	26
all_values[33]	1855	1			T18	8		T20	1		T22	1
all_values[34]	1693	1			T18	4		T20	3		T23	33
all_values[35]	1782	1			T18	3		T19	1		T20	2
all_values[36]	1823	1			T18	10		T20	1		T23	29
all_values[37]	1780	1			T18	5		T23	29		T74	14
all_values[38]	1759	1			T18	9		T19	4		T20	1
all_values[39]	1746	1			T18	4		T19	2		T22	1
all_values[40]	1775	1			T18	5		T19	2		T20	2
all_values[41]	1831	1			T18	10		T19	2		T22	1
all_values[42]	1860	1			T18	5		T19	1		T22	3
all_values[43]	1754	1			T18	10		T19	2		T20	2
all_values[44]	1811	1			T18	7		T20	1		T22	1
all_values[45]	1812	1			T18	3		T19	1		T23	19
all_values[46]	1787	1			T18	4		T19	2		T20	3
all_values[47]	1834	1			T18	6		T19	2		T20	1
all_values[48]	1820	1			T18	7		T20	3		T22	4
all_values[49]	1759	1			T18	9		T22	1		T23	34
all_values[50]	1851	1			T18	4		T20	1		T23	27
all_values[51]	1790	1			T18	7		T19	1		T23	32
all_values[52]	1826	1			T18	6		T20	4		T22	3
all_values[53]	1802	1			T18	5		T20	3		T22	1
all_values[54]	1814	1			T18	3		T19	1		T20	2
all_values[55]	1796	1			T18	5		T19	1		T22	4
all_values[56]	1780	1			T18	4		T19	3		T20	2
all_values[57]	1785	1			T18	6		T22	1		T23	23
all_values[58]	1860	1			T18	4		T20	1		T22	4
all_values[59]	1754	1			T18	7		T19	2		T20	2
all_values[60]	1790	1			T18	7		T20	1		T22	1
all_values[61]	1797	1			T18	10		T20	2		T22	2
all_values[62]	1883	1			T18	8		T19	2		T22	2
all_values[63]	1833	1			T18	5		T20	1		T23	29