Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1778	1			T1	6		T2	21		T10	2
all_values[1]	1793	1			T1	6		T2	25		T10	3
all_values[2]	1845	1			T1	6		T2	19		T10	3
all_values[3]	1796	1			T1	3		T2	28		T10	3
all_values[4]	1860	1			T1	5		T2	32		T10	5
all_values[5]	1884	1			T1	6		T2	34		T10	2
all_values[6]	1788	1			T1	3		T2	26		T10	4
all_values[7]	1875	1			T1	7		T2	36		T10	1
all_values[8]	1807	1			T1	7		T2	23		T10	5
all_values[9]	1848	1			T1	2		T2	28		T10	5
all_values[10]	1862	1			T1	8		T2	27		T10	3
all_values[11]	1898	1			T1	5		T2	20		T10	3
all_values[12]	1820	1			T1	10		T2	29		T10	2
all_values[13]	1874	1			T1	2		T2	34		T10	3
all_values[14]	1831	1			T1	6		T2	17		T10	5
all_values[15]	1846	1			T1	8		T2	35		T10	6
all_values[16]	1813	1			T1	8		T2	23		T10	1
all_values[17]	1847	1			T1	3		T2	21		T10	4
all_values[18]	1826	1			T1	3		T2	19		T7	8
all_values[19]	1849	1			T1	4		T2	26		T10	4
all_values[20]	1903	1			T1	3		T2	28		T10	2
all_values[21]	1840	1			T1	2		T2	19		T10	2
all_values[22]	1839	1			T1	4		T2	28		T10	5
all_values[23]	1779	1			T1	6		T2	31		T10	2
all_values[24]	1855	1			T1	2		T2	31		T10	3
all_values[25]	1773	1			T1	4		T2	20		T10	2
all_values[26]	1841	1			T1	2		T2	31		T10	4
all_values[27]	1827	1			T1	3		T2	19		T10	3
all_values[28]	1797	1			T1	3		T2	18		T10	2
all_values[29]	1928	1			T1	7		T2	27		T10	5
all_values[30]	1779	1			T1	3		T2	26		T10	2
all_values[31]	1778	1			T1	4		T2	22		T10	2
all_values[32]	1724	1			T1	8		T2	20		T10	4
all_values[33]	1735	1			T1	4		T2	27		T10	1
all_values[34]	1834	1			T1	3		T2	24		T10	2
all_values[35]	1846	1			T1	5		T2	29		T10	4
all_values[36]	1829	1			T1	4		T2	33		T10	1
all_values[37]	1698	1			T1	8		T2	31		T10	3
all_values[38]	1803	1			T1	6		T2	39		T10	2
all_values[39]	1848	1			T1	5		T2	20		T10	7
all_values[40]	1829	1			T1	6		T2	29		T10	5
all_values[41]	1896	1			T1	5		T2	36		T10	5
all_values[42]	1882	1			T1	3		T2	26		T10	1
all_values[43]	1819	1			T1	8		T2	32		T10	1
all_values[44]	1767	1			T1	6		T2	29		T10	1
all_values[45]	1785	1			T1	4		T2	27		T10	3
all_values[46]	1834	1			T1	5		T2	32		T10	2
all_values[47]	1770	1			T1	9		T2	28		T10	4
all_values[48]	1799	1			T1	7		T2	34		T10	4
all_values[49]	1859	1			T1	7		T2	23		T10	3
all_values[50]	1895	1			T1	8		T2	23		T10	7
all_values[51]	1833	1			T1	9		T2	22		T10	1
all_values[52]	1794	1			T1	5		T2	19		T10	1
all_values[53]	1847	1			T1	4		T2	43		T10	2
all_values[54]	1789	1			T1	4		T2	25		T10	4
all_values[55]	1858	1			T1	3		T2	34		T10	4
all_values[56]	1883	1			T1	6		T2	18		T10	1
all_values[57]	1826	1			T1	7		T2	28		T10	4
all_values[58]	1772	1			T1	1		T2	30		T10	3
all_values[59]	1829	1			T1	4		T2	26		T10	5
all_values[60]	1858	1			T1	5		T2	20		T10	2
all_values[61]	1843	1			T1	2		T2	27		T10	2
all_values[62]	1845	1			T1	7		T2	24		T10	3
all_values[63]	1864	1			T1	9		T2	25		T10	3