Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.05	99.26	89.05	98.80		95.90	99.26	100.00

Total test records in report: 900

T57	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3293206671	Apr 02 12:53:18 PM PDT 24	Apr 02 12:53:25 PM PDT 24	239350653 ps
T760	/workspace/coverage/xbar_build_mode/49.xbar_error_random.3738187490	Apr 02 12:55:38 PM PDT 24	Apr 02 12:55:54 PM PDT 24	121792904 ps
T160	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.2233293892	Apr 02 12:55:01 PM PDT 24	Apr 02 12:55:57 PM PDT 24	5593820539 ps
T761	/workspace/coverage/xbar_build_mode/14.xbar_smoke.586979127	Apr 02 12:53:00 PM PDT 24	Apr 02 12:53:04 PM PDT 24	500111086 ps
T762	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2519632004	Apr 02 12:54:23 PM PDT 24	Apr 02 12:58:10 PM PDT 24	51469759988 ps
T763	/workspace/coverage/xbar_build_mode/36.xbar_error_random.2969114812	Apr 02 12:54:43 PM PDT 24	Apr 02 12:54:52 PM PDT 24	349091203 ps
T764	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4044824648	Apr 02 12:55:13 PM PDT 24	Apr 02 12:55:33 PM PDT 24	162791939 ps
T765	/workspace/coverage/xbar_build_mode/23.xbar_same_source.4220574567	Apr 02 12:53:42 PM PDT 24	Apr 02 12:54:18 PM PDT 24	3991890047 ps
T766	/workspace/coverage/xbar_build_mode/0.xbar_same_source.2844946505	Apr 02 12:52:19 PM PDT 24	Apr 02 12:52:23 PM PDT 24	100543158 ps
T767	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1743113314	Apr 02 12:54:17 PM PDT 24	Apr 02 12:59:37 PM PDT 24	18477103270 ps
T768	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1492064359	Apr 02 12:54:46 PM PDT 24	Apr 02 12:56:19 PM PDT 24	925279770 ps
T769	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3763063294	Apr 02 12:53:17 PM PDT 24	Apr 02 12:55:10 PM PDT 24	4102865007 ps
T770	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2693246487	Apr 02 12:55:15 PM PDT 24	Apr 02 12:55:38 PM PDT 24	327061418 ps
T771	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3236596958	Apr 02 12:53:22 PM PDT 24	Apr 02 12:53:26 PM PDT 24	28182768 ps
T772	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3225595238	Apr 02 12:55:15 PM PDT 24	Apr 02 12:59:20 PM PDT 24	3451334659 ps
T773	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.4272215046	Apr 02 12:53:29 PM PDT 24	Apr 02 12:53:35 PM PDT 24	159586870 ps
T774	/workspace/coverage/xbar_build_mode/18.xbar_smoke.176475078	Apr 02 12:53:19 PM PDT 24	Apr 02 12:53:23 PM PDT 24	234749372 ps
T775	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1986198297	Apr 02 12:52:37 PM PDT 24	Apr 02 12:52:45 PM PDT 24	237907448 ps
T776	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3043057064	Apr 02 12:55:00 PM PDT 24	Apr 02 12:56:42 PM PDT 24	279146520 ps
T777	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1392001938	Apr 02 12:52:43 PM PDT 24	Apr 02 12:53:45 PM PDT 24	20451104170 ps
T778	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3145118031	Apr 02 12:54:48 PM PDT 24	Apr 02 12:56:35 PM PDT 24	11261809723 ps
T112	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2663516320	Apr 02 12:53:30 PM PDT 24	Apr 02 12:53:41 PM PDT 24	659852253 ps
T779	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.358900829	Apr 02 12:53:56 PM PDT 24	Apr 02 12:56:49 PM PDT 24	2779691628 ps
T780	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.4043624012	Apr 02 12:52:38 PM PDT 24	Apr 02 12:53:24 PM PDT 24	1913902870 ps
T781	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2634642923	Apr 02 12:53:36 PM PDT 24	Apr 02 12:53:59 PM PDT 24	270160306 ps
T782	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.458495274	Apr 02 12:52:28 PM PDT 24	Apr 02 12:52:32 PM PDT 24	33184995 ps
T783	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2931859205	Apr 02 12:54:46 PM PDT 24	Apr 02 12:55:23 PM PDT 24	16815699124 ps
T784	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1103277989	Apr 02 12:53:52 PM PDT 24	Apr 02 12:57:27 PM PDT 24	41396173643 ps
T785	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1270405378	Apr 02 12:53:23 PM PDT 24	Apr 02 12:53:26 PM PDT 24	28576886 ps
T786	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1378002699	Apr 02 12:55:41 PM PDT 24	Apr 02 12:56:05 PM PDT 24	390241166 ps
T787	/workspace/coverage/xbar_build_mode/18.xbar_random.992847398	Apr 02 12:53:17 PM PDT 24	Apr 02 12:53:47 PM PDT 24	1164450182 ps
T788	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1460785181	Apr 02 12:54:20 PM PDT 24	Apr 02 12:54:53 PM PDT 24	164909963 ps
T789	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.4018176548	Apr 02 12:54:39 PM PDT 24	Apr 02 12:59:03 PM PDT 24	10692765926 ps
T790	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2975807546	Apr 02 12:52:18 PM PDT 24	Apr 02 12:52:45 PM PDT 24	2764313363 ps
T791	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2937661224	Apr 02 12:54:04 PM PDT 24	Apr 02 12:57:59 PM PDT 24	1022053639 ps
T27	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1973241507	Apr 02 12:53:57 PM PDT 24	Apr 02 01:00:19 PM PDT 24	1555753489 ps
T792	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3564788022	Apr 02 12:54:53 PM PDT 24	Apr 02 12:55:03 PM PDT 24	140457215 ps
T793	/workspace/coverage/xbar_build_mode/3.xbar_error_random.1161198095	Apr 02 12:52:29 PM PDT 24	Apr 02 12:52:44 PM PDT 24	171759021 ps
T794	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.960060666	Apr 02 12:55:25 PM PDT 24	Apr 02 12:55:52 PM PDT 24	602080632 ps
T795	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1061674879	Apr 02 12:54:24 PM PDT 24	Apr 02 12:54:28 PM PDT 24	130815039 ps
T796	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.213022354	Apr 02 12:52:37 PM PDT 24	Apr 02 12:53:05 PM PDT 24	4407066715 ps
T797	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2207482919	Apr 02 12:53:18 PM PDT 24	Apr 02 12:55:14 PM PDT 24	5864514272 ps
T29	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3869188232	Apr 02 12:54:29 PM PDT 24	Apr 02 01:00:51 PM PDT 24	18146710867 ps
T798	/workspace/coverage/xbar_build_mode/45.xbar_same_source.1260451591	Apr 02 12:55:17 PM PDT 24	Apr 02 12:55:40 PM PDT 24	334105230 ps
T799	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4035411443	Apr 02 12:53:04 PM PDT 24	Apr 02 01:06:27 PM PDT 24	103769831315 ps
T800	/workspace/coverage/xbar_build_mode/47.xbar_random.13879509	Apr 02 12:55:23 PM PDT 24	Apr 02 12:55:41 PM PDT 24	110405508 ps
T801	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.417968929	Apr 02 12:54:20 PM PDT 24	Apr 02 12:54:33 PM PDT 24	1484378180 ps
T802	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.247688961	Apr 02 12:53:29 PM PDT 24	Apr 02 12:53:59 PM PDT 24	244442227 ps
T803	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1771138685	Apr 02 12:52:20 PM PDT 24	Apr 02 12:53:21 PM PDT 24	9922037567 ps
T804	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.286296423	Apr 02 12:55:08 PM PDT 24	Apr 02 12:55:32 PM PDT 24	106635416 ps
T805	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.279554943	Apr 02 12:52:58 PM PDT 24	Apr 02 12:53:00 PM PDT 24	23697032 ps
T806	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1270513060	Apr 02 12:54:30 PM PDT 24	Apr 02 12:54:34 PM PDT 24	125404022 ps
T807	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.566604625	Apr 02 12:54:03 PM PDT 24	Apr 02 12:54:41 PM PDT 24	5314341966 ps
T808	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3231152835	Apr 02 12:53:49 PM PDT 24	Apr 02 12:56:04 PM PDT 24	6005046967 ps
T809	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3644052758	Apr 02 12:52:25 PM PDT 24	Apr 02 12:54:07 PM PDT 24	35184080887 ps
T810	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3957372971	Apr 02 12:53:50 PM PDT 24	Apr 02 12:54:20 PM PDT 24	4997783373 ps
T811	/workspace/coverage/xbar_build_mode/9.xbar_random.178510619	Apr 02 12:52:34 PM PDT 24	Apr 02 12:52:42 PM PDT 24	187283060 ps
T177	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.279189431	Apr 02 12:54:56 PM PDT 24	Apr 02 12:59:08 PM PDT 24	27696238779 ps
T812	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.3719888190	Apr 02 12:52:32 PM PDT 24	Apr 02 12:53:27 PM PDT 24	1557243411 ps
T813	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1628899764	Apr 02 12:53:11 PM PDT 24	Apr 02 12:53:29 PM PDT 24	459149122 ps
T814	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3777078804	Apr 02 12:53:59 PM PDT 24	Apr 02 12:54:25 PM PDT 24	2519092999 ps
T815	/workspace/coverage/xbar_build_mode/6.xbar_error_random.1330709905	Apr 02 12:52:26 PM PDT 24	Apr 02 12:53:01 PM PDT 24	1052810357 ps
T816	/workspace/coverage/xbar_build_mode/34.xbar_random.2652162915	Apr 02 12:54:30 PM PDT 24	Apr 02 12:54:43 PM PDT 24	257396555 ps
T817	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2367405755	Apr 02 12:54:20 PM PDT 24	Apr 02 12:54:58 PM PDT 24	16180663809 ps
T818	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.924804880	Apr 02 12:52:19 PM PDT 24	Apr 02 12:53:30 PM PDT 24	2149862675 ps
T819	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3941834023	Apr 02 12:53:14 PM PDT 24	Apr 02 12:53:36 PM PDT 24	2492638219 ps
T820	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3445783600	Apr 02 12:52:59 PM PDT 24	Apr 02 12:53:43 PM PDT 24	4334894576 ps
T821	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3440007601	Apr 02 12:54:01 PM PDT 24	Apr 02 12:57:40 PM PDT 24	857335122 ps
T822	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1141035560	Apr 02 12:52:59 PM PDT 24	Apr 02 12:53:30 PM PDT 24	4605666646 ps
T823	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2855687479	Apr 02 12:55:24 PM PDT 24	Apr 02 12:55:27 PM PDT 24	38278032 ps
T824	/workspace/coverage/xbar_build_mode/9.xbar_error_random.1194249667	Apr 02 12:52:37 PM PDT 24	Apr 02 12:52:56 PM PDT 24	605514311 ps
T825	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1078991997	Apr 02 12:52:08 PM PDT 24	Apr 02 12:52:34 PM PDT 24	4732708995 ps
T826	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.330753815	Apr 02 12:53:22 PM PDT 24	Apr 02 12:53:52 PM PDT 24	930444417 ps
T827	/workspace/coverage/xbar_build_mode/15.xbar_random.2535550531	Apr 02 12:53:11 PM PDT 24	Apr 02 12:53:43 PM PDT 24	2002016114 ps
T828	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4258990020	Apr 02 12:54:36 PM PDT 24	Apr 02 12:55:13 PM PDT 24	16398990178 ps
T829	/workspace/coverage/xbar_build_mode/36.xbar_smoke.2452869670	Apr 02 12:54:37 PM PDT 24	Apr 02 12:54:41 PM PDT 24	757789249 ps
T830	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1672188513	Apr 02 12:52:54 PM PDT 24	Apr 02 12:53:35 PM PDT 24	10906667453 ps
T831	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2167475494	Apr 02 12:52:55 PM PDT 24	Apr 02 12:54:22 PM PDT 24	2864218513 ps
T832	/workspace/coverage/xbar_build_mode/29.xbar_smoke.3903732351	Apr 02 12:54:06 PM PDT 24	Apr 02 12:54:09 PM PDT 24	87007986 ps
T833	/workspace/coverage/xbar_build_mode/19.xbar_random.1074694019	Apr 02 12:53:22 PM PDT 24	Apr 02 12:53:26 PM PDT 24	29111817 ps
T834	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1045376836	Apr 02 12:54:46 PM PDT 24	Apr 02 12:56:27 PM PDT 24	985314161 ps
T835	/workspace/coverage/xbar_build_mode/2.xbar_error_random.4239018685	Apr 02 12:52:28 PM PDT 24	Apr 02 12:52:44 PM PDT 24	248613696 ps
T836	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3033205171	Apr 02 12:52:30 PM PDT 24	Apr 02 12:54:28 PM PDT 24	5191785641 ps
T837	/workspace/coverage/xbar_build_mode/47.xbar_smoke.2866957753	Apr 02 12:55:17 PM PDT 24	Apr 02 12:55:21 PM PDT 24	340447781 ps
T838	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1948018547	Apr 02 12:54:35 PM PDT 24	Apr 02 12:55:03 PM PDT 24	237987426 ps
T839	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.256141142	Apr 02 12:55:27 PM PDT 24	Apr 02 12:56:23 PM PDT 24	2144614745 ps
T840	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2092625973	Apr 02 12:52:19 PM PDT 24	Apr 02 12:52:33 PM PDT 24	300048120 ps
T841	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.143109968	Apr 02 12:54:35 PM PDT 24	Apr 02 12:56:01 PM PDT 24	4103629272 ps
T842	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1327666965	Apr 02 12:55:19 PM PDT 24	Apr 02 01:05:25 PM PDT 24	185701251636 ps
T843	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1380706476	Apr 02 12:54:45 PM PDT 24	Apr 02 12:56:03 PM PDT 24	2487375304 ps
T844	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1849536881	Apr 02 12:52:45 PM PDT 24	Apr 02 12:53:18 PM PDT 24	13025769256 ps
T845	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2761729331	Apr 02 12:55:10 PM PDT 24	Apr 02 12:55:18 PM PDT 24	71305679 ps
T846	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.808844203	Apr 02 12:52:46 PM PDT 24	Apr 02 12:53:02 PM PDT 24	88511841 ps
T847	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.381381406	Apr 02 12:54:09 PM PDT 24	Apr 02 12:56:46 PM PDT 24	66103029135 ps
T848	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3709813150	Apr 02 12:53:18 PM PDT 24	Apr 02 12:53:21 PM PDT 24	33652653 ps
T849	/workspace/coverage/xbar_build_mode/33.xbar_smoke.3449316988	Apr 02 12:54:19 PM PDT 24	Apr 02 12:54:23 PM PDT 24	301768456 ps
T850	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1122841433	Apr 02 12:52:23 PM PDT 24	Apr 02 12:52:26 PM PDT 24	35815908 ps
T851	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2893323654	Apr 02 12:52:23 PM PDT 24	Apr 02 12:52:26 PM PDT 24	75423539 ps
T852	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1608516032	Apr 02 12:54:19 PM PDT 24	Apr 02 12:59:14 PM PDT 24	66414590238 ps
T853	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.4009389550	Apr 02 12:53:27 PM PDT 24	Apr 02 12:53:46 PM PDT 24	214422373 ps
T854	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3695828724	Apr 02 12:55:05 PM PDT 24	Apr 02 12:55:11 PM PDT 24	73710018 ps
T257	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.4114798116	Apr 02 12:55:15 PM PDT 24	Apr 02 12:56:27 PM PDT 24	34221372837 ps
T855	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1897966387	Apr 02 12:55:14 PM PDT 24	Apr 02 12:55:39 PM PDT 24	7600042467 ps
T856	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4111201179	Apr 02 12:52:42 PM PDT 24	Apr 02 12:55:30 PM PDT 24	34604919760 ps
T857	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.566488523	Apr 02 12:53:09 PM PDT 24	Apr 02 12:55:21 PM PDT 24	56935302879 ps
T858	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.94730555	Apr 02 12:52:40 PM PDT 24	Apr 02 12:52:48 PM PDT 24	422149523 ps
T859	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.492043640	Apr 02 12:54:44 PM PDT 24	Apr 02 12:57:57 PM PDT 24	19517165901 ps
T113	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2576080431	Apr 02 12:52:24 PM PDT 24	Apr 02 12:52:36 PM PDT 24	673784062 ps
T860	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1095858868	Apr 02 12:53:46 PM PDT 24	Apr 02 12:56:03 PM PDT 24	5734674583 ps
T861	/workspace/coverage/xbar_build_mode/27.xbar_random.4222042545	Apr 02 12:53:58 PM PDT 24	Apr 02 12:54:13 PM PDT 24	1122042363 ps
T862	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2521976892	Apr 02 12:54:53 PM PDT 24	Apr 02 12:55:08 PM PDT 24	1555654684 ps
T863	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3033789066	Apr 02 12:52:17 PM PDT 24	Apr 02 12:52:30 PM PDT 24	118338676 ps
T864	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3605001760	Apr 02 12:55:26 PM PDT 24	Apr 02 12:55:38 PM PDT 24	301058692 ps
T865	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1095717580	Apr 02 12:54:57 PM PDT 24	Apr 02 12:57:49 PM PDT 24	1374703931 ps
T866	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3021644645	Apr 02 12:53:12 PM PDT 24	Apr 02 12:55:53 PM PDT 24	10347718186 ps
T867	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2376030454	Apr 02 12:54:58 PM PDT 24	Apr 02 12:55:19 PM PDT 24	895317745 ps
T868	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2222875966	Apr 02 12:52:28 PM PDT 24	Apr 02 12:52:40 PM PDT 24	1134218360 ps
T869	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1317354000	Apr 02 12:53:59 PM PDT 24	Apr 02 12:54:53 PM PDT 24	483562891 ps
T870	/workspace/coverage/xbar_build_mode/7.xbar_error_random.3570468368	Apr 02 12:52:32 PM PDT 24	Apr 02 12:52:35 PM PDT 24	69743752 ps
T871	/workspace/coverage/xbar_build_mode/15.xbar_smoke.923728806	Apr 02 12:53:03 PM PDT 24	Apr 02 12:53:07 PM PDT 24	170759821 ps
T872	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.670293372	Apr 02 12:53:21 PM PDT 24	Apr 02 12:58:38 PM PDT 24	65158209540 ps
T873	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3976382137	Apr 02 12:52:12 PM PDT 24	Apr 02 12:52:38 PM PDT 24	2305526164 ps
T874	/workspace/coverage/xbar_build_mode/26.xbar_same_source.2323698158	Apr 02 12:53:52 PM PDT 24	Apr 02 12:54:27 PM PDT 24	4189088414 ps
T875	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2990896798	Apr 02 12:54:26 PM PDT 24	Apr 02 12:54:58 PM PDT 24	10396765906 ps
T876	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.331778709	Apr 02 12:54:51 PM PDT 24	Apr 02 12:55:18 PM PDT 24	13294647760 ps
T877	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1151557687	Apr 02 12:52:40 PM PDT 24	Apr 02 12:53:16 PM PDT 24	9548161669 ps
T878	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2021604695	Apr 02 12:55:30 PM PDT 24	Apr 02 12:58:58 PM PDT 24	9196338394 ps
T879	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2136282487	Apr 02 12:52:57 PM PDT 24	Apr 02 12:53:27 PM PDT 24	16133231044 ps
T880	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.434144101	Apr 02 12:52:55 PM PDT 24	Apr 02 12:53:25 PM PDT 24	5310689519 ps
T881	/workspace/coverage/xbar_build_mode/33.xbar_same_source.3794754711	Apr 02 12:54:24 PM PDT 24	Apr 02 12:54:26 PM PDT 24	53156036 ps
T882	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1569778493	Apr 02 12:54:02 PM PDT 24	Apr 02 12:59:48 PM PDT 24	4284882005 ps
T883	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.561370015	Apr 02 12:52:59 PM PDT 24	Apr 02 12:55:51 PM PDT 24	328378818 ps
T884	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.77991151	Apr 02 12:53:58 PM PDT 24	Apr 02 12:54:07 PM PDT 24	83525633 ps
T885	/workspace/coverage/xbar_build_mode/10.xbar_error_random.545158709	Apr 02 12:52:41 PM PDT 24	Apr 02 12:53:12 PM PDT 24	1060914150 ps
T886	/workspace/coverage/xbar_build_mode/42.xbar_random.2697919589	Apr 02 12:55:01 PM PDT 24	Apr 02 12:55:24 PM PDT 24	945528403 ps
T887	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2244236548	Apr 02 12:55:07 PM PDT 24	Apr 02 12:55:10 PM PDT 24	28500547 ps
T888	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.76144808	Apr 02 12:52:22 PM PDT 24	Apr 02 12:52:33 PM PDT 24	108117404 ps
T889	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.3510909193	Apr 02 12:53:28 PM PDT 24	Apr 02 12:55:42 PM PDT 24	4890808577 ps
T890	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.148011069	Apr 02 12:54:14 PM PDT 24	Apr 02 12:54:17 PM PDT 24	29314058 ps
T891	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1541224979	Apr 02 12:52:30 PM PDT 24	Apr 02 12:56:10 PM PDT 24	40518546461 ps
T892	/workspace/coverage/xbar_build_mode/32.xbar_error_random.3090650087	Apr 02 12:54:19 PM PDT 24	Apr 02 12:54:23 PM PDT 24	222276584 ps
T893	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3421991225	Apr 02 12:55:01 PM PDT 24	Apr 02 12:59:47 PM PDT 24	41586273666 ps
T894	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3192693234	Apr 02 12:55:27 PM PDT 24	Apr 02 12:57:33 PM PDT 24	322842133 ps
T895	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2087252632	Apr 02 12:53:07 PM PDT 24	Apr 02 12:53:27 PM PDT 24	166713372 ps
T896	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4041897696	Apr 02 12:53:52 PM PDT 24	Apr 02 12:54:04 PM PDT 24	143576028 ps
T897	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.2169456233	Apr 02 12:52:40 PM PDT 24	Apr 02 12:53:26 PM PDT 24	928199879 ps
T898	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1946804866	Apr 02 12:53:29 PM PDT 24	Apr 02 01:00:55 PM PDT 24	47941850439 ps
T899	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.246210098	Apr 02 12:52:40 PM PDT 24	Apr 02 12:52:43 PM PDT 24	75498006 ps
T251	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3649771525	Apr 02 12:53:58 PM PDT 24	Apr 02 12:55:31 PM PDT 24	46386124849 ps
T900	/workspace/coverage/xbar_build_mode/23.xbar_random.574000376	Apr 02 12:53:37 PM PDT 24	Apr 02 12:53:50 PM PDT 24	91986843 ps

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.1887472485
Short name	T1
Test name
Test status
Simulation time	6563259540 ps
CPU time	165.2 seconds
Started	Apr 02 12:55:38 PM PDT 24
Finished	Apr 02 12:58:24 PM PDT 24
Peak memory	207480 kb
Host	smart-c1fbd172-c7d2-430b-8d6a-f592d33db125
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1887472485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1887472485
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.927368567
Short name	T67
Test name
Test status
Simulation time	89329421059 ps
CPU time	578.17 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 01:02:02 PM PDT 24
Peak memory	207304 kb
Host	smart-674e35c0-18ed-4901-896c-f28f418c0ec6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=927368567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow _rsp.927368567
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.350375691
Short name	T258
Test name
Test status
Simulation time	357739206035 ps
CPU time	591.49 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 01:02:11 PM PDT 24
Peak memory	207284 kb
Host	smart-01ce2f93-30af-4aea-90f1-44a86f9a2655
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=350375691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.350375691
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4124116502
Short name	T20
Test name
Test status
Simulation time	7585284861 ps
CPU time	284.96 seconds
Started	Apr 02 12:53:13 PM PDT 24
Finished	Apr 02 12:57:58 PM PDT 24
Peak memory	219944 kb
Host	smart-29ef194d-7833-46b9-9889-61213097a4f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4124116502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.4124116502
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2215496027
Short name	T222
Test name
Test status
Simulation time	72651886636 ps
CPU time	445.58 seconds
Started	Apr 02 12:55:41 PM PDT 24
Finished	Apr 02 01:03:08 PM PDT 24
Peak memory	211776 kb
Host	smart-8e3de386-ec62-4cf8-91f8-e5d60334ff9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2215496027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.2215496027
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.993008181
Short name	T110
Test name
Test status
Simulation time	34837354718 ps
CPU time	272.86 seconds
Started	Apr 02 12:54:51 PM PDT 24
Finished	Apr 02 12:59:24 PM PDT 24
Peak memory	206704 kb
Host	smart-2108a938-a6c3-4bf2-bc80-6025c0b7d445
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=993008181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo w_rsp.993008181
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1190500879
Short name	T30
Test name
Test status
Simulation time	2285398816 ps
CPU time	176.04 seconds
Started	Apr 02 12:53:41 PM PDT 24
Finished	Apr 02 12:56:37 PM PDT 24
Peak memory	209100 kb
Host	smart-0b7d5fc4-06f7-4be5-aa08-019e2e68afad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1190500879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.1190500879
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2926109461
Short name	T13
Test name
Test status
Simulation time	344553973 ps
CPU time	9.69 seconds
Started	Apr 02 12:53:03 PM PDT 24
Finished	Apr 02 12:53:13 PM PDT 24
Peak memory	205724 kb
Host	smart-b50265e0-eeb8-4aa2-acf2-7c35fb0f669d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2926109461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2926109461
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2927597007
Short name	T101
Test name
Test status
Simulation time	4816400278 ps
CPU time	27.35 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:42 PM PDT 24
Peak memory	203444 kb
Host	smart-f34eea1c-4ada-4185-9cf1-3b490418c65f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927597007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2927597007
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.1297763139
Short name	T58
Test name
Test status
Simulation time	3686389649 ps
CPU time	113.11 seconds
Started	Apr 02 12:55:18 PM PDT 24
Finished	Apr 02 12:57:12 PM PDT 24
Peak memory	207056 kb
Host	smart-dd2722cb-92d6-422a-9fe2-6e2653aa0559
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1297763139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1297763139
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.3321824754
Short name	T98
Test name
Test status
Simulation time	18997852447 ps
CPU time	191.01 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:58:27 PM PDT 24
Peak memory	209172 kb
Host	smart-87d92c81-6cc5-4e9a-9256-67fb1f6ed309
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3321824754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3321824754
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.899555200
Short name	T135
Test name
Test status
Simulation time	912195444 ps
CPU time	225.75 seconds
Started	Apr 02 12:53:27 PM PDT 24
Finished	Apr 02 12:57:13 PM PDT 24
Peak memory	209612 kb
Host	smart-1a64cf9d-db6e-4046-bed5-19cd307b5e22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=899555200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand _reset.899555200
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.4029418165
Short name	T63
Test name
Test status
Simulation time	3124622954 ps
CPU time	135.1 seconds
Started	Apr 02 12:55:05 PM PDT 24
Finished	Apr 02 12:57:21 PM PDT 24
Peak memory	209180 kb
Host	smart-24be7dad-6fc8-4379-9a6f-5a78e51f6b8b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4029418165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4029418165
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1642464640
Short name	T2
Test name
Test status
Simulation time	2344159346 ps
CPU time	326.53 seconds
Started	Apr 02 12:53:30 PM PDT 24
Finished	Apr 02 12:58:57 PM PDT 24
Peak memory	223292 kb
Host	smart-81020b36-5921-440f-a7b2-657f40594768
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642464640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1642464640
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.294187932
Short name	T31
Test name
Test status
Simulation time	1573965635 ps
CPU time	422.92 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 01:01:25 PM PDT 24
Peak memory	211000 kb
Host	smart-074dfcb3-855d-4797-ab19-f2edb1c2eb9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=294187932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand _reset.294187932
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.467815391
Short name	T208
Test name
Test status
Simulation time	657143657 ps
CPU time	138.53 seconds
Started	Apr 02 12:55:12 PM PDT 24
Finished	Apr 02 12:57:31 PM PDT 24
Peak memory	208376 kb
Host	smart-93b407c7-971d-4421-8865-7bead24b9da4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=467815391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand _reset.467815391
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3185499827
Short name	T25
Test name
Test status
Simulation time	3181412736 ps
CPU time	81.87 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:54:54 PM PDT 24
Peak memory	208680 kb
Host	smart-d6242bb2-011c-4b2e-ae71-8443fb663a27
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3185499827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3185499827
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1563302745
Short name	T23
Test name
Test status
Simulation time	2487009658 ps
CPU time	189.14 seconds
Started	Apr 02 12:53:19 PM PDT 24
Finished	Apr 02 12:56:28 PM PDT 24
Peak memory	210592 kb
Host	smart-339b8dcf-563a-40f5-991a-ecd739cc3068
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563302745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1563302745
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.4058056107
Short name	T26
Test name
Test status
Simulation time	1969323689 ps
CPU time	346.97 seconds
Started	Apr 02 12:53:19 PM PDT 24
Finished	Apr 02 12:59:06 PM PDT 24
Peak memory	210260 kb
Host	smart-4080778e-029d-4a16-9505-8fe65ac9957e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4058056107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.4058056107
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3869188232
Short name	T29
Test name
Test status
Simulation time	18146710867 ps
CPU time	382.21 seconds
Started	Apr 02 12:54:29 PM PDT 24
Finished	Apr 02 01:00:51 PM PDT 24
Peak memory	220428 kb
Host	smart-438349dd-79fd-465a-a9a0-25870173a818
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3869188232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3869188232
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2951149761
Short name	T34
Test name
Test status
Simulation time	199203833 ps
CPU time	80.63 seconds
Started	Apr 02 12:54:40 PM PDT 24
Finished	Apr 02 12:56:00 PM PDT 24
Peak memory	209112 kb
Host	smart-647b70bd-15ad-49ba-ab8a-6b0974f3da33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2951149761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2951149761
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1436867118
Short name	T62
Test name
Test status
Simulation time	18398111955 ps
CPU time	126.42 seconds
Started	Apr 02 12:52:47 PM PDT 24
Finished	Apr 02 12:54:54 PM PDT 24
Peak memory	211656 kb
Host	smart-e108d979-1ee3-468c-9527-71b41958c1b2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1436867118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1436867118
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1821478229
Short name	T3
Test name
Test status
Simulation time	1739525248 ps
CPU time	28.3 seconds
Started	Apr 02 12:52:12 PM PDT 24
Finished	Apr 02 12:52:40 PM PDT 24
Peak memory	205764 kb
Host	smart-d23f5bce-c04b-47e3-af23-8b80c0d3de1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1821478229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1821478229
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2351924466
Short name	T596
Test name
Test status
Simulation time	15207545070 ps
CPU time	85.03 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:53:45 PM PDT 24
Peak memory	206216 kb
Host	smart-ac8accd7-0d37-4df4-a1a3-ee64eac483f0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2351924466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2351924466
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1412630519
Short name	T311
Test name
Test status
Simulation time	107995612 ps
CPU time	7.69 seconds
Started	Apr 02 12:52:15 PM PDT 24
Finished	Apr 02 12:52:23 PM PDT 24
Peak memory	203520 kb
Host	smart-651672c2-fe55-460e-8646-b759c9f2fb32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1412630519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1412630519
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.1560444978
Short name	T441
Test name
Test status
Simulation time	459206043 ps
CPU time	12.58 seconds
Started	Apr 02 12:52:09 PM PDT 24
Finished	Apr 02 12:52:22 PM PDT 24
Peak memory	203496 kb
Host	smart-e57ab3cd-471c-4398-bdf5-5c993bc7f2c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1560444978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1560444978
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.2744741409
Short name	T592
Test name
Test status
Simulation time	238521178 ps
CPU time	12.92 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:52:34 PM PDT 24
Peak memory	204676 kb
Host	smart-b4753560-0fd0-4366-8611-0c5a965a9be1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2744741409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2744741409
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2719199042
Short name	T435
Test name
Test status
Simulation time	20821738918 ps
CPU time	99.12 seconds
Started	Apr 02 12:52:10 PM PDT 24
Finished	Apr 02 12:53:50 PM PDT 24
Peak memory	211664 kb
Host	smart-db8d1130-224e-4183-9e3c-11ae0c424a21
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719199042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2719199042
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1070057277
Short name	T366
Test name
Test status
Simulation time	29406615608 ps
CPU time	58.48 seconds
Started	Apr 02 12:52:09 PM PDT 24
Finished	Apr 02 12:53:08 PM PDT 24
Peak memory	204904 kb
Host	smart-4a6d83fa-ac8b-4c61-a032-a378f0ceff6b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1070057277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1070057277
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.629087199
Short name	T341
Test name
Test status
Simulation time	173872092 ps
CPU time	9.57 seconds
Started	Apr 02 12:52:09 PM PDT 24
Finished	Apr 02 12:52:19 PM PDT 24
Peak memory	204628 kb
Host	smart-017515ea-c41d-4003-ae3d-814e08686f2b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629087199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.629087199
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.2844946505
Short name	T766
Test name
Test status
Simulation time	100543158 ps
CPU time	4.2 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:52:23 PM PDT 24
Peak memory	203776 kb
Host	smart-0e746143-a911-47b2-ab5e-fd1561a5fcd5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2844946505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2844946505
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.713968722
Short name	T284
Test name
Test status
Simulation time	41845026 ps
CPU time	2.75 seconds
Started	Apr 02 12:52:21 PM PDT 24
Finished	Apr 02 12:52:24 PM PDT 24
Peak memory	203516 kb
Host	smart-a90d05aa-6027-4579-a001-88e4458e6ea2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=713968722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.713968722
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2748350875
Short name	T706
Test name
Test status
Simulation time	4661903403 ps
CPU time	25.03 seconds
Started	Apr 02 12:52:10 PM PDT 24
Finished	Apr 02 12:52:36 PM PDT 24
Peak memory	203576 kb
Host	smart-4b10c106-c0f3-4910-9878-64b7b4f12094
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748350875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2748350875
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1078991997
Short name	T825
Test name
Test status
Simulation time	4732708995 ps
CPU time	25.66 seconds
Started	Apr 02 12:52:08 PM PDT 24
Finished	Apr 02 12:52:34 PM PDT 24
Peak memory	203512 kb
Host	smart-868e15a5-3074-477b-862e-da6c0258ff50
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1078991997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1078991997
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3771947022
Short name	T650
Test name
Test status
Simulation time	46532048 ps
CPU time	2.27 seconds
Started	Apr 02 12:52:09 PM PDT 24
Finished	Apr 02 12:52:12 PM PDT 24
Peak memory	203448 kb
Host	smart-89ad9c02-4acd-4ae4-8750-126685032418
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771947022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3771947022
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.897052389
Short name	T188
Test name
Test status
Simulation time	6245939520 ps
CPU time	185 seconds
Started	Apr 02 12:52:10 PM PDT 24
Finished	Apr 02 12:55:15 PM PDT 24
Peak memory	208764 kb
Host	smart-18457469-1636-4517-bbc5-ee8117d18e71
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=897052389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.897052389
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1771138685
Short name	T803
Test name
Test status
Simulation time	9922037567 ps
CPU time	60.9 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	205932 kb
Host	smart-7fe04250-8567-400e-a70a-fafc6b58f5cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1771138685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1771138685
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3043296971
Short name	T573
Test name
Test status
Simulation time	163851561 ps
CPU time	51.61 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:53:12 PM PDT 24
Peak memory	208300 kb
Host	smart-8e1fcc2a-608d-46b5-93c2-bbe216ebe482
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3043296971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3043296971
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.789461496
Short name	T429
Test name
Test status
Simulation time	2773731504 ps
CPU time	255.15 seconds
Started	Apr 02 12:52:09 PM PDT 24
Finished	Apr 02 12:56:24 PM PDT 24
Peak memory	219872 kb
Host	smart-596b0fe8-38c1-4cf1-822e-afd7d69093df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=789461496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese t_error.789461496
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1465107011
Short name	T327
Test name
Test status
Simulation time	1272456469 ps
CPU time	27.18 seconds
Started	Apr 02 12:52:10 PM PDT 24
Finished	Apr 02 12:52:38 PM PDT 24
Peak memory	205084 kb
Host	smart-262891ad-ef83-4f0f-9b8d-1ae671ff7bff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1465107011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1465107011
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3126336898
Short name	T427
Test name
Test status
Simulation time	2130345746 ps
CPU time	57.72 seconds
Started	Apr 02 12:52:13 PM PDT 24
Finished	Apr 02 12:53:11 PM PDT 24
Peak memory	206240 kb
Host	smart-52b8ed28-e6f8-4dc0-a761-137c9e99d916
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3126336898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3126336898
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2215629636
Short name	T499
Test name
Test status
Simulation time	108576861954 ps
CPU time	711.9 seconds
Started	Apr 02 12:52:14 PM PDT 24
Finished	Apr 02 01:04:07 PM PDT 24
Peak memory	206032 kb
Host	smart-4f42ee5f-d8c6-4aa4-babc-3981101dba92
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2215629636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2215629636
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3976382137
Short name	T873
Test name
Test status
Simulation time	2305526164 ps
CPU time	25.65 seconds
Started	Apr 02 12:52:12 PM PDT 24
Finished	Apr 02 12:52:38 PM PDT 24
Peak memory	204028 kb
Host	smart-78998114-1d27-4693-af26-204613c1064f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3976382137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3976382137
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.1009432042
Short name	T414
Test name
Test status
Simulation time	146810221 ps
CPU time	7.25 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:52:28 PM PDT 24
Peak memory	203508 kb
Host	smart-a24f987c-60b8-46ff-bc25-fd6c3e5b5349
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1009432042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1009432042
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.3807481033
Short name	T683
Test name
Test status
Simulation time	893607875 ps
CPU time	25.29 seconds
Started	Apr 02 12:52:15 PM PDT 24
Finished	Apr 02 12:52:40 PM PDT 24
Peak memory	211640 kb
Host	smart-e821ef08-9c18-4944-b86b-7a0811bc416d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3807481033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3807481033
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3377109890
Short name	T719
Test name
Test status
Simulation time	28679791624 ps
CPU time	185.26 seconds
Started	Apr 02 12:52:12 PM PDT 24
Finished	Apr 02 12:55:18 PM PDT 24
Peak memory	205480 kb
Host	smart-fd7ec745-0abb-41f6-bb3c-09de56b69bdc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377109890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3377109890
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2421999912
Short name	T83
Test name
Test status
Simulation time	27609601696 ps
CPU time	162.33 seconds
Started	Apr 02 12:52:21 PM PDT 24
Finished	Apr 02 12:55:04 PM PDT 24
Peak memory	205160 kb
Host	smart-be6121e3-26d1-4d9a-9828-0d899657d1c7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2421999912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2421999912
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3263694580
Short name	T641
Test name
Test status
Simulation time	74197002 ps
CPU time	7.68 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:52:36 PM PDT 24
Peak memory	211588 kb
Host	smart-769af311-b4c9-4359-82b5-80fd0f4487b7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263694580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3263694580
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.2591080931
Short name	T591
Test name
Test status
Simulation time	876980483 ps
CPU time	18.11 seconds
Started	Apr 02 12:52:15 PM PDT 24
Finished	Apr 02 12:52:34 PM PDT 24
Peak memory	204052 kb
Host	smart-df5e9910-c45e-4851-8094-235aabdd749f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2591080931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2591080931
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.3546570613
Short name	T247
Test name
Test status
Simulation time	153384653 ps
CPU time	2.42 seconds
Started	Apr 02 12:52:08 PM PDT 24
Finished	Apr 02 12:52:11 PM PDT 24
Peak memory	203416 kb
Host	smart-099d518c-d1a5-459b-a0b8-02020228f5dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3546570613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3546570613
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1778586248
Short name	T226
Test name
Test status
Simulation time	22414499452 ps
CPU time	36.65 seconds
Started	Apr 02 12:52:14 PM PDT 24
Finished	Apr 02 12:52:51 PM PDT 24
Peak memory	203568 kb
Host	smart-a9b87aa4-d6e2-4879-9ff9-d1cce90636eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778586248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1778586248
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.443554695
Short name	T552
Test name
Test status
Simulation time	7265411620 ps
CPU time	26.93 seconds
Started	Apr 02 12:52:12 PM PDT 24
Finished	Apr 02 12:52:39 PM PDT 24
Peak memory	203548 kb
Host	smart-5caaeb5b-88b6-47e3-858e-67b7378ad85c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=443554695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.443554695
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3829944804
Short name	T572
Test name
Test status
Simulation time	27881708 ps
CPU time	2.56 seconds
Started	Apr 02 12:52:14 PM PDT 24
Finished	Apr 02 12:52:16 PM PDT 24
Peak memory	203504 kb
Host	smart-0ce353df-b183-4829-9081-5975915d8495
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829944804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3829944804
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.3043348484
Short name	T152
Test name
Test status
Simulation time	1549173770 ps
CPU time	104.07 seconds
Started	Apr 02 12:52:13 PM PDT 24
Finished	Apr 02 12:53:57 PM PDT 24
Peak memory	208680 kb
Host	smart-cbce82fc-4a27-4baa-a12b-1fdd8a8176d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3043348484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3043348484
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1147581191
Short name	T710
Test name
Test status
Simulation time	622379705 ps
CPU time	58.3 seconds
Started	Apr 02 12:52:14 PM PDT 24
Finished	Apr 02 12:53:12 PM PDT 24
Peak memory	205124 kb
Host	smart-280d714f-511b-4d52-bd0b-d0992dcc1e0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1147581191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1147581191
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1958518061
Short name	T147
Test name
Test status
Simulation time	678928845 ps
CPU time	125.65 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:54:25 PM PDT 24
Peak memory	208464 kb
Host	smart-8bec777b-f274-4b7f-9679-b2c46233ff92
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1958518061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1958518061
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2038490461
Short name	T205
Test name
Test status
Simulation time	327932091 ps
CPU time	104.6 seconds
Started	Apr 02 12:52:15 PM PDT 24
Finished	Apr 02 12:54:00 PM PDT 24
Peak memory	209556 kb
Host	smart-7708fd75-9737-455c-8e1a-5fef903aebda
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2038490461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.2038490461
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1301498478
Short name	T438
Test name
Test status
Simulation time	77766006 ps
CPU time	9.75 seconds
Started	Apr 02 12:52:14 PM PDT 24
Finished	Apr 02 12:52:24 PM PDT 24
Peak memory	211676 kb
Host	smart-4f6a3629-baef-4da6-be6c-2dcb1fa9b4c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301498478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1301498478
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.4043624012
Short name	T780
Test name
Test status
Simulation time	1913902870 ps
CPU time	45.21 seconds
Started	Apr 02 12:52:38 PM PDT 24
Finished	Apr 02 12:53:24 PM PDT 24
Peak memory	204544 kb
Host	smart-277c53db-2c04-4291-8e28-6f12c51a1907
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4043624012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.4043624012
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1969499894
Short name	T593
Test name
Test status
Simulation time	164231873659 ps
CPU time	548.7 seconds
Started	Apr 02 12:52:42 PM PDT 24
Finished	Apr 02 01:01:51 PM PDT 24
Peak memory	207188 kb
Host	smart-a8cd0d65-5a55-4360-9434-f15d174357d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1969499894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1969499894
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2244292472
Short name	T28
Test name
Test status
Simulation time	291246584 ps
CPU time	12 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:52:51 PM PDT 24
Peak memory	203464 kb
Host	smart-da329c2a-91e6-41b0-9378-38a4b62ca5cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2244292472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2244292472
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.545158709
Short name	T885
Test name
Test status
Simulation time	1060914150 ps
CPU time	30.46 seconds
Started	Apr 02 12:52:41 PM PDT 24
Finished	Apr 02 12:53:12 PM PDT 24
Peak memory	203500 kb
Host	smart-3ced85bd-dd6c-49d3-a442-b87b1ac88459
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=545158709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.545158709
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.3155436960
Short name	T123
Test name
Test status
Simulation time	1413599890 ps
CPU time	41.84 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	211660 kb
Host	smart-f91f7cea-bed1-428c-a3e3-897505e89399
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3155436960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3155436960
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2443491236
Short name	T236
Test name
Test status
Simulation time	5186001689 ps
CPU time	30.01 seconds
Started	Apr 02 12:52:40 PM PDT 24
Finished	Apr 02 12:53:10 PM PDT 24
Peak memory	211712 kb
Host	smart-17074fa8-8c56-4c21-a535-9847ffc529f8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443491236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2443491236
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2344413790
Short name	T149
Test name
Test status
Simulation time	19550092555 ps
CPU time	171.72 seconds
Started	Apr 02 12:52:40 PM PDT 24
Finished	Apr 02 12:55:31 PM PDT 24
Peak memory	211756 kb
Host	smart-1fa691d7-fe8e-4383-81d3-47666d5f1f8b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2344413790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2344413790
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1511954583
Short name	T234
Test name
Test status
Simulation time	18518563 ps
CPU time	2.21 seconds
Started	Apr 02 12:52:38 PM PDT 24
Finished	Apr 02 12:52:41 PM PDT 24
Peak memory	203520 kb
Host	smart-f216b184-e7cc-44a4-99a4-ce8c6600e083
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511954583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1511954583
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.1742312721
Short name	T199
Test name
Test status
Simulation time	1424088646 ps
CPU time	15.5 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:52:54 PM PDT 24
Peak memory	203520 kb
Host	smart-e7292a02-2bf6-4495-9496-f628234e196e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1742312721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1742312721
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.814106221
Short name	T534
Test name
Test status
Simulation time	174289618 ps
CPU time	3.67 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:52:43 PM PDT 24
Peak memory	203488 kb
Host	smart-843c0d66-3ffa-4416-a936-8cc3a56edab4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=814106221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.814106221
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1151557687
Short name	T877
Test name
Test status
Simulation time	9548161669 ps
CPU time	35.79 seconds
Started	Apr 02 12:52:40 PM PDT 24
Finished	Apr 02 12:53:16 PM PDT 24
Peak memory	203572 kb
Host	smart-74464d81-edae-40d8-be8b-f11293a8c672
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151557687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1151557687
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.913187597
Short name	T612
Test name
Test status
Simulation time	2387627868 ps
CPU time	17.6 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:52:57 PM PDT 24
Peak memory	203556 kb
Host	smart-a7d07c8f-daf9-47b0-8e1b-29efe0168a0f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=913187597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.913187597
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.246210098
Short name	T899
Test name
Test status
Simulation time	75498006 ps
CPU time	2.61 seconds
Started	Apr 02 12:52:40 PM PDT 24
Finished	Apr 02 12:52:43 PM PDT 24
Peak memory	203500 kb
Host	smart-796e4fde-0a05-4f5b-839b-717d00d7cb0a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246210098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.246210098
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.2169456233
Short name	T897
Test name
Test status
Simulation time	928199879 ps
CPU time	45.11 seconds
Started	Apr 02 12:52:40 PM PDT 24
Finished	Apr 02 12:53:26 PM PDT 24
Peak memory	206164 kb
Host	smart-727a1573-b8c3-4d0f-b7e3-3eba0187deed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2169456233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2169456233
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4111201179
Short name	T856
Test name
Test status
Simulation time	34604919760 ps
CPU time	168.06 seconds
Started	Apr 02 12:52:42 PM PDT 24
Finished	Apr 02 12:55:30 PM PDT 24
Peak memory	208320 kb
Host	smart-0a5daf4e-3c14-4b2e-a5e4-a34384e1e647
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4111201179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4111201179
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2153551526
Short name	T466
Test name
Test status
Simulation time	3566878191 ps
CPU time	296.98 seconds
Started	Apr 02 12:52:41 PM PDT 24
Finished	Apr 02 12:57:38 PM PDT 24
Peak memory	208560 kb
Host	smart-d1f5ae7e-6d44-4a1c-8e88-59cb6a3ce55e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2153551526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2153551526
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3037489505
Short name	T321
Test name
Test status
Simulation time	7954713 ps
CPU time	8.8 seconds
Started	Apr 02 12:52:46 PM PDT 24
Finished	Apr 02 12:52:55 PM PDT 24
Peak memory	203392 kb
Host	smart-11a3a972-fccd-4d54-8e93-2b8b60783036
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3037489505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.3037489505
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.94730555
Short name	T858
Test name
Test status
Simulation time	422149523 ps
CPU time	8.2 seconds
Started	Apr 02 12:52:40 PM PDT 24
Finished	Apr 02 12:52:48 PM PDT 24
Peak memory	204992 kb
Host	smart-c62256d4-f112-47f5-af68-a8290332b52e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=94730555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.94730555
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3121368760
Short name	T86
Test name
Test status
Simulation time	692431402 ps
CPU time	9.34 seconds
Started	Apr 02 12:52:42 PM PDT 24
Finished	Apr 02 12:52:52 PM PDT 24
Peak memory	203856 kb
Host	smart-86b937a8-3b48-4988-8329-b9864ee581be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3121368760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3121368760
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2769644238
Short name	T418
Test name
Test status
Simulation time	2579452145 ps
CPU time	23.6 seconds
Started	Apr 02 12:52:50 PM PDT 24
Finished	Apr 02 12:53:14 PM PDT 24
Peak memory	204040 kb
Host	smart-9bf80b86-01bf-41bd-9564-77b965a27d66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2769644238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2769644238
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.3906879968
Short name	T410
Test name
Test status
Simulation time	3079596621 ps
CPU time	33.09 seconds
Started	Apr 02 12:52:48 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	203556 kb
Host	smart-258e6b3d-f0ed-4abb-88e1-78d36babb8ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906879968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3906879968
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.3526544324
Short name	T563
Test name
Test status
Simulation time	142360083 ps
CPU time	16.76 seconds
Started	Apr 02 12:52:43 PM PDT 24
Finished	Apr 02 12:52:59 PM PDT 24
Peak memory	204848 kb
Host	smart-7ea70706-5311-4631-8d65-94bd010f3ba7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3526544324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3526544324
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1392001938
Short name	T777
Test name
Test status
Simulation time	20451104170 ps
CPU time	61.99 seconds
Started	Apr 02 12:52:43 PM PDT 24
Finished	Apr 02 12:53:45 PM PDT 24
Peak memory	211708 kb
Host	smart-f9027054-fd01-4fd6-8b88-97aa5d91895a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392001938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1392001938
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.4048413913
Short name	T557
Test name
Test status
Simulation time	5542810634 ps
CPU time	39.2 seconds
Started	Apr 02 12:52:44 PM PDT 24
Finished	Apr 02 12:53:23 PM PDT 24
Peak memory	204780 kb
Host	smart-b7051427-a5b3-4faf-ae7e-6ebb1a25dcdc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4048413913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4048413913
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.3426913857
Short name	T156
Test name
Test status
Simulation time	247255541 ps
CPU time	14.1 seconds
Started	Apr 02 12:52:44 PM PDT 24
Finished	Apr 02 12:52:58 PM PDT 24
Peak memory	211708 kb
Host	smart-d12ea5a8-e989-4657-9b19-45bc505ca010
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426913857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3426913857
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.1793595147
Short name	T571
Test name
Test status
Simulation time	2734776048 ps
CPU time	18.57 seconds
Started	Apr 02 12:52:49 PM PDT 24
Finished	Apr 02 12:53:08 PM PDT 24
Peak memory	204104 kb
Host	smart-b3d72aba-cdf6-4c8e-a878-4d3029c9e7ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1793595147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1793595147
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.3310436143
Short name	T698
Test name
Test status
Simulation time	202517405 ps
CPU time	3.71 seconds
Started	Apr 02 12:52:43 PM PDT 24
Finished	Apr 02 12:52:47 PM PDT 24
Peak memory	203472 kb
Host	smart-81507f4c-db7c-4f0d-8856-3517313b7682
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3310436143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3310436143
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1849536881
Short name	T844
Test name
Test status
Simulation time	13025769256 ps
CPU time	32.09 seconds
Started	Apr 02 12:52:45 PM PDT 24
Finished	Apr 02 12:53:18 PM PDT 24
Peak memory	203568 kb
Host	smart-e95d3510-bbe0-465d-8b77-dbcd4b17f648
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849536881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1849536881
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2009385596
Short name	T628
Test name
Test status
Simulation time	8990112751 ps
CPU time	33.45 seconds
Started	Apr 02 12:52:42 PM PDT 24
Finished	Apr 02 12:53:16 PM PDT 24
Peak memory	203508 kb
Host	smart-70166c79-3031-47b5-85d4-0745efdb9c27
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2009385596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2009385596
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2573318967
Short name	T173
Test name
Test status
Simulation time	34683830 ps
CPU time	2.48 seconds
Started	Apr 02 12:52:43 PM PDT 24
Finished	Apr 02 12:52:46 PM PDT 24
Peak memory	203492 kb
Host	smart-0066549a-d444-4796-96f0-b35a67fcb722
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573318967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2573318967
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.2095957166
Short name	T756
Test name
Test status
Simulation time	727430275 ps
CPU time	93.38 seconds
Started	Apr 02 12:52:48 PM PDT 24
Finished	Apr 02 12:54:22 PM PDT 24
Peak memory	206976 kb
Host	smart-f2531ba9-77c4-478b-8394-a072b763aaa0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2095957166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2095957166
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2949075400
Short name	T699
Test name
Test status
Simulation time	2200197077 ps
CPU time	35.09 seconds
Started	Apr 02 12:52:48 PM PDT 24
Finished	Apr 02 12:53:23 PM PDT 24
Peak memory	203824 kb
Host	smart-33ffcb5c-bec8-4e82-acd7-e12d3b23c0f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2949075400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2949075400
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3455888774
Short name	T433
Test name
Test status
Simulation time	2875263257 ps
CPU time	168.89 seconds
Started	Apr 02 12:52:50 PM PDT 24
Finished	Apr 02 12:55:39 PM PDT 24
Peak memory	208320 kb
Host	smart-0bfaba69-1042-407e-be5f-14205f715f59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3455888774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.3455888774
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1890205929
Short name	T494
Test name
Test status
Simulation time	283505346 ps
CPU time	58.51 seconds
Started	Apr 02 12:52:46 PM PDT 24
Finished	Apr 02 12:53:45 PM PDT 24
Peak memory	207972 kb
Host	smart-1765effc-8ac2-4143-8e64-5b03515f9d90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1890205929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1890205929
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.808844203
Short name	T846
Test name
Test status
Simulation time	88511841 ps
CPU time	15 seconds
Started	Apr 02 12:52:46 PM PDT 24
Finished	Apr 02 12:53:02 PM PDT 24
Peak memory	211708 kb
Host	smart-52842d7b-f3d5-4836-8762-e27a462254f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808844203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.808844203
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.494874052
Short name	T401
Test name
Test status
Simulation time	167384790 ps
CPU time	10.87 seconds
Started	Apr 02 12:52:51 PM PDT 24
Finished	Apr 02 12:53:02 PM PDT 24
Peak memory	204476 kb
Host	smart-1ab354da-f76b-487d-bcf6-aa3783720997
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=494874052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.494874052
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.270634921
Short name	T595
Test name
Test status
Simulation time	571084782643 ps
CPU time	1166.21 seconds
Started	Apr 02 12:52:50 PM PDT 24
Finished	Apr 02 01:12:17 PM PDT 24
Peak memory	207724 kb
Host	smart-9654298c-1fb5-4ac9-9044-704ced81dad7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=270634921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slo w_rsp.270634921
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2888190552
Short name	T227
Test name
Test status
Simulation time	657389469 ps
CPU time	6.18 seconds
Started	Apr 02 12:52:49 PM PDT 24
Finished	Apr 02 12:52:56 PM PDT 24
Peak memory	203796 kb
Host	smart-5a445ff6-369b-407f-95c7-8c0372605dfd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2888190552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2888190552
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.2551404779
Short name	T445
Test name
Test status
Simulation time	227906771 ps
CPU time	28.14 seconds
Started	Apr 02 12:52:53 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	203504 kb
Host	smart-d699ef67-37b3-4833-a842-947f6708ea57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2551404779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2551404779
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.1449819978
Short name	T510
Test name
Test status
Simulation time	88979389 ps
CPU time	9.87 seconds
Started	Apr 02 12:52:47 PM PDT 24
Finished	Apr 02 12:52:57 PM PDT 24
Peak memory	204596 kb
Host	smart-463caa62-f986-4802-81c2-cf47ba6d3754
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1449819978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1449819978
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1558808308
Short name	T181
Test name
Test status
Simulation time	87172635483 ps
CPU time	244.18 seconds
Started	Apr 02 12:52:47 PM PDT 24
Finished	Apr 02 12:56:52 PM PDT 24
Peak memory	211748 kb
Host	smart-5a6b0a5f-43fe-411f-b0de-f2eb70c20b1c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558808308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1558808308
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2445580734
Short name	T6
Test name
Test status
Simulation time	12045948090 ps
CPU time	100.51 seconds
Started	Apr 02 12:52:51 PM PDT 24
Finished	Apr 02 12:54:32 PM PDT 24
Peak memory	205208 kb
Host	smart-1452efee-0654-418d-af9a-f89a8d9e3173
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2445580734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2445580734
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2494722224
Short name	T383
Test name
Test status
Simulation time	374888242 ps
CPU time	8.7 seconds
Started	Apr 02 12:52:47 PM PDT 24
Finished	Apr 02 12:52:55 PM PDT 24
Peak memory	211620 kb
Host	smart-bffb6099-c138-4224-8c68-aa8e50eef614
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494722224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2494722224
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.1922135878
Short name	T652
Test name
Test status
Simulation time	96805474 ps
CPU time	4.56 seconds
Started	Apr 02 12:52:51 PM PDT 24
Finished	Apr 02 12:52:56 PM PDT 24
Peak memory	203740 kb
Host	smart-b30cf552-521a-42d3-a545-4a04d0c84f28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1922135878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1922135878
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.2386941010
Short name	T377
Test name
Test status
Simulation time	149236024 ps
CPU time	3.6 seconds
Started	Apr 02 12:52:50 PM PDT 24
Finished	Apr 02 12:52:54 PM PDT 24
Peak memory	203496 kb
Host	smart-d153cc5e-b803-485d-83de-556f451e70a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2386941010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2386941010
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.354172209
Short name	T581
Test name
Test status
Simulation time	4956950870 ps
CPU time	30.53 seconds
Started	Apr 02 12:52:48 PM PDT 24
Finished	Apr 02 12:53:19 PM PDT 24
Peak memory	203516 kb
Host	smart-9cd64f86-3f25-47fb-832f-ac44c391d5a6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=354172209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.354172209
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3064530596
Short name	T295
Test name
Test status
Simulation time	1922262177 ps
CPU time	18.46 seconds
Started	Apr 02 12:52:47 PM PDT 24
Finished	Apr 02 12:53:06 PM PDT 24
Peak memory	203484 kb
Host	smart-b55bdf87-d8a6-4c12-a516-b5ba86770c11
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3064530596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3064530596
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3270874772
Short name	T609
Test name
Test status
Simulation time	29525481 ps
CPU time	2.08 seconds
Started	Apr 02 12:52:49 PM PDT 24
Finished	Apr 02 12:52:52 PM PDT 24
Peak memory	203496 kb
Host	smart-bf777d8f-5ee3-4439-8d25-9e32338f3e7d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270874772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3270874772
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.2997290920
Short name	T49
Test name
Test status
Simulation time	6700298862 ps
CPU time	230.43 seconds
Started	Apr 02 12:52:51 PM PDT 24
Finished	Apr 02 12:56:41 PM PDT 24
Peak memory	209608 kb
Host	smart-2c229804-f98c-40e6-a9a0-2752216ddbcd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2997290920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2997290920
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2167475494
Short name	T831
Test name
Test status
Simulation time	2864218513 ps
CPU time	87.34 seconds
Started	Apr 02 12:52:55 PM PDT 24
Finished	Apr 02 12:54:22 PM PDT 24
Peak memory	205924 kb
Host	smart-fb24e5ec-5421-4595-bd8b-75c8288880c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2167475494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2167475494
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3369937774
Short name	T702
Test name
Test status
Simulation time	1066467460 ps
CPU time	403.34 seconds
Started	Apr 02 12:52:55 PM PDT 24
Finished	Apr 02 12:59:38 PM PDT 24
Peak memory	208816 kb
Host	smart-a2db3094-2c0f-473b-8479-b89ae1f1329b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3369937774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3369937774
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3222519569
Short name	T626
Test name
Test status
Simulation time	8035318549 ps
CPU time	229.9 seconds
Started	Apr 02 12:52:53 PM PDT 24
Finished	Apr 02 12:56:43 PM PDT 24
Peak memory	209108 kb
Host	smart-c3dee529-ec14-4aee-b9a3-b13031b68f6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3222519569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3222519569
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1334954665
Short name	T241
Test name
Test status
Simulation time	1203508197 ps
CPU time	21.51 seconds
Started	Apr 02 12:52:50 PM PDT 24
Finished	Apr 02 12:53:12 PM PDT 24
Peak memory	205076 kb
Host	smart-8599aae9-7818-4afc-beb4-0fa5aab8088a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1334954665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1334954665
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2856465839
Short name	T153
Test name
Test status
Simulation time	352375744 ps
CPU time	27.63 seconds
Started	Apr 02 12:53:01 PM PDT 24
Finished	Apr 02 12:53:29 PM PDT 24
Peak memory	205756 kb
Host	smart-188b5132-ecb7-43ff-ad4b-fe0ff72e4087
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2856465839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2856465839
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.744530881
Short name	T589
Test name
Test status
Simulation time	50083898869 ps
CPU time	383.54 seconds
Started	Apr 02 12:52:59 PM PDT 24
Finished	Apr 02 12:59:23 PM PDT 24
Peak memory	211752 kb
Host	smart-581e4fc5-a364-4971-ba39-2490d1e45db4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=744530881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo w_rsp.744530881
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.576040080
Short name	T375
Test name
Test status
Simulation time	1050493191 ps
CPU time	30.67 seconds
Started	Apr 02 12:53:02 PM PDT 24
Finished	Apr 02 12:53:33 PM PDT 24
Peak memory	204192 kb
Host	smart-4f07695c-f6bc-4842-95f7-52b4d275094a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=576040080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.576040080
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.4092580808
Short name	T666
Test name
Test status
Simulation time	241139008 ps
CPU time	21.63 seconds
Started	Apr 02 12:53:00 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	203416 kb
Host	smart-3648fd73-fedb-41b1-a999-72d05f27fe3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4092580808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4092580808
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.4161148063
Short name	T157
Test name
Test status
Simulation time	116124022 ps
CPU time	4.67 seconds
Started	Apr 02 12:52:54 PM PDT 24
Finished	Apr 02 12:52:59 PM PDT 24
Peak memory	204056 kb
Host	smart-c2040fe5-d639-4392-a0ea-c1934a6fb798
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4161148063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.4161148063
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2834117227
Short name	T159
Test name
Test status
Simulation time	30218875044 ps
CPU time	190.05 seconds
Started	Apr 02 12:52:54 PM PDT 24
Finished	Apr 02 12:56:04 PM PDT 24
Peak memory	211720 kb
Host	smart-6c1e24e5-1e35-49d7-be98-e8263c844d26
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834117227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2834117227
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1141035560
Short name	T822
Test name
Test status
Simulation time	4605666646 ps
CPU time	30.19 seconds
Started	Apr 02 12:52:59 PM PDT 24
Finished	Apr 02 12:53:30 PM PDT 24
Peak memory	204632 kb
Host	smart-fea31803-3ff7-4cd7-9d82-bac6e6d1280d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1141035560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1141035560
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1404552117
Short name	T525
Test name
Test status
Simulation time	109346063 ps
CPU time	14.34 seconds
Started	Apr 02 12:52:56 PM PDT 24
Finished	Apr 02 12:53:10 PM PDT 24
Peak memory	204856 kb
Host	smart-6736b9c3-693f-4369-bbf8-51c125e35de5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404552117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1404552117
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.2704037887
Short name	T746
Test name
Test status
Simulation time	209547092 ps
CPU time	10.47 seconds
Started	Apr 02 12:52:59 PM PDT 24
Finished	Apr 02 12:53:09 PM PDT 24
Peak memory	204072 kb
Host	smart-b2b26149-3d7f-4dc6-902c-98acea355272
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2704037887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2704037887
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.575897607
Short name	T245
Test name
Test status
Simulation time	201600485 ps
CPU time	3.61 seconds
Started	Apr 02 12:52:54 PM PDT 24
Finished	Apr 02 12:52:57 PM PDT 24
Peak memory	203504 kb
Host	smart-d0a46719-1cce-4671-af2a-ba1fdfb388ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=575897607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.575897607
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1672188513
Short name	T830
Test name
Test status
Simulation time	10906667453 ps
CPU time	40.79 seconds
Started	Apr 02 12:52:54 PM PDT 24
Finished	Apr 02 12:53:35 PM PDT 24
Peak memory	203572 kb
Host	smart-8211e305-7f2f-4986-86d6-31b694d67a1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672188513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1672188513
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.434144101
Short name	T880
Test name
Test status
Simulation time	5310689519 ps
CPU time	30.07 seconds
Started	Apr 02 12:52:55 PM PDT 24
Finished	Apr 02 12:53:25 PM PDT 24
Peak memory	203560 kb
Host	smart-bf6360e1-dbf5-43c7-948a-bcc24fcc53b8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=434144101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.434144101
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3083964078
Short name	T695
Test name
Test status
Simulation time	32712837 ps
CPU time	2.18 seconds
Started	Apr 02 12:52:55 PM PDT 24
Finished	Apr 02 12:52:57 PM PDT 24
Peak memory	203508 kb
Host	smart-0f3d2a0f-8926-45dd-9af7-aa5c14a1eb71
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083964078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3083964078
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.1215286373
Short name	T171
Test name
Test status
Simulation time	1769558512 ps
CPU time	99.33 seconds
Started	Apr 02 12:52:57 PM PDT 24
Finished	Apr 02 12:54:36 PM PDT 24
Peak memory	208540 kb
Host	smart-8999bbda-d006-4a96-ac5a-5d86c0148d37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1215286373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1215286373
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3445783600
Short name	T820
Test name
Test status
Simulation time	4334894576 ps
CPU time	43.08 seconds
Started	Apr 02 12:52:59 PM PDT 24
Finished	Apr 02 12:53:43 PM PDT 24
Peak memory	204668 kb
Host	smart-0c05101a-80fa-4a79-b5b6-9e6a75d02a5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3445783600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3445783600
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1877228261
Short name	T674
Test name
Test status
Simulation time	1645466540 ps
CPU time	379.48 seconds
Started	Apr 02 12:53:04 PM PDT 24
Finished	Apr 02 12:59:24 PM PDT 24
Peak memory	211952 kb
Host	smart-354b5b1e-a9b1-459a-8117-1d720f7918e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1877228261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1877228261
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.561370015
Short name	T883
Test name
Test status
Simulation time	328378818 ps
CPU time	172.4 seconds
Started	Apr 02 12:52:59 PM PDT 24
Finished	Apr 02 12:55:51 PM PDT 24
Peak memory	211448 kb
Host	smart-6e7b4b7e-bd7d-4855-85c7-5c60dfcd4e97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561370015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.561370015
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3413599609
Short name	T88
Test name
Test status
Simulation time	848273750 ps
CPU time	27.44 seconds
Started	Apr 02 12:52:58 PM PDT 24
Finished	Apr 02 12:53:26 PM PDT 24
Peak memory	205244 kb
Host	smart-dc0d6b3a-e5f8-4924-945e-d77b52cc33a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3413599609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3413599609
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4035411443
Short name	T799
Test name
Test status
Simulation time	103769831315 ps
CPU time	803.15 seconds
Started	Apr 02 12:53:04 PM PDT 24
Finished	Apr 02 01:06:27 PM PDT 24
Peak memory	207528 kb
Host	smart-934c916c-fa4e-460d-8537-08cbf7b78b53
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4035411443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.4035411443
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2589626806
Short name	T380
Test name
Test status
Simulation time	284782052 ps
CPU time	2.55 seconds
Started	Apr 02 12:53:04 PM PDT 24
Finished	Apr 02 12:53:07 PM PDT 24
Peak memory	203496 kb
Host	smart-e3c5c930-ddb2-44fe-acb6-1459a732aee1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2589626806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2589626806
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.1771715869
Short name	T303
Test name
Test status
Simulation time	828262053 ps
CPU time	31.82 seconds
Started	Apr 02 12:53:01 PM PDT 24
Finished	Apr 02 12:53:33 PM PDT 24
Peak memory	203432 kb
Host	smart-2fe8f93f-27b2-4fcc-a8cf-a3500ebe4184
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1771715869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1771715869
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.3324433599
Short name	T496
Test name
Test status
Simulation time	51893294 ps
CPU time	7.52 seconds
Started	Apr 02 12:52:58 PM PDT 24
Finished	Apr 02 12:53:05 PM PDT 24
Peak memory	204608 kb
Host	smart-270c636c-5f17-4a77-ae62-91b3e7d77969
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3324433599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3324433599
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1232005575
Short name	T368
Test name
Test status
Simulation time	51644821690 ps
CPU time	249.05 seconds
Started	Apr 02 12:52:58 PM PDT 24
Finished	Apr 02 12:57:07 PM PDT 24
Peak memory	205148 kb
Host	smart-216b68d2-e86a-4638-a532-edacad3e977a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232005575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1232005575
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2582584217
Short name	T471
Test name
Test status
Simulation time	2974708799 ps
CPU time	12.65 seconds
Started	Apr 02 12:52:57 PM PDT 24
Finished	Apr 02 12:53:09 PM PDT 24
Peak memory	203572 kb
Host	smart-d6a44e5d-b520-4c62-be2b-d85f3453b05c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2582584217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2582584217
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.581287283
Short name	T491
Test name
Test status
Simulation time	215258836 ps
CPU time	26.96 seconds
Started	Apr 02 12:53:04 PM PDT 24
Finished	Apr 02 12:53:31 PM PDT 24
Peak memory	204772 kb
Host	smart-6dfb57e7-5ded-4d34-978d-88cb98ce06fe
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581287283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.581287283
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.2348832629
Short name	T469
Test name
Test status
Simulation time	35644356 ps
CPU time	1.68 seconds
Started	Apr 02 12:53:02 PM PDT 24
Finished	Apr 02 12:53:04 PM PDT 24
Peak memory	203524 kb
Host	smart-d448590a-8885-4ea0-9418-8eae9129c947
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348832629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2348832629
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.586979127
Short name	T761
Test name
Test status
Simulation time	500111086 ps
CPU time	3.39 seconds
Started	Apr 02 12:53:00 PM PDT 24
Finished	Apr 02 12:53:04 PM PDT 24
Peak memory	203416 kb
Host	smart-60f54922-7f43-48ee-89fa-f765725fa0a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=586979127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.586979127
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2020648301
Short name	T326
Test name
Test status
Simulation time	6001276847 ps
CPU time	35.03 seconds
Started	Apr 02 12:52:58 PM PDT 24
Finished	Apr 02 12:53:33 PM PDT 24
Peak memory	203552 kb
Host	smart-f0890a30-d3a3-404f-8402-a13f61bc5dab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020648301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2020648301
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2136282487
Short name	T879
Test name
Test status
Simulation time	16133231044 ps
CPU time	29.62 seconds
Started	Apr 02 12:52:57 PM PDT 24
Finished	Apr 02 12:53:27 PM PDT 24
Peak memory	203440 kb
Host	smart-bed89709-fdae-49d9-ba66-561ceb4104eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2136282487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2136282487
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.279554943
Short name	T805
Test name
Test status
Simulation time	23697032 ps
CPU time	2.02 seconds
Started	Apr 02 12:52:58 PM PDT 24
Finished	Apr 02 12:53:00 PM PDT 24
Peak memory	203448 kb
Host	smart-8d27df30-eb70-48f2-8763-632b7580f1d5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279554943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.279554943
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.2585301389
Short name	T755
Test name
Test status
Simulation time	882762879 ps
CPU time	123.83 seconds
Started	Apr 02 12:53:05 PM PDT 24
Finished	Apr 02 12:55:09 PM PDT 24
Peak memory	209400 kb
Host	smart-962653cf-f985-4914-8540-b5dc629a49dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2585301389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2585301389
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1609409793
Short name	T269
Test name
Test status
Simulation time	6983756541 ps
CPU time	250.65 seconds
Started	Apr 02 12:53:05 PM PDT 24
Finished	Apr 02 12:57:16 PM PDT 24
Peak memory	209448 kb
Host	smart-70d9d84b-5f9f-4b99-99b2-aca204ce2dbc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1609409793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1609409793
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3221311098
Short name	T635
Test name
Test status
Simulation time	353800619 ps
CPU time	151.48 seconds
Started	Apr 02 12:53:03 PM PDT 24
Finished	Apr 02 12:55:34 PM PDT 24
Peak memory	209500 kb
Host	smart-37565fb1-3ee0-4cf8-90b6-e7e9013d3647
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221311098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.3221311098
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2469298478
Short name	T446
Test name
Test status
Simulation time	119016917 ps
CPU time	45.03 seconds
Started	Apr 02 12:53:01 PM PDT 24
Finished	Apr 02 12:53:46 PM PDT 24
Peak memory	208000 kb
Host	smart-8ecf2e1b-409c-472b-8a4b-28ff5ebc3bb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2469298478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2469298478
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2087252632
Short name	T895
Test name
Test status
Simulation time	166713372 ps
CPU time	20.72 seconds
Started	Apr 02 12:53:07 PM PDT 24
Finished	Apr 02 12:53:27 PM PDT 24
Peak memory	211664 kb
Host	smart-018d948e-9edf-4fd0-a94c-ac832d32230d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2087252632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2087252632
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2059525310
Short name	T658
Test name
Test status
Simulation time	2021010585 ps
CPU time	36.94 seconds
Started	Apr 02 12:53:08 PM PDT 24
Finished	Apr 02 12:53:45 PM PDT 24
Peak memory	211656 kb
Host	smart-89de0922-26fd-4164-be61-88fa6ac2cf26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2059525310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2059525310
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.77800905
Short name	T267
Test name
Test status
Simulation time	55010453393 ps
CPU time	378.55 seconds
Started	Apr 02 12:53:13 PM PDT 24
Finished	Apr 02 12:59:31 PM PDT 24
Peak memory	207244 kb
Host	smart-93656155-bf2a-4c4d-8c85-29a485ff299d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=77800905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow _rsp.77800905
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2979870189
Short name	T386
Test name
Test status
Simulation time	3095650837 ps
CPU time	32.73 seconds
Started	Apr 02 12:53:08 PM PDT 24
Finished	Apr 02 12:53:41 PM PDT 24
Peak memory	203524 kb
Host	smart-313ecaf4-75fb-46ac-9134-5251c459efe6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979870189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2979870189
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.2744061917
Short name	T325
Test name
Test status
Simulation time	56457391 ps
CPU time	2.28 seconds
Started	Apr 02 12:53:08 PM PDT 24
Finished	Apr 02 12:53:10 PM PDT 24
Peak memory	203508 kb
Host	smart-f9077ef6-7bc9-4113-b3ab-f5fe6ed9edbc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2744061917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2744061917
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.2535550531
Short name	T827
Test name
Test status
Simulation time	2002016114 ps
CPU time	31.79 seconds
Started	Apr 02 12:53:11 PM PDT 24
Finished	Apr 02 12:53:43 PM PDT 24
Peak memory	205092 kb
Host	smart-044e5605-27db-49f5-ab39-7efba79a6211
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2535550531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2535550531
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2764096879
Short name	T629
Test name
Test status
Simulation time	6929567646 ps
CPU time	26.45 seconds
Started	Apr 02 12:53:07 PM PDT 24
Finished	Apr 02 12:53:33 PM PDT 24
Peak memory	203540 kb
Host	smart-7dd2aeda-79d9-4ad9-881d-1d924cb8892f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764096879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2764096879
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3400177682
Short name	T237
Test name
Test status
Simulation time	20019549785 ps
CPU time	162.11 seconds
Started	Apr 02 12:53:06 PM PDT 24
Finished	Apr 02 12:55:48 PM PDT 24
Peak memory	211772 kb
Host	smart-8fb3f6f0-b603-4c09-98d1-c0dff0701838
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3400177682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3400177682
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2710278878
Short name	T170
Test name
Test status
Simulation time	198235204 ps
CPU time	6.7 seconds
Started	Apr 02 12:53:10 PM PDT 24
Finished	Apr 02 12:53:17 PM PDT 24
Peak memory	211656 kb
Host	smart-c9e00b69-cdd1-4152-acbc-734e99a81445
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710278878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2710278878
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.216382678
Short name	T214
Test name
Test status
Simulation time	7345400971 ps
CPU time	29.24 seconds
Started	Apr 02 12:53:07 PM PDT 24
Finished	Apr 02 12:53:36 PM PDT 24
Peak memory	204704 kb
Host	smart-9764ce35-100d-4c4c-8a60-8d1ea6f21884
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=216382678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.216382678
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.923728806
Short name	T871
Test name
Test status
Simulation time	170759821 ps
CPU time	3.55 seconds
Started	Apr 02 12:53:03 PM PDT 24
Finished	Apr 02 12:53:07 PM PDT 24
Peak memory	203456 kb
Host	smart-8d7c9c94-47c8-453b-9a56-83e6fbb7ae1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=923728806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.923728806
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.327120214
Short name	T48
Test name
Test status
Simulation time	7935957781 ps
CPU time	27.82 seconds
Started	Apr 02 12:53:05 PM PDT 24
Finished	Apr 02 12:53:33 PM PDT 24
Peak memory	203568 kb
Host	smart-ea4dc473-9b6e-4173-a6ba-7467c7d326db
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=327120214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.327120214
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.264238804
Short name	T297
Test name
Test status
Simulation time	3004589367 ps
CPU time	25.78 seconds
Started	Apr 02 12:53:06 PM PDT 24
Finished	Apr 02 12:53:32 PM PDT 24
Peak memory	203544 kb
Host	smart-a45383c7-7706-4273-a21a-49cbc8fba4a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=264238804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.264238804
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.392656540
Short name	T524
Test name
Test status
Simulation time	100893912 ps
CPU time	2.65 seconds
Started	Apr 02 12:53:04 PM PDT 24
Finished	Apr 02 12:53:07 PM PDT 24
Peak memory	203428 kb
Host	smart-64a09259-0e6b-44ec-a99b-24a0263149c2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392656540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.392656540
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.272536103
Short name	T404
Test name
Test status
Simulation time	3403937044 ps
CPU time	220.93 seconds
Started	Apr 02 12:53:09 PM PDT 24
Finished	Apr 02 12:56:50 PM PDT 24
Peak memory	210488 kb
Host	smart-9e969a17-3b1b-42fd-a1d9-35c61b289dc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=272536103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.272536103
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3021644645
Short name	T866
Test name
Test status
Simulation time	10347718186 ps
CPU time	161.35 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:55:53 PM PDT 24
Peak memory	207116 kb
Host	smart-89b00485-7cc9-4430-bbd4-dfe5ffe1eb59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3021644645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3021644645
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.296888958
Short name	T335
Test name
Test status
Simulation time	4138737842 ps
CPU time	172 seconds
Started	Apr 02 12:53:06 PM PDT 24
Finished	Apr 02 12:55:58 PM PDT 24
Peak memory	209536 kb
Host	smart-06154808-f2eb-438b-b98d-2c11cfba587c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=296888958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand _reset.296888958
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2738773760
Short name	T276
Test name
Test status
Simulation time	307865653 ps
CPU time	170.03 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:56:02 PM PDT 24
Peak memory	211284 kb
Host	smart-d4c5f0a4-d371-4165-8cd5-a5c60ccfcbe8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738773760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.2738773760
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1628899764
Short name	T813
Test name
Test status
Simulation time	459149122 ps
CPU time	17.65 seconds
Started	Apr 02 12:53:11 PM PDT 24
Finished	Apr 02 12:53:29 PM PDT 24
Peak memory	211644 kb
Host	smart-53fe2d29-57c3-4b01-936f-10a12d6fd0d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1628899764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1628899764
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2470411856
Short name	T228
Test name
Test status
Simulation time	370301478 ps
CPU time	10 seconds
Started	Apr 02 12:53:10 PM PDT 24
Finished	Apr 02 12:53:20 PM PDT 24
Peak memory	204556 kb
Host	smart-b1cab2dc-9068-47fd-bc7b-1a98c1c7e645
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2470411856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2470411856
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2184811053
Short name	T95
Test name
Test status
Simulation time	155688560738 ps
CPU time	817.84 seconds
Started	Apr 02 12:53:11 PM PDT 24
Finished	Apr 02 01:06:49 PM PDT 24
Peak memory	206224 kb
Host	smart-296f9b22-294e-4ea5-9b4d-d21095cbb51d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2184811053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2184811053
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2057717758
Short name	T405
Test name
Test status
Simulation time	1004882599 ps
CPU time	21.31 seconds
Started	Apr 02 12:53:14 PM PDT 24
Finished	Apr 02 12:53:36 PM PDT 24
Peak memory	203516 kb
Host	smart-7f9e29db-3c3c-4573-8799-1832760316d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2057717758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2057717758
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.1901706916
Short name	T213
Test name
Test status
Simulation time	1827670001 ps
CPU time	23.32 seconds
Started	Apr 02 12:53:09 PM PDT 24
Finished	Apr 02 12:53:32 PM PDT 24
Peak memory	203424 kb
Host	smart-bfecf7ac-6f0e-4d2c-b6ff-1c9456b56b34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1901706916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1901706916
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.2760585916
Short name	T587
Test name
Test status
Simulation time	117161987 ps
CPU time	16.88 seconds
Started	Apr 02 12:53:09 PM PDT 24
Finished	Apr 02 12:53:26 PM PDT 24
Peak memory	204820 kb
Host	smart-98359906-8edc-4193-901b-5a7b6f80032f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2760585916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2760585916
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.566488523
Short name	T857
Test name
Test status
Simulation time	56935302879 ps
CPU time	131.81 seconds
Started	Apr 02 12:53:09 PM PDT 24
Finished	Apr 02 12:55:21 PM PDT 24
Peak memory	204852 kb
Host	smart-f7f3f764-2d3f-488e-91c0-28ba794530c0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=566488523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.566488523
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1651390115
Short name	T137
Test name
Test status
Simulation time	26881138693 ps
CPU time	215.13 seconds
Started	Apr 02 12:53:11 PM PDT 24
Finished	Apr 02 12:56:46 PM PDT 24
Peak memory	204880 kb
Host	smart-7f4a3bc7-4923-4a6d-a3ca-21e89cc28136
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1651390115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1651390115
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4235717111
Short name	T402
Test name
Test status
Simulation time	365745028 ps
CPU time	30.93 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:53:43 PM PDT 24
Peak memory	211656 kb
Host	smart-320b9170-3103-4d01-8412-9a13cee672b3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235717111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4235717111
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.2065661220
Short name	T547
Test name
Test status
Simulation time	578221698 ps
CPU time	20.33 seconds
Started	Apr 02 12:53:13 PM PDT 24
Finished	Apr 02 12:53:33 PM PDT 24
Peak memory	204284 kb
Host	smart-f415b546-7ba6-4428-8aa9-4c740b1ba9ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2065661220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2065661220
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.1354699114
Short name	T238
Test name
Test status
Simulation time	221834209 ps
CPU time	2.88 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:53:15 PM PDT 24
Peak memory	203412 kb
Host	smart-401ad83c-5cea-4cf8-bf49-bca954853e84
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1354699114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1354699114
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.256332854
Short name	T680
Test name
Test status
Simulation time	8505363164 ps
CPU time	33.02 seconds
Started	Apr 02 12:53:13 PM PDT 24
Finished	Apr 02 12:53:46 PM PDT 24
Peak memory	203572 kb
Host	smart-b7791fd0-064e-4b36-954c-e96ced072c77
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=256332854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.256332854
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.337969400
Short name	T138
Test name
Test status
Simulation time	5621270744 ps
CPU time	36.41 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:53:48 PM PDT 24
Peak memory	203440 kb
Host	smart-ec88c09f-af99-4468-b8d7-6fd78e13b733
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=337969400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.337969400
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3655694879
Short name	T253
Test name
Test status
Simulation time	98901075 ps
CPU time	1.9 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:53:14 PM PDT 24
Peak memory	203500 kb
Host	smart-7dd1937f-ec12-46d0-a255-1a6d90befb1a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655694879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3655694879
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.1645672513
Short name	T174
Test name
Test status
Simulation time	2771626226 ps
CPU time	185.11 seconds
Started	Apr 02 12:53:11 PM PDT 24
Finished	Apr 02 12:56:16 PM PDT 24
Peak memory	206040 kb
Host	smart-3ca4503b-dee3-43bb-bde1-860baaaddc4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1645672513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1645672513
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.814698989
Short name	T266
Test name
Test status
Simulation time	22712422053 ps
CPU time	135.63 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:55:28 PM PDT 24
Peak memory	206708 kb
Host	smart-c7433952-d7f3-4751-b953-ecfcf7108332
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=814698989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.814698989
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.912045669
Short name	T329
Test name
Test status
Simulation time	4218582077 ps
CPU time	150.25 seconds
Started	Apr 02 12:53:10 PM PDT 24
Finished	Apr 02 12:55:40 PM PDT 24
Peak memory	209452 kb
Host	smart-db56e113-d3cd-4af1-8f84-d1cd9af0b4a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=912045669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.912045669
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.4268241565
Short name	T681
Test name
Test status
Simulation time	5198431905 ps
CPU time	35.46 seconds
Started	Apr 02 12:53:12 PM PDT 24
Finished	Apr 02 12:53:47 PM PDT 24
Peak memory	205264 kb
Host	smart-bc455158-239b-4dbe-aee5-bd92994c15bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4268241565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4268241565
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2286642902
Short name	T15
Test name
Test status
Simulation time	122463233 ps
CPU time	14.69 seconds
Started	Apr 02 12:53:13 PM PDT 24
Finished	Apr 02 12:53:28 PM PDT 24
Peak memory	211576 kb
Host	smart-78adb503-262a-4673-bea6-4f9455623f5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2286642902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2286642902
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1148444968
Short name	T624
Test name
Test status
Simulation time	239160658715 ps
CPU time	494.78 seconds
Started	Apr 02 12:53:13 PM PDT 24
Finished	Apr 02 01:01:28 PM PDT 24
Peak memory	206856 kb
Host	smart-1636a953-bb5f-4d9d-ab57-74897a021e06
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1148444968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1148444968
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.274216974
Short name	T543
Test name
Test status
Simulation time	109341805 ps
CPU time	5.79 seconds
Started	Apr 02 12:53:15 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	203684 kb
Host	smart-e867d06d-a89d-4ec5-b2b6-9dca2a09b583
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=274216974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.274216974
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.3020626059
Short name	T566
Test name
Test status
Simulation time	128917644 ps
CPU time	12.23 seconds
Started	Apr 02 12:53:14 PM PDT 24
Finished	Apr 02 12:53:26 PM PDT 24
Peak memory	203496 kb
Host	smart-57055db4-5fa0-4d32-add7-b73bbe61720f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020626059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3020626059
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.645850362
Short name	T185
Test name
Test status
Simulation time	1410318926 ps
CPU time	32.59 seconds
Started	Apr 02 12:53:14 PM PDT 24
Finished	Apr 02 12:53:47 PM PDT 24
Peak memory	211672 kb
Host	smart-c4136afc-db2a-4310-b597-f521eda5b6e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=645850362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.645850362
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.134608391
Short name	T360
Test name
Test status
Simulation time	21853384825 ps
CPU time	48.15 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:54:06 PM PDT 24
Peak memory	204956 kb
Host	smart-139a577a-4814-4497-b594-316ce5a60d7e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=134608391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.134608391
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3941834023
Short name	T819
Test name
Test status
Simulation time	2492638219 ps
CPU time	21.77 seconds
Started	Apr 02 12:53:14 PM PDT 24
Finished	Apr 02 12:53:36 PM PDT 24
Peak memory	204040 kb
Host	smart-92bbd7fc-b7b4-441f-93de-832b6421d6ab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3941834023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3941834023
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1275334115
Short name	T559
Test name
Test status
Simulation time	218017576 ps
CPU time	16.95 seconds
Started	Apr 02 12:53:13 PM PDT 24
Finished	Apr 02 12:53:30 PM PDT 24
Peak memory	204580 kb
Host	smart-61437a61-692e-47b9-b90b-646bac93350f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275334115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1275334115
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.2322369522
Short name	T584
Test name
Test status
Simulation time	34653018 ps
CPU time	3.23 seconds
Started	Apr 02 12:53:15 PM PDT 24
Finished	Apr 02 12:53:18 PM PDT 24
Peak memory	203540 kb
Host	smart-d4b7385a-71e9-4544-a096-6083ddcfc6f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322369522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2322369522
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.3935933021
Short name	T453
Test name
Test status
Simulation time	30917400 ps
CPU time	2.2 seconds
Started	Apr 02 12:53:16 PM PDT 24
Finished	Apr 02 12:53:18 PM PDT 24
Peak memory	203476 kb
Host	smart-d2489dba-4e43-4edb-a556-bf5ce22c61a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3935933021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3935933021
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1995102542
Short name	T300
Test name
Test status
Simulation time	6935964902 ps
CPU time	31.04 seconds
Started	Apr 02 12:53:15 PM PDT 24
Finished	Apr 02 12:53:46 PM PDT 24
Peak memory	203580 kb
Host	smart-e4ff5af3-6bd0-41e6-8498-197c1d88f90b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995102542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1995102542
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1657137121
Short name	T46
Test name
Test status
Simulation time	3907530438 ps
CPU time	24.23 seconds
Started	Apr 02 12:53:16 PM PDT 24
Finished	Apr 02 12:53:40 PM PDT 24
Peak memory	203564 kb
Host	smart-2d40c206-b243-43df-ab0d-4514f6840a03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1657137121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1657137121
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.4194492246
Short name	T610
Test name
Test status
Simulation time	43099373 ps
CPU time	2.49 seconds
Started	Apr 02 12:53:44 PM PDT 24
Finished	Apr 02 12:53:46 PM PDT 24
Peak memory	203492 kb
Host	smart-246bc80a-240a-49d5-8d27-25ac57ff06b6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194492246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.4194492246
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.3728069181
Short name	T155
Test name
Test status
Simulation time	847949505 ps
CPU time	96.66 seconds
Started	Apr 02 12:53:19 PM PDT 24
Finished	Apr 02 12:54:55 PM PDT 24
Peak memory	208048 kb
Host	smart-2f22dfbb-aa29-46fa-afbd-8acff7e9aba6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3728069181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3728069181
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2207482919
Short name	T797
Test name
Test status
Simulation time	5864514272 ps
CPU time	116.3 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:55:14 PM PDT 24
Peak memory	206308 kb
Host	smart-154ff615-3860-48da-9766-0f4bf0cd645b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2207482919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2207482919
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1673841314
Short name	T117
Test name
Test status
Simulation time	125512930 ps
CPU time	91.85 seconds
Started	Apr 02 12:53:17 PM PDT 24
Finished	Apr 02 12:54:49 PM PDT 24
Peak memory	208000 kb
Host	smart-2e229e3f-7572-42d0-b2e6-7523524b452d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1673841314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1673841314
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3293206671
Short name	T57
Test name
Test status
Simulation time	239350653 ps
CPU time	7.43 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:53:25 PM PDT 24
Peak memory	204972 kb
Host	smart-777b82b6-2423-463b-9480-3f22b1b0cf85
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3293206671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3293206671
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1623063907
Short name	T68
Test name
Test status
Simulation time	7178106717 ps
CPU time	54.17 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:54:16 PM PDT 24
Peak memory	211716 kb
Host	smart-3c2d57b9-252d-4bd1-ab68-4068b9d1d417
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1623063907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1623063907
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1004844927
Short name	T599
Test name
Test status
Simulation time	50762447379 ps
CPU time	474.79 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 01:01:13 PM PDT 24
Peak memory	206100 kb
Host	smart-52268ca8-d04f-43b3-826a-b248600063dd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1004844927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1004844927
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3335144322
Short name	T548
Test name
Test status
Simulation time	159477879 ps
CPU time	2.1 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	203440 kb
Host	smart-3a0f3e0c-4fd0-464d-aa2d-105c61021fe7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3335144322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3335144322
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.4228597277
Short name	T207
Test name
Test status
Simulation time	123521145 ps
CPU time	9.58 seconds
Started	Apr 02 12:53:21 PM PDT 24
Finished	Apr 02 12:53:31 PM PDT 24
Peak memory	203484 kb
Host	smart-8e442c74-b6fb-4e53-9e54-5110e3ef700e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4228597277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.4228597277
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.992847398
Short name	T787
Test name
Test status
Simulation time	1164450182 ps
CPU time	28.96 seconds
Started	Apr 02 12:53:17 PM PDT 24
Finished	Apr 02 12:53:47 PM PDT 24
Peak memory	204580 kb
Host	smart-729a3ae6-c8fc-44d6-8ea7-3bfe8660d0af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992847398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.992847398
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.918271836
Short name	T146
Test name
Test status
Simulation time	79602474580 ps
CPU time	157.65 seconds
Started	Apr 02 12:53:20 PM PDT 24
Finished	Apr 02 12:55:58 PM PDT 24
Peak memory	205496 kb
Host	smart-25c0ceb7-be27-47d7-9773-ed93b5789799
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=918271836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.918271836
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.272431573
Short name	T193
Test name
Test status
Simulation time	25474041573 ps
CPU time	191.37 seconds
Started	Apr 02 12:53:17 PM PDT 24
Finished	Apr 02 12:56:28 PM PDT 24
Peak memory	211704 kb
Host	smart-ed3f0a50-9981-4425-875d-b4250ac85221
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=272431573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.272431573
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2930955738
Short name	T357
Test name
Test status
Simulation time	36698543 ps
CPU time	4.86 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:53:23 PM PDT 24
Peak memory	204632 kb
Host	smart-778e9a22-987a-408c-b697-c385dd0a28a6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930955738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2930955738
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.2993109220
Short name	T504
Test name
Test status
Simulation time	212005299 ps
CPU time	3.88 seconds
Started	Apr 02 12:53:21 PM PDT 24
Finished	Apr 02 12:53:24 PM PDT 24
Peak memory	203992 kb
Host	smart-3e54bfea-b042-4189-8e95-5662f1a3c0e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2993109220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2993109220
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.176475078
Short name	T774
Test name
Test status
Simulation time	234749372 ps
CPU time	3.69 seconds
Started	Apr 02 12:53:19 PM PDT 24
Finished	Apr 02 12:53:23 PM PDT 24
Peak memory	203424 kb
Host	smart-37e4be7f-0f98-4764-8949-9fedb29ee275
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=176475078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.176475078
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3181980239
Short name	T394
Test name
Test status
Simulation time	5276056061 ps
CPU time	24.9 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:53:43 PM PDT 24
Peak memory	203564 kb
Host	smart-a1f55067-67a0-4e6f-9aa2-b914126b2d1f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181980239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3181980239
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2968781721
Short name	T176
Test name
Test status
Simulation time	14678028668 ps
CPU time	43.5 seconds
Started	Apr 02 12:53:19 PM PDT 24
Finished	Apr 02 12:54:03 PM PDT 24
Peak memory	203572 kb
Host	smart-40e462c3-d42b-4868-9592-08401c357739
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2968781721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2968781721
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3709813150
Short name	T848
Test name
Test status
Simulation time	33652653 ps
CPU time	2.87 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	203424 kb
Host	smart-1ec6776b-c656-4e2e-85f3-edc3e97f4359
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709813150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3709813150
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.3424790809
Short name	T118
Test name
Test status
Simulation time	1870946472 ps
CPU time	57.28 seconds
Started	Apr 02 12:53:16 PM PDT 24
Finished	Apr 02 12:54:14 PM PDT 24
Peak memory	206212 kb
Host	smart-48a993e2-9ca4-4010-9269-51e0277c19f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3424790809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3424790809
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3763063294
Short name	T769
Test name
Test status
Simulation time	4102865007 ps
CPU time	111.87 seconds
Started	Apr 02 12:53:17 PM PDT 24
Finished	Apr 02 12:55:10 PM PDT 24
Peak memory	206576 kb
Host	smart-4fb02928-b8d8-4fab-9599-c6573597efba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3763063294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3763063294
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.4251686389
Short name	T22
Test name
Test status
Simulation time	7848041195 ps
CPU time	453.02 seconds
Started	Apr 02 12:53:21 PM PDT 24
Finished	Apr 02 01:00:54 PM PDT 24
Peak memory	225864 kb
Host	smart-e8e9313d-be21-4215-9434-efb75c531ca4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4251686389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.4251686389
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3013909997
Short name	T39
Test name
Test status
Simulation time	48852738 ps
CPU time	2.57 seconds
Started	Apr 02 12:53:18 PM PDT 24
Finished	Apr 02 12:53:21 PM PDT 24
Peak memory	203524 kb
Host	smart-58433376-f92f-4098-8baa-47b266e9c1a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3013909997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3013909997
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.330753815
Short name	T826
Test name
Test status
Simulation time	930444417 ps
CPU time	29.65 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:53:52 PM PDT 24
Peak memory	205256 kb
Host	smart-5e046767-0f0c-40f5-98f5-5853918179c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=330753815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.330753815
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.670293372
Short name	T872
Test name
Test status
Simulation time	65158209540 ps
CPU time	316.39 seconds
Started	Apr 02 12:53:21 PM PDT 24
Finished	Apr 02 12:58:38 PM PDT 24
Peak memory	211660 kb
Host	smart-d11f0e14-399a-490f-830a-f64c19cd2223
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=670293372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo w_rsp.670293372
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.19771228
Short name	T378
Test name
Test status
Simulation time	705509117 ps
CPU time	11 seconds
Started	Apr 02 12:53:29 PM PDT 24
Finished	Apr 02 12:53:40 PM PDT 24
Peak memory	203692 kb
Host	smart-206d5319-6db4-484f-85f0-7f252b90f668
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=19771228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.19771228
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.1737803371
Short name	T285
Test name
Test status
Simulation time	255666328 ps
CPU time	6.66 seconds
Started	Apr 02 12:53:20 PM PDT 24
Finished	Apr 02 12:53:27 PM PDT 24
Peak memory	203452 kb
Host	smart-c5297c40-99b7-48d5-8d7e-7d92cc25a4d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1737803371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1737803371
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.1074694019
Short name	T833
Test name
Test status
Simulation time	29111817 ps
CPU time	3.03 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:53:26 PM PDT 24
Peak memory	203516 kb
Host	smart-9b34e80d-8cb2-4891-8a39-5de2c8a2d43c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1074694019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1074694019
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.968415888
Short name	T84
Test name
Test status
Simulation time	46123817946 ps
CPU time	83.69 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:54:45 PM PDT 24
Peak memory	211732 kb
Host	smart-b1504d80-776e-41b8-912d-10b1bef3d4a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=968415888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.968415888
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.855931270
Short name	T142
Test name
Test status
Simulation time	22462726435 ps
CPU time	59.98 seconds
Started	Apr 02 12:53:24 PM PDT 24
Finished	Apr 02 12:54:25 PM PDT 24
Peak memory	211760 kb
Host	smart-0f9cd158-00d1-4d87-8ada-1a3d280a114d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=855931270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.855931270
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3236596958
Short name	T771
Test name
Test status
Simulation time	28182768 ps
CPU time	3.41 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:53:26 PM PDT 24
Peak memory	204400 kb
Host	smart-ec2b073a-bca3-4e1e-b3d9-cfd85cbcd63b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236596958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3236596958
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.667723251
Short name	T322
Test name
Test status
Simulation time	1096704887 ps
CPU time	25.06 seconds
Started	Apr 02 12:53:23 PM PDT 24
Finished	Apr 02 12:53:49 PM PDT 24
Peak memory	203508 kb
Host	smart-2e8c7925-2fb9-48f7-ab15-12de00dd2f26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=667723251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.667723251
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.147386913
Short name	T342
Test name
Test status
Simulation time	32660976 ps
CPU time	2.39 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:53:25 PM PDT 24
Peak memory	203496 kb
Host	smart-be8efab9-7779-4613-8068-aa214901f28b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=147386913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.147386913
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3369360501
Short name	T704
Test name
Test status
Simulation time	14533289943 ps
CPU time	35.13 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:53:57 PM PDT 24
Peak memory	203556 kb
Host	smart-69eb0819-7bef-4f7c-9141-73b62cc10b6a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369360501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3369360501
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.919660126
Short name	T356
Test name
Test status
Simulation time	3459524252 ps
CPU time	25.84 seconds
Started	Apr 02 12:53:23 PM PDT 24
Finished	Apr 02 12:53:49 PM PDT 24
Peak memory	203508 kb
Host	smart-e0743807-f6c3-47fa-8221-f77d93265c3f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=919660126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.919660126
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1270405378
Short name	T785
Test name
Test status
Simulation time	28576886 ps
CPU time	2.81 seconds
Started	Apr 02 12:53:23 PM PDT 24
Finished	Apr 02 12:53:26 PM PDT 24
Peak memory	203460 kb
Host	smart-96be961e-8943-4f10-ae5a-06180fa5e518
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270405378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1270405378
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.3510909193
Short name	T889
Test name
Test status
Simulation time	4890808577 ps
CPU time	133.56 seconds
Started	Apr 02 12:53:28 PM PDT 24
Finished	Apr 02 12:55:42 PM PDT 24
Peak memory	207748 kb
Host	smart-527002a8-8d9b-4d89-ab8d-0629348db8db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3510909193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3510909193
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3840419626
Short name	T752
Test name
Test status
Simulation time	346018246 ps
CPU time	33.87 seconds
Started	Apr 02 12:53:26 PM PDT 24
Finished	Apr 02 12:54:00 PM PDT 24
Peak memory	204248 kb
Host	smart-83a51dc5-a291-4f3b-aba6-91ebbe1df5a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3840419626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3840419626
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.589876435
Short name	T495
Test name
Test status
Simulation time	234688133 ps
CPU time	33.56 seconds
Started	Apr 02 12:53:29 PM PDT 24
Finished	Apr 02 12:54:03 PM PDT 24
Peak memory	206368 kb
Host	smart-4a43a4e3-2ac3-4c83-8452-3be482329af7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=589876435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.589876435
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.217023317
Short name	T714
Test name
Test status
Simulation time	3101472100 ps
CPU time	26.31 seconds
Started	Apr 02 12:53:22 PM PDT 24
Finished	Apr 02 12:53:49 PM PDT 24
Peak memory	205216 kb
Host	smart-38a44b73-0e27-423a-8b91-4e5cc2a71e02
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=217023317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.217023317
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1289925219
Short name	T240
Test name
Test status
Simulation time	201431342 ps
CPU time	7.09 seconds
Started	Apr 02 12:52:18 PM PDT 24
Finished	Apr 02 12:52:25 PM PDT 24
Peak memory	203856 kb
Host	smart-fec03a1b-ef47-46a8-90b0-5defa78edb8f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289925219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1289925219
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3033789066
Short name	T863
Test name
Test status
Simulation time	118338676 ps
CPU time	12.36 seconds
Started	Apr 02 12:52:17 PM PDT 24
Finished	Apr 02 12:52:30 PM PDT 24
Peak memory	203652 kb
Host	smart-63d36816-d7db-4028-970c-b16a31b13c7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3033789066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3033789066
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.4239018685
Short name	T835
Test name
Test status
Simulation time	248613696 ps
CPU time	15.58 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:52:44 PM PDT 24
Peak memory	203392 kb
Host	smart-72cd27ef-6a6c-4417-baa8-9f5222cec642
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4239018685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.4239018685
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.4075760757
Short name	T8
Test name
Test status
Simulation time	55501429 ps
CPU time	3.33 seconds
Started	Apr 02 12:52:12 PM PDT 24
Finished	Apr 02 12:52:16 PM PDT 24
Peak memory	203512 kb
Host	smart-821471b5-9e86-4693-b99d-7e542b2b59e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4075760757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.4075760757
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.721025985
Short name	T56
Test name
Test status
Simulation time	2391681239 ps
CPU time	10.72 seconds
Started	Apr 02 12:52:14 PM PDT 24
Finished	Apr 02 12:52:25 PM PDT 24
Peak memory	203604 kb
Host	smart-500b163e-a577-4771-894c-0f8c8b1dc7db
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=721025985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.721025985
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3874006439
Short name	T74
Test name
Test status
Simulation time	40774638519 ps
CPU time	171.39 seconds
Started	Apr 02 12:52:16 PM PDT 24
Finished	Apr 02 12:55:07 PM PDT 24
Peak memory	211748 kb
Host	smart-1db70d84-9a03-477c-981e-1c3b480f6b95
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3874006439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3874006439
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1214914304
Short name	T720
Test name
Test status
Simulation time	167679271 ps
CPU time	12.68 seconds
Started	Apr 02 12:52:13 PM PDT 24
Finished	Apr 02 12:52:26 PM PDT 24
Peak memory	204592 kb
Host	smart-95101bc6-8ab7-49bf-8f63-f3addd3b6cbd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214914304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1214914304
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.3183883318
Short name	T220
Test name
Test status
Simulation time	1929373292 ps
CPU time	26.14 seconds
Started	Apr 02 12:52:15 PM PDT 24
Finished	Apr 02 12:52:42 PM PDT 24
Peak memory	203960 kb
Host	smart-5c65d2e3-e511-4598-a4de-e9a57a2890c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3183883318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3183883318
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.1583281574
Short name	T562
Test name
Test status
Simulation time	159056400 ps
CPU time	3.69 seconds
Started	Apr 02 12:52:11 PM PDT 24
Finished	Apr 02 12:52:15 PM PDT 24
Peak memory	203504 kb
Host	smart-69b2c632-3ca0-4271-983b-aa9d355f7a7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1583281574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1583281574
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2866545188
Short name	T560
Test name
Test status
Simulation time	6535311697 ps
CPU time	33.03 seconds
Started	Apr 02 12:52:12 PM PDT 24
Finished	Apr 02 12:52:46 PM PDT 24
Peak memory	203568 kb
Host	smart-607a422b-16df-4bf1-bff4-74fdc019e6f9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866545188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2866545188
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1517457386
Short name	T262
Test name
Test status
Simulation time	5010002484 ps
CPU time	43.31 seconds
Started	Apr 02 12:52:13 PM PDT 24
Finished	Apr 02 12:52:56 PM PDT 24
Peak memory	203508 kb
Host	smart-7807a20e-32e3-4cb1-9a7c-51d61394a7d9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1517457386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1517457386
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.4199249110
Short name	T700
Test name
Test status
Simulation time	27235353 ps
CPU time	2.32 seconds
Started	Apr 02 12:52:13 PM PDT 24
Finished	Apr 02 12:52:15 PM PDT 24
Peak memory	203496 kb
Host	smart-b60c2cb5-1b1e-4a84-9c90-2a310f7c58ff
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199249110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.4199249110
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.2548900971
Short name	T270
Test name
Test status
Simulation time	2477758276 ps
CPU time	145.41 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:54:54 PM PDT 24
Peak memory	206964 kb
Host	smart-6fd628b0-545c-433c-a1df-251ed6f82677
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2548900971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2548900971
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2561713776
Short name	T328
Test name
Test status
Simulation time	12029561905 ps
CPU time	145.55 seconds
Started	Apr 02 12:52:16 PM PDT 24
Finished	Apr 02 12:54:42 PM PDT 24
Peak memory	206296 kb
Host	smart-6397e232-a8cc-41cf-a9e0-90f8025e475a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2561713776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2561713776
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3214108233
Short name	T215
Test name
Test status
Simulation time	604594663 ps
CPU time	214.73 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:55:55 PM PDT 24
Peak memory	208476 kb
Host	smart-8942d9ed-df38-4419-9729-f23f55896ede
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3214108233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3214108233
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3634202678
Short name	T731
Test name
Test status
Simulation time	1720781997 ps
CPU time	366.72 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:58:36 PM PDT 24
Peak memory	224308 kb
Host	smart-689a4c4e-3bac-4e33-a850-40e4e74288f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3634202678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3634202678
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.317849272
Short name	T60
Test name
Test status
Simulation time	2061384702 ps
CPU time	31.6 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:52:51 PM PDT 24
Peak memory	211568 kb
Host	smart-4cda6504-f2b7-47f3-9ad5-b41008a966a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317849272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.317849272
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2954206821
Short name	T305
Test name
Test status
Simulation time	414488843 ps
CPU time	49 seconds
Started	Apr 02 12:53:25 PM PDT 24
Finished	Apr 02 12:54:15 PM PDT 24
Peak memory	211652 kb
Host	smart-216fd0d1-ce06-49e2-bfe5-eea681181a16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2954206821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2954206821
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1268036497
Short name	T115
Test name
Test status
Simulation time	22556956299 ps
CPU time	197.98 seconds
Started	Apr 02 12:53:28 PM PDT 24
Finished	Apr 02 12:56:47 PM PDT 24
Peak memory	211728 kb
Host	smart-5fb305dc-cff1-4ba3-b530-2e08aaed580c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1268036497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.1268036497
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3286285692
Short name	T424
Test name
Test status
Simulation time	235434058 ps
CPU time	8.33 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:53:41 PM PDT 24
Peak memory	203764 kb
Host	smart-f1703940-5381-46c9-a0f9-3b97817234ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3286285692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3286285692
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.489633000
Short name	T225
Test name
Test status
Simulation time	419327901 ps
CPU time	12.78 seconds
Started	Apr 02 12:53:30 PM PDT 24
Finished	Apr 02 12:53:43 PM PDT 24
Peak memory	203504 kb
Host	smart-556fcf4f-388d-4007-91cc-0daf7c07ee6e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=489633000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.489633000
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.379757949
Short name	T87
Test name
Test status
Simulation time	1726208976 ps
CPU time	26.65 seconds
Started	Apr 02 12:53:26 PM PDT 24
Finished	Apr 02 12:53:53 PM PDT 24
Peak memory	211608 kb
Host	smart-b2ff5c1a-b27c-408f-8284-c38b4ce35a35
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=379757949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.379757949
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2273333593
Short name	T505
Test name
Test status
Simulation time	39553412120 ps
CPU time	235.07 seconds
Started	Apr 02 12:53:25 PM PDT 24
Finished	Apr 02 12:57:20 PM PDT 24
Peak memory	205092 kb
Host	smart-850f6e4b-4928-40ba-856e-efcdeab45463
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273333593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2273333593
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.445513693
Short name	T567
Test name
Test status
Simulation time	21137108694 ps
CPU time	140.72 seconds
Started	Apr 02 12:53:24 PM PDT 24
Finished	Apr 02 12:55:45 PM PDT 24
Peak memory	204864 kb
Host	smart-710087e3-74ff-4f0f-91da-17ddcda892e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=445513693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.445513693
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.4009389550
Short name	T853
Test name
Test status
Simulation time	214422373 ps
CPU time	18.41 seconds
Started	Apr 02 12:53:27 PM PDT 24
Finished	Apr 02 12:53:46 PM PDT 24
Peak memory	204628 kb
Host	smart-977ffebc-ef4a-49e7-a6cf-47ca5af665db
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009389550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.4009389550
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.3356923734
Short name	T373
Test name
Test status
Simulation time	1224315786 ps
CPU time	26.81 seconds
Started	Apr 02 12:53:28 PM PDT 24
Finished	Apr 02 12:53:56 PM PDT 24
Peak memory	204044 kb
Host	smart-f83a9cca-5d99-4f48-bc67-13bd80593f70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3356923734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3356923734
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.1896026460
Short name	T577
Test name
Test status
Simulation time	158896041 ps
CPU time	3.73 seconds
Started	Apr 02 12:53:26 PM PDT 24
Finished	Apr 02 12:53:30 PM PDT 24
Peak memory	203484 kb
Host	smart-b3eae4c3-8817-4e8d-b7bf-8bff02a693a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1896026460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1896026460
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1525808290
Short name	T121
Test name
Test status
Simulation time	18551770814 ps
CPU time	36.05 seconds
Started	Apr 02 12:53:28 PM PDT 24
Finished	Apr 02 12:54:05 PM PDT 24
Peak memory	203552 kb
Host	smart-d62ff989-7391-4e2a-811a-8cb787e8a34b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525808290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1525808290
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2116419206
Short name	T317
Test name
Test status
Simulation time	5000371244 ps
CPU time	22.31 seconds
Started	Apr 02 12:53:27 PM PDT 24
Finished	Apr 02 12:53:49 PM PDT 24
Peak memory	203568 kb
Host	smart-ff0881c9-e5e5-421c-8664-92f74142b385
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2116419206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2116419206
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2250700253
Short name	T126
Test name
Test status
Simulation time	27374266 ps
CPU time	2.19 seconds
Started	Apr 02 12:53:26 PM PDT 24
Finished	Apr 02 12:53:28 PM PDT 24
Peak memory	203480 kb
Host	smart-c6290dd2-4f17-4836-8608-10f1ffced5b8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250700253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2250700253
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.131987324
Short name	T542
Test name
Test status
Simulation time	1045365257 ps
CPU time	85.98 seconds
Started	Apr 02 12:53:33 PM PDT 24
Finished	Apr 02 12:54:59 PM PDT 24
Peak memory	206652 kb
Host	smart-670d040e-d095-4d3b-bcdd-4c850c60720a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=131987324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.131987324
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1064446501
Short name	T190
Test name
Test status
Simulation time	8167959954 ps
CPU time	212.09 seconds
Started	Apr 02 12:53:27 PM PDT 24
Finished	Apr 02 12:57:00 PM PDT 24
Peak memory	210520 kb
Host	smart-538f56f7-ab12-4d75-8e1c-f656c7cee0b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1064446501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1064446501
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.257865713
Short name	T32
Test name
Test status
Simulation time	1630241606 ps
CPU time	284.75 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:58:17 PM PDT 24
Peak memory	209332 kb
Host	smart-fb34ddac-685b-4872-a7ec-ec4eab176449
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=257865713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.257865713
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.4272215046
Short name	T773
Test name
Test status
Simulation time	159586870 ps
CPU time	5.24 seconds
Started	Apr 02 12:53:29 PM PDT 24
Finished	Apr 02 12:53:35 PM PDT 24
Peak memory	211648 kb
Host	smart-3db6f88d-219a-4b5e-9442-89b0fb5510c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4272215046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4272215046
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2663516320
Short name	T112
Test name
Test status
Simulation time	659852253 ps
CPU time	11.16 seconds
Started	Apr 02 12:53:30 PM PDT 24
Finished	Apr 02 12:53:41 PM PDT 24
Peak memory	204296 kb
Host	smart-904a9618-fbbb-4e8c-b449-03b2064462e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2663516320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2663516320
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1946804866
Short name	T898
Test name
Test status
Simulation time	47941850439 ps
CPU time	445.66 seconds
Started	Apr 02 12:53:29 PM PDT 24
Finished	Apr 02 01:00:55 PM PDT 24
Peak memory	211664 kb
Host	smart-05b2fa23-cffc-4212-8a76-61a9ae98b289
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1946804866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1946804866
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.904252405
Short name	T353
Test name
Test status
Simulation time	291456927 ps
CPU time	4.96 seconds
Started	Apr 02 12:53:36 PM PDT 24
Finished	Apr 02 12:53:42 PM PDT 24
Peak memory	203528 kb
Host	smart-15f77ee1-3648-4236-bb0b-8f0fa5fcf58d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=904252405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.904252405
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.3486337292
Short name	T382
Test name
Test status
Simulation time	555024645 ps
CPU time	24.46 seconds
Started	Apr 02 12:53:29 PM PDT 24
Finished	Apr 02 12:53:54 PM PDT 24
Peak memory	203504 kb
Host	smart-97a4a2c6-6303-4309-b2ef-31f2695ae24f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3486337292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3486337292
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.743545762
Short name	T158
Test name
Test status
Simulation time	1793282092 ps
CPU time	26.68 seconds
Started	Apr 02 12:53:30 PM PDT 24
Finished	Apr 02 12:53:57 PM PDT 24
Peak memory	204700 kb
Host	smart-ec9a9b82-6c50-4ded-bf87-bfc86786d580
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=743545762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.743545762
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2963672119
Short name	T747
Test name
Test status
Simulation time	38378209873 ps
CPU time	248.88 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:57:41 PM PDT 24
Peak memory	211600 kb
Host	smart-0df87970-8626-4078-b751-77b5d31853b3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963672119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2963672119
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2295120493
Short name	T167
Test name
Test status
Simulation time	46191015538 ps
CPU time	122.47 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:55:34 PM PDT 24
Peak memory	204940 kb
Host	smart-e704b237-42ae-4e8c-b0f8-c456c63dae69
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2295120493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2295120493
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.247688961
Short name	T802
Test name
Test status
Simulation time	244442227 ps
CPU time	29.73 seconds
Started	Apr 02 12:53:29 PM PDT 24
Finished	Apr 02 12:53:59 PM PDT 24
Peak memory	211648 kb
Host	smart-6fab85f5-3311-436b-9992-9153d8614bd6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247688961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.247688961
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.3848372794
Short name	T709
Test name
Test status
Simulation time	278288924 ps
CPU time	16.62 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:53:49 PM PDT 24
Peak memory	204092 kb
Host	smart-b46c2659-c056-4fda-8565-95ff8323be1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3848372794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3848372794
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.410760591
Short name	T578
Test name
Test status
Simulation time	42251442 ps
CPU time	2.11 seconds
Started	Apr 02 12:53:33 PM PDT 24
Finished	Apr 02 12:53:35 PM PDT 24
Peak memory	203416 kb
Host	smart-56ed6370-d4a8-4647-8e50-617864a00951
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=410760591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.410760591
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.717573968
Short name	T487
Test name
Test status
Simulation time	12903784147 ps
CPU time	34.19 seconds
Started	Apr 02 12:53:29 PM PDT 24
Finished	Apr 02 12:54:03 PM PDT 24
Peak memory	203564 kb
Host	smart-af8f71e6-1383-4978-a1b0-c0d7eeb11a4a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=717573968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.717573968
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2878823299
Short name	T657
Test name
Test status
Simulation time	26676832859 ps
CPU time	42.81 seconds
Started	Apr 02 12:53:41 PM PDT 24
Finished	Apr 02 12:54:24 PM PDT 24
Peak memory	203560 kb
Host	smart-abf833a0-3b20-4257-968b-939e8ab60229
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2878823299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2878823299
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2947775112
Short name	T621
Test name
Test status
Simulation time	46329568 ps
CPU time	2.21 seconds
Started	Apr 02 12:53:31 PM PDT 24
Finished	Apr 02 12:53:33 PM PDT 24
Peak memory	203444 kb
Host	smart-6e87ebc1-804e-41fc-8bef-c6092af3eaa3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947775112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2947775112
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.1908043180
Short name	T246
Test name
Test status
Simulation time	2529339732 ps
CPU time	106.93 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:55:20 PM PDT 24
Peak memory	206700 kb
Host	smart-90d369cf-8361-4fbd-8d85-38f526a1f814
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1908043180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1908043180
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3298618122
Short name	T734
Test name
Test status
Simulation time	9434710038 ps
CPU time	171.57 seconds
Started	Apr 02 12:53:33 PM PDT 24
Finished	Apr 02 12:56:25 PM PDT 24
Peak memory	207336 kb
Host	smart-345b0cbc-fef3-4d21-b95f-b3df81929f40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3298618122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3298618122
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3197831307
Short name	T184
Test name
Test status
Simulation time	209156566 ps
CPU time	78.52 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:54:51 PM PDT 24
Peak memory	208524 kb
Host	smart-2191a5fa-9c2e-4d14-9a3e-f5f31b111cb2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3197831307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3197831307
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2002962281
Short name	T204
Test name
Test status
Simulation time	155284519 ps
CPU time	13.87 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:53:46 PM PDT 24
Peak memory	211652 kb
Host	smart-1aa23310-1ab7-4503-89ca-09701e5c154c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2002962281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2002962281
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1841901070
Short name	T582
Test name
Test status
Simulation time	869005207 ps
CPU time	49.33 seconds
Started	Apr 02 12:53:34 PM PDT 24
Finished	Apr 02 12:54:23 PM PDT 24
Peak memory	205644 kb
Host	smart-89f0dbcf-2eae-47e2-a50b-38fc6aaeaf4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1841901070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1841901070
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3971343499
Short name	T196
Test name
Test status
Simulation time	95532975984 ps
CPU time	532.59 seconds
Started	Apr 02 12:53:33 PM PDT 24
Finished	Apr 02 01:02:26 PM PDT 24
Peak memory	207368 kb
Host	smart-aedf76bf-b9f7-447a-8406-e689fba92187
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3971343499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.3971343499
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3581717327
Short name	T647
Test name
Test status
Simulation time	745356845 ps
CPU time	10.69 seconds
Started	Apr 02 12:53:43 PM PDT 24
Finished	Apr 02 12:53:54 PM PDT 24
Peak memory	203844 kb
Host	smart-0c46e3f3-41ae-42ac-b98e-caa46994fa03
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3581717327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3581717327
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.233324799
Short name	T713
Test name
Test status
Simulation time	463519270 ps
CPU time	16.6 seconds
Started	Apr 02 12:53:43 PM PDT 24
Finished	Apr 02 12:54:00 PM PDT 24
Peak memory	203456 kb
Host	smart-33773df9-1be2-4f4b-99db-69e60f1dd6ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=233324799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.233324799
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.1322422284
Short name	T388
Test name
Test status
Simulation time	209926355 ps
CPU time	8.48 seconds
Started	Apr 02 12:53:32 PM PDT 24
Finished	Apr 02 12:53:41 PM PDT 24
Peak memory	204552 kb
Host	smart-e46f8aa9-77b8-4568-bdb5-099dc6417378
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322422284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1322422284
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1892015098
Short name	T332
Test name
Test status
Simulation time	22777351216 ps
CPU time	145.69 seconds
Started	Apr 02 12:53:33 PM PDT 24
Finished	Apr 02 12:55:59 PM PDT 24
Peak memory	205272 kb
Host	smart-972e8202-e7ec-40e2-a4fb-d1820ebabf42
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892015098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1892015098
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2942637374
Short name	T52
Test name
Test status
Simulation time	172938485889 ps
CPU time	338.31 seconds
Started	Apr 02 12:53:34 PM PDT 24
Finished	Apr 02 12:59:12 PM PDT 24
Peak memory	205208 kb
Host	smart-abae14f4-88de-4b10-8d1a-b824046f473c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2942637374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2942637374
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2634642923
Short name	T781
Test name
Test status
Simulation time	270160306 ps
CPU time	22.7 seconds
Started	Apr 02 12:53:36 PM PDT 24
Finished	Apr 02 12:53:59 PM PDT 24
Peak memory	205036 kb
Host	smart-f782b277-e313-4af5-96f3-8c94a54c9a60
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634642923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2634642923
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.3414131955
Short name	T531
Test name
Test status
Simulation time	235504299 ps
CPU time	3.6 seconds
Started	Apr 02 12:53:37 PM PDT 24
Finished	Apr 02 12:53:41 PM PDT 24
Peak memory	203616 kb
Host	smart-0b553f8b-7322-4595-824f-4aab58fbbe6e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3414131955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3414131955
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.2206392283
Short name	T299
Test name
Test status
Simulation time	152138748 ps
CPU time	2.34 seconds
Started	Apr 02 12:53:33 PM PDT 24
Finished	Apr 02 12:53:36 PM PDT 24
Peak memory	203472 kb
Host	smart-e4eb4581-af15-45e7-8992-41af354fcd80
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2206392283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2206392283
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1073227640
Short name	T687
Test name
Test status
Simulation time	19498341100 ps
CPU time	32.01 seconds
Started	Apr 02 12:53:36 PM PDT 24
Finished	Apr 02 12:54:08 PM PDT 24
Peak memory	203556 kb
Host	smart-473a5091-0f1d-4532-bae2-fe6f2571b260
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073227640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1073227640
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1074750901
Short name	T178
Test name
Test status
Simulation time	27457549177 ps
CPU time	43.71 seconds
Started	Apr 02 12:53:34 PM PDT 24
Finished	Apr 02 12:54:18 PM PDT 24
Peak memory	203580 kb
Host	smart-9f3b16df-2f5f-46aa-a1b1-a4df570e1fcf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1074750901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1074750901
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3522555612
Short name	T736
Test name
Test status
Simulation time	38094343 ps
CPU time	2.54 seconds
Started	Apr 02 12:53:34 PM PDT 24
Finished	Apr 02 12:53:37 PM PDT 24
Peak memory	203500 kb
Host	smart-c0a71f7d-58f2-49c2-922f-3c3809516426
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522555612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3522555612
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.4131828457
Short name	T717
Test name
Test status
Simulation time	611257773 ps
CPU time	73.3 seconds
Started	Apr 02 12:53:38 PM PDT 24
Finished	Apr 02 12:54:52 PM PDT 24
Peak memory	205816 kb
Host	smart-79aa9784-cf32-46d3-bc37-23b5bd5c95e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4131828457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.4131828457
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1656344500
Short name	T522
Test name
Test status
Simulation time	5810329340 ps
CPU time	174.24 seconds
Started	Apr 02 12:53:37 PM PDT 24
Finished	Apr 02 12:56:32 PM PDT 24
Peak memory	210580 kb
Host	smart-8900c41e-aed2-47e3-9de2-de9c616717ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1656344500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1656344500
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.4149491486
Short name	T556
Test name
Test status
Simulation time	395846334 ps
CPU time	184.82 seconds
Started	Apr 02 12:53:38 PM PDT 24
Finished	Apr 02 12:56:43 PM PDT 24
Peak memory	208916 kb
Host	smart-356b5895-f71d-4e75-b4c4-cb7e571c0309
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4149491486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.4149491486
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3165317327
Short name	T645
Test name
Test status
Simulation time	15827065338 ps
CPU time	286.07 seconds
Started	Apr 02 12:53:40 PM PDT 24
Finished	Apr 02 12:58:27 PM PDT 24
Peak memory	210788 kb
Host	smart-e4a82d18-00fb-4a8b-bd01-6a5f0aec2c17
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3165317327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3165317327
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.422516386
Short name	T488
Test name
Test status
Simulation time	41839905 ps
CPU time	7.6 seconds
Started	Apr 02 12:53:38 PM PDT 24
Finished	Apr 02 12:53:47 PM PDT 24
Peak memory	204948 kb
Host	smart-0c828dc3-3bee-4f4f-b45a-a54fec0fed2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=422516386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.422516386
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.390338288
Short name	T483
Test name
Test status
Simulation time	915381289 ps
CPU time	27.3 seconds
Started	Apr 02 12:53:40 PM PDT 24
Finished	Apr 02 12:54:07 PM PDT 24
Peak memory	204600 kb
Host	smart-a08c94c8-fdd3-4f92-bb84-fea927c94a82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=390338288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.390338288
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1081658510
Short name	T390
Test name
Test status
Simulation time	12195105844 ps
CPU time	62.73 seconds
Started	Apr 02 12:53:42 PM PDT 24
Finished	Apr 02 12:54:45 PM PDT 24
Peak memory	204684 kb
Host	smart-231fce71-4cf4-43a2-b66a-545a0b30dc1f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1081658510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.1081658510
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.449436671
Short name	T743
Test name
Test status
Simulation time	478651585 ps
CPU time	22.22 seconds
Started	Apr 02 12:53:43 PM PDT 24
Finished	Apr 02 12:54:05 PM PDT 24
Peak memory	211684 kb
Host	smart-246034e8-83da-48ef-aeb6-6281bb544992
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=449436671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.449436671
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.1261158703
Short name	T425
Test name
Test status
Simulation time	1503785193 ps
CPU time	29.66 seconds
Started	Apr 02 12:53:41 PM PDT 24
Finished	Apr 02 12:54:11 PM PDT 24
Peak memory	203484 kb
Host	smart-454f6950-76c9-4e0f-bbb7-edcd5213cbeb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1261158703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1261158703
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.574000376
Short name	T900
Test name
Test status
Simulation time	91986843 ps
CPU time	12.91 seconds
Started	Apr 02 12:53:37 PM PDT 24
Finished	Apr 02 12:53:50 PM PDT 24
Peak memory	204616 kb
Host	smart-142344c5-407c-4d24-9655-0b2efb88f337
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=574000376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.574000376
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.712816436
Short name	T546
Test name
Test status
Simulation time	13961062810 ps
CPU time	70.45 seconds
Started	Apr 02 12:53:38 PM PDT 24
Finished	Apr 02 12:54:49 PM PDT 24
Peak memory	204856 kb
Host	smart-1c627865-6106-49ea-b686-2f6b640bae1a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=712816436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.712816436
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3826093138
Short name	T41
Test name
Test status
Simulation time	46150298687 ps
CPU time	213.36 seconds
Started	Apr 02 12:53:38 PM PDT 24
Finished	Apr 02 12:57:12 PM PDT 24
Peak memory	205428 kb
Host	smart-2a9815ac-3531-4abb-81dc-67818b4334e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3826093138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3826093138
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1920271710
Short name	T11
Test name
Test status
Simulation time	94747512 ps
CPU time	13.09 seconds
Started	Apr 02 12:53:38 PM PDT 24
Finished	Apr 02 12:53:51 PM PDT 24
Peak memory	204484 kb
Host	smart-47171dc0-c4b0-4599-b624-82ace40a6182
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920271710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1920271710
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.4220574567
Short name	T765
Test name
Test status
Simulation time	3991890047 ps
CPU time	35.63 seconds
Started	Apr 02 12:53:42 PM PDT 24
Finished	Apr 02 12:54:18 PM PDT 24
Peak memory	204168 kb
Host	smart-ead163b6-37ee-4f15-ae87-b82e9f245469
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4220574567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4220574567
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.831862224
Short name	T553
Test name
Test status
Simulation time	150468369 ps
CPU time	3.62 seconds
Started	Apr 02 12:53:39 PM PDT 24
Finished	Apr 02 12:53:43 PM PDT 24
Peak memory	203504 kb
Host	smart-33bb7678-9874-4e98-a0e5-1fc8d30574e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831862224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.831862224
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2643767164
Short name	T749
Test name
Test status
Simulation time	13221907670 ps
CPU time	33.02 seconds
Started	Apr 02 12:53:37 PM PDT 24
Finished	Apr 02 12:54:10 PM PDT 24
Peak memory	203572 kb
Host	smart-0eef50d3-e773-42bf-be4e-b93d843be87f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643767164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2643767164
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3986678497
Short name	T294
Test name
Test status
Simulation time	3492532708 ps
CPU time	25.68 seconds
Started	Apr 02 12:53:38 PM PDT 24
Finished	Apr 02 12:54:05 PM PDT 24
Peak memory	203552 kb
Host	smart-e053dc11-7d78-47b8-9700-b51d66b7258f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3986678497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3986678497
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2445692723
Short name	T730
Test name
Test status
Simulation time	37495186 ps
CPU time	2.04 seconds
Started	Apr 02 12:53:37 PM PDT 24
Finished	Apr 02 12:53:39 PM PDT 24
Peak memory	203408 kb
Host	smart-39e0ce64-1e85-40e4-9580-d40e78371ca1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445692723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2445692723
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.3628481520
Short name	T70
Test name
Test status
Simulation time	7424722352 ps
CPU time	196.76 seconds
Started	Apr 02 12:53:43 PM PDT 24
Finished	Apr 02 12:57:00 PM PDT 24
Peak memory	206452 kb
Host	smart-0957aeb7-f7ff-4874-9602-f8974a317b9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3628481520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3628481520
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1900967108
Short name	T694
Test name
Test status
Simulation time	17728270735 ps
CPU time	230.89 seconds
Started	Apr 02 12:53:42 PM PDT 24
Finished	Apr 02 12:57:33 PM PDT 24
Peak memory	207260 kb
Host	smart-408b90d1-0a2c-4752-8cf9-8dc84cabedab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1900967108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1900967108
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1660315385
Short name	T439
Test name
Test status
Simulation time	391781184 ps
CPU time	113.88 seconds
Started	Apr 02 12:53:41 PM PDT 24
Finished	Apr 02 12:55:35 PM PDT 24
Peak memory	209692 kb
Host	smart-f1127c10-edc7-4c52-a9fb-223017f02f5f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1660315385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1660315385
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3386670990
Short name	T393
Test name
Test status
Simulation time	51764895 ps
CPU time	2.57 seconds
Started	Apr 02 12:53:41 PM PDT 24
Finished	Apr 02 12:53:44 PM PDT 24
Peak memory	203484 kb
Host	smart-c0fb8be8-0722-44f5-a14e-c114a140f47f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386670990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3386670990
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2751897108
Short name	T133
Test name
Test status
Simulation time	1480060407 ps
CPU time	29.14 seconds
Started	Apr 02 12:53:44 PM PDT 24
Finished	Apr 02 12:54:14 PM PDT 24
Peak memory	204548 kb
Host	smart-db79ac1e-ad0e-4b3e-b60f-4850286e72df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751897108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2751897108
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.631446784
Short name	T732
Test name
Test status
Simulation time	13554932232 ps
CPU time	116.34 seconds
Started	Apr 02 12:53:47 PM PDT 24
Finished	Apr 02 12:55:44 PM PDT 24
Peak memory	211708 kb
Host	smart-4ee66674-6032-4765-ad22-4e793dab3fb3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=631446784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.631446784
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1744229997
Short name	T541
Test name
Test status
Simulation time	1876803635 ps
CPU time	21.81 seconds
Started	Apr 02 12:53:44 PM PDT 24
Finished	Apr 02 12:54:06 PM PDT 24
Peak memory	204028 kb
Host	smart-273710fc-434b-44ba-a90f-f488d20e0191
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1744229997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1744229997
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.3750444698
Short name	T442
Test name
Test status
Simulation time	1456699724 ps
CPU time	23.65 seconds
Started	Apr 02 12:53:48 PM PDT 24
Finished	Apr 02 12:54:13 PM PDT 24
Peak memory	203508 kb
Host	smart-849f255e-3ab4-49d6-b4d4-f5d34f6ce488
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3750444698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3750444698
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.1015753283
Short name	T549
Test name
Test status
Simulation time	299687138 ps
CPU time	24.8 seconds
Started	Apr 02 12:53:44 PM PDT 24
Finished	Apr 02 12:54:09 PM PDT 24
Peak memory	211604 kb
Host	smart-695119a3-a747-4f7f-b385-180ffbef8559
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1015753283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1015753283
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3669340428
Short name	T478
Test name
Test status
Simulation time	10692083641 ps
CPU time	69.73 seconds
Started	Apr 02 12:53:44 PM PDT 24
Finished	Apr 02 12:54:54 PM PDT 24
Peak memory	205008 kb
Host	smart-3c16e66c-5bbe-45e2-a817-a4cc8568cd6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669340428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3669340428
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1123751193
Short name	T140
Test name
Test status
Simulation time	21898565715 ps
CPU time	116.97 seconds
Started	Apr 02 12:53:44 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	211696 kb
Host	smart-b1d382eb-7da1-415c-8a82-3241f04540d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1123751193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1123751193
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1827756458
Short name	T623
Test name
Test status
Simulation time	75304120 ps
CPU time	13.35 seconds
Started	Apr 02 12:53:44 PM PDT 24
Finished	Apr 02 12:53:58 PM PDT 24
Peak memory	204524 kb
Host	smart-ccf3d736-5518-4540-ab6c-f76bae32b964
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827756458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1827756458
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.830679741
Short name	T80
Test name
Test status
Simulation time	715419682 ps
CPU time	14.07 seconds
Started	Apr 02 12:53:45 PM PDT 24
Finished	Apr 02 12:54:00 PM PDT 24
Peak memory	204216 kb
Host	smart-11b171ca-621e-4f06-8675-e16a08949320
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830679741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.830679741
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.1541638558
Short name	T180
Test name
Test status
Simulation time	381822432 ps
CPU time	4.18 seconds
Started	Apr 02 12:53:40 PM PDT 24
Finished	Apr 02 12:53:45 PM PDT 24
Peak memory	203412 kb
Host	smart-c6eab0a0-c2f5-48eb-b4e6-2b79c6e01b1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1541638558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1541638558
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1504024746
Short name	T512
Test name
Test status
Simulation time	4733021698 ps
CPU time	24.22 seconds
Started	Apr 02 12:53:40 PM PDT 24
Finished	Apr 02 12:54:05 PM PDT 24
Peak memory	203572 kb
Host	smart-eab827d8-ddfb-436f-a1f2-984268e167ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504024746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1504024746
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1248849065
Short name	T673
Test name
Test status
Simulation time	8359540987 ps
CPU time	29.51 seconds
Started	Apr 02 12:53:45 PM PDT 24
Finished	Apr 02 12:54:15 PM PDT 24
Peak memory	203488 kb
Host	smart-d261a0c9-ea3e-475d-9349-b16f64ae9755
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1248849065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1248849065
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1242459923
Short name	T576
Test name
Test status
Simulation time	36772839 ps
CPU time	2.22 seconds
Started	Apr 02 12:53:43 PM PDT 24
Finished	Apr 02 12:53:46 PM PDT 24
Peak memory	203504 kb
Host	smart-49d8d3bf-2e72-4482-8719-0133ea31ad29
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242459923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1242459923
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.2398714376
Short name	T36
Test name
Test status
Simulation time	434968461 ps
CPU time	7.04 seconds
Started	Apr 02 12:53:45 PM PDT 24
Finished	Apr 02 12:53:52 PM PDT 24
Peak memory	204864 kb
Host	smart-487dc962-90fd-4567-baa6-3d7f2ad31ad0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2398714376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2398714376
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1095858868
Short name	T860
Test name
Test status
Simulation time	5734674583 ps
CPU time	136.59 seconds
Started	Apr 02 12:53:46 PM PDT 24
Finished	Apr 02 12:56:03 PM PDT 24
Peak memory	209080 kb
Host	smart-30e1bb00-137d-4f93-9b69-73bb17b39a13
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1095858868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1095858868
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.325868999
Short name	T489
Test name
Test status
Simulation time	248273278 ps
CPU time	116.59 seconds
Started	Apr 02 12:53:51 PM PDT 24
Finished	Apr 02 12:55:47 PM PDT 24
Peak memory	208000 kb
Host	smart-5dc62f02-fc39-476e-b830-859a24b336b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325868999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.325868999
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.319473328
Short name	T412
Test name
Test status
Simulation time	2783691882 ps
CPU time	452.41 seconds
Started	Apr 02 12:53:45 PM PDT 24
Finished	Apr 02 01:01:18 PM PDT 24
Peak memory	220932 kb
Host	smart-687fbfa5-3549-4174-9043-241ba1d0070d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=319473328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.319473328
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3380338387
Short name	T432
Test name
Test status
Simulation time	73123386 ps
CPU time	12.08 seconds
Started	Apr 02 12:53:48 PM PDT 24
Finished	Apr 02 12:54:00 PM PDT 24
Peak memory	204876 kb
Host	smart-e05779ba-00dc-4393-9433-e0edce47dd42
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3380338387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3380338387
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3861422642
Short name	T201
Test name
Test status
Simulation time	1577949683 ps
CPU time	64.67 seconds
Started	Apr 02 12:53:49 PM PDT 24
Finished	Apr 02 12:54:54 PM PDT 24
Peak memory	205756 kb
Host	smart-7c1cf035-0632-41e3-8714-c210dc881a02
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3861422642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3861422642
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2370927731
Short name	T111
Test name
Test status
Simulation time	42348635391 ps
CPU time	288.92 seconds
Started	Apr 02 12:53:51 PM PDT 24
Finished	Apr 02 12:58:40 PM PDT 24
Peak memory	205964 kb
Host	smart-953498a6-ffc5-4bf6-a4d8-fb81b2b535f1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2370927731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2370927731
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1800710894
Short name	T536
Test name
Test status
Simulation time	3807030674 ps
CPU time	21.83 seconds
Started	Apr 02 12:53:48 PM PDT 24
Finished	Apr 02 12:54:10 PM PDT 24
Peak memory	203584 kb
Host	smart-3a031a47-f89c-417d-b9c8-e8e3e4322cc3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1800710894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1800710894
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.1431807109
Short name	T323
Test name
Test status
Simulation time	1102590150 ps
CPU time	24.79 seconds
Started	Apr 02 12:53:52 PM PDT 24
Finished	Apr 02 12:54:17 PM PDT 24
Peak memory	203604 kb
Host	smart-05c57ad8-61f7-46c5-813b-8ec63c4434e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1431807109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1431807109
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.1457646304
Short name	T16
Test name
Test status
Simulation time	617159358 ps
CPU time	27.7 seconds
Started	Apr 02 12:53:49 PM PDT 24
Finished	Apr 02 12:54:17 PM PDT 24
Peak memory	204956 kb
Host	smart-127f94c9-65a7-4c68-a2ed-ebdcd9095521
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1457646304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1457646304
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2145178444
Short name	T249
Test name
Test status
Simulation time	23394812685 ps
CPU time	98.99 seconds
Started	Apr 02 12:53:49 PM PDT 24
Finished	Apr 02 12:55:28 PM PDT 24
Peak memory	204880 kb
Host	smart-a9e0d4c8-2a66-4ddb-9fb8-d1781fc67378
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145178444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2145178444
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2726870035
Short name	T130
Test name
Test status
Simulation time	36185118474 ps
CPU time	110.4 seconds
Started	Apr 02 12:53:48 PM PDT 24
Finished	Apr 02 12:55:40 PM PDT 24
Peak memory	204996 kb
Host	smart-998f9744-dece-4de7-aa1b-5528312f3341
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2726870035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2726870035
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3099855867
Short name	T741
Test name
Test status
Simulation time	70070473 ps
CPU time	10.55 seconds
Started	Apr 02 12:53:49 PM PDT 24
Finished	Apr 02 12:54:00 PM PDT 24
Peak memory	204612 kb
Host	smart-42306f99-5e67-4715-a14b-cad6cc662ed2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099855867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3099855867
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.2087218274
Short name	T355
Test name
Test status
Simulation time	334659011 ps
CPU time	20.28 seconds
Started	Apr 02 12:53:49 PM PDT 24
Finished	Apr 02 12:54:10 PM PDT 24
Peak memory	204056 kb
Host	smart-62feb240-2005-4fe4-9961-aeb9189af937
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2087218274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2087218274
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.271684758
Short name	T292
Test name
Test status
Simulation time	34718663 ps
CPU time	2.26 seconds
Started	Apr 02 12:53:47 PM PDT 24
Finished	Apr 02 12:53:50 PM PDT 24
Peak memory	203428 kb
Host	smart-cb7f8feb-c363-4f6e-af88-d933c4dd106e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=271684758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.271684758
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3957372971
Short name	T810
Test name
Test status
Simulation time	4997783373 ps
CPU time	30.17 seconds
Started	Apr 02 12:53:50 PM PDT 24
Finished	Apr 02 12:54:20 PM PDT 24
Peak memory	203544 kb
Host	smart-b5cbcf37-a8ba-41d3-b40b-9bed74640755
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957372971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3957372971
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.4172354726
Short name	T430
Test name
Test status
Simulation time	5883089410 ps
CPU time	37.2 seconds
Started	Apr 02 12:53:50 PM PDT 24
Finished	Apr 02 12:54:27 PM PDT 24
Peak memory	203544 kb
Host	smart-fbec8cdd-3f6b-4846-ba38-614b73e58f75
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4172354726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4172354726
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.4031702880
Short name	T372
Test name
Test status
Simulation time	146814915 ps
CPU time	2.63 seconds
Started	Apr 02 12:53:50 PM PDT 24
Finished	Apr 02 12:53:53 PM PDT 24
Peak memory	203508 kb
Host	smart-bafb8ca1-7ef2-435f-a602-07030ddff3e0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031702880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.4031702880
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.3545668368
Short name	T145
Test name
Test status
Simulation time	2023184419 ps
CPU time	23.78 seconds
Started	Apr 02 12:53:48 PM PDT 24
Finished	Apr 02 12:54:13 PM PDT 24
Peak memory	205524 kb
Host	smart-376c6026-919a-4cf9-afec-406269889381
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3545668368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3545668368
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3231152835
Short name	T808
Test name
Test status
Simulation time	6005046967 ps
CPU time	134.77 seconds
Started	Apr 02 12:53:49 PM PDT 24
Finished	Apr 02 12:56:04 PM PDT 24
Peak memory	206632 kb
Host	smart-4c187154-d66f-4aed-a79e-d78955646c76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3231152835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3231152835
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4009797889
Short name	T186
Test name
Test status
Simulation time	991661892 ps
CPU time	189.09 seconds
Started	Apr 02 12:53:49 PM PDT 24
Finished	Apr 02 12:56:58 PM PDT 24
Peak memory	208436 kb
Host	smart-8cb207a0-c9bb-415e-89af-f62b06669335
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4009797889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.4009797889
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1956116695
Short name	T500
Test name
Test status
Simulation time	6744988781 ps
CPU time	308.87 seconds
Started	Apr 02 12:53:53 PM PDT 24
Finished	Apr 02 12:59:02 PM PDT 24
Peak memory	211704 kb
Host	smart-d0ca9240-460b-4e16-8549-47f5cab3e063
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1956116695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1956116695
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2538919847
Short name	T202
Test name
Test status
Simulation time	23733603 ps
CPU time	2.86 seconds
Started	Apr 02 12:53:50 PM PDT 24
Finished	Apr 02 12:53:53 PM PDT 24
Peak memory	211596 kb
Host	smart-3f177ff4-2555-4da9-a01c-944d8df58573
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2538919847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2538919847
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4041897696
Short name	T896
Test name
Test status
Simulation time	143576028 ps
CPU time	12.28 seconds
Started	Apr 02 12:53:52 PM PDT 24
Finished	Apr 02 12:54:04 PM PDT 24
Peak memory	204528 kb
Host	smart-94a36245-5f93-444b-b2a9-1fdfbe33da5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4041897696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4041897696
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2330655037
Short name	T272
Test name
Test status
Simulation time	20079622394 ps
CPU time	86.44 seconds
Started	Apr 02 12:53:51 PM PDT 24
Finished	Apr 02 12:55:17 PM PDT 24
Peak memory	206096 kb
Host	smart-ac81ae5b-7d1d-4750-b90c-5339b9f445c0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2330655037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.2330655037
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2516196092
Short name	T125
Test name
Test status
Simulation time	173005314 ps
CPU time	9.14 seconds
Started	Apr 02 12:53:58 PM PDT 24
Finished	Apr 02 12:54:09 PM PDT 24
Peak memory	203688 kb
Host	smart-d2e807cc-9f09-4923-83f2-4642ef27c4ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2516196092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2516196092
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.2291300422
Short name	T712
Test name
Test status
Simulation time	75890050 ps
CPU time	10.46 seconds
Started	Apr 02 12:53:51 PM PDT 24
Finished	Apr 02 12:54:01 PM PDT 24
Peak memory	203528 kb
Host	smart-07a1f4d1-96b1-4c70-ac10-51e4eaafe9d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291300422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2291300422
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.1037084058
Short name	T131
Test name
Test status
Simulation time	851773863 ps
CPU time	21.32 seconds
Started	Apr 02 12:53:57 PM PDT 24
Finished	Apr 02 12:54:20 PM PDT 24
Peak memory	204572 kb
Host	smart-24404d7a-b716-41cb-9078-7868514ef71e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037084058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1037084058
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1103277989
Short name	T784
Test name
Test status
Simulation time	41396173643 ps
CPU time	215.27 seconds
Started	Apr 02 12:53:52 PM PDT 24
Finished	Apr 02 12:57:27 PM PDT 24
Peak memory	205080 kb
Host	smart-6101695f-5643-45de-bfb4-cdf7ae9f967c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103277989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1103277989
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1578288734
Short name	T289
Test name
Test status
Simulation time	5727866254 ps
CPU time	23.25 seconds
Started	Apr 02 12:53:53 PM PDT 24
Finished	Apr 02 12:54:16 PM PDT 24
Peak memory	204624 kb
Host	smart-8e533885-7b37-4b39-8d9a-56730b167556
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1578288734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1578288734
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1354114364
Short name	T223
Test name
Test status
Simulation time	215290566 ps
CPU time	24.17 seconds
Started	Apr 02 12:53:52 PM PDT 24
Finished	Apr 02 12:54:17 PM PDT 24
Peak memory	211608 kb
Host	smart-3b233072-5fb3-4a90-b7cf-40768049d751
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354114364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1354114364
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.2323698158
Short name	T874
Test name
Test status
Simulation time	4189088414 ps
CPU time	35.06 seconds
Started	Apr 02 12:53:52 PM PDT 24
Finished	Apr 02 12:54:27 PM PDT 24
Peak memory	203620 kb
Host	smart-2de661d4-7839-4236-a310-62e4576df829
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2323698158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2323698158
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.4244226528
Short name	T625
Test name
Test status
Simulation time	289375223 ps
CPU time	3.71 seconds
Started	Apr 02 12:53:53 PM PDT 24
Finished	Apr 02 12:53:57 PM PDT 24
Peak memory	203464 kb
Host	smart-8df7eb28-075b-412c-810a-73b58138031d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4244226528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4244226528
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2725393613
Short name	T333
Test name
Test status
Simulation time	5225191870 ps
CPU time	28.31 seconds
Started	Apr 02 12:53:52 PM PDT 24
Finished	Apr 02 12:54:20 PM PDT 24
Peak memory	203572 kb
Host	smart-713efd92-c87e-4084-a72e-b6189d219375
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725393613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2725393613
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2980874044
Short name	T457
Test name
Test status
Simulation time	4037666580 ps
CPU time	28.56 seconds
Started	Apr 02 12:53:51 PM PDT 24
Finished	Apr 02 12:54:20 PM PDT 24
Peak memory	203572 kb
Host	smart-00ff7ed5-d99a-4a31-aceb-d51ffed9abd2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2980874044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2980874044
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1754084391
Short name	T728
Test name
Test status
Simulation time	25766637 ps
CPU time	2.19 seconds
Started	Apr 02 12:53:52 PM PDT 24
Finished	Apr 02 12:53:55 PM PDT 24
Peak memory	203468 kb
Host	smart-f1c6adf1-8c33-4f8c-9348-b79f6fa0ed3a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754084391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1754084391
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.358900829
Short name	T779
Test name
Test status
Simulation time	2779691628 ps
CPU time	172.04 seconds
Started	Apr 02 12:53:56 PM PDT 24
Finished	Apr 02 12:56:49 PM PDT 24
Peak memory	209788 kb
Host	smart-e9346db9-3c43-4257-aaf5-0878e2862874
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=358900829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.358900829
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1317354000
Short name	T869
Test name
Test status
Simulation time	483562891 ps
CPU time	51.94 seconds
Started	Apr 02 12:53:59 PM PDT 24
Finished	Apr 02 12:54:53 PM PDT 24
Peak memory	206408 kb
Host	smart-fe114f39-b9dd-4e8d-abd7-50759c5be66f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1317354000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1317354000
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1973241507
Short name	T27
Test name
Test status
Simulation time	1555753489 ps
CPU time	380.59 seconds
Started	Apr 02 12:53:57 PM PDT 24
Finished	Apr 02 01:00:19 PM PDT 24
Peak memory	208488 kb
Host	smart-8db4e4cb-d1b8-44a7-8a1b-7bc4970bd6fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1973241507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1973241507
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1155024045
Short name	T527
Test name
Test status
Simulation time	327179896 ps
CPU time	117.92 seconds
Started	Apr 02 12:53:58 PM PDT 24
Finished	Apr 02 12:55:57 PM PDT 24
Peak memory	209116 kb
Host	smart-fb8e0f8b-7e41-444d-af4f-7cc81f33e1b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1155024045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1155024045
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3347821145
Short name	T492
Test name
Test status
Simulation time	1944897731 ps
CPU time	33.7 seconds
Started	Apr 02 12:54:00 PM PDT 24
Finished	Apr 02 12:54:35 PM PDT 24
Peak memory	204968 kb
Host	smart-983d8741-cf6e-483a-865c-7cdfb09c50f8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347821145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3347821145
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3038368215
Short name	T506
Test name
Test status
Simulation time	9376230302 ps
CPU time	75.85 seconds
Started	Apr 02 12:54:04 PM PDT 24
Finished	Apr 02 12:55:20 PM PDT 24
Peak memory	207504 kb
Host	smart-1d338c54-2479-46ed-a629-00d02e478a14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3038368215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3038368215
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.236227577
Short name	T61
Test name
Test status
Simulation time	65793772813 ps
CPU time	169.92 seconds
Started	Apr 02 12:54:04 PM PDT 24
Finished	Apr 02 12:56:54 PM PDT 24
Peak memory	211712 kb
Host	smart-7d612cfe-0d86-424b-adc5-69f4061ab1f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=236227577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.236227577
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3620489853
Short name	T597
Test name
Test status
Simulation time	210695861 ps
CPU time	17.66 seconds
Started	Apr 02 12:54:00 PM PDT 24
Finished	Apr 02 12:54:19 PM PDT 24
Peak memory	203732 kb
Host	smart-389af0f1-3aec-40c8-86cf-abc6046570f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3620489853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3620489853
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.3703195889
Short name	T340
Test name
Test status
Simulation time	3747130411 ps
CPU time	36.47 seconds
Started	Apr 02 12:53:57 PM PDT 24
Finished	Apr 02 12:54:35 PM PDT 24
Peak memory	203508 kb
Host	smart-784211be-9744-493b-9981-57ef1642d292
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3703195889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3703195889
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.4222042545
Short name	T861
Test name
Test status
Simulation time	1122042363 ps
CPU time	13.97 seconds
Started	Apr 02 12:53:58 PM PDT 24
Finished	Apr 02 12:54:13 PM PDT 24
Peak memory	204576 kb
Host	smart-2cacbecd-1535-42b7-bc26-18f2e10636f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4222042545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.4222042545
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3649771525
Short name	T251
Test name
Test status
Simulation time	46386124849 ps
CPU time	92.23 seconds
Started	Apr 02 12:53:58 PM PDT 24
Finished	Apr 02 12:55:31 PM PDT 24
Peak memory	211680 kb
Host	smart-17739433-6ef2-400c-b475-422cae580e20
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649771525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3649771525
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1808472384
Short name	T132
Test name
Test status
Simulation time	3322656539 ps
CPU time	25.58 seconds
Started	Apr 02 12:54:04 PM PDT 24
Finished	Apr 02 12:54:30 PM PDT 24
Peak memory	204252 kb
Host	smart-59f6abd9-f92c-4796-9c59-164369c3dbcd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1808472384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1808472384
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.77991151
Short name	T884
Test name
Test status
Simulation time	83525633 ps
CPU time	8.13 seconds
Started	Apr 02 12:53:58 PM PDT 24
Finished	Apr 02 12:54:07 PM PDT 24
Peak memory	204624 kb
Host	smart-8ad44f31-7402-4c12-92cd-f5cb045f7fb6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77991151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.77991151
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.3205807576
Short name	T642
Test name
Test status
Simulation time	1308328976 ps
CPU time	8.74 seconds
Started	Apr 02 12:53:56 PM PDT 24
Finished	Apr 02 12:54:06 PM PDT 24
Peak memory	203940 kb
Host	smart-ea987a5b-aba2-4b9a-bad0-8eb3673e1825
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3205807576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3205807576
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.562191173
Short name	T224
Test name
Test status
Simulation time	74767420 ps
CPU time	2.34 seconds
Started	Apr 02 12:53:57 PM PDT 24
Finished	Apr 02 12:54:01 PM PDT 24
Peak memory	203504 kb
Host	smart-c4991ab6-3c4d-4c02-9f36-874671ca1086
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=562191173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.562191173
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2035107403
Short name	T544
Test name
Test status
Simulation time	28314677960 ps
CPU time	42.3 seconds
Started	Apr 02 12:53:57 PM PDT 24
Finished	Apr 02 12:54:41 PM PDT 24
Peak memory	203572 kb
Host	smart-41a959f9-92d4-41b3-9bfd-034b3ed5457c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035107403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2035107403
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3777078804
Short name	T814
Test name
Test status
Simulation time	2519092999 ps
CPU time	25.28 seconds
Started	Apr 02 12:53:59 PM PDT 24
Finished	Apr 02 12:54:25 PM PDT 24
Peak memory	203508 kb
Host	smart-88b27a5f-1075-4da8-b678-941f98fb57f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3777078804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3777078804
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1026256370
Short name	T358
Test name
Test status
Simulation time	121844329 ps
CPU time	2.09 seconds
Started	Apr 02 12:53:57 PM PDT 24
Finished	Apr 02 12:53:59 PM PDT 24
Peak memory	203484 kb
Host	smart-af687314-1344-4fe7-b276-c586bfff5058
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026256370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1026256370
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.1814399124
Short name	T162
Test name
Test status
Simulation time	1979482459 ps
CPU time	43.59 seconds
Started	Apr 02 12:54:01 PM PDT 24
Finished	Apr 02 12:54:47 PM PDT 24
Peak memory	206232 kb
Host	smart-198923a8-3290-4a38-afa3-a8e38cc46d69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814399124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1814399124
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3452467661
Short name	T268
Test name
Test status
Simulation time	11532791704 ps
CPU time	95.31 seconds
Started	Apr 02 12:54:02 PM PDT 24
Finished	Apr 02 12:55:39 PM PDT 24
Peak memory	206328 kb
Host	smart-ac9b17a5-1843-4791-b0ae-ee44ae51a891
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3452467661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3452467661
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3440007601
Short name	T821
Test name
Test status
Simulation time	857335122 ps
CPU time	218.05 seconds
Started	Apr 02 12:54:01 PM PDT 24
Finished	Apr 02 12:57:40 PM PDT 24
Peak memory	209960 kb
Host	smart-0b5019e4-8bf4-44fb-9bc3-f481887a6b89
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440007601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3440007601
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.309608715
Short name	T651
Test name
Test status
Simulation time	16529485009 ps
CPU time	464.84 seconds
Started	Apr 02 12:54:01 PM PDT 24
Finished	Apr 02 01:01:46 PM PDT 24
Peak memory	227084 kb
Host	smart-16ff1f31-e8c8-488c-99e0-f6b28e0fe73d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=309608715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.309608715
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.4219689520
Short name	T338
Test name
Test status
Simulation time	53941357 ps
CPU time	3.07 seconds
Started	Apr 02 12:54:05 PM PDT 24
Finished	Apr 02 12:54:08 PM PDT 24
Peak memory	204540 kb
Host	smart-24f239d7-b98d-4f9e-8e8c-cce3bb3d0797
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4219689520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.4219689520
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2517446864
Short name	T397
Test name
Test status
Simulation time	693898347 ps
CPU time	30.04 seconds
Started	Apr 02 12:54:00 PM PDT 24
Finished	Apr 02 12:54:32 PM PDT 24
Peak memory	206232 kb
Host	smart-d59888e1-7394-4d7a-b619-ce78c56e3d23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2517446864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2517446864
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2205256096
Short name	T653
Test name
Test status
Simulation time	30691656595 ps
CPU time	127.79 seconds
Started	Apr 02 12:54:03 PM PDT 24
Finished	Apr 02 12:56:11 PM PDT 24
Peak memory	206036 kb
Host	smart-3a82d717-cf67-4944-a609-4939a2bb9f72
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2205256096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.2205256096
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.396480211
Short name	T389
Test name
Test status
Simulation time	457004010 ps
CPU time	12.22 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:19 PM PDT 24
Peak memory	203452 kb
Host	smart-399a0d92-8421-4433-8da5-5537ad0c121d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=396480211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.396480211
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.448054166
Short name	T568
Test name
Test status
Simulation time	1024818465 ps
CPU time	37.66 seconds
Started	Apr 02 12:54:00 PM PDT 24
Finished	Apr 02 12:54:39 PM PDT 24
Peak memory	203400 kb
Host	smart-19b84a0b-8f5f-4914-b6c6-d6af7bd56b67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=448054166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.448054166
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.1586975843
Short name	T163
Test name
Test status
Simulation time	1169923168 ps
CPU time	36.42 seconds
Started	Apr 02 12:54:01 PM PDT 24
Finished	Apr 02 12:54:38 PM PDT 24
Peak memory	204644 kb
Host	smart-badf9b8d-e97e-4979-bd7e-35c93dcc9ab3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1586975843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1586975843
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3828897842
Short name	T620
Test name
Test status
Simulation time	6506434416 ps
CPU time	12.8 seconds
Started	Apr 02 12:54:00 PM PDT 24
Finished	Apr 02 12:54:14 PM PDT 24
Peak memory	203552 kb
Host	smart-46bfedab-27c1-477b-84d4-a1f0bce4ca1a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828897842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3828897842
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4142930290
Short name	T686
Test name
Test status
Simulation time	60558548394 ps
CPU time	119.16 seconds
Started	Apr 02 12:54:02 PM PDT 24
Finished	Apr 02 12:56:03 PM PDT 24
Peak memory	211724 kb
Host	smart-0e080729-d573-453c-9dce-c8e020943e82
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4142930290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4142930290
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1885693205
Short name	T725
Test name
Test status
Simulation time	142127016 ps
CPU time	8.84 seconds
Started	Apr 02 12:54:00 PM PDT 24
Finished	Apr 02 12:54:10 PM PDT 24
Peak memory	204720 kb
Host	smart-db4b4daf-2465-477f-a2f5-64bbbde162c7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885693205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1885693205
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.2172393403
Short name	T280
Test name
Test status
Simulation time	646918041 ps
CPU time	16.02 seconds
Started	Apr 02 12:54:04 PM PDT 24
Finished	Apr 02 12:54:21 PM PDT 24
Peak memory	204116 kb
Host	smart-91535e22-035e-439a-90b6-23fc98d4b891
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2172393403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2172393403
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.678448119
Short name	T298
Test name
Test status
Simulation time	66158273 ps
CPU time	2.5 seconds
Started	Apr 02 12:54:00 PM PDT 24
Finished	Apr 02 12:54:04 PM PDT 24
Peak memory	203476 kb
Host	smart-462a6a81-b71a-4493-adf4-839e22afa886
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=678448119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.678448119
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2410028185
Short name	T309
Test name
Test status
Simulation time	6418037440 ps
CPU time	29.32 seconds
Started	Apr 02 12:54:03 PM PDT 24
Finished	Apr 02 12:54:33 PM PDT 24
Peak memory	203504 kb
Host	smart-58d39ff9-d79c-450b-b03c-5d2ba98ee367
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410028185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2410028185
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.566604625
Short name	T807
Test name
Test status
Simulation time	5314341966 ps
CPU time	37.16 seconds
Started	Apr 02 12:54:03 PM PDT 24
Finished	Apr 02 12:54:41 PM PDT 24
Peak memory	203556 kb
Host	smart-91e041b7-fdca-4238-8736-e5e92255cecb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=566604625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.566604625
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.182740315
Short name	T381
Test name
Test status
Simulation time	35654029 ps
CPU time	2.6 seconds
Started	Apr 02 12:54:04 PM PDT 24
Finished	Apr 02 12:54:07 PM PDT 24
Peak memory	203500 kb
Host	smart-1ab82372-caaa-4ae6-9850-f2e44fd93dd1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182740315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.182740315
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.3700187801
Short name	T179
Test name
Test status
Simulation time	3789991900 ps
CPU time	291.19 seconds
Started	Apr 02 12:54:03 PM PDT 24
Finished	Apr 02 12:58:55 PM PDT 24
Peak memory	212980 kb
Host	smart-781abfb6-a34c-433b-9d8a-f6a961907510
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3700187801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3700187801
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1802246691
Short name	T598
Test name
Test status
Simulation time	41840885655 ps
CPU time	284.01 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:58:51 PM PDT 24
Peak memory	207268 kb
Host	smart-6e66141c-1b0c-480a-b9cf-6410b1ef22e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1802246691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1802246691
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1569778493
Short name	T882
Test name
Test status
Simulation time	4284882005 ps
CPU time	344.87 seconds
Started	Apr 02 12:54:02 PM PDT 24
Finished	Apr 02 12:59:48 PM PDT 24
Peak memory	210896 kb
Host	smart-8e377511-6ae4-4b21-ad0e-af34fddeba67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1569778493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.1569778493
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1178350952
Short name	T484
Test name
Test status
Simulation time	531883426 ps
CPU time	54.33 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:55:01 PM PDT 24
Peak memory	207256 kb
Host	smart-b6d6da5c-018b-4169-bdf3-622d83777310
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1178350952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1178350952
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3656071899
Short name	T71
Test name
Test status
Simulation time	824951738 ps
CPU time	25.45 seconds
Started	Apr 02 12:54:01 PM PDT 24
Finished	Apr 02 12:54:29 PM PDT 24
Peak memory	205068 kb
Host	smart-0987a061-d5ae-41dc-807c-80ed7fd7f681
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3656071899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3656071899
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2456971616
Short name	T350
Test name
Test status
Simulation time	482294096 ps
CPU time	28.87 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:36 PM PDT 24
Peak memory	204972 kb
Host	smart-8eccc27e-cf90-44f0-a804-2495bdc56f73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2456971616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2456971616
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3200419079
Short name	T91
Test name
Test status
Simulation time	48437865012 ps
CPU time	214.55 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:57:41 PM PDT 24
Peak memory	206028 kb
Host	smart-8b8df78c-17e7-4f2d-9f6b-216da5f44d59
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3200419079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3200419079
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.4165816508
Short name	T569
Test name
Test status
Simulation time	3842474918 ps
CPU time	26.13 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:33 PM PDT 24
Peak memory	204044 kb
Host	smart-d853bcef-3df2-4a08-b75a-1c3236cd26dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4165816508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.4165816508
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.1113917793
Short name	T690
Test name
Test status
Simulation time	3392101171 ps
CPU time	24.56 seconds
Started	Apr 02 12:54:04 PM PDT 24
Finished	Apr 02 12:54:29 PM PDT 24
Peak memory	203524 kb
Host	smart-ec0d0956-ecf2-44b4-87e8-75e185ef997b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1113917793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1113917793
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.1500254995
Short name	T685
Test name
Test status
Simulation time	1552382330 ps
CPU time	16.83 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:24 PM PDT 24
Peak memory	204812 kb
Host	smart-6d13eda0-4f84-44b4-9cd8-79d883b945dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1500254995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1500254995
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1068290938
Short name	T102
Test name
Test status
Simulation time	22150500038 ps
CPU time	94.48 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	211764 kb
Host	smart-c1812b71-54d7-4044-9a8b-6009f8c579f5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068290938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1068290938
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3556286438
Short name	T473
Test name
Test status
Simulation time	34089656064 ps
CPU time	296.74 seconds
Started	Apr 02 12:54:08 PM PDT 24
Finished	Apr 02 12:59:05 PM PDT 24
Peak memory	205480 kb
Host	smart-6afeb6d0-252f-483e-b5db-b826cf34da71
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3556286438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3556286438
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1594012235
Short name	T210
Test name
Test status
Simulation time	248720634 ps
CPU time	18.25 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:25 PM PDT 24
Peak memory	211660 kb
Host	smart-4124479c-b349-4836-99f0-2adabf3a3ef9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594012235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1594012235
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.2948924134
Short name	T278
Test name
Test status
Simulation time	550318852 ps
CPU time	14.85 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:54:22 PM PDT 24
Peak memory	204168 kb
Host	smart-2ba6210e-b1b8-4a3b-934b-846f71a2e05c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2948924134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2948924134
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.3903732351
Short name	T832
Test name
Test status
Simulation time	87007986 ps
CPU time	2.44 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:54:09 PM PDT 24
Peak memory	203352 kb
Host	smart-64a82982-1a88-4f94-8c13-8bb6c5fa98d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3903732351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3903732351
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2431149922
Short name	T343
Test name
Test status
Simulation time	8370011193 ps
CPU time	29.31 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:36 PM PDT 24
Peak memory	203504 kb
Host	smart-40a72259-6bb1-4299-8c5d-f34dee733131
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431149922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2431149922
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2254522874
Short name	T379
Test name
Test status
Simulation time	9855882466 ps
CPU time	40.25 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:49 PM PDT 24
Peak memory	203524 kb
Host	smart-0669a204-2174-48fc-ad8d-53a5594350ad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2254522874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2254522874
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.738469287
Short name	T315
Test name
Test status
Simulation time	65609346 ps
CPU time	2.32 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:09 PM PDT 24
Peak memory	203492 kb
Host	smart-c5a58804-a610-4efc-81e1-ad81e33b5c27
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738469287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.738469287
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.1220460074
Short name	T252
Test name
Test status
Simulation time	2166808317 ps
CPU time	67.43 seconds
Started	Apr 02 12:54:05 PM PDT 24
Finished	Apr 02 12:55:13 PM PDT 24
Peak memory	205264 kb
Host	smart-b5f0ac73-01c9-48d1-afae-1d24a28cd3f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1220460074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1220460074
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.568897537
Short name	T346
Test name
Test status
Simulation time	1154195683 ps
CPU time	20.96 seconds
Started	Apr 02 12:54:07 PM PDT 24
Finished	Apr 02 12:54:29 PM PDT 24
Peak memory	203972 kb
Host	smart-eab747f0-a49a-4a0b-b14d-9585350a8743
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=568897537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.568897537
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.296598836
Short name	T740
Test name
Test status
Simulation time	231442056 ps
CPU time	131.1 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:56:18 PM PDT 24
Peak memory	207128 kb
Host	smart-7054bd15-7769-4b1b-b137-e276341e73cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=296598836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.296598836
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2937661224
Short name	T791
Test name
Test status
Simulation time	1022053639 ps
CPU time	234.71 seconds
Started	Apr 02 12:54:04 PM PDT 24
Finished	Apr 02 12:57:59 PM PDT 24
Peak memory	219808 kb
Host	smart-de3dc2d8-6c00-4cf9-840c-d76b836f263d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2937661224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2937661224
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2109001992
Short name	T50
Test name
Test status
Simulation time	115879680 ps
CPU time	5.37 seconds
Started	Apr 02 12:54:05 PM PDT 24
Finished	Apr 02 12:54:11 PM PDT 24
Peak memory	211604 kb
Host	smart-b32e847d-e549-450f-97b3-c42807009f45
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2109001992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2109001992
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.62360125
Short name	T259
Test name
Test status
Simulation time	1674322092 ps
CPU time	33.32 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:53:01 PM PDT 24
Peak memory	205464 kb
Host	smart-34fb36a5-a3b9-4cd1-b286-7d0df77b804b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=62360125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.62360125
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2641278069
Short name	T93
Test name
Test status
Simulation time	31445848612 ps
CPU time	131.39 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:54:32 PM PDT 24
Peak memory	205912 kb
Host	smart-51450c60-2a73-42f7-aeca-29097a46a458
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2641278069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.2641278069
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3909775158
Short name	T551
Test name
Test status
Simulation time	258625261 ps
CPU time	16.86 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:52:46 PM PDT 24
Peak memory	203396 kb
Host	smart-45ec05de-b6f9-4839-9a97-df5d4e60c990
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3909775158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3909775158
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.1161198095
Short name	T793
Test name
Test status
Simulation time	171759021 ps
CPU time	14.01 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:52:44 PM PDT 24
Peak memory	203392 kb
Host	smart-ea6b4b6c-7d17-4a71-aa31-405ec16634ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1161198095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1161198095
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.2686550361
Short name	T187
Test name
Test status
Simulation time	1608157662 ps
CPU time	28.49 seconds
Started	Apr 02 12:52:15 PM PDT 24
Finished	Apr 02 12:52:44 PM PDT 24
Peak memory	204728 kb
Host	smart-b012cc37-4d7c-4c95-b739-b26712b159e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2686550361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2686550361
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3873073941
Short name	T141
Test name
Test status
Simulation time	58916948143 ps
CPU time	118.93 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:54:20 PM PDT 24
Peak memory	204888 kb
Host	smart-55533c46-7c5e-4dda-8bab-7d6e8661776c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873073941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3873073941
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.640308635
Short name	T85
Test name
Test status
Simulation time	51350422168 ps
CPU time	211.61 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:56:00 PM PDT 24
Peak memory	211652 kb
Host	smart-1ae24376-f454-4aed-8c12-76b21aee366d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=640308635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.640308635
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2092625973
Short name	T840
Test name
Test status
Simulation time	300048120 ps
CPU time	13.13 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:52:33 PM PDT 24
Peak memory	204548 kb
Host	smart-ad11c083-435d-46d1-9cee-aacaa7619293
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092625973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2092625973
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.101170066
Short name	T742
Test name
Test status
Simulation time	1125952805 ps
CPU time	19.08 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:52:48 PM PDT 24
Peak memory	204052 kb
Host	smart-ea31aa5e-6e82-446d-8c19-23663d7f0897
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=101170066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.101170066
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.1585497314
Short name	T617
Test name
Test status
Simulation time	39080479 ps
CPU time	2.41 seconds
Started	Apr 02 12:52:17 PM PDT 24
Finished	Apr 02 12:52:19 PM PDT 24
Peak memory	203504 kb
Host	smart-33b96a6c-4cdc-49dc-bfaa-aa4cb553ae34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1585497314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1585497314
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3595683381
Short name	T750
Test name
Test status
Simulation time	12684386982 ps
CPU time	39.63 seconds
Started	Apr 02 12:52:30 PM PDT 24
Finished	Apr 02 12:53:10 PM PDT 24
Peak memory	203456 kb
Host	smart-a281fcf8-4566-44e5-9953-124cf132f692
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595683381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3595683381
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2287285485
Short name	T662
Test name
Test status
Simulation time	3306328627 ps
CPU time	27.33 seconds
Started	Apr 02 12:52:14 PM PDT 24
Finished	Apr 02 12:52:42 PM PDT 24
Peak memory	203536 kb
Host	smart-85c0bdb3-e23c-49da-8511-4d87468fbce4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2287285485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2287285485
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1122841433
Short name	T850
Test name
Test status
Simulation time	35815908 ps
CPU time	2.15 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:26 PM PDT 24
Peak memory	203500 kb
Host	smart-3676e13a-94e8-478f-82fa-ead24d12a25f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122841433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1122841433
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.1581839592
Short name	T232
Test name
Test status
Simulation time	5122647627 ps
CPU time	103.92 seconds
Started	Apr 02 12:52:18 PM PDT 24
Finished	Apr 02 12:54:02 PM PDT 24
Peak memory	207076 kb
Host	smart-0fd55f92-f5f2-461b-9e95-570ea25767f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1581839592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1581839592
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2846329101
Short name	T497
Test name
Test status
Simulation time	15446573605 ps
CPU time	291.07 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:57:21 PM PDT 24
Peak memory	207524 kb
Host	smart-5fd00ddf-6ae4-4222-8944-fe0ce251c226
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2846329101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2846329101
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1913463815
Short name	T468
Test name
Test status
Simulation time	99875076 ps
CPU time	15.73 seconds
Started	Apr 02 12:52:17 PM PDT 24
Finished	Apr 02 12:52:33 PM PDT 24
Peak memory	206424 kb
Host	smart-26262441-fb43-456a-ac7f-009d65bd9b63
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1913463815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.1913463815
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.4239453627
Short name	T689
Test name
Test status
Simulation time	2895090987 ps
CPU time	73.34 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:53:37 PM PDT 24
Peak memory	209628 kb
Host	smart-23733aa2-e84f-4a76-a965-52bf88e7b1d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4239453627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.4239453627
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.4242422703
Short name	T219
Test name
Test status
Simulation time	181703834 ps
CPU time	10.7 seconds
Started	Apr 02 12:52:15 PM PDT 24
Finished	Apr 02 12:52:26 PM PDT 24
Peak memory	205076 kb
Host	smart-ce45426a-1d42-4a0e-bbe2-fd327a7d9f03
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242422703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.4242422703
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.502580177
Short name	T565
Test name
Test status
Simulation time	208688463 ps
CPU time	6.6 seconds
Started	Apr 02 12:54:09 PM PDT 24
Finished	Apr 02 12:54:16 PM PDT 24
Peak memory	204000 kb
Host	smart-1ccaf1ac-d916-4b36-b87b-939ed7f353ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=502580177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.502580177
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3450195427
Short name	T470
Test name
Test status
Simulation time	53994177469 ps
CPU time	393.81 seconds
Started	Apr 02 12:54:12 PM PDT 24
Finished	Apr 02 01:00:46 PM PDT 24
Peak memory	206924 kb
Host	smart-460a6b01-c61d-4e8d-9fab-54856f551602
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3450195427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.3450195427
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3797799012
Short name	T265
Test name
Test status
Simulation time	1287932188 ps
CPU time	24.11 seconds
Started	Apr 02 12:54:11 PM PDT 24
Finished	Apr 02 12:54:35 PM PDT 24
Peak memory	203508 kb
Host	smart-07cfb14b-1738-4e9f-864b-106b87dbc22b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3797799012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3797799012
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.3464485221
Short name	T535
Test name
Test status
Simulation time	583972970 ps
CPU time	26.47 seconds
Started	Apr 02 12:54:12 PM PDT 24
Finished	Apr 02 12:54:38 PM PDT 24
Peak memory	204040 kb
Host	smart-9a4d12c9-5315-4638-909c-a2f9fb14bb59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3464485221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3464485221
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.2241979586
Short name	T279
Test name
Test status
Simulation time	23224415 ps
CPU time	3.63 seconds
Started	Apr 02 12:54:12 PM PDT 24
Finished	Apr 02 12:54:16 PM PDT 24
Peak memory	204112 kb
Host	smart-8a4ea939-a65e-40a0-a245-470508d27144
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2241979586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2241979586
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.381381406
Short name	T847
Test name
Test status
Simulation time	66103029135 ps
CPU time	157.24 seconds
Started	Apr 02 12:54:09 PM PDT 24
Finished	Apr 02 12:56:46 PM PDT 24
Peak memory	205020 kb
Host	smart-73a6d838-0c8e-4775-a93c-84276339f1b8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=381381406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.381381406
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3247938224
Short name	T114
Test name
Test status
Simulation time	22481651191 ps
CPU time	107.98 seconds
Started	Apr 02 12:54:11 PM PDT 24
Finished	Apr 02 12:55:59 PM PDT 24
Peak memory	204728 kb
Host	smart-6fbeddca-10fe-4be1-a656-c2ff4a8be0cd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3247938224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3247938224
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.578614980
Short name	T290
Test name
Test status
Simulation time	152536899 ps
CPU time	10.64 seconds
Started	Apr 02 12:54:08 PM PDT 24
Finished	Apr 02 12:54:19 PM PDT 24
Peak memory	211680 kb
Host	smart-dcc03252-9860-43f8-83eb-cf66c182da1f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578614980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.578614980
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.4278343819
Short name	T733
Test name
Test status
Simulation time	311845275 ps
CPU time	16.91 seconds
Started	Apr 02 12:54:11 PM PDT 24
Finished	Apr 02 12:54:28 PM PDT 24
Peak memory	203528 kb
Host	smart-e2c1d8f5-787c-4272-a145-ef4f02b7e513
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4278343819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4278343819
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.99442126
Short name	T684
Test name
Test status
Simulation time	132576978 ps
CPU time	3.77 seconds
Started	Apr 02 12:54:06 PM PDT 24
Finished	Apr 02 12:54:11 PM PDT 24
Peak memory	203508 kb
Host	smart-867475df-7ca9-495f-b705-49deac893dc7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=99442126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.99442126
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2376857493
Short name	T217
Test name
Test status
Simulation time	7179273545 ps
CPU time	24.86 seconds
Started	Apr 02 12:54:09 PM PDT 24
Finished	Apr 02 12:54:35 PM PDT 24
Peak memory	203472 kb
Host	smart-fb741eae-9ce1-447e-bed2-e5990bc0d021
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376857493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2376857493
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3705920358
Short name	T263
Test name
Test status
Simulation time	4726108073 ps
CPU time	33.2 seconds
Started	Apr 02 12:54:11 PM PDT 24
Finished	Apr 02 12:54:44 PM PDT 24
Peak memory	203572 kb
Host	smart-e531168c-f4ad-4fa0-ad04-d6a4c500142e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3705920358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3705920358
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2526628186
Short name	T291
Test name
Test status
Simulation time	25501535 ps
CPU time	2.13 seconds
Started	Apr 02 12:54:11 PM PDT 24
Finished	Apr 02 12:54:13 PM PDT 24
Peak memory	203512 kb
Host	smart-d73e6925-66a1-4784-bb94-6e85b9d79db3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526628186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2526628186
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.872108078
Short name	T502
Test name
Test status
Simulation time	242925222 ps
CPU time	21.86 seconds
Started	Apr 02 12:54:10 PM PDT 24
Finished	Apr 02 12:54:32 PM PDT 24
Peak memory	205264 kb
Host	smart-907bc1c7-21ff-4f3c-8c4d-5174be497fe6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=872108078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.872108078
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2619648296
Short name	T392
Test name
Test status
Simulation time	18612031757 ps
CPU time	290.22 seconds
Started	Apr 02 12:54:12 PM PDT 24
Finished	Apr 02 12:59:02 PM PDT 24
Peak memory	211204 kb
Host	smart-84c6dc4f-2bb7-409c-b3ee-083af6891741
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2619648296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2619648296
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.987460303
Short name	T231
Test name
Test status
Simulation time	372342039 ps
CPU time	270.01 seconds
Started	Apr 02 12:54:11 PM PDT 24
Finished	Apr 02 12:58:41 PM PDT 24
Peak memory	208728 kb
Host	smart-2e61174b-14f7-488f-ab04-9c4a0b217de5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987460303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand _reset.987460303
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1849655960
Short name	T440
Test name
Test status
Simulation time	1114537585 ps
CPU time	205.72 seconds
Started	Apr 02 12:54:10 PM PDT 24
Finished	Apr 02 12:57:36 PM PDT 24
Peak memory	219884 kb
Host	smart-b6052113-d8d8-45c6-96f3-7032fbf711b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1849655960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1849655960
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.3294006664
Short name	T109
Test name
Test status
Simulation time	606600513 ps
CPU time	13.74 seconds
Started	Apr 02 12:54:10 PM PDT 24
Finished	Apr 02 12:54:24 PM PDT 24
Peak memory	205032 kb
Host	smart-875de6d2-1870-483f-9239-99fa6e544010
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3294006664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3294006664
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2394829533
Short name	T75
Test name
Test status
Simulation time	235397826 ps
CPU time	27.51 seconds
Started	Apr 02 12:54:16 PM PDT 24
Finished	Apr 02 12:54:44 PM PDT 24
Peak memory	211608 kb
Host	smart-fa219f9c-facd-450b-ad26-ffdea7b2d6f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394829533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2394829533
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.4034883033
Short name	T169
Test name
Test status
Simulation time	82279773236 ps
CPU time	598.36 seconds
Started	Apr 02 12:54:16 PM PDT 24
Finished	Apr 02 01:04:14 PM PDT 24
Peak memory	207372 kb
Host	smart-acdf98d5-f892-4371-85c8-96798d3eb827
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4034883033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.4034883033
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1714949165
Short name	T726
Test name
Test status
Simulation time	158613189 ps
CPU time	14.25 seconds
Started	Apr 02 12:54:21 PM PDT 24
Finished	Apr 02 12:54:35 PM PDT 24
Peak memory	203476 kb
Host	smart-bf417557-065a-457d-b461-38e5f78ec8e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1714949165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1714949165
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.2259095330
Short name	T533
Test name
Test status
Simulation time	2032354548 ps
CPU time	28.31 seconds
Started	Apr 02 12:54:14 PM PDT 24
Finished	Apr 02 12:54:43 PM PDT 24
Peak memory	203492 kb
Host	smart-ec8f8a90-a5af-44bb-8cfe-06580f864dea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2259095330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2259095330
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.1024183698
Short name	T76
Test name
Test status
Simulation time	137612669 ps
CPU time	16.66 seconds
Started	Apr 02 12:54:14 PM PDT 24
Finished	Apr 02 12:54:31 PM PDT 24
Peak memory	211684 kb
Host	smart-9f217f7c-118b-422b-b7bb-0004ea6494c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1024183698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1024183698
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3814868554
Short name	T688
Test name
Test status
Simulation time	12017045692 ps
CPU time	39.79 seconds
Started	Apr 02 12:54:18 PM PDT 24
Finished	Apr 02 12:54:58 PM PDT 24
Peak memory	211680 kb
Host	smart-620e2af7-c7a6-4b51-90c7-c15173a9c410
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814868554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3814868554
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.735374119
Short name	T296
Test name
Test status
Simulation time	18960502948 ps
CPU time	176.31 seconds
Started	Apr 02 12:54:13 PM PDT 24
Finished	Apr 02 12:57:09 PM PDT 24
Peak memory	211700 kb
Host	smart-283c218e-dd09-4c30-9c55-9f877ea062ad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=735374119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.735374119
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3428899312
Short name	T426
Test name
Test status
Simulation time	327593481 ps
CPU time	25.77 seconds
Started	Apr 02 12:54:16 PM PDT 24
Finished	Apr 02 12:54:42 PM PDT 24
Peak memory	205004 kb
Host	smart-48490d77-3689-4eca-86ae-12c44dab4eed
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428899312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3428899312
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.819642969
Short name	T672
Test name
Test status
Simulation time	1114386558 ps
CPU time	18.26 seconds
Started	Apr 02 12:54:13 PM PDT 24
Finished	Apr 02 12:54:31 PM PDT 24
Peak memory	204040 kb
Host	smart-b2a41617-e369-4fd9-9531-7a3a90de59ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=819642969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.819642969
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.3927329724
Short name	T697
Test name
Test status
Simulation time	30311138 ps
CPU time	2.61 seconds
Started	Apr 02 12:54:16 PM PDT 24
Finished	Apr 02 12:54:19 PM PDT 24
Peak memory	203472 kb
Host	smart-44cdd7b0-620f-4c45-8f48-699b857faa61
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3927329724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3927329724
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2367405755
Short name	T817
Test name
Test status
Simulation time	16180663809 ps
CPU time	38.62 seconds
Started	Apr 02 12:54:20 PM PDT 24
Finished	Apr 02 12:54:58 PM PDT 24
Peak memory	203540 kb
Host	smart-bff81b36-6f46-469f-8449-79dc252202de
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367405755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2367405755
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3987193438
Short name	T594
Test name
Test status
Simulation time	3536333519 ps
CPU time	26.38 seconds
Started	Apr 02 12:54:14 PM PDT 24
Finished	Apr 02 12:54:40 PM PDT 24
Peak memory	203556 kb
Host	smart-4b1ef799-cc05-49ad-b1cf-eb1a15625615
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3987193438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3987193438
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.148011069
Short name	T890
Test name
Test status
Simulation time	29314058 ps
CPU time	2.24 seconds
Started	Apr 02 12:54:14 PM PDT 24
Finished	Apr 02 12:54:17 PM PDT 24
Peak memory	203492 kb
Host	smart-7b465e61-c7df-4284-b481-62448016e1b4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148011069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.148011069
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.3766660725
Short name	T493
Test name
Test status
Simulation time	2523787581 ps
CPU time	58.28 seconds
Started	Apr 02 12:54:16 PM PDT 24
Finished	Apr 02 12:55:14 PM PDT 24
Peak memory	205660 kb
Host	smart-6a747089-be56-4b07-9137-03e136e76810
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3766660725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3766660725
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1743113314
Short name	T767
Test name
Test status
Simulation time	18477103270 ps
CPU time	319.37 seconds
Started	Apr 02 12:54:17 PM PDT 24
Finished	Apr 02 12:59:37 PM PDT 24
Peak memory	211748 kb
Host	smart-4251ffd6-4718-4e55-95ec-a56e2e2650e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1743113314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1743113314
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4081621935
Short name	T475
Test name
Test status
Simulation time	442796280 ps
CPU time	74.96 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:55:37 PM PDT 24
Peak memory	206964 kb
Host	smart-a4a7509c-15d0-46d2-866c-7aec10e08a02
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4081621935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.4081621935
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1460785181
Short name	T788
Test name
Test status
Simulation time	164909963 ps
CPU time	32.37 seconds
Started	Apr 02 12:54:20 PM PDT 24
Finished	Apr 02 12:54:53 PM PDT 24
Peak memory	206224 kb
Host	smart-d7129dd8-05b1-40d1-bfee-5d80bf0ed5ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460785181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1460785181
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3922384406
Short name	T403
Test name
Test status
Simulation time	80245131 ps
CPU time	2.54 seconds
Started	Apr 02 12:54:14 PM PDT 24
Finished	Apr 02 12:54:17 PM PDT 24
Peak memory	203488 kb
Host	smart-50efccfc-1ef7-4763-8f1a-84dd1a5ad6cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3922384406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3922384406
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.397581462
Short name	T139
Test name
Test status
Simulation time	443171351 ps
CPU time	4.06 seconds
Started	Apr 02 12:54:21 PM PDT 24
Finished	Apr 02 12:54:25 PM PDT 24
Peak memory	203552 kb
Host	smart-3ba933c0-a30a-48f2-bc62-6a0fab0f123d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=397581462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.397581462
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2022004472
Short name	T239
Test name
Test status
Simulation time	69274794502 ps
CPU time	331.96 seconds
Started	Apr 02 12:54:18 PM PDT 24
Finished	Apr 02 12:59:51 PM PDT 24
Peak memory	206876 kb
Host	smart-7407dd8e-304e-4774-a1d8-ec7a2fa1bbcd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2022004472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2022004472
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.4149803447
Short name	T521
Test name
Test status
Simulation time	174253457 ps
CPU time	6.27 seconds
Started	Apr 02 12:54:20 PM PDT 24
Finished	Apr 02 12:54:26 PM PDT 24
Peak memory	203652 kb
Host	smart-2ad9145a-3e12-4448-bb73-d99c9ba346ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4149803447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.4149803447
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.3090650087
Short name	T892
Test name
Test status
Simulation time	222276584 ps
CPU time	4.24 seconds
Started	Apr 02 12:54:19 PM PDT 24
Finished	Apr 02 12:54:23 PM PDT 24
Peak memory	203476 kb
Host	smart-7192d865-3567-4a9a-9540-18e005c3e165
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3090650087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3090650087
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.988676897
Short name	T209
Test name
Test status
Simulation time	110650749 ps
CPU time	18.15 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:54:40 PM PDT 24
Peak memory	204716 kb
Host	smart-5a7efed5-0950-4bbf-a7be-918363caaa0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=988676897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.988676897
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1608516032
Short name	T852
Test name
Test status
Simulation time	66414590238 ps
CPU time	294.06 seconds
Started	Apr 02 12:54:19 PM PDT 24
Finished	Apr 02 12:59:14 PM PDT 24
Peak memory	204868 kb
Host	smart-8c469275-375a-4123-88e8-999faa23f66c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608516032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1608516032
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.417968929
Short name	T801
Test name
Test status
Simulation time	1484378180 ps
CPU time	12.23 seconds
Started	Apr 02 12:54:20 PM PDT 24
Finished	Apr 02 12:54:33 PM PDT 24
Peak memory	203512 kb
Host	smart-e8276c0f-7e5e-43e0-b566-c196d76bb432
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=417968929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.417968929
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3510039052
Short name	T627
Test name
Test status
Simulation time	191549564 ps
CPU time	22.25 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:54:44 PM PDT 24
Peak memory	211688 kb
Host	smart-97578a6c-4957-4155-93f4-1638797d2b52
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510039052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3510039052
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.4191598420
Short name	T486
Test name
Test status
Simulation time	1622496855 ps
CPU time	35.45 seconds
Started	Apr 02 12:54:20 PM PDT 24
Finished	Apr 02 12:54:55 PM PDT 24
Peak memory	204076 kb
Host	smart-6483b752-981b-4b3d-864e-403a1690cd04
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4191598420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4191598420
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.1934142107
Short name	T77
Test name
Test status
Simulation time	23934019 ps
CPU time	2.08 seconds
Started	Apr 02 12:54:20 PM PDT 24
Finished	Apr 02 12:54:22 PM PDT 24
Peak memory	203508 kb
Host	smart-c2e51674-7428-43b5-baf2-ac1eb70fa29b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1934142107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1934142107
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2741357868
Short name	T200
Test name
Test status
Simulation time	26324227857 ps
CPU time	40.24 seconds
Started	Apr 02 12:54:19 PM PDT 24
Finished	Apr 02 12:55:00 PM PDT 24
Peak memory	203504 kb
Host	smart-854d1551-78cf-4aea-863f-ab49e3d1f23d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741357868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2741357868
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2028665333
Short name	T462
Test name
Test status
Simulation time	16391664711 ps
CPU time	42.75 seconds
Started	Apr 02 12:54:19 PM PDT 24
Finished	Apr 02 12:55:02 PM PDT 24
Peak memory	203440 kb
Host	smart-5dab08d5-c292-40e3-b4c6-477e03226510
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2028665333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2028665333
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2379558490
Short name	T539
Test name
Test status
Simulation time	35692780 ps
CPU time	2.38 seconds
Started	Apr 02 12:54:19 PM PDT 24
Finished	Apr 02 12:54:21 PM PDT 24
Peak memory	203408 kb
Host	smart-2fcc07ad-7fde-48fa-bad8-1ca6ec2dcc73
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379558490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2379558490
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.1110309664
Short name	T408
Test name
Test status
Simulation time	6999761144 ps
CPU time	169.49 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:57:11 PM PDT 24
Peak memory	208764 kb
Host	smart-b8b21033-0ff0-46c8-b4ac-c315e7282cdf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1110309664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1110309664
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1881411107
Short name	T467
Test name
Test status
Simulation time	1897538065 ps
CPU time	60.05 seconds
Started	Apr 02 12:54:21 PM PDT 24
Finished	Apr 02 12:55:21 PM PDT 24
Peak memory	205836 kb
Host	smart-a2829659-cb6b-41c7-ad17-e4a3723be9ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1881411107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1881411107
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.467415963
Short name	T264
Test name
Test status
Simulation time	537009701 ps
CPU time	160.19 seconds
Started	Apr 02 12:54:21 PM PDT 24
Finished	Apr 02 12:57:01 PM PDT 24
Peak memory	211708 kb
Host	smart-36adb399-ebb1-471f-a00e-735e9ecfe6b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=467415963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res et_error.467415963
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3055904551
Short name	T406
Test name
Test status
Simulation time	380858993 ps
CPU time	12.89 seconds
Started	Apr 02 12:54:20 PM PDT 24
Finished	Apr 02 12:54:33 PM PDT 24
Peak memory	205048 kb
Host	smart-b7014a52-8cf0-4282-a2f4-43fdeecc562b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3055904551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3055904551
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.989978823
Short name	T9
Test name
Test status
Simulation time	97950905 ps
CPU time	11.07 seconds
Started	Apr 02 12:54:24 PM PDT 24
Finished	Apr 02 12:54:36 PM PDT 24
Peak memory	211612 kb
Host	smart-980a9af2-daff-4a33-9528-b05a853e951b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=989978823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.989978823
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1312239838
Short name	T89
Test name
Test status
Simulation time	145351307681 ps
CPU time	511.53 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 01:02:54 PM PDT 24
Peak memory	211768 kb
Host	smart-e017b957-11a8-4235-b984-5ee6c02a9739
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1312239838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1312239838
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1685856593
Short name	T585
Test name
Test status
Simulation time	1774354760 ps
CPU time	19.74 seconds
Started	Apr 02 12:54:23 PM PDT 24
Finished	Apr 02 12:54:43 PM PDT 24
Peak memory	203884 kb
Host	smart-ca83176f-ce2e-4e8e-8af0-05eb23e0b2df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1685856593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1685856593
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.3042686898
Short name	T282
Test name
Test status
Simulation time	98228969 ps
CPU time	2.81 seconds
Started	Apr 02 12:54:21 PM PDT 24
Finished	Apr 02 12:54:24 PM PDT 24
Peak memory	203480 kb
Host	smart-bec3f846-2b8c-4bca-ac5d-069740f72623
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3042686898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3042686898
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.591171240
Short name	T737
Test name
Test status
Simulation time	18863185 ps
CPU time	2.08 seconds
Started	Apr 02 12:54:24 PM PDT 24
Finished	Apr 02 12:54:26 PM PDT 24
Peak memory	203700 kb
Host	smart-2f85c135-47b4-4ee7-824e-b9d88002c192
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=591171240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.591171240
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3115329993
Short name	T316
Test name
Test status
Simulation time	7965735606 ps
CPU time	24.23 seconds
Started	Apr 02 12:54:23 PM PDT 24
Finished	Apr 02 12:54:47 PM PDT 24
Peak memory	203584 kb
Host	smart-ae406dfa-6efc-4757-9af1-b1870c87a49f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115329993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3115329993
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.322962924
Short name	T458
Test name
Test status
Simulation time	82292772773 ps
CPU time	275.79 seconds
Started	Apr 02 12:54:25 PM PDT 24
Finished	Apr 02 12:59:01 PM PDT 24
Peak memory	211720 kb
Host	smart-ee9276ef-c6c5-4a4e-891f-ffbe3c0381d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=322962924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.322962924
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1731480952
Short name	T354
Test name
Test status
Simulation time	316805049 ps
CPU time	29.23 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:55:00 PM PDT 24
Peak memory	204404 kb
Host	smart-b1b0dd40-8b95-404d-a69b-bd5e91e5fc78
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731480952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1731480952
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.3794754711
Short name	T881
Test name
Test status
Simulation time	53156036 ps
CPU time	1.89 seconds
Started	Apr 02 12:54:24 PM PDT 24
Finished	Apr 02 12:54:26 PM PDT 24
Peak memory	203504 kb
Host	smart-91856278-9814-4929-b261-f21aa7d8db73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3794754711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3794754711
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.3449316988
Short name	T849
Test name
Test status
Simulation time	301768456 ps
CPU time	4.04 seconds
Started	Apr 02 12:54:19 PM PDT 24
Finished	Apr 02 12:54:23 PM PDT 24
Peak memory	203420 kb
Host	smart-03a49441-02ac-4c91-a5c1-687fa509d76a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3449316988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3449316988
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3655380197
Short name	T692
Test name
Test status
Simulation time	29065627784 ps
CPU time	41.53 seconds
Started	Apr 02 12:54:24 PM PDT 24
Finished	Apr 02 12:55:05 PM PDT 24
Peak memory	203564 kb
Host	smart-fd7e256d-a785-4d0b-ac63-78449d484bb0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655380197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3655380197
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1565814755
Short name	T172
Test name
Test status
Simulation time	4261942391 ps
CPU time	28.69 seconds
Started	Apr 02 12:54:25 PM PDT 24
Finished	Apr 02 12:54:53 PM PDT 24
Peak memory	203556 kb
Host	smart-2759f8d5-7c48-410a-b007-b5155f85db9e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1565814755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1565814755
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2385359828
Short name	T330
Test name
Test status
Simulation time	32307002 ps
CPU time	2.21 seconds
Started	Apr 02 12:54:19 PM PDT 24
Finished	Apr 02 12:54:22 PM PDT 24
Peak memory	203432 kb
Host	smart-f8b78fea-cd3a-4228-9ac2-f628a977706b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385359828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2385359828
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.3426173196
Short name	T601
Test name
Test status
Simulation time	619383858 ps
CPU time	77.07 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:55:40 PM PDT 24
Peak memory	206448 kb
Host	smart-40eb2483-1a53-4ed0-b625-de8a55ea8634
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3426173196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3426173196
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2514619939
Short name	T255
Test name
Test status
Simulation time	13651089694 ps
CPU time	127.35 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:56:38 PM PDT 24
Peak memory	206260 kb
Host	smart-021fb9a6-907a-4999-98ea-e02e404b4329
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2514619939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2514619939
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3388672845
Short name	T150
Test name
Test status
Simulation time	7897257754 ps
CPU time	604.42 seconds
Started	Apr 02 12:54:29 PM PDT 24
Finished	Apr 02 01:04:34 PM PDT 24
Peak memory	209848 kb
Host	smart-24518421-7786-4d0a-a377-20f59789d4be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3388672845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3388672845
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1061674879
Short name	T795
Test name
Test status
Simulation time	130815039 ps
CPU time	3.76 seconds
Started	Apr 02 12:54:24 PM PDT 24
Finished	Apr 02 12:54:28 PM PDT 24
Peak memory	204260 kb
Host	smart-d9c09249-b275-4329-9342-24a27a559630
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1061674879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1061674879
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2017055680
Short name	T411
Test name
Test status
Simulation time	1501875119 ps
CPU time	42.77 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:55:13 PM PDT 24
Peak memory	205532 kb
Host	smart-ee85e187-70ee-47e3-a4cc-9c57db48b55b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2017055680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2017055680
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.530485836
Short name	T100
Test name
Test status
Simulation time	74350607804 ps
CPU time	568.19 seconds
Started	Apr 02 12:54:27 PM PDT 24
Finished	Apr 02 01:03:55 PM PDT 24
Peak memory	207472 kb
Host	smart-1747c50f-39b1-4deb-b613-ecc98b60a48e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=530485836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.530485836
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.347168835
Short name	T301
Test name
Test status
Simulation time	607158342 ps
CPU time	19.11 seconds
Started	Apr 02 12:54:27 PM PDT 24
Finished	Apr 02 12:54:46 PM PDT 24
Peak memory	204000 kb
Host	smart-9c0d4de8-8cdf-44fd-9461-3d9a09559240
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=347168835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.347168835
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.223575599
Short name	T370
Test name
Test status
Simulation time	303473269 ps
CPU time	2.87 seconds
Started	Apr 02 12:54:29 PM PDT 24
Finished	Apr 02 12:54:32 PM PDT 24
Peak memory	203468 kb
Host	smart-f27eb1a2-1dca-4a56-9ca0-21e160c7eab0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=223575599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.223575599
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.2652162915
Short name	T816
Test name
Test status
Simulation time	257396555 ps
CPU time	12.4 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:54:43 PM PDT 24
Peak memory	204692 kb
Host	smart-dedc2cad-953f-41be-aefe-8fffc9bbdb69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2652162915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2652162915
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2519632004
Short name	T762
Test name
Test status
Simulation time	51469759988 ps
CPU time	226.94 seconds
Started	Apr 02 12:54:23 PM PDT 24
Finished	Apr 02 12:58:10 PM PDT 24
Peak memory	205360 kb
Host	smart-f1de0d92-b6a8-4e37-b377-1ba7685ec5db
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519632004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2519632004
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.375358730
Short name	T459
Test name
Test status
Simulation time	96657447616 ps
CPU time	251.58 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:58:34 PM PDT 24
Peak memory	205344 kb
Host	smart-0392e5ee-24a7-4695-a652-c9503a6e962e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=375358730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.375358730
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1214334278
Short name	T254
Test name
Test status
Simulation time	29404666 ps
CPU time	2.2 seconds
Started	Apr 02 12:54:23 PM PDT 24
Finished	Apr 02 12:54:25 PM PDT 24
Peak memory	203508 kb
Host	smart-f1bf4346-59f1-4390-b30c-3ccfd8e281ef
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214334278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1214334278
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.3320573023
Short name	T520
Test name
Test status
Simulation time	114601031 ps
CPU time	10.15 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:54:40 PM PDT 24
Peak memory	203416 kb
Host	smart-05f8660d-af90-4ece-bdd5-4ec2be456dc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320573023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3320573023
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.4121646482
Short name	T622
Test name
Test status
Simulation time	58290295 ps
CPU time	2.42 seconds
Started	Apr 02 12:54:24 PM PDT 24
Finished	Apr 02 12:54:26 PM PDT 24
Peak memory	203460 kb
Host	smart-e66c6450-24a3-4cc9-94dd-790e2c1c6cf0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4121646482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4121646482
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2171006446
Short name	T454
Test name
Test status
Simulation time	6972214204 ps
CPU time	31.49 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:54:53 PM PDT 24
Peak memory	203552 kb
Host	smart-d543260d-fec8-426f-b2bc-f67696e60701
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171006446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2171006446
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2539868986
Short name	T708
Test name
Test status
Simulation time	11107132072 ps
CPU time	40.24 seconds
Started	Apr 02 12:54:23 PM PDT 24
Finished	Apr 02 12:55:04 PM PDT 24
Peak memory	203496 kb
Host	smart-48fbeef6-4cce-43f1-bdd9-258b37c47a8f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2539868986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2539868986
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.837901067
Short name	T407
Test name
Test status
Simulation time	42656342 ps
CPU time	2.66 seconds
Started	Apr 02 12:54:22 PM PDT 24
Finished	Apr 02 12:54:25 PM PDT 24
Peak memory	203500 kb
Host	smart-304afefe-2404-4cf2-b9b0-a800fcd6aeef
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837901067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.837901067
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.2005859734
Short name	T452
Test name
Test status
Simulation time	3028318346 ps
CPU time	87.61 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:55:58 PM PDT 24
Peak memory	206076 kb
Host	smart-1b64f224-d008-4f2e-9bab-1de50276c4ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2005859734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2005859734
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1279676275
Short name	T519
Test name
Test status
Simulation time	135216655 ps
CPU time	13.35 seconds
Started	Apr 02 12:54:28 PM PDT 24
Finished	Apr 02 12:54:42 PM PDT 24
Peak memory	204168 kb
Host	smart-36b9d57d-8853-4948-a203-45cf3899c5fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1279676275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1279676275
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.245447597
Short name	T352
Test name
Test status
Simulation time	1428642492 ps
CPU time	214.95 seconds
Started	Apr 02 12:54:26 PM PDT 24
Finished	Apr 02 12:58:01 PM PDT 24
Peak memory	211628 kb
Host	smart-34a8b1ba-d22b-4226-b1bc-ee4ae6219e3d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=245447597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand _reset.245447597
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.378751770
Short name	T638
Test name
Test status
Simulation time	169483703 ps
CPU time	79.36 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:55:50 PM PDT 24
Peak memory	208908 kb
Host	smart-4370c6a2-7aa6-49a5-94fe-8a841543d0b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=378751770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.378751770
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.889572839
Short name	T5
Test name
Test status
Simulation time	104656880 ps
CPU time	16.4 seconds
Started	Apr 02 12:54:26 PM PDT 24
Finished	Apr 02 12:54:43 PM PDT 24
Peak memory	211644 kb
Host	smart-1d7b50d9-1694-4054-a961-f684b89fd2b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=889572839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.889572839
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1881705099
Short name	T144
Test name
Test status
Simulation time	948658757 ps
CPU time	45.31 seconds
Started	Apr 02 12:54:32 PM PDT 24
Finished	Apr 02 12:55:18 PM PDT 24
Peak memory	211688 kb
Host	smart-13b73247-d205-4634-a3eb-8b5051e959e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1881705099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1881705099
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.4192542490
Short name	T274
Test name
Test status
Simulation time	65458475260 ps
CPU time	143.1 seconds
Started	Apr 02 12:54:29 PM PDT 24
Finished	Apr 02 12:56:53 PM PDT 24
Peak memory	211708 kb
Host	smart-b0908663-376f-483d-9b9e-08bab630dfc5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4192542490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.4192542490
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.463276224
Short name	T538
Test name
Test status
Simulation time	471473755 ps
CPU time	17.7 seconds
Started	Apr 02 12:54:33 PM PDT 24
Finished	Apr 02 12:54:51 PM PDT 24
Peak memory	203748 kb
Host	smart-7b219740-f669-4f62-b2a9-767af9fc3cc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=463276224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.463276224
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.560698429
Short name	T639
Test name
Test status
Simulation time	122577666 ps
CPU time	8.11 seconds
Started	Apr 02 12:54:32 PM PDT 24
Finished	Apr 02 12:54:40 PM PDT 24
Peak memory	203432 kb
Host	smart-3eadd05e-284c-46f9-97c5-20917cdc9b82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=560698429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.560698429
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.1690770305
Short name	T528
Test name
Test status
Simulation time	626841135 ps
CPU time	16.68 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:54:47 PM PDT 24
Peak memory	204580 kb
Host	smart-092bc90f-d5b7-458f-9b79-b1b9e7cb4287
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1690770305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1690770305
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1188560799
Short name	T367
Test name
Test status
Simulation time	51083226814 ps
CPU time	216.43 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:58:07 PM PDT 24
Peak memory	204960 kb
Host	smart-868983fd-4c8a-4405-9e28-2aeb24a87ef7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188560799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1188560799
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3942514857
Short name	T648
Test name
Test status
Simulation time	3323741479 ps
CPU time	34.23 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:55:05 PM PDT 24
Peak memory	204568 kb
Host	smart-11b7ef81-76c1-410e-a091-02e7c4cf14a3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3942514857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3942514857
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1990402360
Short name	T416
Test name
Test status
Simulation time	68888775 ps
CPU time	6.01 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:54:37 PM PDT 24
Peak memory	204572 kb
Host	smart-47cf4901-72ed-434d-b7bc-551f8c38c10b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990402360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1990402360
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.3033060216
Short name	T537
Test name
Test status
Simulation time	117636075 ps
CPU time	7.47 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:54:38 PM PDT 24
Peak memory	204192 kb
Host	smart-5a978763-7754-4680-b881-133015f49631
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3033060216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3033060216
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.3938079950
Short name	T711
Test name
Test status
Simulation time	42598925 ps
CPU time	2.05 seconds
Started	Apr 02 12:54:26 PM PDT 24
Finished	Apr 02 12:54:28 PM PDT 24
Peak memory	203416 kb
Host	smart-674b2843-b971-4baa-a079-75a0f55bbf59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3938079950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3938079950
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3870609361
Short name	T105
Test name
Test status
Simulation time	10900043691 ps
CPU time	29.93 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:55:01 PM PDT 24
Peak memory	203572 kb
Host	smart-b70f300e-e877-4fa0-a7c6-1ff09821ad96
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870609361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3870609361
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2990896798
Short name	T875
Test name
Test status
Simulation time	10396765906 ps
CPU time	31.94 seconds
Started	Apr 02 12:54:26 PM PDT 24
Finished	Apr 02 12:54:58 PM PDT 24
Peak memory	203568 kb
Host	smart-f4e31ae8-e51b-44ef-bab0-8f79864413f5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2990896798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2990896798
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1270513060
Short name	T806
Test name
Test status
Simulation time	125404022 ps
CPU time	2.97 seconds
Started	Apr 02 12:54:30 PM PDT 24
Finished	Apr 02 12:54:34 PM PDT 24
Peak memory	203488 kb
Host	smart-5ea097c8-d46e-43f3-8ffb-59dae8e39f8c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270513060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1270513060
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.2516151606
Short name	T242
Test name
Test status
Simulation time	8405283696 ps
CPU time	197.26 seconds
Started	Apr 02 12:54:31 PM PDT 24
Finished	Apr 02 12:57:49 PM PDT 24
Peak memory	207640 kb
Host	smart-cc9976c9-6599-456e-a675-773858d798ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2516151606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2516151606
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.143109968
Short name	T841
Test name
Test status
Simulation time	4103629272 ps
CPU time	84.76 seconds
Started	Apr 02 12:54:35 PM PDT 24
Finished	Apr 02 12:56:01 PM PDT 24
Peak memory	205092 kb
Host	smart-48004ea6-ea40-48a4-9e49-a1f053b341be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=143109968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.143109968
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.438439460
Short name	T7
Test name
Test status
Simulation time	11035434372 ps
CPU time	242.49 seconds
Started	Apr 02 12:54:35 PM PDT 24
Finished	Apr 02 12:58:37 PM PDT 24
Peak memory	209764 kb
Host	smart-4a641007-d068-4362-9810-b9d94a31062d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=438439460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.438439460
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2756890808
Short name	T415
Test name
Test status
Simulation time	224652504 ps
CPU time	66.09 seconds
Started	Apr 02 12:54:35 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	207184 kb
Host	smart-3d136d75-231d-44f2-a60d-59df2527ec0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2756890808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2756890808
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.915884170
Short name	T374
Test name
Test status
Simulation time	1738630728 ps
CPU time	23.72 seconds
Started	Apr 02 12:54:32 PM PDT 24
Finished	Apr 02 12:54:56 PM PDT 24
Peak memory	211672 kb
Host	smart-c2352ecf-0aed-47d5-af8d-f39f7f873987
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=915884170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.915884170
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.218568764
Short name	T53
Test name
Test status
Simulation time	1232324653 ps
CPU time	43.15 seconds
Started	Apr 02 12:54:37 PM PDT 24
Finished	Apr 02 12:55:20 PM PDT 24
Peak memory	211616 kb
Host	smart-c6aa3ae7-4652-4a3d-9999-5198d0df75ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=218568764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.218568764
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.683387895
Short name	T250
Test name
Test status
Simulation time	19655841822 ps
CPU time	169.19 seconds
Started	Apr 02 12:54:37 PM PDT 24
Finished	Apr 02 12:57:26 PM PDT 24
Peak memory	211676 kb
Host	smart-be0fe71c-9230-4d99-9085-7f3880eefad2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=683387895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.683387895
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2278945834
Short name	T682
Test name
Test status
Simulation time	149334019 ps
CPU time	3.44 seconds
Started	Apr 02 12:54:38 PM PDT 24
Finished	Apr 02 12:54:42 PM PDT 24
Peak memory	203500 kb
Host	smart-c7dc018a-3571-4426-ae2a-675d1458b400
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2278945834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2278945834
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.2969114812
Short name	T763
Test name
Test status
Simulation time	349091203 ps
CPU time	9.09 seconds
Started	Apr 02 12:54:43 PM PDT 24
Finished	Apr 02 12:54:52 PM PDT 24
Peak memory	203520 kb
Host	smart-2b26fb56-a386-42f7-8970-69c95697832f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2969114812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2969114812
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.850837359
Short name	T398
Test name
Test status
Simulation time	799314133 ps
CPU time	20.1 seconds
Started	Apr 02 12:54:34 PM PDT 24
Finished	Apr 02 12:54:54 PM PDT 24
Peak memory	205024 kb
Host	smart-2f970270-bbde-4aff-bffe-2c28c06158a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=850837359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.850837359
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3727084185
Short name	T724
Test name
Test status
Simulation time	44184183532 ps
CPU time	217.59 seconds
Started	Apr 02 12:54:33 PM PDT 24
Finished	Apr 02 12:58:11 PM PDT 24
Peak memory	205916 kb
Host	smart-5f05038b-02a7-4fe2-ab88-ed4377d7d34e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727084185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3727084185
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.663284250
Short name	T319
Test name
Test status
Simulation time	14226349885 ps
CPU time	116.51 seconds
Started	Apr 02 12:54:36 PM PDT 24
Finished	Apr 02 12:56:33 PM PDT 24
Peak memory	205012 kb
Host	smart-5cd07ac2-08ab-41e1-9c22-eab6aaa7e48b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=663284250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.663284250
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1948018547
Short name	T838
Test name
Test status
Simulation time	237987426 ps
CPU time	27.56 seconds
Started	Apr 02 12:54:35 PM PDT 24
Finished	Apr 02 12:55:03 PM PDT 24
Peak memory	204932 kb
Host	smart-c0745014-1d5f-4ab6-bb01-1b323e4859ac
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948018547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1948018547
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2278250429
Short name	T729
Test name
Test status
Simulation time	1348877114 ps
CPU time	30.56 seconds
Started	Apr 02 12:54:34 PM PDT 24
Finished	Apr 02 12:55:05 PM PDT 24
Peak memory	204112 kb
Host	smart-8e1447ec-2c53-4953-9936-6689a933c081
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2278250429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2278250429
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.2452869670
Short name	T829
Test name
Test status
Simulation time	757789249 ps
CPU time	3.96 seconds
Started	Apr 02 12:54:37 PM PDT 24
Finished	Apr 02 12:54:41 PM PDT 24
Peak memory	203420 kb
Host	smart-4fceae98-d6b0-45ff-9a96-fe26be4040bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2452869670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2452869670
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2172348514
Short name	T745
Test name
Test status
Simulation time	3619730719 ps
CPU time	23.03 seconds
Started	Apr 02 12:54:38 PM PDT 24
Finished	Apr 02 12:55:01 PM PDT 24
Peak memory	203492 kb
Host	smart-e67b02e8-47e5-42ab-88a0-80177d6650c8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172348514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2172348514
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3868825995
Short name	T498
Test name
Test status
Simulation time	9480686090 ps
CPU time	29.03 seconds
Started	Apr 02 12:54:34 PM PDT 24
Finished	Apr 02 12:55:03 PM PDT 24
Peak memory	203552 kb
Host	smart-f19a68a3-032e-4744-8209-3168b1b13cf2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3868825995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3868825995
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2500665935
Short name	T363
Test name
Test status
Simulation time	23556872 ps
CPU time	2.22 seconds
Started	Apr 02 12:54:33 PM PDT 24
Finished	Apr 02 12:54:35 PM PDT 24
Peak memory	203496 kb
Host	smart-3301dc3e-d2a0-4783-9745-562e2c5d3346
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500665935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2500665935
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.4018176548
Short name	T789
Test name
Test status
Simulation time	10692765926 ps
CPU time	264.47 seconds
Started	Apr 02 12:54:39 PM PDT 24
Finished	Apr 02 12:59:03 PM PDT 24
Peak memory	211756 kb
Host	smart-28736feb-b65e-4827-a5c4-0dcba5d691ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018176548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4018176548
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1875902647
Short name	T574
Test name
Test status
Simulation time	13713073249 ps
CPU time	181.65 seconds
Started	Apr 02 12:54:44 PM PDT 24
Finished	Apr 02 12:57:45 PM PDT 24
Peak memory	206816 kb
Host	smart-506ce153-67a5-4431-a0e1-1c578b74cdc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1875902647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1875902647
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3004400686
Short name	T640
Test name
Test status
Simulation time	643269480 ps
CPU time	179.43 seconds
Started	Apr 02 12:54:40 PM PDT 24
Finished	Apr 02 12:57:39 PM PDT 24
Peak memory	208784 kb
Host	smart-b1198555-b8e7-41f4-b17c-c944d311456b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3004400686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3004400686
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1349411651
Short name	T677
Test name
Test status
Simulation time	116118996 ps
CPU time	21.09 seconds
Started	Apr 02 12:54:37 PM PDT 24
Finished	Apr 02 12:54:59 PM PDT 24
Peak memory	205340 kb
Host	smart-3949ebc9-9b27-45e4-884f-740b574ff89f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1349411651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1349411651
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1579751889
Short name	T696
Test name
Test status
Simulation time	4238558684 ps
CPU time	74.03 seconds
Started	Apr 02 12:54:44 PM PDT 24
Finished	Apr 02 12:55:58 PM PDT 24
Peak memory	206872 kb
Host	smart-a6e86afb-b6c8-4855-a5b5-0ae12b5076f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1579751889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1579751889
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3358837964
Short name	T564
Test name
Test status
Simulation time	70230876297 ps
CPU time	438.97 seconds
Started	Apr 02 12:54:39 PM PDT 24
Finished	Apr 02 01:01:58 PM PDT 24
Peak memory	207020 kb
Host	smart-13211c60-8352-4559-bca7-8ba57af635f2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3358837964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3358837964
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2789495400
Short name	T660
Test name
Test status
Simulation time	190895009 ps
CPU time	19.04 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:55:00 PM PDT 24
Peak memory	203508 kb
Host	smart-ccbcf5de-4317-420a-8d99-38c331b8a165
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2789495400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2789495400
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.2971333323
Short name	T656
Test name
Test status
Simulation time	356588036 ps
CPU time	8.41 seconds
Started	Apr 02 12:54:38 PM PDT 24
Finished	Apr 02 12:54:47 PM PDT 24
Peak memory	203480 kb
Host	smart-fadaddd2-909f-4e8e-825e-0e0f9dc1f2b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971333323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2971333323
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.2617062149
Short name	T359
Test name
Test status
Simulation time	123907807 ps
CPU time	11.33 seconds
Started	Apr 02 12:54:36 PM PDT 24
Finished	Apr 02 12:54:48 PM PDT 24
Peak memory	204788 kb
Host	smart-1b57cd81-dcb9-454e-ac37-571a51a8f1b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2617062149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2617062149
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3878228437
Short name	T477
Test name
Test status
Simulation time	62174349336 ps
CPU time	226.54 seconds
Started	Apr 02 12:54:44 PM PDT 24
Finished	Apr 02 12:58:30 PM PDT 24
Peak memory	204780 kb
Host	smart-5699dc22-1507-4bcc-a2f8-97f82b6bc6b1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878228437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3878228437
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.93428740
Short name	T136
Test name
Test status
Simulation time	25918740582 ps
CPU time	67.44 seconds
Started	Apr 02 12:54:37 PM PDT 24
Finished	Apr 02 12:55:45 PM PDT 24
Peak memory	211780 kb
Host	smart-a08154ad-161e-4b30-82b3-da1d30df06f9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=93428740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.93428740
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2136342027
Short name	T659
Test name
Test status
Simulation time	357044169 ps
CPU time	13.65 seconds
Started	Apr 02 12:54:40 PM PDT 24
Finished	Apr 02 12:54:54 PM PDT 24
Peak memory	211676 kb
Host	smart-a0d4ef40-14b7-4d5e-b09c-e2e7af660e69
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136342027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2136342027
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.473335417
Short name	T751
Test name
Test status
Simulation time	4536366222 ps
CPU time	39.24 seconds
Started	Apr 02 12:54:37 PM PDT 24
Finished	Apr 02 12:55:16 PM PDT 24
Peak memory	204648 kb
Host	smart-210731cf-0f54-4d85-8833-3545ab17d373
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=473335417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.473335417
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.2853378223
Short name	T422
Test name
Test status
Simulation time	193931266 ps
CPU time	2.78 seconds
Started	Apr 02 12:54:39 PM PDT 24
Finished	Apr 02 12:54:42 PM PDT 24
Peak memory	203460 kb
Host	smart-a1a2ac8f-45b0-4862-aabe-1cf6052b5ba0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2853378223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2853378223
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4258990020
Short name	T828
Test name
Test status
Simulation time	16398990178 ps
CPU time	36.69 seconds
Started	Apr 02 12:54:36 PM PDT 24
Finished	Apr 02 12:55:13 PM PDT 24
Peak memory	203504 kb
Host	smart-2d190c45-8cb4-4b0f-bcff-1c48783a97ef
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258990020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4258990020
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.117514013
Short name	T336
Test name
Test status
Simulation time	3309007175 ps
CPU time	21.91 seconds
Started	Apr 02 12:54:38 PM PDT 24
Finished	Apr 02 12:55:00 PM PDT 24
Peak memory	203568 kb
Host	smart-c3695a88-ac05-47e5-965e-632c7b17e2e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=117514013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.117514013
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1145323317
Short name	T508
Test name
Test status
Simulation time	28768111 ps
CPU time	2.17 seconds
Started	Apr 02 12:54:40 PM PDT 24
Finished	Apr 02 12:54:43 PM PDT 24
Peak memory	203448 kb
Host	smart-052ed295-1b30-4a2b-9754-c2be95c16679
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145323317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1145323317
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.3196866440
Short name	T665
Test name
Test status
Simulation time	5848885253 ps
CPU time	125.59 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:56:47 PM PDT 24
Peak memory	209156 kb
Host	smart-e29476b3-4d8f-4e3b-9a27-e46bb957f4c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3196866440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3196866440
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.661334988
Short name	T443
Test name
Test status
Simulation time	3454327134 ps
CPU time	26.05 seconds
Started	Apr 02 12:54:40 PM PDT 24
Finished	Apr 02 12:55:07 PM PDT 24
Peak memory	204584 kb
Host	smart-6ab5ded8-a40a-490d-8075-1ae2fa086712
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=661334988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.661334988
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3532309657
Short name	T14
Test name
Test status
Simulation time	1545923396 ps
CPU time	390.11 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 01:01:11 PM PDT 24
Peak memory	219892 kb
Host	smart-971e3b95-b5f4-4ab7-a41f-4a43658d139f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3532309657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.3532309657
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3144757456
Short name	T277
Test name
Test status
Simulation time	710941701 ps
CPU time	223.25 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:58:25 PM PDT 24
Peak memory	219808 kb
Host	smart-2be2eb7b-74b6-4893-8543-ab8c8f27a369
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3144757456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3144757456
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2991029404
Short name	T428
Test name
Test status
Simulation time	968113210 ps
CPU time	12.84 seconds
Started	Apr 02 12:54:38 PM PDT 24
Finished	Apr 02 12:54:51 PM PDT 24
Peak memory	205056 kb
Host	smart-60f188e2-6e51-4a23-b3f9-5131f3863165
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991029404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2991029404
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3386906751
Short name	T417
Test name
Test status
Simulation time	884500203 ps
CPU time	10.29 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:54:51 PM PDT 24
Peak memory	204164 kb
Host	smart-546ca862-a651-4cea-bafa-dd8aa7193d73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386906751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3386906751
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3219431522
Short name	T580
Test name
Test status
Simulation time	55023884425 ps
CPU time	352.34 seconds
Started	Apr 02 12:54:43 PM PDT 24
Finished	Apr 02 01:00:36 PM PDT 24
Peak memory	205992 kb
Host	smart-19aebef6-81bf-472d-a9d5-fc4a88c18e5f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3219431522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3219431522
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.335193417
Short name	T545
Test name
Test status
Simulation time	147393014 ps
CPU time	11.06 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:54:57 PM PDT 24
Peak memory	203528 kb
Host	smart-4320fad8-12e1-4dc2-a51e-f76e77e50c0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=335193417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.335193417
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.1125934312
Short name	T603
Test name
Test status
Simulation time	373956342 ps
CPU time	11.78 seconds
Started	Apr 02 12:54:45 PM PDT 24
Finished	Apr 02 12:54:57 PM PDT 24
Peak memory	203504 kb
Host	smart-8ba2d74f-e7c7-410d-a586-ad67795e9cda
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1125934312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1125934312
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.2747559892
Short name	T94
Test name
Test status
Simulation time	161921393 ps
CPU time	5.5 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:54:46 PM PDT 24
Peak memory	204248 kb
Host	smart-b29ef720-f5d3-4a7f-a770-7672393d1f72
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2747559892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2747559892
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2117651464
Short name	T302
Test name
Test status
Simulation time	79995469591 ps
CPU time	190.92 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:57:52 PM PDT 24
Peak memory	204952 kb
Host	smart-0219991c-2592-4cfd-a8fa-db930f67966b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117651464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2117651464
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2391403497
Short name	T275
Test name
Test status
Simulation time	35637827441 ps
CPU time	299.46 seconds
Started	Apr 02 12:54:44 PM PDT 24
Finished	Apr 02 12:59:44 PM PDT 24
Peak memory	205500 kb
Host	smart-14e9cf7d-e710-45cd-a9be-a3fc20b6cf99
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2391403497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2391403497
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1677341786
Short name	T107
Test name
Test status
Simulation time	105073867 ps
CPU time	15.92 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:55:02 PM PDT 24
Peak memory	211688 kb
Host	smart-88ad0bb3-aedc-423b-8351-bdce5e3d77ea
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677341786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1677341786
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.2934169846
Short name	T96
Test name
Test status
Simulation time	2679236038 ps
CPU time	33.59 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:55:15 PM PDT 24
Peak memory	204292 kb
Host	smart-f9589bfe-f4b2-4ce8-9929-795632143b50
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2934169846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2934169846
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.541221183
Short name	T235
Test name
Test status
Simulation time	1094900428 ps
CPU time	4.79 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:54:46 PM PDT 24
Peak memory	203456 kb
Host	smart-be5c01ea-de17-48b4-9bf3-9eb45082460f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=541221183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.541221183
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2258775302
Short name	T40
Test name
Test status
Simulation time	9764803377 ps
CPU time	28.35 seconds
Started	Apr 02 12:54:44 PM PDT 24
Finished	Apr 02 12:55:12 PM PDT 24
Peak memory	203548 kb
Host	smart-85610c03-947d-44a2-ae51-5e142d273cf7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258775302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2258775302
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1812995684
Short name	T480
Test name
Test status
Simulation time	4837909996 ps
CPU time	44.7 seconds
Started	Apr 02 12:54:41 PM PDT 24
Finished	Apr 02 12:55:26 PM PDT 24
Peak memory	203552 kb
Host	smart-460d099f-80ee-4020-9193-ad3001269847
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1812995684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1812995684
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3767663590
Short name	T456
Test name
Test status
Simulation time	33689402 ps
CPU time	1.88 seconds
Started	Apr 02 12:54:47 PM PDT 24
Finished	Apr 02 12:54:49 PM PDT 24
Peak memory	203496 kb
Host	smart-1bf6fec0-ea00-4922-8bad-d7965289c87c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767663590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3767663590
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.492043640
Short name	T859
Test name
Test status
Simulation time	19517165901 ps
CPU time	192.96 seconds
Started	Apr 02 12:54:44 PM PDT 24
Finished	Apr 02 12:57:57 PM PDT 24
Peak memory	209572 kb
Host	smart-ee635e97-b4dc-4745-b3aa-6cfae0d4c5e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=492043640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.492043640
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1380706476
Short name	T843
Test name
Test status
Simulation time	2487375304 ps
CPU time	78.17 seconds
Started	Apr 02 12:54:45 PM PDT 24
Finished	Apr 02 12:56:03 PM PDT 24
Peak memory	205344 kb
Host	smart-6bf990a8-770d-426b-aaba-dbc58d1ce403
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1380706476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1380706476
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1045376836
Short name	T834
Test name
Test status
Simulation time	985314161 ps
CPU time	101.18 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:56:27 PM PDT 24
Peak memory	208508 kb
Host	smart-55a9844f-6a5f-4dfa-9dca-29dc8f3661e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1045376836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1045376836
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1492064359
Short name	T768
Test name
Test status
Simulation time	925279770 ps
CPU time	93.46 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:56:19 PM PDT 24
Peak memory	207792 kb
Host	smart-fec85ff3-d3df-4fca-b545-950bc59ef757
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492064359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.1492064359
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3735124604
Short name	T261
Test name
Test status
Simulation time	572339431 ps
CPU time	16.53 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:55:02 PM PDT 24
Peak memory	205100 kb
Host	smart-f9e38cac-c150-4433-8fba-203e1291f8cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3735124604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3735124604
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3564788022
Short name	T792
Test name
Test status
Simulation time	140457215 ps
CPU time	9.75 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:55:03 PM PDT 24
Peak memory	204204 kb
Host	smart-1132c156-37f5-47d5-b2f3-0c933c8a3a2d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3564788022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3564788022
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.960395856
Short name	T166
Test name
Test status
Simulation time	482186801 ps
CPU time	16.26 seconds
Started	Apr 02 12:54:50 PM PDT 24
Finished	Apr 02 12:55:06 PM PDT 24
Peak memory	203968 kb
Host	smart-16a0afcd-1aa1-4554-af27-94f5fc9a4c9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960395856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.960395856
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.1760980588
Short name	T206
Test name
Test status
Simulation time	183575755 ps
CPU time	21.01 seconds
Started	Apr 02 12:54:52 PM PDT 24
Finished	Apr 02 12:55:13 PM PDT 24
Peak memory	203600 kb
Host	smart-6c593df4-b4bd-4a23-ba83-97b91594a993
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1760980588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1760980588
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.1491839239
Short name	T195
Test name
Test status
Simulation time	763428530 ps
CPU time	27.87 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:55:14 PM PDT 24
Peak memory	204620 kb
Host	smart-50b97ccb-1e2c-4e6f-b38c-d5a17b3b0763
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1491839239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1491839239
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.85409941
Short name	T460
Test name
Test status
Simulation time	41473395433 ps
CPU time	173.4 seconds
Started	Apr 02 12:54:49 PM PDT 24
Finished	Apr 02 12:57:42 PM PDT 24
Peak memory	205048 kb
Host	smart-549c27cc-fc65-4f8f-ae9a-5ba510b158cd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=85409941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.85409941
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3145118031
Short name	T778
Test name
Test status
Simulation time	11261809723 ps
CPU time	106.77 seconds
Started	Apr 02 12:54:48 PM PDT 24
Finished	Apr 02 12:56:35 PM PDT 24
Peak memory	204812 kb
Host	smart-ead3b023-4912-465d-a334-6d53f90c92c5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3145118031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3145118031
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3459715740
Short name	T465
Test name
Test status
Simulation time	52353889 ps
CPU time	5.22 seconds
Started	Apr 02 12:54:45 PM PDT 24
Finished	Apr 02 12:54:50 PM PDT 24
Peak memory	211676 kb
Host	smart-dd9b4f38-a534-4557-9fe5-21cd3889a5fc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459715740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3459715740
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.664499147
Short name	T283
Test name
Test status
Simulation time	440757921 ps
CPU time	15.51 seconds
Started	Apr 02 12:54:48 PM PDT 24
Finished	Apr 02 12:55:04 PM PDT 24
Peak memory	204100 kb
Host	smart-5db91c83-a28e-4ccb-8d96-57f5c2cb7898
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=664499147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.664499147
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.863928395
Short name	T349
Test name
Test status
Simulation time	216276344 ps
CPU time	3.85 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:54:50 PM PDT 24
Peak memory	203488 kb
Host	smart-c68657d0-4658-4e05-bdf2-ffe16c7bd08b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863928395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.863928395
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3683898418
Short name	T81
Test name
Test status
Simulation time	4979798508 ps
CPU time	30.52 seconds
Started	Apr 02 12:54:44 PM PDT 24
Finished	Apr 02 12:55:15 PM PDT 24
Peak memory	203576 kb
Host	smart-a8cfe580-a338-44a5-8b01-86d7001e25e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683898418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3683898418
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2931859205
Short name	T783
Test name
Test status
Simulation time	16815699124 ps
CPU time	36.93 seconds
Started	Apr 02 12:54:46 PM PDT 24
Finished	Apr 02 12:55:23 PM PDT 24
Peak memory	203544 kb
Host	smart-dd127f87-17dc-46cd-934c-3da25cf5be21
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2931859205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2931859205
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3957358739
Short name	T613
Test name
Test status
Simulation time	28403105 ps
CPU time	2 seconds
Started	Apr 02 12:54:47 PM PDT 24
Finished	Apr 02 12:54:49 PM PDT 24
Peak memory	203420 kb
Host	smart-a0d94452-0dd1-4773-98c8-aa6b44b9bd64
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957358739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3957358739
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.1874098358
Short name	T127
Test name
Test status
Simulation time	442471486 ps
CPU time	12.2 seconds
Started	Apr 02 12:54:50 PM PDT 24
Finished	Apr 02 12:55:02 PM PDT 24
Peak memory	211688 kb
Host	smart-a46f4ad5-d3bd-4bd2-90f8-84151cd8864d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1874098358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1874098358
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1412998904
Short name	T753
Test name
Test status
Simulation time	3086556988 ps
CPU time	93.05 seconds
Started	Apr 02 12:54:50 PM PDT 24
Finished	Apr 02 12:56:23 PM PDT 24
Peak memory	206712 kb
Host	smart-df0fd0ac-eb99-40dd-b4b8-c72bd666d79c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1412998904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1412998904
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3043057064
Short name	T776
Test name
Test status
Simulation time	279146520 ps
CPU time	100.98 seconds
Started	Apr 02 12:55:00 PM PDT 24
Finished	Apr 02 12:56:42 PM PDT 24
Peak memory	207388 kb
Host	smart-4100c933-15c0-43f3-8465-e05b114920d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3043057064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3043057064
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3328600981
Short name	T739
Test name
Test status
Simulation time	3193433866 ps
CPU time	447.33 seconds
Started	Apr 02 12:54:51 PM PDT 24
Finished	Apr 02 01:02:19 PM PDT 24
Peak memory	220084 kb
Host	smart-3d23b65a-96c6-491c-9a3b-eaf95e2447ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3328600981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.3328600981
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3502843831
Short name	T758
Test name
Test status
Simulation time	50094840 ps
CPU time	6.44 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:55:00 PM PDT 24
Peak memory	204868 kb
Host	smart-77ef3ebe-53b5-498d-b3a2-a2a01aa653db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3502843831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3502843831
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2957967037
Short name	T600
Test name
Test status
Simulation time	2670754009 ps
CPU time	66.96 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:53:30 PM PDT 24
Peak memory	206732 kb
Host	smart-b4421066-bb30-47d6-823d-47c677470eb0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2957967037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2957967037
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2893323654
Short name	T851
Test name
Test status
Simulation time	75423539 ps
CPU time	2.52 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:26 PM PDT 24
Peak memory	203500 kb
Host	smart-30ff0d8e-13ab-4add-904d-628b97e4d864
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2893323654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2893323654
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.3139034854
Short name	T618
Test name
Test status
Simulation time	61431315 ps
CPU time	5.3 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:52:25 PM PDT 24
Peak memory	203520 kb
Host	smart-94ed20c7-0ffa-4edd-80f4-7eaca992469a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3139034854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3139034854
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.1568261105
Short name	T501
Test name
Test status
Simulation time	2536779833 ps
CPU time	42.56 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:53:03 PM PDT 24
Peak memory	205284 kb
Host	smart-349aded0-8d51-4a58-abe6-a92658c9eb33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1568261105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1568261105
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1670843910
Short name	T503
Test name
Test status
Simulation time	151175105607 ps
CPU time	251.19 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:56:32 PM PDT 24
Peak memory	205432 kb
Host	smart-0679f318-6527-470a-98bd-4c08b4fc8679
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670843910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1670843910
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3826976247
Short name	T420
Test name
Test status
Simulation time	46576882678 ps
CPU time	190.5 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:55:30 PM PDT 24
Peak memory	205240 kb
Host	smart-dd39574c-5cd8-42fa-9884-f21e085acf38
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3826976247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3826976247
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1657775642
Short name	T668
Test name
Test status
Simulation time	208902249 ps
CPU time	18.23 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:52:38 PM PDT 24
Peak memory	211708 kb
Host	smart-73952cfb-879f-4096-aefa-f579749bd38a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657775642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1657775642
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.934013616
Short name	T514
Test name
Test status
Simulation time	2007602347 ps
CPU time	8.46 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:32 PM PDT 24
Peak memory	203632 kb
Host	smart-ce61cb93-954a-46ac-81ab-1b58b40c987f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=934013616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.934013616
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.984511727
Short name	T664
Test name
Test status
Simulation time	57495699 ps
CPU time	2.29 seconds
Started	Apr 02 12:52:21 PM PDT 24
Finished	Apr 02 12:52:24 PM PDT 24
Peak memory	203488 kb
Host	smart-8d15537f-50cd-432d-937c-a9dfb284659f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=984511727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.984511727
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.339829609
Short name	T230
Test name
Test status
Simulation time	5207035364 ps
CPU time	27.92 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:52:48 PM PDT 24
Peak memory	203588 kb
Host	smart-0503c611-3b2b-4b65-a894-2abe33c75604
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=339829609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.339829609
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2975807546
Short name	T790
Test name
Test status
Simulation time	2764313363 ps
CPU time	26.43 seconds
Started	Apr 02 12:52:18 PM PDT 24
Finished	Apr 02 12:52:45 PM PDT 24
Peak memory	203572 kb
Host	smart-2369788b-5e00-47f0-a481-caea38c38974
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2975807546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2975807546
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.4201659699
Short name	T351
Test name
Test status
Simulation time	42960172 ps
CPU time	1.81 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:26 PM PDT 24
Peak memory	203280 kb
Host	smart-9c0f351a-7b09-4ab4-a452-1baee2ed04b6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201659699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.4201659699
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.1446387011
Short name	T526
Test name
Test status
Simulation time	2632885963 ps
CPU time	89.8 seconds
Started	Apr 02 12:52:21 PM PDT 24
Finished	Apr 02 12:53:51 PM PDT 24
Peak memory	208320 kb
Host	smart-7cbb9016-aad5-4315-b4fe-d6693026e1be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446387011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1446387011
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.924804880
Short name	T818
Test name
Test status
Simulation time	2149862675 ps
CPU time	70.12 seconds
Started	Apr 02 12:52:19 PM PDT 24
Finished	Apr 02 12:53:30 PM PDT 24
Peak memory	205008 kb
Host	smart-16f850e7-a18f-472f-bb6b-c0e6892b3b4c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=924804880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.924804880
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.86130478
Short name	T165
Test name
Test status
Simulation time	2620613705 ps
CPU time	324.08 seconds
Started	Apr 02 12:52:21 PM PDT 24
Finished	Apr 02 12:57:46 PM PDT 24
Peak memory	221388 kb
Host	smart-46d83b0b-4240-4db3-b8a4-670cd55bd52f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=86130478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_r eset.86130478
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.299595218
Short name	T35
Test name
Test status
Simulation time	697583762 ps
CPU time	151.01 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:54:55 PM PDT 24
Peak memory	210916 kb
Host	smart-88e2e07d-6b0b-4480-8e6c-d47eeb7a4aff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=299595218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.299595218
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.428507858
Short name	T175
Test name
Test status
Simulation time	657805183 ps
CPU time	8.74 seconds
Started	Apr 02 12:52:22 PM PDT 24
Finished	Apr 02 12:52:31 PM PDT 24
Peak memory	204868 kb
Host	smart-8e11dd75-453f-44f0-be70-c31e77d1554e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=428507858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.428507858
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.600776541
Short name	T345
Test name
Test status
Simulation time	401890656 ps
CPU time	36.53 seconds
Started	Apr 02 12:54:52 PM PDT 24
Finished	Apr 02 12:55:28 PM PDT 24
Peak memory	211656 kb
Host	smart-ed26b811-72d9-4640-8b2a-7fb9352785f8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=600776541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.600776541
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2814773131
Short name	T384
Test name
Test status
Simulation time	24285664551 ps
CPU time	194.27 seconds
Started	Apr 02 12:54:57 PM PDT 24
Finished	Apr 02 12:58:12 PM PDT 24
Peak memory	211740 kb
Host	smart-818f5195-28af-4ff5-9053-b0e327a195ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2814773131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.2814773131
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3599679139
Short name	T385
Test name
Test status
Simulation time	1521598204 ps
CPU time	27.49 seconds
Started	Apr 02 12:54:54 PM PDT 24
Finished	Apr 02 12:55:21 PM PDT 24
Peak memory	204072 kb
Host	smart-b29466f1-8f36-4bac-8ab4-ad7554dbc5d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3599679139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3599679139
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.2949111085
Short name	T423
Test name
Test status
Simulation time	1141128787 ps
CPU time	21.02 seconds
Started	Apr 02 12:54:54 PM PDT 24
Finished	Apr 02 12:55:16 PM PDT 24
Peak memory	203520 kb
Host	smart-54f24dbe-6034-4d11-ac33-4246f82d4017
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2949111085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2949111085
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.629526503
Short name	T611
Test name
Test status
Simulation time	210059509 ps
CPU time	23.49 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:55:17 PM PDT 24
Peak memory	205000 kb
Host	smart-7ce08fc9-7243-4114-84b8-68df7028dc8d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=629526503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.629526503
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1895714850
Short name	T45
Test name
Test status
Simulation time	27315133587 ps
CPU time	99.79 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:56:33 PM PDT 24
Peak memory	204868 kb
Host	smart-c799be25-5b0e-45be-adb1-61a31de36dbe
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895714850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1895714850
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2521976892
Short name	T862
Test name
Test status
Simulation time	1555654684 ps
CPU time	15.14 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:55:08 PM PDT 24
Peak memory	203524 kb
Host	smart-6f724ac0-88f2-4f64-995c-5e161beef104
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2521976892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2521976892
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.750694129
Short name	T324
Test name
Test status
Simulation time	187964673 ps
CPU time	21.84 seconds
Started	Apr 02 12:54:54 PM PDT 24
Finished	Apr 02 12:55:16 PM PDT 24
Peak memory	205000 kb
Host	smart-e6378d0c-6a65-4f97-ba78-fefbe723b819
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750694129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.750694129
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.2970281575
Short name	T644
Test name
Test status
Simulation time	2048810381 ps
CPU time	16.81 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:55:10 PM PDT 24
Peak memory	204084 kb
Host	smart-9ab5777e-c9e3-43af-96d7-8f108ffe4b88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970281575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2970281575
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.2847619761
Short name	T120
Test name
Test status
Simulation time	98129906 ps
CPU time	2.3 seconds
Started	Apr 02 12:54:47 PM PDT 24
Finished	Apr 02 12:54:50 PM PDT 24
Peak memory	203484 kb
Host	smart-f0cb0c28-83a4-4129-b33b-10dc223945f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2847619761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2847619761
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.331778709
Short name	T876
Test name
Test status
Simulation time	13294647760 ps
CPU time	27.01 seconds
Started	Apr 02 12:54:51 PM PDT 24
Finished	Apr 02 12:55:18 PM PDT 24
Peak memory	203572 kb
Host	smart-141e1d7b-4d55-4b38-a399-9bf17f33505c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=331778709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.331778709
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.21973767
Short name	T675
Test name
Test status
Simulation time	5130767168 ps
CPU time	37.52 seconds
Started	Apr 02 12:54:49 PM PDT 24
Finished	Apr 02 12:55:27 PM PDT 24
Peak memory	203504 kb
Host	smart-5306b0bc-49de-4740-90ba-287b22a287dc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=21973767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.21973767
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2171937506
Short name	T42
Test name
Test status
Simulation time	32109836 ps
CPU time	2.55 seconds
Started	Apr 02 12:54:50 PM PDT 24
Finished	Apr 02 12:54:53 PM PDT 24
Peak memory	203444 kb
Host	smart-12b43c8d-2d88-4540-a75b-0573fdd04c85
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171937506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2171937506
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.1102327396
Short name	T481
Test name
Test status
Simulation time	271484688 ps
CPU time	16.79 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:55:10 PM PDT 24
Peak memory	205372 kb
Host	smart-17746d3a-e12b-4d42-8e79-0ab9b67c02e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102327396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1102327396
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.4194404633
Short name	T718
Test name
Test status
Simulation time	1805257059 ps
CPU time	111.94 seconds
Started	Apr 02 12:54:53 PM PDT 24
Finished	Apr 02 12:56:45 PM PDT 24
Peak memory	208288 kb
Host	smart-1b4c9ffe-01a4-40eb-a3bf-d8731ad3a168
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4194404633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4194404633
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2964559557
Short name	T69
Test name
Test status
Simulation time	6652517542 ps
CPU time	300.94 seconds
Started	Apr 02 12:54:55 PM PDT 24
Finished	Apr 02 12:59:56 PM PDT 24
Peak memory	208400 kb
Host	smart-90adbad8-88d3-4a40-9cf5-3666639d079e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964559557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2964559557
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3459443850
Short name	T122
Test name
Test status
Simulation time	1054923862 ps
CPU time	255.83 seconds
Started	Apr 02 12:54:52 PM PDT 24
Finished	Apr 02 12:59:09 PM PDT 24
Peak memory	219908 kb
Host	smart-9aad987b-d7f2-4a7a-a4f3-fd5c8ebdc2df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3459443850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3459443850
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.619843202
Short name	T387
Test name
Test status
Simulation time	678824531 ps
CPU time	19.84 seconds
Started	Apr 02 12:54:54 PM PDT 24
Finished	Apr 02 12:55:14 PM PDT 24
Peak memory	204912 kb
Host	smart-70844740-47ab-4b1e-8221-16a7513f9348
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=619843202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.619843202
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1773723790
Short name	T339
Test name
Test status
Simulation time	243126078 ps
CPU time	28.64 seconds
Started	Apr 02 12:54:57 PM PDT 24
Finished	Apr 02 12:55:26 PM PDT 24
Peak memory	204788 kb
Host	smart-e241a0f5-3e17-49fb-9ed8-a05e266ba58d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773723790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1773723790
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.279189431
Short name	T177
Test name
Test status
Simulation time	27696238779 ps
CPU time	251.16 seconds
Started	Apr 02 12:54:56 PM PDT 24
Finished	Apr 02 12:59:08 PM PDT 24
Peak memory	211652 kb
Host	smart-45a4eaf4-f182-4f78-a246-cea481cd564c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=279189431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo w_rsp.279189431
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2895533673
Short name	T314
Test name
Test status
Simulation time	142735586 ps
CPU time	10.65 seconds
Started	Apr 02 12:55:00 PM PDT 24
Finished	Apr 02 12:55:12 PM PDT 24
Peak memory	203516 kb
Host	smart-222e5be3-2f57-4617-9c2d-bd226f54d8b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2895533673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2895533673
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.3491166904
Short name	T670
Test name
Test status
Simulation time	75760064 ps
CPU time	2.87 seconds
Started	Apr 02 12:54:55 PM PDT 24
Finished	Apr 02 12:54:58 PM PDT 24
Peak memory	203412 kb
Host	smart-ea972a46-1075-4fb4-94d0-d64226421528
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3491166904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3491166904
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.225880117
Short name	T104
Test name
Test status
Simulation time	200573459 ps
CPU time	19.11 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 12:55:17 PM PDT 24
Peak memory	204840 kb
Host	smart-a91facf9-0362-4330-a797-4ad5b0a88c67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=225880117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.225880117
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.4112850918
Short name	T744
Test name
Test status
Simulation time	11987219076 ps
CPU time	77.81 seconds
Started	Apr 02 12:54:56 PM PDT 24
Finished	Apr 02 12:56:13 PM PDT 24
Peak memory	211668 kb
Host	smart-877f93c3-42ab-49ee-b20d-8505a7ef56e5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112850918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.4112850918
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.666614863
Short name	T434
Test name
Test status
Simulation time	23306209231 ps
CPU time	135.64 seconds
Started	Apr 02 12:54:57 PM PDT 24
Finished	Apr 02 12:57:13 PM PDT 24
Peak memory	204856 kb
Host	smart-ed9eaf36-7d5a-4a08-95b2-a6cdf184a2a9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=666614863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.666614863
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2376030454
Short name	T867
Test name
Test status
Simulation time	895317745 ps
CPU time	20.9 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 12:55:19 PM PDT 24
Peak memory	205032 kb
Host	smart-f3472e6d-dd30-4ee4-aad0-199fe06cc528
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376030454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2376030454
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.1368645930
Short name	T532
Test name
Test status
Simulation time	337913193 ps
CPU time	20.83 seconds
Started	Apr 02 12:54:57 PM PDT 24
Finished	Apr 02 12:55:18 PM PDT 24
Peak memory	203584 kb
Host	smart-5b9348e0-e884-4317-80ad-5621bedeae0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1368645930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1368645930
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.3666712265
Short name	T369
Test name
Test status
Simulation time	357446631 ps
CPU time	3.53 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 12:55:02 PM PDT 24
Peak memory	203420 kb
Host	smart-0dc07cad-74e9-4eef-b92f-36ff738e0266
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3666712265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3666712265
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3375159367
Short name	T590
Test name
Test status
Simulation time	8874673966 ps
CPU time	32.98 seconds
Started	Apr 02 12:54:59 PM PDT 24
Finished	Apr 02 12:55:33 PM PDT 24
Peak memory	203544 kb
Host	smart-f891ac95-758a-4ee7-a23f-cf9c0e2828fe
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375159367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3375159367
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2620301686
Short name	T604
Test name
Test status
Simulation time	6550617780 ps
CPU time	34.21 seconds
Started	Apr 02 12:54:56 PM PDT 24
Finished	Apr 02 12:55:31 PM PDT 24
Peak memory	203564 kb
Host	smart-cdf1d2f1-0a99-454f-9f01-e5ad883b2019
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2620301686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2620301686
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1736165506
Short name	T448
Test name
Test status
Simulation time	40015115 ps
CPU time	2.62 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 12:55:01 PM PDT 24
Peak memory	203508 kb
Host	smart-c35c5f8b-b221-43ce-bcc8-d8104aa08f9c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736165506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1736165506
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.2747979295
Short name	T678
Test name
Test status
Simulation time	29036140575 ps
CPU time	304.53 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 01:00:02 PM PDT 24
Peak memory	207500 kb
Host	smart-9436f17f-dd7e-456e-98e4-2e339f09ba21
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2747979295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2747979295
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2657556403
Short name	T540
Test name
Test status
Simulation time	3742292461 ps
CPU time	75.85 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 12:56:14 PM PDT 24
Peak memory	205212 kb
Host	smart-7035d863-b192-4f3c-a57d-310484eac243
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657556403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2657556403
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2856874900
Short name	T151
Test name
Test status
Simulation time	13549091606 ps
CPU time	476.14 seconds
Started	Apr 02 12:54:56 PM PDT 24
Finished	Apr 02 01:02:53 PM PDT 24
Peak memory	210048 kb
Host	smart-68328bd8-6d17-4118-b7cc-6f5af3ead616
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2856874900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.2856874900
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1095717580
Short name	T865
Test name
Test status
Simulation time	1374703931 ps
CPU time	171.8 seconds
Started	Apr 02 12:54:57 PM PDT 24
Finished	Apr 02 12:57:49 PM PDT 24
Peak memory	210780 kb
Host	smart-1ff4cd5d-a902-461c-a7a8-229191afe689
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1095717580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.1095717580
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1104264590
Short name	T18
Test name
Test status
Simulation time	163817431 ps
CPU time	11.8 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 12:55:10 PM PDT 24
Peak memory	211684 kb
Host	smart-1d3779cc-d203-4805-961e-0b3789750dfa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1104264590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1104264590
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.386048893
Short name	T365
Test name
Test status
Simulation time	605272554 ps
CPU time	19.01 seconds
Started	Apr 02 12:55:00 PM PDT 24
Finished	Apr 02 12:55:20 PM PDT 24
Peak memory	204492 kb
Host	smart-ae1a7b6e-1f29-4fc6-9e78-842df60638d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=386048893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.386048893
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3421991225
Short name	T893
Test name
Test status
Simulation time	41586273666 ps
CPU time	284.95 seconds
Started	Apr 02 12:55:01 PM PDT 24
Finished	Apr 02 12:59:47 PM PDT 24
Peak memory	211764 kb
Host	smart-d1b192bc-971f-470c-b68a-5558315f7921
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3421991225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.3421991225
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3437085168
Short name	T679
Test name
Test status
Simulation time	126924125 ps
CPU time	17.31 seconds
Started	Apr 02 12:55:02 PM PDT 24
Finished	Apr 02 12:55:20 PM PDT 24
Peak memory	203832 kb
Host	smart-00cef636-3d57-47d2-b7a7-fc9e14188748
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437085168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3437085168
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.2215061737
Short name	T347
Test name
Test status
Simulation time	250579975 ps
CPU time	11.07 seconds
Started	Apr 02 12:55:00 PM PDT 24
Finished	Apr 02 12:55:11 PM PDT 24
Peak memory	203528 kb
Host	smart-9051045d-7205-4e8a-b811-9750aeeb7029
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2215061737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2215061737
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.2697919589
Short name	T886
Test name
Test status
Simulation time	945528403 ps
CPU time	21.99 seconds
Started	Apr 02 12:55:01 PM PDT 24
Finished	Apr 02 12:55:24 PM PDT 24
Peak memory	211688 kb
Host	smart-4a5dc152-3c60-400e-8cef-b5fcc1a9ebff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2697919589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2697919589
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2874838404
Short name	T399
Test name
Test status
Simulation time	16116547862 ps
CPU time	80.04 seconds
Started	Apr 02 12:55:01 PM PDT 24
Finished	Apr 02 12:56:22 PM PDT 24
Peak memory	211688 kb
Host	smart-0be67198-5379-4e2c-aa9c-ba8bb34d51ee
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874838404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2874838404
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1458638492
Short name	T555
Test name
Test status
Simulation time	73907535753 ps
CPU time	269.71 seconds
Started	Apr 02 12:55:01 PM PDT 24
Finished	Apr 02 12:59:32 PM PDT 24
Peak memory	205096 kb
Host	smart-fe7e60cb-04c9-4edf-8aef-5d01f59b5ad6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1458638492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1458638492
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2917061408
Short name	T44
Test name
Test status
Simulation time	71684116 ps
CPU time	11.51 seconds
Started	Apr 02 12:55:02 PM PDT 24
Finished	Apr 02 12:55:15 PM PDT 24
Peak memory	204604 kb
Host	smart-23458938-13f2-4b37-a804-37df4d58c36f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917061408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2917061408
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.2213100501
Short name	T64
Test name
Test status
Simulation time	2133957983 ps
CPU time	32.98 seconds
Started	Apr 02 12:54:59 PM PDT 24
Finished	Apr 02 12:55:32 PM PDT 24
Peak memory	204004 kb
Host	smart-d17b58c9-0b20-42ef-8a66-f25899aec739
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2213100501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2213100501
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.3356590849
Short name	T37
Test name
Test status
Simulation time	41436785 ps
CPU time	2.32 seconds
Started	Apr 02 12:54:56 PM PDT 24
Finished	Apr 02 12:54:58 PM PDT 24
Peak memory	203464 kb
Host	smart-31a7feed-540c-422a-8e8c-b6ec0b2d9e4b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3356590849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3356590849
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3567183639
Short name	T344
Test name
Test status
Simulation time	9604932661 ps
CPU time	30.85 seconds
Started	Apr 02 12:54:58 PM PDT 24
Finished	Apr 02 12:55:29 PM PDT 24
Peak memory	203500 kb
Host	smart-8182de30-de91-489a-9ba5-90d4e918cfcb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567183639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3567183639
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3321927628
Short name	T748
Test name
Test status
Simulation time	10163430731 ps
CPU time	33.95 seconds
Started	Apr 02 12:55:00 PM PDT 24
Finished	Apr 02 12:55:34 PM PDT 24
Peak memory	203500 kb
Host	smart-7ae4f4e7-92c6-46f6-a2f5-4504668f25fe
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3321927628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3321927628
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3519940839
Short name	T304
Test name
Test status
Simulation time	58932801 ps
CPU time	2.42 seconds
Started	Apr 02 12:54:59 PM PDT 24
Finished	Apr 02 12:55:02 PM PDT 24
Peak memory	203504 kb
Host	smart-170b5b49-9bde-4dd1-9315-87c04e7a7446
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519940839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3519940839
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.2233293892
Short name	T160
Test name
Test status
Simulation time	5593820539 ps
CPU time	55.2 seconds
Started	Apr 02 12:55:01 PM PDT 24
Finished	Apr 02 12:55:57 PM PDT 24
Peak memory	207304 kb
Host	smart-c6913cc7-77f2-4519-be98-2b67a4a2782e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2233293892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2233293892
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.941237885
Short name	T516
Test name
Test status
Simulation time	313927206 ps
CPU time	31.62 seconds
Started	Apr 02 12:55:02 PM PDT 24
Finished	Apr 02 12:55:35 PM PDT 24
Peak memory	204892 kb
Host	smart-ba08e101-23f8-42c1-9265-32c2d35506ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=941237885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.941237885
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1341169204
Short name	T182
Test name
Test status
Simulation time	2418528021 ps
CPU time	193.17 seconds
Started	Apr 02 12:55:02 PM PDT 24
Finished	Apr 02 12:58:16 PM PDT 24
Peak memory	209136 kb
Host	smart-4710a8d9-420b-43fd-b59c-4c32b279a795
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1341169204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1341169204
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3945616969
Short name	T608
Test name
Test status
Simulation time	6019576955 ps
CPU time	351.91 seconds
Started	Apr 02 12:55:01 PM PDT 24
Finished	Apr 02 01:00:54 PM PDT 24
Peak memory	219920 kb
Host	smart-2bf0f051-1737-4b33-8d5c-402683758a0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3945616969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3945616969
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2529739166
Short name	T735
Test name
Test status
Simulation time	327663321 ps
CPU time	11.27 seconds
Started	Apr 02 12:55:02 PM PDT 24
Finished	Apr 02 12:55:14 PM PDT 24
Peak memory	205184 kb
Host	smart-2a813a74-3113-4d34-a9cb-7bcafef32584
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2529739166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2529739166
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.4044926760
Short name	T463
Test name
Test status
Simulation time	899966676 ps
CPU time	28.87 seconds
Started	Apr 02 12:55:05 PM PDT 24
Finished	Apr 02 12:55:35 PM PDT 24
Peak memory	211624 kb
Host	smart-85e5be76-0000-468b-9c1b-4de237979510
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4044926760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4044926760
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1589412944
Short name	T72
Test name
Test status
Simulation time	39776625370 ps
CPU time	188.13 seconds
Started	Apr 02 12:55:04 PM PDT 24
Finished	Apr 02 12:58:13 PM PDT 24
Peak memory	206464 kb
Host	smart-eed0d98a-8e13-400c-ae08-0f9b209959c7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1589412944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1589412944
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3197267421
Short name	T485
Test name
Test status
Simulation time	373424152 ps
CPU time	9.74 seconds
Started	Apr 02 12:55:04 PM PDT 24
Finished	Apr 02 12:55:14 PM PDT 24
Peak memory	203776 kb
Host	smart-c2954b9d-8f80-48cf-8457-5448c29cd83e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3197267421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3197267421
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.3631334407
Short name	T396
Test name
Test status
Simulation time	888874833 ps
CPU time	16.82 seconds
Started	Apr 02 12:55:04 PM PDT 24
Finished	Apr 02 12:55:21 PM PDT 24
Peak memory	203500 kb
Host	smart-ddc4fa72-d17f-43c8-8fe6-02b6916f4798
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3631334407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3631334407
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.1252378152
Short name	T632
Test name
Test status
Simulation time	431243063 ps
CPU time	14.26 seconds
Started	Apr 02 12:55:04 PM PDT 24
Finished	Apr 02 12:55:20 PM PDT 24
Peak memory	204600 kb
Host	smart-fcb78022-7e09-4f4b-a370-a880d5878bf4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1252378152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1252378152
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2376229206
Short name	T643
Test name
Test status
Simulation time	38625727139 ps
CPU time	249.22 seconds
Started	Apr 02 12:55:03 PM PDT 24
Finished	Apr 02 12:59:13 PM PDT 24
Peak memory	204624 kb
Host	smart-a23fcd1c-8432-4bd5-b468-d63b15004e1b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376229206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2376229206
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4248952195
Short name	T667
Test name
Test status
Simulation time	135119473886 ps
CPU time	297.91 seconds
Started	Apr 02 12:55:03 PM PDT 24
Finished	Apr 02 01:00:02 PM PDT 24
Peak memory	204724 kb
Host	smart-bad10563-5d05-4050-a97e-d5cd11cdd3e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4248952195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4248952195
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.4075862415
Short name	T337
Test name
Test status
Simulation time	297267097 ps
CPU time	19.26 seconds
Started	Apr 02 12:55:02 PM PDT 24
Finished	Apr 02 12:55:22 PM PDT 24
Peak memory	204840 kb
Host	smart-4b5b4f44-538e-44f0-828b-477380d92a42
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075862415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.4075862415
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.626240280
Short name	T518
Test name
Test status
Simulation time	707326351 ps
CPU time	13.96 seconds
Started	Apr 02 12:55:05 PM PDT 24
Finished	Apr 02 12:55:20 PM PDT 24
Peak memory	204108 kb
Host	smart-2eb5c941-8cb0-4b24-8c6b-25e6a6e9aab5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626240280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.626240280
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.1984143010
Short name	T515
Test name
Test status
Simulation time	30026183 ps
CPU time	2.35 seconds
Started	Apr 02 12:54:59 PM PDT 24
Finished	Apr 02 12:55:01 PM PDT 24
Peak memory	203464 kb
Host	smart-7904a04d-6e21-451d-9498-cb1a99c61fa3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1984143010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1984143010
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2478630785
Short name	T413
Test name
Test status
Simulation time	6117759355 ps
CPU time	36.64 seconds
Started	Apr 02 12:55:04 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	203540 kb
Host	smart-11864cbb-a69c-4e18-afeb-229e317d3e47
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478630785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2478630785
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3448194651
Short name	T511
Test name
Test status
Simulation time	4500009999 ps
CPU time	30.9 seconds
Started	Apr 02 12:55:07 PM PDT 24
Finished	Apr 02 12:55:38 PM PDT 24
Peak memory	203508 kb
Host	smart-805dcc3f-a51f-455d-a193-e74f66f1b733
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3448194651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3448194651
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1215387249
Short name	T707
Test name
Test status
Simulation time	33644427 ps
CPU time	2.33 seconds
Started	Apr 02 12:55:01 PM PDT 24
Finished	Apr 02 12:55:04 PM PDT 24
Peak memory	203504 kb
Host	smart-3aef3b7c-8f2d-4370-8bc0-1539b44a2e6d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215387249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1215387249
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3631352954
Short name	T558
Test name
Test status
Simulation time	7822129662 ps
CPU time	151.87 seconds
Started	Apr 02 12:55:07 PM PDT 24
Finished	Apr 02 12:57:39 PM PDT 24
Peak memory	209224 kb
Host	smart-34352583-c606-43ce-98ba-8b3414d71ee1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3631352954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3631352954
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.286296423
Short name	T804
Test name
Test status
Simulation time	106635416 ps
CPU time	24.44 seconds
Started	Apr 02 12:55:08 PM PDT 24
Finished	Apr 02 12:55:32 PM PDT 24
Peak memory	205836 kb
Host	smart-182ecf0a-d350-4bb2-8e75-550ebf5d51e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=286296423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand _reset.286296423
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3442322681
Short name	T271
Test name
Test status
Simulation time	2665564426 ps
CPU time	323.18 seconds
Started	Apr 02 12:55:08 PM PDT 24
Finished	Apr 02 01:00:32 PM PDT 24
Peak memory	211208 kb
Host	smart-5ca37016-acee-4632-80fd-8ead3e9ffbc8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3442322681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3442322681
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3695828724
Short name	T854
Test name
Test status
Simulation time	73710018 ps
CPU time	4.69 seconds
Started	Apr 02 12:55:05 PM PDT 24
Finished	Apr 02 12:55:11 PM PDT 24
Peak memory	204880 kb
Host	smart-fae5fba7-3e4d-4c26-916a-683e69f2d7a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3695828724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3695828724
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3423525894
Short name	T364
Test name
Test status
Simulation time	994020765 ps
CPU time	46.03 seconds
Started	Apr 02 12:55:12 PM PDT 24
Finished	Apr 02 12:55:58 PM PDT 24
Peak memory	206260 kb
Host	smart-5d6ad819-d193-45e2-8bef-72410cc95726
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3423525894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3423525894
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.907197748
Short name	T116
Test name
Test status
Simulation time	32131218508 ps
CPU time	85.82 seconds
Started	Apr 02 12:55:12 PM PDT 24
Finished	Apr 02 12:56:38 PM PDT 24
Peak memory	204348 kb
Host	smart-8f634969-9c98-4291-9afe-fd24e2461158
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=907197748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo w_rsp.907197748
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2915547510
Short name	T649
Test name
Test status
Simulation time	142365258 ps
CPU time	14.53 seconds
Started	Apr 02 12:55:13 PM PDT 24
Finished	Apr 02 12:55:27 PM PDT 24
Peak memory	204072 kb
Host	smart-03472ea1-c65d-4f03-8331-5920f80f00af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2915547510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2915547510
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.1279536835
Short name	T661
Test name
Test status
Simulation time	157213069 ps
CPU time	15.86 seconds
Started	Apr 02 12:55:07 PM PDT 24
Finished	Apr 02 12:55:23 PM PDT 24
Peak memory	203484 kb
Host	smart-a857946b-92f1-4afe-8ac8-69d0b10590dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1279536835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1279536835
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.49973262
Short name	T663
Test name
Test status
Simulation time	1234968151 ps
CPU time	29.71 seconds
Started	Apr 02 12:55:09 PM PDT 24
Finished	Apr 02 12:55:39 PM PDT 24
Peak memory	204680 kb
Host	smart-6ae2ba7b-acbd-46ca-8898-9a92f6c49213
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=49973262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.49973262
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1233361703
Short name	T73
Test name
Test status
Simulation time	39640096487 ps
CPU time	187.88 seconds
Started	Apr 02 12:55:10 PM PDT 24
Finished	Apr 02 12:58:19 PM PDT 24
Peak memory	205496 kb
Host	smart-fce2365c-f2c0-407d-bc8b-9d64f4e27afd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233361703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1233361703
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1474354436
Short name	T614
Test name
Test status
Simulation time	7030969999 ps
CPU time	31.61 seconds
Started	Apr 02 12:55:09 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	204876 kb
Host	smart-b21f8951-6a0e-4008-9554-33a97d186b9f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1474354436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1474354436
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2761729331
Short name	T845
Test name
Test status
Simulation time	71305679 ps
CPU time	8.09 seconds
Started	Apr 02 12:55:10 PM PDT 24
Finished	Apr 02 12:55:18 PM PDT 24
Peak memory	211684 kb
Host	smart-30226dce-ae3d-43d1-a99e-8b1ed40c0d29
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761729331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2761729331
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.531522028
Short name	T530
Test name
Test status
Simulation time	3811892442 ps
CPU time	35.8 seconds
Started	Apr 02 12:55:12 PM PDT 24
Finished	Apr 02 12:55:48 PM PDT 24
Peak memory	204592 kb
Host	smart-a9017da8-2afb-499a-9bc4-199bd796f17f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=531522028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.531522028
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.3238349083
Short name	T637
Test name
Test status
Simulation time	238165548 ps
CPU time	3.75 seconds
Started	Apr 02 12:55:07 PM PDT 24
Finished	Apr 02 12:55:11 PM PDT 24
Peak memory	203472 kb
Host	smart-f83aefb9-c9f9-45e8-a306-886f4553ab78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3238349083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3238349083
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1777488343
Short name	T308
Test name
Test status
Simulation time	5330369420 ps
CPU time	30.86 seconds
Started	Apr 02 12:55:11 PM PDT 24
Finished	Apr 02 12:55:43 PM PDT 24
Peak memory	203552 kb
Host	smart-642376d8-f944-47d7-8c0b-e492b57423ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777488343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1777488343
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2359016458
Short name	T754
Test name
Test status
Simulation time	3626311241 ps
CPU time	29.46 seconds
Started	Apr 02 12:55:16 PM PDT 24
Finished	Apr 02 12:55:46 PM PDT 24
Peak memory	203564 kb
Host	smart-071129c4-f712-4d67-9c97-66bd107e51b6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2359016458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2359016458
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2244236548
Short name	T887
Test name
Test status
Simulation time	28500547 ps
CPU time	2.52 seconds
Started	Apr 02 12:55:07 PM PDT 24
Finished	Apr 02 12:55:10 PM PDT 24
Peak memory	203476 kb
Host	smart-d406425c-3788-4bf5-9b5e-a74a8a197b46
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244236548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2244236548
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3040424425
Short name	T288
Test name
Test status
Simulation time	4410637482 ps
CPU time	126.07 seconds
Started	Apr 02 12:55:12 PM PDT 24
Finished	Apr 02 12:57:18 PM PDT 24
Peak memory	210144 kb
Host	smart-c78aefca-07a1-4dc7-a015-e9d16a63d13a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3040424425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3040424425
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.269776466
Short name	T313
Test name
Test status
Simulation time	4357593409 ps
CPU time	219.84 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:58:55 PM PDT 24
Peak memory	211708 kb
Host	smart-753d4216-8c3a-4052-a842-3451e8bea4ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=269776466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.269776466
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3260759262
Short name	T221
Test name
Test status
Simulation time	1136777458 ps
CPU time	25.21 seconds
Started	Apr 02 12:55:16 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	211616 kb
Host	smart-c3b12b1d-49fd-4545-941b-876cb300029c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3260759262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3260759262
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2758692611
Short name	T676
Test name
Test status
Simulation time	235976654 ps
CPU time	17.08 seconds
Started	Apr 02 12:55:16 PM PDT 24
Finished	Apr 02 12:55:34 PM PDT 24
Peak memory	204480 kb
Host	smart-9b75a837-f7ec-4433-8c96-2acf1389c223
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758692611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2758692611
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.953486682
Short name	T55
Test name
Test status
Simulation time	175431061231 ps
CPU time	521.17 seconds
Started	Apr 02 12:55:17 PM PDT 24
Finished	Apr 02 01:03:59 PM PDT 24
Peak memory	211716 kb
Host	smart-8c6a0796-8ddd-4e37-8f1d-e7121b49fc9d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=953486682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.953486682
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4044824648
Short name	T764
Test name
Test status
Simulation time	162791939 ps
CPU time	19.54 seconds
Started	Apr 02 12:55:13 PM PDT 24
Finished	Apr 02 12:55:33 PM PDT 24
Peak memory	203444 kb
Host	smart-4c158021-2a7b-4440-8fa9-d6a7edd58c4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4044824648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4044824648
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.507685474
Short name	T691
Test name
Test status
Simulation time	212976759 ps
CPU time	13.7 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:29 PM PDT 24
Peak memory	203520 kb
Host	smart-a0eac42d-5599-49fb-81f1-dff98974c25c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=507685474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.507685474
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.797842258
Short name	T197
Test name
Test status
Simulation time	1003708567 ps
CPU time	33.53 seconds
Started	Apr 02 12:55:14 PM PDT 24
Finished	Apr 02 12:55:47 PM PDT 24
Peak memory	211688 kb
Host	smart-94866f11-3c1b-427d-8a42-625ce6665167
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=797842258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.797842258
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.966394742
Short name	T616
Test name
Test status
Simulation time	20697194032 ps
CPU time	42.47 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:58 PM PDT 24
Peak memory	211708 kb
Host	smart-ee86b577-8407-41d9-8cb9-631a07bc872e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=966394742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.966394742
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.4114798116
Short name	T257
Test name
Test status
Simulation time	34221372837 ps
CPU time	72.68 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:56:27 PM PDT 24
Peak memory	204600 kb
Host	smart-d993de6c-ac61-47e4-b8bf-c254e3ee6ae1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4114798116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.4114798116
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1186149159
Short name	T455
Test name
Test status
Simulation time	105704921 ps
CPU time	12.79 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:28 PM PDT 24
Peak memory	204764 kb
Host	smart-f4c53850-c152-497e-8c6b-099facebd3aa
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186149159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1186149159
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.1260451591
Short name	T798
Test name
Test status
Simulation time	334105230 ps
CPU time	21.99 seconds
Started	Apr 02 12:55:17 PM PDT 24
Finished	Apr 02 12:55:40 PM PDT 24
Peak memory	204472 kb
Host	smart-5f22331a-1150-4968-b28a-ae42b3fa346e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1260451591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1260451591
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.3058855474
Short name	T82
Test name
Test status
Simulation time	133240491 ps
CPU time	2.89 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:18 PM PDT 24
Peak memory	203496 kb
Host	smart-2cc95ee9-1bec-46f7-a259-10ca6dbce53f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3058855474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3058855474
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1897966387
Short name	T855
Test name
Test status
Simulation time	7600042467 ps
CPU time	24.83 seconds
Started	Apr 02 12:55:14 PM PDT 24
Finished	Apr 02 12:55:39 PM PDT 24
Peak memory	203556 kb
Host	smart-6c4c565e-64f4-491e-a314-5335f4716bbb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897966387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1897966387
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.4223204023
Short name	T482
Test name
Test status
Simulation time	3633358465 ps
CPU time	29.22 seconds
Started	Apr 02 12:55:14 PM PDT 24
Finished	Apr 02 12:55:44 PM PDT 24
Peak memory	203576 kb
Host	smart-7b623418-55b8-4eb2-ab9d-edc0db1d9be7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4223204023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4223204023
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2922473803
Short name	T134
Test name
Test status
Simulation time	40240654 ps
CPU time	2.47 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:17 PM PDT 24
Peak memory	203492 kb
Host	smart-38c8a17c-7d6a-4f25-829a-839dd02b434d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922473803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2922473803
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3673571293
Short name	T447
Test name
Test status
Simulation time	12945428903 ps
CPU time	128.65 seconds
Started	Apr 02 12:55:24 PM PDT 24
Finished	Apr 02 12:57:33 PM PDT 24
Peak memory	211740 kb
Host	smart-502ce142-5931-4df3-8c20-b0765f6dcdf1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3673571293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3673571293
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2295867252
Short name	T476
Test name
Test status
Simulation time	1735804680 ps
CPU time	31.6 seconds
Started	Apr 02 12:55:14 PM PDT 24
Finished	Apr 02 12:55:46 PM PDT 24
Peak memory	206836 kb
Host	smart-971be054-5769-465a-a2fd-da0d1df244a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2295867252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.2295867252
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3225595238
Short name	T772
Test name
Test status
Simulation time	3451334659 ps
CPU time	244.12 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:59:20 PM PDT 24
Peak memory	210960 kb
Host	smart-1e060954-8f16-486e-9158-32c8ba267d2c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3225595238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3225595238
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1447162164
Short name	T395
Test name
Test status
Simulation time	517608677 ps
CPU time	15.43 seconds
Started	Apr 02 12:55:16 PM PDT 24
Finished	Apr 02 12:55:32 PM PDT 24
Peak memory	211628 kb
Host	smart-aa8e4311-fdbd-45d8-b730-9641037c0474
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1447162164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1447162164
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1210424175
Short name	T579
Test name
Test status
Simulation time	1330091503 ps
CPU time	29.33 seconds
Started	Apr 02 12:55:22 PM PDT 24
Finished	Apr 02 12:55:52 PM PDT 24
Peak memory	206040 kb
Host	smart-86a71640-7b2d-480e-816a-b41f101b9dba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1210424175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1210424175
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1327666965
Short name	T842
Test name
Test status
Simulation time	185701251636 ps
CPU time	604.47 seconds
Started	Apr 02 12:55:19 PM PDT 24
Finished	Apr 02 01:05:25 PM PDT 24
Peak memory	211744 kb
Host	smart-a66506df-e949-4776-b767-d52f1f5252e5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1327666965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.1327666965
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.424466719
Short name	T312
Test name
Test status
Simulation time	1416414754 ps
CPU time	23.42 seconds
Started	Apr 02 12:55:18 PM PDT 24
Finished	Apr 02 12:55:42 PM PDT 24
Peak memory	203500 kb
Host	smart-1881b868-c5fc-46c0-bec7-feee75097842
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424466719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.424466719
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.1532388293
Short name	T334
Test name
Test status
Simulation time	747302136 ps
CPU time	29.08 seconds
Started	Apr 02 12:55:25 PM PDT 24
Finished	Apr 02 12:55:54 PM PDT 24
Peak memory	203668 kb
Host	smart-19470e86-eda3-4754-b835-f8b0c2c6b263
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1532388293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1532388293
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.143290310
Short name	T669
Test name
Test status
Simulation time	613377990 ps
CPU time	23.56 seconds
Started	Apr 02 12:55:17 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	204980 kb
Host	smart-d23d6683-e362-47db-8b0b-06f06b0f7238
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=143290310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.143290310
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.221619244
Short name	T92
Test name
Test status
Simulation time	22052036321 ps
CPU time	56.63 seconds
Started	Apr 02 12:55:17 PM PDT 24
Finished	Apr 02 12:56:14 PM PDT 24
Peak memory	205056 kb
Host	smart-9aef07c7-27a8-45ef-972d-add5d247a1a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=221619244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.221619244
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.844510384
Short name	T371
Test name
Test status
Simulation time	24566679564 ps
CPU time	178.07 seconds
Started	Apr 02 12:55:20 PM PDT 24
Finished	Apr 02 12:58:18 PM PDT 24
Peak memory	211680 kb
Host	smart-3bc792b5-6de0-4071-82ba-309123d56b03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=844510384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.844510384
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2693246487
Short name	T770
Test name
Test status
Simulation time	327061418 ps
CPU time	23.25 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:38 PM PDT 24
Peak memory	204604 kb
Host	smart-bbe0eade-0943-42a0-b1dc-a6eaa804679b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693246487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2693246487
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.3661913879
Short name	T256
Test name
Test status
Simulation time	114091833 ps
CPU time	11.16 seconds
Started	Apr 02 12:55:18 PM PDT 24
Finished	Apr 02 12:55:30 PM PDT 24
Peak memory	204016 kb
Host	smart-996844a5-4a48-4184-9e02-3d418dd2c088
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3661913879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3661913879
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.1741693579
Short name	T513
Test name
Test status
Simulation time	208994068 ps
CPU time	3.44 seconds
Started	Apr 02 12:55:18 PM PDT 24
Finished	Apr 02 12:55:22 PM PDT 24
Peak memory	203468 kb
Host	smart-8229dcfe-87c5-4ada-8f50-9f0052dff1fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1741693579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1741693579
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3942933959
Short name	T588
Test name
Test status
Simulation time	3092568677 ps
CPU time	25.7 seconds
Started	Apr 02 12:55:15 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	203560 kb
Host	smart-fac1ebd5-6545-4741-b0ed-f34c722b6314
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3942933959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3942933959
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2855687479
Short name	T823
Test name
Test status
Simulation time	38278032 ps
CPU time	2.22 seconds
Started	Apr 02 12:55:24 PM PDT 24
Finished	Apr 02 12:55:27 PM PDT 24
Peak memory	203492 kb
Host	smart-7071d52e-9ee3-465d-9ed3-c6a9e993daa1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855687479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2855687479
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.1089050724
Short name	T78
Test name
Test status
Simulation time	6001100 ps
CPU time	0.8 seconds
Started	Apr 02 12:55:25 PM PDT 24
Finished	Apr 02 12:55:26 PM PDT 24
Peak memory	195220 kb
Host	smart-e36a36cd-3f8b-476a-af7c-581241774fbb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1089050724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1089050724
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.761602937
Short name	T605
Test name
Test status
Simulation time	730401165 ps
CPU time	77.9 seconds
Started	Apr 02 12:55:19 PM PDT 24
Finished	Apr 02 12:56:38 PM PDT 24
Peak memory	207108 kb
Host	smart-d2726983-ade9-4f91-a614-74e65d4c538c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=761602937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.761602937
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.4037263679
Short name	T161
Test name
Test status
Simulation time	2899707415 ps
CPU time	349.03 seconds
Started	Apr 02 12:55:22 PM PDT 24
Finished	Apr 02 01:01:11 PM PDT 24
Peak memory	221556 kb
Host	smart-f86c816f-802f-47c2-abe2-41886d981279
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4037263679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.4037263679
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.883319152
Short name	T721
Test name
Test status
Simulation time	7144832 ps
CPU time	4.52 seconds
Started	Apr 02 12:55:22 PM PDT 24
Finished	Apr 02 12:55:27 PM PDT 24
Peak memory	203424 kb
Host	smart-cb1b0343-5b0d-4f21-acae-97287eb2aad9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883319152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.883319152
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2588558858
Short name	T286
Test name
Test status
Simulation time	40128987 ps
CPU time	5.98 seconds
Started	Apr 02 12:55:17 PM PDT 24
Finished	Apr 02 12:55:24 PM PDT 24
Peak memory	204728 kb
Host	smart-a60c3186-a615-412f-aa89-d0b56df54229
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588558858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2588558858
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.784105034
Short name	T630
Test name
Test status
Simulation time	176555034 ps
CPU time	21.88 seconds
Started	Apr 02 12:55:21 PM PDT 24
Finished	Apr 02 12:55:43 PM PDT 24
Peak memory	211620 kb
Host	smart-60142ced-1126-4c5b-aa43-95ef41269852
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=784105034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.784105034
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2238947803
Short name	T128
Test name
Test status
Simulation time	44977125100 ps
CPU time	319.78 seconds
Started	Apr 02 12:55:22 PM PDT 24
Finished	Apr 02 01:00:42 PM PDT 24
Peak memory	206680 kb
Host	smart-e28d26a6-0c36-4097-ac0d-d408e6eaa8e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2238947803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2238947803
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4091877021
Short name	T723
Test name
Test status
Simulation time	44552521 ps
CPU time	5.2 seconds
Started	Apr 02 12:55:24 PM PDT 24
Finished	Apr 02 12:55:29 PM PDT 24
Peak memory	203708 kb
Host	smart-e362ffc2-d75f-4054-8b69-71782cd5c30d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091877021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4091877021
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.2655880098
Short name	T307
Test name
Test status
Simulation time	98355180 ps
CPU time	3.73 seconds
Started	Apr 02 12:55:23 PM PDT 24
Finished	Apr 02 12:55:26 PM PDT 24
Peak memory	203516 kb
Host	smart-c783f94c-7d9a-4f9e-8e00-de4a68fa8787
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2655880098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2655880098
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.13879509
Short name	T800
Test name
Test status
Simulation time	110405508 ps
CPU time	17.59 seconds
Started	Apr 02 12:55:23 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	204604 kb
Host	smart-899e8b5e-0752-46c1-a67f-f65d0f37bd52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=13879509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.13879509
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3441790479
Short name	T490
Test name
Test status
Simulation time	33898841272 ps
CPU time	74.54 seconds
Started	Apr 02 12:55:23 PM PDT 24
Finished	Apr 02 12:56:38 PM PDT 24
Peak memory	204824 kb
Host	smart-2c7bf736-d61e-4447-aa1b-7b8a18844fdf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441790479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3441790479
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3776314389
Short name	T310
Test name
Test status
Simulation time	31862929065 ps
CPU time	267.14 seconds
Started	Apr 02 12:55:21 PM PDT 24
Finished	Apr 02 12:59:49 PM PDT 24
Peak memory	204736 kb
Host	smart-c4682138-a84b-4393-82a7-f4ccdea4ffbc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3776314389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3776314389
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3698522450
Short name	T634
Test name
Test status
Simulation time	487091340 ps
CPU time	24.97 seconds
Started	Apr 02 12:55:22 PM PDT 24
Finished	Apr 02 12:55:47 PM PDT 24
Peak memory	205160 kb
Host	smart-db2b2c56-0983-47c2-bc0d-db08e1c35b80
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698522450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3698522450
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.1433535648
Short name	T759
Test name
Test status
Simulation time	172612664 ps
CPU time	11.39 seconds
Started	Apr 02 12:55:22 PM PDT 24
Finished	Apr 02 12:55:34 PM PDT 24
Peak memory	204160 kb
Host	smart-f20d24cb-27e5-41df-95c7-9dfd758f9b26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1433535648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1433535648
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.2866957753
Short name	T837
Test name
Test status
Simulation time	340447781 ps
CPU time	3.82 seconds
Started	Apr 02 12:55:17 PM PDT 24
Finished	Apr 02 12:55:21 PM PDT 24
Peak memory	203496 kb
Host	smart-7f3c1cf8-bc2d-4ed3-b12e-b85698164830
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866957753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2866957753
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1857896191
Short name	T376
Test name
Test status
Simulation time	5957549218 ps
CPU time	36.44 seconds
Started	Apr 02 12:55:17 PM PDT 24
Finished	Apr 02 12:55:54 PM PDT 24
Peak memory	203492 kb
Host	smart-37a3c732-42eb-4098-880c-88b287ef383a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857896191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1857896191
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3430711261
Short name	T631
Test name
Test status
Simulation time	15050112889 ps
CPU time	37.41 seconds
Started	Apr 02 12:55:20 PM PDT 24
Finished	Apr 02 12:55:59 PM PDT 24
Peak memory	203568 kb
Host	smart-4b56decd-0edf-4bbe-9e77-c0cca04a520b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3430711261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3430711261
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2763706397
Short name	T189
Test name
Test status
Simulation time	35341330 ps
CPU time	2.56 seconds
Started	Apr 02 12:55:25 PM PDT 24
Finished	Apr 02 12:55:28 PM PDT 24
Peak memory	203488 kb
Host	smart-4198ed24-b5b3-40d1-a7f1-a78b6cc07e09
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763706397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2763706397
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.2733252079
Short name	T90
Test name
Test status
Simulation time	15078919802 ps
CPU time	195.27 seconds
Started	Apr 02 12:55:24 PM PDT 24
Finished	Apr 02 12:58:40 PM PDT 24
Peak memory	205648 kb
Host	smart-c3ac3b1e-0a5e-4eff-8255-d5ad09f0a776
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2733252079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2733252079
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.256141142
Short name	T839
Test name
Test status
Simulation time	2144614745 ps
CPU time	56.29 seconds
Started	Apr 02 12:55:27 PM PDT 24
Finished	Apr 02 12:56:23 PM PDT 24
Peak memory	205912 kb
Host	smart-376e370b-14bf-4bb5-897c-69a872cd023d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=256141142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.256141142
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2146632802
Short name	T66
Test name
Test status
Simulation time	5867494884 ps
CPU time	426.38 seconds
Started	Apr 02 12:55:22 PM PDT 24
Finished	Apr 02 01:02:29 PM PDT 24
Peak memory	211776 kb
Host	smart-dc32c5c7-a061-4b5f-bc2e-47d07f840782
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2146632802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2146632802
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2786953550
Short name	T19
Test name
Test status
Simulation time	1743374723 ps
CPU time	183.03 seconds
Started	Apr 02 12:55:28 PM PDT 24
Finished	Apr 02 12:58:31 PM PDT 24
Peak memory	208588 kb
Host	smart-e65ada7e-1d84-460d-967b-28d57f4c3f0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2786953550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2786953550
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3740428967
Short name	T212
Test name
Test status
Simulation time	192455710 ps
CPU time	17.24 seconds
Started	Apr 02 12:55:24 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	204988 kb
Host	smart-5b2b581f-94e5-42e2-ac76-1b97312ba10a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740428967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3740428967
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3605001760
Short name	T864
Test name
Test status
Simulation time	301058692 ps
CPU time	11.49 seconds
Started	Apr 02 12:55:26 PM PDT 24
Finished	Apr 02 12:55:38 PM PDT 24
Peak memory	211596 kb
Host	smart-1dd2807b-9d98-4dfc-a5a3-ce7973e69375
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605001760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3605001760
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1170881437
Short name	T550
Test name
Test status
Simulation time	386581814 ps
CPU time	14.89 seconds
Started	Apr 02 12:55:27 PM PDT 24
Finished	Apr 02 12:55:42 PM PDT 24
Peak memory	203664 kb
Host	smart-34786e53-e4e8-4b6f-9fb5-39d27dad03a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1170881437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1170881437
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.546561699
Short name	T211
Test name
Test status
Simulation time	852156196 ps
CPU time	28.35 seconds
Started	Apr 02 12:55:41 PM PDT 24
Finished	Apr 02 12:56:10 PM PDT 24
Peak memory	203556 kb
Host	smart-d01017d4-f3a1-4d2f-bca1-e750343cc424
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=546561699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.546561699
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.3508118432
Short name	T65
Test name
Test status
Simulation time	1074001283 ps
CPU time	39.23 seconds
Started	Apr 02 12:55:41 PM PDT 24
Finished	Apr 02 12:56:21 PM PDT 24
Peak memory	205228 kb
Host	smart-c1af1578-3915-49e1-9794-91222b78c204
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3508118432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3508118432
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2092029362
Short name	T391
Test name
Test status
Simulation time	19467873943 ps
CPU time	69.92 seconds
Started	Apr 02 12:55:25 PM PDT 24
Finished	Apr 02 12:56:35 PM PDT 24
Peak memory	204768 kb
Host	smart-0548959b-4036-4531-94ca-042b2f572dae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092029362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2092029362
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3402190929
Short name	T47
Test name
Test status
Simulation time	21738724570 ps
CPU time	196.73 seconds
Started	Apr 02 12:55:25 PM PDT 24
Finished	Apr 02 12:58:42 PM PDT 24
Peak memory	205064 kb
Host	smart-3ce7bd2d-baff-440d-98e6-14bef97bfe5c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3402190929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3402190929
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1378002699
Short name	T786
Test name
Test status
Simulation time	390241166 ps
CPU time	22.89 seconds
Started	Apr 02 12:55:41 PM PDT 24
Finished	Apr 02 12:56:05 PM PDT 24
Peak memory	204640 kb
Host	smart-38402862-fe9d-4a28-b677-25766de28c5d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378002699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1378002699
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.2533577490
Short name	T216
Test name
Test status
Simulation time	1014151155 ps
CPU time	14.88 seconds
Started	Apr 02 12:55:26 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	204064 kb
Host	smart-e07f56d8-5686-417f-8d5a-0ce5c50f2cde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2533577490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2533577490
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.2417495096
Short name	T148
Test name
Test status
Simulation time	30060662 ps
CPU time	2.23 seconds
Started	Apr 02 12:55:26 PM PDT 24
Finished	Apr 02 12:55:29 PM PDT 24
Peak memory	203488 kb
Host	smart-bf2be89d-3c11-4346-9f35-8d62fd710bb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2417495096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2417495096
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1309232084
Short name	T449
Test name
Test status
Simulation time	16606780171 ps
CPU time	32.09 seconds
Started	Apr 02 12:55:41 PM PDT 24
Finished	Apr 02 12:56:14 PM PDT 24
Peak memory	203580 kb
Host	smart-a55b6f7e-91d0-464e-b767-623009248f2b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309232084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1309232084
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3882716426
Short name	T703
Test name
Test status
Simulation time	28002370668 ps
CPU time	60.02 seconds
Started	Apr 02 12:55:41 PM PDT 24
Finished	Apr 02 12:56:42 PM PDT 24
Peak memory	203552 kb
Host	smart-5623619a-d1c6-4e12-a12f-0bddd3747636
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3882716426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3882716426
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.4278048855
Short name	T529
Test name
Test status
Simulation time	33332017 ps
CPU time	2.2 seconds
Started	Apr 02 12:55:25 PM PDT 24
Finished	Apr 02 12:55:27 PM PDT 24
Peak memory	203484 kb
Host	smart-1d409424-6fee-432c-a6e7-8463200a36ab
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278048855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.4278048855
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.2520833418
Short name	T183
Test name
Test status
Simulation time	7314297656 ps
CPU time	70.73 seconds
Started	Apr 02 12:55:26 PM PDT 24
Finished	Apr 02 12:56:37 PM PDT 24
Peak memory	206116 kb
Host	smart-6ddde4db-bc75-4d74-a9ad-f1103b76a353
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2520833418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2520833418
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2021604695
Short name	T878
Test name
Test status
Simulation time	9196338394 ps
CPU time	207.29 seconds
Started	Apr 02 12:55:30 PM PDT 24
Finished	Apr 02 12:58:58 PM PDT 24
Peak memory	207040 kb
Host	smart-67db8e0c-dce0-4f29-a363-23292019417e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2021604695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2021604695
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3192693234
Short name	T894
Test name
Test status
Simulation time	322842133 ps
CPU time	126.05 seconds
Started	Apr 02 12:55:27 PM PDT 24
Finished	Apr 02 12:57:33 PM PDT 24
Peak memory	208568 kb
Host	smart-aad9b402-898f-40e8-b9b0-e5280551ec55
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3192693234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3192693234
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3682913920
Short name	T583
Test name
Test status
Simulation time	193560035 ps
CPU time	49.86 seconds
Started	Apr 02 12:55:30 PM PDT 24
Finished	Apr 02 12:56:20 PM PDT 24
Peak memory	206608 kb
Host	smart-f1bdaa77-bbb4-401f-a010-9c19e317dd55
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3682913920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3682913920
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.960060666
Short name	T794
Test name
Test status
Simulation time	602080632 ps
CPU time	26.76 seconds
Started	Apr 02 12:55:25 PM PDT 24
Finished	Apr 02 12:55:52 PM PDT 24
Peak memory	204940 kb
Host	smart-a541bfe9-0632-46d4-84f2-96fe2460eefe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960060666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.960060666
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.8410620
Short name	T154
Test name
Test status
Simulation time	162966807 ps
CPU time	18.66 seconds
Started	Apr 02 12:55:29 PM PDT 24
Finished	Apr 02 12:55:47 PM PDT 24
Peak memory	205192 kb
Host	smart-73798ec8-acb2-4db9-b8c3-6e9d475581bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=8410620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.8410620
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3422500177
Short name	T43
Test name
Test status
Simulation time	67027194166 ps
CPU time	651.04 seconds
Started	Apr 02 12:55:32 PM PDT 24
Finished	Apr 02 01:06:23 PM PDT 24
Peak memory	206108 kb
Host	smart-97c1b0d0-0446-4fec-a26c-5017296a6995
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3422500177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.3422500177
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3233903483
Short name	T570
Test name
Test status
Simulation time	370648784 ps
CPU time	12.22 seconds
Started	Apr 02 12:55:34 PM PDT 24
Finished	Apr 02 12:55:47 PM PDT 24
Peak memory	203632 kb
Host	smart-6838ee63-8ef7-408d-ac93-6b5d92f6c3ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3233903483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3233903483
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.3738187490
Short name	T760
Test name
Test status
Simulation time	121792904 ps
CPU time	13.93 seconds
Started	Apr 02 12:55:38 PM PDT 24
Finished	Apr 02 12:55:54 PM PDT 24
Peak memory	203584 kb
Host	smart-6354b860-8d83-48f5-9986-bbf01b2c266e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3738187490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3738187490
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.682438865
Short name	T507
Test name
Test status
Simulation time	478516238 ps
CPU time	13.76 seconds
Started	Apr 02 12:55:30 PM PDT 24
Finished	Apr 02 12:55:43 PM PDT 24
Peak memory	204524 kb
Host	smart-9fdfb823-3ee0-4941-8a72-50063af341cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682438865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.682438865
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1302007594
Short name	T103
Test name
Test status
Simulation time	7356208512 ps
CPU time	28.02 seconds
Started	Apr 02 12:55:31 PM PDT 24
Finished	Apr 02 12:56:00 PM PDT 24
Peak memory	211692 kb
Host	smart-1c553c25-50ec-47dc-9c45-d1a242085598
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302007594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1302007594
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2304599042
Short name	T243
Test name
Test status
Simulation time	21099389482 ps
CPU time	177.47 seconds
Started	Apr 02 12:55:33 PM PDT 24
Finished	Apr 02 12:58:31 PM PDT 24
Peak memory	211728 kb
Host	smart-6e71fca4-9675-41b6-8ad6-7bec9cc6e33e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2304599042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2304599042
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1781189179
Short name	T244
Test name
Test status
Simulation time	136364942 ps
CPU time	10.5 seconds
Started	Apr 02 12:55:30 PM PDT 24
Finished	Apr 02 12:55:41 PM PDT 24
Peak memory	204824 kb
Host	smart-1eda9262-8f43-406d-ac50-1f3e0312c551
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781189179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1781189179
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.561567739
Short name	T361
Test name
Test status
Simulation time	216081832 ps
CPU time	8.19 seconds
Started	Apr 02 12:55:31 PM PDT 24
Finished	Apr 02 12:55:40 PM PDT 24
Peak memory	203492 kb
Host	smart-323a40a9-309e-4ef4-bbdd-10bfe7bf88fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561567739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.561567739
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.128334458
Short name	T4
Test name
Test status
Simulation time	168214134 ps
CPU time	3.98 seconds
Started	Apr 02 12:55:33 PM PDT 24
Finished	Apr 02 12:55:37 PM PDT 24
Peak memory	203468 kb
Host	smart-95a51bfb-982b-4f0e-8dbd-7b3cdd860f2d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=128334458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.128334458
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1543614578
Short name	T218
Test name
Test status
Simulation time	6507733643 ps
CPU time	36.24 seconds
Started	Apr 02 12:55:30 PM PDT 24
Finished	Apr 02 12:56:07 PM PDT 24
Peak memory	203564 kb
Host	smart-8aa413e6-5a12-4303-9d62-9dfde549b362
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543614578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1543614578
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3128951756
Short name	T633
Test name
Test status
Simulation time	8708920124 ps
CPU time	37.09 seconds
Started	Apr 02 12:55:31 PM PDT 24
Finished	Apr 02 12:56:09 PM PDT 24
Peak memory	203548 kb
Host	smart-9c0446a2-d84b-489c-bc8e-373cabb78466
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3128951756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3128951756
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2969178548
Short name	T479
Test name
Test status
Simulation time	45607183 ps
CPU time	2.45 seconds
Started	Apr 02 12:55:31 PM PDT 24
Finished	Apr 02 12:55:34 PM PDT 24
Peak memory	203448 kb
Host	smart-1c259bf7-a2d2-4415-8d08-1b43199e001e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969178548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2969178548
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2117274141
Short name	T273
Test name
Test status
Simulation time	1038786454 ps
CPU time	91.07 seconds
Started	Apr 02 12:55:35 PM PDT 24
Finished	Apr 02 12:57:07 PM PDT 24
Peak memory	207116 kb
Host	smart-1ff9caa4-6e02-4f21-b50d-d6c2d8612b49
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2117274141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2117274141
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.806936944
Short name	T129
Test name
Test status
Simulation time	2954124450 ps
CPU time	151 seconds
Started	Apr 02 12:55:34 PM PDT 24
Finished	Apr 02 12:58:05 PM PDT 24
Peak memory	211720 kb
Host	smart-fe09f468-f5be-437d-9a2c-fb7750b37241
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=806936944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand _reset.806936944
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.429727139
Short name	T33
Test name
Test status
Simulation time	142096530 ps
CPU time	40.45 seconds
Started	Apr 02 12:55:35 PM PDT 24
Finished	Apr 02 12:56:15 PM PDT 24
Peak memory	206620 kb
Host	smart-a5485a6d-18ec-439d-abbf-d82afde9418f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=429727139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res et_error.429727139
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.4070410666
Short name	T461
Test name
Test status
Simulation time	1172195796 ps
CPU time	20.7 seconds
Started	Apr 02 12:55:37 PM PDT 24
Finished	Apr 02 12:55:59 PM PDT 24
Peak memory	211660 kb
Host	smart-777f58eb-38e9-4889-9cf5-b0070b7d28b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4070410666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.4070410666
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3276224289
Short name	T523
Test name
Test status
Simulation time	173605111 ps
CPU time	28.5 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:52:54 PM PDT 24
Peak memory	205848 kb
Host	smart-cecc973f-3cba-4de2-a30d-7c74eab04f1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3276224289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3276224289
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3026114593
Short name	T51
Test name
Test status
Simulation time	122981712696 ps
CPU time	711.54 seconds
Started	Apr 02 12:52:26 PM PDT 24
Finished	Apr 02 01:04:18 PM PDT 24
Peak memory	207760 kb
Host	smart-ce257e46-a6ec-4a11-9bda-5370a7b3e93d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3026114593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3026114593
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.76144808
Short name	T888
Test name
Test status
Simulation time	108117404 ps
CPU time	10.34 seconds
Started	Apr 02 12:52:22 PM PDT 24
Finished	Apr 02 12:52:33 PM PDT 24
Peak memory	203768 kb
Host	smart-75e05fc7-0b18-419e-a603-7c95d253dab0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=76144808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.76144808
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.175556279
Short name	T248
Test name
Test status
Simulation time	581084054 ps
CPU time	17.64 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:52:44 PM PDT 24
Peak memory	203588 kb
Host	smart-718c0eb8-b3fb-465c-999f-6eeae1546e7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=175556279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.175556279
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.4233292382
Short name	T54
Test name
Test status
Simulation time	1850523311 ps
CPU time	14.94 seconds
Started	Apr 02 12:52:21 PM PDT 24
Finished	Apr 02 12:52:36 PM PDT 24
Peak memory	211668 kb
Host	smart-4c4545f0-4c70-49d0-ad9f-f294c1d742c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4233292382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.4233292382
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3644052758
Short name	T809
Test name
Test status
Simulation time	35184080887 ps
CPU time	101.53 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:54:07 PM PDT 24
Peak memory	204984 kb
Host	smart-f52b6b5c-9faa-4df2-8ec3-8be79dfa1b8a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644052758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3644052758
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2753368492
Short name	T705
Test name
Test status
Simulation time	11636560366 ps
CPU time	99.82 seconds
Started	Apr 02 12:52:24 PM PDT 24
Finished	Apr 02 12:54:04 PM PDT 24
Peak memory	205176 kb
Host	smart-b0348b94-6abb-4cc8-a573-2f50344b777f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2753368492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2753368492
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2166280145
Short name	T738
Test name
Test status
Simulation time	257973536 ps
CPU time	11.24 seconds
Started	Apr 02 12:52:20 PM PDT 24
Finished	Apr 02 12:52:32 PM PDT 24
Peak memory	204628 kb
Host	smart-ba895616-1bf3-499e-b13f-8c26e501a707
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166280145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2166280145
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.43689930
Short name	T419
Test name
Test status
Simulation time	552940382 ps
CPU time	12.43 seconds
Started	Apr 02 12:52:24 PM PDT 24
Finished	Apr 02 12:52:36 PM PDT 24
Peak memory	204012 kb
Host	smart-e679f3ab-fe44-4dc8-9d46-f4a738989305
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=43689930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.43689930
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.4099922607
Short name	T472
Test name
Test status
Simulation time	278872127 ps
CPU time	4.13 seconds
Started	Apr 02 12:52:22 PM PDT 24
Finished	Apr 02 12:52:27 PM PDT 24
Peak memory	203400 kb
Host	smart-43668835-43b5-48b8-875b-e8a6c90f9732
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4099922607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.4099922607
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3772619748
Short name	T654
Test name
Test status
Simulation time	36444378060 ps
CPU time	50.79 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:53:15 PM PDT 24
Peak memory	203352 kb
Host	smart-cc74d574-13df-4830-a42a-a1f93135083e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772619748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3772619748
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.792139297
Short name	T287
Test name
Test status
Simulation time	5217559194 ps
CPU time	28.91 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:53 PM PDT 24
Peak memory	203556 kb
Host	smart-882cd647-aaa8-41da-a223-468356762036
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=792139297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.792139297
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.514757806
Short name	T331
Test name
Test status
Simulation time	31129268 ps
CPU time	2.56 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:26 PM PDT 24
Peak memory	203508 kb
Host	smart-cee6439b-88d5-45a0-bd1e-0712326e8728
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514757806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.514757806
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.2818085925
Short name	T693
Test name
Test status
Simulation time	683124851 ps
CPU time	83.64 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:53:49 PM PDT 24
Peak memory	206700 kb
Host	smart-ea257e29-8344-412b-bd2b-5d560718401d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2818085925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2818085925
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.720381582
Short name	T320
Test name
Test status
Simulation time	2296657952 ps
CPU time	58.45 seconds
Started	Apr 02 12:52:27 PM PDT 24
Finished	Apr 02 12:53:25 PM PDT 24
Peak memory	205968 kb
Host	smart-739db2b3-d53d-48cb-80e0-f45548c67fc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=720381582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.720381582
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1707945031
Short name	T306
Test name
Test status
Simulation time	55969703 ps
CPU time	33.04 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:52:59 PM PDT 24
Peak memory	206648 kb
Host	smart-d62f2ef8-a2ef-41dc-9f35-4d1fc6c374bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1707945031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1707945031
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3659308777
Short name	T24
Test name
Test status
Simulation time	4212885586 ps
CPU time	150.47 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:54:56 PM PDT 24
Peak memory	208088 kb
Host	smart-e0ba2c7d-5916-423c-8f40-92fe2fcb37ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3659308777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.3659308777
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1913546644
Short name	T619
Test name
Test status
Simulation time	44294984 ps
CPU time	7.11 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:31 PM PDT 24
Peak memory	211664 kb
Host	smart-7d46d06c-56c2-48fd-8e8c-9b9e14769d81
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1913546644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1913546644
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2576080431
Short name	T113
Test name
Test status
Simulation time	673784062 ps
CPU time	11.09 seconds
Started	Apr 02 12:52:24 PM PDT 24
Finished	Apr 02 12:52:36 PM PDT 24
Peak memory	204300 kb
Host	smart-9b00173f-6250-42ea-8031-1ab9c2cf0171
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2576080431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2576080431
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3382659312
Short name	T509
Test name
Test status
Simulation time	3405863906 ps
CPU time	31.42 seconds
Started	Apr 02 12:52:26 PM PDT 24
Finished	Apr 02 12:52:58 PM PDT 24
Peak memory	203568 kb
Host	smart-02dcb377-80aa-4f32-88c5-5bfd09667855
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3382659312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.3382659312
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2222875966
Short name	T868
Test name
Test status
Simulation time	1134218360 ps
CPU time	12.47 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:52:40 PM PDT 24
Peak memory	203544 kb
Host	smart-2aee71d9-cfff-43a6-8336-2e430dcf8266
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2222875966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2222875966
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.1330709905
Short name	T815
Test name
Test status
Simulation time	1052810357 ps
CPU time	33.91 seconds
Started	Apr 02 12:52:26 PM PDT 24
Finished	Apr 02 12:53:01 PM PDT 24
Peak memory	203664 kb
Host	smart-9662b4a8-2ec6-43c0-be0e-16dcca80406d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1330709905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1330709905
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.4115906672
Short name	T198
Test name
Test status
Simulation time	380765012 ps
CPU time	11.33 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:52:37 PM PDT 24
Peak memory	211700 kb
Host	smart-348801df-a3ec-4a94-90bd-e66323d18df3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4115906672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.4115906672
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.3950812674
Short name	T97
Test name
Test status
Simulation time	42316147405 ps
CPU time	256.07 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:56:42 PM PDT 24
Peak memory	205316 kb
Host	smart-2f16a90b-37dc-42a5-8c77-053b8509f6fd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950812674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3950812674
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1000305865
Short name	T362
Test name
Test status
Simulation time	6315202742 ps
CPU time	45.38 seconds
Started	Apr 02 12:52:24 PM PDT 24
Finished	Apr 02 12:53:10 PM PDT 24
Peak memory	211732 kb
Host	smart-2034fef8-31ea-48d0-b58b-3fb08440a34f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1000305865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1000305865
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2218583130
Short name	T450
Test name
Test status
Simulation time	68997481 ps
CPU time	7.76 seconds
Started	Apr 02 12:52:23 PM PDT 24
Finished	Apr 02 12:52:31 PM PDT 24
Peak memory	204668 kb
Host	smart-bd7e6f3f-98d7-43ce-8638-44f50346e436
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218583130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2218583130
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.3903534998
Short name	T554
Test name
Test status
Simulation time	1411477959 ps
CPU time	30.69 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:52:56 PM PDT 24
Peak memory	204068 kb
Host	smart-11e75c57-b6c7-4164-b8eb-564ba50f7adc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3903534998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3903534998
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.544499586
Short name	T203
Test name
Test status
Simulation time	140568041 ps
CPU time	3.62 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:52:30 PM PDT 24
Peak memory	203504 kb
Host	smart-2898ca65-fb46-4cc2-8246-81540cf45841
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=544499586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.544499586
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1334797505
Short name	T348
Test name
Test status
Simulation time	6562020869 ps
CPU time	30.24 seconds
Started	Apr 02 12:52:22 PM PDT 24
Finished	Apr 02 12:52:53 PM PDT 24
Peak memory	203540 kb
Host	smart-e82356e5-fd21-444a-821a-89ecc7c5ddcc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334797505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1334797505
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1938001737
Short name	T636
Test name
Test status
Simulation time	3596771351 ps
CPU time	26.58 seconds
Started	Apr 02 12:52:24 PM PDT 24
Finished	Apr 02 12:52:51 PM PDT 24
Peak memory	203552 kb
Host	smart-9883a4c9-86a5-4a11-b504-8adec63eb7e7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1938001737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1938001737
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.693445119
Short name	T671
Test name
Test status
Simulation time	24293359 ps
CPU time	2.12 seconds
Started	Apr 02 12:52:25 PM PDT 24
Finished	Apr 02 12:52:27 PM PDT 24
Peak memory	203496 kb
Host	smart-7ed61247-8b7a-4e9d-90b1-a6f7b2259967
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693445119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.693445119
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.3719888190
Short name	T812
Test name
Test status
Simulation time	1557243411 ps
CPU time	55.19 seconds
Started	Apr 02 12:52:32 PM PDT 24
Finished	Apr 02 12:53:27 PM PDT 24
Peak memory	205596 kb
Host	smart-2c4e2a9f-9b0f-4b3c-b3ed-934acafb7d50
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3719888190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3719888190
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1379511063
Short name	T79
Test name
Test status
Simulation time	2135345454 ps
CPU time	87.44 seconds
Started	Apr 02 12:52:27 PM PDT 24
Finished	Apr 02 12:53:54 PM PDT 24
Peak memory	206172 kb
Host	smart-c5db90f7-49cd-4136-80e9-dd0818d34a73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1379511063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1379511063
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3615729251
Short name	T21
Test name
Test status
Simulation time	464793010 ps
CPU time	200.07 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:55:50 PM PDT 24
Peak memory	208356 kb
Host	smart-371cf1af-547e-4d9c-a4f9-f858823cb1d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3615729251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.3615729251
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1366290765
Short name	T615
Test name
Test status
Simulation time	148743976 ps
CPU time	44.2 seconds
Started	Apr 02 12:52:32 PM PDT 24
Finished	Apr 02 12:53:16 PM PDT 24
Peak memory	206736 kb
Host	smart-7c9bd731-3fd1-48d4-9ce1-4c0e65eeb57b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1366290765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1366290765
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1173805624
Short name	T164
Test name
Test status
Simulation time	1853105515 ps
CPU time	18.62 seconds
Started	Apr 02 12:52:27 PM PDT 24
Finished	Apr 02 12:52:46 PM PDT 24
Peak memory	205232 kb
Host	smart-bcbbd442-c376-489c-8645-88fb85cc2d1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173805624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1173805624
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3299483436
Short name	T194
Test name
Test status
Simulation time	8663106953 ps
CPU time	72.54 seconds
Started	Apr 02 12:52:27 PM PDT 24
Finished	Apr 02 12:53:40 PM PDT 24
Peak memory	206760 kb
Host	smart-42237f34-e8ed-4db5-a8e5-10dbaea89835
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3299483436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3299483436
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3771759939
Short name	T168
Test name
Test status
Simulation time	83549490273 ps
CPU time	298.81 seconds
Started	Apr 02 12:52:26 PM PDT 24
Finished	Apr 02 12:57:25 PM PDT 24
Peak memory	211768 kb
Host	smart-195a15b8-2fd6-4db4-98ce-61c2ec35dbac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3771759939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3771759939
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1852436927
Short name	T436
Test name
Test status
Simulation time	962808251 ps
CPU time	17.66 seconds
Started	Apr 02 12:52:33 PM PDT 24
Finished	Apr 02 12:52:51 PM PDT 24
Peak memory	203848 kb
Host	smart-b69df30b-8c1a-42fa-a381-97460e7bd2d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1852436927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1852436927
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.3570468368
Short name	T870
Test name
Test status
Simulation time	69743752 ps
CPU time	2.98 seconds
Started	Apr 02 12:52:32 PM PDT 24
Finished	Apr 02 12:52:35 PM PDT 24
Peak memory	203504 kb
Host	smart-56cc49f5-89ae-4bcb-8c69-cbfdfe08d169
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3570468368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3570468368
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.3029114108
Short name	T293
Test name
Test status
Simulation time	267461081 ps
CPU time	27.25 seconds
Started	Apr 02 12:52:27 PM PDT 24
Finished	Apr 02 12:52:55 PM PDT 24
Peak memory	205124 kb
Host	smart-bd2bd8b0-4756-499a-a7fe-997a8354cbbf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3029114108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3029114108
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3486615016
Short name	T409
Test name
Test status
Simulation time	21081354481 ps
CPU time	58.39 seconds
Started	Apr 02 12:52:26 PM PDT 24
Finished	Apr 02 12:53:25 PM PDT 24
Peak memory	204780 kb
Host	smart-9f30b388-d405-446b-84e2-61b098a8ff5b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486615016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3486615016
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4244717914
Short name	T12
Test name
Test status
Simulation time	74596456966 ps
CPU time	257.12 seconds
Started	Apr 02 12:52:30 PM PDT 24
Finished	Apr 02 12:56:47 PM PDT 24
Peak memory	211720 kb
Host	smart-b6a5bb43-8683-4349-821a-8c498ec9b689
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4244717914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4244717914
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.458495274
Short name	T782
Test name
Test status
Simulation time	33184995 ps
CPU time	3.67 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:52:32 PM PDT 24
Peak memory	204036 kb
Host	smart-6e43b06a-e215-475b-8499-927f61daee93
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458495274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.458495274
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.2466597284
Short name	T191
Test name
Test status
Simulation time	79123821 ps
CPU time	2.31 seconds
Started	Apr 02 12:52:27 PM PDT 24
Finished	Apr 02 12:52:30 PM PDT 24
Peak memory	203572 kb
Host	smart-eb6a9019-2185-47dd-b519-fc6f5c77da3a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2466597284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2466597284
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.2245226532
Short name	T229
Test name
Test status
Simulation time	27222646 ps
CPU time	2.36 seconds
Started	Apr 02 12:52:30 PM PDT 24
Finished	Apr 02 12:52:33 PM PDT 24
Peak memory	203468 kb
Host	smart-edb40706-7c0b-4cb8-af07-52bde745ab05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2245226532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2245226532
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3717655449
Short name	T281
Test name
Test status
Simulation time	8882315020 ps
CPU time	35.24 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:53:04 PM PDT 24
Peak memory	203544 kb
Host	smart-2ac055c5-494b-4131-973c-b8ff9acbc5f1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717655449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3717655449
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.4285553088
Short name	T727
Test name
Test status
Simulation time	3695231356 ps
CPU time	27.87 seconds
Started	Apr 02 12:52:29 PM PDT 24
Finished	Apr 02 12:52:57 PM PDT 24
Peak memory	203552 kb
Host	smart-f1730524-9d31-4494-a034-a66fc5c23803
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4285553088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4285553088
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.241044449
Short name	T17
Test name
Test status
Simulation time	37455822 ps
CPU time	2.52 seconds
Started	Apr 02 12:52:28 PM PDT 24
Finished	Apr 02 12:52:31 PM PDT 24
Peak memory	203512 kb
Host	smart-5d111ad8-d0cc-4ed2-90a1-09fc3480efbb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241044449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.241044449
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.2065472751
Short name	T99
Test name
Test status
Simulation time	7301027343 ps
CPU time	226.31 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:56:18 PM PDT 24
Peak memory	207560 kb
Host	smart-d4ba1dd5-cfa6-457e-a697-d472697ca962
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2065472751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2065472751
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3033205171
Short name	T836
Test name
Test status
Simulation time	5191785641 ps
CPU time	117.43 seconds
Started	Apr 02 12:52:30 PM PDT 24
Finished	Apr 02 12:54:28 PM PDT 24
Peak memory	206824 kb
Host	smart-20f75bae-40b8-4ee0-a65e-9a9303981ce2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3033205171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3033205171
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3980659354
Short name	T59
Test name
Test status
Simulation time	172920008 ps
CPU time	59.54 seconds
Started	Apr 02 12:52:30 PM PDT 24
Finished	Apr 02 12:53:30 PM PDT 24
Peak memory	207660 kb
Host	smart-8779956b-d8e0-4b97-96be-bb7129faf761
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3980659354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.3980659354
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1795264074
Short name	T124
Test name
Test status
Simulation time	374983355 ps
CPU time	46.74 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:53:18 PM PDT 24
Peak memory	206452 kb
Host	smart-4dd52bec-8c3a-49fd-bf9b-57a8648591b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1795264074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.1795264074
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.4180836456
Short name	T260
Test name
Test status
Simulation time	295097374 ps
CPU time	10.5 seconds
Started	Apr 02 12:52:32 PM PDT 24
Finished	Apr 02 12:52:43 PM PDT 24
Peak memory	204972 kb
Host	smart-da13a9f0-9693-473e-b9e7-42105fec75f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4180836456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4180836456
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1636902212
Short name	T106
Test name
Test status
Simulation time	222614306 ps
CPU time	26.08 seconds
Started	Apr 02 12:52:35 PM PDT 24
Finished	Apr 02 12:53:01 PM PDT 24
Peak memory	211656 kb
Host	smart-8726f645-ee87-4ef0-89f3-a16ef9cd0722
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636902212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1636902212
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.4157202936
Short name	T437
Test name
Test status
Simulation time	9424738695 ps
CPU time	61.24 seconds
Started	Apr 02 12:52:34 PM PDT 24
Finished	Apr 02 12:53:35 PM PDT 24
Peak memory	204556 kb
Host	smart-f0b1ae51-dd33-4f43-82d1-c20648b59684
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4157202936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.4157202936
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1941809472
Short name	T444
Test name
Test status
Simulation time	196654932 ps
CPU time	4.05 seconds
Started	Apr 02 12:52:32 PM PDT 24
Finished	Apr 02 12:52:36 PM PDT 24
Peak memory	203516 kb
Host	smart-8043f149-b406-4173-b983-8a3e06044650
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941809472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1941809472
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.1711622329
Short name	T421
Test name
Test status
Simulation time	1119883875 ps
CPU time	29.22 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:53:00 PM PDT 24
Peak memory	203392 kb
Host	smart-83225cda-4c61-4024-ba43-7c27551d1adb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1711622329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1711622329
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.3562509676
Short name	T143
Test name
Test status
Simulation time	3560151684 ps
CPU time	36.04 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:53:07 PM PDT 24
Peak memory	204936 kb
Host	smart-dd43d866-dc61-4c79-9fcc-e64b623249ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3562509676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3562509676
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1541224979
Short name	T891
Test name
Test status
Simulation time	40518546461 ps
CPU time	219.68 seconds
Started	Apr 02 12:52:30 PM PDT 24
Finished	Apr 02 12:56:10 PM PDT 24
Peak memory	204816 kb
Host	smart-757f435d-4f5d-4366-8f5b-6f09047c7644
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541224979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1541224979
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.831449698
Short name	T474
Test name
Test status
Simulation time	4757131740 ps
CPU time	31.48 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:53:03 PM PDT 24
Peak memory	203624 kb
Host	smart-489ed12d-5184-4372-976c-7bc4c9603d5d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=831449698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.831449698
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2016200892
Short name	T561
Test name
Test status
Simulation time	102854494 ps
CPU time	12.68 seconds
Started	Apr 02 12:52:33 PM PDT 24
Finished	Apr 02 12:52:46 PM PDT 24
Peak memory	204624 kb
Host	smart-95992fb2-c487-45d6-8ee5-756cfb95d1ef
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016200892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2016200892
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.4196125535
Short name	T646
Test name
Test status
Simulation time	615100010 ps
CPU time	13.39 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:52:45 PM PDT 24
Peak memory	204040 kb
Host	smart-cc127349-4335-4769-aa0c-13a0be987897
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4196125535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.4196125535
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.4186381544
Short name	T38
Test name
Test status
Simulation time	133343001 ps
CPU time	3.43 seconds
Started	Apr 02 12:52:34 PM PDT 24
Finished	Apr 02 12:52:37 PM PDT 24
Peak memory	203464 kb
Host	smart-f8e35f19-7983-47ea-a0b7-97921bf930c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4186381544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.4186381544
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1987548871
Short name	T575
Test name
Test status
Simulation time	11172837820 ps
CPU time	38.2 seconds
Started	Apr 02 12:52:34 PM PDT 24
Finished	Apr 02 12:53:13 PM PDT 24
Peak memory	203552 kb
Host	smart-623dc3c2-7939-4f83-8dd3-65e2d162643c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987548871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1987548871
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.909862755
Short name	T451
Test name
Test status
Simulation time	14406955442 ps
CPU time	45.54 seconds
Started	Apr 02 12:52:33 PM PDT 24
Finished	Apr 02 12:53:18 PM PDT 24
Peak memory	203572 kb
Host	smart-fb64940d-886d-4616-bacb-b218d2c242c8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=909862755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.909862755
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.858615884
Short name	T119
Test name
Test status
Simulation time	40554604 ps
CPU time	2.39 seconds
Started	Apr 02 12:52:35 PM PDT 24
Finished	Apr 02 12:52:37 PM PDT 24
Peak memory	203484 kb
Host	smart-7e44efa7-6415-4cac-acca-cf054d70cc87
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858615884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.858615884
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.341933564
Short name	T586
Test name
Test status
Simulation time	767636869 ps
CPU time	88.01 seconds
Started	Apr 02 12:52:33 PM PDT 24
Finished	Apr 02 12:54:01 PM PDT 24
Peak memory	206944 kb
Host	smart-8449df2d-ba9a-44e8-b81a-69fc6e957f74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=341933564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.341933564
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1075336067
Short name	T722
Test name
Test status
Simulation time	36287390834 ps
CPU time	227.54 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:56:26 PM PDT 24
Peak memory	206980 kb
Host	smart-26d471c0-1875-4041-a0b8-68dbd6a29331
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1075336067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1075336067
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1353025531
Short name	T517
Test name
Test status
Simulation time	329538508 ps
CPU time	77.82 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:53:50 PM PDT 24
Peak memory	207912 kb
Host	smart-8142816d-5792-4ee1-9b99-7d347c44a84f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1353025531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.1353025531
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3805861287
Short name	T400
Test name
Test status
Simulation time	625285335 ps
CPU time	151.72 seconds
Started	Apr 02 12:52:36 PM PDT 24
Finished	Apr 02 12:55:08 PM PDT 24
Peak memory	211124 kb
Host	smart-c608b6c9-c218-443a-b0a2-220587945dbe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3805861287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.3805861287
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1208839590
Short name	T715
Test name
Test status
Simulation time	46786832 ps
CPU time	8.08 seconds
Started	Apr 02 12:52:31 PM PDT 24
Finished	Apr 02 12:52:39 PM PDT 24
Peak memory	204868 kb
Host	smart-df8080fe-5253-4f7e-b980-a1697a049f86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1208839590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1208839590
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1986198297
Short name	T775
Test name
Test status
Simulation time	237907448 ps
CPU time	7.46 seconds
Started	Apr 02 12:52:37 PM PDT 24
Finished	Apr 02 12:52:45 PM PDT 24
Peak memory	203600 kb
Host	smart-2deb7c51-09a4-4084-869b-5ce95553ba83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1986198297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1986198297
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2484683303
Short name	T757
Test name
Test status
Simulation time	98319670788 ps
CPU time	517.18 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 01:01:16 PM PDT 24
Peak memory	207296 kb
Host	smart-933162bf-96c1-4af9-a35f-19135a6f5ad0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2484683303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2484683303
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1268275878
Short name	T464
Test name
Test status
Simulation time	39799479 ps
CPU time	4.48 seconds
Started	Apr 02 12:52:38 PM PDT 24
Finished	Apr 02 12:52:43 PM PDT 24
Peak memory	203648 kb
Host	smart-205d64f0-c23b-4e60-bcd9-5078f10f8f78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1268275878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1268275878
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.1194249667
Short name	T824
Test name
Test status
Simulation time	605514311 ps
CPU time	17.79 seconds
Started	Apr 02 12:52:37 PM PDT 24
Finished	Apr 02 12:52:56 PM PDT 24
Peak memory	203504 kb
Host	smart-6a692b1c-1911-4083-b112-dbd20e216ed4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1194249667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1194249667
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.178510619
Short name	T811
Test name
Test status
Simulation time	187283060 ps
CPU time	7.56 seconds
Started	Apr 02 12:52:34 PM PDT 24
Finished	Apr 02 12:52:42 PM PDT 24
Peak memory	204516 kb
Host	smart-b73721f9-c22c-4ad2-9f76-6151cab57d84
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=178510619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.178510619
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.989054661
Short name	T233
Test name
Test status
Simulation time	140690399228 ps
CPU time	174.01 seconds
Started	Apr 02 12:52:37 PM PDT 24
Finished	Apr 02 12:55:32 PM PDT 24
Peak memory	204780 kb
Host	smart-2e60ea68-2564-4a97-90ca-4cd468402d67
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=989054661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.989054661
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1859171542
Short name	T192
Test name
Test status
Simulation time	13730374951 ps
CPU time	108.99 seconds
Started	Apr 02 12:52:37 PM PDT 24
Finished	Apr 02 12:54:26 PM PDT 24
Peak memory	211736 kb
Host	smart-b3034149-cb34-40fe-bdb3-e07bf338777f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1859171542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1859171542
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2947466841
Short name	T431
Test name
Test status
Simulation time	77881193 ps
CPU time	2.56 seconds
Started	Apr 02 12:52:35 PM PDT 24
Finished	Apr 02 12:52:38 PM PDT 24
Peak memory	203684 kb
Host	smart-705ee89e-301a-4e5c-8d68-b226f28ad8db
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947466841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2947466841
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.1642631478
Short name	T10
Test name
Test status
Simulation time	597398062 ps
CPU time	19.59 seconds
Started	Apr 02 12:52:38 PM PDT 24
Finished	Apr 02 12:52:58 PM PDT 24
Peak memory	204196 kb
Host	smart-9d738f30-0412-4c94-b132-fb2558133a8e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642631478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1642631478
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.1956085390
Short name	T108
Test name
Test status
Simulation time	56558542 ps
CPU time	2.13 seconds
Started	Apr 02 12:52:38 PM PDT 24
Finished	Apr 02 12:52:40 PM PDT 24
Peak memory	203468 kb
Host	smart-cad1b6a1-093c-4d74-a9cd-966d4d478172
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1956085390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1956085390
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.213022354
Short name	T796
Test name
Test status
Simulation time	4407066715 ps
CPU time	27.59 seconds
Started	Apr 02 12:52:37 PM PDT 24
Finished	Apr 02 12:53:05 PM PDT 24
Peak memory	203564 kb
Host	smart-0e27130a-16be-4445-be66-745b847d9b8c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=213022354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.213022354
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3408152366
Short name	T606
Test name
Test status
Simulation time	6124657984 ps
CPU time	36.35 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:53:15 PM PDT 24
Peak memory	203496 kb
Host	smart-dd013ea9-7e5f-485c-9728-b4c21bc23fdc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3408152366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3408152366
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1483112128
Short name	T655
Test name
Test status
Simulation time	51225524 ps
CPU time	2.26 seconds
Started	Apr 02 12:52:34 PM PDT 24
Finished	Apr 02 12:52:37 PM PDT 24
Peak memory	203484 kb
Host	smart-42b46099-1cf9-4858-9c08-d22805dafbd7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483112128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1483112128
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.2674665749
Short name	T701
Test name
Test status
Simulation time	6834721529 ps
CPU time	129.03 seconds
Started	Apr 02 12:52:37 PM PDT 24
Finished	Apr 02 12:54:46 PM PDT 24
Peak memory	208416 kb
Host	smart-4a81db37-0f38-46ba-b5a4-106339444552
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2674665749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2674665749
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3372518453
Short name	T318
Test name
Test status
Simulation time	1077027697 ps
CPU time	116.77 seconds
Started	Apr 02 12:52:38 PM PDT 24
Finished	Apr 02 12:54:35 PM PDT 24
Peak memory	208600 kb
Host	smart-1794b83e-c115-4776-86b6-ed7fa0888d26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3372518453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3372518453
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2572693750
Short name	T607
Test name
Test status
Simulation time	3414261500 ps
CPU time	148.41 seconds
Started	Apr 02 12:52:39 PM PDT 24
Finished	Apr 02 12:55:08 PM PDT 24
Peak memory	208032 kb
Host	smart-1e3059a5-1e5e-4f6b-8f4a-ab52c698d140
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2572693750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.2572693750
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2660269455
Short name	T602
Test name
Test status
Simulation time	4785646167 ps
CPU time	347.37 seconds
Started	Apr 02 12:52:41 PM PDT 24
Finished	Apr 02 12:58:28 PM PDT 24
Peak memory	224328 kb
Host	smart-5ccc58f7-9d75-4a27-b84c-4863fcc886f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2660269455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2660269455
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3417249417
Short name	T716
Test name
Test status
Simulation time	397595099 ps
CPU time	6.31 seconds
Started	Apr 02 12:52:38 PM PDT 24
Finished	Apr 02 12:52:44 PM PDT 24
Peak memory	211700 kb
Host	smart-566edc76-4bb4-4119-9327-e66e65837980
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417249417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3417249417
Directory	/workspace/9.xbar_unmapped_addr/latest