Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1829	1			T1	19		T13	1		T17	4
all_values[1]	1807	1			T1	19		T13	2		T17	1
all_values[2]	1803	1			T1	15		T13	2		T17	2
all_values[3]	1768	1			T1	13		T13	3		T66	2
all_values[4]	1826	1			T1	11		T13	2		T17	1
all_values[5]	1811	1			T1	12		T66	2		T20	4
all_values[6]	1838	1			T1	12		T13	1		T17	1
all_values[7]	1767	1			T1	16		T17	1		T66	1
all_values[8]	1751	1			T1	14		T13	2		T66	2
all_values[9]	1822	1			T1	17		T17	2		T66	1
all_values[10]	1867	1			T1	13		T13	1		T17	1
all_values[11]	1759	1			T1	18		T17	1		T66	3
all_values[12]	1821	1			T1	19		T17	2		T66	1
all_values[13]	1804	1			T1	14		T13	3		T17	1
all_values[14]	1821	1			T1	11		T13	1		T66	3
all_values[15]	1801	1			T1	9		T17	1		T66	7
all_values[16]	1798	1			T1	15		T13	1		T17	2
all_values[17]	1725	1			T1	20		T13	1		T17	1
all_values[18]	1782	1			T1	11		T17	1		T66	2
all_values[19]	1808	1			T1	16		T13	4		T17	3
all_values[20]	1779	1			T1	16		T13	2		T66	3
all_values[21]	1822	1			T1	13		T13	1		T66	3
all_values[22]	1842	1			T1	11		T13	2		T17	1
all_values[23]	1762	1			T1	12		T13	1		T17	1
all_values[24]	1786	1			T1	18		T66	4		T20	5
all_values[25]	1809	1			T1	16		T17	1		T66	4
all_values[26]	1772	1			T1	9		T13	1		T17	2
all_values[27]	1734	1			T1	18		T17	1		T66	1
all_values[28]	1791	1			T1	11		T17	2		T66	1
all_values[29]	1821	1			T1	15		T13	2		T17	2
all_values[30]	1778	1			T1	16		T13	2		T17	1
all_values[31]	1889	1			T1	19		T13	2		T17	1
all_values[32]	1834	1			T1	14		T13	2		T66	1
all_values[33]	1858	1			T1	19		T17	1		T66	6
all_values[34]	1779	1			T1	13		T17	1		T20	5
all_values[35]	1740	1			T1	14		T66	2		T20	2
all_values[36]	1811	1			T1	12		T66	2		T21	8
all_values[37]	1819	1			T1	23		T13	1		T66	1
all_values[38]	1876	1			T1	16		T13	1		T66	7
all_values[39]	1806	1			T1	12		T13	1		T17	1
all_values[40]	1840	1			T1	17		T13	2		T66	5
all_values[41]	1771	1			T1	15		T17	1		T66	3
all_values[42]	1808	1			T1	14		T17	1		T66	7
all_values[43]	1774	1			T1	14		T17	1		T66	1
all_values[44]	1722	1			T1	20		T13	2		T17	2
all_values[45]	1794	1			T1	19		T13	2		T17	2
all_values[46]	1764	1			T1	13		T13	2		T17	1
all_values[47]	1786	1			T1	18		T13	1		T17	1
all_values[48]	1790	1			T1	14		T17	2		T66	4
all_values[49]	1868	1			T1	19		T13	3		T66	5
all_values[50]	1805	1			T1	11		T17	1		T66	2
all_values[51]	1783	1			T1	19		T17	2		T66	3
all_values[52]	1769	1			T1	13		T13	4		T17	1
all_values[53]	1804	1			T1	20		T17	2		T66	2
all_values[54]	1860	1			T1	19		T13	2		T17	2
all_values[55]	1788	1			T1	9		T66	1		T20	5
all_values[56]	1788	1			T1	11		T13	1		T17	2
all_values[57]	1727	1			T1	20		T17	2		T66	5
all_values[58]	1788	1			T1	10		T13	1		T17	2
all_values[59]	1821	1			T1	16		T13	1		T66	1
all_values[60]	1767	1			T1	15		T13	1		T17	3
all_values[61]	1771	1			T1	18		T13	4		T17	1
all_values[62]	1779	1			T1	14		T13	1		T17	1
all_values[63]	1860	1			T1	13		T17	1		T66	3