Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 489 1 T9 2 T15 1 T17 3
all_values[1] 523 1 T7 2 T9 3 T17 6
all_values[2] 554 1 T9 4 T17 3 T82 1
all_values[3] 534 1 T9 4 T17 4 T75 3
all_values[4] 485 1 T9 1 T17 5 T75 2
all_values[5] 485 1 T9 3 T15 1 T17 3
all_values[6] 513 1 T7 1 T9 3 T17 9
all_values[7] 549 1 T9 4 T17 4 T50 2
all_values[8] 539 1 T9 3 T17 7 T50 1
all_values[9] 512 1 T9 1 T15 2 T49 1
all_values[10] 477 1 T9 1 T15 1 T49 1
all_values[11] 506 1 T7 1 T9 4 T17 6
all_values[12] 505 1 T7 1 T9 2 T49 1
all_values[13] 507 1 T17 5 T75 1 T82 4
all_values[14] 522 1 T17 4 T50 1 T75 1
all_values[15] 485 1 T49 1 T17 7 T75 1
all_values[16] 563 1 T9 2 T15 1 T17 2
all_values[17] 499 1 T9 5 T15 1 T17 2
all_values[18] 534 1 T9 3 T17 2 T50 1
all_values[19] 489 1 T9 3 T17 5 T75 1
all_values[20] 488 1 T7 1 T9 2 T15 1
all_values[21] 501 1 T9 2 T15 1 T17 6
all_values[22] 495 1 T7 1 T9 3 T15 1
all_values[23] 471 1 T15 1 T17 6 T75 1

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