Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1673	1			T1	2		T3	2		T10	25
all_values[1]	1661	1			T1	3		T3	2		T10	21
all_values[2]	1648	1			T1	2		T3	2		T10	25
all_values[3]	1778	1			T1	1		T3	2		T10	31
all_values[4]	1742	1			T3	3		T10	27		T13	26
all_values[5]	1687	1			T1	1		T10	29		T13	20
all_values[6]	1634	1			T1	1		T3	2		T10	28
all_values[7]	1690	1			T3	1		T10	28		T13	30
all_values[8]	1682	1			T1	1		T10	41		T13	20
all_values[9]	1711	1			T1	2		T10	36		T13	25
all_values[10]	1669	1			T1	3		T3	2		T10	34
all_values[11]	1692	1			T1	1		T10	23		T13	37
all_values[12]	1714	1			T1	1		T3	2		T10	26
all_values[13]	1658	1			T1	2		T10	24		T13	22
all_values[14]	1635	1			T3	4		T10	32		T13	29
all_values[15]	1584	1			T3	1		T10	30		T13	33
all_values[16]	1671	1			T1	1		T3	1		T10	40
all_values[17]	1730	1			T10	33		T13	25		T15	1
all_values[18]	1680	1			T1	2		T3	1		T10	32
all_values[19]	1598	1			T1	2		T10	26		T13	21
all_values[20]	1643	1			T3	1		T10	34		T13	29
all_values[21]	1738	1			T1	1		T3	2		T10	34
all_values[22]	1645	1			T1	1		T3	2		T10	32
all_values[23]	1617	1			T1	2		T3	2		T10	34
all_values[24]	1649	1			T3	2		T10	21		T13	32
all_values[25]	1641	1			T1	2		T3	1		T10	39
all_values[26]	1658	1			T1	2		T10	26		T13	24
all_values[27]	1682	1			T1	1		T3	1		T10	25
all_values[28]	1669	1			T1	1		T3	1		T10	26
all_values[29]	1667	1			T1	2		T10	24		T13	25
all_values[30]	1727	1			T1	1		T3	3		T10	26
all_values[31]	1708	1			T1	1		T3	1		T10	25
all_values[32]	1665	1			T10	31		T13	28		T15	5
all_values[33]	1592	1			T1	3		T3	2		T10	31
all_values[34]	1734	1			T1	1		T10	30		T13	25
all_values[35]	1643	1			T1	3		T3	2		T10	24
all_values[36]	1695	1			T1	1		T10	28		T13	32
all_values[37]	1677	1			T1	1		T10	25		T13	27
all_values[38]	1675	1			T1	1		T10	23		T13	25
all_values[39]	1743	1			T1	1		T3	1		T10	29
all_values[40]	1690	1			T1	2		T10	33		T13	27
all_values[41]	1631	1			T1	3		T3	2		T10	22
all_values[42]	1661	1			T1	4		T10	34		T13	32
all_values[43]	1627	1			T1	2		T3	2		T10	32
all_values[44]	1636	1			T1	1		T3	5		T10	28
all_values[45]	1685	1			T3	1		T10	32		T13	32
all_values[46]	1727	1			T1	2		T3	2		T10	33
all_values[47]	1659	1			T1	1		T3	1		T10	25
all_values[48]	1656	1			T1	3		T3	1		T10	21
all_values[49]	1701	1			T1	1		T3	1		T10	21
all_values[50]	1663	1			T1	2		T3	1		T10	28
all_values[51]	1635	1			T1	1		T10	33		T13	34
all_values[52]	1682	1			T1	2		T3	2		T10	23
all_values[53]	1682	1			T1	1		T3	3		T10	29
all_values[54]	1695	1			T1	4		T10	26		T13	23
all_values[55]	1642	1			T1	1		T3	1		T10	22
all_values[56]	1618	1			T1	1		T3	2		T10	29
all_values[57]	1704	1			T1	3		T3	5		T10	27
all_values[58]	1602	1			T3	4		T10	33		T13	25
all_values[59]	1750	1			T1	3		T10	31		T13	22
all_values[60]	1632	1			T1	3		T3	2		T10	24
all_values[61]	1650	1			T1	2		T3	3		T10	25
all_values[62]	1684	1			T1	1		T3	1		T10	23
all_values[63]	1690	1			T1	2		T10	30		T13	22