Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1724	1			T7	1		T9	1		T11	4
all_values[1]	1681	1			T7	3		T9	4		T11	3
all_values[2]	1744	1			T7	2		T9	3		T11	4
all_values[3]	1671	1			T7	3		T11	2		T15	22
all_values[4]	1733	1			T7	5		T9	1		T11	4
all_values[5]	1728	1			T7	2		T9	4		T11	1
all_values[6]	1757	1			T9	1		T11	2		T15	20
all_values[7]	1749	1			T7	3		T9	1		T11	5
all_values[8]	1783	1			T7	2		T9	1		T11	1
all_values[9]	1755	1			T7	1		T9	2		T11	1
all_values[10]	1724	1			T7	4		T9	1		T11	1
all_values[11]	1648	1			T7	3		T9	1		T11	2
all_values[12]	1724	1			T7	5		T11	1		T15	33
all_values[13]	1697	1			T7	4		T9	2		T11	4
all_values[14]	1734	1			T7	3		T9	1		T11	5
all_values[15]	1759	1			T7	7		T9	3		T11	2
all_values[16]	1703	1			T11	1		T15	30		T30	3
all_values[17]	1710	1			T7	6		T11	1		T15	24
all_values[18]	1682	1			T7	2		T9	2		T11	2
all_values[19]	1760	1			T9	3		T11	1		T15	25
all_values[20]	1798	1			T7	4		T9	1		T11	1
all_values[21]	1783	1			T7	2		T9	1		T11	4
all_values[22]	1693	1			T7	3		T9	2		T11	3
all_values[23]	1704	1			T7	3		T9	2		T11	4
all_values[24]	1701	1			T7	3		T9	1		T11	1
all_values[25]	1725	1			T7	3		T9	1		T11	2
all_values[26]	1761	1			T7	5		T9	1		T11	3
all_values[27]	1752	1			T7	2		T9	1		T11	1
all_values[28]	1643	1			T7	5		T9	1		T11	2
all_values[29]	1713	1			T7	1		T11	1		T15	20
all_values[30]	1749	1			T9	1		T15	27		T30	2
all_values[31]	1689	1			T7	4		T9	1		T11	2
all_values[32]	1674	1			T7	3		T9	1		T11	1
all_values[33]	1710	1			T7	3		T9	1		T11	2
all_values[34]	1700	1			T11	2		T15	29		T30	2
all_values[35]	1756	1			T7	4		T15	22		T30	2
all_values[36]	1785	1			T7	3		T11	3		T15	24
all_values[37]	1629	1			T7	4		T9	3		T11	3
all_values[38]	1752	1			T7	2		T11	1		T15	27
all_values[39]	1645	1			T7	3		T9	2		T11	1
all_values[40]	1689	1			T9	1		T11	4		T15	18
all_values[41]	1758	1			T7	3		T9	3		T11	4
all_values[42]	1677	1			T7	4		T9	1		T11	1
all_values[43]	1754	1			T7	1		T9	1		T11	1
all_values[44]	1748	1			T7	2		T9	1		T11	4
all_values[45]	1712	1			T7	1		T9	1		T11	3
all_values[46]	1642	1			T7	4		T9	5		T11	2
all_values[47]	1731	1			T7	1		T9	1		T11	5
all_values[48]	1758	1			T7	4		T9	1		T11	3
all_values[49]	1792	1			T7	3		T9	1		T11	2
all_values[50]	1740	1			T7	1		T11	2		T15	23
all_values[51]	1722	1			T7	3		T9	3		T11	1
all_values[52]	1727	1			T7	3		T9	1		T11	1
all_values[53]	1669	1			T7	2		T9	1		T11	3
all_values[54]	1689	1			T11	1		T15	27		T30	3
all_values[55]	1689	1			T7	1		T9	1		T11	2
all_values[56]	1751	1			T7	2		T9	3		T15	25
all_values[57]	1731	1			T7	4		T9	1		T11	1
all_values[58]	1631	1			T7	2		T11	4		T15	21
all_values[59]	1756	1			T7	4		T9	2		T11	2
all_values[60]	1787	1			T7	4		T9	2		T11	3
all_values[61]	1768	1			T7	3		T9	3		T11	3
all_values[62]	1731	1			T7	3		T11	2		T15	21
all_values[63]	1777	1			T9	2		T11	3		T15	23