Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.04 99.26 89.02 98.80 95.90 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T763 /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4210107602 Apr 18 12:42:14 PM PDT 24 Apr 18 12:42:59 PM PDT 24 14505264283 ps
T764 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.4062308265 Apr 18 12:43:00 PM PDT 24 Apr 18 12:50:49 PM PDT 24 71143681935 ps
T765 /workspace/coverage/xbar_build_mode/17.xbar_error_random.976206596 Apr 18 12:41:47 PM PDT 24 Apr 18 12:41:58 PM PDT 24 306635661 ps
T766 /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2793790358 Apr 18 12:42:32 PM PDT 24 Apr 18 12:43:00 PM PDT 24 600185654 ps
T767 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3716783899 Apr 18 12:42:12 PM PDT 24 Apr 18 12:45:25 PM PDT 24 9557193498 ps
T768 /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3307603765 Apr 18 12:41:39 PM PDT 24 Apr 18 12:42:02 PM PDT 24 185074744 ps
T769 /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2038181046 Apr 18 12:42:12 PM PDT 24 Apr 18 12:42:36 PM PDT 24 6738818619 ps
T770 /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.945663717 Apr 18 12:41:45 PM PDT 24 Apr 18 12:44:50 PM PDT 24 38301592862 ps
T771 /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3450157300 Apr 18 12:42:00 PM PDT 24 Apr 18 12:52:09 PM PDT 24 132408991958 ps
T772 /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3777712789 Apr 18 12:42:59 PM PDT 24 Apr 18 12:43:49 PM PDT 24 651280649 ps
T773 /workspace/coverage/xbar_build_mode/24.xbar_error_random.3408052074 Apr 18 12:42:10 PM PDT 24 Apr 18 12:42:32 PM PDT 24 333764221 ps
T774 /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1561798941 Apr 18 12:42:41 PM PDT 24 Apr 18 12:43:11 PM PDT 24 6514139080 ps
T775 /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3750346607 Apr 18 12:42:12 PM PDT 24 Apr 18 12:44:11 PM PDT 24 14757561378 ps
T776 /workspace/coverage/xbar_build_mode/43.xbar_same_source.130453629 Apr 18 12:43:07 PM PDT 24 Apr 18 12:43:26 PM PDT 24 4624971970 ps
T777 /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.3997699521 Apr 18 12:41:49 PM PDT 24 Apr 18 12:42:38 PM PDT 24 725219226 ps
T778 /workspace/coverage/xbar_build_mode/26.xbar_smoke.3403248404 Apr 18 12:42:05 PM PDT 24 Apr 18 12:42:10 PM PDT 24 134385822 ps
T779 /workspace/coverage/xbar_build_mode/34.xbar_stress_all.388889615 Apr 18 12:42:30 PM PDT 24 Apr 18 12:42:51 PM PDT 24 110831159 ps
T780 /workspace/coverage/xbar_build_mode/6.xbar_random.2113903665 Apr 18 12:41:06 PM PDT 24 Apr 18 12:41:20 PM PDT 24 81087324 ps
T781 /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1355480953 Apr 18 12:42:25 PM PDT 24 Apr 18 12:44:21 PM PDT 24 1062986010 ps
T782 /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1248658864 Apr 18 12:41:59 PM PDT 24 Apr 18 12:43:19 PM PDT 24 654514945 ps
T783 /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1400751749 Apr 18 12:42:37 PM PDT 24 Apr 18 12:42:59 PM PDT 24 743362541 ps
T784 /workspace/coverage/xbar_build_mode/35.xbar_error_random.2033580092 Apr 18 12:42:41 PM PDT 24 Apr 18 12:42:53 PM PDT 24 108245648 ps
T785 /workspace/coverage/xbar_build_mode/44.xbar_smoke.1874114293 Apr 18 12:43:07 PM PDT 24 Apr 18 12:43:12 PM PDT 24 56720347 ps
T786 /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3778338087 Apr 18 12:42:47 PM PDT 24 Apr 18 12:42:59 PM PDT 24 90306594 ps
T787 /workspace/coverage/xbar_build_mode/22.xbar_smoke.590001884 Apr 18 12:42:22 PM PDT 24 Apr 18 12:42:25 PM PDT 24 34441402 ps
T788 /workspace/coverage/xbar_build_mode/48.xbar_same_source.105539209 Apr 18 12:43:19 PM PDT 24 Apr 18 12:43:29 PM PDT 24 139308864 ps
T789 /workspace/coverage/xbar_build_mode/33.xbar_stress_all.663493428 Apr 18 12:42:33 PM PDT 24 Apr 18 12:43:01 PM PDT 24 266025434 ps
T790 /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.630818316 Apr 18 12:43:16 PM PDT 24 Apr 18 12:43:49 PM PDT 24 5179324031 ps
T791 /workspace/coverage/xbar_build_mode/18.xbar_stress_all.4149165188 Apr 18 12:42:00 PM PDT 24 Apr 18 12:46:01 PM PDT 24 9681111458 ps
T792 /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1820045548 Apr 18 12:41:04 PM PDT 24 Apr 18 12:41:33 PM PDT 24 5811650478 ps
T793 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2514976243 Apr 18 12:43:00 PM PDT 24 Apr 18 12:43:25 PM PDT 24 3786425832 ps
T794 /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1889797265 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:57 PM PDT 24 31297828 ps
T795 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.284327355 Apr 18 12:42:27 PM PDT 24 Apr 18 12:43:01 PM PDT 24 603913575 ps
T796 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3509776302 Apr 18 12:42:41 PM PDT 24 Apr 18 12:43:19 PM PDT 24 22135169 ps
T797 /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.4225370168 Apr 18 12:41:53 PM PDT 24 Apr 18 12:42:11 PM PDT 24 1302726955 ps
T798 /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1357470145 Apr 18 12:42:33 PM PDT 24 Apr 18 12:42:59 PM PDT 24 7668085810 ps
T799 /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.291936253 Apr 18 12:43:00 PM PDT 24 Apr 18 12:43:20 PM PDT 24 459486643 ps
T800 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.4214818323 Apr 18 12:42:19 PM PDT 24 Apr 18 12:42:42 PM PDT 24 322547985 ps
T230 /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.299997417 Apr 18 12:42:44 PM PDT 24 Apr 18 12:45:50 PM PDT 24 21780710677 ps
T239 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3844836715 Apr 18 12:42:22 PM PDT 24 Apr 18 12:43:26 PM PDT 24 256509604 ps
T801 /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1963466595 Apr 18 12:42:43 PM PDT 24 Apr 18 12:46:41 PM PDT 24 41848771655 ps
T802 /workspace/coverage/xbar_build_mode/41.xbar_random.2267029756 Apr 18 12:42:58 PM PDT 24 Apr 18 12:43:05 PM PDT 24 142959599 ps
T803 /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2404949348 Apr 18 12:41:43 PM PDT 24 Apr 18 12:43:03 PM PDT 24 29288239463 ps
T804 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2581457606 Apr 18 12:41:54 PM PDT 24 Apr 18 12:48:37 PM PDT 24 3586091925 ps
T805 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1180041730 Apr 18 12:43:18 PM PDT 24 Apr 18 12:46:44 PM PDT 24 1286039932 ps
T153 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.475618050 Apr 18 12:43:17 PM PDT 24 Apr 18 12:54:22 PM PDT 24 300865550441 ps
T806 /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.4237039965 Apr 18 12:41:40 PM PDT 24 Apr 18 12:42:13 PM PDT 24 4806960629 ps
T807 /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.436836180 Apr 18 12:42:20 PM PDT 24 Apr 18 12:42:24 PM PDT 24 20494789 ps
T808 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2963574258 Apr 18 12:42:16 PM PDT 24 Apr 18 12:43:39 PM PDT 24 312473323 ps
T809 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.382040220 Apr 18 12:43:10 PM PDT 24 Apr 18 12:43:52 PM PDT 24 614920460 ps
T810 /workspace/coverage/xbar_build_mode/2.xbar_error_random.151479363 Apr 18 12:41:07 PM PDT 24 Apr 18 12:41:15 PM PDT 24 39404736 ps
T144 /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.699554558 Apr 18 12:41:10 PM PDT 24 Apr 18 12:42:10 PM PDT 24 1300927521 ps
T811 /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2796615174 Apr 18 12:42:47 PM PDT 24 Apr 18 12:43:12 PM PDT 24 3204238000 ps
T812 /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.4063648128 Apr 18 12:41:40 PM PDT 24 Apr 18 12:41:57 PM PDT 24 771907946 ps
T813 /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1440555 Apr 18 12:43:13 PM PDT 24 Apr 18 12:43:17 PM PDT 24 26412958 ps
T814 /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3270035170 Apr 18 12:42:58 PM PDT 24 Apr 18 12:43:02 PM PDT 24 35709305 ps
T28 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.778770268 Apr 18 12:41:11 PM PDT 24 Apr 18 12:44:46 PM PDT 24 1083142167 ps
T815 /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3141017773 Apr 18 12:41:39 PM PDT 24 Apr 18 12:42:26 PM PDT 24 1434109338 ps
T209 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2189185259 Apr 18 12:43:07 PM PDT 24 Apr 18 12:48:40 PM PDT 24 2172146623 ps
T816 /workspace/coverage/xbar_build_mode/22.xbar_same_source.1465522700 Apr 18 12:41:51 PM PDT 24 Apr 18 12:42:05 PM PDT 24 1162434826 ps
T817 /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2859080455 Apr 18 12:42:54 PM PDT 24 Apr 18 12:43:09 PM PDT 24 104469904 ps
T818 /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3888564291 Apr 18 12:43:20 PM PDT 24 Apr 18 12:43:50 PM PDT 24 1103459704 ps
T819 /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1607513950 Apr 18 12:41:35 PM PDT 24 Apr 18 12:41:41 PM PDT 24 38639668 ps
T820 /workspace/coverage/xbar_build_mode/10.xbar_random.2766149342 Apr 18 12:41:40 PM PDT 24 Apr 18 12:41:49 PM PDT 24 184614010 ps
T821 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1077482701 Apr 18 12:42:25 PM PDT 24 Apr 18 12:42:38 PM PDT 24 198400770 ps
T822 /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.4181153327 Apr 18 12:40:56 PM PDT 24 Apr 18 12:42:43 PM PDT 24 16455899611 ps
T823 /workspace/coverage/xbar_build_mode/27.xbar_error_random.95168321 Apr 18 12:42:16 PM PDT 24 Apr 18 12:42:19 PM PDT 24 18090085 ps
T824 /workspace/coverage/xbar_build_mode/41.xbar_stress_all.998880368 Apr 18 12:42:59 PM PDT 24 Apr 18 12:44:56 PM PDT 24 1692169891 ps
T825 /workspace/coverage/xbar_build_mode/32.xbar_smoke.223970720 Apr 18 12:42:25 PM PDT 24 Apr 18 12:42:31 PM PDT 24 1022947919 ps
T826 /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1251925618 Apr 18 12:41:58 PM PDT 24 Apr 18 12:42:02 PM PDT 24 40412089 ps
T827 /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2116378414 Apr 18 12:43:24 PM PDT 24 Apr 18 12:43:31 PM PDT 24 62908560 ps
T828 /workspace/coverage/xbar_build_mode/27.xbar_random.3080549932 Apr 18 12:42:17 PM PDT 24 Apr 18 12:42:29 PM PDT 24 202432978 ps
T829 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3538016629 Apr 18 12:42:15 PM PDT 24 Apr 18 12:42:37 PM PDT 24 232817204 ps
T830 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1266072578 Apr 18 12:41:15 PM PDT 24 Apr 18 12:42:02 PM PDT 24 1508219634 ps
T831 /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3670372587 Apr 18 12:42:15 PM PDT 24 Apr 18 12:42:55 PM PDT 24 8122835349 ps
T832 /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2286891356 Apr 18 12:42:17 PM PDT 24 Apr 18 12:42:38 PM PDT 24 305645728 ps
T833 /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3043256245 Apr 18 12:41:25 PM PDT 24 Apr 18 12:41:45 PM PDT 24 787386011 ps
T834 /workspace/coverage/xbar_build_mode/34.xbar_same_source.1012506930 Apr 18 12:42:35 PM PDT 24 Apr 18 12:42:40 PM PDT 24 51563298 ps
T835 /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2549277261 Apr 18 12:43:10 PM PDT 24 Apr 18 12:43:41 PM PDT 24 5163940084 ps
T836 /workspace/coverage/xbar_build_mode/25.xbar_smoke.609306651 Apr 18 12:42:05 PM PDT 24 Apr 18 12:42:10 PM PDT 24 189513947 ps
T837 /workspace/coverage/xbar_build_mode/6.xbar_smoke.2681827344 Apr 18 12:41:09 PM PDT 24 Apr 18 12:41:14 PM PDT 24 133738909 ps
T838 /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2583997092 Apr 18 12:42:21 PM PDT 24 Apr 18 12:42:50 PM PDT 24 6607108672 ps
T839 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3149100836 Apr 18 12:41:36 PM PDT 24 Apr 18 12:43:12 PM PDT 24 272723509 ps
T62 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1123398678 Apr 18 12:42:54 PM PDT 24 Apr 18 12:43:32 PM PDT 24 17682185575 ps
T840 /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3588658366 Apr 18 12:41:27 PM PDT 24 Apr 18 12:42:02 PM PDT 24 18354479433 ps
T841 /workspace/coverage/xbar_build_mode/32.xbar_random.4259723558 Apr 18 12:42:30 PM PDT 24 Apr 18 12:42:34 PM PDT 24 44536130 ps
T842 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3046887072 Apr 18 12:42:28 PM PDT 24 Apr 18 12:44:28 PM PDT 24 1403297379 ps
T843 /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2066542734 Apr 18 12:43:23 PM PDT 24 Apr 18 12:44:06 PM PDT 24 1357606255 ps
T844 /workspace/coverage/xbar_build_mode/13.xbar_same_source.2704721716 Apr 18 12:41:47 PM PDT 24 Apr 18 12:41:56 PM PDT 24 245781049 ps
T154 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2387047455 Apr 18 12:41:36 PM PDT 24 Apr 18 12:48:02 PM PDT 24 9543902835 ps
T845 /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2022640542 Apr 18 12:41:36 PM PDT 24 Apr 18 12:43:39 PM PDT 24 12546892310 ps
T846 /workspace/coverage/xbar_build_mode/22.xbar_stress_all.450573409 Apr 18 12:41:58 PM PDT 24 Apr 18 12:45:24 PM PDT 24 7850737953 ps
T847 /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1232499951 Apr 18 12:43:13 PM PDT 24 Apr 18 12:43:29 PM PDT 24 475818038 ps
T848 /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.284853343 Apr 18 12:41:06 PM PDT 24 Apr 18 12:41:10 PM PDT 24 89653866 ps
T849 /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.596572691 Apr 18 12:42:29 PM PDT 24 Apr 18 12:42:42 PM PDT 24 489861963 ps
T850 /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3674314110 Apr 18 12:43:09 PM PDT 24 Apr 18 12:43:28 PM PDT 24 439624618 ps
T851 /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2646013099 Apr 18 12:42:03 PM PDT 24 Apr 18 12:42:16 PM PDT 24 328006895 ps
T852 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2167730514 Apr 18 12:41:36 PM PDT 24 Apr 18 12:46:23 PM PDT 24 2409478206 ps
T145 /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.4171943147 Apr 18 12:41:54 PM PDT 24 Apr 18 12:42:36 PM PDT 24 4378919680 ps
T63 /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3907089158 Apr 18 12:42:20 PM PDT 24 Apr 18 12:45:39 PM PDT 24 41536723110 ps
T853 /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1998338236 Apr 18 12:43:13 PM PDT 24 Apr 18 12:43:22 PM PDT 24 255533562 ps
T854 /workspace/coverage/xbar_build_mode/20.xbar_stress_all.4080347842 Apr 18 12:41:54 PM PDT 24 Apr 18 12:42:48 PM PDT 24 2608010479 ps
T855 /workspace/coverage/xbar_build_mode/38.xbar_smoke.2094761074 Apr 18 12:42:47 PM PDT 24 Apr 18 12:42:50 PM PDT 24 52318945 ps
T856 /workspace/coverage/xbar_build_mode/35.xbar_stress_all.4268644626 Apr 18 12:42:33 PM PDT 24 Apr 18 12:42:52 PM PDT 24 115601898 ps
T857 /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3566257099 Apr 18 12:43:11 PM PDT 24 Apr 18 12:46:59 PM PDT 24 140315050696 ps
T858 /workspace/coverage/xbar_build_mode/0.xbar_random.2697819185 Apr 18 12:41:14 PM PDT 24 Apr 18 12:41:23 PM PDT 24 280109029 ps
T859 /workspace/coverage/xbar_build_mode/16.xbar_same_source.4202418492 Apr 18 12:41:52 PM PDT 24 Apr 18 12:42:09 PM PDT 24 330363709 ps
T38 /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2702181952 Apr 18 12:41:43 PM PDT 24 Apr 18 12:45:00 PM PDT 24 483567681 ps
T860 /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2681673847 Apr 18 12:41:44 PM PDT 24 Apr 18 12:42:20 PM PDT 24 11841508231 ps
T861 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.4041142416 Apr 18 12:43:21 PM PDT 24 Apr 18 12:43:54 PM PDT 24 7717653 ps
T862 /workspace/coverage/xbar_build_mode/8.xbar_smoke.4147457988 Apr 18 12:41:15 PM PDT 24 Apr 18 12:41:18 PM PDT 24 31906247 ps
T863 /workspace/coverage/xbar_build_mode/39.xbar_random.633581494 Apr 18 12:42:56 PM PDT 24 Apr 18 12:43:39 PM PDT 24 4894501171 ps
T864 /workspace/coverage/xbar_build_mode/19.xbar_smoke.2366056005 Apr 18 12:41:53 PM PDT 24 Apr 18 12:41:58 PM PDT 24 159204033 ps
T865 /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.424160328 Apr 18 12:42:12 PM PDT 24 Apr 18 12:42:24 PM PDT 24 442667546 ps
T866 /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1056175890 Apr 18 12:41:08 PM PDT 24 Apr 18 12:41:21 PM PDT 24 276803816 ps
T867 /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1039348773 Apr 18 12:42:16 PM PDT 24 Apr 18 12:42:20 PM PDT 24 34432760 ps
T868 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.848817908 Apr 18 12:41:21 PM PDT 24 Apr 18 12:44:00 PM PDT 24 11427977453 ps
T869 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1778727323 Apr 18 12:42:45 PM PDT 24 Apr 18 12:52:53 PM PDT 24 201248047378 ps
T870 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3429071740 Apr 18 12:42:13 PM PDT 24 Apr 18 12:45:03 PM PDT 24 3201376504 ps
T871 /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4057153793 Apr 18 12:43:17 PM PDT 24 Apr 18 12:44:51 PM PDT 24 1248832227 ps
T872 /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3069171647 Apr 18 12:41:46 PM PDT 24 Apr 18 12:41:55 PM PDT 24 168053230 ps
T873 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3891771616 Apr 18 12:43:07 PM PDT 24 Apr 18 12:48:46 PM PDT 24 2038353770 ps
T874 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.326815249 Apr 18 12:42:22 PM PDT 24 Apr 18 12:45:56 PM PDT 24 2292837974 ps
T875 /workspace/coverage/xbar_build_mode/21.xbar_random.3863622608 Apr 18 12:42:00 PM PDT 24 Apr 18 12:42:16 PM PDT 24 185118415 ps
T876 /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.483185181 Apr 18 12:42:34 PM PDT 24 Apr 18 12:43:04 PM PDT 24 4010828663 ps
T877 /workspace/coverage/xbar_build_mode/20.xbar_error_random.4079776548 Apr 18 12:41:56 PM PDT 24 Apr 18 12:42:22 PM PDT 24 784906382 ps
T878 /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3099005507 Apr 18 12:42:11 PM PDT 24 Apr 18 12:42:44 PM PDT 24 8338711708 ps
T879 /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1433594861 Apr 18 12:42:15 PM PDT 24 Apr 18 12:42:18 PM PDT 24 47141116 ps
T880 /workspace/coverage/xbar_build_mode/40.xbar_same_source.2331662573 Apr 18 12:42:59 PM PDT 24 Apr 18 12:43:19 PM PDT 24 1215763470 ps
T249 /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3490734119 Apr 18 12:42:07 PM PDT 24 Apr 18 12:42:20 PM PDT 24 347343419 ps
T881 /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2431778634 Apr 18 12:42:09 PM PDT 24 Apr 18 12:52:24 PM PDT 24 3146861810 ps
T882 /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3726994068 Apr 18 12:41:42 PM PDT 24 Apr 18 12:41:47 PM PDT 24 26429146 ps
T883 /workspace/coverage/xbar_build_mode/42.xbar_same_source.2397396550 Apr 18 12:43:01 PM PDT 24 Apr 18 12:43:26 PM PDT 24 1218309747 ps
T884 /workspace/coverage/xbar_build_mode/14.xbar_error_random.2062780270 Apr 18 12:41:41 PM PDT 24 Apr 18 12:42:01 PM PDT 24 787881187 ps
T885 /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.477129284 Apr 18 12:41:31 PM PDT 24 Apr 18 12:41:51 PM PDT 24 147308962 ps
T886 /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3456035698 Apr 18 12:41:16 PM PDT 24 Apr 18 12:41:46 PM PDT 24 5561754433 ps
T887 /workspace/coverage/xbar_build_mode/0.xbar_error_random.1014987190 Apr 18 12:41:06 PM PDT 24 Apr 18 12:41:21 PM PDT 24 671413181 ps
T888 /workspace/coverage/xbar_build_mode/31.xbar_same_source.1404599869 Apr 18 12:42:28 PM PDT 24 Apr 18 12:42:46 PM PDT 24 429283763 ps
T889 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2515796572 Apr 18 12:43:25 PM PDT 24 Apr 18 12:46:47 PM PDT 24 8115371845 ps
T890 /workspace/coverage/xbar_build_mode/11.xbar_random.3882700613 Apr 18 12:41:35 PM PDT 24 Apr 18 12:41:59 PM PDT 24 1023109297 ps
T891 /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.392284357 Apr 18 12:42:17 PM PDT 24 Apr 18 12:43:01 PM PDT 24 3335295860 ps
T892 /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.349296800 Apr 18 12:41:02 PM PDT 24 Apr 18 12:44:39 PM PDT 24 36505893593 ps
T893 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2399053768 Apr 18 12:43:22 PM PDT 24 Apr 18 12:43:32 PM PDT 24 197177068 ps
T894 /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3715416755 Apr 18 12:41:05 PM PDT 24 Apr 18 12:41:50 PM PDT 24 18289094949 ps
T895 /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1618189971 Apr 18 12:43:15 PM PDT 24 Apr 18 12:43:24 PM PDT 24 361522678 ps
T896 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2814452265 Apr 18 12:41:54 PM PDT 24 Apr 18 12:42:00 PM PDT 24 38110140 ps
T897 /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1857706887 Apr 18 12:41:50 PM PDT 24 Apr 18 12:43:35 PM PDT 24 735007858 ps
T898 /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2048137563 Apr 18 12:42:25 PM PDT 24 Apr 18 12:43:11 PM PDT 24 9816367446 ps
T899 /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3484156064 Apr 18 12:43:18 PM PDT 24 Apr 18 12:43:47 PM PDT 24 1140355008 ps
T900 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.4283116266 Apr 18 12:41:07 PM PDT 24 Apr 18 12:42:21 PM PDT 24 12764826297 ps

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2838254073
Short name T9
Test name
Test status
Simulation time 1403757520 ps
CPU time 49.35 seconds
Started Apr 18 12:41:33 PM PDT 24
Finished Apr 18 12:42:23 PM PDT 24
Peak memory 204584 kb
Host smart-74e1de72-ebe3-4f9e-b517-e43e5bd10993
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2838254073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2838254073
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.734751979
Short name T45
Test name
Test status
Simulation time 87385676596 ps
CPU time 613.66 seconds
Started Apr 18 12:43:45 PM PDT 24
Finished Apr 18 12:53:59 PM PDT 24
Peak memory 207352 kb
Host smart-1e3bacd5-1fc6-45a1-afdd-b0747ef984f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=734751979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo
w_rsp.734751979
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.371576144
Short name T17
Test name
Test status
Simulation time 62245405867 ps
CPU time 451.89 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:50:35 PM PDT 24
Peak memory 211688 kb
Host smart-0d49afa0-b393-436c-99f7-53833ba1454a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=371576144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo
w_rsp.371576144
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1843587262
Short name T245
Test name
Test status
Simulation time 10337881564 ps
CPU time 311.75 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:47:38 PM PDT 24
Peak memory 219836 kb
Host smart-db1cbb61-a142-4d7e-a90b-88efff992914
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1843587262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.1843587262
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.652540935
Short name T253
Test name
Test status
Simulation time 71503875810 ps
CPU time 350.21 seconds
Started Apr 18 12:41:55 PM PDT 24
Finished Apr 18 12:47:46 PM PDT 24
Peak memory 211608 kb
Host smart-70126c3b-0275-49ef-b0d9-f7d39bbb8cf4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=652540935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slo
w_rsp.652540935
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.473896840
Short name T14
Test name
Test status
Simulation time 3003334428 ps
CPU time 87.13 seconds
Started Apr 18 12:42:08 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 205736 kb
Host smart-240980f1-23ed-4df2-a8d4-45006fc2e7d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=473896840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.473896840
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.70911045
Short name T196
Test name
Test status
Simulation time 21347030861 ps
CPU time 195.3 seconds
Started Apr 18 12:42:28 PM PDT 24
Finished Apr 18 12:45:45 PM PDT 24
Peak memory 211556 kb
Host smart-cfe61db0-4bd9-4a07-a8ac-234ca85d11e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=70911045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow
_rsp.70911045
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3422725893
Short name T1
Test name
Test status
Simulation time 22790685001 ps
CPU time 129.78 seconds
Started Apr 18 12:40:56 PM PDT 24
Finished Apr 18 12:43:08 PM PDT 24
Peak memory 205132 kb
Host smart-ad0747bd-17cf-4da0-8bdc-84fa5b29bcdd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422725893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3422725893
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1318882376
Short name T80
Test name
Test status
Simulation time 6865657982 ps
CPU time 146.01 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:45:53 PM PDT 24
Peak memory 207024 kb
Host smart-b8b3c60e-3110-48a7-acf5-c24136546389
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1318882376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1318882376
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.662795484
Short name T125
Test name
Test status
Simulation time 10983268443 ps
CPU time 370.03 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:48:26 PM PDT 24
Peak memory 212444 kb
Host smart-83fb15a1-2bfa-427b-81fe-4efd695321c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=662795484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.662795484
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1053854751
Short name T19
Test name
Test status
Simulation time 25070962343 ps
CPU time 170.39 seconds
Started Apr 18 12:43:20 PM PDT 24
Finished Apr 18 12:46:11 PM PDT 24
Peak memory 211700 kb
Host smart-e4b92350-3fd0-4a46-98dd-c45a82ca1acb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1053854751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1053854751
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1733831835
Short name T26
Test name
Test status
Simulation time 620179372 ps
CPU time 191.09 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 211528 kb
Host smart-652a652a-775f-4ffb-9d63-ef76e3492025
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1733831835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.1733831835
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3940591263
Short name T86
Test name
Test status
Simulation time 3532126420 ps
CPU time 232.23 seconds
Started Apr 18 12:42:46 PM PDT 24
Finished Apr 18 12:46:39 PM PDT 24
Peak memory 209352 kb
Host smart-e2eb6d0c-bc7a-4884-8183-dd10a6c08bee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3940591263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.3940591263
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2458170594
Short name T21
Test name
Test status
Simulation time 68153676643 ps
CPU time 459.25 seconds
Started Apr 18 12:43:20 PM PDT 24
Finished Apr 18 12:51:00 PM PDT 24
Peak memory 211592 kb
Host smart-49ef3047-8520-4214-a9cc-c52342f06112
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2458170594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2458170594
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3889097047
Short name T25
Test name
Test status
Simulation time 392492950 ps
CPU time 144.42 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 210600 kb
Host smart-92bb9ddd-7d8e-4b28-9557-63593dffc8f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3889097047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.3889097047
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1910457382
Short name T15
Test name
Test status
Simulation time 1982423921 ps
CPU time 361.4 seconds
Started Apr 18 12:42:46 PM PDT 24
Finished Apr 18 12:48:48 PM PDT 24
Peak memory 208420 kb
Host smart-2689a7a2-2c87-4e94-9f6e-8994ee5f65fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1910457382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.1910457382
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1077792099
Short name T120
Test name
Test status
Simulation time 348350992350 ps
CPU time 549.63 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:50:04 PM PDT 24
Peak memory 211620 kb
Host smart-2add6631-3100-40c9-9c26-4c711b427386
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1077792099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.1077792099
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1698117779
Short name T35
Test name
Test status
Simulation time 6162116368 ps
CPU time 303.67 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:46:15 PM PDT 24
Peak memory 219248 kb
Host smart-45459c61-3739-46ca-9645-1eb499c819de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698117779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1698117779
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.777287591
Short name T4
Test name
Test status
Simulation time 537641597 ps
CPU time 133.12 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:44:00 PM PDT 24
Peak memory 209772 kb
Host smart-c87ce4be-e5e3-44a5-9aaa-cf30dd8e5425
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=777287591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res
et_error.777287591
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2578197614
Short name T37
Test name
Test status
Simulation time 6991409260 ps
CPU time 305.19 seconds
Started Apr 18 12:42:53 PM PDT 24
Finished Apr 18 12:47:58 PM PDT 24
Peak memory 210240 kb
Host smart-6a3fe5fd-5de9-47ea-8061-98e86d2b7802
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2578197614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.2578197614
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.1171907743
Short name T11
Test name
Test status
Simulation time 1769286340 ps
CPU time 24.93 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:33 PM PDT 24
Peak memory 203932 kb
Host smart-c82f4c4c-e49e-465e-b86f-384d98eeb896
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1171907743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1171907743
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.89565436
Short name T377
Test name
Test status
Simulation time 387309418 ps
CPU time 28.76 seconds
Started Apr 18 12:40:57 PM PDT 24
Finished Apr 18 12:41:27 PM PDT 24
Peak memory 206132 kb
Host smart-6341a9dc-9def-4c76-8a74-75c1b332719e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89565436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.89565436
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1278528224
Short name T703
Test name
Test status
Simulation time 91180985730 ps
CPU time 576.48 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:50:44 PM PDT 24
Peak memory 211640 kb
Host smart-605efb78-b3d2-4b70-b553-cee213a8556b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1278528224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.1278528224
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1617988933
Short name T433
Test name
Test status
Simulation time 80060281 ps
CPU time 10.43 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:16 PM PDT 24
Peak memory 203980 kb
Host smart-d7f005ca-cc3a-4887-8f2d-79eeb071ba8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1617988933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1617988933
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.1014987190
Short name T887
Test name
Test status
Simulation time 671413181 ps
CPU time 13.68 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:21 PM PDT 24
Peak memory 203336 kb
Host smart-2ca56cb0-29fa-40d3-a2ee-c020f00deba5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1014987190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1014987190
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.2697819185
Short name T858
Test name
Test status
Simulation time 280109029 ps
CPU time 8.43 seconds
Started Apr 18 12:41:14 PM PDT 24
Finished Apr 18 12:41:23 PM PDT 24
Peak memory 204576 kb
Host smart-51c916da-549f-492c-8925-3413aa348086
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2697819185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2697819185
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.4181153327
Short name T822
Test name
Test status
Simulation time 16455899611 ps
CPU time 105.88 seconds
Started Apr 18 12:40:56 PM PDT 24
Finished Apr 18 12:42:43 PM PDT 24
Peak memory 204640 kb
Host smart-2375f102-cf4b-4b3d-82de-b9530a1ad30b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181153327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.4181153327
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1687724933
Short name T64
Test name
Test status
Simulation time 51815300174 ps
CPU time 233.05 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:45:00 PM PDT 24
Peak memory 204724 kb
Host smart-96aa3f3e-2e72-44b4-b3fe-1958bd96e948
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1687724933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1687724933
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.43445135
Short name T180
Test name
Test status
Simulation time 430884328 ps
CPU time 16.12 seconds
Started Apr 18 12:41:08 PM PDT 24
Finished Apr 18 12:41:25 PM PDT 24
Peak memory 204960 kb
Host smart-7d0cd91b-8d03-435a-830d-30969ada2a79
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43445135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.43445135
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.1657070327
Short name T206
Test name
Test status
Simulation time 199525016 ps
CPU time 3.35 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:58 PM PDT 24
Peak memory 203364 kb
Host smart-6c6d59cc-fa40-45d5-80e4-1bdd5aa3b4b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1657070327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1657070327
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.382664755
Short name T283
Test name
Test status
Simulation time 15851105129 ps
CPU time 38.27 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:41:33 PM PDT 24
Peak memory 203416 kb
Host smart-b6ee51b7-ac7e-4444-bfe3-acd711f3e656
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=382664755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.382664755
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.606958073
Short name T382
Test name
Test status
Simulation time 3181492290 ps
CPU time 25.03 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:41:19 PM PDT 24
Peak memory 203440 kb
Host smart-b66b92cf-444f-4744-a1bb-989ceefdcb6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=606958073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.606958073
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1387028821
Short name T646
Test name
Test status
Simulation time 74495451 ps
CPU time 2.18 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:08 PM PDT 24
Peak memory 203420 kb
Host smart-0fca8a69-e5d5-4cec-8686-31f40bf970bf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387028821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1387028821
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.4078732926
Short name T539
Test name
Test status
Simulation time 7775321569 ps
CPU time 236.17 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:44:50 PM PDT 24
Peak memory 207412 kb
Host smart-57b9128f-5dad-4f02-868f-8460975eb9a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4078732926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4078732926
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1583752337
Short name T244
Test name
Test status
Simulation time 108391729 ps
CPU time 9.28 seconds
Started Apr 18 12:41:13 PM PDT 24
Finished Apr 18 12:41:23 PM PDT 24
Peak memory 203532 kb
Host smart-acc2db34-45c2-4d10-bc9d-46234ee3d075
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1583752337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1583752337
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1908087370
Short name T609
Test name
Test status
Simulation time 5749889836 ps
CPU time 322.91 seconds
Started Apr 18 12:41:04 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 208912 kb
Host smart-7f9693c9-6e53-447a-8162-0e813dabafd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1908087370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.1908087370
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.125733492
Short name T579
Test name
Test status
Simulation time 4166913833 ps
CPU time 369.75 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:47:05 PM PDT 24
Peak memory 224640 kb
Host smart-db0cce87-dd6b-4b70-a999-f09a4c3c0485
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=125733492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese
t_error.125733492
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3572748157
Short name T300
Test name
Test status
Simulation time 213489177 ps
CPU time 9.96 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:21 PM PDT 24
Peak memory 204744 kb
Host smart-5f5064f6-fd54-45c8-a80f-0678324d94d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3572748157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3572748157
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2979269939
Short name T124
Test name
Test status
Simulation time 1789183075 ps
CPU time 62.07 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:42:08 PM PDT 24
Peak memory 207056 kb
Host smart-b46e2557-0e57-4ad7-a9d5-3732788f8c3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2979269939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2979269939
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1919795232
Short name T390
Test name
Test status
Simulation time 812443364 ps
CPU time 29.33 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:35 PM PDT 24
Peak memory 203752 kb
Host smart-93e3ec73-b2bb-457f-9ef7-f0f3f1db1527
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1919795232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1919795232
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.497425628
Short name T430
Test name
Test status
Simulation time 1217145560 ps
CPU time 32.31 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:44 PM PDT 24
Peak memory 203560 kb
Host smart-2b7f79fb-9a06-4d6d-9b68-35c35a56072f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=497425628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.497425628
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.870310516
Short name T182
Test name
Test status
Simulation time 868209381 ps
CPU time 19.84 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:28 PM PDT 24
Peak memory 211624 kb
Host smart-b2edbfd2-4a4f-4f60-89e2-d3cd84a761f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=870310516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.870310516
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3639457099
Short name T111
Test name
Test status
Simulation time 37864837438 ps
CPU time 138.48 seconds
Started Apr 18 12:40:55 PM PDT 24
Finished Apr 18 12:43:15 PM PDT 24
Peak memory 204880 kb
Host smart-6c62c5b5-d802-4996-90bc-0485d8debc7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639457099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3639457099
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3861825534
Short name T174
Test name
Test status
Simulation time 44221967782 ps
CPU time 240.81 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 204812 kb
Host smart-1790657a-7de5-4c82-ae99-c1156373792d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3861825534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3861825534
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.4228278702
Short name T304
Test name
Test status
Simulation time 93433357 ps
CPU time 5.81 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:41:00 PM PDT 24
Peak memory 204668 kb
Host smart-35de9188-a3c2-44ac-90ed-40d92094a980
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228278702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.4228278702
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.721655291
Short name T705
Test name
Test status
Simulation time 2902233878 ps
CPU time 14.18 seconds
Started Apr 18 12:40:56 PM PDT 24
Finished Apr 18 12:41:12 PM PDT 24
Peak memory 204108 kb
Host smart-84e926b0-b817-461e-acb5-ab56e70afff3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=721655291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.721655291
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.740781609
Short name T252
Test name
Test status
Simulation time 303769278 ps
CPU time 3.67 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:10 PM PDT 24
Peak memory 203312 kb
Host smart-88a179fb-46e3-4dc6-adab-8ae916e29dea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=740781609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.740781609
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3550303294
Short name T605
Test name
Test status
Simulation time 9589972220 ps
CPU time 43.55 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:49 PM PDT 24
Peak memory 203456 kb
Host smart-b6872f0f-4708-4b2f-9c81-8d4af8651a3e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550303294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3550303294
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1820063897
Short name T415
Test name
Test status
Simulation time 4370422363 ps
CPU time 32.73 seconds
Started Apr 18 12:40:55 PM PDT 24
Finished Apr 18 12:41:33 PM PDT 24
Peak memory 204044 kb
Host smart-031323f4-00ce-4b52-887f-3ad365b79cb3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1820063897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1820063897
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.755395878
Short name T756
Test name
Test status
Simulation time 39943712 ps
CPU time 1.99 seconds
Started Apr 18 12:40:56 PM PDT 24
Finished Apr 18 12:40:59 PM PDT 24
Peak memory 203700 kb
Host smart-e5c87665-0b1c-4426-81df-d41c3df70267
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755395878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.755395878
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1943062567
Short name T187
Test name
Test status
Simulation time 1871762338 ps
CPU time 85.33 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:42:32 PM PDT 24
Peak memory 207280 kb
Host smart-194dea04-dc02-4e3c-ae6d-ab28b3319adb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1943062567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1943062567
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.4283116266
Short name T900
Test name
Test status
Simulation time 12764826297 ps
CPU time 73.07 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:42:21 PM PDT 24
Peak memory 206584 kb
Host smart-961d68f2-ef0c-46ba-9a62-fd4ebddbb223
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4283116266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4283116266
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3064604420
Short name T176
Test name
Test status
Simulation time 341647519 ps
CPU time 124.21 seconds
Started Apr 18 12:40:54 PM PDT 24
Finished Apr 18 12:43:00 PM PDT 24
Peak memory 208272 kb
Host smart-be2cf1be-afc2-4d6b-8e80-0b77bed6d2cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3064604420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.3064604420
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2787473929
Short name T577
Test name
Test status
Simulation time 14182145329 ps
CPU time 498.28 seconds
Started Apr 18 12:41:13 PM PDT 24
Finished Apr 18 12:49:32 PM PDT 24
Peak memory 219924 kb
Host smart-f32b4fa7-0da0-41ac-a5ca-ae52f297d737
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2787473929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.2787473929
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1028076148
Short name T20
Test name
Test status
Simulation time 265868461 ps
CPU time 23.26 seconds
Started Apr 18 12:40:55 PM PDT 24
Finished Apr 18 12:41:19 PM PDT 24
Peak memory 211564 kb
Host smart-8af50345-4f40-4921-9582-6c5c06d583e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1028076148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1028076148
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3545544599
Short name T147
Test name
Test status
Simulation time 66192143 ps
CPU time 3.43 seconds
Started Apr 18 12:41:28 PM PDT 24
Finished Apr 18 12:41:32 PM PDT 24
Peak memory 203452 kb
Host smart-1cb39da0-0bf2-453c-9f8e-81673a5fcb4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3545544599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3545544599
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.4071050548
Short name T140
Test name
Test status
Simulation time 206378432734 ps
CPU time 554.83 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:50:55 PM PDT 24
Peak memory 206132 kb
Host smart-faad12af-cba8-4c74-8cd3-bd8d3eee59d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4071050548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.4071050548
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1735104605
Short name T68
Test name
Test status
Simulation time 98985752 ps
CPU time 13.02 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:41:45 PM PDT 24
Peak memory 203636 kb
Host smart-cede4b6f-c7fe-44a9-9d6f-4914903f16ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1735104605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1735104605
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.1136652491
Short name T748
Test name
Test status
Simulation time 231041968 ps
CPU time 23.03 seconds
Started Apr 18 12:41:29 PM PDT 24
Finished Apr 18 12:41:53 PM PDT 24
Peak memory 203548 kb
Host smart-0026b6f0-48b8-4630-8b99-32cd801c4624
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1136652491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1136652491
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.2766149342
Short name T820
Test name
Test status
Simulation time 184614010 ps
CPU time 7.48 seconds
Started Apr 18 12:41:40 PM PDT 24
Finished Apr 18 12:41:49 PM PDT 24
Peak memory 204604 kb
Host smart-c6c3e725-7ebf-4330-b24c-7ace6929e0fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2766149342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2766149342
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1774580556
Short name T699
Test name
Test status
Simulation time 34494745935 ps
CPU time 154.66 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:44:06 PM PDT 24
Peak memory 211624 kb
Host smart-7c1fb99f-4464-4b46-b3f6-fbdbd51b51a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774580556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1774580556
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1348139413
Short name T128
Test name
Test status
Simulation time 34477859373 ps
CPU time 270.68 seconds
Started Apr 18 12:41:26 PM PDT 24
Finished Apr 18 12:45:58 PM PDT 24
Peak memory 211696 kb
Host smart-950db8fd-b67b-4c5d-b331-fa70ca068ae2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1348139413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1348139413
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3870082012
Short name T321
Test name
Test status
Simulation time 179745359 ps
CPU time 17.9 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:41:58 PM PDT 24
Peak memory 211592 kb
Host smart-79d5c343-3b72-4b61-80f7-cc608e1c0551
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870082012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3870082012
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.773131008
Short name T542
Test name
Test status
Simulation time 215186625 ps
CPU time 5.02 seconds
Started Apr 18 12:41:21 PM PDT 24
Finished Apr 18 12:41:26 PM PDT 24
Peak memory 204176 kb
Host smart-d9f5d8a9-2565-4735-b0fa-fda6036be099
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=773131008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.773131008
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.2784320763
Short name T749
Test name
Test status
Simulation time 118432322 ps
CPU time 3.4 seconds
Started Apr 18 12:41:19 PM PDT 24
Finished Apr 18 12:41:23 PM PDT 24
Peak memory 203488 kb
Host smart-44ffde36-de86-4eef-b60e-7b649332dc41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2784320763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2784320763
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3588658366
Short name T840
Test name
Test status
Simulation time 18354479433 ps
CPU time 34.5 seconds
Started Apr 18 12:41:27 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 203480 kb
Host smart-187a28bc-2fba-4bda-a156-40376133dd76
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588658366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3588658366
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3076194936
Short name T305
Test name
Test status
Simulation time 22701832642 ps
CPU time 41.62 seconds
Started Apr 18 12:41:28 PM PDT 24
Finished Apr 18 12:42:10 PM PDT 24
Peak memory 203428 kb
Host smart-2d799e1d-6112-45b9-b001-e9e3abcce115
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3076194936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3076194936
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.189315554
Short name T137
Test name
Test status
Simulation time 42323115 ps
CPU time 2.4 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:41:33 PM PDT 24
Peak memory 203416 kb
Host smart-0378f849-131d-433c-96d2-b282114e5b95
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189315554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.189315554
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.4234860059
Short name T400
Test name
Test status
Simulation time 1175369080 ps
CPU time 19.46 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:41:51 PM PDT 24
Peak memory 205616 kb
Host smart-d1bea904-b592-45b6-88b8-20de2e93723f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4234860059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4234860059
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3131240624
Short name T570
Test name
Test status
Simulation time 1232322654 ps
CPU time 173.27 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 209420 kb
Host smart-864e1d6a-4ead-40de-98be-0366675d1f26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3131240624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.3131240624
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3149100836
Short name T839
Test name
Test status
Simulation time 272723509 ps
CPU time 94.9 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:43:12 PM PDT 24
Peak memory 208956 kb
Host smart-7b112290-e8bd-486f-a41c-b41f5131fa00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3149100836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.3149100836
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.4063648128
Short name T812
Test name
Test status
Simulation time 771907946 ps
CPU time 15.53 seconds
Started Apr 18 12:41:40 PM PDT 24
Finished Apr 18 12:41:57 PM PDT 24
Peak memory 204884 kb
Host smart-23d047cf-5f35-464e-b51b-6b7097e12400
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4063648128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4063648128
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3141017773
Short name T815
Test name
Test status
Simulation time 1434109338 ps
CPU time 44.43 seconds
Started Apr 18 12:41:39 PM PDT 24
Finished Apr 18 12:42:26 PM PDT 24
Peak memory 205496 kb
Host smart-44319836-4130-4d18-9868-4dac93df324a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3141017773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3141017773
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.445050125
Short name T632
Test name
Test status
Simulation time 68750953264 ps
CPU time 488.64 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:49:44 PM PDT 24
Peak memory 211708 kb
Host smart-af448481-0fa5-44d3-a249-ff2a571ce998
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=445050125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo
w_rsp.445050125
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1639913297
Short name T659
Test name
Test status
Simulation time 1571926114 ps
CPU time 17 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:41:54 PM PDT 24
Peak memory 203424 kb
Host smart-fc88bff6-8e86-4f1b-a72f-b9e80e4bcb39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1639913297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1639913297
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.35673687
Short name T240
Test name
Test status
Simulation time 242995989 ps
CPU time 24.8 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 203504 kb
Host smart-05a777b2-838b-4649-ac2f-94e0b9a643ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35673687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.35673687
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.3882700613
Short name T890
Test name
Test status
Simulation time 1023109297 ps
CPU time 22.83 seconds
Started Apr 18 12:41:35 PM PDT 24
Finished Apr 18 12:41:59 PM PDT 24
Peak memory 204668 kb
Host smart-d84c5a21-f635-4cf5-98c9-514f99cff37c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3882700613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3882700613
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.664579091
Short name T631
Test name
Test status
Simulation time 123072195679 ps
CPU time 192.94 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 205652 kb
Host smart-0e9e2e1f-ef07-4feb-ab7d-2e03e84570f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=664579091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.664579091
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3465950411
Short name T447
Test name
Test status
Simulation time 42677276113 ps
CPU time 190.35 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:44:46 PM PDT 24
Peak memory 211704 kb
Host smart-8a03a3f0-da56-4fef-bc21-73f0bba77729
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3465950411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3465950411
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2033152813
Short name T207
Test name
Test status
Simulation time 110679205 ps
CPU time 11.84 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:41:54 PM PDT 24
Peak memory 204500 kb
Host smart-ce35a9da-893c-4b00-ad3d-34e4c00c5c3c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033152813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2033152813
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.3495051245
Short name T372
Test name
Test status
Simulation time 610842006 ps
CPU time 16.49 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:42:04 PM PDT 24
Peak memory 203476 kb
Host smart-0cc5c42f-77e0-4128-a530-10922e720f49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3495051245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3495051245
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.2617917737
Short name T501
Test name
Test status
Simulation time 272845314 ps
CPU time 3.91 seconds
Started Apr 18 12:41:32 PM PDT 24
Finished Apr 18 12:41:37 PM PDT 24
Peak memory 203368 kb
Host smart-9a2ac40f-27df-47e9-9bd0-f95bc022b784
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2617917737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2617917737
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.254335695
Short name T379
Test name
Test status
Simulation time 27426156495 ps
CPU time 39.63 seconds
Started Apr 18 12:41:37 PM PDT 24
Finished Apr 18 12:42:17 PM PDT 24
Peak memory 203520 kb
Host smart-7bbb57f8-05e1-465e-ac21-19279107a775
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=254335695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.254335695
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2456410243
Short name T636
Test name
Test status
Simulation time 6213406636 ps
CPU time 25.9 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:41:58 PM PDT 24
Peak memory 203376 kb
Host smart-825a00f9-99b0-4f89-b4cf-cd355228f919
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2456410243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2456410243
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.126073515
Short name T464
Test name
Test status
Simulation time 65926402 ps
CPU time 2.21 seconds
Started Apr 18 12:41:24 PM PDT 24
Finished Apr 18 12:41:28 PM PDT 24
Peak memory 203460 kb
Host smart-14358df1-5d9b-416b-a9b1-02cb4126813a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126073515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.126073515
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.865475098
Short name T197
Test name
Test status
Simulation time 400342168 ps
CPU time 35.99 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:42:08 PM PDT 24
Peak memory 206236 kb
Host smart-19962ad1-ea1a-42ca-9c3f-77792553667a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=865475098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.865475098
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.848817908
Short name T868
Test name
Test status
Simulation time 11427977453 ps
CPU time 158.46 seconds
Started Apr 18 12:41:21 PM PDT 24
Finished Apr 18 12:44:00 PM PDT 24
Peak memory 208280 kb
Host smart-e4532789-3e97-4bb8-aadb-e9cf2b9458f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=848817908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.848817908
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1657117171
Short name T580
Test name
Test status
Simulation time 849641152 ps
CPU time 145.93 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:44:01 PM PDT 24
Peak memory 208668 kb
Host smart-3fd21a2c-fd77-4de5-b808-91393575705e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1657117171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.1657117171
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3429999271
Short name T24
Test name
Test status
Simulation time 2457193371 ps
CPU time 370.14 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:47:42 PM PDT 24
Peak memory 219912 kb
Host smart-d482ae93-028f-49a4-a157-40cac372e780
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3429999271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.3429999271
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3139893088
Short name T179
Test name
Test status
Simulation time 154688287 ps
CPU time 20.67 seconds
Started Apr 18 12:41:35 PM PDT 24
Finished Apr 18 12:41:57 PM PDT 24
Peak memory 204936 kb
Host smart-880445b7-04d5-4e68-ab78-9f2e01611936
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3139893088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3139893088
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2116379119
Short name T701
Test name
Test status
Simulation time 221154959 ps
CPU time 12.33 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:41:44 PM PDT 24
Peak memory 204356 kb
Host smart-d8929ff2-a333-4dd0-a041-4461722aa534
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2116379119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2116379119
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2404949348
Short name T803
Test name
Test status
Simulation time 29288239463 ps
CPU time 79 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 211624 kb
Host smart-4f2178d3-69fb-4fe9-8440-abb324a07a56
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2404949348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.2404949348
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.134627643
Short name T550
Test name
Test status
Simulation time 1154873215 ps
CPU time 14.54 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:42:05 PM PDT 24
Peak memory 203504 kb
Host smart-2532b086-64de-4dce-a1a7-fd5ab0e7ff25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=134627643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.134627643
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.456037601
Short name T683
Test name
Test status
Simulation time 1091134898 ps
CPU time 27.01 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:42:11 PM PDT 24
Peak memory 203484 kb
Host smart-20cc3045-4427-4fd1-b7d6-24877188a06c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=456037601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.456037601
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.1576708727
Short name T73
Test name
Test status
Simulation time 380223722 ps
CPU time 15.58 seconds
Started Apr 18 12:41:37 PM PDT 24
Finished Apr 18 12:41:54 PM PDT 24
Peak memory 204484 kb
Host smart-4ac1aa8b-1d99-41c2-8f26-e0f80bd8bfc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1576708727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1576708727
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1720839757
Short name T164
Test name
Test status
Simulation time 149823766858 ps
CPU time 273.64 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:46:19 PM PDT 24
Peak memory 211732 kb
Host smart-e8b3646a-81c9-485d-8cc5-f8b15d7b96ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720839757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1720839757
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3526046171
Short name T621
Test name
Test status
Simulation time 38576490769 ps
CPU time 132.74 seconds
Started Apr 18 12:41:39 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 204752 kb
Host smart-9453518c-1cc1-4bd9-8539-2e701768d417
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3526046171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3526046171
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1549592231
Short name T559
Test name
Test status
Simulation time 86161321 ps
CPU time 10.98 seconds
Started Apr 18 12:41:33 PM PDT 24
Finished Apr 18 12:41:45 PM PDT 24
Peak memory 204508 kb
Host smart-fe0d9dff-2ac8-471a-8b70-4d6a8b5447b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549592231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1549592231
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.894689487
Short name T338
Test name
Test status
Simulation time 400756533 ps
CPU time 12.41 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:41:45 PM PDT 24
Peak memory 203424 kb
Host smart-fd04727c-a99a-4a26-a729-ab7c137b3d43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=894689487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.894689487
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.2779083963
Short name T364
Test name
Test status
Simulation time 125682937 ps
CPU time 3.23 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:41:38 PM PDT 24
Peak memory 203380 kb
Host smart-1296ea5e-0d91-44aa-a05f-33d8784cf19e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2779083963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2779083963
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1579960328
Short name T96
Test name
Test status
Simulation time 10351984642 ps
CPU time 35.05 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:42:07 PM PDT 24
Peak memory 203544 kb
Host smart-9966df0e-6697-4574-9615-7104d188d1ea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579960328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1579960328
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1166778129
Short name T742
Test name
Test status
Simulation time 10290378627 ps
CPU time 27.57 seconds
Started Apr 18 12:41:37 PM PDT 24
Finished Apr 18 12:42:06 PM PDT 24
Peak memory 203536 kb
Host smart-ed2d9af5-3536-49c4-bcee-4e46d39c4434
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1166778129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1166778129
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.4142723074
Short name T301
Test name
Test status
Simulation time 26601993 ps
CPU time 2.05 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:41:37 PM PDT 24
Peak memory 203368 kb
Host smart-8b7060e5-d2d8-45e2-a9ea-a0ebae727865
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142723074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.4142723074
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3046786736
Short name T143
Test name
Test status
Simulation time 3996567905 ps
CPU time 137.4 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:44:04 PM PDT 24
Peak memory 206588 kb
Host smart-34997f20-3528-45e1-92aa-5292e345b9f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3046786736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3046786736
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3571056322
Short name T132
Test name
Test status
Simulation time 291123147 ps
CPU time 6.32 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:41:42 PM PDT 24
Peak memory 203376 kb
Host smart-939e3a09-de59-4d33-b3a7-fb9dcc422a7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3571056322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3571056322
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3650827613
Short name T389
Test name
Test status
Simulation time 211647587 ps
CPU time 28.84 seconds
Started Apr 18 12:41:29 PM PDT 24
Finished Apr 18 12:41:59 PM PDT 24
Peak memory 206776 kb
Host smart-887e08a7-b1a2-4afc-baac-629294328e07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3650827613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.3650827613
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3275220736
Short name T497
Test name
Test status
Simulation time 1809305172 ps
CPU time 29.68 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:42:16 PM PDT 24
Peak memory 205268 kb
Host smart-e5717754-622c-464d-85b3-ec298d7ced54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3275220736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3275220736
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3002227759
Short name T706
Test name
Test status
Simulation time 51902800 ps
CPU time 6.73 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:41:49 PM PDT 24
Peak memory 203408 kb
Host smart-cc2a4953-9e9a-478f-942b-04211ab7b426
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3002227759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3002227759
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3485624909
Short name T123
Test name
Test status
Simulation time 110823549901 ps
CPU time 469.06 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:49:32 PM PDT 24
Peak memory 207028 kb
Host smart-e8e24d1e-2a27-4926-8d29-c27c4459eeff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3485624909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.3485624909
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1057233580
Short name T679
Test name
Test status
Simulation time 234965326 ps
CPU time 10.01 seconds
Started Apr 18 12:41:37 PM PDT 24
Finished Apr 18 12:41:48 PM PDT 24
Peak memory 203852 kb
Host smart-8eb780cf-6b9e-4120-b882-b24e73f6e1e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1057233580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1057233580
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.4014097724
Short name T320
Test name
Test status
Simulation time 50040790 ps
CPU time 5.6 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:41:52 PM PDT 24
Peak memory 203424 kb
Host smart-0762b319-f41a-41e3-8535-1391dfcff91d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4014097724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4014097724
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.3220409164
Short name T474
Test name
Test status
Simulation time 850539098 ps
CPU time 11.28 seconds
Started Apr 18 12:41:40 PM PDT 24
Finished Apr 18 12:41:53 PM PDT 24
Peak memory 204476 kb
Host smart-b52d867b-d5b0-4760-95cc-21577d182f79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3220409164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3220409164
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.1890944648
Short name T146
Test name
Test status
Simulation time 101150917419 ps
CPU time 145.28 seconds
Started Apr 18 12:41:37 PM PDT 24
Finished Apr 18 12:44:03 PM PDT 24
Peak memory 211704 kb
Host smart-1589ab5c-ec17-467c-abed-1c94c25b0e93
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890944648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1890944648
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2022640542
Short name T845
Test name
Test status
Simulation time 12546892310 ps
CPU time 122.21 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 211608 kb
Host smart-33e4f7ea-f72f-4a54-94a4-0b944c6ec229
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2022640542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2022640542
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.629499937
Short name T717
Test name
Test status
Simulation time 361972755 ps
CPU time 21.16 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:42:03 PM PDT 24
Peak memory 204616 kb
Host smart-1038b50a-976d-4f46-88b6-3e7395f46bc4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629499937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.629499937
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.2704721716
Short name T844
Test name
Test status
Simulation time 245781049 ps
CPU time 7.88 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:41:56 PM PDT 24
Peak memory 204024 kb
Host smart-9924315e-8a96-4c41-a17e-dbdde9a3fe0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2704721716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2704721716
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.4282814093
Short name T70
Test name
Test status
Simulation time 67560542 ps
CPU time 2.06 seconds
Started Apr 18 12:41:39 PM PDT 24
Finished Apr 18 12:41:44 PM PDT 24
Peak memory 203356 kb
Host smart-1961471f-3b73-4400-8199-ccf9aed30fb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4282814093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4282814093
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.192795443
Short name T692
Test name
Test status
Simulation time 6433405463 ps
CPU time 26.58 seconds
Started Apr 18 12:42:17 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 203416 kb
Host smart-5d23b04f-9b0b-4162-9f40-59ee0999865f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=192795443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.192795443
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.119520058
Short name T641
Test name
Test status
Simulation time 3417319337 ps
CPU time 30.45 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:42:28 PM PDT 24
Peak memory 203456 kb
Host smart-9ad62e10-f210-4e19-b408-bd82c127197d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=119520058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.119520058
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.396240190
Short name T193
Test name
Test status
Simulation time 77422190 ps
CPU time 2.09 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:41:46 PM PDT 24
Peak memory 203456 kb
Host smart-a377c48c-32d9-4e0a-a5fe-6334b68d0088
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396240190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.396240190
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1265043450
Short name T110
Test name
Test status
Simulation time 8919595461 ps
CPU time 166.33 seconds
Started Apr 18 12:41:39 PM PDT 24
Finished Apr 18 12:44:28 PM PDT 24
Peak memory 207816 kb
Host smart-9245c9c8-a44d-4ef4-aac8-ffb407b82b5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1265043450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1265043450
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1394530207
Short name T487
Test name
Test status
Simulation time 261958632 ps
CPU time 33.43 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:42:15 PM PDT 24
Peak memory 206024 kb
Host smart-02036d86-6143-46bb-bd65-1aa060c6e414
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394530207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1394530207
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2167730514
Short name T852
Test name
Test status
Simulation time 2409478206 ps
CPU time 286.08 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:46:23 PM PDT 24
Peak memory 210644 kb
Host smart-8f8919f5-217b-41ba-a493-0c5c413d1fb1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2167730514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.2167730514
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3880701681
Short name T685
Test name
Test status
Simulation time 52437259 ps
CPU time 8.97 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:41:53 PM PDT 24
Peak memory 204100 kb
Host smart-dd31b055-17ee-4277-8e52-a8145aad93e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3880701681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.3880701681
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2615705590
Short name T354
Test name
Test status
Simulation time 22357867 ps
CPU time 3.95 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:41:53 PM PDT 24
Peak memory 211572 kb
Host smart-602b2d0e-a1bf-429e-bbd7-247503690bd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2615705590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2615705590
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3905803778
Short name T546
Test name
Test status
Simulation time 479921116 ps
CPU time 19.43 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:41:54 PM PDT 24
Peak memory 211484 kb
Host smart-1260b279-2405-4521-889f-42fcb45d1fa9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3905803778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3905803778
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2474627338
Short name T121
Test name
Test status
Simulation time 38919956274 ps
CPU time 384.72 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:48:11 PM PDT 24
Peak memory 206928 kb
Host smart-93f2edab-b9a6-4e19-9b50-37742d9edfb1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2474627338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2474627338
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3562431119
Short name T256
Test name
Test status
Simulation time 3698689480 ps
CPU time 21.19 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:42:06 PM PDT 24
Peak memory 203412 kb
Host smart-4fbbea87-dff2-4a0c-8cb6-55a17766ecd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3562431119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3562431119
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.2062780270
Short name T884
Test name
Test status
Simulation time 787881187 ps
CPU time 18.44 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:42:01 PM PDT 24
Peak memory 203472 kb
Host smart-f0be8d83-0b7d-4e21-b157-84e6d5f06536
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2062780270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2062780270
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.2846542878
Short name T481
Test name
Test status
Simulation time 405406972 ps
CPU time 14.4 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:42:10 PM PDT 24
Peak memory 211516 kb
Host smart-10dc72ea-1ab4-4159-b0be-744197c16d96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2846542878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2846542878
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.125664906
Short name T755
Test name
Test status
Simulation time 21074753494 ps
CPU time 125.31 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:43:51 PM PDT 24
Peak memory 204896 kb
Host smart-476d6f8b-9fb5-4a43-a3d9-9051d56b40e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=125664906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.125664906
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.108406108
Short name T178
Test name
Test status
Simulation time 12675390423 ps
CPU time 81.84 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:43:22 PM PDT 24
Peak memory 211696 kb
Host smart-b9de199a-7a9b-4454-a133-d77938fb288c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=108406108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.108406108
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2227365990
Short name T564
Test name
Test status
Simulation time 300516566 ps
CPU time 20.12 seconds
Started Apr 18 12:41:39 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 204420 kb
Host smart-bae5fd12-d992-4e69-8961-7c3471d2e2a3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227365990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2227365990
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.4172594075
Short name T186
Test name
Test status
Simulation time 1534982277 ps
CPU time 22.17 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 204108 kb
Host smart-a64e6d4b-fa54-4683-bd3c-b65ac4f891da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4172594075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4172594075
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.2643569144
Short name T535
Test name
Test status
Simulation time 167217579 ps
CPU time 3.37 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:41:52 PM PDT 24
Peak memory 203380 kb
Host smart-fc4a79e4-1905-4f06-9f8f-7e12f878bc77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2643569144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2643569144
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.916324919
Short name T56
Test name
Test status
Simulation time 24084042387 ps
CPU time 43.14 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:42:21 PM PDT 24
Peak memory 203388 kb
Host smart-d91bfd4b-f2de-466c-b827-b06723fb7bed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=916324919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.916324919
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2681673847
Short name T860
Test name
Test status
Simulation time 11841508231 ps
CPU time 34.31 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:42:20 PM PDT 24
Peak memory 203504 kb
Host smart-14b12176-4292-4017-b28d-423cd0dbede7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2681673847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2681673847
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2885002868
Short name T397
Test name
Test status
Simulation time 76863013 ps
CPU time 2 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:41:49 PM PDT 24
Peak memory 203352 kb
Host smart-021b1090-4b05-4fbb-b4c7-d7d9896d59fe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885002868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2885002868
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3335589570
Short name T204
Test name
Test status
Simulation time 720351023 ps
CPU time 63.9 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:42:44 PM PDT 24
Peak memory 206140 kb
Host smart-a5cbb4d8-7b71-4c9d-adda-3ee4fb2dbd88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3335589570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3335589570
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.353343866
Short name T396
Test name
Test status
Simulation time 1037354262 ps
CPU time 13.49 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:41:51 PM PDT 24
Peak memory 203548 kb
Host smart-7c24e25e-6f58-41fb-baba-193da3d901de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=353343866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.353343866
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2387047455
Short name T154
Test name
Test status
Simulation time 9543902835 ps
CPU time 384.38 seconds
Started Apr 18 12:41:36 PM PDT 24
Finished Apr 18 12:48:02 PM PDT 24
Peak memory 210596 kb
Host smart-884685af-3156-4436-b845-c52f65211445
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2387047455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.2387047455
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.516037113
Short name T445
Test name
Test status
Simulation time 111358473 ps
CPU time 12.02 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:41:58 PM PDT 24
Peak memory 204708 kb
Host smart-dfbb01f8-dcea-48d8-a37a-d595363943db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=516037113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.516037113
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.4171943147
Short name T145
Test name
Test status
Simulation time 4378919680 ps
CPU time 41.33 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:42:36 PM PDT 24
Peak memory 204956 kb
Host smart-3dffa490-f3e5-45d7-9bf4-02e81264ce79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4171943147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.4171943147
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2616664853
Short name T615
Test name
Test status
Simulation time 33805243502 ps
CPU time 202.58 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:45:07 PM PDT 24
Peak memory 205884 kb
Host smart-f6797816-f95e-46f8-8c7c-d50a7e7e2dea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2616664853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.2616664853
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2597766838
Short name T498
Test name
Test status
Simulation time 438166869 ps
CPU time 19.04 seconds
Started Apr 18 12:41:48 PM PDT 24
Finished Apr 18 12:42:09 PM PDT 24
Peak memory 203976 kb
Host smart-8214eaf0-06d0-4f1b-a1ac-aaacfb8dd52d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2597766838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2597766838
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.3169969858
Short name T707
Test name
Test status
Simulation time 437900959 ps
CPU time 3.84 seconds
Started Apr 18 12:41:35 PM PDT 24
Finished Apr 18 12:41:40 PM PDT 24
Peak memory 203388 kb
Host smart-73a5dc78-8b93-43f9-9cb5-9d2e09de6f9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3169969858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3169969858
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.953083963
Short name T734
Test name
Test status
Simulation time 435955670 ps
CPU time 20.84 seconds
Started Apr 18 12:41:52 PM PDT 24
Finished Apr 18 12:42:14 PM PDT 24
Peak memory 211556 kb
Host smart-e9694b55-a6c4-440c-8f06-e84896666007
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=953083963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.953083963
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2256840058
Short name T102
Test name
Test status
Simulation time 51831693387 ps
CPU time 179.96 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 204840 kb
Host smart-97441949-3ccb-44cd-a030-cdd45fb64a07
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256840058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2256840058
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.698861873
Short name T302
Test name
Test status
Simulation time 12351266366 ps
CPU time 82.3 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 211572 kb
Host smart-2488763c-2161-4427-81aa-8e2da03b3a78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=698861873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.698861873
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2655163643
Short name T738
Test name
Test status
Simulation time 55430765 ps
CPU time 2.2 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:41:44 PM PDT 24
Peak memory 203756 kb
Host smart-711d7378-398c-42d3-9c89-f44993042999
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655163643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2655163643
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.3549604230
Short name T554
Test name
Test status
Simulation time 928913692 ps
CPU time 16.68 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 204120 kb
Host smart-e01f0a9a-d473-4c96-8e14-2c7e03f4f303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549604230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3549604230
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.1177084425
Short name T362
Test name
Test status
Simulation time 245353906 ps
CPU time 3.36 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:41:46 PM PDT 24
Peak memory 203488 kb
Host smart-a07d4b91-0187-4bfe-8560-addd3a2cd151
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1177084425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1177084425
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3961403411
Short name T482
Test name
Test status
Simulation time 4026271746 ps
CPU time 25.8 seconds
Started Apr 18 12:41:33 PM PDT 24
Finished Apr 18 12:42:00 PM PDT 24
Peak memory 203480 kb
Host smart-1a1662d9-5d93-4be0-9da2-b492b47e5c0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961403411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3961403411
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2066945079
Short name T250
Test name
Test status
Simulation time 8124677608 ps
CPU time 28.43 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:42:14 PM PDT 24
Peak memory 203396 kb
Host smart-6c404fef-6dde-4b16-8581-7fd893e49cd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2066945079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2066945079
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3341786622
Short name T740
Test name
Test status
Simulation time 40450832 ps
CPU time 2.34 seconds
Started Apr 18 12:41:48 PM PDT 24
Finished Apr 18 12:41:52 PM PDT 24
Peak memory 203436 kb
Host smart-fc95e2a6-3c60-419c-b3b4-9f8c6ffef782
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341786622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3341786622
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.3151442753
Short name T71
Test name
Test status
Simulation time 1957148445 ps
CPU time 100.32 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 207780 kb
Host smart-6fd6c0a5-516d-4c90-89ee-ddfc936472ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3151442753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3151442753
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3716783899
Short name T767
Test name
Test status
Simulation time 9557193498 ps
CPU time 192.1 seconds
Started Apr 18 12:42:12 PM PDT 24
Finished Apr 18 12:45:25 PM PDT 24
Peak memory 206732 kb
Host smart-8b1c86d5-08c2-4d6c-8338-067e7d00bc49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3716783899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3716783899
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2321269144
Short name T331
Test name
Test status
Simulation time 732882550 ps
CPU time 122.31 seconds
Started Apr 18 12:41:55 PM PDT 24
Finished Apr 18 12:43:59 PM PDT 24
Peak memory 209296 kb
Host smart-da375d73-bcda-43a8-858d-52daec193ece
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2321269144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.2321269144
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.855433540
Short name T221
Test name
Test status
Simulation time 1767872748 ps
CPU time 65.51 seconds
Started Apr 18 12:41:49 PM PDT 24
Finished Apr 18 12:42:56 PM PDT 24
Peak memory 205816 kb
Host smart-d85d16df-b98e-49d4-9f06-15b7fad147a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=855433540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res
et_error.855433540
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3074312620
Short name T629
Test name
Test status
Simulation time 3015654920 ps
CPU time 20.39 seconds
Started Apr 18 12:41:40 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 211568 kb
Host smart-ee6c1c18-05b2-483b-a6ef-a258757025c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3074312620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3074312620
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.744574462
Short name T51
Test name
Test status
Simulation time 2655441256 ps
CPU time 53.76 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 206464 kb
Host smart-a6094bd4-ec99-460b-a6c3-1e5d5b7783e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=744574462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.744574462
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3247601313
Short name T653
Test name
Test status
Simulation time 100913323756 ps
CPU time 284.31 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 206792 kb
Host smart-ed06ed30-31bc-4692-9500-5c1c08accf55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3247601313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.3247601313
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2074552970
Short name T101
Test name
Test status
Simulation time 203465716 ps
CPU time 3.57 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:41:48 PM PDT 24
Peak memory 203392 kb
Host smart-dafebb75-bc45-43f4-9ab4-744b2b920836
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2074552970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2074552970
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.246103093
Short name T363
Test name
Test status
Simulation time 2288090084 ps
CPU time 27.59 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:42:14 PM PDT 24
Peak memory 203564 kb
Host smart-d0e16863-53ed-4884-b153-8dc46a5d3c67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=246103093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.246103093
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.2975566963
Short name T359
Test name
Test status
Simulation time 381188346 ps
CPU time 12.27 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:41:56 PM PDT 24
Peak memory 204344 kb
Host smart-dc5c816a-ea78-4041-b216-2f5c2d232846
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2975566963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2975566963
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2316082359
Short name T429
Test name
Test status
Simulation time 18153456120 ps
CPU time 99.58 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 205020 kb
Host smart-4b65c869-5354-4707-8019-1af118cc0532
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316082359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2316082359
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3813444538
Short name T201
Test name
Test status
Simulation time 101433411042 ps
CPU time 255.19 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:46:09 PM PDT 24
Peak memory 211556 kb
Host smart-852113a9-1f7b-44f3-84f1-b1c8aaf9cb98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3813444538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3813444538
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3110153249
Short name T423
Test name
Test status
Simulation time 970346855 ps
CPU time 22.27 seconds
Started Apr 18 12:41:49 PM PDT 24
Finished Apr 18 12:42:12 PM PDT 24
Peak memory 204484 kb
Host smart-53f51843-3257-4f9d-8361-00bf2a285b99
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110153249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3110153249
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.4202418492
Short name T859
Test name
Test status
Simulation time 330363709 ps
CPU time 15.68 seconds
Started Apr 18 12:41:52 PM PDT 24
Finished Apr 18 12:42:09 PM PDT 24
Peak memory 204084 kb
Host smart-bf2302d6-4365-47f0-b9d8-24238ee8d723
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4202418492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4202418492
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.4086939701
Short name T714
Test name
Test status
Simulation time 35665440 ps
CPU time 2.56 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:41:49 PM PDT 24
Peak memory 203384 kb
Host smart-8e5f7baa-bc26-470b-ac3a-23c4caedb5ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4086939701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.4086939701
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2342145983
Short name T330
Test name
Test status
Simulation time 7213997422 ps
CPU time 39.22 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:42:23 PM PDT 24
Peak memory 203540 kb
Host smart-78c25414-6a47-410c-a562-44425f85a008
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342145983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2342145983
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2954204892
Short name T214
Test name
Test status
Simulation time 5040682700 ps
CPU time 29.78 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 203764 kb
Host smart-553afd1f-6aaa-4db4-b5b6-023a85294520
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2954204892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2954204892
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2449822705
Short name T260
Test name
Test status
Simulation time 30073118 ps
CPU time 2.31 seconds
Started Apr 18 12:42:07 PM PDT 24
Finished Apr 18 12:42:11 PM PDT 24
Peak memory 203424 kb
Host smart-08bae138-ecfd-4e56-a84b-473c4027d0f2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449822705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2449822705
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3933618688
Short name T759
Test name
Test status
Simulation time 3372361877 ps
CPU time 83.27 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:43:09 PM PDT 24
Peak memory 207768 kb
Host smart-4d63bec2-abf4-4d50-b76b-2b3d9f97ef1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3933618688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3933618688
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1288040823
Short name T673
Test name
Test status
Simulation time 4498809708 ps
CPU time 93.58 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:43:20 PM PDT 24
Peak memory 207844 kb
Host smart-cdcde5ae-f324-4e80-b098-ff0ce85914b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1288040823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1288040823
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3256524162
Short name T438
Test name
Test status
Simulation time 4554342767 ps
CPU time 73.77 seconds
Started Apr 18 12:41:51 PM PDT 24
Finished Apr 18 12:43:07 PM PDT 24
Peak memory 206732 kb
Host smart-2af3b63f-2dba-467a-95fe-2bbccf83f550
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3256524162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.3256524162
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1376890376
Short name T34
Test name
Test status
Simulation time 798832978 ps
CPU time 168.3 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:44:37 PM PDT 24
Peak memory 210788 kb
Host smart-50ccb995-17ee-42d9-8320-cb2fa2fdd7db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1376890376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.1376890376
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1233147787
Short name T434
Test name
Test status
Simulation time 1409830187 ps
CPU time 16.82 seconds
Started Apr 18 12:41:57 PM PDT 24
Finished Apr 18 12:42:15 PM PDT 24
Peak memory 205000 kb
Host smart-a5ecb79a-be90-45c4-8e41-867603bb0e9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1233147787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1233147787
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3998788972
Short name T94
Test name
Test status
Simulation time 133943368 ps
CPU time 3.77 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:41:52 PM PDT 24
Peak memory 203652 kb
Host smart-ff9a6248-b72e-4ab6-b9bf-fce800479e9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3998788972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3998788972
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1482092223
Short name T13
Test name
Test status
Simulation time 1962481728 ps
CPU time 29.04 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:42:16 PM PDT 24
Peak memory 204036 kb
Host smart-3fce2575-2bfd-4e0c-907f-bad7f5b7f284
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1482092223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1482092223
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.976206596
Short name T765
Test name
Test status
Simulation time 306635661 ps
CPU time 9.57 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:41:58 PM PDT 24
Peak memory 203380 kb
Host smart-ae00c37f-593b-4398-b1c4-5970f0354efa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976206596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.976206596
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.1374210666
Short name T688
Test name
Test status
Simulation time 147862071 ps
CPU time 11.11 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:42:00 PM PDT 24
Peak memory 204560 kb
Host smart-d14620af-271e-4087-9339-020b05c512e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1374210666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1374210666
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2491630142
Short name T105
Test name
Test status
Simulation time 36584114512 ps
CPU time 222.37 seconds
Started Apr 18 12:42:03 PM PDT 24
Finished Apr 18 12:45:47 PM PDT 24
Peak memory 205436 kb
Host smart-2847dc30-aedb-450e-af1a-577eb2e2c112
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491630142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2491630142
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2184712961
Short name T532
Test name
Test status
Simulation time 14635081155 ps
CPU time 33.49 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:42:19 PM PDT 24
Peak memory 211744 kb
Host smart-1b6a8cdb-de1e-4a19-aed0-08100e91aa98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2184712961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2184712961
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3307603765
Short name T768
Test name
Test status
Simulation time 185074744 ps
CPU time 20.23 seconds
Started Apr 18 12:41:39 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 211496 kb
Host smart-796451e7-856e-41d5-85d8-277389eb8c5c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307603765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3307603765
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.2791735129
Short name T263
Test name
Test status
Simulation time 842995607 ps
CPU time 17.77 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:42:20 PM PDT 24
Peak memory 204008 kb
Host smart-ce2dcd38-71d6-43db-b663-0dbcb101d84e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2791735129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2791735129
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.4173702782
Short name T5
Test name
Test status
Simulation time 23325633 ps
CPU time 1.93 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:41:45 PM PDT 24
Peak memory 203480 kb
Host smart-b9259d5f-e510-43c9-aa6a-24dc61d5aa43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4173702782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.4173702782
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3099005507
Short name T878
Test name
Test status
Simulation time 8338711708 ps
CPU time 31.54 seconds
Started Apr 18 12:42:11 PM PDT 24
Finished Apr 18 12:42:44 PM PDT 24
Peak memory 203468 kb
Host smart-f51a2caa-f6ab-4bde-928d-d94c0b9eaeba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099005507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3099005507
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2035256495
Short name T6
Test name
Test status
Simulation time 2698793344 ps
CPU time 23.8 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:42:35 PM PDT 24
Peak memory 203532 kb
Host smart-9e359a68-f9b5-4e92-b05a-7877135fe695
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2035256495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2035256495
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.304769155
Short name T737
Test name
Test status
Simulation time 26498435 ps
CPU time 2.21 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:41:47 PM PDT 24
Peak memory 203404 kb
Host smart-c702a084-f5ef-4bf9-988a-feefde3b9e43
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304769155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.304769155
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3340096289
Short name T585
Test name
Test status
Simulation time 2447890931 ps
CPU time 147.41 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 211752 kb
Host smart-23456b8d-414c-45d6-adc6-c8344c0fe969
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3340096289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3340096289
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.682328490
Short name T757
Test name
Test status
Simulation time 6785991 ps
CPU time 0.81 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:41:50 PM PDT 24
Peak memory 195140 kb
Host smart-dcca44d8-3a07-486c-b8bd-094456e7c09c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=682328490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.682328490
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2767550575
Short name T523
Test name
Test status
Simulation time 496353914 ps
CPU time 174.74 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:44:53 PM PDT 24
Peak memory 208288 kb
Host smart-4f3244a9-86ca-45e0-8fb4-d21365c61d89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2767550575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.2767550575
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2799235699
Short name T32
Test name
Test status
Simulation time 123005370 ps
CPU time 33.24 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:42:27 PM PDT 24
Peak memory 206292 kb
Host smart-f55bf92d-3101-46db-bf34-a9b3645c9ad4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2799235699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.2799235699
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3069171647
Short name T872
Test name
Test status
Simulation time 168053230 ps
CPU time 6.94 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:41:55 PM PDT 24
Peak memory 204924 kb
Host smart-c00da22b-efc7-4616-a33d-371390727491
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3069171647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3069171647
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3740420044
Short name T623
Test name
Test status
Simulation time 2590086660 ps
CPU time 40.76 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:42:27 PM PDT 24
Peak memory 205624 kb
Host smart-94ad46d3-818e-4c5c-adba-db7d178a9973
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3740420044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3740420044
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.430484219
Short name T130
Test name
Test status
Simulation time 21294154873 ps
CPU time 119.97 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:43:40 PM PDT 24
Peak memory 204800 kb
Host smart-e16d97c8-9467-45bf-81bf-aa75bc83f38f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=430484219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo
w_rsp.430484219
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1125061528
Short name T3
Test name
Test status
Simulation time 163971281 ps
CPU time 19.25 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:42:07 PM PDT 24
Peak memory 204256 kb
Host smart-0212555e-301b-4080-8513-dcf27ef38fa6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1125061528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1125061528
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.3670105910
Short name T374
Test name
Test status
Simulation time 86646043 ps
CPU time 2.86 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:41:50 PM PDT 24
Peak memory 203496 kb
Host smart-2e2afccb-b77d-4c8e-8c6c-2f0efb8fce50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3670105910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3670105910
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.3299832763
Short name T87
Test name
Test status
Simulation time 957582606 ps
CPU time 25.23 seconds
Started Apr 18 12:41:39 PM PDT 24
Finished Apr 18 12:42:12 PM PDT 24
Peak memory 204636 kb
Host smart-cc69e0a9-6a62-4e12-a2da-ec7cdf03c94a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3299832763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3299832763
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.926564302
Short name T407
Test name
Test status
Simulation time 21964340678 ps
CPU time 108.63 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 204732 kb
Host smart-753491d8-a8a2-40fa-b7e6-74663eaa1a59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=926564302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.926564302
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.22083716
Short name T293
Test name
Test status
Simulation time 25791284518 ps
CPU time 213.81 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:45:22 PM PDT 24
Peak memory 211708 kb
Host smart-fa7e13a1-ed2e-4db7-b1cd-840002c627a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=22083716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.22083716
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1808412450
Short name T218
Test name
Test status
Simulation time 136857160 ps
CPU time 11.61 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:41:55 PM PDT 24
Peak memory 204432 kb
Host smart-18b07e46-7c80-4e0f-bab5-1733ec6bf0d6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808412450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1808412450
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.3335609827
Short name T613
Test name
Test status
Simulation time 2058606017 ps
CPU time 14.87 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:42:03 PM PDT 24
Peak memory 204056 kb
Host smart-63af07ef-88d6-43d2-97df-7849dbf085ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3335609827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3335609827
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.3104280435
Short name T75
Test name
Test status
Simulation time 443907925 ps
CPU time 3.61 seconds
Started Apr 18 12:41:52 PM PDT 24
Finished Apr 18 12:41:57 PM PDT 24
Peak memory 203376 kb
Host smart-cddac8eb-3a63-4bff-b027-fff1a8f44fb0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3104280435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3104280435
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1725423470
Short name T298
Test name
Test status
Simulation time 5110692873 ps
CPU time 26.86 seconds
Started Apr 18 12:41:50 PM PDT 24
Finished Apr 18 12:42:18 PM PDT 24
Peak memory 203480 kb
Host smart-90a01c21-d991-4260-a5fb-07ceb2535e23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725423470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1725423470
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.786707892
Short name T42
Test name
Test status
Simulation time 4398989927 ps
CPU time 29.83 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:42:14 PM PDT 24
Peak memory 203424 kb
Host smart-3ec1a2ca-3543-4440-bb1a-9fcdf5dabc55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=786707892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.786707892
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3676805141
Short name T99
Test name
Test status
Simulation time 28900106 ps
CPU time 2.29 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:41:47 PM PDT 24
Peak memory 203348 kb
Host smart-083ec293-fddc-47b4-b277-8e20395b5ac1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676805141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3676805141
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.4149165188
Short name T791
Test name
Test status
Simulation time 9681111458 ps
CPU time 237.16 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 210584 kb
Host smart-153e6f33-dbe9-416a-8335-f0514b60b76e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4149165188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4149165188
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1944767720
Short name T36
Test name
Test status
Simulation time 1640160542 ps
CPU time 167.05 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:44:42 PM PDT 24
Peak memory 206796 kb
Host smart-46aebf57-8fc1-4829-86f8-799a8e101b9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1944767720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1944767720
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1799111298
Short name T323
Test name
Test status
Simulation time 168561971 ps
CPU time 29.43 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:42:29 PM PDT 24
Peak memory 206540 kb
Host smart-dd3c03fc-0395-410f-9b7d-290a66bc6ee4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1799111298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.1799111298
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1637196532
Short name T426
Test name
Test status
Simulation time 1102794836 ps
CPU time 248.79 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:45:57 PM PDT 24
Peak memory 219856 kb
Host smart-f57892c2-0f2b-4573-9a2d-23ebeed4e7f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1637196532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.1637196532
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.233218784
Short name T480
Test name
Test status
Simulation time 531933310 ps
CPU time 12.99 seconds
Started Apr 18 12:41:48 PM PDT 24
Finished Apr 18 12:42:03 PM PDT 24
Peak memory 205004 kb
Host smart-87ef2a6a-6871-4c14-b3e6-9db3659ec047
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=233218784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.233218784
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.3997699521
Short name T777
Test name
Test status
Simulation time 725219226 ps
CPU time 48.05 seconds
Started Apr 18 12:41:49 PM PDT 24
Finished Apr 18 12:42:38 PM PDT 24
Peak memory 204532 kb
Host smart-c530f296-0a5d-4bbc-b3b4-8fbded4a7a48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3997699521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3997699521
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.147925462
Short name T142
Test name
Test status
Simulation time 161105727096 ps
CPU time 609.65 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:52:09 PM PDT 24
Peak memory 207584 kb
Host smart-4d169a58-c1f3-4295-a52d-43dc089e13a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=147925462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo
w_rsp.147925462
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1653648611
Short name T334
Test name
Test status
Simulation time 130138316 ps
CPU time 17.77 seconds
Started Apr 18 12:41:49 PM PDT 24
Finished Apr 18 12:42:09 PM PDT 24
Peak memory 203620 kb
Host smart-87e52e5c-983e-4c50-9010-a7ee5e28a69d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1653648611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1653648611
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.1535004383
Short name T518
Test name
Test status
Simulation time 223091019 ps
CPU time 3.21 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:41:49 PM PDT 24
Peak memory 203344 kb
Host smart-de964b81-b6a3-49dd-b815-b782b1353243
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1535004383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1535004383
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.3385886432
Short name T551
Test name
Test status
Simulation time 3283709524 ps
CPU time 41.6 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:42:28 PM PDT 24
Peak memory 205276 kb
Host smart-5f80d45e-cc97-48b2-84b9-0cc67c2e272b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3385886432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3385886432
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.3383443053
Short name T238
Test name
Test status
Simulation time 43433441204 ps
CPU time 235.74 seconds
Started Apr 18 12:41:51 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 205324 kb
Host smart-463572a9-7b50-4ded-84ca-1d3276ab7aea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383443053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3383443053
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2806544020
Short name T440
Test name
Test status
Simulation time 6935696772 ps
CPU time 61.02 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 204712 kb
Host smart-300165c4-43b4-4064-82fd-45ae0a445c18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2806544020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2806544020
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1603286219
Short name T149
Test name
Test status
Simulation time 46832375 ps
CPU time 6.03 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:41:51 PM PDT 24
Peak memory 211652 kb
Host smart-b1c43c6d-1032-4407-b205-0459a6657de8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603286219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1603286219
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.3459486706
Short name T509
Test name
Test status
Simulation time 1035353843 ps
CPU time 9.34 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:41:55 PM PDT 24
Peak memory 203892 kb
Host smart-d5c72641-beda-48a3-bf5c-c38db49e998a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3459486706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3459486706
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2366056005
Short name T864
Test name
Test status
Simulation time 159204033 ps
CPU time 3.32 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:41:58 PM PDT 24
Peak memory 203360 kb
Host smart-0fa960b6-b5bc-4eff-bf6e-3285da0c2643
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2366056005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2366056005
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3705891615
Short name T191
Test name
Test status
Simulation time 7619966463 ps
CPU time 28.27 seconds
Started Apr 18 12:41:48 PM PDT 24
Finished Apr 18 12:42:18 PM PDT 24
Peak memory 203532 kb
Host smart-67d3741b-62c8-4001-993d-a84dcb9e62ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705891615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3705891615
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1715584963
Short name T175
Test name
Test status
Simulation time 4255224379 ps
CPU time 29.63 seconds
Started Apr 18 12:41:51 PM PDT 24
Finished Apr 18 12:42:22 PM PDT 24
Peak memory 203388 kb
Host smart-d55a5c9d-db17-4fba-9cde-4c919fefeebf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1715584963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1715584963
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3726994068
Short name T882
Test name
Test status
Simulation time 26429146 ps
CPU time 2.53 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:41:47 PM PDT 24
Peak memory 203480 kb
Host smart-4a21cfb9-bc5a-46e0-95ae-73f156dac7d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726994068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3726994068
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.4289410950
Short name T384
Test name
Test status
Simulation time 3673468890 ps
CPU time 78.68 seconds
Started Apr 18 12:41:57 PM PDT 24
Finished Apr 18 12:43:17 PM PDT 24
Peak memory 206728 kb
Host smart-92e78f62-07a2-4caa-8155-dabcf46ccc44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4289410950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4289410950
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1012550555
Short name T173
Test name
Test status
Simulation time 2507549518 ps
CPU time 46.21 seconds
Started Apr 18 12:42:04 PM PDT 24
Finished Apr 18 12:42:51 PM PDT 24
Peak memory 205168 kb
Host smart-9e410797-f376-45af-8a2d-10452c96ef3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1012550555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1012550555
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2581457606
Short name T804
Test name
Test status
Simulation time 3586091925 ps
CPU time 401.81 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:48:37 PM PDT 24
Peak memory 219916 kb
Host smart-5df0550e-4e3a-4b13-924d-6867930ddb5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2581457606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.2581457606
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2191335050
Short name T473
Test name
Test status
Simulation time 9188491181 ps
CPU time 314.14 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:47:03 PM PDT 24
Peak memory 219920 kb
Host smart-bb23eb01-b04c-4955-b9c8-9903f0b66926
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2191335050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.2191335050
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2814452265
Short name T896
Test name
Test status
Simulation time 38110140 ps
CPU time 4.87 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:42:00 PM PDT 24
Peak memory 204904 kb
Host smart-d406e389-727f-407f-aa0a-385759ce2f49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2814452265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2814452265
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.699554558
Short name T144
Test name
Test status
Simulation time 1300927521 ps
CPU time 57.84 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:42:10 PM PDT 24
Peak memory 211624 kb
Host smart-f64b4a41-57cf-4a13-8cca-b353576bf8c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=699554558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.699554558
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3792797594
Short name T495
Test name
Test status
Simulation time 100651771031 ps
CPU time 686.74 seconds
Started Apr 18 12:41:16 PM PDT 24
Finished Apr 18 12:52:44 PM PDT 24
Peak memory 211604 kb
Host smart-50b92015-beb5-419c-9d7c-d86fb25dcb6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3792797594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.3792797594
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4214704244
Short name T22
Test name
Test status
Simulation time 392033896 ps
CPU time 14.29 seconds
Started Apr 18 12:41:08 PM PDT 24
Finished Apr 18 12:41:29 PM PDT 24
Peak memory 203784 kb
Host smart-5cba05d0-a3a1-4d32-b2ea-4cb1eedd6a26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4214704244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4214704244
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.151479363
Short name T810
Test name
Test status
Simulation time 39404736 ps
CPU time 5.87 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:15 PM PDT 24
Peak memory 203380 kb
Host smart-395dab3d-9659-4619-80d1-705f131e215d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=151479363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.151479363
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.1911811766
Short name T512
Test name
Test status
Simulation time 173322704 ps
CPU time 4.39 seconds
Started Apr 18 12:40:57 PM PDT 24
Finished Apr 18 12:41:02 PM PDT 24
Peak memory 203356 kb
Host smart-448c43cf-97b2-4fe5-9ee0-38ab58af19bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1911811766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1911811766
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.475890697
Short name T219
Test name
Test status
Simulation time 44864370087 ps
CPU time 185.89 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:44:13 PM PDT 24
Peak memory 204880 kb
Host smart-58e9ac9f-29a4-48e8-aaa7-15017d4b6e2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=475890697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.475890697
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1733671061
Short name T225
Test name
Test status
Simulation time 14243816702 ps
CPU time 111.4 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 211600 kb
Host smart-44fbbc27-ddd2-47c7-8e49-ad08d5048a7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1733671061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1733671061
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1625509043
Short name T229
Test name
Test status
Simulation time 107443813 ps
CPU time 15.65 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:26 PM PDT 24
Peak memory 204592 kb
Host smart-7d462274-a1e1-4615-b3ce-0ef9f2fff16c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625509043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1625509043
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.52155438
Short name T662
Test name
Test status
Simulation time 1870061243 ps
CPU time 10.58 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:19 PM PDT 24
Peak memory 203604 kb
Host smart-caf50060-159b-4fa4-8af0-d2799156d3a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52155438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.52155438
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.2403214316
Short name T84
Test name
Test status
Simulation time 210726406 ps
CPU time 3.32 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:15 PM PDT 24
Peak memory 203352 kb
Host smart-5aef5296-b37a-481f-a41a-f9a95fc5eb78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2403214316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2403214316
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1820045548
Short name T792
Test name
Test status
Simulation time 5811650478 ps
CPU time 28.98 seconds
Started Apr 18 12:41:04 PM PDT 24
Finished Apr 18 12:41:33 PM PDT 24
Peak memory 203524 kb
Host smart-4f5a951b-f1f4-408e-a2b1-039aaae72e3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820045548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1820045548
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2940430848
Short name T177
Test name
Test status
Simulation time 3737328039 ps
CPU time 31.41 seconds
Started Apr 18 12:41:03 PM PDT 24
Finished Apr 18 12:41:35 PM PDT 24
Peak memory 203468 kb
Host smart-9fd3abe1-3012-4508-a57b-d2f1c899092d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2940430848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2940430848
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1889797265
Short name T794
Test name
Test status
Simulation time 31297828 ps
CPU time 2.52 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:57 PM PDT 24
Peak memory 203456 kb
Host smart-76651a6b-2a55-4d2c-b539-61fcceb85973
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889797265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1889797265
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2252012829
Short name T43
Test name
Test status
Simulation time 220297091 ps
CPU time 4.66 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:11 PM PDT 24
Peak memory 204268 kb
Host smart-874876b1-8bd2-4830-9f6e-e0773eb03084
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2252012829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2252012829
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.880322992
Short name T310
Test name
Test status
Simulation time 2261204286 ps
CPU time 154.24 seconds
Started Apr 18 12:41:04 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 210160 kb
Host smart-f1c742db-cde1-4b37-b61b-d8770d22f25a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=880322992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.880322992
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3058902585
Short name T39
Test name
Test status
Simulation time 332722512 ps
CPU time 146.59 seconds
Started Apr 18 12:41:13 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 208332 kb
Host smart-59b9e257-c05e-442f-b40a-5325648f488f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3058902585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.3058902585
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.155939081
Short name T243
Test name
Test status
Simulation time 455791914 ps
CPU time 71.33 seconds
Started Apr 18 12:41:04 PM PDT 24
Finished Apr 18 12:42:16 PM PDT 24
Peak memory 208712 kb
Host smart-c827409b-6fbc-4eb7-8974-400da5b75657
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=155939081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese
t_error.155939081
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3684388649
Short name T637
Test name
Test status
Simulation time 622859437 ps
CPU time 12.59 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:21 PM PDT 24
Peak memory 204944 kb
Host smart-158489f4-ec1b-47b0-83ed-8a8cc6d6a7c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3684388649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3684388649
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1200878870
Short name T194
Test name
Test status
Simulation time 1065231290 ps
CPU time 44.33 seconds
Started Apr 18 12:42:07 PM PDT 24
Finished Apr 18 12:42:53 PM PDT 24
Peak memory 211540 kb
Host smart-6c2e084a-62cd-40f8-87a8-843cedabab4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1200878870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1200878870
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.945663717
Short name T770
Test name
Test status
Simulation time 38301592862 ps
CPU time 183.12 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:44:50 PM PDT 24
Peak memory 205936 kb
Host smart-136dcfbf-99fe-4ca7-b89b-45a27e6e2dae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=945663717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo
w_rsp.945663717
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.76447939
Short name T700
Test name
Test status
Simulation time 173540713 ps
CPU time 13.88 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:42:12 PM PDT 24
Peak memory 203960 kb
Host smart-a4eedf37-c402-4084-b8ba-897234206015
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76447939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.76447939
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.4079776548
Short name T877
Test name
Test status
Simulation time 784906382 ps
CPU time 24.09 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:42:22 PM PDT 24
Peak memory 203500 kb
Host smart-44335365-87c6-482e-aadb-54b6fb00d449
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4079776548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4079776548
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.1595348051
Short name T436
Test name
Test status
Simulation time 3454916518 ps
CPU time 35.29 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:42:21 PM PDT 24
Peak memory 211616 kb
Host smart-135aad82-32af-4816-82db-84b1d3333ddb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1595348051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1595348051
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1146382860
Short name T160
Test name
Test status
Simulation time 21703163622 ps
CPU time 102.21 seconds
Started Apr 18 12:41:42 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 204800 kb
Host smart-aa2acaf0-5be0-445e-bcec-c10a1b6d3459
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146382860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1146382860
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3546811595
Short name T133
Test name
Test status
Simulation time 10030800880 ps
CPU time 87.44 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:43:23 PM PDT 24
Peak memory 204920 kb
Host smart-e62b8dfc-2b3b-4e3b-8274-eb82a4fb97ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3546811595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3546811595
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3729063434
Short name T505
Test name
Test status
Simulation time 182142299 ps
CPU time 27.71 seconds
Started Apr 18 12:41:45 PM PDT 24
Finished Apr 18 12:42:14 PM PDT 24
Peak memory 205148 kb
Host smart-3da9926f-b8e8-4c9d-93cd-9630c53fffed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729063434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3729063434
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.1618576330
Short name T136
Test name
Test status
Simulation time 89904536 ps
CPU time 4.19 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:41:50 PM PDT 24
Peak memory 203676 kb
Host smart-c6ad5b53-c022-48ae-984c-7b7d343f1d4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1618576330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1618576330
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.976983452
Short name T678
Test name
Test status
Simulation time 33459172 ps
CPU time 2.45 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:42:06 PM PDT 24
Peak memory 203460 kb
Host smart-e7323909-6840-441d-89cd-dd526b1abbca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976983452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.976983452
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2789842688
Short name T443
Test name
Test status
Simulation time 9805826919 ps
CPU time 29.19 seconds
Started Apr 18 12:41:51 PM PDT 24
Finished Apr 18 12:42:22 PM PDT 24
Peak memory 203432 kb
Host smart-e9ad32ed-faab-46a4-b15b-655e71dab47f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789842688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2789842688
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2344244732
Short name T573
Test name
Test status
Simulation time 13404622549 ps
CPU time 31.5 seconds
Started Apr 18 12:41:44 PM PDT 24
Finished Apr 18 12:42:17 PM PDT 24
Peak memory 203428 kb
Host smart-7577395f-3aec-42a3-9666-4ec4e1011b53
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2344244732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2344244732
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1251925618
Short name T826
Test name
Test status
Simulation time 40412089 ps
CPU time 2.22 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 203332 kb
Host smart-2bcbe5c3-cb93-4d4b-b12e-b06103b2fd1b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251925618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1251925618
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.4080347842
Short name T854
Test name
Test status
Simulation time 2608010479 ps
CPU time 52.58 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:42:48 PM PDT 24
Peak memory 206496 kb
Host smart-aec97c16-278f-453e-9f98-350c03e18ab6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4080347842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.4080347842
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1248658864
Short name T782
Test name
Test status
Simulation time 654514945 ps
CPU time 77.8 seconds
Started Apr 18 12:41:59 PM PDT 24
Finished Apr 18 12:43:19 PM PDT 24
Peak memory 204796 kb
Host smart-f94446e0-b5c3-4d65-927f-22a891936002
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1248658864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1248658864
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2702181952
Short name T38
Test name
Test status
Simulation time 483567681 ps
CPU time 194.61 seconds
Started Apr 18 12:41:43 PM PDT 24
Finished Apr 18 12:45:00 PM PDT 24
Peak memory 209272 kb
Host smart-44a5880e-f2ca-4ee0-95ec-262ed6217df6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2702181952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.2702181952
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1391940056
Short name T381
Test name
Test status
Simulation time 328970709 ps
CPU time 113.04 seconds
Started Apr 18 12:42:01 PM PDT 24
Finished Apr 18 12:43:57 PM PDT 24
Peak memory 208544 kb
Host smart-eb921dc7-4868-46d0-8f64-e030dd35c9b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1391940056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.1391940056
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3506874884
Short name T97
Test name
Test status
Simulation time 296915791 ps
CPU time 19.83 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:42:19 PM PDT 24
Peak memory 204868 kb
Host smart-180efb35-9950-482f-b0a2-bd786f95e255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3506874884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3506874884
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2736345814
Short name T228
Test name
Test status
Simulation time 4845079366 ps
CPU time 43.6 seconds
Started Apr 18 12:41:55 PM PDT 24
Finished Apr 18 12:42:40 PM PDT 24
Peak memory 205772 kb
Host smart-d09f9d45-b70e-468c-a0a9-c3a5e2cc7f43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2736345814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2736345814
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3007017260
Short name T462
Test name
Test status
Simulation time 49233834099 ps
CPU time 443.56 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:49:27 PM PDT 24
Peak memory 206068 kb
Host smart-52baec9f-5b55-4c5d-baaf-ce95c94d5fa6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3007017260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.3007017260
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2646013099
Short name T851
Test name
Test status
Simulation time 328006895 ps
CPU time 11.55 seconds
Started Apr 18 12:42:03 PM PDT 24
Finished Apr 18 12:42:16 PM PDT 24
Peak memory 203756 kb
Host smart-be021920-5f38-4a06-b2d7-08c89630beb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2646013099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2646013099
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3561006428
Short name T453
Test name
Test status
Simulation time 571825845 ps
CPU time 17.03 seconds
Started Apr 18 12:42:03 PM PDT 24
Finished Apr 18 12:42:22 PM PDT 24
Peak memory 203496 kb
Host smart-e2585cc6-d4cf-443b-8663-f6f7eded4e35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3561006428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3561006428
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.3863622608
Short name T875
Test name
Test status
Simulation time 185118415 ps
CPU time 12.83 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:42:16 PM PDT 24
Peak memory 211512 kb
Host smart-0ff122ce-93de-4080-98a5-7f693a560112
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3863622608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3863622608
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1346657655
Short name T262
Test name
Test status
Simulation time 22517913581 ps
CPU time 95.74 seconds
Started Apr 18 12:42:18 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 211584 kb
Host smart-a7063b11-8c80-4e71-a44a-816d23d4dcaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346657655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1346657655
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.633563414
Short name T392
Test name
Test status
Simulation time 42632330662 ps
CPU time 107.21 seconds
Started Apr 18 12:41:46 PM PDT 24
Finished Apr 18 12:43:35 PM PDT 24
Peak memory 211568 kb
Host smart-c391f1ee-7236-49fe-b5bc-2f29d4fc2299
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=633563414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.633563414
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1698244011
Short name T638
Test name
Test status
Simulation time 134340761 ps
CPU time 17.13 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:42:15 PM PDT 24
Peak memory 211688 kb
Host smart-ffac2f8e-1ca8-4623-baaf-635590f638f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698244011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1698244011
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.2968472203
Short name T118
Test name
Test status
Simulation time 4202853779 ps
CPU time 34.69 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:42:38 PM PDT 24
Peak memory 204120 kb
Host smart-7c78ef33-04b4-4f84-aec3-799cda49d5ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2968472203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2968472203
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.1730464752
Short name T166
Test name
Test status
Simulation time 34079506 ps
CPU time 2.59 seconds
Started Apr 18 12:41:57 PM PDT 24
Finished Apr 18 12:42:01 PM PDT 24
Peak memory 203388 kb
Host smart-5377d5ea-c5ea-484e-9413-e71f52bd70b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1730464752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1730464752
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.80446171
Short name T241
Test name
Test status
Simulation time 6349878678 ps
CPU time 23.84 seconds
Started Apr 18 12:41:51 PM PDT 24
Finished Apr 18 12:42:16 PM PDT 24
Peak memory 203532 kb
Host smart-e3471eb4-e5b9-4738-bf00-84002d6baacb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80446171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.80446171
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.842805639
Short name T127
Test name
Test status
Simulation time 3715167374 ps
CPU time 26.2 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:42:22 PM PDT 24
Peak memory 203408 kb
Host smart-6e4fbdeb-4919-4dac-8256-d235746bb591
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=842805639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.842805639
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2926360123
Short name T563
Test name
Test status
Simulation time 51672765 ps
CPU time 2.52 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:41:57 PM PDT 24
Peak memory 203376 kb
Host smart-62d7f01e-bb1e-4b0c-9880-1a5d9b2e4270
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926360123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2926360123
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1857706887
Short name T897
Test name
Test status
Simulation time 735007858 ps
CPU time 103.23 seconds
Started Apr 18 12:41:50 PM PDT 24
Finished Apr 18 12:43:35 PM PDT 24
Peak memory 208396 kb
Host smart-147f0c71-9899-4ead-963f-b1be25307c16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1857706887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1857706887
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.4214818323
Short name T800
Test name
Test status
Simulation time 322547985 ps
CPU time 22.48 seconds
Started Apr 18 12:42:19 PM PDT 24
Finished Apr 18 12:42:42 PM PDT 24
Peak memory 203400 kb
Host smart-c4ad4e0a-3852-4f26-a787-45706f34651c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4214818323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.4214818323
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2422959895
Short name T188
Test name
Test status
Simulation time 1963532836 ps
CPU time 221.11 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 208236 kb
Host smart-a3e07d87-dad6-4bc1-bd40-27f5a24c73d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2422959895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.2422959895
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1488846645
Short name T504
Test name
Test status
Simulation time 1567534803 ps
CPU time 123.13 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:44:05 PM PDT 24
Peak memory 208844 kb
Host smart-8c206822-4d0b-4ddf-95d3-96ba5d175ba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1488846645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.1488846645
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3992379855
Short name T232
Test name
Test status
Simulation time 699727392 ps
CPU time 10.98 seconds
Started Apr 18 12:41:55 PM PDT 24
Finished Apr 18 12:42:07 PM PDT 24
Peak memory 204856 kb
Host smart-ddae57f4-cd02-42b8-a0f3-1d0a6ce9f47e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3992379855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3992379855
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.118318577
Short name T666
Test name
Test status
Simulation time 478708151 ps
CPU time 11.4 seconds
Started Apr 18 12:42:01 PM PDT 24
Finished Apr 18 12:42:15 PM PDT 24
Peak memory 211620 kb
Host smart-934ccebf-595b-4051-a81c-09a303d77ed0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=118318577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.118318577
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3450157300
Short name T771
Test name
Test status
Simulation time 132408991958 ps
CPU time 606.39 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:52:09 PM PDT 24
Peak memory 205932 kb
Host smart-0846437a-05ec-4ee2-9d3a-2f2095307c58
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3450157300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3450157300
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1110229970
Short name T513
Test name
Test status
Simulation time 1474263965 ps
CPU time 19.45 seconds
Started Apr 18 12:41:57 PM PDT 24
Finished Apr 18 12:42:18 PM PDT 24
Peak memory 203368 kb
Host smart-03a36afc-3b87-4891-9849-d8c7347bd680
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1110229970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1110229970
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1132295354
Short name T353
Test name
Test status
Simulation time 1178843606 ps
CPU time 22.53 seconds
Started Apr 18 12:42:07 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 203496 kb
Host smart-1fc0e9bd-9dba-4077-ac55-0fd235194cd5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1132295354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1132295354
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.238744767
Short name T421
Test name
Test status
Simulation time 18586045 ps
CPU time 2.16 seconds
Started Apr 18 12:42:01 PM PDT 24
Finished Apr 18 12:42:06 PM PDT 24
Peak memory 203420 kb
Host smart-d84e4092-2908-4a16-9218-0d3fc3b97048
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=238744767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.238744767
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2682372588
Short name T311
Test name
Test status
Simulation time 6128337910 ps
CPU time 30.79 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 204528 kb
Host smart-1d45f292-81e9-472d-a0e9-51493c22d3ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682372588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2682372588
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.557550650
Short name T47
Test name
Test status
Simulation time 22076135400 ps
CPU time 194.68 seconds
Started Apr 18 12:41:49 PM PDT 24
Finished Apr 18 12:45:05 PM PDT 24
Peak memory 205008 kb
Host smart-98b7b19f-5224-4832-9e89-6abfe7d2bf0a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=557550650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.557550650
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3835647827
Short name T731
Test name
Test status
Simulation time 96763063 ps
CPU time 10.8 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:42:06 PM PDT 24
Peak memory 204580 kb
Host smart-a2ba8448-bf9f-4640-837f-77de96a8de6f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835647827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3835647827
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.1465522700
Short name T816
Test name
Test status
Simulation time 1162434826 ps
CPU time 13.11 seconds
Started Apr 18 12:41:51 PM PDT 24
Finished Apr 18 12:42:05 PM PDT 24
Peak memory 203976 kb
Host smart-d9a45670-fc2e-46d4-b629-a90c37b81baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1465522700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1465522700
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.590001884
Short name T787
Test name
Test status
Simulation time 34441402 ps
CPU time 2.07 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 203372 kb
Host smart-9e9cd3a6-1a0e-4e35-9795-d82258570db7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=590001884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.590001884
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1117377574
Short name T720
Test name
Test status
Simulation time 4766659091 ps
CPU time 26.92 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 203544 kb
Host smart-65e4e9d5-846b-4399-873d-1911ad55b2da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117377574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1117377574
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2992841160
Short name T574
Test name
Test status
Simulation time 15205153564 ps
CPU time 37.99 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:42:49 PM PDT 24
Peak memory 203536 kb
Host smart-14fe0ef8-5995-47c3-bbe7-f764b46ff5e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2992841160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2992841160
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.214638593
Short name T455
Test name
Test status
Simulation time 66586851 ps
CPU time 2.23 seconds
Started Apr 18 12:41:47 PM PDT 24
Finished Apr 18 12:41:51 PM PDT 24
Peak memory 203476 kb
Host smart-ea5a024d-70f6-4253-beb3-6c717f19b6d4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214638593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.214638593
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.450573409
Short name T846
Test name
Test status
Simulation time 7850737953 ps
CPU time 204.34 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:45:24 PM PDT 24
Peak memory 210584 kb
Host smart-68742789-8507-4729-a326-85acf924faa5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=450573409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.450573409
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.866509126
Short name T114
Test name
Test status
Simulation time 14546914438 ps
CPU time 126.23 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:44:01 PM PDT 24
Peak memory 211616 kb
Host smart-2be10c7a-5436-45f6-93bb-cd746f375fb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=866509126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.866509126
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1628439929
Short name T155
Test name
Test status
Simulation time 5934975173 ps
CPU time 292.89 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:46:48 PM PDT 24
Peak memory 208756 kb
Host smart-b27eca10-d7d3-49b1-a2ed-d9e224f36a37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1628439929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.1628439929
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1274538409
Short name T278
Test name
Test status
Simulation time 5117251571 ps
CPU time 353.65 seconds
Started Apr 18 12:42:01 PM PDT 24
Finished Apr 18 12:47:57 PM PDT 24
Peak memory 219840 kb
Host smart-f7aa91f4-6b03-4505-87a8-4a804e6fffb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1274538409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.1274538409
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2478984674
Short name T216
Test name
Test status
Simulation time 604129806 ps
CPU time 24.69 seconds
Started Apr 18 12:41:50 PM PDT 24
Finished Apr 18 12:42:16 PM PDT 24
Peak memory 205160 kb
Host smart-f11905a4-8990-4bad-af0b-9159d9bd8459
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2478984674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2478984674
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2435110636
Short name T435
Test name
Test status
Simulation time 102974785 ps
CPU time 5.26 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:42:09 PM PDT 24
Peak memory 203748 kb
Host smart-408e2951-0cf2-4d62-a498-de11b90ed7a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2435110636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2435110636
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3510611492
Short name T571
Test name
Test status
Simulation time 29891281818 ps
CPU time 230.28 seconds
Started Apr 18 12:42:06 PM PDT 24
Finished Apr 18 12:45:57 PM PDT 24
Peak memory 206220 kb
Host smart-ba5cf4af-586e-481c-a24d-de1afc8451dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3510611492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.3510611492
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.4225370168
Short name T797
Test name
Test status
Simulation time 1302726955 ps
CPU time 17.04 seconds
Started Apr 18 12:41:53 PM PDT 24
Finished Apr 18 12:42:11 PM PDT 24
Peak memory 203784 kb
Host smart-e20c5342-6664-4747-9306-a19cc0a9f4f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4225370168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.4225370168
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.1845837718
Short name T211
Test name
Test status
Simulation time 75385692 ps
CPU time 4.15 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:42:07 PM PDT 24
Peak memory 203496 kb
Host smart-9c21e925-3f25-42c7-84e4-b2aae138985d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1845837718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1845837718
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.2926541722
Short name T89
Test name
Test status
Simulation time 893106229 ps
CPU time 24.91 seconds
Started Apr 18 12:42:01 PM PDT 24
Finished Apr 18 12:42:29 PM PDT 24
Peak memory 211484 kb
Host smart-9ad44151-32cd-4bc7-ae63-54a6301cb808
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2926541722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2926541722
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3727954258
Short name T148
Test name
Test status
Simulation time 31428382083 ps
CPU time 128.32 seconds
Started Apr 18 12:41:59 PM PDT 24
Finished Apr 18 12:44:09 PM PDT 24
Peak memory 204628 kb
Host smart-3aefdd5e-26cb-426d-ac0d-e18281b1fb30
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727954258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3727954258
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2162358157
Short name T575
Test name
Test status
Simulation time 6736830258 ps
CPU time 50.65 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:42:55 PM PDT 24
Peak memory 204800 kb
Host smart-c71c1f9d-20d2-46cf-bfbc-0c646b8b3a74
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2162358157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2162358157
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3013031640
Short name T217
Test name
Test status
Simulation time 350063458 ps
CPU time 14.49 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 204632 kb
Host smart-3a1ef901-3bd6-477e-b01f-2cc05a270432
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013031640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3013031640
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.2347084643
Short name T410
Test name
Test status
Simulation time 316483335 ps
CPU time 5.03 seconds
Started Apr 18 12:41:59 PM PDT 24
Finished Apr 18 12:42:05 PM PDT 24
Peak memory 203560 kb
Host smart-55ea68b9-1461-4fb4-a350-91c0367e4364
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2347084643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2347084643
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.774242826
Short name T437
Test name
Test status
Simulation time 150007776 ps
CPU time 3.22 seconds
Started Apr 18 12:41:49 PM PDT 24
Finished Apr 18 12:41:53 PM PDT 24
Peak memory 203480 kb
Host smart-901ac63d-3565-487a-90da-e1b7601f99b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=774242826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.774242826
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2677134389
Short name T326
Test name
Test status
Simulation time 6149961706 ps
CPU time 28.58 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:42:33 PM PDT 24
Peak memory 203536 kb
Host smart-c89eb339-42bf-4cbd-9f79-b15f84709679
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677134389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2677134389
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3084393379
Short name T517
Test name
Test status
Simulation time 4889569630 ps
CPU time 35.8 seconds
Started Apr 18 12:41:54 PM PDT 24
Finished Apr 18 12:42:32 PM PDT 24
Peak memory 203528 kb
Host smart-2b88a772-49ec-420d-a8f8-23bf3643e822
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3084393379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3084393379
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3502996486
Short name T735
Test name
Test status
Simulation time 26358626 ps
CPU time 2.01 seconds
Started Apr 18 12:41:56 PM PDT 24
Finished Apr 18 12:42:00 PM PDT 24
Peak memory 203472 kb
Host smart-a2599a2f-d977-40f4-9410-058cbf02d28b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502996486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3502996486
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3507934797
Short name T661
Test name
Test status
Simulation time 1220983185 ps
CPU time 41.35 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 205684 kb
Host smart-ac175891-25b3-4e6f-9002-1518f0e42e0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3507934797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3507934797
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1751177846
Short name T721
Test name
Test status
Simulation time 684936656 ps
CPU time 40.02 seconds
Started Apr 18 12:41:57 PM PDT 24
Finished Apr 18 12:42:39 PM PDT 24
Peak memory 205248 kb
Host smart-df14b70f-46ed-4f25-8b45-392a0e330c32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1751177846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1751177846
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.5278476
Short name T675
Test name
Test status
Simulation time 118773237 ps
CPU time 38.76 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:42:43 PM PDT 24
Peak memory 207100 kb
Host smart-a1355eae-db3a-48d1-9e6e-7854e57a4913
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5278476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_r
eset.5278476
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1215714220
Short name T269
Test name
Test status
Simulation time 661074670 ps
CPU time 190.59 seconds
Started Apr 18 12:42:03 PM PDT 24
Finished Apr 18 12:45:15 PM PDT 24
Peak memory 219860 kb
Host smart-2fd6fccd-8480-4965-a091-593aa3de25e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1215714220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.1215714220
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3490734119
Short name T249
Test name
Test status
Simulation time 347343419 ps
CPU time 11.75 seconds
Started Apr 18 12:42:07 PM PDT 24
Finished Apr 18 12:42:20 PM PDT 24
Peak memory 211568 kb
Host smart-7146172d-3c3a-4edd-9e91-9b0707b348f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3490734119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3490734119
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3613793738
Short name T681
Test name
Test status
Simulation time 204033370 ps
CPU time 20.04 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:42:19 PM PDT 24
Peak memory 204636 kb
Host smart-138d9286-195c-4601-88aa-90760c129a87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3613793738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3613793738
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2368457516
Short name T270
Test name
Test status
Simulation time 61376755187 ps
CPU time 561.02 seconds
Started Apr 18 12:42:03 PM PDT 24
Finished Apr 18 12:51:26 PM PDT 24
Peak memory 207380 kb
Host smart-ea7df1b0-531a-459b-a6d7-5223e58d65df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2368457516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.2368457516
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1228602344
Short name T645
Test name
Test status
Simulation time 648101712 ps
CPU time 12.7 seconds
Started Apr 18 12:42:01 PM PDT 24
Finished Apr 18 12:42:17 PM PDT 24
Peak memory 203476 kb
Host smart-bb98f91a-badd-48f6-9bf0-a7e45ab7dc7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1228602344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1228602344
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.3408052074
Short name T773
Test name
Test status
Simulation time 333764221 ps
CPU time 19.99 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:42:32 PM PDT 24
Peak memory 203492 kb
Host smart-841975b8-742e-4ec9-8e44-2fde34416fd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3408052074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3408052074
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.1840880378
Short name T405
Test name
Test status
Simulation time 842667399 ps
CPU time 36.33 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 205116 kb
Host smart-7ab029fd-6fd8-4f08-8272-abb872d5b02e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1840880378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1840880378
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1859591957
Short name T170
Test name
Test status
Simulation time 64564538692 ps
CPU time 163.33 seconds
Started Apr 18 12:42:08 PM PDT 24
Finished Apr 18 12:44:53 PM PDT 24
Peak memory 205024 kb
Host smart-f26b6f49-8402-40ff-898a-147ebb19ae31
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859591957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1859591957
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2601409755
Short name T431
Test name
Test status
Simulation time 27434227905 ps
CPU time 217.84 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:45:40 PM PDT 24
Peak memory 204688 kb
Host smart-f29eef4d-90f3-4cf4-96b5-e1b8464d1e13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2601409755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2601409755
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1043905833
Short name T652
Test name
Test status
Simulation time 200967759 ps
CPU time 25.54 seconds
Started Apr 18 12:42:01 PM PDT 24
Finished Apr 18 12:42:29 PM PDT 24
Peak memory 211632 kb
Host smart-c8b7cdef-41fc-40b5-8c21-2e5722ef90ac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043905833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1043905833
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.4223286590
Short name T116
Test name
Test status
Simulation time 164725681 ps
CPU time 16.39 seconds
Started Apr 18 12:42:07 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 204116 kb
Host smart-e6b36d94-757a-4091-ae7f-b10225b03246
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4223286590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4223286590
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.1991084970
Short name T317
Test name
Test status
Simulation time 665208212 ps
CPU time 3.61 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:42:08 PM PDT 24
Peak memory 203348 kb
Host smart-ae79095a-604a-442c-b883-31236e8ec817
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1991084970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1991084970
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3187789545
Short name T344
Test name
Test status
Simulation time 9250723612 ps
CPU time 33.78 seconds
Started Apr 18 12:42:04 PM PDT 24
Finished Apr 18 12:42:39 PM PDT 24
Peak memory 203540 kb
Host smart-a65ec9d3-d815-4e1b-997d-4746afed405f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187789545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3187789545
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3752984596
Short name T349
Test name
Test status
Simulation time 13262860678 ps
CPU time 35.1 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:42:47 PM PDT 24
Peak memory 203552 kb
Host smart-ca3d72ff-406e-47c9-9177-d9612fdfe8fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3752984596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3752984596
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.406723242
Short name T610
Test name
Test status
Simulation time 123886506 ps
CPU time 2.41 seconds
Started Apr 18 12:42:04 PM PDT 24
Finished Apr 18 12:42:08 PM PDT 24
Peak memory 203360 kb
Host smart-a1f9902c-abd7-44d9-89f6-6f0aac81f1b4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406723242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.406723242
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1382284285
Short name T30
Test name
Test status
Simulation time 1157580640 ps
CPU time 100.08 seconds
Started Apr 18 12:42:13 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 206328 kb
Host smart-999e9da8-9e06-45f4-948b-debcde2c14c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1382284285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1382284285
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1326104239
Short name T85
Test name
Test status
Simulation time 6179674236 ps
CPU time 193.93 seconds
Started Apr 18 12:42:32 PM PDT 24
Finished Apr 18 12:45:47 PM PDT 24
Peak memory 208608 kb
Host smart-db7ff530-d1a2-41ff-9a44-28aa564989e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1326104239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.1326104239
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2624947666
Short name T281
Test name
Test status
Simulation time 944488562 ps
CPU time 123.82 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 210016 kb
Host smart-8f8489f9-91c5-4ff7-9cda-0613e687b3cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2624947666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.2624947666
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.228330272
Short name T538
Test name
Test status
Simulation time 164556820 ps
CPU time 21.4 seconds
Started Apr 18 12:42:08 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 204992 kb
Host smart-b48006aa-0a50-46c8-9cfe-a08164153beb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=228330272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.228330272
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3538016629
Short name T829
Test name
Test status
Simulation time 232817204 ps
CPU time 20.8 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:42:37 PM PDT 24
Peak memory 204556 kb
Host smart-eede853e-e4f9-498f-9ed5-90c8ebaa9a24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3538016629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3538016629
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.981251289
Short name T569
Test name
Test status
Simulation time 51839766642 ps
CPU time 425.83 seconds
Started Apr 18 12:42:02 PM PDT 24
Finished Apr 18 12:49:10 PM PDT 24
Peak memory 211600 kb
Host smart-be3236c1-498f-40e5-9742-cfb16043ba32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=981251289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.981251289
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.424160328
Short name T865
Test name
Test status
Simulation time 442667546 ps
CPU time 11.08 seconds
Started Apr 18 12:42:12 PM PDT 24
Finished Apr 18 12:42:24 PM PDT 24
Peak memory 203536 kb
Host smart-8beb8edf-dc6d-4be5-ba0b-6c26ce5565e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=424160328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.424160328
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.196628426
Short name T614
Test name
Test status
Simulation time 128335798 ps
CPU time 4.08 seconds
Started Apr 18 12:42:05 PM PDT 24
Finished Apr 18 12:42:10 PM PDT 24
Peak memory 203376 kb
Host smart-9ff31900-5c5c-4184-b0f1-add11a197f6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=196628426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.196628426
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.4145467464
Short name T295
Test name
Test status
Simulation time 2760012404 ps
CPU time 17.27 seconds
Started Apr 18 12:42:06 PM PDT 24
Finished Apr 18 12:42:24 PM PDT 24
Peak memory 211664 kb
Host smart-ef20fff5-e220-44ac-b585-0e073eca0f18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4145467464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.4145467464
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.200607798
Short name T444
Test name
Test status
Simulation time 68882461403 ps
CPU time 205.74 seconds
Started Apr 18 12:41:58 PM PDT 24
Finished Apr 18 12:45:26 PM PDT 24
Peak memory 205544 kb
Host smart-1f6bfd62-1240-4006-8547-608469a0ab93
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=200607798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.200607798
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3385423797
Short name T60
Test name
Test status
Simulation time 3663870195 ps
CPU time 33.88 seconds
Started Apr 18 12:42:24 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 204204 kb
Host smart-d5c0ddf8-cc02-415e-ab3d-8cccc5d0ee38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3385423797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3385423797
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.87970921
Short name T696
Test name
Test status
Simulation time 29180724 ps
CPU time 4.12 seconds
Started Apr 18 12:41:59 PM PDT 24
Finished Apr 18 12:42:05 PM PDT 24
Peak memory 203364 kb
Host smart-f1782723-c723-4386-9eb2-b0a7fffa7d4a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87970921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.87970921
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.554843475
Short name T289
Test name
Test status
Simulation time 88582244 ps
CPU time 7.1 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:42:29 PM PDT 24
Peak memory 203936 kb
Host smart-5aa9c745-46a2-49cd-bbd2-6e6f625d2ee2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=554843475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.554843475
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.609306651
Short name T836
Test name
Test status
Simulation time 189513947 ps
CPU time 3.81 seconds
Started Apr 18 12:42:05 PM PDT 24
Finished Apr 18 12:42:10 PM PDT 24
Peak memory 203456 kb
Host smart-66cab910-1add-46c6-aa00-54d4f4c5ed22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=609306651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.609306651
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.4133182332
Short name T650
Test name
Test status
Simulation time 6267836073 ps
CPU time 31.91 seconds
Started Apr 18 12:42:07 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 203528 kb
Host smart-3ac9de87-a4f9-473d-b055-5745c3f25aef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133182332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.4133182332
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.255066216
Short name T476
Test name
Test status
Simulation time 2205738410 ps
CPU time 19.76 seconds
Started Apr 18 12:42:03 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 203504 kb
Host smart-6d6554d2-4c14-47b4-b7a0-a1c1191f291a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=255066216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.255066216
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2491844724
Short name T255
Test name
Test status
Simulation time 28948468 ps
CPU time 2.26 seconds
Started Apr 18 12:41:59 PM PDT 24
Finished Apr 18 12:42:04 PM PDT 24
Peak memory 203396 kb
Host smart-ae148942-cacb-4d09-b387-76a933580e00
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491844724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2491844724
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1868415761
Short name T514
Test name
Test status
Simulation time 1676192819 ps
CPU time 126.89 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:44:19 PM PDT 24
Peak memory 208644 kb
Host smart-430061ac-d5d5-47a4-904a-0bbce47a7940
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1868415761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1868415761
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.4283258529
Short name T452
Test name
Test status
Simulation time 3136123506 ps
CPU time 122.77 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:44:14 PM PDT 24
Peak memory 208276 kb
Host smart-a1646097-d38c-44a4-b113-da82459b3af3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4283258529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.4283258529
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2431778634
Short name T881
Test name
Test status
Simulation time 3146861810 ps
CPU time 614.59 seconds
Started Apr 18 12:42:09 PM PDT 24
Finished Apr 18 12:52:24 PM PDT 24
Peak memory 208976 kb
Host smart-0e116fef-e4f4-449e-b8de-b9aa62ae26f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2431778634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.2431778634
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.976423952
Short name T690
Test name
Test status
Simulation time 7452136033 ps
CPU time 318.54 seconds
Started Apr 18 12:41:59 PM PDT 24
Finished Apr 18 12:47:19 PM PDT 24
Peak memory 211584 kb
Host smart-2bc6baf5-2524-4ad4-9179-b35ec5c41ecc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976423952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res
et_error.976423952
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.337044110
Short name T596
Test name
Test status
Simulation time 1268771208 ps
CPU time 23.98 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 205180 kb
Host smart-04f57100-1031-4191-9d1e-4a5701140a34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=337044110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.337044110
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.250840445
Short name T510
Test name
Test status
Simulation time 1841124841 ps
CPU time 40.17 seconds
Started Apr 18 12:42:05 PM PDT 24
Finished Apr 18 12:42:47 PM PDT 24
Peak memory 204904 kb
Host smart-d839a210-c716-41e2-92e5-9358472c0129
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=250840445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.250840445
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3606615064
Short name T670
Test name
Test status
Simulation time 21715248237 ps
CPU time 183.34 seconds
Started Apr 18 12:42:08 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 205912 kb
Host smart-7de579d1-5441-4c37-ab5c-cac14a0107c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3606615064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.3606615064
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3652255480
Short name T622
Test name
Test status
Simulation time 105087297 ps
CPU time 14.47 seconds
Started Apr 18 12:42:17 PM PDT 24
Finished Apr 18 12:42:33 PM PDT 24
Peak memory 203960 kb
Host smart-20e4006b-789d-41bb-a6f4-aecc22becaae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3652255480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3652255480
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.1900590525
Short name T365
Test name
Test status
Simulation time 627954818 ps
CPU time 7.94 seconds
Started Apr 18 12:42:09 PM PDT 24
Finished Apr 18 12:42:18 PM PDT 24
Peak memory 203488 kb
Host smart-4e151475-e9a6-40a9-8591-b6047389c849
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1900590525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1900590525
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3217574731
Short name T122
Test name
Test status
Simulation time 4352152189 ps
CPU time 27.76 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 205204 kb
Host smart-0daf882a-c7c4-4ad7-9beb-b784d1d308f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3217574731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3217574731
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1215578415
Short name T602
Test name
Test status
Simulation time 67367173298 ps
CPU time 233.4 seconds
Started Apr 18 12:42:11 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 205116 kb
Host smart-23128ac9-476d-439b-9602-6c2b230fc723
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215578415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1215578415
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1622571572
Short name T109
Test name
Test status
Simulation time 77977087411 ps
CPU time 195.14 seconds
Started Apr 18 12:42:13 PM PDT 24
Finished Apr 18 12:45:30 PM PDT 24
Peak memory 204944 kb
Host smart-19a123be-3326-4f17-86eb-00beb60529bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1622571572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1622571572
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1077482701
Short name T821
Test name
Test status
Simulation time 198400770 ps
CPU time 11.64 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:38 PM PDT 24
Peak memory 204484 kb
Host smart-7da96ebd-6b25-43e2-a65f-3eed45803eb4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077482701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1077482701
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.4242515189
Short name T7
Test name
Test status
Simulation time 2515191153 ps
CPU time 29.8 seconds
Started Apr 18 12:42:10 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 204064 kb
Host smart-c157ebbc-35e4-4c62-9db7-413fd595dc7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4242515189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4242515189
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.3403248404
Short name T778
Test name
Test status
Simulation time 134385822 ps
CPU time 3.55 seconds
Started Apr 18 12:42:05 PM PDT 24
Finished Apr 18 12:42:10 PM PDT 24
Peak memory 203380 kb
Host smart-10e49d90-4c22-459d-b20c-182dca7495f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3403248404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3403248404
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3491547713
Short name T531
Test name
Test status
Simulation time 5471812419 ps
CPU time 27.88 seconds
Started Apr 18 12:42:00 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 203532 kb
Host smart-32bde801-30dc-4061-b017-822b1f3485c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491547713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3491547713
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3670372587
Short name T831
Test name
Test status
Simulation time 8122835349 ps
CPU time 37.47 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:42:55 PM PDT 24
Peak memory 203536 kb
Host smart-15f0d24e-38fb-4b1c-9368-23d6a4c502b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3670372587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3670372587
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1386079697
Short name T671
Test name
Test status
Simulation time 37806722 ps
CPU time 2.03 seconds
Started Apr 18 12:41:59 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 203424 kb
Host smart-efaf9fd8-1bef-4b3b-8904-1eb63da34ef3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386079697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1386079697
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3183293185
Short name T493
Test name
Test status
Simulation time 5791875584 ps
CPU time 128.23 seconds
Started Apr 18 12:42:30 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 206684 kb
Host smart-cc22e40d-0f6a-4757-bbcc-d8339ea98a48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3183293185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3183293185
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1391201380
Short name T754
Test name
Test status
Simulation time 3317503877 ps
CPU time 242.03 seconds
Started Apr 18 12:42:08 PM PDT 24
Finished Apr 18 12:46:11 PM PDT 24
Peak memory 209772 kb
Host smart-f6a7fa25-3681-4e13-bae5-73ea50bfb0c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1391201380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1391201380
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2960674594
Short name T456
Test name
Test status
Simulation time 9528635034 ps
CPU time 381.78 seconds
Started Apr 18 12:42:17 PM PDT 24
Finished Apr 18 12:48:40 PM PDT 24
Peak memory 211700 kb
Host smart-666de7c9-dc0a-46be-a92d-d4e57f4321c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2960674594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.2960674594
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.644931178
Short name T635
Test name
Test status
Simulation time 470921503 ps
CPU time 16.08 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:42:40 PM PDT 24
Peak memory 205040 kb
Host smart-61417e3a-61ed-493d-91c6-24b48fc8c156
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=644931178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.644931178
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1960747755
Short name T91
Test name
Test status
Simulation time 2006441426 ps
CPU time 58.57 seconds
Started Apr 18 12:42:06 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 211660 kb
Host smart-75918a2d-71e1-4e97-a966-dc154046b051
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1960747755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1960747755
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1593430237
Short name T644
Test name
Test status
Simulation time 58894328727 ps
CPU time 401.77 seconds
Started Apr 18 12:42:14 PM PDT 24
Finished Apr 18 12:48:57 PM PDT 24
Peak memory 206984 kb
Host smart-90f0f3c0-ac33-43a2-ab4a-578af111c272
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1593430237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.1593430237
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3769810108
Short name T291
Test name
Test status
Simulation time 508656526 ps
CPU time 19.06 seconds
Started Apr 18 12:42:49 PM PDT 24
Finished Apr 18 12:43:09 PM PDT 24
Peak memory 203540 kb
Host smart-8504112c-3e78-41a4-a570-2003a4bbf989
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3769810108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3769810108
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.95168321
Short name T823
Test name
Test status
Simulation time 18090085 ps
CPU time 1.96 seconds
Started Apr 18 12:42:16 PM PDT 24
Finished Apr 18 12:42:19 PM PDT 24
Peak memory 203476 kb
Host smart-1bc48e45-ff13-44e7-bef0-2caea46ae330
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95168321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.95168321
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.3080549932
Short name T828
Test name
Test status
Simulation time 202432978 ps
CPU time 10.6 seconds
Started Apr 18 12:42:17 PM PDT 24
Finished Apr 18 12:42:29 PM PDT 24
Peak memory 204680 kb
Host smart-408e3418-a79e-4634-9471-e81fb084b3ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3080549932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3080549932
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.325352762
Short name T290
Test name
Test status
Simulation time 14762040261 ps
CPU time 55.36 seconds
Started Apr 18 12:42:18 PM PDT 24
Finished Apr 18 12:43:14 PM PDT 24
Peak memory 211672 kb
Host smart-7943c3ff-0578-43bc-bafa-2f24da982990
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=325352762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.325352762
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3750346607
Short name T775
Test name
Test status
Simulation time 14757561378 ps
CPU time 117.27 seconds
Started Apr 18 12:42:12 PM PDT 24
Finished Apr 18 12:44:11 PM PDT 24
Peak memory 204996 kb
Host smart-a2314872-bd65-4f58-805b-42ad1e3dace2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3750346607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3750346607
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2286891356
Short name T832
Test name
Test status
Simulation time 305645728 ps
CPU time 20.18 seconds
Started Apr 18 12:42:17 PM PDT 24
Finished Apr 18 12:42:38 PM PDT 24
Peak memory 204568 kb
Host smart-8af972b7-b36e-4c6a-bd2c-5217252557db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286891356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2286891356
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.683594450
Short name T117
Test name
Test status
Simulation time 67447549 ps
CPU time 5.46 seconds
Started Apr 18 12:42:20 PM PDT 24
Finished Apr 18 12:42:27 PM PDT 24
Peak memory 203428 kb
Host smart-b31d37cd-0058-4ca5-a07f-0fd250750bf1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=683594450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.683594450
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.1414583320
Short name T583
Test name
Test status
Simulation time 156695065 ps
CPU time 3.21 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:42:20 PM PDT 24
Peak memory 203396 kb
Host smart-9f9d95ba-8f03-4ef5-9129-1a475d76ad2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1414583320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1414583320
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2038181046
Short name T769
Test name
Test status
Simulation time 6738818619 ps
CPU time 22.89 seconds
Started Apr 18 12:42:12 PM PDT 24
Finished Apr 18 12:42:36 PM PDT 24
Peak memory 203412 kb
Host smart-07e3e737-d337-4aef-94e9-3a6e6367fb61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038181046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2038181046
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.345506957
Short name T761
Test name
Test status
Simulation time 3444959929 ps
CPU time 24.11 seconds
Started Apr 18 12:42:06 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 203404 kb
Host smart-1856cc8d-5b0e-4347-96d8-08b48bc32fbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=345506957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.345506957
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1039348773
Short name T867
Test name
Test status
Simulation time 34432760 ps
CPU time 2.6 seconds
Started Apr 18 12:42:16 PM PDT 24
Finished Apr 18 12:42:20 PM PDT 24
Peak memory 203436 kb
Host smart-4edb6e1a-373d-415a-a8e4-d2729bcd4543
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039348773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1039348773
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.852757576
Short name T643
Test name
Test status
Simulation time 4275486279 ps
CPU time 111.51 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:44:15 PM PDT 24
Peak memory 206836 kb
Host smart-7d3adf75-9f0e-4445-b629-31b277fa253a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=852757576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.852757576
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2281888249
Short name T234
Test name
Test status
Simulation time 7273653434 ps
CPU time 127.87 seconds
Started Apr 18 12:42:11 PM PDT 24
Finished Apr 18 12:44:20 PM PDT 24
Peak memory 207512 kb
Host smart-628aa47e-8782-491c-a96b-17dd6197fcf1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281888249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2281888249
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2963574258
Short name T808
Test name
Test status
Simulation time 312473323 ps
CPU time 81.41 seconds
Started Apr 18 12:42:16 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 207872 kb
Host smart-9fe408ce-d082-4954-9d8f-b31684837d45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2963574258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.2963574258
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1658110177
Short name T647
Test name
Test status
Simulation time 6651349268 ps
CPU time 238.12 seconds
Started Apr 18 12:42:20 PM PDT 24
Finished Apr 18 12:46:19 PM PDT 24
Peak memory 211716 kb
Host smart-fe11d55f-80b6-4883-a912-0382fc0bdf59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658110177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.1658110177
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3165493619
Short name T483
Test name
Test status
Simulation time 125589365 ps
CPU time 14.41 seconds
Started Apr 18 12:42:14 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 211528 kb
Host smart-c466fa3e-b2fa-49a9-b048-57e196462713
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3165493619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3165493619
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.392284357
Short name T891
Test name
Test status
Simulation time 3335295860 ps
CPU time 43.52 seconds
Started Apr 18 12:42:17 PM PDT 24
Finished Apr 18 12:43:01 PM PDT 24
Peak memory 211640 kb
Host smart-3820a8da-920c-4d73-aa9f-170e2062cafd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=392284357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.392284357
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1227465031
Short name T715
Test name
Test status
Simulation time 104988957386 ps
CPU time 539.05 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:51:16 PM PDT 24
Peak memory 206052 kb
Host smart-0aaffc4b-cf30-483b-95b5-a16935f2bdfd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1227465031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.1227465031
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4202383181
Short name T556
Test name
Test status
Simulation time 1016755770 ps
CPU time 27.21 seconds
Started Apr 18 12:42:30 PM PDT 24
Finished Apr 18 12:42:58 PM PDT 24
Peak memory 204104 kb
Host smart-944b16d7-ebe0-477d-b2e7-9df1a9f33896
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4202383181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4202383181
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.3244558286
Short name T424
Test name
Test status
Simulation time 109581962 ps
CPU time 10.79 seconds
Started Apr 18 12:42:14 PM PDT 24
Finished Apr 18 12:42:27 PM PDT 24
Peak memory 203420 kb
Host smart-f47f0426-6c17-4eec-928c-91e8870d056a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3244558286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3244558286
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.2592813101
Short name T567
Test name
Test status
Simulation time 382805981 ps
CPU time 17.44 seconds
Started Apr 18 12:42:26 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 204592 kb
Host smart-945b7809-1f3c-4d69-9fe0-53bad4cf5fb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2592813101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2592813101
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3517052005
Short name T328
Test name
Test status
Simulation time 245812866152 ps
CPU time 311.26 seconds
Started Apr 18 12:42:11 PM PDT 24
Finished Apr 18 12:47:24 PM PDT 24
Peak memory 211628 kb
Host smart-018e81dd-59e6-4114-9045-487b0de698a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517052005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3517052005
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.523163308
Short name T582
Test name
Test status
Simulation time 57319616090 ps
CPU time 227.21 seconds
Started Apr 18 12:42:14 PM PDT 24
Finished Apr 18 12:46:03 PM PDT 24
Peak memory 205012 kb
Host smart-078c6f99-f89e-4059-8cbd-0e3f57beab2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=523163308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.523163308
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3653666625
Short name T499
Test name
Test status
Simulation time 49976351 ps
CPU time 4.26 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:42:27 PM PDT 24
Peak memory 204248 kb
Host smart-80e60724-1fe0-4ab1-b041-c96eb411e6a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653666625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3653666625
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.156675021
Short name T401
Test name
Test status
Simulation time 417708640 ps
CPU time 17.75 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:42:40 PM PDT 24
Peak memory 203960 kb
Host smart-8f1baf68-887c-4c50-8d53-f58f1eb4a360
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=156675021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.156675021
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.1099919737
Short name T169
Test name
Test status
Simulation time 268111569 ps
CPU time 3.92 seconds
Started Apr 18 12:42:16 PM PDT 24
Finished Apr 18 12:42:21 PM PDT 24
Peak memory 203488 kb
Host smart-c0fe97a1-7a34-4c0a-97d4-96665e354bd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1099919737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1099919737
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2671904120
Short name T386
Test name
Test status
Simulation time 7616911696 ps
CPU time 34.39 seconds
Started Apr 18 12:42:14 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 203552 kb
Host smart-197788fd-a272-4eca-889e-bb4358fdefb0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671904120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2671904120
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3130392591
Short name T57
Test name
Test status
Simulation time 4600137677 ps
CPU time 29.12 seconds
Started Apr 18 12:42:12 PM PDT 24
Finished Apr 18 12:42:43 PM PDT 24
Peak memory 203360 kb
Host smart-c0e581f6-4bd6-4348-beee-a127f40bd0ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3130392591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3130392591
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1688933969
Short name T165
Test name
Test status
Simulation time 30114567 ps
CPU time 2.13 seconds
Started Apr 18 12:42:24 PM PDT 24
Finished Apr 18 12:42:28 PM PDT 24
Peak memory 203456 kb
Host smart-af82fcd9-938c-4eac-acf4-c9be8c3958d0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688933969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1688933969
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1433594861
Short name T879
Test name
Test status
Simulation time 47141116 ps
CPU time 2.09 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:42:18 PM PDT 24
Peak memory 203348 kb
Host smart-e2e3cc4a-ed6a-4149-9716-7999213e4cf3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1433594861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1433594861
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.4229111365
Short name T762
Test name
Test status
Simulation time 772133775 ps
CPU time 45.79 seconds
Started Apr 18 12:42:19 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 205684 kb
Host smart-e49e2925-06b7-4295-ac55-bbe8fb035a93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4229111365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.4229111365
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3429071740
Short name T870
Test name
Test status
Simulation time 3201376504 ps
CPU time 167.85 seconds
Started Apr 18 12:42:13 PM PDT 24
Finished Apr 18 12:45:03 PM PDT 24
Peak memory 208928 kb
Host smart-38241906-9ff7-47af-b01a-81ba4a335b65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3429071740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.3429071740
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.326815249
Short name T874
Test name
Test status
Simulation time 2292837974 ps
CPU time 211.93 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:45:56 PM PDT 24
Peak memory 211672 kb
Host smart-e8864743-bdfe-4b71-af23-a0f9fb418731
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=326815249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res
et_error.326815249
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3315318262
Short name T654
Test name
Test status
Simulation time 115349358 ps
CPU time 17.19 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:42:40 PM PDT 24
Peak memory 204908 kb
Host smart-83e529cd-b8da-4618-8c41-8e00edc4835b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3315318262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3315318262
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.61984023
Short name T710
Test name
Test status
Simulation time 2436649037 ps
CPU time 59.24 seconds
Started Apr 18 12:42:24 PM PDT 24
Finished Apr 18 12:43:24 PM PDT 24
Peak memory 211560 kb
Host smart-7f380cf4-f688-4665-9e9c-1062b68050c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=61984023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.61984023
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.4285329530
Short name T274
Test name
Test status
Simulation time 282611585920 ps
CPU time 622.11 seconds
Started Apr 18 12:42:32 PM PDT 24
Finished Apr 18 12:52:55 PM PDT 24
Peak memory 206004 kb
Host smart-005e58e2-37ac-4cb7-854b-8a40cabecb96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4285329530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.4285329530
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.436836180
Short name T807
Test name
Test status
Simulation time 20494789 ps
CPU time 2.72 seconds
Started Apr 18 12:42:20 PM PDT 24
Finished Apr 18 12:42:24 PM PDT 24
Peak memory 203408 kb
Host smart-0a726f83-a891-4e88-b127-6b38b7074d65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=436836180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.436836180
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.4091451516
Short name T503
Test name
Test status
Simulation time 1559597062 ps
CPU time 26.93 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 203388 kb
Host smart-791a654d-dc26-4c9a-a665-00e1cc0563ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4091451516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4091451516
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.602328865
Short name T530
Test name
Test status
Simulation time 236393348 ps
CPU time 12.73 seconds
Started Apr 18 12:42:20 PM PDT 24
Finished Apr 18 12:42:34 PM PDT 24
Peak memory 211664 kb
Host smart-4de91de4-3532-4af5-ace0-7cd31eb34f28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=602328865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.602328865
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2048137563
Short name T898
Test name
Test status
Simulation time 9816367446 ps
CPU time 45.37 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:43:11 PM PDT 24
Peak memory 204532 kb
Host smart-3b40839d-c617-4d78-be4f-53eefab60436
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048137563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2048137563
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2929319019
Short name T126
Test name
Test status
Simulation time 33807477554 ps
CPU time 169.5 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 205076 kb
Host smart-e32e16f5-9f6b-42ad-8d5a-5b89afb2eb34
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2929319019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2929319019
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1855986645
Short name T525
Test name
Test status
Simulation time 230774734 ps
CPU time 7.12 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:42:29 PM PDT 24
Peak memory 204460 kb
Host smart-cf69638b-4e28-4388-8141-2d186f33b8c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855986645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1855986645
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.2719239128
Short name T716
Test name
Test status
Simulation time 198036098 ps
CPU time 5.65 seconds
Started Apr 18 12:42:24 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 203792 kb
Host smart-484cac57-c4fd-4ea7-850f-6d02c6031d7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2719239128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2719239128
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.3983162026
Short name T138
Test name
Test status
Simulation time 146548482 ps
CPU time 3.62 seconds
Started Apr 18 12:42:20 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 203468 kb
Host smart-a0822771-6ea2-45d5-a24a-252d6f376dae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3983162026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3983162026
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.205403146
Short name T158
Test name
Test status
Simulation time 10107792268 ps
CPU time 36.34 seconds
Started Apr 18 12:42:15 PM PDT 24
Finished Apr 18 12:42:53 PM PDT 24
Peak memory 203440 kb
Host smart-4fd746bd-b6ef-4301-b462-4fe7269d0043
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=205403146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.205403146
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4210107602
Short name T763
Test name
Test status
Simulation time 14505264283 ps
CPU time 43.11 seconds
Started Apr 18 12:42:14 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 203544 kb
Host smart-31e5c9ec-cce6-4e7e-bc78-71ac263f8180
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4210107602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4210107602
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.20498413
Short name T418
Test name
Test status
Simulation time 41017715 ps
CPU time 2.48 seconds
Started Apr 18 12:42:13 PM PDT 24
Finished Apr 18 12:42:17 PM PDT 24
Peak memory 203460 kb
Host smart-cbd76247-d227-489e-8a38-9ae908d65e1c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20498413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.20498413
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.815947313
Short name T199
Test name
Test status
Simulation time 11930762161 ps
CPU time 194.22 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 206348 kb
Host smart-655d5e55-a431-48d8-af99-dff6bf572792
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=815947313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.815947313
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.96099242
Short name T352
Test name
Test status
Simulation time 13949909846 ps
CPU time 246.41 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 210808 kb
Host smart-81113226-fe2f-4e40-8975-759d6341ca93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96099242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.96099242
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3844836715
Short name T239
Test name
Test status
Simulation time 256509604 ps
CPU time 63.05 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 207184 kb
Host smart-cd4cdb4b-41c7-486e-b5f0-05552b24f16e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3844836715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.3844836715
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2022491407
Short name T603
Test name
Test status
Simulation time 141928206 ps
CPU time 19.16 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:42:42 PM PDT 24
Peak memory 205040 kb
Host smart-0ae2d694-dfec-4141-8d26-f46782f7e050
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2022491407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2022491407
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1204236905
Short name T544
Test name
Test status
Simulation time 1421474541 ps
CPU time 27.66 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:35 PM PDT 24
Peak memory 204528 kb
Host smart-f3522901-9893-47fa-9670-bc340ddc633e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1204236905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1204236905
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2087376046
Short name T687
Test name
Test status
Simulation time 54272440524 ps
CPU time 347.52 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:46:55 PM PDT 24
Peak memory 206800 kb
Host smart-2dd65a7a-5e6b-4097-a063-584e083b5103
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2087376046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.2087376046
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2269682843
Short name T287
Test name
Test status
Simulation time 5839350920 ps
CPU time 28.17 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:36 PM PDT 24
Peak memory 204556 kb
Host smart-d6a53bcf-ac18-4a1c-ab1f-74be14c34931
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2269682843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2269682843
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.1138770245
Short name T760
Test name
Test status
Simulation time 179766315 ps
CPU time 18.49 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:26 PM PDT 24
Peak memory 203564 kb
Host smart-dc044424-ee9e-4e72-80fe-1f449a82b464
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1138770245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1138770245
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.1550787437
Short name T33
Test name
Test status
Simulation time 1820539796 ps
CPU time 34.14 seconds
Started Apr 18 12:40:57 PM PDT 24
Finished Apr 18 12:41:32 PM PDT 24
Peak memory 204532 kb
Host smart-c599a8a0-c774-408c-8442-48d7e5e6594f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1550787437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1550787437
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.930047980
Short name T23
Test name
Test status
Simulation time 66386264771 ps
CPU time 111.85 seconds
Started Apr 18 12:41:13 PM PDT 24
Finished Apr 18 12:43:05 PM PDT 24
Peak memory 204936 kb
Host smart-74febbef-3d2a-4b15-88f5-656803407ce2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=930047980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.930047980
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1056175890
Short name T866
Test name
Test status
Simulation time 276803816 ps
CPU time 11.41 seconds
Started Apr 18 12:41:08 PM PDT 24
Finished Apr 18 12:41:21 PM PDT 24
Peak memory 204500 kb
Host smart-df42a1db-b5f7-4c03-a802-615a362eb873
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056175890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1056175890
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3950493745
Short name T627
Test name
Test status
Simulation time 244046251 ps
CPU time 17.71 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:26 PM PDT 24
Peak memory 203988 kb
Host smart-57b2f603-6df8-4480-b320-0ac468c01f80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3950493745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3950493745
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.2734288683
Short name T506
Test name
Test status
Simulation time 74237428 ps
CPU time 2.34 seconds
Started Apr 18 12:40:59 PM PDT 24
Finished Apr 18 12:41:02 PM PDT 24
Peak memory 203460 kb
Host smart-77a0df3e-6ae1-48d4-86e4-818f80aa74ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2734288683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2734288683
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1291510497
Short name T50
Test name
Test status
Simulation time 6145107595 ps
CPU time 24.63 seconds
Started Apr 18 12:40:58 PM PDT 24
Finished Apr 18 12:41:23 PM PDT 24
Peak memory 203536 kb
Host smart-12e0665c-c741-44ea-8b81-7f313d0e32f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291510497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1291510497
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1054917350
Short name T308
Test name
Test status
Simulation time 2551635541 ps
CPU time 24.33 seconds
Started Apr 18 12:41:02 PM PDT 24
Finished Apr 18 12:41:27 PM PDT 24
Peak memory 203452 kb
Host smart-f1924c10-2bde-4935-870f-d2057223d6ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1054917350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1054917350
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.50662926
Short name T257
Test name
Test status
Simulation time 131423906 ps
CPU time 2.35 seconds
Started Apr 18 12:41:03 PM PDT 24
Finished Apr 18 12:41:07 PM PDT 24
Peak memory 203360 kb
Host smart-3aa156e4-f183-47b7-acf0-e13452d982c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50662926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.50662926
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.4255185
Short name T104
Test name
Test status
Simulation time 1119446414 ps
CPU time 42.56 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:51 PM PDT 24
Peak memory 205520 kb
Host smart-6d9e34ec-6e2d-42f4-a7e1-2082a6014de4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4255185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.4255185
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3905547657
Short name T339
Test name
Test status
Simulation time 265696689 ps
CPU time 22.24 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:31 PM PDT 24
Peak memory 204140 kb
Host smart-e2342de2-bf2f-4bce-abf4-509cf7fb3933
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3905547657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3905547657
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2272865500
Short name T27
Test name
Test status
Simulation time 2320497796 ps
CPU time 275.24 seconds
Started Apr 18 12:40:59 PM PDT 24
Finished Apr 18 12:45:34 PM PDT 24
Peak memory 219192 kb
Host smart-897e4ace-99c2-438e-99b0-edeaef5f59bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2272865500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.2272865500
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2023027456
Short name T220
Test name
Test status
Simulation time 437839500 ps
CPU time 18.86 seconds
Started Apr 18 12:40:57 PM PDT 24
Finished Apr 18 12:41:17 PM PDT 24
Peak memory 205144 kb
Host smart-ae4285f7-da31-4c8f-b1ed-6057dee47efd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2023027456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2023027456
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3529662373
Short name T460
Test name
Test status
Simulation time 961999653 ps
CPU time 40.6 seconds
Started Apr 18 12:42:24 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 204452 kb
Host smart-36dd75a4-e5c4-4747-8dc1-0e2960528908
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3529662373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3529662373
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.307893765
Short name T119
Test name
Test status
Simulation time 30307440740 ps
CPU time 308.59 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:47:32 PM PDT 24
Peak memory 206616 kb
Host smart-de203c83-7659-44d2-a022-7955640c498c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=307893765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo
w_rsp.307893765
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2468388545
Short name T533
Test name
Test status
Simulation time 161053855 ps
CPU time 11.87 seconds
Started Apr 18 12:42:28 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 203828 kb
Host smart-d243b78c-5173-49d2-8864-98340da5766f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2468388545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2468388545
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.672659757
Short name T488
Test name
Test status
Simulation time 687363803 ps
CPU time 6.18 seconds
Started Apr 18 12:42:23 PM PDT 24
Finished Apr 18 12:42:30 PM PDT 24
Peak memory 203380 kb
Host smart-22986f33-605f-4953-8718-36e1d2d70036
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=672659757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.672659757
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.4252110164
Short name T730
Test name
Test status
Simulation time 249038318 ps
CPU time 16.67 seconds
Started Apr 18 12:42:20 PM PDT 24
Finished Apr 18 12:42:38 PM PDT 24
Peak memory 204620 kb
Host smart-67b94c80-7300-4956-8883-9368588912d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4252110164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.4252110164
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.455029453
Short name T572
Test name
Test status
Simulation time 64061058705 ps
CPU time 216.44 seconds
Started Apr 18 12:42:19 PM PDT 24
Finished Apr 18 12:45:56 PM PDT 24
Peak memory 211588 kb
Host smart-2fdf5de9-856e-436b-9f5a-8f93ee8c1ade
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=455029453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.455029453
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3907089158
Short name T63
Test name
Test status
Simulation time 41536723110 ps
CPU time 198.01 seconds
Started Apr 18 12:42:20 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 205116 kb
Host smart-4985e53e-daa5-47a8-bd2f-0e840080e6e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3907089158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3907089158
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3601996890
Short name T502
Test name
Test status
Simulation time 81649302 ps
CPU time 3.01 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:30 PM PDT 24
Peak memory 203412 kb
Host smart-07fcef65-0f75-49c9-8064-8a2430d8cebc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601996890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3601996890
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.1471632627
Short name T69
Test name
Test status
Simulation time 102937406 ps
CPU time 8.84 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 204152 kb
Host smart-a11e3353-f465-4773-9cb0-633bdea620bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1471632627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1471632627
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.3592180006
Short name T210
Test name
Test status
Simulation time 314467619 ps
CPU time 4.32 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 203412 kb
Host smart-56f99fb5-4a3c-44f4-a62d-81ae6d88c132
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3592180006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3592180006
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3995328641
Short name T223
Test name
Test status
Simulation time 7804219247 ps
CPU time 33.01 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 203408 kb
Host smart-eae36a06-1062-4ca1-ba9f-45b089c85167
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995328641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3995328641
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2583997092
Short name T838
Test name
Test status
Simulation time 6607108672 ps
CPU time 27.87 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 203532 kb
Host smart-9bf11681-15a4-479e-b337-332424a87e32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2583997092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2583997092
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1511724570
Short name T727
Test name
Test status
Simulation time 41355749 ps
CPU time 2.54 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:42:25 PM PDT 24
Peak memory 203408 kb
Host smart-fa0b423b-2923-4c8c-850d-161588c7eeb3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511724570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1511724570
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3163118028
Short name T660
Test name
Test status
Simulation time 230312569 ps
CPU time 3.82 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:42:27 PM PDT 24
Peak memory 203488 kb
Host smart-5dc4ca30-0ef8-4763-9e88-943e87601a05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3163118028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3163118028
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.284327355
Short name T795
Test name
Test status
Simulation time 603913575 ps
CPU time 32.41 seconds
Started Apr 18 12:42:27 PM PDT 24
Finished Apr 18 12:43:01 PM PDT 24
Peak memory 205476 kb
Host smart-59d076f3-d8f8-4096-b062-9a382d6a1b64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=284327355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.284327355
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2811046809
Short name T268
Test name
Test status
Simulation time 5328873316 ps
CPU time 204.45 seconds
Started Apr 18 12:42:29 PM PDT 24
Finished Apr 18 12:45:55 PM PDT 24
Peak memory 208964 kb
Host smart-f47ffa01-aa00-413c-8f6a-10c0e5511b71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2811046809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.2811046809
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.567167058
Short name T475
Test name
Test status
Simulation time 725191364 ps
CPU time 75.76 seconds
Started Apr 18 12:42:26 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 208256 kb
Host smart-1be33dcd-d255-49cd-80fd-6a3f4669e8dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=567167058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res
et_error.567167058
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1824835615
Short name T150
Test name
Test status
Simulation time 311342710 ps
CPU time 11.97 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:38 PM PDT 24
Peak memory 205092 kb
Host smart-1f51dc26-59b7-4081-b497-095af90c454e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1824835615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1824835615
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2625941706
Short name T744
Test name
Test status
Simulation time 3917478925 ps
CPU time 48.59 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:43:15 PM PDT 24
Peak memory 206268 kb
Host smart-d434f7da-b9c1-437d-97b5-05867b5c9cfb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2625941706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2625941706
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2672139806
Short name T658
Test name
Test status
Simulation time 99619298 ps
CPU time 4.19 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:30 PM PDT 24
Peak memory 203520 kb
Host smart-e9bafae2-6cb0-41a7-b59a-2f85c235bc2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2672139806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2672139806
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.869809938
Short name T508
Test name
Test status
Simulation time 1200864414 ps
CPU time 16.69 seconds
Started Apr 18 12:42:28 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 203408 kb
Host smart-a1b15d3f-2df2-4a0f-a51b-506c6d14aebe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=869809938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.869809938
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.4026757057
Short name T521
Test name
Test status
Simulation time 400659048 ps
CPU time 17.13 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:43 PM PDT 24
Peak memory 211528 kb
Host smart-b6affadc-5878-448c-8d0a-6a2d43852a0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4026757057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.4026757057
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.452036356
Short name T242
Test name
Test status
Simulation time 50837608750 ps
CPU time 191.64 seconds
Started Apr 18 12:42:26 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 204672 kb
Host smart-ec4a62da-bac7-4aca-93cc-7d349a878ab9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=452036356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.452036356
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.585161603
Short name T336
Test name
Test status
Simulation time 35302854814 ps
CPU time 172.63 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:45:16 PM PDT 24
Peak memory 211648 kb
Host smart-b2059f20-52be-4487-9937-3ec9d8fcb9cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=585161603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.585161603
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.2262455817
Short name T399
Test name
Test status
Simulation time 55223032 ps
CPU time 7.05 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:33 PM PDT 24
Peak memory 204440 kb
Host smart-5497982e-0c62-4f21-b577-21dff6e2ad26
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262455817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2262455817
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.1404599869
Short name T888
Test name
Test status
Simulation time 429283763 ps
CPU time 16.95 seconds
Started Apr 18 12:42:28 PM PDT 24
Finished Apr 18 12:42:46 PM PDT 24
Peak memory 204056 kb
Host smart-d9636fcc-61e3-4611-9ff3-bc2139a0017d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1404599869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1404599869
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.1078910716
Short name T312
Test name
Test status
Simulation time 50355021 ps
CPU time 2.43 seconds
Started Apr 18 12:42:27 PM PDT 24
Finished Apr 18 12:42:30 PM PDT 24
Peak memory 203380 kb
Host smart-6b6b3cbd-364c-4659-9f98-e1e9df2d89c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1078910716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1078910716
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1240583546
Short name T360
Test name
Test status
Simulation time 11529582001 ps
CPU time 38.45 seconds
Started Apr 18 12:42:53 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 203524 kb
Host smart-4382061a-c4f3-48a4-a30a-3eb25ed44e31
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240583546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1240583546
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2523715556
Short name T167
Test name
Test status
Simulation time 8959035250 ps
CPU time 34.57 seconds
Started Apr 18 12:42:28 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 203380 kb
Host smart-997a1580-a57b-4f70-950f-a828d18daa62
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2523715556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2523715556
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1987112548
Short name T624
Test name
Test status
Simulation time 54015303 ps
CPU time 2.03 seconds
Started Apr 18 12:42:27 PM PDT 24
Finished Apr 18 12:42:30 PM PDT 24
Peak memory 203304 kb
Host smart-ccecf06e-129e-4e15-9e11-84b087f8af7f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987112548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1987112548
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2793790358
Short name T766
Test name
Test status
Simulation time 600185654 ps
CPU time 27.36 seconds
Started Apr 18 12:42:32 PM PDT 24
Finished Apr 18 12:43:00 PM PDT 24
Peak memory 206180 kb
Host smart-1534b7af-a336-4a17-9f63-7ceee4b18676
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2793790358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2793790358
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3046887072
Short name T842
Test name
Test status
Simulation time 1403297379 ps
CPU time 118.43 seconds
Started Apr 18 12:42:28 PM PDT 24
Finished Apr 18 12:44:28 PM PDT 24
Peak memory 208244 kb
Host smart-44c0f764-431b-4997-9bac-259106e02b68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3046887072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3046887072
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2093592152
Short name T555
Test name
Test status
Simulation time 497528755 ps
CPU time 179.24 seconds
Started Apr 18 12:42:22 PM PDT 24
Finished Apr 18 12:45:22 PM PDT 24
Peak memory 207984 kb
Host smart-66678c34-3403-4e42-bcb5-e637ec8c3b1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2093592152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.2093592152
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2676413099
Short name T728
Test name
Test status
Simulation time 625793856 ps
CPU time 135.22 seconds
Started Apr 18 12:42:26 PM PDT 24
Finished Apr 18 12:44:43 PM PDT 24
Peak memory 210596 kb
Host smart-82fd0388-7c95-4a94-adc5-d4bc004c3d3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2676413099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.2676413099
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.980338708
Short name T67
Test name
Test status
Simulation time 3469748183 ps
CPU time 34.33 seconds
Started Apr 18 12:42:26 PM PDT 24
Finished Apr 18 12:43:02 PM PDT 24
Peak memory 205016 kb
Host smart-9a9cd1b6-9018-4dc6-8a14-5d1b9d5d7af9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=980338708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.980338708
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2557009276
Short name T655
Test name
Test status
Simulation time 551368004 ps
CPU time 39.67 seconds
Started Apr 18 12:42:21 PM PDT 24
Finished Apr 18 12:43:02 PM PDT 24
Peak memory 205272 kb
Host smart-6d654abd-ad5b-4537-8a53-074e6aeb82a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2557009276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2557009276
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3917770868
Short name T680
Test name
Test status
Simulation time 72911049394 ps
CPU time 461.02 seconds
Started Apr 18 12:42:26 PM PDT 24
Finished Apr 18 12:50:09 PM PDT 24
Peak memory 211632 kb
Host smart-30b38ff3-539e-4601-aa0d-273f71eb088f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3917770868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.3917770868
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.596572691
Short name T849
Test name
Test status
Simulation time 489861963 ps
CPU time 12.46 seconds
Started Apr 18 12:42:29 PM PDT 24
Finished Apr 18 12:42:42 PM PDT 24
Peak memory 203756 kb
Host smart-2511e2b7-4b08-4685-8ff7-1097bed9ef7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=596572691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.596572691
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.1349110629
Short name T695
Test name
Test status
Simulation time 73781683 ps
CPU time 8.93 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:42:47 PM PDT 24
Peak memory 203388 kb
Host smart-01248b3b-8910-419c-87cb-7cb4edade32b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1349110629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1349110629
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.4259723558
Short name T841
Test name
Test status
Simulation time 44536130 ps
CPU time 2.58 seconds
Started Apr 18 12:42:30 PM PDT 24
Finished Apr 18 12:42:34 PM PDT 24
Peak memory 203476 kb
Host smart-8becf257-c99a-410a-9519-fabee0ab0bb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4259723558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4259723558
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3413242055
Short name T309
Test name
Test status
Simulation time 13606054380 ps
CPU time 67.91 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:43:34 PM PDT 24
Peak memory 204536 kb
Host smart-e6e5bfd2-3e7f-4080-a51e-b46d07acbc58
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413242055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3413242055
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1715558676
Short name T719
Test name
Test status
Simulation time 12642265468 ps
CPU time 87.32 seconds
Started Apr 18 12:42:24 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 204948 kb
Host smart-91cde4f9-f414-4f1b-b0d1-601c73f0dddf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1715558676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1715558676
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2516813376
Short name T458
Test name
Test status
Simulation time 257615587 ps
CPU time 21.43 seconds
Started Apr 18 12:42:27 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 211528 kb
Host smart-085af880-6fc5-4596-83c1-37d94848c814
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516813376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2516813376
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.1785612671
Short name T213
Test name
Test status
Simulation time 399074058 ps
CPU time 11.43 seconds
Started Apr 18 12:42:24 PM PDT 24
Finished Apr 18 12:42:36 PM PDT 24
Peak memory 203992 kb
Host smart-e1358271-fdd0-4d4a-8de8-b4162ff5a7e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1785612671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1785612671
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.223970720
Short name T825
Test name
Test status
Simulation time 1022947919 ps
CPU time 4.36 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:31 PM PDT 24
Peak memory 203376 kb
Host smart-c815cf55-100f-4203-af2f-3b211e476dec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=223970720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.223970720
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1939739952
Short name T74
Test name
Test status
Simulation time 9415921368 ps
CPU time 33.69 seconds
Started Apr 18 12:42:29 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 203544 kb
Host smart-224f9422-d805-45d9-a596-d6bda8ae134c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939739952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1939739952
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2843365610
Short name T414
Test name
Test status
Simulation time 3133336885 ps
CPU time 26.56 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:42:53 PM PDT 24
Peak memory 203432 kb
Host smart-d139782d-38fb-4425-bf7f-83d4b64844e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2843365610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2843365610
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1658940679
Short name T306
Test name
Test status
Simulation time 31015020 ps
CPU time 2.08 seconds
Started Apr 18 12:42:27 PM PDT 24
Finished Apr 18 12:42:30 PM PDT 24
Peak memory 203468 kb
Host smart-4ed393b0-5e91-4be7-93ad-f4fb9db9bf78
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658940679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1658940679
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1355480953
Short name T781
Test name
Test status
Simulation time 1062986010 ps
CPU time 114.71 seconds
Started Apr 18 12:42:25 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 205872 kb
Host smart-abe06c9a-8ec1-4383-a75e-559d0c5427f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1355480953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1355480953
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.94177296
Short name T697
Test name
Test status
Simulation time 342466569 ps
CPU time 27.4 seconds
Started Apr 18 12:42:31 PM PDT 24
Finished Apr 18 12:43:00 PM PDT 24
Peak memory 205112 kb
Host smart-07082a26-7b75-467f-b021-b6fa23a0f2c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94177296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.94177296
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1620296710
Short name T107
Test name
Test status
Simulation time 4851996849 ps
CPU time 226.45 seconds
Started Apr 18 12:42:34 PM PDT 24
Finished Apr 18 12:46:22 PM PDT 24
Peak memory 208432 kb
Host smart-2512ac6d-40bf-44b1-bfd1-6bea9262ac95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1620296710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.1620296710
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3487197840
Short name T617
Test name
Test status
Simulation time 9149809583 ps
CPU time 361.05 seconds
Started Apr 18 12:42:30 PM PDT 24
Finished Apr 18 12:48:32 PM PDT 24
Peak memory 219924 kb
Host smart-5012d0a7-f58b-42d9-a171-921c83246eb0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3487197840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.3487197840
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1400751749
Short name T783
Test name
Test status
Simulation time 743362541 ps
CPU time 15.84 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 205232 kb
Host smart-a1d632c5-0bce-454c-89f6-e2e4d51ad900
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1400751749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1400751749
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.4215372602
Short name T78
Test name
Test status
Simulation time 1071486532 ps
CPU time 18.06 seconds
Started Apr 18 12:42:31 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 211560 kb
Host smart-8197adc9-6e15-4df3-a76e-ae3ad5aa067e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4215372602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.4215372602
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1107345851
Short name T48
Test name
Test status
Simulation time 8577274832 ps
CPU time 57.2 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 205596 kb
Host smart-7084c98c-e224-4fe9-ace6-05590dbc95f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1107345851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.1107345851
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2684225892
Short name T272
Test name
Test status
Simulation time 718001586 ps
CPU time 15 seconds
Started Apr 18 12:42:39 PM PDT 24
Finished Apr 18 12:42:55 PM PDT 24
Peak memory 203516 kb
Host smart-03709f68-5fd7-4195-aae8-ed6e7596273c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2684225892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2684225892
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.3391281072
Short name T343
Test name
Test status
Simulation time 2383433958 ps
CPU time 29.12 seconds
Started Apr 18 12:42:33 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 203556 kb
Host smart-2a969026-cc8f-402b-8124-8a91c3d02d4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3391281072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3391281072
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.1845743081
Short name T227
Test name
Test status
Simulation time 474681526 ps
CPU time 13.26 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:42:49 PM PDT 24
Peak memory 204476 kb
Host smart-2e821a56-75c9-41aa-86f7-26590eef94ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1845743081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1845743081
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.552725557
Short name T651
Test name
Test status
Simulation time 109420270894 ps
CPU time 264.84 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:47:03 PM PDT 24
Peak memory 204944 kb
Host smart-06f8c876-db44-41cc-ae8b-b0af4df0c9d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=552725557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.552725557
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3499333497
Short name T470
Test name
Test status
Simulation time 33916080312 ps
CPU time 216.28 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:46:15 PM PDT 24
Peak memory 211592 kb
Host smart-ef3ce6b0-abd9-4781-a3b4-2ea70a0524a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3499333497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3499333497
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1871155445
Short name T468
Test name
Test status
Simulation time 283784807 ps
CPU time 17.23 seconds
Started Apr 18 12:42:33 PM PDT 24
Finished Apr 18 12:42:51 PM PDT 24
Peak memory 204644 kb
Host smart-3fd368ae-eb2e-4d46-84d0-36b780500040
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871155445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1871155445
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.3767394903
Short name T383
Test name
Test status
Simulation time 895953117 ps
CPU time 19.95 seconds
Started Apr 18 12:42:42 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 204176 kb
Host smart-669479e9-8992-4119-8367-5c272de995f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3767394903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3767394903
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.3567371922
Short name T515
Test name
Test status
Simulation time 175750507 ps
CPU time 3.39 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 203484 kb
Host smart-d8597a91-1026-40d9-98ba-8ffa4df6b36b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3567371922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3567371922
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3005453899
Short name T534
Test name
Test status
Simulation time 12600464699 ps
CPU time 34.51 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:43:13 PM PDT 24
Peak memory 203540 kb
Host smart-423d7933-3ccc-452b-9a9e-3ed2f5b096fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005453899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3005453899
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2689957034
Short name T537
Test name
Test status
Simulation time 3513410545 ps
CPU time 28.04 seconds
Started Apr 18 12:42:39 PM PDT 24
Finished Apr 18 12:43:07 PM PDT 24
Peak memory 203512 kb
Host smart-f8b301f8-8057-4fd6-85a3-feecc471faa3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2689957034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2689957034
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.566365527
Short name T79
Test name
Test status
Simulation time 35102296 ps
CPU time 2.05 seconds
Started Apr 18 12:42:31 PM PDT 24
Finished Apr 18 12:42:34 PM PDT 24
Peak memory 203344 kb
Host smart-d156aa0d-acf0-4d21-a22e-8e900ef0e4f0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566365527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.566365527
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.663493428
Short name T789
Test name
Test status
Simulation time 266025434 ps
CPU time 27.73 seconds
Started Apr 18 12:42:33 PM PDT 24
Finished Apr 18 12:43:01 PM PDT 24
Peak memory 204968 kb
Host smart-1bd55f4e-7abe-462f-a678-f016998dc265
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=663493428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.663493428
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1341638896
Short name T442
Test name
Test status
Simulation time 585230274 ps
CPU time 57.93 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:43:35 PM PDT 24
Peak memory 204808 kb
Host smart-d7102160-6c7e-4efd-be07-83dffec63b06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1341638896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1341638896
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3509776302
Short name T796
Test name
Test status
Simulation time 22135169 ps
CPU time 36.89 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:43:19 PM PDT 24
Peak memory 205352 kb
Host smart-ae337191-70bf-4f62-b342-5d35eacc6045
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3509776302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3509776302
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.607932096
Short name T708
Test name
Test status
Simulation time 2268452317 ps
CPU time 412.7 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:49:29 PM PDT 24
Peak memory 228112 kb
Host smart-ad9576da-5f19-4411-ba1d-6c49c040ebfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=607932096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res
et_error.607932096
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4247985753
Short name T593
Test name
Test status
Simulation time 190358337 ps
CPU time 20.29 seconds
Started Apr 18 12:42:43 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 204996 kb
Host smart-806cfe41-6b41-421f-871e-198c8abd0e37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4247985753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4247985753
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3199275072
Short name T54
Test name
Test status
Simulation time 4764547284 ps
CPU time 58.52 seconds
Started Apr 18 12:42:31 PM PDT 24
Finished Apr 18 12:43:31 PM PDT 24
Peak memory 206732 kb
Host smart-b21837bc-f02d-43d8-a5a0-384b8c6f321c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3199275072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3199275072
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2889786908
Short name T479
Test name
Test status
Simulation time 34033899776 ps
CPU time 102.67 seconds
Started Apr 18 12:42:29 PM PDT 24
Finished Apr 18 12:44:12 PM PDT 24
Peak memory 205872 kb
Host smart-13667ba3-2cb6-491d-9553-46da935cfcc4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2889786908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.2889786908
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2702854781
Short name T314
Test name
Test status
Simulation time 785962982 ps
CPU time 18.53 seconds
Started Apr 18 12:42:33 PM PDT 24
Finished Apr 18 12:42:52 PM PDT 24
Peak memory 203860 kb
Host smart-4e70b12f-ad1e-4b44-90d2-96f9ac1e9089
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2702854781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2702854781
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.2552493831
Short name T633
Test name
Test status
Simulation time 1532919225 ps
CPU time 13.97 seconds
Started Apr 18 12:42:38 PM PDT 24
Finished Apr 18 12:42:53 PM PDT 24
Peak memory 203492 kb
Host smart-7936f044-9252-4191-8f62-1a279dbaf0b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2552493831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2552493831
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.3737365538
Short name T161
Test name
Test status
Simulation time 610416450 ps
CPU time 21.23 seconds
Started Apr 18 12:42:38 PM PDT 24
Finished Apr 18 12:43:00 PM PDT 24
Peak memory 211684 kb
Host smart-d0d9f5e9-f8f1-4e3b-9fde-a74168f12cb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3737365538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3737365538
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3424237778
Short name T600
Test name
Test status
Simulation time 5454598115 ps
CPU time 35.46 seconds
Started Apr 18 12:42:30 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 204832 kb
Host smart-1e4795d7-6f50-4b4e-8bba-6028cdf5a03a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424237778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3424237778
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3640938459
Short name T264
Test name
Test status
Simulation time 33968266064 ps
CPU time 211.65 seconds
Started Apr 18 12:42:34 PM PDT 24
Finished Apr 18 12:46:07 PM PDT 24
Peak memory 211548 kb
Host smart-3a2128ab-eb04-493d-b4bc-6a90b403662e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3640938459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3640938459
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3445644873
Short name T152
Test name
Test status
Simulation time 50358417 ps
CPU time 4.91 seconds
Started Apr 18 12:42:39 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 204596 kb
Host smart-8315255f-19e4-4708-a494-10c8c2fdf1c9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445644873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3445644873
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.1012506930
Short name T834
Test name
Test status
Simulation time 51563298 ps
CPU time 3.9 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:42:40 PM PDT 24
Peak memory 203684 kb
Host smart-91935b01-f1ed-4a21-8054-badafba6dd57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1012506930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1012506930
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.1139437813
Short name T205
Test name
Test status
Simulation time 180252419 ps
CPU time 4.74 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:42:42 PM PDT 24
Peak memory 203384 kb
Host smart-200fe63e-cd20-47ae-a06a-3d5de814de8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1139437813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1139437813
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2645660037
Short name T375
Test name
Test status
Simulation time 4918920411 ps
CPU time 26.32 seconds
Started Apr 18 12:42:39 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 203544 kb
Host smart-59ebe71e-09f7-4178-b3d2-56c28f2caacf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645660037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2645660037
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2716469545
Short name T284
Test name
Test status
Simulation time 11813097147 ps
CPU time 32.98 seconds
Started Apr 18 12:42:38 PM PDT 24
Finished Apr 18 12:43:12 PM PDT 24
Peak memory 203408 kb
Host smart-e8664045-15b1-49f2-bc79-c1a1968dca7f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2716469545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2716469545
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3286347714
Short name T12
Test name
Test status
Simulation time 24877380 ps
CPU time 2.26 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:42:39 PM PDT 24
Peak memory 203480 kb
Host smart-791a256c-6a65-4a71-b6b5-cf405b0b2199
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286347714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3286347714
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.388889615
Short name T779
Test name
Test status
Simulation time 110831159 ps
CPU time 20.04 seconds
Started Apr 18 12:42:30 PM PDT 24
Finished Apr 18 12:42:51 PM PDT 24
Peak memory 206480 kb
Host smart-6a187488-adb8-44f7-acc0-ec74f5c47687
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=388889615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.388889615
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3889890534
Short name T451
Test name
Test status
Simulation time 13351934488 ps
CPU time 170.41 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:45:27 PM PDT 24
Peak memory 207956 kb
Host smart-beb3c4e0-6460-4646-aa8f-ca3cdf21743c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3889890534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3889890534
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.825105877
Short name T325
Test name
Test status
Simulation time 101774856 ps
CPU time 37.52 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:43:14 PM PDT 24
Peak memory 208148 kb
Host smart-480ee6ce-9b83-41a1-8b08-a73158a33fc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=825105877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand
_reset.825105877
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1833566020
Short name T562
Test name
Test status
Simulation time 7397244 ps
CPU time 9.87 seconds
Started Apr 18 12:42:31 PM PDT 24
Finished Apr 18 12:42:42 PM PDT 24
Peak memory 204088 kb
Host smart-88283873-691c-4bdc-b748-235fbb464ea3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1833566020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1833566020
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1994274506
Short name T181
Test name
Test status
Simulation time 110804718 ps
CPU time 16.59 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:42:52 PM PDT 24
Peak memory 211676 kb
Host smart-cb493d52-3f27-4c27-9bf3-6a4e64d35b23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1994274506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1994274506
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.4076445298
Short name T369
Test name
Test status
Simulation time 320787116 ps
CPU time 23.11 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:43:01 PM PDT 24
Peak memory 204404 kb
Host smart-dab62fd8-0129-46c4-a6e1-95a0156b8266
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4076445298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4076445298
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2929805735
Short name T471
Test name
Test status
Simulation time 282869825351 ps
CPU time 508.17 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:51:05 PM PDT 24
Peak memory 206804 kb
Host smart-56556a36-8c10-4f49-beac-cdf1720622b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2929805735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.2929805735
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2620394728
Short name T319
Test name
Test status
Simulation time 527808942 ps
CPU time 8.42 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:42:51 PM PDT 24
Peak memory 203500 kb
Host smart-fe301fbd-9623-4ff4-b362-a6ab002c3a63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2620394728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2620394728
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.2033580092
Short name T784
Test name
Test status
Simulation time 108245648 ps
CPU time 11.4 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:42:53 PM PDT 24
Peak memory 203352 kb
Host smart-72432aa6-3076-45c7-b61c-11279dbc5e22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2033580092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2033580092
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.852101517
Short name T607
Test name
Test status
Simulation time 1144372077 ps
CPU time 24.22 seconds
Started Apr 18 12:42:34 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 204864 kb
Host smart-0b5c9a51-6bfa-497f-9c5b-1975583e46a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=852101517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.852101517
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1357470145
Short name T798
Test name
Test status
Simulation time 7668085810 ps
CPU time 25.01 seconds
Started Apr 18 12:42:33 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 211576 kb
Host smart-01bacd4c-6853-450d-96a1-08c693ceb3e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357470145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1357470145
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2640034459
Short name T590
Test name
Test status
Simulation time 81727152076 ps
CPU time 194 seconds
Started Apr 18 12:42:42 PM PDT 24
Finished Apr 18 12:45:57 PM PDT 24
Peak memory 204680 kb
Host smart-9c1db0d4-d2c5-43f8-822f-1d9a46ae1540
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2640034459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2640034459
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3396352770
Short name T224
Test name
Test status
Simulation time 201770062 ps
CPU time 10.66 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:42:48 PM PDT 24
Peak memory 204576 kb
Host smart-bfe937c9-66d0-467d-8368-5325fe307e9a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396352770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3396352770
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.4097777752
Short name T131
Test name
Test status
Simulation time 180113040 ps
CPU time 9.86 seconds
Started Apr 18 12:42:34 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 204064 kb
Host smart-99695502-6869-4018-8ddd-22790a032e67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4097777752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4097777752
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.1978091432
Short name T254
Test name
Test status
Simulation time 174903251 ps
CPU time 3.48 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 203396 kb
Host smart-31c2590a-ca5a-413b-a5d4-c9c2bec0e27c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1978091432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1978091432
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2514474401
Short name T676
Test name
Test status
Simulation time 7556067306 ps
CPU time 31.72 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:43:08 PM PDT 24
Peak memory 203528 kb
Host smart-ee0bbfde-f4f4-4ceb-8a93-21447733ce8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514474401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2514474401
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.483185181
Short name T876
Test name
Test status
Simulation time 4010828663 ps
CPU time 29.6 seconds
Started Apr 18 12:42:34 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 203532 kb
Host smart-11695af5-c99c-489c-be3f-4f3127c35f0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=483185181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.483185181
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2602898046
Short name T733
Test name
Test status
Simulation time 36391641 ps
CPU time 2.18 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:42:38 PM PDT 24
Peak memory 203348 kb
Host smart-58ad555e-1cd6-4374-8b4b-47dc6ffb37ef
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602898046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2602898046
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.4268644626
Short name T856
Test name
Test status
Simulation time 115601898 ps
CPU time 17.92 seconds
Started Apr 18 12:42:33 PM PDT 24
Finished Apr 18 12:42:52 PM PDT 24
Peak memory 205132 kb
Host smart-40c2be2c-6be3-46fe-80d4-726ae0a7d44c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4268644626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4268644626
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1713120517
Short name T491
Test name
Test status
Simulation time 121149645 ps
CPU time 16.06 seconds
Started Apr 18 12:42:42 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 204368 kb
Host smart-f083a13c-5a33-4f02-a357-9177f2ddae74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1713120517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1713120517
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1709701858
Short name T29
Test name
Test status
Simulation time 5764742812 ps
CPU time 239.61 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:46:37 PM PDT 24
Peak memory 210484 kb
Host smart-c0632923-15a1-4c66-943c-2fa03584bef9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1709701858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.1709701858
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.856811448
Short name T412
Test name
Test status
Simulation time 483186226 ps
CPU time 196.4 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:45:55 PM PDT 24
Peak memory 211652 kb
Host smart-256639b0-9422-4e2c-a52d-092274a6f0af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856811448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res
et_error.856811448
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.652429560
Short name T378
Test name
Test status
Simulation time 698919810 ps
CPU time 23.7 seconds
Started Apr 18 12:42:52 PM PDT 24
Finished Apr 18 12:43:16 PM PDT 24
Peak memory 205040 kb
Host smart-d5e650b4-9a7b-4ae2-9ad5-61523e350e4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=652429560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.652429560
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1610291599
Short name T202
Test name
Test status
Simulation time 2256352574 ps
CPU time 64.15 seconds
Started Apr 18 12:42:33 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 206116 kb
Host smart-c829d8db-b5cc-4d8d-bbbe-64472b5eff22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1610291599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1610291599
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1874843875
Short name T547
Test name
Test status
Simulation time 292303113755 ps
CPU time 611.83 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:52:48 PM PDT 24
Peak memory 211724 kb
Host smart-08d6bbdc-7de5-4d14-8b6e-5a6788564ce3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1874843875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.1874843875
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2506189362
Short name T459
Test name
Test status
Simulation time 2525016327 ps
CPU time 22.9 seconds
Started Apr 18 12:42:55 PM PDT 24
Finished Apr 18 12:43:20 PM PDT 24
Peak memory 203972 kb
Host smart-1df818e8-f95a-4ad7-9105-106420b70d04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2506189362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2506189362
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2219455708
Short name T741
Test name
Test status
Simulation time 729009345 ps
CPU time 25.8 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:43:02 PM PDT 24
Peak memory 203484 kb
Host smart-da415958-6ac8-4b32-8aab-dfd39e3df4bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219455708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2219455708
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.3109068111
Short name T208
Test name
Test status
Simulation time 199025387 ps
CPU time 24.01 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:43:02 PM PDT 24
Peak memory 204772 kb
Host smart-ba3f435a-a630-428e-9448-ff9367dc7fff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3109068111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3109068111
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3863587333
Short name T747
Test name
Test status
Simulation time 4027326299 ps
CPU time 25.64 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:43:01 PM PDT 24
Peak memory 204384 kb
Host smart-851c5bd3-5b4f-4229-a047-406410298b6f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863587333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3863587333
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.4003162104
Short name T248
Test name
Test status
Simulation time 54060908608 ps
CPU time 195.48 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:45:53 PM PDT 24
Peak memory 211680 kb
Host smart-d755625a-0267-4efa-b94a-c1c8ccf219a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4003162104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.4003162104
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.4246242179
Short name T492
Test name
Test status
Simulation time 100360450 ps
CPU time 15.27 seconds
Started Apr 18 12:42:35 PM PDT 24
Finished Apr 18 12:42:52 PM PDT 24
Peak memory 211516 kb
Host smart-10c99de9-038c-4ffd-804a-898909c93164
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246242179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4246242179
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.3092868568
Short name T528
Test name
Test status
Simulation time 425693691 ps
CPU time 16.82 seconds
Started Apr 18 12:42:39 PM PDT 24
Finished Apr 18 12:42:56 PM PDT 24
Peak memory 204140 kb
Host smart-36815ae8-6177-4bf2-8d6c-b8f96ce88d21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3092868568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3092868568
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.3969546327
Short name T329
Test name
Test status
Simulation time 64375789 ps
CPU time 2.32 seconds
Started Apr 18 12:42:40 PM PDT 24
Finished Apr 18 12:42:44 PM PDT 24
Peak memory 203380 kb
Host smart-390b1d60-7e41-4109-9540-e7c1f7bd6030
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3969546327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3969546327
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2483367940
Short name T44
Test name
Test status
Simulation time 14962927334 ps
CPU time 37.78 seconds
Started Apr 18 12:42:42 PM PDT 24
Finished Apr 18 12:43:20 PM PDT 24
Peak memory 203544 kb
Host smart-ef233f5c-6291-4bc8-bb17-c47e8610337d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483367940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2483367940
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3925597907
Short name T612
Test name
Test status
Simulation time 5136159916 ps
CPU time 24.69 seconds
Started Apr 18 12:42:34 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 203508 kb
Host smart-097ca6d8-c1d8-4ce9-925f-7fcf5fff8d8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3925597907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3925597907
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2002749163
Short name T669
Test name
Test status
Simulation time 29777540 ps
CPU time 2.14 seconds
Started Apr 18 12:42:36 PM PDT 24
Finished Apr 18 12:42:39 PM PDT 24
Peak memory 203356 kb
Host smart-e9731019-0021-4177-a356-57b8ff2e3579
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002749163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2002749163
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2732783623
Short name T61
Test name
Test status
Simulation time 15960695411 ps
CPU time 319.37 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:47:57 PM PDT 24
Peak memory 207484 kb
Host smart-bc4468dc-25f0-433f-add4-51df2b5c662c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2732783623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2732783623
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1719147718
Short name T273
Test name
Test status
Simulation time 1294529889 ps
CPU time 130.2 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:44:56 PM PDT 24
Peak memory 208460 kb
Host smart-f8035bd9-4e3e-4ada-8635-d7b5a0517505
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1719147718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1719147718
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.405274164
Short name T628
Test name
Test status
Simulation time 178943635 ps
CPU time 44.62 seconds
Started Apr 18 12:42:43 PM PDT 24
Finished Apr 18 12:43:29 PM PDT 24
Peak memory 207052 kb
Host smart-cf5e660f-3797-4c89-9724-52a3aaa4560f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=405274164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand
_reset.405274164
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3931021161
Short name T172
Test name
Test status
Simulation time 264317802 ps
CPU time 40.76 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:43:25 PM PDT 24
Peak memory 207556 kb
Host smart-8caead3b-b438-4b0e-99d6-da8e1ae477cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3931021161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.3931021161
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2951240635
Short name T516
Test name
Test status
Simulation time 64040100 ps
CPU time 3.48 seconds
Started Apr 18 12:42:37 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 211672 kb
Host smart-38aee158-ba5e-4ce5-a9cf-81ce27b78d7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2951240635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2951240635
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2196263631
Short name T576
Test name
Test status
Simulation time 249161937 ps
CPU time 13.4 seconds
Started Apr 18 12:42:43 PM PDT 24
Finished Apr 18 12:42:57 PM PDT 24
Peak memory 205644 kb
Host smart-0d09f030-787d-4c70-9546-c835d2bc4f2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2196263631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2196263631
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1778727323
Short name T869
Test name
Test status
Simulation time 201248047378 ps
CPU time 606.96 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:52:53 PM PDT 24
Peak memory 207364 kb
Host smart-5a973384-7960-4b0c-a658-416e73021cca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1778727323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1778727323
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1052340663
Short name T522
Test name
Test status
Simulation time 74499550 ps
CPU time 7.18 seconds
Started Apr 18 12:42:53 PM PDT 24
Finished Apr 18 12:43:01 PM PDT 24
Peak memory 203424 kb
Host smart-545759ec-b49f-41b6-8f38-c412de88f3ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1052340663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1052340663
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.592797915
Short name T540
Test name
Test status
Simulation time 1171861186 ps
CPU time 35.51 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:22 PM PDT 24
Peak memory 203548 kb
Host smart-31078c8b-35d2-4874-b0c3-3b45ec60afcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=592797915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.592797915
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.607123572
Short name T55
Test name
Test status
Simulation time 3889452971 ps
CPU time 30.74 seconds
Started Apr 18 12:42:40 PM PDT 24
Finished Apr 18 12:43:11 PM PDT 24
Peak memory 211620 kb
Host smart-27d9ee96-22d6-455e-9484-9dd46b9ead80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=607123572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.607123572
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1628251798
Short name T642
Test name
Test status
Simulation time 2930238201 ps
CPU time 16.99 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 203420 kb
Host smart-5df37498-42d7-423c-8847-abb06a3475bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628251798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1628251798
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.299997417
Short name T230
Test name
Test status
Simulation time 21780710677 ps
CPU time 185.98 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:45:50 PM PDT 24
Peak memory 205088 kb
Host smart-83d5be4a-ad77-4faf-b877-3d9f9afee37a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=299997417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.299997417
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.793091507
Short name T625
Test name
Test status
Simulation time 182646859 ps
CPU time 20.59 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:07 PM PDT 24
Peak memory 204400 kb
Host smart-0f8b922f-3c5c-411e-a655-600f6b79ffa2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793091507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.793091507
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.1787132691
Short name T81
Test name
Test status
Simulation time 2731364531 ps
CPU time 34.71 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:43:17 PM PDT 24
Peak memory 204108 kb
Host smart-634419c4-097c-4cb0-bdc0-7adf6ada75a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1787132691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1787132691
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.2375853125
Short name T385
Test name
Test status
Simulation time 870854163 ps
CPU time 3.99 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 203428 kb
Host smart-0759679d-2aaf-435d-b1f5-fc8bd6f693e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2375853125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2375853125
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4130370396
Short name T478
Test name
Test status
Simulation time 4957114413 ps
CPU time 26.61 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:43:08 PM PDT 24
Peak memory 203516 kb
Host smart-9f0a03c0-fbe6-4f51-97f0-b08dc758cc2d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130370396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4130370396
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2140435230
Short name T388
Test name
Test status
Simulation time 3433650745 ps
CPU time 25 seconds
Started Apr 18 12:42:56 PM PDT 24
Finished Apr 18 12:43:22 PM PDT 24
Peak memory 203536 kb
Host smart-bc8e0a9b-83f5-40d2-ba5d-31c540af9b6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2140435230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2140435230
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2555310268
Short name T597
Test name
Test status
Simulation time 26539379 ps
CPU time 2.18 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:42:47 PM PDT 24
Peak memory 203468 kb
Host smart-049343d3-1656-412c-8ef3-4a1f06d9e64a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555310268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2555310268
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3632104139
Short name T753
Test name
Test status
Simulation time 1008540489 ps
CPU time 103.67 seconds
Started Apr 18 12:42:39 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 206972 kb
Host smart-2ad42754-f8a9-485d-8622-a28efc554ffb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3632104139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3632104139
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.450969324
Short name T236
Test name
Test status
Simulation time 943681529 ps
CPU time 58.01 seconds
Started Apr 18 12:43:12 PM PDT 24
Finished Apr 18 12:44:11 PM PDT 24
Peak memory 207028 kb
Host smart-dc89c067-0436-4d1e-b92d-e24fefc51f48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=450969324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.450969324
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3134337893
Short name T215
Test name
Test status
Simulation time 332182725 ps
CPU time 146.18 seconds
Started Apr 18 12:42:43 PM PDT 24
Finished Apr 18 12:45:10 PM PDT 24
Peak memory 207964 kb
Host smart-3ca7920d-6a81-46c6-8cc7-8e7d5d92f013
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3134337893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.3134337893
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1759728835
Short name T704
Test name
Test status
Simulation time 99975192 ps
CPU time 85.73 seconds
Started Apr 18 12:42:39 PM PDT 24
Finished Apr 18 12:44:06 PM PDT 24
Peak memory 208740 kb
Host smart-03954f22-ad1a-4eaf-a090-fa841317d35c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1759728835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.1759728835
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.4082329225
Short name T77
Test name
Test status
Simulation time 37765342 ps
CPU time 2.91 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:42:48 PM PDT 24
Peak memory 204448 kb
Host smart-6ff04cde-3176-47b9-ac10-813f13d67757
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4082329225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4082329225
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2691506308
Short name T258
Test name
Test status
Simulation time 357648056 ps
CPU time 29.27 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:43:11 PM PDT 24
Peak memory 204536 kb
Host smart-b326403a-76e2-4808-95de-31ce77738334
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2691506308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2691506308
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3029673697
Short name T657
Test name
Test status
Simulation time 67474209139 ps
CPU time 178.5 seconds
Started Apr 18 12:42:40 PM PDT 24
Finished Apr 18 12:45:40 PM PDT 24
Peak memory 206312 kb
Host smart-2f39c109-f33a-44c4-ba5f-5241d96ff5f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3029673697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.3029673697
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1386660485
Short name T288
Test name
Test status
Simulation time 550269021 ps
CPU time 21.52 seconds
Started Apr 18 12:42:50 PM PDT 24
Finished Apr 18 12:43:12 PM PDT 24
Peak memory 203840 kb
Host smart-8f1c703b-1585-47e8-99ac-313fd970759e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1386660485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1386660485
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.3259261043
Short name T2
Test name
Test status
Simulation time 891857640 ps
CPU time 33.74 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:43:16 PM PDT 24
Peak memory 203408 kb
Host smart-31d80556-810f-4d57-8693-6cfb5b65d8e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3259261043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3259261043
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.1470764172
Short name T247
Test name
Test status
Simulation time 1646036242 ps
CPU time 37.27 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:23 PM PDT 24
Peak memory 204792 kb
Host smart-5df8b43b-7787-41fe-bf1f-a9d8d13401b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1470764172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1470764172
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1963466595
Short name T801
Test name
Test status
Simulation time 41848771655 ps
CPU time 237.52 seconds
Started Apr 18 12:42:43 PM PDT 24
Finished Apr 18 12:46:41 PM PDT 24
Peak memory 204988 kb
Host smart-5cb2f1c5-bc05-4cde-9039-525fa1fb675e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963466595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1963466595
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1423452719
Short name T545
Test name
Test status
Simulation time 31534450238 ps
CPU time 187.64 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:45:54 PM PDT 24
Peak memory 211628 kb
Host smart-3acb5c2a-7ec3-4349-af00-01fa9d0a0142
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1423452719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1423452719
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1678066397
Short name T198
Test name
Test status
Simulation time 232449719 ps
CPU time 8.12 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:42:53 PM PDT 24
Peak memory 204516 kb
Host smart-28b398ce-8a6f-40be-80de-85e05e8b68ad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678066397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1678066397
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.2434504205
Short name T465
Test name
Test status
Simulation time 423004774 ps
CPU time 16.72 seconds
Started Apr 18 12:42:42 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 204128 kb
Host smart-95298bfa-970d-4f00-8aed-7178750527c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2434504205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2434504205
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.2094761074
Short name T855
Test name
Test status
Simulation time 52318945 ps
CPU time 2.12 seconds
Started Apr 18 12:42:47 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 203488 kb
Host smart-737e43f3-cb1e-4b55-9d62-774bf65859df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2094761074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2094761074
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3210631496
Short name T526
Test name
Test status
Simulation time 11378578677 ps
CPU time 36.94 seconds
Started Apr 18 12:42:42 PM PDT 24
Finished Apr 18 12:43:20 PM PDT 24
Peak memory 203388 kb
Host smart-9465a8ff-7abb-4d57-ae89-4b28132ff392
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210631496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3210631496
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1561798941
Short name T774
Test name
Test status
Simulation time 6514139080 ps
CPU time 28.67 seconds
Started Apr 18 12:42:41 PM PDT 24
Finished Apr 18 12:43:11 PM PDT 24
Peak memory 203532 kb
Host smart-93ba24b5-b56b-47fc-97b8-d6589dcecca6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1561798941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1561798941
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3950277886
Short name T41
Test name
Test status
Simulation time 49750404 ps
CPU time 2.26 seconds
Started Apr 18 12:42:42 PM PDT 24
Finished Apr 18 12:42:45 PM PDT 24
Peak memory 203476 kb
Host smart-2efb90b6-1486-48f3-9ec5-58c94138bbd8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950277886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3950277886
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3991473609
Short name T135
Test name
Test status
Simulation time 2592039673 ps
CPU time 93.22 seconds
Started Apr 18 12:42:48 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 206160 kb
Host smart-d01d27d2-d0e5-4a3e-ab2e-7355eb78f359
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3991473609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3991473609
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1295867784
Short name T103
Test name
Test status
Simulation time 1777042753 ps
CPU time 43.92 seconds
Started Apr 18 12:42:53 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 205296 kb
Host smart-9a2b0c15-a94f-4899-a48e-55e7f453cf42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1295867784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1295867784
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2350369533
Short name T183
Test name
Test status
Simulation time 3834182341 ps
CPU time 459.3 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:50:25 PM PDT 24
Peak memory 221876 kb
Host smart-8256ea24-983b-4356-9dd3-475075652541
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2350369533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.2350369533
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3139319816
Short name T95
Test name
Test status
Simulation time 491375557 ps
CPU time 17.87 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 205028 kb
Host smart-9005613b-ef3d-4376-88a1-5f6a142cd215
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3139319816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3139319816
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3656419485
Short name T450
Test name
Test status
Simulation time 427239784 ps
CPU time 17.02 seconds
Started Apr 18 12:42:46 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 204700 kb
Host smart-0da623eb-a946-4c42-ae03-3b0f3ffb18e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3656419485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3656419485
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3815896072
Short name T82
Test name
Test status
Simulation time 8622903188 ps
CPU time 77.32 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:44:13 PM PDT 24
Peak memory 206044 kb
Host smart-630069ab-44da-478d-aa3f-d9142f73176e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3815896072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.3815896072
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2189705377
Short name T604
Test name
Test status
Simulation time 815611037 ps
CPU time 16.51 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 203932 kb
Host smart-cb22582b-b800-40b6-9a58-11ba8abc6bc1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2189705377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2189705377
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.1783882436
Short name T686
Test name
Test status
Simulation time 1524012283 ps
CPU time 24.93 seconds
Started Apr 18 12:42:48 PM PDT 24
Finished Apr 18 12:43:14 PM PDT 24
Peak memory 203388 kb
Host smart-f2327c2d-5c62-447f-8d27-d10040ae4416
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1783882436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1783882436
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.633581494
Short name T863
Test name
Test status
Simulation time 4894501171 ps
CPU time 42.37 seconds
Started Apr 18 12:42:56 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 205280 kb
Host smart-74448ba6-03b7-4a39-8408-98bb3af209c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=633581494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.633581494
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1715575700
Short name T370
Test name
Test status
Simulation time 3976057637 ps
CPU time 13.45 seconds
Started Apr 18 12:42:46 PM PDT 24
Finished Apr 18 12:43:00 PM PDT 24
Peak memory 203524 kb
Host smart-7fba9663-8809-40f0-baf6-eb62958ce1f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715575700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1715575700
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1466241904
Short name T346
Test name
Test status
Simulation time 34635053569 ps
CPU time 213.67 seconds
Started Apr 18 12:42:49 PM PDT 24
Finished Apr 18 12:46:23 PM PDT 24
Peak memory 204920 kb
Host smart-ae3f5d18-0379-4e3f-ac0d-9febb51ea363
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1466241904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1466241904
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1619226923
Short name T8
Test name
Test status
Simulation time 140845845 ps
CPU time 12.53 seconds
Started Apr 18 12:42:46 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 204728 kb
Host smart-6d943a6d-b2a1-47a7-9a80-842d006c714d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619226923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1619226923
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.1210513071
Short name T265
Test name
Test status
Simulation time 1422370841 ps
CPU time 23.41 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:09 PM PDT 24
Peak memory 203984 kb
Host smart-096a5728-9b80-4457-87f5-926b39a50a3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1210513071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1210513071
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.1908134873
Short name T663
Test name
Test status
Simulation time 34938476 ps
CPU time 2.04 seconds
Started Apr 18 12:42:46 PM PDT 24
Finished Apr 18 12:42:49 PM PDT 24
Peak memory 203400 kb
Host smart-902b3172-8c93-4b3c-88a8-34817c295026
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1908134873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1908134873
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2720685242
Short name T724
Test name
Test status
Simulation time 6178676597 ps
CPU time 36.99 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:43:23 PM PDT 24
Peak memory 203540 kb
Host smart-0d16aebf-d0e3-496d-a933-38ade366b4b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720685242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2720685242
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2796615174
Short name T811
Test name
Test status
Simulation time 3204238000 ps
CPU time 25.26 seconds
Started Apr 18 12:42:47 PM PDT 24
Finished Apr 18 12:43:12 PM PDT 24
Peak memory 203532 kb
Host smart-ecb74dd8-0842-439a-8228-7ad1b79b24e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2796615174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2796615174
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3301023861
Short name T441
Test name
Test status
Simulation time 68144660 ps
CPU time 2.51 seconds
Started Apr 18 12:42:51 PM PDT 24
Finished Apr 18 12:42:54 PM PDT 24
Peak memory 203372 kb
Host smart-9efc932b-0873-4cfd-b0d6-f26cce091320
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301023861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3301023861
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1834153626
Short name T333
Test name
Test status
Simulation time 253865461 ps
CPU time 35.29 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:21 PM PDT 24
Peak memory 205388 kb
Host smart-d7619870-3915-4b00-9d3a-e18fa1b8854e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1834153626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1834153626
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2705816836
Short name T355
Test name
Test status
Simulation time 1516296282 ps
CPU time 103.35 seconds
Started Apr 18 12:42:49 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 205264 kb
Host smart-bc535b46-0705-48a8-8092-a6cbe0586d88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2705816836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2705816836
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.143971990
Short name T656
Test name
Test status
Simulation time 14021431827 ps
CPU time 273.19 seconds
Started Apr 18 12:42:49 PM PDT 24
Finished Apr 18 12:47:22 PM PDT 24
Peak memory 212704 kb
Host smart-933e74ab-9528-40f1-9028-e3dd4376dd8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=143971990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.143971990
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.158536282
Short name T233
Test name
Test status
Simulation time 85165940 ps
CPU time 9.34 seconds
Started Apr 18 12:42:47 PM PDT 24
Finished Apr 18 12:42:57 PM PDT 24
Peak memory 204840 kb
Host smart-d3246b4c-62e1-43d3-91a7-d175bee99fc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=158536282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.158536282
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3292276424
Short name T53
Test name
Test status
Simulation time 106710151 ps
CPU time 8.31 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:20 PM PDT 24
Peak memory 204168 kb
Host smart-e72dba61-66dc-4de5-9e97-d09eaeed3432
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3292276424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3292276424
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2212670442
Short name T277
Test name
Test status
Simulation time 123434847094 ps
CPU time 589.39 seconds
Started Apr 18 12:41:11 PM PDT 24
Finished Apr 18 12:51:02 PM PDT 24
Peak memory 207520 kb
Host smart-77c528ee-9aa2-4bc5-a233-b426aeb06fad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2212670442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.2212670442
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3361540640
Short name T750
Test name
Test status
Simulation time 545989958 ps
CPU time 23.21 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:29 PM PDT 24
Peak memory 204264 kb
Host smart-86affe1f-426a-489d-b467-2f04f7757b3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3361540640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3361540640
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.1001814290
Short name T318
Test name
Test status
Simulation time 839475815 ps
CPU time 33.46 seconds
Started Apr 18 12:40:59 PM PDT 24
Finished Apr 18 12:41:34 PM PDT 24
Peak memory 203652 kb
Host smart-f268c78f-ddf1-4cc6-9e8b-f2fbf89aebc9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1001814290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1001814290
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2194736623
Short name T408
Test name
Test status
Simulation time 882967319 ps
CPU time 23.74 seconds
Started Apr 18 12:41:11 PM PDT 24
Finished Apr 18 12:41:40 PM PDT 24
Peak memory 211672 kb
Host smart-594fb2c9-5dcc-49fd-b5d3-f233203c2fb1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2194736623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2194736623
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2815496822
Short name T611
Test name
Test status
Simulation time 3169262160 ps
CPU time 15.12 seconds
Started Apr 18 12:41:13 PM PDT 24
Finished Apr 18 12:41:29 PM PDT 24
Peak memory 203520 kb
Host smart-35108728-df20-45d3-b90f-3d93a306ef06
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815496822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2815496822
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.349296800
Short name T892
Test name
Test status
Simulation time 36505893593 ps
CPU time 217.09 seconds
Started Apr 18 12:41:02 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 211572 kb
Host smart-815dd866-16c8-4dad-a292-84f091a4f3e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=349296800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.349296800
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.380263368
Short name T335
Test name
Test status
Simulation time 130171722 ps
CPU time 5.65 seconds
Started Apr 18 12:41:08 PM PDT 24
Finished Apr 18 12:41:15 PM PDT 24
Peak memory 204592 kb
Host smart-f23b4ae4-d903-485d-9933-ce12552b9352
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380263368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.380263368
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.697141332
Short name T358
Test name
Test status
Simulation time 215033689 ps
CPU time 4.81 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:15 PM PDT 24
Peak memory 203628 kb
Host smart-ba3c70d0-482c-4e9b-9cd3-f53643dad969
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=697141332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.697141332
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1088518812
Short name T356
Test name
Test status
Simulation time 161538526 ps
CPU time 3.49 seconds
Started Apr 18 12:40:59 PM PDT 24
Finished Apr 18 12:41:03 PM PDT 24
Peak memory 203504 kb
Host smart-9342179d-7d3e-45de-ba15-45d9dfd0be03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1088518812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1088518812
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1533159486
Short name T391
Test name
Test status
Simulation time 7205014801 ps
CPU time 27.14 seconds
Started Apr 18 12:40:57 PM PDT 24
Finished Apr 18 12:41:25 PM PDT 24
Peak memory 203500 kb
Host smart-079b32c6-5f10-4f67-a614-753bb81678ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533159486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1533159486
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2985843086
Short name T616
Test name
Test status
Simulation time 6941229064 ps
CPU time 32.99 seconds
Started Apr 18 12:41:14 PM PDT 24
Finished Apr 18 12:41:48 PM PDT 24
Peak memory 203544 kb
Host smart-fb250796-7891-4e55-9d99-2041a61165dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2985843086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2985843086
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3200202800
Short name T511
Test name
Test status
Simulation time 104927022 ps
CPU time 2.5 seconds
Started Apr 18 12:41:13 PM PDT 24
Finished Apr 18 12:41:16 PM PDT 24
Peak memory 203448 kb
Host smart-1b56dda3-f654-4066-bf41-05933f799fac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200202800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3200202800
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3484574296
Short name T684
Test name
Test status
Simulation time 96818458 ps
CPU time 12.65 seconds
Started Apr 18 12:41:13 PM PDT 24
Finished Apr 18 12:41:26 PM PDT 24
Peak memory 205000 kb
Host smart-c815fe3c-2b18-4d95-ae99-d1c6356ec917
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3484574296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3484574296
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2285494144
Short name T406
Test name
Test status
Simulation time 1324275470 ps
CPU time 48.34 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:59 PM PDT 24
Peak memory 204296 kb
Host smart-15593cf7-5a10-4daa-b43a-6a461208a68b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2285494144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2285494144
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.778770268
Short name T28
Test name
Test status
Simulation time 1083142167 ps
CPU time 214.16 seconds
Started Apr 18 12:41:11 PM PDT 24
Finished Apr 18 12:44:46 PM PDT 24
Peak memory 209168 kb
Host smart-83bec39e-204e-4aad-ab37-461d97681914
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=778770268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_
reset.778770268
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.23058098
Short name T280
Test name
Test status
Simulation time 8143384179 ps
CPU time 364.26 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:47:12 PM PDT 24
Peak memory 211628 kb
Host smart-874a3fe1-115f-4426-90c1-b5fec6b9889d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23058098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset
_error.23058098
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1604446576
Short name T427
Test name
Test status
Simulation time 39653901 ps
CPU time 5.92 seconds
Started Apr 18 12:41:00 PM PDT 24
Finished Apr 18 12:41:06 PM PDT 24
Peak memory 205140 kb
Host smart-e8733b98-7b20-4a2f-8479-b8bd5172d27f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604446576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1604446576
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3881760476
Short name T347
Test name
Test status
Simulation time 346789189 ps
CPU time 42.56 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 205260 kb
Host smart-b06f3799-a677-423c-9399-42c0957f5a55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3881760476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3881760476
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.4062308265
Short name T764
Test name
Test status
Simulation time 71143681935 ps
CPU time 465.49 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:50:49 PM PDT 24
Peak memory 211604 kb
Host smart-81b80e33-b981-45b3-8135-50d913ac610e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4062308265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.4062308265
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2859080455
Short name T817
Test name
Test status
Simulation time 104469904 ps
CPU time 13.55 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:43:09 PM PDT 24
Peak memory 203384 kb
Host smart-bc09833b-3db4-49ee-a51f-892714fc5691
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2859080455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2859080455
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.3711277164
Short name T566
Test name
Test status
Simulation time 395408386 ps
CPU time 13.02 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:43:08 PM PDT 24
Peak memory 203468 kb
Host smart-54f3b105-1729-4ef8-b212-ccd32ed8c9f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3711277164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3711277164
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.1281605266
Short name T725
Test name
Test status
Simulation time 514320596 ps
CPU time 17.9 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 204728 kb
Host smart-295ca641-1273-4063-9747-b97a90497455
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1281605266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1281605266
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2081973839
Short name T299
Test name
Test status
Simulation time 52237206531 ps
CPU time 131.76 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:45:08 PM PDT 24
Peak memory 205000 kb
Host smart-7d31d96f-4d20-4b47-bdbd-adb5bdebed79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081973839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2081973839
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3219969895
Short name T271
Test name
Test status
Simulation time 17088718476 ps
CPU time 145.87 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 204976 kb
Host smart-95af72ae-e64b-47f2-ac37-881882235743
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3219969895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3219969895
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3778338087
Short name T786
Test name
Test status
Simulation time 90306594 ps
CPU time 11.3 seconds
Started Apr 18 12:42:47 PM PDT 24
Finished Apr 18 12:42:59 PM PDT 24
Peak memory 211568 kb
Host smart-7d12801b-b09e-4cd0-aa53-81669e887d5a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778338087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3778338087
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2331662573
Short name T880
Test name
Test status
Simulation time 1215763470 ps
CPU time 15.79 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:19 PM PDT 24
Peak memory 204048 kb
Host smart-ba0bd976-d87b-4bcb-84dc-9f080190a909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2331662573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2331662573
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.2176106451
Short name T49
Test name
Test status
Simulation time 325888641 ps
CPU time 3.37 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:42:58 PM PDT 24
Peak memory 203488 kb
Host smart-8fba5c7f-f8db-4170-a1c8-f9d5f32d7913
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2176106451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2176106451
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.694428260
Short name T286
Test name
Test status
Simulation time 8370023469 ps
CPU time 26.24 seconds
Started Apr 18 12:42:45 PM PDT 24
Finished Apr 18 12:43:12 PM PDT 24
Peak memory 203452 kb
Host smart-055b2ac1-80b3-4ba0-b4fe-f757ac192dbf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=694428260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.694428260
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3153376097
Short name T668
Test name
Test status
Simulation time 9605203822 ps
CPU time 35.74 seconds
Started Apr 18 12:42:44 PM PDT 24
Finished Apr 18 12:43:21 PM PDT 24
Peak memory 203440 kb
Host smart-edaaa7b5-7b7b-4563-adfc-b1c73b05dfad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3153376097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3153376097
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.4073428617
Short name T413
Test name
Test status
Simulation time 91912368 ps
CPU time 2.32 seconds
Started Apr 18 12:42:48 PM PDT 24
Finished Apr 18 12:42:51 PM PDT 24
Peak memory 203332 kb
Host smart-b0782f6c-ab0a-4e9f-8b56-b8fefc6ee30b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073428617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.4073428617
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2725766334
Short name T367
Test name
Test status
Simulation time 1377728353 ps
CPU time 48.79 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 205504 kb
Host smart-6bf65891-f214-462e-ad47-fc5b71313376
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2725766334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2725766334
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2454523057
Short name T630
Test name
Test status
Simulation time 275030284 ps
CPU time 19.38 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:23 PM PDT 24
Peak memory 203560 kb
Host smart-562f9e54-d32a-43ce-8577-bf0942e5c7bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2454523057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2454523057
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2976256389
Short name T350
Test name
Test status
Simulation time 183397859 ps
CPU time 39.9 seconds
Started Apr 18 12:42:52 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 206656 kb
Host smart-0d6ccb21-239b-42ac-8872-56d29a1608c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2976256389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.2976256389
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1460389659
Short name T698
Test name
Test status
Simulation time 946700284 ps
CPU time 31.7 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:36 PM PDT 24
Peak memory 205072 kb
Host smart-7f1a823e-ef37-4c8e-8e28-b9574f2d2ddb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1460389659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1460389659
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1079032489
Short name T417
Test name
Test status
Simulation time 734840384 ps
CPU time 21.35 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:25 PM PDT 24
Peak memory 204528 kb
Host smart-01fa5152-cf9a-40e2-8df5-4f4555844424
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1079032489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1079032489
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.956941815
Short name T200
Test name
Test status
Simulation time 114172540809 ps
CPU time 545.26 seconds
Started Apr 18 12:42:52 PM PDT 24
Finished Apr 18 12:51:58 PM PDT 24
Peak memory 206972 kb
Host smart-3c6e35b0-919a-4f0b-8e3e-def1b0d5f4fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=956941815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo
w_rsp.956941815
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.522936636
Short name T694
Test name
Test status
Simulation time 140272615 ps
CPU time 13.2 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:15 PM PDT 24
Peak memory 203808 kb
Host smart-bcb4dbf0-54b5-464d-b032-33468f0354d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=522936636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.522936636
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.159178863
Short name T467
Test name
Test status
Simulation time 39829898 ps
CPU time 4.3 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:08 PM PDT 24
Peak memory 203372 kb
Host smart-f26f7012-ad19-41c9-b601-024d5e55d0d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=159178863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.159178863
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.2267029756
Short name T802
Test name
Test status
Simulation time 142959599 ps
CPU time 4.37 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:05 PM PDT 24
Peak memory 203876 kb
Host smart-2f3516ab-beaa-4cbd-a9a4-b1e90eac57f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2267029756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2267029756
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.414154195
Short name T446
Test name
Test status
Simulation time 5557048120 ps
CPU time 18.22 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:18 PM PDT 24
Peak memory 203368 kb
Host smart-0599130f-a18c-4a65-9b57-50f74aff2cf1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=414154195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.414154195
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1567999671
Short name T157
Test name
Test status
Simulation time 44495466636 ps
CPU time 150.53 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:45:34 PM PDT 24
Peak memory 204748 kb
Host smart-f3eaa062-6f9d-4833-92a9-803f5a00da9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1567999671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1567999671
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1701113680
Short name T689
Test name
Test status
Simulation time 855721686 ps
CPU time 26 seconds
Started Apr 18 12:42:55 PM PDT 24
Finished Apr 18 12:43:23 PM PDT 24
Peak memory 211516 kb
Host smart-9787c087-a652-4f4f-bf49-8fa8ad4a452e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701113680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1701113680
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.3053013624
Short name T292
Test name
Test status
Simulation time 857817110 ps
CPU time 14.49 seconds
Started Apr 18 12:42:55 PM PDT 24
Finished Apr 18 12:43:11 PM PDT 24
Peak memory 203904 kb
Host smart-beb0bef6-75bf-42a0-8972-a8a1aa8e2099
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3053013624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3053013624
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1198560677
Short name T297
Test name
Test status
Simulation time 113665627 ps
CPU time 2.17 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:05 PM PDT 24
Peak memory 203312 kb
Host smart-5ac61563-c6b6-46af-ae5b-9f34a7dfb6b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1198560677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1198560677
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1123398678
Short name T62
Test name
Test status
Simulation time 17682185575 ps
CPU time 36.37 seconds
Started Apr 18 12:42:54 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 203468 kb
Host smart-b6762267-7a70-4af3-99ec-036ee9576fc6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123398678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1123398678
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4083193384
Short name T261
Test name
Test status
Simulation time 5733650471 ps
CPU time 33.81 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:35 PM PDT 24
Peak memory 203376 kb
Host smart-11f184ab-18d7-45fd-ae5b-5ce4ba383b15
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4083193384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4083193384
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.389482860
Short name T507
Test name
Test status
Simulation time 27292364 ps
CPU time 1.98 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:05 PM PDT 24
Peak memory 203240 kb
Host smart-9f9d72a8-24d2-406c-a0a0-99cedfa86ebd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389482860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.389482860
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.998880368
Short name T824
Test name
Test status
Simulation time 1692169891 ps
CPU time 113.27 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:44:56 PM PDT 24
Peak memory 208332 kb
Host smart-245d1e29-62ce-435a-ba9b-a95eaa3c54ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=998880368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.998880368
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3777712789
Short name T772
Test name
Test status
Simulation time 651280649 ps
CPU time 46.16 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 205800 kb
Host smart-156d6778-a729-4af1-918a-a860a8f8d6cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3777712789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3777712789
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.449520524
Short name T500
Test name
Test status
Simulation time 3512946692 ps
CPU time 110.62 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:44:52 PM PDT 24
Peak memory 208904 kb
Host smart-c98d116e-e069-497c-89fe-4146476144a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=449520524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res
et_error.449520524
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.406269890
Short name T303
Test name
Test status
Simulation time 202003787 ps
CPU time 11.8 seconds
Started Apr 18 12:42:52 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 204676 kb
Host smart-45a1f5e8-2478-4744-82e5-855284d09148
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=406269890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.406269890
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3598306884
Short name T88
Test name
Test status
Simulation time 829358245 ps
CPU time 30.25 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:34 PM PDT 24
Peak memory 205560 kb
Host smart-2c971d7c-4c62-448d-afbf-928ab89aa25e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3598306884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3598306884
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3681156699
Short name T106
Test name
Test status
Simulation time 49920397919 ps
CPU time 407.67 seconds
Started Apr 18 12:43:01 PM PDT 24
Finished Apr 18 12:49:52 PM PDT 24
Peak memory 206932 kb
Host smart-06487640-226c-48d4-b14a-a081db383021
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3681156699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.3681156699
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.291936253
Short name T799
Test name
Test status
Simulation time 459486643 ps
CPU time 15.95 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:20 PM PDT 24
Peak memory 203844 kb
Host smart-ff817306-fb18-41c5-bf1c-8705cb2b60a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=291936253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.291936253
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.2382476845
Short name T712
Test name
Test status
Simulation time 80732687 ps
CPU time 7.23 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:09 PM PDT 24
Peak memory 203356 kb
Host smart-c5814fa6-7ce9-4114-a622-8309bfa7b028
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2382476845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2382476845
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.3598990985
Short name T454
Test name
Test status
Simulation time 144996914 ps
CPU time 24.09 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:27 PM PDT 24
Peak memory 204504 kb
Host smart-d12b62be-2f7c-40c5-aae6-ac653e35d89c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3598990985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3598990985
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1783668840
Short name T40
Test name
Test status
Simulation time 51058056091 ps
CPU time 121.59 seconds
Started Apr 18 12:43:10 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 204692 kb
Host smart-490842a4-0339-4802-b894-8cc2dd114c3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783668840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1783668840
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2397826863
Short name T732
Test name
Test status
Simulation time 55605597330 ps
CPU time 157.16 seconds
Started Apr 18 12:42:57 PM PDT 24
Finished Apr 18 12:45:36 PM PDT 24
Peak memory 205088 kb
Host smart-6f91ca32-fb3c-412f-9175-a36c39119d91
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2397826863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2397826863
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3993864862
Short name T192
Test name
Test status
Simulation time 192911427 ps
CPU time 17.81 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:19 PM PDT 24
Peak memory 204556 kb
Host smart-7cd0a63a-3be7-493e-b933-7d8241b2609b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993864862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3993864862
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.2397396550
Short name T883
Test name
Test status
Simulation time 1218309747 ps
CPU time 21.69 seconds
Started Apr 18 12:43:01 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 203916 kb
Host smart-d434d11e-3780-4097-a90d-d2b27e30dce4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2397396550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2397396550
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.857822802
Short name T345
Test name
Test status
Simulation time 227421877 ps
CPU time 3.43 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 203384 kb
Host smart-ffb171bd-9fb2-42ba-810f-5f3f984d1a3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=857822802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.857822802
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2821029757
Short name T212
Test name
Test status
Simulation time 36493041233 ps
CPU time 55.36 seconds
Started Apr 18 12:43:03 PM PDT 24
Finished Apr 18 12:44:00 PM PDT 24
Peak memory 203516 kb
Host smart-80df36c1-4ef0-4cbd-aa56-81964a9a6df4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821029757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2821029757
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1351023588
Short name T457
Test name
Test status
Simulation time 8707161553 ps
CPU time 29.1 seconds
Started Apr 18 12:42:57 PM PDT 24
Finished Apr 18 12:43:28 PM PDT 24
Peak memory 203380 kb
Host smart-55dfc13c-90c2-4327-910e-248262acf3ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1351023588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1351023588
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1724106313
Short name T112
Test name
Test status
Simulation time 29499149 ps
CPU time 2.08 seconds
Started Apr 18 12:42:57 PM PDT 24
Finished Apr 18 12:43:00 PM PDT 24
Peak memory 203400 kb
Host smart-828ec630-153d-4536-851e-2b6842d64572
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724106313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1724106313
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.582065726
Short name T598
Test name
Test status
Simulation time 6402688242 ps
CPU time 147.51 seconds
Started Apr 18 12:43:01 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 209408 kb
Host smart-6b497ffc-5bba-415e-8a84-9d3b138ec103
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=582065726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.582065726
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2631279284
Short name T608
Test name
Test status
Simulation time 100907713 ps
CPU time 4.04 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:08 PM PDT 24
Peak memory 203420 kb
Host smart-4d7317e6-3059-4012-8351-52442fdc1703
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2631279284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2631279284
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1894473946
Short name T672
Test name
Test status
Simulation time 230036700 ps
CPU time 93.7 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:44:37 PM PDT 24
Peak memory 208636 kb
Host smart-4ee79237-a8ee-4763-9b46-2bfdf6d6d0da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1894473946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.1894473946
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2236694830
Short name T340
Test name
Test status
Simulation time 235989648 ps
CPU time 124.69 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 210440 kb
Host smart-4ef5638d-9e41-4f3c-9d24-b163744a2e1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2236694830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.2236694830
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2168080431
Short name T485
Test name
Test status
Simulation time 228677292 ps
CPU time 10 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:10 PM PDT 24
Peak memory 204780 kb
Host smart-8c36f9d3-9624-48be-b22a-24a7388de6f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2168080431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2168080431
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.499072779
Short name T568
Test name
Test status
Simulation time 2511825109 ps
CPU time 55.79 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:59 PM PDT 24
Peak memory 206720 kb
Host smart-6a8c4cf3-2997-4688-bb10-4f7e1321de5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=499072779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.499072779
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.4120231568
Short name T307
Test name
Test status
Simulation time 100743600 ps
CPU time 5.83 seconds
Started Apr 18 12:43:08 PM PDT 24
Finished Apr 18 12:43:16 PM PDT 24
Peak memory 203676 kb
Host smart-16bd4307-7e9c-4b49-939e-5293e2ec90d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4120231568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.4120231568
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.753639577
Short name T702
Test name
Test status
Simulation time 1299843270 ps
CPU time 34.22 seconds
Started Apr 18 12:43:07 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 203432 kb
Host smart-67c6f224-4737-48d9-be50-e988c7fa5c0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=753639577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.753639577
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.1292131184
Short name T589
Test name
Test status
Simulation time 64133956 ps
CPU time 2.79 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:03 PM PDT 24
Peak memory 203500 kb
Host smart-c5390da2-d449-435f-9f9a-ea4be8bfdd3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1292131184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1292131184
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1941409023
Short name T98
Test name
Test status
Simulation time 14637420250 ps
CPU time 53.49 seconds
Started Apr 18 12:42:57 PM PDT 24
Finished Apr 18 12:43:51 PM PDT 24
Peak memory 204684 kb
Host smart-67f54ff8-fcd5-4405-a140-ac6d38821483
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941409023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1941409023
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2600781357
Short name T490
Test name
Test status
Simulation time 24282986305 ps
CPU time 203.8 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 211724 kb
Host smart-4d69caec-b093-4fad-bfaa-40135e342391
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2600781357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2600781357
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3810458494
Short name T529
Test name
Test status
Simulation time 17102690 ps
CPU time 1.86 seconds
Started Apr 18 12:43:01 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 203340 kb
Host smart-03992f71-3bf0-4f78-b7f1-b9249b428825
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810458494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3810458494
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.130453629
Short name T776
Test name
Test status
Simulation time 4624971970 ps
CPU time 16.97 seconds
Started Apr 18 12:43:07 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 204512 kb
Host smart-4a62f3c2-68bf-4314-b0dc-e008a52a3f69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=130453629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.130453629
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.1954866738
Short name T373
Test name
Test status
Simulation time 142974939 ps
CPU time 3.65 seconds
Started Apr 18 12:42:59 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 203332 kb
Host smart-530688df-2820-43c6-8f0c-b78e7469a6fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954866738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1954866738
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.4151799197
Short name T620
Test name
Test status
Simulation time 19549071934 ps
CPU time 38.43 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 203404 kb
Host smart-6afd12e1-5df2-4e27-9bdc-565f9e973d25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151799197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.4151799197
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2514976243
Short name T793
Test name
Test status
Simulation time 3786425832 ps
CPU time 20.81 seconds
Started Apr 18 12:43:00 PM PDT 24
Finished Apr 18 12:43:25 PM PDT 24
Peak memory 203428 kb
Host smart-4fdcae61-6ef5-4465-acd0-029bd319601a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2514976243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2514976243
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3270035170
Short name T814
Test name
Test status
Simulation time 35709305 ps
CPU time 2.3 seconds
Started Apr 18 12:42:58 PM PDT 24
Finished Apr 18 12:43:02 PM PDT 24
Peak memory 203464 kb
Host smart-f6f86352-5831-4ffb-915f-8e7d397fc42a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270035170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3270035170
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3813081158
Short name T184
Test name
Test status
Simulation time 946222644 ps
CPU time 72.41 seconds
Started Apr 18 12:43:10 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 207560 kb
Host smart-c2b2bc20-6a54-4b58-9990-8c8bf0b813c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3813081158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3813081158
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3785478854
Short name T416
Test name
Test status
Simulation time 19137712080 ps
CPU time 135 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:45:27 PM PDT 24
Peak memory 211644 kb
Host smart-6b964738-ce12-47fe-8b25-f03f84d88de1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3785478854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3785478854
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2189185259
Short name T209
Test name
Test status
Simulation time 2172146623 ps
CPU time 330.7 seconds
Started Apr 18 12:43:07 PM PDT 24
Finished Apr 18 12:48:40 PM PDT 24
Peak memory 210380 kb
Host smart-3cc69a6b-5538-45e0-a6e2-f6113f3d21ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2189185259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.2189185259
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3891771616
Short name T873
Test name
Test status
Simulation time 2038353770 ps
CPU time 336.65 seconds
Started Apr 18 12:43:07 PM PDT 24
Finished Apr 18 12:48:46 PM PDT 24
Peak memory 224696 kb
Host smart-b0fff1c6-0210-4b90-ae3f-6a9f2cb6e6ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3891771616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.3891771616
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3674314110
Short name T850
Test name
Test status
Simulation time 439624618 ps
CPU time 17.13 seconds
Started Apr 18 12:43:09 PM PDT 24
Finished Apr 18 12:43:28 PM PDT 24
Peak memory 211560 kb
Host smart-6d44a9ed-90a3-456f-834a-b4de75ca5903
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3674314110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3674314110
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.382040220
Short name T809
Test name
Test status
Simulation time 614920460 ps
CPU time 39.94 seconds
Started Apr 18 12:43:10 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 206132 kb
Host smart-7f797677-10c7-4527-afe2-400a101946fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=382040220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.382040220
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1984382577
Short name T141
Test name
Test status
Simulation time 96632275721 ps
CPU time 690.78 seconds
Started Apr 18 12:43:08 PM PDT 24
Finished Apr 18 12:54:41 PM PDT 24
Peak memory 206080 kb
Host smart-5f377193-c4e0-4734-8046-6738cad13690
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1984382577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.1984382577
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4032246357
Short name T595
Test name
Test status
Simulation time 38297954 ps
CPU time 4.72 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:43:17 PM PDT 24
Peak memory 203684 kb
Host smart-789a2b2a-fac2-4e59-bb85-ff9dc686fbfa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4032246357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.4032246357
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.95383921
Short name T66
Test name
Test status
Simulation time 1010713691 ps
CPU time 37.17 seconds
Started Apr 18 12:43:10 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 203732 kb
Host smart-1aa68bcf-035a-4372-af77-c163e220dbf6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95383921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.95383921
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.2722588641
Short name T275
Test name
Test status
Simulation time 137549189 ps
CPU time 15.18 seconds
Started Apr 18 12:43:10 PM PDT 24
Finished Apr 18 12:43:27 PM PDT 24
Peak memory 204600 kb
Host smart-6a74e626-97dc-401d-abbf-ceac4fc2071d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2722588641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2722588641
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2549277261
Short name T835
Test name
Test status
Simulation time 5163940084 ps
CPU time 29.99 seconds
Started Apr 18 12:43:10 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 204176 kb
Host smart-fa759bf9-dbc4-4b42-93bd-28c4047a90e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549277261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2549277261
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1448400664
Short name T46
Test name
Test status
Simulation time 47000174826 ps
CPU time 282.27 seconds
Started Apr 18 12:43:08 PM PDT 24
Finished Apr 18 12:47:52 PM PDT 24
Peak memory 211592 kb
Host smart-a242d108-8dbf-4975-8662-d464ae92a33e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1448400664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1448400664
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.449133893
Short name T726
Test name
Test status
Simulation time 91698621 ps
CPU time 10.91 seconds
Started Apr 18 12:43:09 PM PDT 24
Finished Apr 18 12:43:21 PM PDT 24
Peak memory 204600 kb
Host smart-ddb9f7d4-5ca4-43d2-8f45-549e631047dd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449133893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.449133893
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.1896449080
Short name T100
Test name
Test status
Simulation time 1551434060 ps
CPU time 9.88 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:43:23 PM PDT 24
Peak memory 204016 kb
Host smart-8900b4ea-18f9-48c0-acc6-52dd8b86fdbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1896449080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1896449080
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1874114293
Short name T785
Test name
Test status
Simulation time 56720347 ps
CPU time 2.32 seconds
Started Apr 18 12:43:07 PM PDT 24
Finished Apr 18 12:43:12 PM PDT 24
Peak memory 203424 kb
Host smart-d36f40c7-d853-4f78-aa84-cb375c880b7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1874114293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1874114293
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2815435072
Short name T594
Test name
Test status
Simulation time 18893603076 ps
CPU time 43.6 seconds
Started Apr 18 12:43:07 PM PDT 24
Finished Apr 18 12:43:53 PM PDT 24
Peak memory 203544 kb
Host smart-c8ca5ad5-60fc-4957-9a26-84b9e6558788
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815435072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2815435072
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.908596391
Short name T159
Test name
Test status
Simulation time 3658269521 ps
CPU time 32 seconds
Started Apr 18 12:43:17 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 203552 kb
Host smart-d395b76b-4f09-4347-bda3-e0cfbd529089
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=908596391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.908596391
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2406458365
Short name T729
Test name
Test status
Simulation time 93641645 ps
CPU time 2.35 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:43:15 PM PDT 24
Peak memory 203464 kb
Host smart-6720f1a2-323e-49c2-a7e8-027a837e30fe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406458365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2406458365
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.2992836899
Short name T189
Test name
Test status
Simulation time 3343397237 ps
CPU time 68.71 seconds
Started Apr 18 12:43:06 PM PDT 24
Finished Apr 18 12:44:17 PM PDT 24
Peak memory 206252 kb
Host smart-c1d32c2a-62ba-4789-8ce5-be55327ad89f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2992836899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2992836899
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2042730000
Short name T548
Test name
Test status
Simulation time 9918229161 ps
CPU time 172.98 seconds
Started Apr 18 12:43:08 PM PDT 24
Finished Apr 18 12:46:03 PM PDT 24
Peak memory 206828 kb
Host smart-331e83ff-961a-448f-8822-379f4a45177c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2042730000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2042730000
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4080780932
Short name T351
Test name
Test status
Simulation time 2417295461 ps
CPU time 293.54 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:48:06 PM PDT 24
Peak memory 209360 kb
Host smart-f9f92918-49f6-4ba5-a6ee-b803ae4f2b37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4080780932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.4080780932
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2511417771
Short name T591
Test name
Test status
Simulation time 684602537 ps
CPU time 201.59 seconds
Started Apr 18 12:43:08 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 211612 kb
Host smart-caad0b98-027e-464d-8497-7ec35ad5a818
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2511417771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.2511417771
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2085823175
Short name T203
Test name
Test status
Simulation time 459031646 ps
CPU time 20.63 seconds
Started Apr 18 12:43:08 PM PDT 24
Finished Apr 18 12:43:30 PM PDT 24
Peak memory 211592 kb
Host smart-22e8039e-f958-4312-9ea2-0507593f1fa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2085823175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2085823175
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3991643471
Short name T496
Test name
Test status
Simulation time 2138956735 ps
CPU time 21.74 seconds
Started Apr 18 12:43:09 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 211588 kb
Host smart-32921434-b0ed-4f45-add6-acb01cd1022e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3991643471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3991643471
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.475618050
Short name T153
Test name
Test status
Simulation time 300865550441 ps
CPU time 664.45 seconds
Started Apr 18 12:43:17 PM PDT 24
Finished Apr 18 12:54:22 PM PDT 24
Peak memory 206028 kb
Host smart-7edc0a08-55cc-4dcd-9242-b60adca74e24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=475618050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo
w_rsp.475618050
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3104634569
Short name T361
Test name
Test status
Simulation time 605009247 ps
CPU time 15.55 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:31 PM PDT 24
Peak memory 204040 kb
Host smart-18380414-28b2-4feb-81c1-99c1a14a1a52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3104634569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3104634569
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2837002511
Short name T711
Test name
Test status
Simulation time 965481110 ps
CPU time 11.23 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 203420 kb
Host smart-bc2edc53-b3c9-49bc-aa41-4795d14f7b87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2837002511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2837002511
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.3376038403
Short name T411
Test name
Test status
Simulation time 173587705 ps
CPU time 6.82 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:43:20 PM PDT 24
Peak memory 204592 kb
Host smart-db8d75c4-118e-42e8-82e5-8149268ebe94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3376038403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3376038403
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3566257099
Short name T857
Test name
Test status
Simulation time 140315050696 ps
CPU time 226.99 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:46:59 PM PDT 24
Peak memory 205364 kb
Host smart-143857df-d82b-4c6c-bc04-2ddfc563d7ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566257099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3566257099
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2544558801
Short name T58
Test name
Test status
Simulation time 136271099115 ps
CPU time 286.38 seconds
Started Apr 18 12:43:10 PM PDT 24
Finished Apr 18 12:47:57 PM PDT 24
Peak memory 205304 kb
Host smart-97056b4f-0ca5-4ff5-b420-2694ab74eedd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2544558801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2544558801
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3792875759
Short name T18
Test name
Test status
Simulation time 365884262 ps
CPU time 19.84 seconds
Started Apr 18 12:43:17 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 204880 kb
Host smart-394c4039-ce88-4642-aa46-f95132cccfd7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792875759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3792875759
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.412259820
Short name T92
Test name
Test status
Simulation time 1047031381 ps
CPU time 25.52 seconds
Started Apr 18 12:43:09 PM PDT 24
Finished Apr 18 12:43:36 PM PDT 24
Peak memory 204248 kb
Host smart-ce59b3df-5802-4398-ac7c-d43d6c0c531f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=412259820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.412259820
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.4246474667
Short name T463
Test name
Test status
Simulation time 182844962 ps
CPU time 3.78 seconds
Started Apr 18 12:43:06 PM PDT 24
Finished Apr 18 12:43:11 PM PDT 24
Peak memory 203488 kb
Host smart-58ae69a6-53ad-49b4-b96d-45e64a579f56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4246474667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4246474667
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.945148340
Short name T466
Test name
Test status
Simulation time 9126781622 ps
CPU time 28.89 seconds
Started Apr 18 12:43:07 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 203524 kb
Host smart-8e8b1343-aefc-4409-90ea-2b2c4b757952
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=945148340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.945148340
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.630818316
Short name T790
Test name
Test status
Simulation time 5179324031 ps
CPU time 31.96 seconds
Started Apr 18 12:43:16 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 203552 kb
Host smart-4110cd50-08a5-4645-8cd4-2951cde37008
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=630818316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.630818316
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1515325839
Short name T376
Test name
Test status
Simulation time 33220629 ps
CPU time 2.45 seconds
Started Apr 18 12:43:08 PM PDT 24
Finished Apr 18 12:43:13 PM PDT 24
Peak memory 203400 kb
Host smart-918541ba-6f14-451f-97dc-cd335c530db8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515325839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1515325839
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.429286198
Short name T231
Test name
Test status
Simulation time 1704689174 ps
CPU time 74.94 seconds
Started Apr 18 12:43:16 PM PDT 24
Finished Apr 18 12:44:32 PM PDT 24
Peak memory 205976 kb
Host smart-a084c83e-777e-4051-9f2e-6c7341cdb3ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=429286198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.429286198
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2510384068
Short name T520
Test name
Test status
Simulation time 1652576382 ps
CPU time 131.03 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:45:26 PM PDT 24
Peak memory 207676 kb
Host smart-2f2ddff0-5312-4dcc-87b7-cb67fb3e0d54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2510384068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2510384068
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3725584268
Short name T543
Test name
Test status
Simulation time 281470057 ps
CPU time 128.55 seconds
Started Apr 18 12:43:11 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 209264 kb
Host smart-47dcc7df-1969-4507-8c18-8759c7ba7d57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3725584268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.3725584268
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.4124279068
Short name T432
Test name
Test status
Simulation time 11876828422 ps
CPU time 336.17 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:48:51 PM PDT 24
Peak memory 219796 kb
Host smart-cdd34653-6421-4924-ac11-21fccad8e6f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4124279068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.4124279068
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2047835711
Short name T10
Test name
Test status
Simulation time 27277535 ps
CPU time 3.32 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:19 PM PDT 24
Peak memory 211504 kb
Host smart-2a7c24ef-87c0-4aa8-82f4-152a2397a2f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2047835711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2047835711
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1444497244
Short name T52
Test name
Test status
Simulation time 1995355781 ps
CPU time 66.25 seconds
Started Apr 18 12:43:12 PM PDT 24
Finished Apr 18 12:44:19 PM PDT 24
Peak memory 205460 kb
Host smart-118d5dc7-bf2f-4bf1-8174-170b5fc7d909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1444497244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1444497244
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.21308048
Short name T664
Test name
Test status
Simulation time 9689312255 ps
CPU time 66.76 seconds
Started Apr 18 12:43:15 PM PDT 24
Finished Apr 18 12:44:22 PM PDT 24
Peak memory 205588 kb
Host smart-8b41e735-e67d-47a0-ae4b-c2607875e90b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=21308048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow
_rsp.21308048
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1618189971
Short name T895
Test name
Test status
Simulation time 361522678 ps
CPU time 8.03 seconds
Started Apr 18 12:43:15 PM PDT 24
Finished Apr 18 12:43:24 PM PDT 24
Peak memory 203600 kb
Host smart-5c3e7bc8-9046-4b7a-ae1f-1aaef6a3a5f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1618189971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1618189971
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.1781822425
Short name T419
Test name
Test status
Simulation time 517987693 ps
CPU time 24.12 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 203408 kb
Host smart-c05a0d29-749d-4aaa-b67d-bfd038848e60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1781822425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1781822425
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.2256074634
Short name T162
Test name
Test status
Simulation time 443969162 ps
CPU time 19.89 seconds
Started Apr 18 12:43:12 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 204664 kb
Host smart-c1bc7937-6ddb-4d08-91f7-12f9d11fbd85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2256074634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2256074634
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3958218469
Short name T634
Test name
Test status
Simulation time 60238097686 ps
CPU time 167.11 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 205192 kb
Host smart-2124346d-6896-4e57-ac3f-54a8f73cef50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958218469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3958218469
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1661555433
Short name T527
Test name
Test status
Simulation time 3039366820 ps
CPU time 30.44 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:45 PM PDT 24
Peak memory 203400 kb
Host smart-cce3d140-1238-4ca2-b068-c5db61d60ef0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1661555433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1661555433
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2509792881
Short name T486
Test name
Test status
Simulation time 47230764 ps
CPU time 6.31 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:43:20 PM PDT 24
Peak memory 204356 kb
Host smart-81fa8a38-a939-462f-b4d7-bcf7e69660dc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509792881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2509792881
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.3296414307
Short name T565
Test name
Test status
Simulation time 233908196 ps
CPU time 5.9 seconds
Started Apr 18 12:43:16 PM PDT 24
Finished Apr 18 12:43:22 PM PDT 24
Peak memory 203944 kb
Host smart-a1e8c0a0-0a74-4b20-8079-761205ad535c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3296414307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3296414307
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.959960035
Short name T472
Test name
Test status
Simulation time 26853529 ps
CPU time 2.23 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:18 PM PDT 24
Peak memory 203372 kb
Host smart-407a84c5-bcd2-43ea-8833-53bd45d95d83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=959960035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.959960035
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3379779149
Short name T156
Test name
Test status
Simulation time 7324132146 ps
CPU time 32.83 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 203432 kb
Host smart-f75cc48e-e5d9-437d-ae7f-5b90ea4d3f72
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379779149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3379779149
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2691726874
Short name T599
Test name
Test status
Simulation time 4786830111 ps
CPU time 42.08 seconds
Started Apr 18 12:43:12 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 203512 kb
Host smart-52325806-418d-410c-8aa9-ba22aae3a28d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2691726874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2691726874
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1440555
Short name T813
Test name
Test status
Simulation time 26412958 ps
CPU time 2.24 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:43:17 PM PDT 24
Peak memory 203376 kb
Host smart-25653ea1-9e21-42d2-8f87-fe61897733ab
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1440555
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1998338236
Short name T853
Test name
Test status
Simulation time 255533562 ps
CPU time 7.11 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:43:22 PM PDT 24
Peak memory 204532 kb
Host smart-773b91ce-ede4-46b5-981e-9a1b669fe003
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1998338236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1998338236
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2502408938
Short name T439
Test name
Test status
Simulation time 3642854049 ps
CPU time 55.38 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:44:11 PM PDT 24
Peak memory 205476 kb
Host smart-c14e746d-ff1a-48c0-8962-9a0478735d46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2502408938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2502408938
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3608625542
Short name T163
Test name
Test status
Simulation time 735611124 ps
CPU time 250.09 seconds
Started Apr 18 12:43:12 PM PDT 24
Finished Apr 18 12:47:23 PM PDT 24
Peak memory 209184 kb
Host smart-a040c065-f99d-40b9-bf9e-a6fde9ef850f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3608625542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.3608625542
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4057153793
Short name T871
Test name
Test status
Simulation time 1248832227 ps
CPU time 92.97 seconds
Started Apr 18 12:43:17 PM PDT 24
Finished Apr 18 12:44:51 PM PDT 24
Peak memory 208256 kb
Host smart-125e6d3c-55bd-48d1-abbe-5bdcd3d72827
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4057153793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.4057153793
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1232499951
Short name T847
Test name
Test status
Simulation time 475818038 ps
CPU time 15.53 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:43:29 PM PDT 24
Peak memory 205196 kb
Host smart-309dca97-ed0b-4979-b96a-a58b804e47cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1232499951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1232499951
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2827356731
Short name T90
Test name
Test status
Simulation time 2842809662 ps
CPU time 61.19 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:44:26 PM PDT 24
Peak memory 206656 kb
Host smart-e97f4e9f-179f-44e0-b2fb-12afdc327d96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2827356731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2827356731
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3484156064
Short name T899
Test name
Test status
Simulation time 1140355008 ps
CPU time 27.75 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:43:47 PM PDT 24
Peak memory 203668 kb
Host smart-d7bd73bd-58bd-4afc-b0b2-8b6e0d08c9bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3484156064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3484156064
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.525259163
Short name T713
Test name
Test status
Simulation time 256610629 ps
CPU time 8.98 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:43:35 PM PDT 24
Peak memory 203492 kb
Host smart-8a5b8fe3-5416-46ec-9c8f-472bf38fc6c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=525259163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.525259163
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.331834932
Short name T380
Test name
Test status
Simulation time 1088452287 ps
CPU time 27.26 seconds
Started Apr 18 12:43:12 PM PDT 24
Finished Apr 18 12:43:40 PM PDT 24
Peak memory 211656 kb
Host smart-469cdd75-921b-4651-99fd-e219c0a8e336
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=331834932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.331834932
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3267021997
Short name T448
Test name
Test status
Simulation time 32221028627 ps
CPU time 181.15 seconds
Started Apr 18 12:43:19 PM PDT 24
Finished Apr 18 12:46:21 PM PDT 24
Peak memory 211728 kb
Host smart-71e84b0d-9795-438b-94e7-928c583fb873
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267021997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3267021997
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1151041766
Short name T315
Test name
Test status
Simulation time 19717901992 ps
CPU time 152.43 seconds
Started Apr 18 12:43:15 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 211724 kb
Host smart-81597ea2-505a-4314-830b-c995f2240d4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1151041766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1151041766
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1526962196
Short name T619
Test name
Test status
Simulation time 97901691 ps
CPU time 16.79 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 204724 kb
Host smart-8e67af9e-20be-428f-816a-7a58a620f83a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526962196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1526962196
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.743444210
Short name T524
Test name
Test status
Simulation time 1221983266 ps
CPU time 19.92 seconds
Started Apr 18 12:43:21 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 204084 kb
Host smart-48c232bc-9890-4831-930e-81024d8eb62a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=743444210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.743444210
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.1129908131
Short name T398
Test name
Test status
Simulation time 63466118 ps
CPU time 2.12 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:17 PM PDT 24
Peak memory 203336 kb
Host smart-76b53555-22c1-49a3-bb62-b78ddda86d78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1129908131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1129908131
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.363410322
Short name T420
Test name
Test status
Simulation time 5709921601 ps
CPU time 28.22 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 203412 kb
Host smart-e9b44c57-9fc9-4354-8592-16b7278bc6b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=363410322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.363410322
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1685905794
Short name T606
Test name
Test status
Simulation time 4316642865 ps
CPU time 23.91 seconds
Started Apr 18 12:43:13 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 203420 kb
Host smart-2d464990-8af3-43be-b908-cf1dd8c4f9d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1685905794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1685905794
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1413204166
Short name T489
Test name
Test status
Simulation time 41586586 ps
CPU time 2.15 seconds
Started Apr 18 12:43:14 PM PDT 24
Finished Apr 18 12:43:17 PM PDT 24
Peak memory 203452 kb
Host smart-1b91b68b-4212-4435-a737-bb755738fc09
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413204166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1413204166
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2223410575
Short name T139
Test name
Test status
Simulation time 9083587312 ps
CPU time 217.31 seconds
Started Apr 18 12:43:19 PM PDT 24
Finished Apr 18 12:46:57 PM PDT 24
Peak memory 207528 kb
Host smart-df390a1a-c515-4968-b726-4c699c7171a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2223410575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2223410575
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1972176105
Short name T324
Test name
Test status
Simulation time 2525031748 ps
CPU time 139.89 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 209880 kb
Host smart-35191406-d3b9-468f-a600-814a19078aea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1972176105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1972176105
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2515796572
Short name T889
Test name
Test status
Simulation time 8115371845 ps
CPU time 200.99 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:46:47 PM PDT 24
Peak memory 209908 kb
Host smart-05e22979-1ab3-4173-af85-6883856e9bf0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2515796572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.2515796572
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.749716193
Short name T279
Test name
Test status
Simulation time 739174116 ps
CPU time 176.92 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 211784 kb
Host smart-5ee137a5-23bd-4999-be0b-2f335e1e8f5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=749716193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_res
et_error.749716193
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2399053768
Short name T893
Test name
Test status
Simulation time 197177068 ps
CPU time 8.62 seconds
Started Apr 18 12:43:22 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 204968 kb
Host smart-fdd5b9e7-0ac9-487e-af3f-977787bed4df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2399053768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2399053768
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3888564291
Short name T818
Test name
Test status
Simulation time 1103459704 ps
CPU time 28.79 seconds
Started Apr 18 12:43:20 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 211640 kb
Host smart-8f15a8f2-9dc4-4810-bdf2-8ab7c29fd0cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3888564291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3888564291
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3021053037
Short name T251
Test name
Test status
Simulation time 596476280 ps
CPU time 20.45 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:43:51 PM PDT 24
Peak memory 204268 kb
Host smart-60eb204b-0e1e-4886-ad61-cbb8a7cb4dc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3021053037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3021053037
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.3729311589
Short name T561
Test name
Test status
Simulation time 763886457 ps
CPU time 14.97 seconds
Started Apr 18 12:44:20 PM PDT 24
Finished Apr 18 12:44:42 PM PDT 24
Peak memory 203440 kb
Host smart-de4a023d-b121-4aea-a2c6-0b625530ef96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3729311589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3729311589
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.1976917812
Short name T461
Test name
Test status
Simulation time 172704467 ps
CPU time 13.18 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 204836 kb
Host smart-3bbe894b-fa9d-48f9-99b7-1046abfe6df4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1976917812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1976917812
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2963354959
Short name T718
Test name
Test status
Simulation time 84007043804 ps
CPU time 245.24 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:47:25 PM PDT 24
Peak memory 205260 kb
Host smart-4b249276-c969-4079-a333-42a846a06ec3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963354959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2963354959
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3078339223
Short name T357
Test name
Test status
Simulation time 18153260 ps
CPU time 2.22 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:43:28 PM PDT 24
Peak memory 203392 kb
Host smart-7955ecbc-af28-47bc-9d6c-12d77f357e37
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078339223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3078339223
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.105539209
Short name T788
Test name
Test status
Simulation time 139308864 ps
CPU time 8.95 seconds
Started Apr 18 12:43:19 PM PDT 24
Finished Apr 18 12:43:29 PM PDT 24
Peak memory 204020 kb
Host smart-4b74268b-1f29-4978-b41b-fbcefb077aa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105539209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.105539209
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.2518521564
Short name T626
Test name
Test status
Simulation time 642227199 ps
CPU time 4.11 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:43:23 PM PDT 24
Peak memory 203356 kb
Host smart-01ccc6f1-fe42-4639-9b6a-36a06235a4bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2518521564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2518521564
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.219197672
Short name T171
Test name
Test status
Simulation time 33392555525 ps
CPU time 54.92 seconds
Started Apr 18 12:43:23 PM PDT 24
Finished Apr 18 12:44:19 PM PDT 24
Peak memory 203532 kb
Host smart-8fd98ce0-881a-4272-a36a-f021ea30de8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=219197672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.219197672
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.28590209
Short name T285
Test name
Test status
Simulation time 3092639894 ps
CPU time 26.66 seconds
Started Apr 18 12:43:19 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 203552 kb
Host smart-c3dfb6d7-9709-4089-9046-fc83c3128e39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=28590209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.28590209
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2800115062
Short name T276
Test name
Test status
Simulation time 115377224 ps
CPU time 2.25 seconds
Started Apr 18 12:43:23 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 203368 kb
Host smart-0dde7970-9dae-496c-90d7-c560a51c381f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800115062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2800115062
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2066542734
Short name T843
Test name
Test status
Simulation time 1357606255 ps
CPU time 41.53 seconds
Started Apr 18 12:43:23 PM PDT 24
Finished Apr 18 12:44:06 PM PDT 24
Peak memory 205604 kb
Host smart-ded3cd93-4eb8-41fe-8d62-831dafd3d4ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2066542734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2066542734
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3313407360
Short name T549
Test name
Test status
Simulation time 3657871073 ps
CPU time 114.56 seconds
Started Apr 18 12:43:20 PM PDT 24
Finished Apr 18 12:45:15 PM PDT 24
Peak memory 206324 kb
Host smart-671ef342-4fd7-4b12-9de7-3963734b54c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313407360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3313407360
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.4041142416
Short name T861
Test name
Test status
Simulation time 7717653 ps
CPU time 33.02 seconds
Started Apr 18 12:43:21 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 203248 kb
Host smart-e44be59b-172e-4e55-bcdc-63318e7b92f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4041142416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.4041142416
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1180041730
Short name T805
Test name
Test status
Simulation time 1286039932 ps
CPU time 205.03 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 209864 kb
Host smart-84dd5041-96b2-471f-8885-f73cd4de6f4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1180041730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.1180041730
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3916767497
Short name T667
Test name
Test status
Simulation time 988499362 ps
CPU time 23.91 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 204980 kb
Host smart-cdf7b0cf-72f1-46d9-8dcd-9d14ca357c4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3916767497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3916767497
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1669230962
Short name T422
Test name
Test status
Simulation time 3330359510 ps
CPU time 63.83 seconds
Started Apr 18 12:43:20 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 206780 kb
Host smart-023b8f27-b86c-4136-aeed-e4d9a4e5086e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1669230962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1669230962
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3487074166
Short name T134
Test name
Test status
Simulation time 32309842008 ps
CPU time 235.18 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 206028 kb
Host smart-fceb8022-9c01-43a1-a198-418105906993
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3487074166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.3487074166
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2116378414
Short name T827
Test name
Test status
Simulation time 62908560 ps
CPU time 5.91 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:43:31 PM PDT 24
Peak memory 203392 kb
Host smart-4f4fc7e3-9e4e-4004-a758-b7e450cc9f0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2116378414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2116378414
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.4140772849
Short name T72
Test name
Test status
Simulation time 108099038 ps
CPU time 16.81 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:47 PM PDT 24
Peak memory 203728 kb
Host smart-127ba2f5-1083-42bc-8e10-f1bbd10192b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4140772849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4140772849
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.1563272103
Short name T222
Test name
Test status
Simulation time 135121410 ps
CPU time 8.62 seconds
Started Apr 18 12:43:22 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 204588 kb
Host smart-0f0e30cf-8c7c-4a80-acc1-6baae3421fd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1563272103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1563272103
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.989413831
Short name T129
Test name
Test status
Simulation time 8433656826 ps
CPU time 38.61 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:44:09 PM PDT 24
Peak memory 211936 kb
Host smart-22ded72f-0c48-4c0d-ad78-ebb1c4136385
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=989413831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.989413831
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3348332422
Short name T558
Test name
Test status
Simulation time 43855266306 ps
CPU time 137.35 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:45:37 PM PDT 24
Peak memory 205144 kb
Host smart-553d6655-6b6b-4eb5-87e0-63bc78d0a806
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3348332422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3348332422
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2133019131
Short name T677
Test name
Test status
Simulation time 239075306 ps
CPU time 19.67 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 204836 kb
Host smart-10c336c8-c3eb-4d82-b4fd-7b64fdbbb62a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133019131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2133019131
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.4183560952
Short name T395
Test name
Test status
Simulation time 622710435 ps
CPU time 10.67 seconds
Started Apr 18 12:43:21 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 203916 kb
Host smart-fd37bddb-cebc-4739-b6e4-3633d4534350
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4183560952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4183560952
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.1514056259
Short name T536
Test name
Test status
Simulation time 149373514 ps
CPU time 3.73 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:43:22 PM PDT 24
Peak memory 203388 kb
Host smart-2f0964c1-6397-4dd6-a73b-d62a16c1ab98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1514056259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1514056259
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2991841624
Short name T185
Test name
Test status
Simulation time 34656152296 ps
CPU time 53.18 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:44:12 PM PDT 24
Peak memory 203424 kb
Host smart-2c61a1cc-d0d6-44f5-ab9d-36c0ddaeb43a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991841624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2991841624
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3696539475
Short name T332
Test name
Test status
Simulation time 2520263660 ps
CPU time 22.21 seconds
Started Apr 18 12:43:19 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 203456 kb
Host smart-fd357356-9ea4-4e22-808d-bbe91f95097b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3696539475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3696539475
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1542279669
Short name T259
Test name
Test status
Simulation time 27828721 ps
CPU time 2 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:43:28 PM PDT 24
Peak memory 203372 kb
Host smart-4a6d4d95-e644-4820-b3c1-f9db763f83fb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542279669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1542279669
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3855053018
Short name T76
Test name
Test status
Simulation time 16594606336 ps
CPU time 137.85 seconds
Started Apr 18 12:43:27 PM PDT 24
Finished Apr 18 12:45:47 PM PDT 24
Peak memory 211748 kb
Host smart-fa79296d-304e-48dd-8af0-58ff949859c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3855053018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3855053018
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3462089356
Short name T519
Test name
Test status
Simulation time 232619249 ps
CPU time 57.26 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:44:22 PM PDT 24
Peak memory 207248 kb
Host smart-359c656a-a414-4e2b-bcea-a888f9b13ad1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3462089356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.3462089356
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2554168892
Short name T581
Test name
Test status
Simulation time 6524936884 ps
CPU time 218.83 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:47:08 PM PDT 24
Peak memory 219948 kb
Host smart-104ee1b3-05f2-4889-84ab-ef212bfd0cd5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2554168892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.2554168892
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2396573616
Short name T494
Test name
Test status
Simulation time 888934902 ps
CPU time 30.77 seconds
Started Apr 18 12:43:18 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 204916 kb
Host smart-d53cb500-51df-43f1-ba5c-e1e15b25e5a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2396573616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2396573616
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.4029635030
Short name T588
Test name
Test status
Simulation time 593893430 ps
CPU time 40.02 seconds
Started Apr 18 12:41:11 PM PDT 24
Finished Apr 18 12:41:52 PM PDT 24
Peak memory 204360 kb
Host smart-a4d42a62-c158-4926-b1d1-1e2af8bebb97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4029635030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.4029635030
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3699677889
Short name T115
Test name
Test status
Simulation time 64100018763 ps
CPU time 303.83 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:46:14 PM PDT 24
Peak memory 206604 kb
Host smart-973d61c8-d5af-418c-8c51-46df00c773ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3699677889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3699677889
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4111944099
Short name T751
Test name
Test status
Simulation time 537626580 ps
CPU time 5.61 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:14 PM PDT 24
Peak memory 203672 kb
Host smart-7de35118-fd81-40c1-b212-ad0af213b64b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111944099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4111944099
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.311069839
Short name T709
Test name
Test status
Simulation time 327942096 ps
CPU time 10.25 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:22 PM PDT 24
Peak memory 203488 kb
Host smart-06e10361-f9aa-4d6b-b7ab-755b0d9d0f57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=311069839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.311069839
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.2624259731
Short name T59
Test name
Test status
Simulation time 334717885 ps
CPU time 4.23 seconds
Started Apr 18 12:41:08 PM PDT 24
Finished Apr 18 12:41:14 PM PDT 24
Peak memory 203924 kb
Host smart-7b5650fd-64db-49be-b938-b443702cba30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2624259731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2624259731
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.678740575
Short name T693
Test name
Test status
Simulation time 97867108260 ps
CPU time 218.9 seconds
Started Apr 18 12:41:20 PM PDT 24
Finished Apr 18 12:44:59 PM PDT 24
Peak memory 204820 kb
Host smart-e2b00cb4-9a37-400a-9d07-5148bbb693fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=678740575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.678740575
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2502536241
Short name T267
Test name
Test status
Simulation time 44413885072 ps
CPU time 269.02 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:45:40 PM PDT 24
Peak memory 204840 kb
Host smart-2fb874e6-e15f-4568-9ad6-78ae9d63b75e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2502536241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2502536241
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3218840967
Short name T16
Test name
Test status
Simulation time 209378578 ps
CPU time 25.18 seconds
Started Apr 18 12:41:08 PM PDT 24
Finished Apr 18 12:41:35 PM PDT 24
Peak memory 204844 kb
Host smart-0485b1b1-0fd6-4c70-a93b-7cfe5983f904
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218840967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3218840967
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.530035443
Short name T371
Test name
Test status
Simulation time 547720618 ps
CPU time 11.9 seconds
Started Apr 18 12:41:32 PM PDT 24
Finished Apr 18 12:41:45 PM PDT 24
Peak memory 203372 kb
Host smart-54de4fb7-2248-4aaf-9481-1307bfcd47e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=530035443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.530035443
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.2204579429
Short name T553
Test name
Test status
Simulation time 431827052 ps
CPU time 3.59 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:12 PM PDT 24
Peak memory 203364 kb
Host smart-aec9d145-9729-4990-b178-61affcf0288f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2204579429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2204579429
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.810345110
Short name T337
Test name
Test status
Simulation time 10428413178 ps
CPU time 33.13 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:43 PM PDT 24
Peak memory 203536 kb
Host smart-dec52834-b9f0-4f76-b5c9-bd670c666634
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=810345110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.810345110
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2981544539
Short name T425
Test name
Test status
Simulation time 17282342070 ps
CPU time 37.73 seconds
Started Apr 18 12:41:04 PM PDT 24
Finished Apr 18 12:41:43 PM PDT 24
Peak memory 203428 kb
Host smart-17a3b202-00de-4719-a91e-504b3adf0d55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2981544539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2981544539
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.919448120
Short name T235
Test name
Test status
Simulation time 27862279 ps
CPU time 2.34 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:14 PM PDT 24
Peak memory 203300 kb
Host smart-ee7fb273-d1de-42bb-b658-88b0e6c65d5f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919448120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.919448120
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3420420018
Short name T665
Test name
Test status
Simulation time 1776421693 ps
CPU time 111.52 seconds
Started Apr 18 12:41:14 PM PDT 24
Finished Apr 18 12:43:06 PM PDT 24
Peak memory 206640 kb
Host smart-89f783ca-543a-4bcc-8c92-da1afe24065c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3420420018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3420420018
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2333663647
Short name T151
Test name
Test status
Simulation time 7836914438 ps
CPU time 109.47 seconds
Started Apr 18 12:41:14 PM PDT 24
Finished Apr 18 12:43:04 PM PDT 24
Peak memory 208856 kb
Host smart-1e552293-02f5-4a71-9c82-2550c35bf4c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2333663647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2333663647
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.4230494248
Short name T195
Test name
Test status
Simulation time 1962178295 ps
CPU time 375.27 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:47:23 PM PDT 24
Peak memory 208392 kb
Host smart-caa18424-2c31-489c-89d8-88d4cc5b28e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4230494248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.4230494248
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3383163928
Short name T366
Test name
Test status
Simulation time 7681035425 ps
CPU time 364.59 seconds
Started Apr 18 12:41:18 PM PDT 24
Finished Apr 18 12:47:23 PM PDT 24
Peak memory 219952 kb
Host smart-1d2681ef-ebf8-45f8-8959-2353da3b81b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3383163928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.3383163928
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.472869002
Short name T190
Test name
Test status
Simulation time 158270117 ps
CPU time 5.25 seconds
Started Apr 18 12:41:11 PM PDT 24
Finished Apr 18 12:41:17 PM PDT 24
Peak memory 204888 kb
Host smart-001b32a2-f7de-44d7-b3a1-e23227860f8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=472869002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.472869002
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3616759413
Short name T618
Test name
Test status
Simulation time 605958248 ps
CPU time 30.1 seconds
Started Apr 18 12:41:14 PM PDT 24
Finished Apr 18 12:41:46 PM PDT 24
Peak memory 205516 kb
Host smart-52e6176c-d169-46c2-a4c6-76047b4c2023
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3616759413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3616759413
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1263845517
Short name T65
Test name
Test status
Simulation time 35403364961 ps
CPU time 83.94 seconds
Started Apr 18 12:41:08 PM PDT 24
Finished Apr 18 12:42:34 PM PDT 24
Peak memory 211576 kb
Host smart-00888191-a9e8-4ba8-ba64-9b02992f4fa5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1263845517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.1263845517
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2650169232
Short name T294
Test name
Test status
Simulation time 154266380 ps
CPU time 17.63 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:41:33 PM PDT 24
Peak memory 203592 kb
Host smart-2e2309e0-ad33-4dbb-930f-15e15e7a9f67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2650169232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2650169232
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.617757497
Short name T403
Test name
Test status
Simulation time 3870206949 ps
CPU time 32.35 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:44 PM PDT 24
Peak memory 203788 kb
Host smart-dbc4244b-7d6b-44cc-acdc-1e35e2ef0b60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=617757497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.617757497
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.2113903665
Short name T780
Test name
Test status
Simulation time 81087324 ps
CPU time 11.86 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:20 PM PDT 24
Peak memory 204516 kb
Host smart-d721f007-20a5-4f29-b267-50b038833823
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2113903665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2113903665
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.143117671
Short name T736
Test name
Test status
Simulation time 31843208843 ps
CPU time 174.69 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:44:06 PM PDT 24
Peak memory 211720 kb
Host smart-380e6a55-a7db-4937-bdf0-88d4fe21c410
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=143117671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.143117671
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.516701986
Short name T674
Test name
Test status
Simulation time 7726548471 ps
CPU time 47.04 seconds
Started Apr 18 12:41:12 PM PDT 24
Finished Apr 18 12:42:00 PM PDT 24
Peak memory 204644 kb
Host smart-6cc98e32-6d35-4f73-b5af-fc03f5417a5f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=516701986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.516701986
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1207501974
Short name T691
Test name
Test status
Simulation time 78227098 ps
CPU time 11.28 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:22 PM PDT 24
Peak memory 204608 kb
Host smart-87702ab7-6a84-491a-8f57-f380f7569971
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207501974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1207501974
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.1507097975
Short name T449
Test name
Test status
Simulation time 1320520337 ps
CPU time 30.95 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:42 PM PDT 24
Peak memory 204144 kb
Host smart-f0baaa75-5f80-4b9f-bf4d-345a79e88063
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1507097975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1507097975
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.2681827344
Short name T837
Test name
Test status
Simulation time 133738909 ps
CPU time 3.59 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:14 PM PDT 24
Peak memory 203380 kb
Host smart-5f8359a0-c8d6-4442-a309-384dad33f736
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2681827344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2681827344
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3876469577
Short name T409
Test name
Test status
Simulation time 11479020113 ps
CPU time 26.72 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:38 PM PDT 24
Peak memory 203416 kb
Host smart-1334da22-bbe4-4499-837c-37124543e586
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876469577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3876469577
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3715416755
Short name T894
Test name
Test status
Simulation time 18289094949 ps
CPU time 44.24 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:50 PM PDT 24
Peak memory 203536 kb
Host smart-a4c60e53-789b-42a2-a68c-61cedea0ad9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3715416755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3715416755
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.284853343
Short name T848
Test name
Test status
Simulation time 89653866 ps
CPU time 2.25 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:10 PM PDT 24
Peak memory 203372 kb
Host smart-827b9d0c-8ee9-4416-a1eb-6709df389a3e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284853343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.284853343
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2278254452
Short name T266
Test name
Test status
Simulation time 9929379293 ps
CPU time 146.77 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 207256 kb
Host smart-543a4622-17d4-4aba-bd0f-211fa1a453fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2278254452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2278254452
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3476811241
Short name T601
Test name
Test status
Simulation time 1590137018 ps
CPU time 48.88 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:42:00 PM PDT 24
Peak memory 204520 kb
Host smart-35925fb0-13de-4789-9d90-0b8385e99ef0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3476811241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3476811241
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.478296708
Short name T246
Test name
Test status
Simulation time 513042420 ps
CPU time 187.71 seconds
Started Apr 18 12:41:18 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 211488 kb
Host smart-647c493c-666b-4e07-9739-5c65413ef082
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=478296708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.478296708
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2810199403
Short name T578
Test name
Test status
Simulation time 1452461624 ps
CPU time 240.19 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:45:42 PM PDT 24
Peak memory 211560 kb
Host smart-8a3e8058-56f1-407c-8d82-e892883252e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2810199403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.2810199403
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.33922216
Short name T758
Test name
Test status
Simulation time 1320088322 ps
CPU time 25.86 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:36 PM PDT 24
Peak memory 204920 kb
Host smart-d6cc63d8-c337-4385-88cf-3cc6a4ac4028
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33922216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.33922216
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1266072578
Short name T830
Test name
Test status
Simulation time 1508219634 ps
CPU time 46.34 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 211544 kb
Host smart-c122cbbd-6c48-4d12-8d9a-e5f9fc8762f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1266072578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1266072578
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1800709840
Short name T168
Test name
Test status
Simulation time 81441850830 ps
CPU time 323.47 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:46:35 PM PDT 24
Peak memory 211696 kb
Host smart-dabe987a-400e-43c0-8d07-57e13687fb24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1800709840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.1800709840
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3857310172
Short name T722
Test name
Test status
Simulation time 717193283 ps
CPU time 26.44 seconds
Started Apr 18 12:41:19 PM PDT 24
Finished Apr 18 12:41:46 PM PDT 24
Peak memory 203536 kb
Host smart-cb2785ce-eb76-4620-a2fe-7d34b17d05b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3857310172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3857310172
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.4148725128
Short name T394
Test name
Test status
Simulation time 980053704 ps
CPU time 17.59 seconds
Started Apr 18 12:41:29 PM PDT 24
Finished Apr 18 12:41:47 PM PDT 24
Peak memory 203428 kb
Host smart-51270680-ba11-46f7-8dd5-0c6eac3296d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4148725128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4148725128
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.1612194850
Short name T368
Test name
Test status
Simulation time 70364576 ps
CPU time 2.64 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:41:19 PM PDT 24
Peak memory 203500 kb
Host smart-77c8b6ff-d49c-4054-bbba-3ab8777a979f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1612194850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1612194850
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1159829387
Short name T402
Test name
Test status
Simulation time 4857411996 ps
CPU time 28.21 seconds
Started Apr 18 12:41:29 PM PDT 24
Finished Apr 18 12:41:58 PM PDT 24
Peak memory 204624 kb
Host smart-ae26e9a9-6ba8-4fc4-9fff-4a6409064962
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159829387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1159829387
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3644429711
Short name T393
Test name
Test status
Simulation time 81431470328 ps
CPU time 250.06 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:45:49 PM PDT 24
Peak memory 204984 kb
Host smart-5c9e77b9-9ed7-41d3-9434-c6f6b5539812
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3644429711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3644429711
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2036955925
Short name T587
Test name
Test status
Simulation time 121218117 ps
CPU time 11.78 seconds
Started Apr 18 12:41:11 PM PDT 24
Finished Apr 18 12:41:24 PM PDT 24
Peak memory 204712 kb
Host smart-4fb142b1-2bc4-4054-b10a-1e5e1214a645
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036955925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2036955925
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.3825637739
Short name T639
Test name
Test status
Simulation time 1796312160 ps
CPU time 32 seconds
Started Apr 18 12:41:09 PM PDT 24
Finished Apr 18 12:41:43 PM PDT 24
Peak memory 203388 kb
Host smart-248af510-7db7-4bfe-80a3-c59f36610c8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3825637739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3825637739
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.3189327313
Short name T557
Test name
Test status
Simulation time 24913957 ps
CPU time 2.23 seconds
Started Apr 18 12:41:16 PM PDT 24
Finished Apr 18 12:41:19 PM PDT 24
Peak memory 203420 kb
Host smart-405aacf8-f414-4a4d-a803-be02a4338c45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3189327313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3189327313
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3456035698
Short name T886
Test name
Test status
Simulation time 5561754433 ps
CPU time 29.07 seconds
Started Apr 18 12:41:16 PM PDT 24
Finished Apr 18 12:41:46 PM PDT 24
Peak memory 203520 kb
Host smart-fa3d123f-8f93-4f28-b80b-d6267ddc0b9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456035698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3456035698
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3001685193
Short name T113
Test name
Test status
Simulation time 7267753634 ps
CPU time 30.29 seconds
Started Apr 18 12:41:28 PM PDT 24
Finished Apr 18 12:41:59 PM PDT 24
Peak memory 203308 kb
Host smart-5b0d0ec8-5c7c-49a9-978d-969c0ecaca11
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3001685193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3001685193
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1437883955
Short name T723
Test name
Test status
Simulation time 35360225 ps
CPU time 1.99 seconds
Started Apr 18 12:41:14 PM PDT 24
Finished Apr 18 12:41:17 PM PDT 24
Peak memory 203440 kb
Host smart-d8540dd4-e20f-4b90-9994-208d07663ec7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437883955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1437883955
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2289646803
Short name T541
Test name
Test status
Simulation time 1134068515 ps
CPU time 134 seconds
Started Apr 18 12:41:23 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 209232 kb
Host smart-b39f34b9-5d02-4658-a2d2-f2c3cd4c4688
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2289646803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2289646803
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.4010265919
Short name T348
Test name
Test status
Simulation time 14687910053 ps
CPU time 200.99 seconds
Started Apr 18 12:41:16 PM PDT 24
Finished Apr 18 12:44:38 PM PDT 24
Peak memory 209948 kb
Host smart-948a58e3-657b-41af-abac-8d8a2f977b65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4010265919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.4010265919
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.234042656
Short name T560
Test name
Test status
Simulation time 23903437 ps
CPU time 8.13 seconds
Started Apr 18 12:41:27 PM PDT 24
Finished Apr 18 12:41:36 PM PDT 24
Peak memory 205256 kb
Host smart-14aac9c0-b0b8-4b2a-b983-2da706dc2d98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=234042656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_
reset.234042656
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3373193286
Short name T31
Test name
Test status
Simulation time 153733243 ps
CPU time 35.28 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:41:52 PM PDT 24
Peak memory 206196 kb
Host smart-88914d9a-54ed-44aa-b57d-3346477a70f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3373193286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.3373193286
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3656986912
Short name T586
Test name
Test status
Simulation time 139843123 ps
CPU time 22.18 seconds
Started Apr 18 12:41:28 PM PDT 24
Finished Apr 18 12:41:51 PM PDT 24
Peak memory 205004 kb
Host smart-df43280e-49d2-4780-9b21-a9c4fa4e1973
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3656986912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3656986912
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2907667696
Short name T387
Test name
Test status
Simulation time 2151874174 ps
CPU time 52.06 seconds
Started Apr 18 12:41:34 PM PDT 24
Finished Apr 18 12:42:27 PM PDT 24
Peak memory 206420 kb
Host smart-efe41fda-1587-4e12-8e61-ba2464332e53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2907667696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2907667696
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3480919825
Short name T327
Test name
Test status
Simulation time 133659991453 ps
CPU time 397.73 seconds
Started Apr 18 12:41:28 PM PDT 24
Finished Apr 18 12:48:06 PM PDT 24
Peak memory 206868 kb
Host smart-9c5f8c27-bb67-452c-ae30-0da5d8667bb2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3480919825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.3480919825
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.491437177
Short name T342
Test name
Test status
Simulation time 354294971 ps
CPU time 5.25 seconds
Started Apr 18 12:41:38 PM PDT 24
Finished Apr 18 12:41:46 PM PDT 24
Peak memory 203392 kb
Host smart-a6a6b6ee-f275-46ac-9a90-0f392694433d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=491437177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.491437177
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.2529480395
Short name T469
Test name
Test status
Simulation time 89298665 ps
CPU time 9.15 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:41:25 PM PDT 24
Peak memory 203484 kb
Host smart-b9d3af89-b286-4393-82e3-a2434c7ce607
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2529480395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2529480395
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.2708890745
Short name T682
Test name
Test status
Simulation time 878653708 ps
CPU time 37.02 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:41:53 PM PDT 24
Peak memory 204960 kb
Host smart-1744ed54-c9a0-46fd-9d1a-257b41cf5cc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2708890745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2708890745
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3537503664
Short name T745
Test name
Test status
Simulation time 37819201990 ps
CPU time 145.5 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 211708 kb
Host smart-96bfa7ef-d45b-49d2-b2b9-2a14cbdeb915
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537503664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3537503664
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.503726844
Short name T477
Test name
Test status
Simulation time 25358836076 ps
CPU time 215.12 seconds
Started Apr 18 12:41:27 PM PDT 24
Finished Apr 18 12:45:03 PM PDT 24
Peak memory 211600 kb
Host smart-fd44326d-8e6d-43b7-8cd9-5896ddcd0206
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=503726844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.503726844
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3587159290
Short name T752
Test name
Test status
Simulation time 204427755 ps
CPU time 14.29 seconds
Started Apr 18 12:41:25 PM PDT 24
Finished Apr 18 12:41:40 PM PDT 24
Peak memory 204528 kb
Host smart-a3953cb2-1204-4709-8dbb-e1ec13a90c08
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587159290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3587159290
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2043972208
Short name T552
Test name
Test status
Simulation time 695451707 ps
CPU time 9.23 seconds
Started Apr 18 12:41:41 PM PDT 24
Finished Apr 18 12:41:52 PM PDT 24
Peak memory 204080 kb
Host smart-5d59f7f2-26d4-4c3e-96f7-9a8ea2b540d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2043972208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2043972208
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.4147457988
Short name T862
Test name
Test status
Simulation time 31906247 ps
CPU time 2.45 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:41:18 PM PDT 24
Peak memory 203408 kb
Host smart-bdeaa5db-c7ce-4e00-b713-ccebb3875bac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4147457988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.4147457988
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.252625247
Short name T584
Test name
Test status
Simulation time 16739241090 ps
CPU time 43.09 seconds
Started Apr 18 12:41:18 PM PDT 24
Finished Apr 18 12:42:02 PM PDT 24
Peak memory 203536 kb
Host smart-175e38c4-0768-4aa7-813e-8a184910b323
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=252625247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.252625247
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.670730454
Short name T237
Test name
Test status
Simulation time 6528457069 ps
CPU time 28.43 seconds
Started Apr 18 12:41:35 PM PDT 24
Finished Apr 18 12:42:04 PM PDT 24
Peak memory 203548 kb
Host smart-1103876e-905c-4df6-bc15-5033b5f7eed7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=670730454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.670730454
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3197472788
Short name T649
Test name
Test status
Simulation time 29570185 ps
CPU time 2.37 seconds
Started Apr 18 12:41:22 PM PDT 24
Finished Apr 18 12:41:25 PM PDT 24
Peak memory 203372 kb
Host smart-e9cfb1d5-02ac-46d8-8854-c78e397ac9a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197472788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3197472788
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.104930002
Short name T108
Test name
Test status
Simulation time 3387647213 ps
CPU time 80.41 seconds
Started Apr 18 12:41:19 PM PDT 24
Finished Apr 18 12:42:41 PM PDT 24
Peak memory 206656 kb
Host smart-45aa4727-3161-46c8-bab0-1dd1ff9504b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104930002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.104930002
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.59057370
Short name T743
Test name
Test status
Simulation time 9103497503 ps
CPU time 268.96 seconds
Started Apr 18 12:41:29 PM PDT 24
Finished Apr 18 12:45:59 PM PDT 24
Peak memory 207188 kb
Host smart-ce87db0d-4927-4f6e-bb33-50ded548d93d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59057370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.59057370
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.322700328
Short name T648
Test name
Test status
Simulation time 7476961210 ps
CPU time 211.99 seconds
Started Apr 18 12:41:29 PM PDT 24
Finished Apr 18 12:45:02 PM PDT 24
Peak memory 209716 kb
Host smart-64201ffd-bd2b-4185-b4f5-093705e0b332
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=322700328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_
reset.322700328
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.623089554
Short name T322
Test name
Test status
Simulation time 257756704 ps
CPU time 78.12 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:42:51 PM PDT 24
Peak memory 207028 kb
Host smart-d9e38227-a1cb-48f6-817f-2d7314a40b33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=623089554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese
t_error.623089554
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.477129284
Short name T885
Test name
Test status
Simulation time 147308962 ps
CPU time 18.63 seconds
Started Apr 18 12:41:31 PM PDT 24
Finished Apr 18 12:41:51 PM PDT 24
Peak memory 204812 kb
Host smart-943f5be3-0344-47ee-82e1-d72ee88ee69c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=477129284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.477129284
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3798246324
Short name T640
Test name
Test status
Simulation time 587152608 ps
CPU time 35.8 seconds
Started Apr 18 12:41:27 PM PDT 24
Finished Apr 18 12:42:03 PM PDT 24
Peak memory 205188 kb
Host smart-3349fede-0de5-4f26-8a96-f07d5dba91f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3798246324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3798246324
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.789232110
Short name T83
Test name
Test status
Simulation time 57630551929 ps
CPU time 427.83 seconds
Started Apr 18 12:41:33 PM PDT 24
Finished Apr 18 12:48:42 PM PDT 24
Peak memory 207096 kb
Host smart-e8722305-6d8e-4d37-ac7c-34b3149dc471
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=789232110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow
_rsp.789232110
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1607513950
Short name T819
Test name
Test status
Simulation time 38639668 ps
CPU time 4.9 seconds
Started Apr 18 12:41:35 PM PDT 24
Finished Apr 18 12:41:41 PM PDT 24
Peak memory 203612 kb
Host smart-46f35ffb-9448-4207-b52d-d838b8ef7c97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1607513950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1607513950
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.4117907298
Short name T428
Test name
Test status
Simulation time 1194852676 ps
CPU time 14.22 seconds
Started Apr 18 12:41:17 PM PDT 24
Finished Apr 18 12:41:32 PM PDT 24
Peak memory 203340 kb
Host smart-de0fd6f1-0b59-4a98-b553-afc7a1d1c1a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4117907298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4117907298
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.1553116325
Short name T226
Test name
Test status
Simulation time 114203084 ps
CPU time 16.94 seconds
Started Apr 18 12:41:37 PM PDT 24
Finished Apr 18 12:41:55 PM PDT 24
Peak memory 211572 kb
Host smart-a9ce5e93-a16f-4ca1-8846-e9f31840896a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1553116325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1553116325
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.4237039965
Short name T806
Test name
Test status
Simulation time 4806960629 ps
CPU time 30.97 seconds
Started Apr 18 12:41:40 PM PDT 24
Finished Apr 18 12:42:13 PM PDT 24
Peak memory 204768 kb
Host smart-cf4ecb8c-1def-4632-805e-4c500b79a2b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237039965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4237039965
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1325245426
Short name T746
Test name
Test status
Simulation time 6814030918 ps
CPU time 39.58 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:42:10 PM PDT 24
Peak memory 211616 kb
Host smart-03dacb5a-c8a0-4ee4-bf7a-c731b2c2833c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1325245426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1325245426
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3862196027
Short name T592
Test name
Test status
Simulation time 188513086 ps
CPU time 15.69 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:41:46 PM PDT 24
Peak memory 204724 kb
Host smart-2c2cd514-4927-497e-9609-687b798363d2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862196027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3862196027
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3303620395
Short name T313
Test name
Test status
Simulation time 208675275 ps
CPU time 7.49 seconds
Started Apr 18 12:41:32 PM PDT 24
Finished Apr 18 12:41:40 PM PDT 24
Peak memory 204044 kb
Host smart-252018dd-a14a-47d2-81a1-89640a8567c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3303620395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3303620395
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.1868122044
Short name T93
Test name
Test status
Simulation time 123620406 ps
CPU time 3.54 seconds
Started Apr 18 12:41:33 PM PDT 24
Finished Apr 18 12:41:38 PM PDT 24
Peak memory 203420 kb
Host smart-fd51dd6e-fdfd-4644-ba58-47c1fe96ab35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1868122044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1868122044
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.776101014
Short name T484
Test name
Test status
Simulation time 9645374900 ps
CPU time 31.62 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:42:03 PM PDT 24
Peak memory 203520 kb
Host smart-41a110ac-3a7c-47fc-98c5-0ea1a970e228
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=776101014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.776101014
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2805050351
Short name T341
Test name
Test status
Simulation time 2868627223 ps
CPU time 25.16 seconds
Started Apr 18 12:41:28 PM PDT 24
Finished Apr 18 12:41:54 PM PDT 24
Peak memory 203488 kb
Host smart-c4d5ed8e-48db-451e-9212-02991d02c43b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2805050351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2805050351
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3607602350
Short name T316
Test name
Test status
Simulation time 61058048 ps
CPU time 2.47 seconds
Started Apr 18 12:41:32 PM PDT 24
Finished Apr 18 12:41:35 PM PDT 24
Peak memory 203304 kb
Host smart-47702e77-26a8-445c-b89f-90e58101314f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607602350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3607602350
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3043256245
Short name T833
Test name
Test status
Simulation time 787386011 ps
CPU time 18.54 seconds
Started Apr 18 12:41:25 PM PDT 24
Finished Apr 18 12:41:45 PM PDT 24
Peak memory 204956 kb
Host smart-579f7de3-7913-422c-bbde-08660d7ffde1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3043256245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3043256245
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.585320448
Short name T404
Test name
Test status
Simulation time 9828299861 ps
CPU time 196.55 seconds
Started Apr 18 12:41:29 PM PDT 24
Finished Apr 18 12:44:47 PM PDT 24
Peak memory 210140 kb
Host smart-c6178b83-51e5-4061-860c-9d990fb53d43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=585320448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.585320448
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.518371239
Short name T739
Test name
Test status
Simulation time 179080983 ps
CPU time 50.16 seconds
Started Apr 18 12:41:28 PM PDT 24
Finished Apr 18 12:42:19 PM PDT 24
Peak memory 206868 kb
Host smart-ad52cb75-884c-4e81-8f58-f421358394b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=518371239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_
reset.518371239
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3433894016
Short name T282
Test name
Test status
Simulation time 69205867 ps
CPU time 32.12 seconds
Started Apr 18 12:41:30 PM PDT 24
Finished Apr 18 12:42:03 PM PDT 24
Peak memory 206356 kb
Host smart-b48106e7-6aee-418f-a001-981f6b98d814
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3433894016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.3433894016
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2124627763
Short name T296
Test name
Test status
Simulation time 64679260 ps
CPU time 6.33 seconds
Started Apr 18 12:41:27 PM PDT 24
Finished Apr 18 12:41:34 PM PDT 24
Peak memory 204916 kb
Host smart-3e9971f8-26b9-4ccc-af9d-2c72e8a56729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2124627763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2124627763
Directory /workspace/9.xbar_unmapped_addr/latest
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