Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	99.26	88.94	98.80		95.88	99.26	100.00

Total test records in report: 900

T762	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2376790982	Apr 21 12:27:09 PM PDT 24	Apr 21 12:27:12 PM PDT 24	119387381 ps
T763	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3732163739	Apr 21 12:27:29 PM PDT 24	Apr 21 12:27:58 PM PDT 24	7158538394 ps
T764	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1883453729	Apr 21 12:28:04 PM PDT 24	Apr 21 12:28:07 PM PDT 24	50979762 ps
T765	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.987908762	Apr 21 12:28:04 PM PDT 24	Apr 21 12:28:49 PM PDT 24	17159730113 ps
T766	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.956476562	Apr 21 12:26:38 PM PDT 24	Apr 21 12:28:27 PM PDT 24	16217556852 ps
T767	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2618946090	Apr 21 12:27:31 PM PDT 24	Apr 21 12:27:40 PM PDT 24	105838939 ps
T768	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1428013836	Apr 21 12:27:18 PM PDT 24	Apr 21 12:27:49 PM PDT 24	9552600691 ps
T769	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2120466453	Apr 21 12:27:26 PM PDT 24	Apr 21 12:27:29 PM PDT 24	34407227 ps
T230	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.592878580	Apr 21 12:27:37 PM PDT 24	Apr 21 12:31:06 PM PDT 24	64021572597 ps
T125	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3389592208	Apr 21 12:26:46 PM PDT 24	Apr 21 12:34:11 PM PDT 24	21101125307 ps
T770	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2749742318	Apr 21 12:27:24 PM PDT 24	Apr 21 12:27:47 PM PDT 24	653903320 ps
T771	/workspace/coverage/xbar_build_mode/38.xbar_same_source.723438883	Apr 21 12:28:00 PM PDT 24	Apr 21 12:28:05 PM PDT 24	68806987 ps
T772	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3416086718	Apr 21 12:27:47 PM PDT 24	Apr 21 12:28:06 PM PDT 24	177887946 ps
T773	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2720418641	Apr 21 12:27:24 PM PDT 24	Apr 21 12:30:20 PM PDT 24	18502322593 ps
T774	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4210710851	Apr 21 12:27:48 PM PDT 24	Apr 21 12:28:20 PM PDT 24	2230868528 ps
T35	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2345322519	Apr 21 12:27:43 PM PDT 24	Apr 21 12:33:14 PM PDT 24	2208630915 ps
T775	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1830383410	Apr 21 12:26:59 PM PDT 24	Apr 21 12:27:50 PM PDT 24	4622635223 ps
T188	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1026008421	Apr 21 12:27:24 PM PDT 24	Apr 21 12:27:50 PM PDT 24	1162415749 ps
T776	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.829877180	Apr 21 12:29:10 PM PDT 24	Apr 21 12:33:51 PM PDT 24	19058718106 ps
T777	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2476344122	Apr 21 12:27:29 PM PDT 24	Apr 21 12:27:50 PM PDT 24	2022682060 ps
T778	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1744602244	Apr 21 12:26:50 PM PDT 24	Apr 21 12:31:10 PM PDT 24	775173968 ps
T779	/workspace/coverage/xbar_build_mode/4.xbar_smoke.4090514557	Apr 21 12:26:47 PM PDT 24	Apr 21 12:26:52 PM PDT 24	799421211 ps
T780	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1167396254	Apr 21 12:26:38 PM PDT 24	Apr 21 12:26:41 PM PDT 24	55112822 ps
T781	/workspace/coverage/xbar_build_mode/48.xbar_smoke.1663706561	Apr 21 12:28:35 PM PDT 24	Apr 21 12:28:38 PM PDT 24	184563207 ps
T782	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4227619544	Apr 21 12:27:57 PM PDT 24	Apr 21 12:33:54 PM PDT 24	47740234804 ps
T783	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.704292768	Apr 21 12:27:49 PM PDT 24	Apr 21 12:28:32 PM PDT 24	17048335963 ps
T784	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1208129429	Apr 21 12:26:51 PM PDT 24	Apr 21 12:27:24 PM PDT 24	2297981275 ps
T129	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.612992361	Apr 21 12:26:50 PM PDT 24	Apr 21 12:29:09 PM PDT 24	3869755191 ps
T785	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2672667931	Apr 21 12:28:08 PM PDT 24	Apr 21 12:28:20 PM PDT 24	192137798 ps
T786	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1677964069	Apr 21 12:27:22 PM PDT 24	Apr 21 12:27:24 PM PDT 24	57290673 ps
T787	/workspace/coverage/xbar_build_mode/0.xbar_error_random.669090512	Apr 21 12:26:33 PM PDT 24	Apr 21 12:26:50 PM PDT 24	128256347 ps
T788	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2631822140	Apr 21 12:28:26 PM PDT 24	Apr 21 12:28:31 PM PDT 24	390977381 ps
T789	/workspace/coverage/xbar_build_mode/29.xbar_same_source.677224774	Apr 21 12:27:55 PM PDT 24	Apr 21 12:28:14 PM PDT 24	953073951 ps
T790	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1178389454	Apr 21 12:28:22 PM PDT 24	Apr 21 12:32:03 PM PDT 24	36735248297 ps
T791	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2420777966	Apr 21 12:29:36 PM PDT 24	Apr 21 12:29:52 PM PDT 24	243363368 ps
T126	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.3865085371	Apr 21 12:27:48 PM PDT 24	Apr 21 12:30:06 PM PDT 24	6822548273 ps
T792	/workspace/coverage/xbar_build_mode/33.xbar_smoke.1891293465	Apr 21 12:27:52 PM PDT 24	Apr 21 12:28:01 PM PDT 24	352978563 ps
T793	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2043761759	Apr 21 12:27:59 PM PDT 24	Apr 21 12:29:51 PM PDT 24	17278882063 ps
T794	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3913921244	Apr 21 12:28:13 PM PDT 24	Apr 21 12:28:16 PM PDT 24	41995311 ps
T189	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1714042575	Apr 21 12:28:39 PM PDT 24	Apr 21 12:40:00 PM PDT 24	145159827377 ps
T147	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.1960574324	Apr 21 12:27:31 PM PDT 24	Apr 21 12:29:34 PM PDT 24	4781411840 ps
T795	/workspace/coverage/xbar_build_mode/11.xbar_error_random.2940439464	Apr 21 12:27:13 PM PDT 24	Apr 21 12:27:24 PM PDT 24	1144896087 ps
T796	/workspace/coverage/xbar_build_mode/40.xbar_random.381144939	Apr 21 12:28:10 PM PDT 24	Apr 21 12:28:23 PM PDT 24	140226867 ps
T797	/workspace/coverage/xbar_build_mode/14.xbar_random.2758017621	Apr 21 12:26:51 PM PDT 24	Apr 21 12:27:12 PM PDT 24	175123299 ps
T798	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.217055618	Apr 21 12:26:38 PM PDT 24	Apr 21 12:27:46 PM PDT 24	9384936978 ps
T799	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3356291346	Apr 21 12:28:20 PM PDT 24	Apr 21 12:29:22 PM PDT 24	778015159 ps
T800	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2964367910	Apr 21 12:27:52 PM PDT 24	Apr 21 12:28:12 PM PDT 24	1438607472 ps
T801	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.182530678	Apr 21 12:27:11 PM PDT 24	Apr 21 12:31:27 PM PDT 24	5401978217 ps
T802	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1827733729	Apr 21 12:27:00 PM PDT 24	Apr 21 12:32:55 PM PDT 24	141830218160 ps
T803	/workspace/coverage/xbar_build_mode/36.xbar_error_random.2043692621	Apr 21 12:27:51 PM PDT 24	Apr 21 12:27:56 PM PDT 24	734250156 ps
T804	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2946389024	Apr 21 12:26:38 PM PDT 24	Apr 21 12:27:17 PM PDT 24	12443467211 ps
T805	/workspace/coverage/xbar_build_mode/10.xbar_smoke.1337043414	Apr 21 12:26:59 PM PDT 24	Apr 21 12:27:03 PM PDT 24	172639220 ps
T806	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3959388906	Apr 21 12:26:47 PM PDT 24	Apr 21 12:26:58 PM PDT 24	496096489 ps
T807	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.1840078793	Apr 21 12:27:33 PM PDT 24	Apr 21 12:27:54 PM PDT 24	199272503 ps
T808	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1304507271	Apr 21 12:26:32 PM PDT 24	Apr 21 12:26:35 PM PDT 24	25829848 ps
T809	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.419860270	Apr 21 12:27:57 PM PDT 24	Apr 21 12:28:18 PM PDT 24	163515068 ps
T810	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2968720946	Apr 21 12:26:41 PM PDT 24	Apr 21 12:28:21 PM PDT 24	13307895846 ps
T811	/workspace/coverage/xbar_build_mode/26.xbar_smoke.2146681857	Apr 21 12:27:28 PM PDT 24	Apr 21 12:27:32 PM PDT 24	146373402 ps
T812	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3746173033	Apr 21 12:29:10 PM PDT 24	Apr 21 12:30:39 PM PDT 24	4367803958 ps
T813	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3583678538	Apr 21 12:27:46 PM PDT 24	Apr 21 12:27:49 PM PDT 24	31860162 ps
T814	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3131781827	Apr 21 12:28:37 PM PDT 24	Apr 21 12:28:46 PM PDT 24	483380551 ps
T815	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.4293563660	Apr 21 12:26:58 PM PDT 24	Apr 21 12:31:37 PM PDT 24	82354093154 ps
T816	/workspace/coverage/xbar_build_mode/49.xbar_error_random.2995516303	Apr 21 12:28:41 PM PDT 24	Apr 21 12:28:48 PM PDT 24	173662039 ps
T817	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1782380988	Apr 21 12:28:20 PM PDT 24	Apr 21 12:28:48 PM PDT 24	4496035401 ps
T818	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.4134726575	Apr 21 12:27:09 PM PDT 24	Apr 21 12:27:21 PM PDT 24	108175513 ps
T819	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3909981827	Apr 21 12:27:06 PM PDT 24	Apr 21 12:27:39 PM PDT 24	8984993986 ps
T820	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.2351781774	Apr 21 12:26:51 PM PDT 24	Apr 21 12:29:21 PM PDT 24	9152283428 ps
T821	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1774920649	Apr 21 12:27:10 PM PDT 24	Apr 21 12:27:41 PM PDT 24	691209432 ps
T822	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.597509022	Apr 21 12:27:19 PM PDT 24	Apr 21 12:27:22 PM PDT 24	13940617 ps
T823	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.582564527	Apr 21 12:28:21 PM PDT 24	Apr 21 12:32:45 PM PDT 24	9807879093 ps
T824	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3444554223	Apr 21 12:26:42 PM PDT 24	Apr 21 12:27:16 PM PDT 24	9265949062 ps
T825	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.1399744676	Apr 21 12:29:23 PM PDT 24	Apr 21 12:31:04 PM PDT 24	1368628725 ps
T826	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3400338771	Apr 21 12:27:20 PM PDT 24	Apr 21 12:27:45 PM PDT 24	10441719999 ps
T827	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3455374263	Apr 21 12:27:49 PM PDT 24	Apr 21 12:28:13 PM PDT 24	679575337 ps
T828	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4177085107	Apr 21 12:28:05 PM PDT 24	Apr 21 12:30:36 PM PDT 24	1147072131 ps
T829	/workspace/coverage/xbar_build_mode/16.xbar_error_random.4117874242	Apr 21 12:27:12 PM PDT 24	Apr 21 12:27:36 PM PDT 24	1082851198 ps
T830	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.760195855	Apr 21 12:27:26 PM PDT 24	Apr 21 12:32:42 PM PDT 24	824094283 ps
T831	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3619986001	Apr 21 12:26:51 PM PDT 24	Apr 21 12:27:17 PM PDT 24	5103046544 ps
T832	/workspace/coverage/xbar_build_mode/47.xbar_random.452460613	Apr 21 12:28:22 PM PDT 24	Apr 21 12:28:49 PM PDT 24	612642352 ps
T833	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2321487148	Apr 21 12:27:28 PM PDT 24	Apr 21 12:27:32 PM PDT 24	50081628 ps
T834	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3013547570	Apr 21 12:26:38 PM PDT 24	Apr 21 12:27:02 PM PDT 24	856788279 ps
T835	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3523300282	Apr 21 12:27:31 PM PDT 24	Apr 21 12:29:26 PM PDT 24	24029034784 ps
T836	/workspace/coverage/xbar_build_mode/21.xbar_smoke.973759541	Apr 21 12:27:24 PM PDT 24	Apr 21 12:27:28 PM PDT 24	177128857 ps
T837	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3163621935	Apr 21 12:27:16 PM PDT 24	Apr 21 12:30:23 PM PDT 24	26490344516 ps
T838	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1580998245	Apr 21 12:26:52 PM PDT 24	Apr 21 12:27:00 PM PDT 24	404698475 ps
T839	/workspace/coverage/xbar_build_mode/17.xbar_random.1730321985	Apr 21 12:27:10 PM PDT 24	Apr 21 12:27:26 PM PDT 24	720432273 ps
T840	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.318960045	Apr 21 12:27:48 PM PDT 24	Apr 21 12:27:51 PM PDT 24	86585208 ps
T841	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1716335362	Apr 21 12:28:00 PM PDT 24	Apr 21 12:28:09 PM PDT 24	234819307 ps
T842	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2494658410	Apr 21 12:27:18 PM PDT 24	Apr 21 12:27:27 PM PDT 24	121358260 ps
T843	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.253904458	Apr 21 12:27:01 PM PDT 24	Apr 21 12:27:35 PM PDT 24	7969537157 ps
T844	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3079806408	Apr 21 12:27:02 PM PDT 24	Apr 21 12:27:27 PM PDT 24	188404359 ps
T845	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2080646043	Apr 21 12:27:54 PM PDT 24	Apr 21 12:29:52 PM PDT 24	3711366432 ps
T846	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.613610570	Apr 21 12:26:45 PM PDT 24	Apr 21 12:27:05 PM PDT 24	194561178 ps
T847	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3993588557	Apr 21 12:27:18 PM PDT 24	Apr 21 12:27:21 PM PDT 24	79132289 ps
T848	/workspace/coverage/xbar_build_mode/11.xbar_random.3853709306	Apr 21 12:27:14 PM PDT 24	Apr 21 12:27:41 PM PDT 24	987847519 ps
T849	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.412636802	Apr 21 12:26:35 PM PDT 24	Apr 21 12:29:05 PM PDT 24	1541541040 ps
T850	/workspace/coverage/xbar_build_mode/18.xbar_same_source.2080229055	Apr 21 12:27:19 PM PDT 24	Apr 21 12:27:39 PM PDT 24	1125302850 ps
T851	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3937614227	Apr 21 12:26:41 PM PDT 24	Apr 21 12:27:12 PM PDT 24	5915386781 ps
T852	/workspace/coverage/xbar_build_mode/44.xbar_same_source.3965643411	Apr 21 12:29:39 PM PDT 24	Apr 21 12:29:55 PM PDT 24	1092157053 ps
T853	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.767825727	Apr 21 12:27:31 PM PDT 24	Apr 21 12:27:44 PM PDT 24	196006785 ps
T854	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1557671425	Apr 21 12:27:07 PM PDT 24	Apr 21 12:28:48 PM PDT 24	10326524707 ps
T855	/workspace/coverage/xbar_build_mode/18.xbar_smoke.1650718776	Apr 21 12:27:17 PM PDT 24	Apr 21 12:27:20 PM PDT 24	31148209 ps
T856	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4203041789	Apr 21 12:28:18 PM PDT 24	Apr 21 12:28:35 PM PDT 24	6573878 ps
T857	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1864826139	Apr 21 12:27:12 PM PDT 24	Apr 21 12:27:41 PM PDT 24	249609336 ps
T229	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2267376241	Apr 21 12:27:43 PM PDT 24	Apr 21 12:28:32 PM PDT 24	23975805659 ps
T858	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3304707021	Apr 21 12:27:56 PM PDT 24	Apr 21 12:28:03 PM PDT 24	149531064 ps
T859	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1490650713	Apr 21 12:27:55 PM PDT 24	Apr 21 12:28:38 PM PDT 24	8068858200 ps
T860	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.134247229	Apr 21 12:27:23 PM PDT 24	Apr 21 12:27:35 PM PDT 24	12690644 ps
T861	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.684673605	Apr 21 12:27:24 PM PDT 24	Apr 21 12:27:32 PM PDT 24	97516426 ps
T862	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.291993604	Apr 21 12:29:09 PM PDT 24	Apr 21 12:29:13 PM PDT 24	58725704 ps
T863	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3719311292	Apr 21 12:28:03 PM PDT 24	Apr 21 12:30:04 PM PDT 24	2048270029 ps
T864	/workspace/coverage/xbar_build_mode/31.xbar_error_random.1028073648	Apr 21 12:27:37 PM PDT 24	Apr 21 12:27:55 PM PDT 24	579999696 ps
T865	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3745798986	Apr 21 12:27:39 PM PDT 24	Apr 21 12:28:16 PM PDT 24	3715964644 ps
T866	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.3234894787	Apr 21 12:26:47 PM PDT 24	Apr 21 12:28:32 PM PDT 24	4082205226 ps
T867	/workspace/coverage/xbar_build_mode/25.xbar_smoke.183659745	Apr 21 12:27:57 PM PDT 24	Apr 21 12:27:59 PM PDT 24	23434099 ps
T868	/workspace/coverage/xbar_build_mode/28.xbar_random.3152809141	Apr 21 12:27:33 PM PDT 24	Apr 21 12:27:50 PM PDT 24	358663231 ps
T869	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2280748785	Apr 21 12:27:46 PM PDT 24	Apr 21 12:27:51 PM PDT 24	29792432 ps
T870	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2352393292	Apr 21 12:27:07 PM PDT 24	Apr 21 12:27:12 PM PDT 24	31350273 ps
T871	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.603452158	Apr 21 12:27:50 PM PDT 24	Apr 21 12:28:04 PM PDT 24	3892114497 ps
T872	/workspace/coverage/xbar_build_mode/37.xbar_random.1823909713	Apr 21 12:27:53 PM PDT 24	Apr 21 12:28:14 PM PDT 24	365166150 ps
T139	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4193198367	Apr 21 12:26:58 PM PDT 24	Apr 21 12:35:57 PM PDT 24	54678507484 ps
T873	/workspace/coverage/xbar_build_mode/3.xbar_error_random.2186474510	Apr 21 12:26:45 PM PDT 24	Apr 21 12:26:59 PM PDT 24	641906592 ps
T874	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.2417644767	Apr 21 12:27:50 PM PDT 24	Apr 21 12:28:47 PM PDT 24	2508936916 ps
T875	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2200532243	Apr 21 12:28:08 PM PDT 24	Apr 21 12:32:27 PM PDT 24	992594568 ps
T876	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3146491907	Apr 21 12:27:35 PM PDT 24	Apr 21 12:29:30 PM PDT 24	5789396116 ps
T877	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1333297595	Apr 21 12:28:20 PM PDT 24	Apr 21 12:28:54 PM PDT 24	5194688262 ps
T878	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.267375300	Apr 21 12:27:13 PM PDT 24	Apr 21 12:30:12 PM PDT 24	135700054006 ps
T879	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1676822967	Apr 21 12:28:17 PM PDT 24	Apr 21 12:30:20 PM PDT 24	19985956190 ps
T880	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.4143140034	Apr 21 12:27:06 PM PDT 24	Apr 21 12:27:38 PM PDT 24	4564045124 ps
T881	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2261431873	Apr 21 12:28:18 PM PDT 24	Apr 21 12:28:29 PM PDT 24	100146217 ps
T882	/workspace/coverage/xbar_build_mode/23.xbar_same_source.2487048228	Apr 21 12:27:30 PM PDT 24	Apr 21 12:27:34 PM PDT 24	111256365 ps
T883	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.286447776	Apr 21 12:28:28 PM PDT 24	Apr 21 12:28:39 PM PDT 24	157630583 ps
T884	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1938925389	Apr 21 12:29:10 PM PDT 24	Apr 21 12:32:43 PM PDT 24	80839888892 ps
T885	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.909509148	Apr 21 12:27:46 PM PDT 24	Apr 21 12:27:50 PM PDT 24	140468265 ps
T886	/workspace/coverage/xbar_build_mode/13.xbar_same_source.1418012036	Apr 21 12:26:53 PM PDT 24	Apr 21 12:26:56 PM PDT 24	132723479 ps
T887	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1446237598	Apr 21 12:28:14 PM PDT 24	Apr 21 12:28:18 PM PDT 24	369613630 ps
T888	/workspace/coverage/xbar_build_mode/14.xbar_smoke.372777521	Apr 21 12:27:12 PM PDT 24	Apr 21 12:27:16 PM PDT 24	242041153 ps
T889	/workspace/coverage/xbar_build_mode/1.xbar_error_random.1480419294	Apr 21 12:26:48 PM PDT 24	Apr 21 12:26:53 PM PDT 24	452925727 ps
T890	/workspace/coverage/xbar_build_mode/6.xbar_error_random.1544970864	Apr 21 12:26:48 PM PDT 24	Apr 21 12:26:56 PM PDT 24	280274073 ps
T891	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2809810965	Apr 21 12:26:54 PM PDT 24	Apr 21 12:33:50 PM PDT 24	1143086056 ps
T892	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2261525499	Apr 21 12:27:29 PM PDT 24	Apr 21 12:30:16 PM PDT 24	7088814910 ps
T893	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4087570860	Apr 21 12:27:19 PM PDT 24	Apr 21 12:27:55 PM PDT 24	11689523513 ps
T894	/workspace/coverage/xbar_build_mode/24.xbar_random.1086678833	Apr 21 12:27:55 PM PDT 24	Apr 21 12:28:11 PM PDT 24	486223210 ps
T895	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.709222300	Apr 21 12:28:07 PM PDT 24	Apr 21 12:28:34 PM PDT 24	9945825629 ps
T896	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3133019718	Apr 21 12:28:22 PM PDT 24	Apr 21 12:28:54 PM PDT 24	822770775 ps
T897	/workspace/coverage/xbar_build_mode/33.xbar_random.4011257754	Apr 21 12:28:07 PM PDT 24	Apr 21 12:28:29 PM PDT 24	405362542 ps
T34	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.468717531	Apr 21 12:27:03 PM PDT 24	Apr 21 12:29:13 PM PDT 24	178596508 ps
T898	/workspace/coverage/xbar_build_mode/20.xbar_error_random.3553626930	Apr 21 12:27:26 PM PDT 24	Apr 21 12:27:44 PM PDT 24	826102485 ps
T899	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3423985025	Apr 21 12:26:55 PM PDT 24	Apr 21 12:27:18 PM PDT 24	109452734 ps
T900	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1796664897	Apr 21 12:27:30 PM PDT 24	Apr 21 12:29:08 PM PDT 24	303725785 ps

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3519392910
Short name	T13
Test name
Test status
Simulation time	4707749393 ps
CPU time	108.93 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:30:04 PM PDT 24
Peak memory	206172 kb
Host	smart-c1d38542-64f9-4d3d-afd9-81b9011432d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3519392910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3519392910
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1264086996
Short name	T74
Test name
Test status
Simulation time	126303360165 ps
CPU time	679.02 seconds
Started	Apr 21 12:27:44 PM PDT 24
Finished	Apr 21 12:39:04 PM PDT 24
Peak memory	207668 kb
Host	smart-a5ffd4da-f5bd-45cb-909a-62d99254c7d1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1264086996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1264086996
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3972596165
Short name	T83
Test name
Test status
Simulation time	130714071472 ps
CPU time	536.29 seconds
Started	Apr 21 12:27:06 PM PDT 24
Finished	Apr 21 12:36:03 PM PDT 24
Peak memory	211488 kb
Host	smart-3726ebf1-6717-43b3-9cd0-c7f45e7f5e61
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3972596165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3972596165
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.943293323
Short name	T92
Test name
Test status
Simulation time	81812586476 ps
CPU time	592.48 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:37:02 PM PDT 24
Peak memory	207252 kb
Host	smart-499851d3-dd19-4efb-9e5f-b7bc484828f9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=943293323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo w_rsp.943293323
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3261249802
Short name	T4
Test name
Test status
Simulation time	3330669603 ps
CPU time	30.74 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	203304 kb
Host	smart-1c35be4c-e452-4920-95e5-64276ee49709
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3261249802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3261249802
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.711328327
Short name	T8
Test name
Test status
Simulation time	5311508457 ps
CPU time	237.44 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:31:07 PM PDT 24
Peak memory	211572 kb
Host	smart-d2341442-3d6c-4771-8034-0c520e5573cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711328327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.711328327
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.751432099
Short name	T104
Test name
Test status
Simulation time	50081226056 ps
CPU time	359.93 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:34:22 PM PDT 24
Peak memory	211504 kb
Host	smart-bd281ef9-ad84-4d53-ba0a-01e96bb6cb45
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=751432099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo w_rsp.751432099
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1113772844
Short name	T96
Test name
Test status
Simulation time	115521034805 ps
CPU time	226.3 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:32:15 PM PDT 24
Peak memory	204684 kb
Host	smart-4f420ee6-e4f5-4ca9-8fb8-10e347bc0a4a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113772844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1113772844
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.548999193
Short name	T28
Test name
Test status
Simulation time	15781981871 ps
CPU time	321.37 seconds
Started	Apr 21 12:27:56 PM PDT 24
Finished	Apr 21 12:33:18 PM PDT 24
Peak memory	209860 kb
Host	smart-af0d6015-69ce-4ebf-8233-7ecc8b47681a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=548999193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand _reset.548999193
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2764244471
Short name	T381
Test name
Test status
Simulation time	370144767 ps
CPU time	97.87 seconds
Started	Apr 21 12:27:56 PM PDT 24
Finished	Apr 21 12:29:34 PM PDT 24
Peak memory	209156 kb
Host	smart-ca843890-880b-4640-8d09-72cf965e23ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2764244471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2764244471
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3440186736
Short name	T123
Test name
Test status
Simulation time	6888542270 ps
CPU time	520.51 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:36:55 PM PDT 24
Peak memory	211624 kb
Host	smart-0565acdb-68d7-4b75-9fce-741f6b0f4d43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440186736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3440186736
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.3539160735
Short name	T45
Test name
Test status
Simulation time	4956546334 ps
CPU time	96.98 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:29:30 PM PDT 24
Peak memory	211508 kb
Host	smart-12b7b3ed-4bdb-4e51-91cc-fbfbc91718b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3539160735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3539160735
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2726568220
Short name	T121
Test name
Test status
Simulation time	9921521247 ps
CPU time	625.58 seconds
Started	Apr 21 12:28:02 PM PDT 24
Finished	Apr 21 12:38:28 PM PDT 24
Peak memory	219796 kb
Host	smart-b1596a20-142f-4715-984b-7dbe0658126b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2726568220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2726568220
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.824618270
Short name	T38
Test name
Test status
Simulation time	623006255 ps
CPU time	177.3 seconds
Started	Apr 21 12:26:49 PM PDT 24
Finished	Apr 21 12:29:47 PM PDT 24
Peak memory	210188 kb
Host	smart-96bd2fe3-c5e9-4184-96fe-6e90b8f2050e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=824618270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.824618270
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3841093694
Short name	T114
Test name
Test status
Simulation time	80239322983 ps
CPU time	516.61 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:35:53 PM PDT 24
Peak memory	207136 kb
Host	smart-5bc93680-3866-444c-8c64-79f54a99afd9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3841093694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.3841093694
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.468717531
Short name	T34
Test name
Test status
Simulation time	178596508 ps
CPU time	130.2 seconds
Started	Apr 21 12:27:03 PM PDT 24
Finished	Apr 21 12:29:13 PM PDT 24
Peak memory	209648 kb
Host	smart-beb34dab-bac5-4a22-bdc2-5e00c96049d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=468717531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.468717531
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3323140090
Short name	T254
Test name
Test status
Simulation time	131193957 ps
CPU time	3.55 seconds
Started	Apr 21 12:26:46 PM PDT 24
Finished	Apr 21 12:26:50 PM PDT 24
Peak memory	203320 kb
Host	smart-a6c2b113-67d5-49d2-8785-6689aa9d2a3e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3323140090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3323140090
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2345322519
Short name	T35
Test name
Test status
Simulation time	2208630915 ps
CPU time	329.26 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:33:14 PM PDT 24
Peak memory	209572 kb
Host	smart-f06642f3-3c43-497b-9d49-1fb129de01f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2345322519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.2345322519
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.860442743
Short name	T25
Test name
Test status
Simulation time	20075867625 ps
CPU time	362.46 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:34:23 PM PDT 24
Peak memory	221492 kb
Host	smart-9f4f6195-9f75-4e05-82ff-257819ff037b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=860442743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res et_error.860442743
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3553438318
Short name	T9
Test name
Test status
Simulation time	124919431 ps
CPU time	47.91 seconds
Started	Apr 21 12:28:43 PM PDT 24
Finished	Apr 21 12:29:32 PM PDT 24
Peak memory	208104 kb
Host	smart-58195c17-96e8-4f21-aaa4-be63bc6f201c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3553438318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3553438318
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.379593127
Short name	T454
Test name
Test status
Simulation time	68023993 ps
CPU time	13.57 seconds
Started	Apr 21 12:26:36 PM PDT 24
Finished	Apr 21 12:26:50 PM PDT 24
Peak memory	204280 kb
Host	smart-1e2a53be-0bae-4c5c-9b2e-394cd2a63e4e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=379593127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.379593127
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3885489728
Short name	T738
Test name
Test status
Simulation time	259775427613 ps
CPU time	757.82 seconds
Started	Apr 21 12:26:29 PM PDT 24
Finished	Apr 21 12:39:08 PM PDT 24
Peak memory	207264 kb
Host	smart-039e4f9d-63d8-41f9-853d-24d77c7db759
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3885489728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.3885489728
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1304507271
Short name	T808
Test name
Test status
Simulation time	25829848 ps
CPU time	2.64 seconds
Started	Apr 21 12:26:32 PM PDT 24
Finished	Apr 21 12:26:35 PM PDT 24
Peak memory	203260 kb
Host	smart-c0071a22-e1b4-4af0-b977-673f066570f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1304507271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1304507271
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.669090512
Short name	T787
Test name
Test status
Simulation time	128256347 ps
CPU time	16.58 seconds
Started	Apr 21 12:26:33 PM PDT 24
Finished	Apr 21 12:26:50 PM PDT 24
Peak memory	203276 kb
Host	smart-6615fee6-f0e6-4b37-b1b4-8bb9d36307dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=669090512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.669090512
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.3073538564
Short name	T747
Test name
Test status
Simulation time	349579003 ps
CPU time	14.46 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:27:15 PM PDT 24
Peak memory	211536 kb
Host	smart-ae9ac034-569a-4a8d-9060-eed86c5cfcc9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3073538564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3073538564
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1632853860
Short name	T641
Test name
Test status
Simulation time	37332591539 ps
CPU time	180.52 seconds
Started	Apr 21 12:26:41 PM PDT 24
Finished	Apr 21 12:29:42 PM PDT 24
Peak memory	211548 kb
Host	smart-d35fc346-181e-4ece-9a13-69b6aee3ae4e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632853860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1632853860
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1295145513
Short name	T337
Test name
Test status
Simulation time	39257843566 ps
CPU time	140.11 seconds
Started	Apr 21 12:26:56 PM PDT 24
Finished	Apr 21 12:29:17 PM PDT 24
Peak memory	211476 kb
Host	smart-28810c81-b3e6-47d9-8dad-31fd08841167
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1295145513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1295145513
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2176895834
Short name	T310
Test name
Test status
Simulation time	60739172 ps
CPU time	8.22 seconds
Started	Apr 21 12:27:02 PM PDT 24
Finished	Apr 21 12:27:11 PM PDT 24
Peak memory	204528 kb
Host	smart-1caaec1e-baa7-420d-93a7-7fb861048e53
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176895834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2176895834
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.2020152642
Short name	T680
Test name
Test status
Simulation time	1353264162 ps
CPU time	21.93 seconds
Started	Apr 21 12:26:26 PM PDT 24
Finished	Apr 21 12:26:49 PM PDT 24
Peak memory	203276 kb
Host	smart-2da062d2-af11-485c-a7fd-ed72094df578
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2020152642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2020152642
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.3284403295
Short name	T316
Test name
Test status
Simulation time	26232238 ps
CPU time	2.05 seconds
Started	Apr 21 12:26:35 PM PDT 24
Finished	Apr 21 12:26:38 PM PDT 24
Peak memory	203332 kb
Host	smart-f5b98ec6-4705-4a80-a65b-163a192fb012
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3284403295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3284403295
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.4187067531
Short name	T315
Test name
Test status
Simulation time	10429335797 ps
CPU time	31.72 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:27:11 PM PDT 24
Peak memory	203304 kb
Host	smart-09329af7-8a2b-4c1f-88df-15138e6fdf9f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187067531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4187067531
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.555149793
Short name	T731
Test name
Test status
Simulation time	5143957544 ps
CPU time	30.35 seconds
Started	Apr 21 12:26:44 PM PDT 24
Finished	Apr 21 12:27:14 PM PDT 24
Peak memory	203312 kb
Host	smart-a6ea9a1d-459d-46d0-bd32-e0abf906fb61
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=555149793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.555149793
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1539651935
Short name	T163
Test name
Test status
Simulation time	43973740 ps
CPU time	2.26 seconds
Started	Apr 21 12:26:45 PM PDT 24
Finished	Apr 21 12:26:47 PM PDT 24
Peak memory	203264 kb
Host	smart-765fbc62-5906-4976-bd9a-22c8e55341eb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539651935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1539651935
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.9782978
Short name	T269
Test name
Test status
Simulation time	795459645 ps
CPU time	32.52 seconds
Started	Apr 21 12:27:04 PM PDT 24
Finished	Apr 21 12:27:37 PM PDT 24
Peak memory	205860 kb
Host	smart-95f31b1d-1d1f-4f01-b54e-305c64bb58bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=9782978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.9782978
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3780688660
Short name	T430
Test name
Test status
Simulation time	5462189139 ps
CPU time	44.81 seconds
Started	Apr 21 12:26:57 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	205072 kb
Host	smart-51e59fbf-7812-42c9-b016-0b456a281390
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3780688660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3780688660
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.568278604
Short name	T760
Test name
Test status
Simulation time	29081610 ps
CPU time	3.74 seconds
Started	Apr 21 12:26:49 PM PDT 24
Finished	Apr 21 12:26:53 PM PDT 24
Peak memory	204768 kb
Host	smart-c815f45a-a4ee-41dd-8a53-162a4af220d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=568278604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_ reset.568278604
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1182640963
Short name	T537
Test name
Test status
Simulation time	363268458 ps
CPU time	99.34 seconds
Started	Apr 21 12:26:45 PM PDT 24
Finished	Apr 21 12:28:25 PM PDT 24
Peak memory	209300 kb
Host	smart-07c47d22-6d36-4d17-a60e-fcc70f91773c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1182640963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.1182640963
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.4171891246
Short name	T473
Test name
Test status
Simulation time	110920864 ps
CPU time	10.78 seconds
Started	Apr 21 12:26:36 PM PDT 24
Finished	Apr 21 12:26:47 PM PDT 24
Peak memory	204600 kb
Host	smart-3a5de13a-5422-4195-9a4e-30b1b45c4c61
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4171891246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.4171891246
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.758655194
Short name	T232
Test name
Test status
Simulation time	1400073169 ps
CPU time	43.99 seconds
Started	Apr 21 12:26:41 PM PDT 24
Finished	Apr 21 12:27:26 PM PDT 24
Peak memory	205452 kb
Host	smart-cea5c42d-4d83-4307-9949-a825c129d6fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=758655194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.758655194
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2486355614
Short name	T619
Test name
Test status
Simulation time	138134216132 ps
CPU time	442.3 seconds
Started	Apr 21 12:26:45 PM PDT 24
Finished	Apr 21 12:34:08 PM PDT 24
Peak memory	211516 kb
Host	smart-42024269-f8c8-49cd-a62c-5cfe615aef25
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2486355614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2486355614
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2479309949
Short name	T734
Test name
Test status
Simulation time	3152282624 ps
CPU time	20.64 seconds
Started	Apr 21 12:26:37 PM PDT 24
Finished	Apr 21 12:26:58 PM PDT 24
Peak memory	203316 kb
Host	smart-8759a043-0a92-4c03-80fd-d0e68439881c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2479309949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2479309949
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.1480419294
Short name	T889
Test name
Test status
Simulation time	452925727 ps
CPU time	4.44 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:26:53 PM PDT 24
Peak memory	203272 kb
Host	smart-ddc02f43-b425-45ed-a793-57216de00b26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1480419294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1480419294
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.342745248
Short name	T396
Test name
Test status
Simulation time	515152179 ps
CPU time	8 seconds
Started	Apr 21 12:26:36 PM PDT 24
Finished	Apr 21 12:26:45 PM PDT 24
Peak memory	204376 kb
Host	smart-d94b0442-1c10-41ca-9807-36d35b1c4300
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=342745248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.342745248
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.790733215
Short name	T480
Test name
Test status
Simulation time	14070251269 ps
CPU time	40.58 seconds
Started	Apr 21 12:26:45 PM PDT 24
Finished	Apr 21 12:27:31 PM PDT 24
Peak memory	211548 kb
Host	smart-71bff4c3-f529-4e70-b2ea-76dfd397a27b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=790733215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.790733215
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3424406181
Short name	T205
Test name
Test status
Simulation time	6444407932 ps
CPU time	32.02 seconds
Started	Apr 21 12:26:37 PM PDT 24
Finished	Apr 21 12:27:10 PM PDT 24
Peak memory	211556 kb
Host	smart-0165fe34-7114-414b-8d52-3d6f87d26cc4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3424406181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3424406181
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3013547570
Short name	T834
Test name
Test status
Simulation time	856788279 ps
CPU time	24.63 seconds
Started	Apr 21 12:26:38 PM PDT 24
Finished	Apr 21 12:27:02 PM PDT 24
Peak memory	211540 kb
Host	smart-bea8212f-c5fe-40ed-9690-dd0bcbcecd50
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013547570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3013547570
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.3427873917
Short name	T534
Test name
Test status
Simulation time	76120586 ps
CPU time	6.06 seconds
Started	Apr 21 12:26:37 PM PDT 24
Finished	Apr 21 12:26:43 PM PDT 24
Peak memory	203276 kb
Host	smart-eb929acb-6f2d-47e4-892c-7808bfa3971e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3427873917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3427873917
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.3160195169
Short name	T659
Test name
Test status
Simulation time	159491033 ps
CPU time	3.33 seconds
Started	Apr 21 12:26:26 PM PDT 24
Finished	Apr 21 12:26:29 PM PDT 24
Peak memory	203348 kb
Host	smart-dc3ccabf-47f1-4355-bd6a-9bb72e910d4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3160195169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3160195169
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1437097606
Short name	T710
Test name
Test status
Simulation time	7683416336 ps
CPU time	30.55 seconds
Started	Apr 21 12:26:34 PM PDT 24
Finished	Apr 21 12:27:06 PM PDT 24
Peak memory	203300 kb
Host	smart-699af154-548e-4e35-a147-18a493b80526
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437097606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1437097606
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3803788461
Short name	T10
Test name
Test status
Simulation time	3029653680 ps
CPU time	22.46 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:27:14 PM PDT 24
Peak memory	203176 kb
Host	smart-597ff71a-cf32-45f7-baf3-203de735b66f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3803788461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3803788461
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1663621387
Short name	T278
Test name
Test status
Simulation time	26954550 ps
CPU time	2.03 seconds
Started	Apr 21 12:26:41 PM PDT 24
Finished	Apr 21 12:26:43 PM PDT 24
Peak memory	203320 kb
Host	smart-4f583cec-8c1a-4983-952a-043193633bb4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663621387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1663621387
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.3234894787
Short name	T866
Test name
Test status
Simulation time	4082205226 ps
CPU time	104.94 seconds
Started	Apr 21 12:26:47 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	211512 kb
Host	smart-047332ca-36f3-47cc-b05c-65d9dd369790
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3234894787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3234894787
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.465101575
Short name	T175
Test name
Test status
Simulation time	1759192679 ps
CPU time	131.13 seconds
Started	Apr 21 12:26:37 PM PDT 24
Finished	Apr 21 12:28:49 PM PDT 24
Peak memory	206472 kb
Host	smart-8c85b828-76ea-4831-b50c-a8f8c382f9fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465101575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.465101575
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3174169031
Short name	T457
Test name
Test status
Simulation time	49777735 ps
CPU time	32.47 seconds
Started	Apr 21 12:26:33 PM PDT 24
Finished	Apr 21 12:27:11 PM PDT 24
Peak memory	206384 kb
Host	smart-3681713a-80da-47c7-8deb-8297dbadb1f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3174169031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.3174169031
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1729226003
Short name	T758
Test name
Test status
Simulation time	31539525 ps
CPU time	3.4 seconds
Started	Apr 21 12:26:40 PM PDT 24
Finished	Apr 21 12:26:44 PM PDT 24
Peak memory	203540 kb
Host	smart-f38641f4-517e-4381-b126-79bc2109d3af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1729226003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1729226003
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3485585624
Short name	T7
Test name
Test status
Simulation time	42922245 ps
CPU time	2.27 seconds
Started	Apr 21 12:26:46 PM PDT 24
Finished	Apr 21 12:26:49 PM PDT 24
Peak memory	203348 kb
Host	smart-84766546-1da6-49ab-ac29-f7118dcda99f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3485585624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3485585624
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1668483430
Short name	T373
Test name
Test status
Simulation time	2337062566 ps
CPU time	33.82 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	204820 kb
Host	smart-a1f5621b-4f5e-4fa7-afcb-834c8699d8ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1668483430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1668483430
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3479183315
Short name	T513
Test name
Test status
Simulation time	46286793889 ps
CPU time	229.7 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:30:43 PM PDT 24
Peak memory	206172 kb
Host	smart-672b892f-c8aa-4f62-99ae-aff67ba19de4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3479183315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.3479183315
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3160467650
Short name	T752
Test name
Test status
Simulation time	153380743 ps
CPU time	18.66 seconds
Started	Apr 21 12:26:36 PM PDT 24
Finished	Apr 21 12:26:55 PM PDT 24
Peak memory	203312 kb
Host	smart-00ebecd8-bb1b-405b-9b8b-83f70edc9704
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3160467650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3160467650
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.3265270382
Short name	T722
Test name
Test status
Simulation time	688278592 ps
CPU time	21.27 seconds
Started	Apr 21 12:26:49 PM PDT 24
Finished	Apr 21 12:27:10 PM PDT 24
Peak memory	203268 kb
Host	smart-edac61fb-6d15-4380-9558-3bcb1f8c8070
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3265270382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3265270382
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.2841540183
Short name	T605
Test name
Test status
Simulation time	1487226765 ps
CPU time	28.7 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:27:28 PM PDT 24
Peak memory	211444 kb
Host	smart-3297980e-69ff-448c-b02b-08ecd312c73e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2841540183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2841540183
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2966846283
Short name	T363
Test name
Test status
Simulation time	1497815909 ps
CPU time	9.95 seconds
Started	Apr 21 12:26:42 PM PDT 24
Finished	Apr 21 12:26:53 PM PDT 24
Peak memory	203252 kb
Host	smart-c272c341-f8bd-467a-a55a-877acd91cb8b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966846283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2966846283
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.964563817
Short name	T720
Test name
Test status
Simulation time	90429391160 ps
CPU time	260.8 seconds
Started	Apr 21 12:27:10 PM PDT 24
Finished	Apr 21 12:31:31 PM PDT 24
Peak memory	211584 kb
Host	smart-0b58bc3a-9a47-4b1b-898f-18b3766161e9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=964563817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.964563817
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.999970527
Short name	T750
Test name
Test status
Simulation time	258828909 ps
CPU time	23.61 seconds
Started	Apr 21 12:27:02 PM PDT 24
Finished	Apr 21 12:27:31 PM PDT 24
Peak memory	204668 kb
Host	smart-595f3562-0730-4e06-89fd-1adae42328cf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999970527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.999970527
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.235402710
Short name	T221
Test name
Test status
Simulation time	1729018520 ps
CPU time	10.53 seconds
Started	Apr 21 12:26:49 PM PDT 24
Finished	Apr 21 12:27:00 PM PDT 24
Peak memory	203300 kb
Host	smart-d9aa53ef-d76d-440c-9a58-8469dd974f57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=235402710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.235402710
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.1337043414
Short name	T805
Test name
Test status
Simulation time	172639220 ps
CPU time	3.66 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:27:03 PM PDT 24
Peak memory	203332 kb
Host	smart-62aeb7b4-358d-4501-832b-bc5be25c835c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1337043414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1337043414
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3782427883
Short name	T341
Test name
Test status
Simulation time	9156650617 ps
CPU time	34.06 seconds
Started	Apr 21 12:26:58 PM PDT 24
Finished	Apr 21 12:27:33 PM PDT 24
Peak memory	203236 kb
Host	smart-7523438b-665e-449b-9f3b-aa410d872bc9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782427883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3782427883
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.4288647303
Short name	T571
Test name
Test status
Simulation time	8559753431 ps
CPU time	26.75 seconds
Started	Apr 21 12:26:50 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203408 kb
Host	smart-dcbe2dcf-6fef-4676-8f0d-45938e36ed23
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4288647303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.4288647303
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3829968294
Short name	T350
Test name
Test status
Simulation time	37217307 ps
CPU time	2.42 seconds
Started	Apr 21 12:26:56 PM PDT 24
Finished	Apr 21 12:26:59 PM PDT 24
Peak memory	203344 kb
Host	smart-a868f1fc-5baf-429d-8ca6-69e554b3a4b2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829968294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3829968294
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.1688398259
Short name	T183
Test name
Test status
Simulation time	8083517305 ps
CPU time	113.67 seconds
Started	Apr 21 12:27:02 PM PDT 24
Finished	Apr 21 12:28:56 PM PDT 24
Peak memory	211492 kb
Host	smart-110810d2-02a2-4e18-b5ea-97593eb6f8fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1688398259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1688398259
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1557671425
Short name	T854
Test name
Test status
Simulation time	10326524707 ps
CPU time	100.2 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	205312 kb
Host	smart-e6d5ed3d-d08c-45af-9876-4a373ec8ba5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1557671425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1557671425
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.939982718
Short name	T719
Test name
Test status
Simulation time	7720779 ps
CPU time	6.76 seconds
Started	Apr 21 12:26:44 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	203436 kb
Host	smart-552b41ef-c71b-4083-bf50-30a71dce0884
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=939982718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand _reset.939982718
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1282972618
Short name	T397
Test name
Test status
Simulation time	117612415 ps
CPU time	68.01 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:28:20 PM PDT 24
Peak memory	207092 kb
Host	smart-8b2848eb-f297-41e2-8068-dfef604dcab4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1282972618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1282972618
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2352393292
Short name	T870
Test name
Test status
Simulation time	31350273 ps
CPU time	4.18 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:27:12 PM PDT 24
Peak memory	211524 kb
Host	smart-6aefc78b-5e57-4f0f-9956-7f944cecfa80
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2352393292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2352393292
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.579852079
Short name	T89
Test name
Test status
Simulation time	1657246417 ps
CPU time	67.87 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:28:25 PM PDT 24
Peak memory	206636 kb
Host	smart-2cf5a885-b668-4a38-a18a-ff9febb2d996
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=579852079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.579852079
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4250334498
Short name	T339
Test name
Test status
Simulation time	202240858 ps
CPU time	6.47 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:27:23 PM PDT 24
Peak memory	203364 kb
Host	smart-e512efc1-3181-4b43-a0ea-1b42e92c1c17
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4250334498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4250334498
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.2940439464
Short name	T795
Test name
Test status
Simulation time	1144896087 ps
CPU time	10.42 seconds
Started	Apr 21 12:27:13 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	203356 kb
Host	smart-bb79dfcf-9c3c-466a-a8f5-1fc8efba1f92
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2940439464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2940439464
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.3853709306
Short name	T848
Test name
Test status
Simulation time	987847519 ps
CPU time	26.21 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:27:41 PM PDT 24
Peak memory	204292 kb
Host	smart-f19d74d1-c903-4cd1-a447-b6a6986c2e59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3853709306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3853709306
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1853691101
Short name	T718
Test name
Test status
Simulation time	29504355232 ps
CPU time	39.18 seconds
Started	Apr 21 12:26:46 PM PDT 24
Finished	Apr 21 12:27:26 PM PDT 24
Peak memory	203460 kb
Host	smart-1ccec4ae-c8c3-429e-b35b-d03397423e9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853691101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1853691101
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.4143140034
Short name	T880
Test name
Test status
Simulation time	4564045124 ps
CPU time	31.56 seconds
Started	Apr 21 12:27:06 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	211464 kb
Host	smart-d97ee4f6-1978-45fc-a559-8d3416735cd9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4143140034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4143140034
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1135312139
Short name	T657
Test name
Test status
Simulation time	533103825 ps
CPU time	22.62 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:27:40 PM PDT 24
Peak memory	204884 kb
Host	smart-0b85509e-0cb8-4264-b48a-123f284920b0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135312139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1135312139
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.3507157815
Short name	T628
Test name
Test status
Simulation time	132220592 ps
CPU time	10.2 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:27:04 PM PDT 24
Peak memory	203384 kb
Host	smart-cd8d7aed-a15c-4550-8dd1-7e88226f9774
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507157815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3507157815
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.1084877591
Short name	T736
Test name
Test status
Simulation time	443907286 ps
CPU time	3.22 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:27:21 PM PDT 24
Peak memory	203308 kb
Host	smart-e5708c63-04af-49a2-a9fb-37e5ef829430
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1084877591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1084877591
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2808141172
Short name	T716
Test name
Test status
Simulation time	9382985360 ps
CPU time	32.35 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	203352 kb
Host	smart-3c6acdec-f6ad-4906-aa3d-65d021ce002e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808141172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2808141172
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3916110346
Short name	T728
Test name
Test status
Simulation time	4278575707 ps
CPU time	32.37 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:27:48 PM PDT 24
Peak memory	203360 kb
Host	smart-92b76e67-7ac3-4b46-b549-6f9ba8b2817b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3916110346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3916110346
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3103772133
Short name	T466
Test name
Test status
Simulation time	38626903 ps
CPU time	2.02 seconds
Started	Apr 21 12:27:04 PM PDT 24
Finished	Apr 21 12:27:07 PM PDT 24
Peak memory	203220 kb
Host	smart-8fe87bf2-da29-416e-92c5-6fcfc29641b5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103772133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3103772133
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.2477883377
Short name	T231
Test name
Test status
Simulation time	5224148335 ps
CPU time	105.87 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:29:05 PM PDT 24
Peak memory	207308 kb
Host	smart-4d41fbca-af7b-49fe-b909-666b546fb173
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2477883377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2477883377
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.284786477
Short name	T617
Test name
Test status
Simulation time	14301922855 ps
CPU time	197 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:30:30 PM PDT 24
Peak memory	207064 kb
Host	smart-8686dfd3-a86a-4cc7-b249-6891d2a63df2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=284786477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.284786477
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.501416342
Short name	T212
Test name
Test status
Simulation time	102029082 ps
CPU time	75.06 seconds
Started	Apr 21 12:26:55 PM PDT 24
Finished	Apr 21 12:28:11 PM PDT 24
Peak memory	208172 kb
Host	smart-fe448be9-1c59-4d0c-b888-7582f9aae4b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=501416342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.501416342
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2853086908
Short name	T245
Test name
Test status
Simulation time	136061244 ps
CPU time	44.91 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:28:01 PM PDT 24
Peak memory	206432 kb
Host	smart-71e0141c-5e2f-47b3-8310-314648e1f551
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2853086908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.2853086908
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2445062085
Short name	T195
Test name
Test status
Simulation time	55018664 ps
CPU time	7.33 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:20 PM PDT 24
Peak memory	204880 kb
Host	smart-f13e9cba-dbab-4622-bbd4-b55c51b611fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2445062085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2445062085
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.4134726575
Short name	T818
Test name
Test status
Simulation time	108175513 ps
CPU time	11.5 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:27:21 PM PDT 24
Peak memory	205104 kb
Host	smart-c4637b04-266b-4029-b511-36c59a979d62
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134726575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.4134726575
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2104166489
Short name	T88
Test name
Test status
Simulation time	75000942511 ps
CPU time	436.59 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:34:26 PM PDT 24
Peak memory	211604 kb
Host	smart-38ca0a1c-7085-4d56-bc74-b4a2d94a05bb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2104166489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2104166489
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.561811837
Short name	T197
Test name
Test status
Simulation time	115487180 ps
CPU time	10.65 seconds
Started	Apr 21 12:27:06 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203352 kb
Host	smart-3641467c-b57d-4d9e-be02-3c1d56e055ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561811837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.561811837
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.1069074252
Short name	T370
Test name
Test status
Simulation time	1435110382 ps
CPU time	26.91 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	203356 kb
Host	smart-22be56c7-1686-4774-8d37-85931a015241
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1069074252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1069074252
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.2749542909
Short name	T20
Test name
Test status
Simulation time	176260060 ps
CPU time	18.21 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:27:27 PM PDT 24
Peak memory	211388 kb
Host	smart-07cff59f-930a-4bbd-acbb-1dcc302081e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2749542909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2749542909
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.484486905
Short name	T200
Test name
Test status
Simulation time	42508530822 ps
CPU time	113.77 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:29:02 PM PDT 24
Peak memory	211580 kb
Host	smart-866be98a-b67e-4c55-a48f-4ea6c059b9ef
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=484486905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.484486905
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2003248160
Short name	T658
Test name
Test status
Simulation time	16905213394 ps
CPU time	125.46 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:28:59 PM PDT 24
Peak memory	211580 kb
Host	smart-b7a83a74-0e59-4939-abe2-93f975c3ee1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2003248160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2003248160
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3236630227
Short name	T344
Test name
Test status
Simulation time	48490275 ps
CPU time	2.2 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:15 PM PDT 24
Peak memory	203332 kb
Host	smart-ea7596f3-ba45-4cd5-8162-d7b5b22d9f79
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236630227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3236630227
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.3675741578
Short name	T664
Test name
Test status
Simulation time	2679864208 ps
CPU time	26.31 seconds
Started	Apr 21 12:27:03 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	211488 kb
Host	smart-5d7f7a61-67ba-4552-8b21-e532c1cb2fcf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3675741578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3675741578
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.396180449
Short name	T530
Test name
Test status
Simulation time	109826791 ps
CPU time	3.16 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:27:04 PM PDT 24
Peak memory	203284 kb
Host	smart-b92491a8-2cef-4fcc-b845-0a60114d199d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=396180449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.396180449
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.4227503913
Short name	T149
Test name
Test status
Simulation time	21599913096 ps
CPU time	34.4 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203332 kb
Host	smart-bef6e567-6da5-4aa8-accf-b88cbe59e612
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227503913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4227503913
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1807473564
Short name	T54
Test name
Test status
Simulation time	6717661424 ps
CPU time	24.17 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	203288 kb
Host	smart-63e41a31-2435-4eb8-91c1-c14af4ba4cd6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1807473564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1807473564
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.732095705
Short name	T53
Test name
Test status
Simulation time	79406191 ps
CPU time	2.23 seconds
Started	Apr 21 12:27:06 PM PDT 24
Finished	Apr 21 12:27:09 PM PDT 24
Peak memory	203324 kb
Host	smart-96eb0d11-6549-485e-8b31-a613469bd73a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732095705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.732095705
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.1201713438
Short name	T375
Test name
Test status
Simulation time	6479100140 ps
CPU time	98.72 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:28:50 PM PDT 24
Peak memory	208304 kb
Host	smart-aefca1c6-170e-4476-9fb0-42c5f691487b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1201713438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1201713438
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.508116946
Short name	T356
Test name
Test status
Simulation time	2338629924 ps
CPU time	94.36 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:28:43 PM PDT 24
Peak memory	208556 kb
Host	smart-af09c947-b05f-4d00-93b3-e23f11719888
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=508116946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.508116946
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1220639933
Short name	T477
Test name
Test status
Simulation time	272277182 ps
CPU time	91.98 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:28:44 PM PDT 24
Peak memory	208156 kb
Host	smart-895276ca-020b-4427-92fd-e0623515a053
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1220639933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1220639933
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3854145592
Short name	T436
Test name
Test status
Simulation time	4585035942 ps
CPU time	285.59 seconds
Started	Apr 21 12:27:05 PM PDT 24
Finished	Apr 21 12:31:51 PM PDT 24
Peak memory	224104 kb
Host	smart-74d5b92b-455c-4194-829a-24c271df0acf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3854145592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3854145592
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1263490951
Short name	T388
Test name
Test status
Simulation time	186020614 ps
CPU time	9.79 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:27:19 PM PDT 24
Peak memory	211532 kb
Host	smart-6a02ca54-a8cd-4199-a8cf-6f859b6b494f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1263490951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1263490951
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1774920649
Short name	T821
Test name
Test status
Simulation time	691209432 ps
CPU time	30.76 seconds
Started	Apr 21 12:27:10 PM PDT 24
Finished	Apr 21 12:27:41 PM PDT 24
Peak memory	204740 kb
Host	smart-c856c5d3-21e0-4145-ba3c-f6543b06dba1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1774920649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1774920649
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1448378199
Short name	T106
Test name
Test status
Simulation time	128911986 ps
CPU time	16.47 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:27:26 PM PDT 24
Peak memory	203332 kb
Host	smart-ede43571-c6e9-42d5-aa9a-faaabbfef5ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1448378199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1448378199
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.2736436878
Short name	T391
Test name
Test status
Simulation time	127771324 ps
CPU time	16.1 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	203368 kb
Host	smart-90e6a721-9265-4a3a-9d71-a44e3cadf364
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2736436878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2736436878
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.1387426627
Short name	T655
Test name
Test status
Simulation time	194349856 ps
CPU time	18.19 seconds
Started	Apr 21 12:26:58 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	204764 kb
Host	smart-678e997f-c5f4-49bb-ae61-0334b5c85eb0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1387426627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1387426627
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2831072659
Short name	T634
Test name
Test status
Simulation time	10689739860 ps
CPU time	48.48 seconds
Started	Apr 21 12:27:10 PM PDT 24
Finished	Apr 21 12:27:59 PM PDT 24
Peak memory	211584 kb
Host	smart-fa086a2a-da74-40d1-84bb-015ddceab1a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831072659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2831072659
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1955466514
Short name	T561
Test name
Test status
Simulation time	28971205899 ps
CPU time	101.62 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:28:52 PM PDT 24
Peak memory	204776 kb
Host	smart-62ea76ee-20e2-42a5-bbc1-20c20dd5310d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1955466514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1955466514
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1785197141
Short name	T431
Test name
Test status
Simulation time	261564992 ps
CPU time	16.74 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	211520 kb
Host	smart-6ddf19af-fc7e-4a10-98e4-41754c1f82a1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785197141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1785197141
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.1418012036
Short name	T886
Test name
Test status
Simulation time	132723479 ps
CPU time	3.37 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:26:56 PM PDT 24
Peak memory	203232 kb
Host	smart-b8265da6-56bd-4e43-818c-9d0fe4cd180d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1418012036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1418012036
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.1488644010
Short name	T288
Test name
Test status
Simulation time	74619683 ps
CPU time	2.56 seconds
Started	Apr 21 12:26:55 PM PDT 24
Finished	Apr 21 12:26:59 PM PDT 24
Peak memory	203268 kb
Host	smart-21eeb8fc-7971-4fe7-8f93-2eb5750a8090
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1488644010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1488644010
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2880602454
Short name	T340
Test name
Test status
Simulation time	5440538025 ps
CPU time	29.08 seconds
Started	Apr 21 12:26:52 PM PDT 24
Finished	Apr 21 12:27:22 PM PDT 24
Peak memory	203240 kb
Host	smart-29283799-1dcb-45b4-86f7-d79fcacbc71b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880602454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2880602454
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2087413888
Short name	T706
Test name
Test status
Simulation time	8651960884 ps
CPU time	35.06 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	203288 kb
Host	smart-b887b3a9-ec9d-4f83-b127-9812670199f0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2087413888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2087413888
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.4059392858
Short name	T584
Test name
Test status
Simulation time	32693513 ps
CPU time	2.53 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203244 kb
Host	smart-232efe37-0588-4b43-ae61-9dfef16c8736
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059392858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.4059392858
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.3797498375
Short name	T201
Test name
Test status
Simulation time	1555333188 ps
CPU time	126.4 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:29:24 PM PDT 24
Peak memory	206008 kb
Host	smart-62621f6e-4218-4cd6-bdec-e361c17c4a26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3797498375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3797498375
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3751111039
Short name	T683
Test name
Test status
Simulation time	9841072294 ps
CPU time	162.45 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:30:02 PM PDT 24
Peak memory	208096 kb
Host	smart-58a9531f-06ef-4239-bf85-bfb8ab582b7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3751111039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3751111039
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.182530678
Short name	T801
Test name
Test status
Simulation time	5401978217 ps
CPU time	255.5 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:31:27 PM PDT 24
Peak memory	210320 kb
Host	smart-1bb58e9a-729d-4c65-8051-eff16f6c2209
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=182530678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand _reset.182530678
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.685532069
Short name	T279
Test name
Test status
Simulation time	674850432 ps
CPU time	24.85 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:27:36 PM PDT 24
Peak memory	205208 kb
Host	smart-3596de1c-c09a-4724-afc8-effd19aaae52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=685532069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.685532069
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1864826139
Short name	T857
Test name
Test status
Simulation time	249609336 ps
CPU time	29.22 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:41 PM PDT 24
Peak memory	211544 kb
Host	smart-48cc4d30-e491-4f03-a404-fdb771f91db8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1864826139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1864826139
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4193198367
Short name	T139
Test name
Test status
Simulation time	54678507484 ps
CPU time	537.94 seconds
Started	Apr 21 12:26:58 PM PDT 24
Finished	Apr 21 12:35:57 PM PDT 24
Peak memory	211440 kb
Host	smart-c7584e71-cde5-42fb-adb7-cd65fa5a51a6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4193198367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.4193198367
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2354726028
Short name	T148
Test name
Test status
Simulation time	1725257135 ps
CPU time	17.82 seconds
Started	Apr 21 12:26:58 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203336 kb
Host	smart-a5f826bc-3850-481d-842c-e3be59a0511a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2354726028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2354726028
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.1718161913
Short name	T256
Test name
Test status
Simulation time	602246621 ps
CPU time	21.31 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	203336 kb
Host	smart-44b2d007-e703-4ff6-b151-acb371cdc99b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1718161913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1718161913
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.2758017621
Short name	T797
Test name
Test status
Simulation time	175123299 ps
CPU time	21.24 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:27:12 PM PDT 24
Peak memory	204692 kb
Host	smart-894489f1-541e-4172-af9d-d7c35610202f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758017621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2758017621
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2571045653
Short name	T216
Test name
Test status
Simulation time	97451959075 ps
CPU time	143.31 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:29:33 PM PDT 24
Peak memory	204876 kb
Host	smart-db3abec5-9b41-466a-8dc7-92f93d70b751
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571045653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2571045653
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3163621935
Short name	T837
Test name
Test status
Simulation time	26490344516 ps
CPU time	186.48 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:30:23 PM PDT 24
Peak memory	211484 kb
Host	smart-706bdda3-3f32-4e6e-8c4b-6d878ad82ea6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3163621935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3163621935
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.405187637
Short name	T585
Test name
Test status
Simulation time	39812958 ps
CPU time	4.4 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:27:21 PM PDT 24
Peak memory	211504 kb
Host	smart-957d6e56-fea6-4377-b676-8bbb44e58bf3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405187637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.405187637
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.1734813693
Short name	T511
Test name
Test status
Simulation time	272683591 ps
CPU time	5.23 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203244 kb
Host	smart-2f6afc56-0fbc-42c1-ac0a-0b4bc94b5130
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1734813693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1734813693
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.372777521
Short name	T888
Test name
Test status
Simulation time	242041153 ps
CPU time	3.47 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:16 PM PDT 24
Peak memory	203232 kb
Host	smart-faa1fed0-29bd-4fa9-a377-888c1b727257
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=372777521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.372777521
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3400338771
Short name	T826
Test name
Test status
Simulation time	10441719999 ps
CPU time	25.11 seconds
Started	Apr 21 12:27:20 PM PDT 24
Finished	Apr 21 12:27:45 PM PDT 24
Peak memory	203280 kb
Host	smart-3fa3acbc-704f-4117-b0ec-8296c287c5d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400338771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3400338771
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2795954246
Short name	T382
Test name
Test status
Simulation time	3013497416 ps
CPU time	26.66 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:39 PM PDT 24
Peak memory	203392 kb
Host	smart-5f2f16f6-5ac3-4daf-8a74-1fcb7b32adb8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2795954246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2795954246
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2980888159
Short name	T405
Test name
Test status
Simulation time	41018796 ps
CPU time	2.04 seconds
Started	Apr 21 12:27:04 PM PDT 24
Finished	Apr 21 12:27:07 PM PDT 24
Peak memory	203348 kb
Host	smart-09a85d1c-d0d8-4b31-acf0-336ba523e22f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980888159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2980888159
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1110410992
Short name	T1
Test name
Test status
Simulation time	1677873104 ps
CPU time	24.19 seconds
Started	Apr 21 12:27:22 PM PDT 24
Finished	Apr 21 12:27:46 PM PDT 24
Peak memory	204512 kb
Host	smart-13fac1c7-1a8b-4e55-875e-ee49442fb3aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1110410992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1110410992
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2264899630
Short name	T408
Test name
Test status
Simulation time	360676742 ps
CPU time	121.99 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:29:10 PM PDT 24
Peak memory	208532 kb
Host	smart-257da1e9-d1e0-4eae-8711-35a18a250f79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2264899630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.2264899630
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.134247229
Short name	T860
Test name
Test status
Simulation time	12690644 ps
CPU time	11.13 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	204088 kb
Host	smart-48028bd3-bc50-4dae-b962-aa0c23d69836
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=134247229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.134247229
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2280493030
Short name	T670
Test name
Test status
Simulation time	504100472 ps
CPU time	18.41 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	211444 kb
Host	smart-73644cd6-2997-49b3-8e1d-5a8401853099
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2280493030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2280493030
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1755471541
Short name	T687
Test name
Test status
Simulation time	1029423791 ps
CPU time	27.88 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:47 PM PDT 24
Peak memory	204884 kb
Host	smart-c9bd6cce-5012-4ebf-8ce7-172b72658460
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1755471541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1755471541
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1181676279
Short name	T296
Test name
Test status
Simulation time	62880630037 ps
CPU time	235.62 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:31:20 PM PDT 24
Peak memory	211604 kb
Host	smart-a1ce88d3-8dc0-4796-a59f-cc447a02982c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1181676279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1181676279
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.4158097023
Short name	T372
Test name
Test status
Simulation time	81188725 ps
CPU time	6.86 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:27:21 PM PDT 24
Peak memory	203208 kb
Host	smart-3b459152-f262-4e88-a918-eecf986049b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4158097023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4158097023
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.4197055713
Short name	T690
Test name
Test status
Simulation time	293831006 ps
CPU time	18.01 seconds
Started	Apr 21 12:27:03 PM PDT 24
Finished	Apr 21 12:27:22 PM PDT 24
Peak memory	203312 kb
Host	smart-e22f5d44-0ad2-43c5-a8c9-af8c161e063a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4197055713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4197055713
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.2980884416
Short name	T208
Test name
Test status
Simulation time	341296997 ps
CPU time	18.25 seconds
Started	Apr 21 12:27:05 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	204636 kb
Host	smart-41f967a3-f069-41c0-889b-399ce9d026c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2980884416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2980884416
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3385593603
Short name	T276
Test name
Test status
Simulation time	109254805758 ps
CPU time	186.37 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:30:14 PM PDT 24
Peak memory	211532 kb
Host	smart-44719cb5-301f-4b0c-890f-2548145835a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385593603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3385593603
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1827733729
Short name	T802
Test name
Test status
Simulation time	141830218160 ps
CPU time	355.22 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:32:55 PM PDT 24
Peak memory	211484 kb
Host	smart-7ee2d585-855b-4938-9301-df8612050f73
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1827733729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1827733729
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.528363952
Short name	T326
Test name
Test status
Simulation time	333311425 ps
CPU time	21.82 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	204780 kb
Host	smart-1cae8416-7853-4b20-a15d-d12dd602715c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528363952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.528363952
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.1915840905
Short name	T564
Test name
Test status
Simulation time	88060586 ps
CPU time	5.86 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:27:14 PM PDT 24
Peak memory	203416 kb
Host	smart-7daf3774-9e83-49d1-8882-93248e6b5f5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1915840905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1915840905
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.3732050662
Short name	T196
Test name
Test status
Simulation time	171887541 ps
CPU time	3.07 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:27:26 PM PDT 24
Peak memory	203252 kb
Host	smart-c7e09afb-6b6c-480c-93c4-59f55aed398d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3732050662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3732050662
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.4264348686
Short name	T677
Test name
Test status
Simulation time	10216528327 ps
CPU time	29.74 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:49 PM PDT 24
Peak memory	203384 kb
Host	smart-b9095ca2-998e-47c9-a684-1e3c21145f46
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264348686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.4264348686
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1428013836
Short name	T768
Test name
Test status
Simulation time	9552600691 ps
CPU time	30.1 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:27:49 PM PDT 24
Peak memory	203304 kb
Host	smart-c80566a5-8a48-45ba-a351-b93165503f93
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1428013836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1428013836
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2236797523
Short name	T342
Test name
Test status
Simulation time	25835212 ps
CPU time	2.21 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:27:13 PM PDT 24
Peak memory	203196 kb
Host	smart-59e8d91f-0971-4ca9-bc96-51ce6aca5150
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236797523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2236797523
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.3109609841
Short name	T224
Test name
Test status
Simulation time	10751355932 ps
CPU time	113.55 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:29:08 PM PDT 24
Peak memory	207328 kb
Host	smart-4236003c-acb4-4b27-bf8f-9decda60a904
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109609841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3109609841
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1010653971
Short name	T351
Test name
Test status
Simulation time	7496896805 ps
CPU time	94.94 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:28:58 PM PDT 24
Peak memory	207556 kb
Host	smart-de0bbac0-96a3-4ae2-b40c-380346641d32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1010653971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1010653971
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3399244169
Short name	T202
Test name
Test status
Simulation time	12861457912 ps
CPU time	326.69 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:32:39 PM PDT 24
Peak memory	209888 kb
Host	smart-b67773aa-e2d4-49b9-a10d-0a5bea493832
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3399244169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3399244169
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.902749418
Short name	T679
Test name
Test status
Simulation time	318919584 ps
CPU time	110.94 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:29:07 PM PDT 24
Peak memory	209648 kb
Host	smart-2296b2a4-4f18-4f93-a93d-963d76c41498
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=902749418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res et_error.902749418
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.2340906672
Short name	T745
Test name
Test status
Simulation time	1447729450 ps
CPU time	24.05 seconds
Started	Apr 21 12:27:05 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	211536 kb
Host	smart-02b382e5-7974-4eda-a8d5-b726f07a2397
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2340906672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2340906672
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3392867413
Short name	T684
Test name
Test status
Simulation time	1370121967 ps
CPU time	46.13 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:27:58 PM PDT 24
Peak memory	211532 kb
Host	smart-fbb4e84e-b34a-460c-92ae-89552c99d1a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3392867413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3392867413
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1239271464
Short name	T137
Test name
Test status
Simulation time	42127555382 ps
CPU time	231.18 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:31:00 PM PDT 24
Peak memory	205800 kb
Host	smart-580460c6-df57-4c43-b568-5f3b8536890e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1239271464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.1239271464
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2876598716
Short name	T542
Test name
Test status
Simulation time	248582171 ps
CPU time	5.13 seconds
Started	Apr 21 12:27:20 PM PDT 24
Finished	Apr 21 12:27:26 PM PDT 24
Peak memory	203344 kb
Host	smart-5fefb8a5-803b-4b71-bf7a-2437a86f6207
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2876598716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2876598716
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.4117874242
Short name	T829
Test name
Test status
Simulation time	1082851198 ps
CPU time	23.75 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:36 PM PDT 24
Peak memory	203212 kb
Host	smart-ad7d49f5-2a47-4f2d-9b78-4f52ec4a385b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4117874242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.4117874242
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.2729664179
Short name	T138
Test name
Test status
Simulation time	237112071 ps
CPU time	18.89 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:27:37 PM PDT 24
Peak memory	204604 kb
Host	smart-a91f87da-1e77-424b-99c1-5c13a30f91ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2729664179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2729664179
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1085906159
Short name	T507
Test name
Test status
Simulation time	3424044156 ps
CPU time	17.92 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:27:36 PM PDT 24
Peak memory	203408 kb
Host	smart-97a9d13c-adbc-455d-8e35-fc36909d70d9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085906159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1085906159
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2298437069
Short name	T434
Test name
Test status
Simulation time	15237372742 ps
CPU time	82.4 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:28:39 PM PDT 24
Peak memory	211604 kb
Host	smart-6829085e-a123-48a8-b07f-32c082e34a6b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2298437069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2298437069
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2089943739
Short name	T445
Test name
Test status
Simulation time	168885913 ps
CPU time	22 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	204464 kb
Host	smart-42832c8d-e9e1-4524-9af9-5a8fa347c9c1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089943739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2089943739
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.4138523171
Short name	T223
Test name
Test status
Simulation time	1826145286 ps
CPU time	24.68 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	203376 kb
Host	smart-29f66db1-6924-427a-93f9-2ec26e58ca46
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4138523171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4138523171
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.359573912
Short name	T394
Test name
Test status
Simulation time	134232499 ps
CPU time	3.03 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:15 PM PDT 24
Peak memory	203236 kb
Host	smart-e50dd49d-6f18-49c3-88e6-d37f0730db19
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=359573912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.359573912
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3253738264
Short name	T481
Test name
Test status
Simulation time	17808644205 ps
CPU time	47.24 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:28:00 PM PDT 24
Peak memory	203300 kb
Host	smart-e5e6a9be-90d8-49dd-95d1-73c5a6161e65
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253738264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3253738264
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2909479919
Short name	T703
Test name
Test status
Simulation time	3280542597 ps
CPU time	19.52 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	203292 kb
Host	smart-b9deec74-db2d-4dd7-b8ce-84915040284f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2909479919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2909479919
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2376790982
Short name	T762
Test name
Test status
Simulation time	119387381 ps
CPU time	2.4 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:27:12 PM PDT 24
Peak memory	203336 kb
Host	smart-a9b2f780-27fc-4276-b244-3655fa765974
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376790982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2376790982
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.3994891531
Short name	T266
Test name
Test status
Simulation time	100687586 ps
CPU time	9.54 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	205284 kb
Host	smart-e7efaf99-e99b-4556-9616-b25939c68f25
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3994891531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3994891531
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1346157662
Short name	T729
Test name
Test status
Simulation time	2848008555 ps
CPU time	74.52 seconds
Started	Apr 21 12:27:13 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	211552 kb
Host	smart-a9707a42-04c7-4627-aa67-d0e5b608ade3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1346157662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1346157662
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3938231918
Short name	T412
Test name
Test status
Simulation time	112008195 ps
CPU time	42.47 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	206784 kb
Host	smart-f276a674-0c82-4b2d-85c3-b981bd2a311d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3938231918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3938231918
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3497254897
Short name	T31
Test name
Test status
Simulation time	1721690515 ps
CPU time	177.4 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:30:21 PM PDT 24
Peak memory	210940 kb
Host	smart-1b39a95d-bf94-433c-b53c-f5d3b168f714
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3497254897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3497254897
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3474035642
Short name	T495
Test name
Test status
Simulation time	1100263660 ps
CPU time	26.95 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:46 PM PDT 24
Peak memory	204780 kb
Host	smart-866c6c19-1030-4ddb-9a46-ae189705aa3e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3474035642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3474035642
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3524613661
Short name	T264
Test name
Test status
Simulation time	304504166 ps
CPU time	23.07 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:43 PM PDT 24
Peak memory	204316 kb
Host	smart-c42a9dcd-abb3-4f95-bbf9-db5723665574
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524613661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3524613661
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.473995939
Short name	T226
Test name
Test status
Simulation time	30101976040 ps
CPU time	246.18 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:31:21 PM PDT 24
Peak memory	211484 kb
Host	smart-ff2d478d-480a-42d0-9e7a-9ece89182675
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=473995939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slo w_rsp.473995939
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2749742318
Short name	T770
Test name
Test status
Simulation time	653903320 ps
CPU time	21.89 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:47 PM PDT 24
Peak memory	203300 kb
Host	smart-62bf23b6-13eb-4d22-889e-63dbedd232c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2749742318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2749742318
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.3875784175
Short name	T36
Test name
Test status
Simulation time	715434501 ps
CPU time	22.01 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:27:40 PM PDT 24
Peak memory	203352 kb
Host	smart-bf3cfc28-aacb-4766-abd5-1696cae8a3db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3875784175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3875784175
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.1730321985
Short name	T839
Test name
Test status
Simulation time	720432273 ps
CPU time	14.81 seconds
Started	Apr 21 12:27:10 PM PDT 24
Finished	Apr 21 12:27:26 PM PDT 24
Peak memory	204364 kb
Host	smart-1ccfe5ab-71ec-416a-9227-6eb3574be8c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1730321985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1730321985
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.457955329
Short name	T695
Test name
Test status
Simulation time	42541440721 ps
CPU time	191.33 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:30:26 PM PDT 24
Peak memory	204588 kb
Host	smart-30c0e2b3-146a-46f2-9a04-6f721b88278b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=457955329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.457955329
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3186388635
Short name	T567
Test name
Test status
Simulation time	7224671090 ps
CPU time	37.3 seconds
Started	Apr 21 12:27:38 PM PDT 24
Finished	Apr 21 12:28:16 PM PDT 24
Peak memory	211548 kb
Host	smart-d38ec688-4571-457e-8e9f-84907d1cfede
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3186388635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3186388635
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1569790381
Short name	T169
Test name
Test status
Simulation time	99212873 ps
CPU time	7.75 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:27:16 PM PDT 24
Peak memory	211448 kb
Host	smart-f5476400-dee1-4d59-8ac8-3f2d54d96503
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569790381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1569790381
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.1795147823
Short name	T271
Test name
Test status
Simulation time	590002077 ps
CPU time	14.75 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	203284 kb
Host	smart-4acb9baa-f9a4-4427-b07d-7678f05759cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1795147823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1795147823
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.298960216
Short name	T272
Test name
Test status
Simulation time	175546161 ps
CPU time	3.63 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:27:15 PM PDT 24
Peak memory	203332 kb
Host	smart-e8567a0a-b275-4811-9771-0bf31a931a77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=298960216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.298960216
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1724324504
Short name	T549
Test name
Test status
Simulation time	6360670530 ps
CPU time	33.41 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:27:49 PM PDT 24
Peak memory	203344 kb
Host	smart-20572ee8-2bd6-4fe1-ac0c-c7f46da3af4b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724324504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1724324504
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.547028298
Short name	T49
Test name
Test status
Simulation time	2814005610 ps
CPU time	19.84 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	203340 kb
Host	smart-c05b2628-ea79-4c52-84fe-8d2a4430d89e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=547028298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.547028298
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1404559780
Short name	T595
Test name
Test status
Simulation time	43124942 ps
CPU time	2.11 seconds
Started	Apr 21 12:27:11 PM PDT 24
Finished	Apr 21 12:27:14 PM PDT 24
Peak memory	203232 kb
Host	smart-5332aeaa-2da3-4784-923b-acd05aea6cde
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404559780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1404559780
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.1382713561
Short name	T165
Test name
Test status
Simulation time	8086956857 ps
CPU time	103.42 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:29:03 PM PDT 24
Peak memory	207232 kb
Host	smart-988d3036-039b-448d-8fec-f0da49a801a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1382713561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1382713561
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2261525499
Short name	T892
Test name
Test status
Simulation time	7088814910 ps
CPU time	165.46 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:30:16 PM PDT 24
Peak memory	211600 kb
Host	smart-c3303bf1-2934-48b8-bff8-87734c0992ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261525499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2261525499
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.760195855
Short name	T830
Test name
Test status
Simulation time	824094283 ps
CPU time	315.98 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:32:42 PM PDT 24
Peak memory	210560 kb
Host	smart-40b0e4c2-d412-4d8f-a6d0-f32b15afb11b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=760195855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand _reset.760195855
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2032401973
Short name	T78
Test name
Test status
Simulation time	566212003 ps
CPU time	59.09 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	206008 kb
Host	smart-2f5ea6ac-88a6-4860-a6c6-f1002329b3c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2032401973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.2032401973
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3952032293
Short name	T426
Test name
Test status
Simulation time	75692055 ps
CPU time	6.47 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:31 PM PDT 24
Peak memory	204832 kb
Host	smart-b863f6ef-2244-4f23-b575-411151ced6e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3952032293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3952032293
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2159056617
Short name	T681
Test name
Test status
Simulation time	408769507 ps
CPU time	25.56 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:58 PM PDT 24
Peak memory	211424 kb
Host	smart-5b0909b1-2717-499f-936c-0e3e8a4d0af5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2159056617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2159056617
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2419518259
Short name	T486
Test name
Test status
Simulation time	161857509 ps
CPU time	5.94 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:27:40 PM PDT 24
Peak memory	203252 kb
Host	smart-fd289e7c-7102-41a8-9fd9-05ac778c4cce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419518259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2419518259
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.1970377757
Short name	T380
Test name
Test status
Simulation time	162305504 ps
CPU time	12.3 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	203324 kb
Host	smart-9af10ef8-dbba-4399-888d-c6f4ebd37c77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1970377757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1970377757
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.312968940
Short name	T613
Test name
Test status
Simulation time	100967958 ps
CPU time	11.54 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	211396 kb
Host	smart-0a89e4d4-840c-42e7-a034-4842d691f79a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=312968940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.312968940
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.528047759
Short name	T110
Test name
Test status
Simulation time	11918305449 ps
CPU time	43.13 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:28:10 PM PDT 24
Peak memory	211480 kb
Host	smart-26bf43fe-8439-459e-909e-9986a61ed545
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=528047759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.528047759
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3373965507
Short name	T390
Test name
Test status
Simulation time	7893638690 ps
CPU time	14.04 seconds
Started	Apr 21 12:27:20 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203352 kb
Host	smart-5d6bcce0-fd15-4c73-a4ec-3d72e0d76d27
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3373965507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3373965507
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2494658410
Short name	T842
Test name
Test status
Simulation time	121358260 ps
CPU time	8.42 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:27:27 PM PDT 24
Peak memory	204484 kb
Host	smart-31b292ad-8f70-45f5-8b5b-37f8755e1b16
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494658410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2494658410
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.2080229055
Short name	T850
Test name
Test status
Simulation time	1125302850 ps
CPU time	19.12 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:39 PM PDT 24
Peak memory	203368 kb
Host	smart-8472251d-8554-4bea-b18f-7335ca1baf01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2080229055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2080229055
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.1650718776
Short name	T855
Test name
Test status
Simulation time	31148209 ps
CPU time	2.19 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:27:20 PM PDT 24
Peak memory	203288 kb
Host	smart-63595cb3-c8eb-4fba-9dd2-8721d08da9ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1650718776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1650718776
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4087570860
Short name	T893
Test name
Test status
Simulation time	11689523513 ps
CPU time	35.24 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:55 PM PDT 24
Peak memory	203316 kb
Host	smart-6e6e7ca1-9cd2-47f6-8e13-18aa9fa479f4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087570860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4087570860
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.896118822
Short name	T504
Test name
Test status
Simulation time	3050287232 ps
CPU time	24.17 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:27:48 PM PDT 24
Peak memory	203408 kb
Host	smart-7ef57841-2b22-401f-980d-ce6a9e34610c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=896118822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.896118822
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3401373317
Short name	T528
Test name
Test status
Simulation time	31030823 ps
CPU time	2.18 seconds
Started	Apr 21 12:27:13 PM PDT 24
Finished	Apr 21 12:27:15 PM PDT 24
Peak memory	203224 kb
Host	smart-8efc44a8-50fa-45a6-a3df-88a06b1b4ab9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401373317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3401373317
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.2356761743
Short name	T253
Test name
Test status
Simulation time	737032875 ps
CPU time	29.96 seconds
Started	Apr 21 12:27:13 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	205428 kb
Host	smart-d39b1646-f377-443a-a394-3fe651a837c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2356761743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2356761743
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2145817812
Short name	T355
Test name
Test status
Simulation time	1638022668 ps
CPU time	82.22 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:28:41 PM PDT 24
Peak memory	205968 kb
Host	smart-8a15cc60-4ca4-420b-b4ad-4b867e04aa48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2145817812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2145817812
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2184246285
Short name	T727
Test name
Test status
Simulation time	1643488224 ps
CPU time	353.29 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:33:13 PM PDT 24
Peak memory	211440 kb
Host	smart-a0ae7aeb-e12b-4ef1-9798-fa357729b21c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2184246285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.2184246285
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.502863720
Short name	T491
Test name
Test status
Simulation time	883599562 ps
CPU time	184.02 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:30:29 PM PDT 24
Peak memory	219716 kb
Host	smart-072b6c7b-8036-4b32-a11b-7000f7423457
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=502863720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res et_error.502863720
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.341690326
Short name	T732
Test name
Test status
Simulation time	850374160 ps
CPU time	11.37 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:28:07 PM PDT 24
Peak memory	211496 kb
Host	smart-655fe1f2-181c-4678-800c-c0ca7db8eb43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=341690326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.341690326
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2138271621
Short name	T624
Test name
Test status
Simulation time	2335820118 ps
CPU time	59.57 seconds
Started	Apr 21 12:27:17 PM PDT 24
Finished	Apr 21 12:28:17 PM PDT 24
Peak memory	206556 kb
Host	smart-752cc627-c838-47ed-8f0f-7f267cda5591
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2138271621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2138271621
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.109210101
Short name	T85
Test name
Test status
Simulation time	39167657830 ps
CPU time	369.89 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:33:25 PM PDT 24
Peak memory	211536 kb
Host	smart-ca85f2c1-1cb8-4775-a26b-a0acb53c8501
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=109210101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo w_rsp.109210101
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1660849057
Short name	T586
Test name
Test status
Simulation time	205789629 ps
CPU time	13.59 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	211420 kb
Host	smart-df8525c9-7b82-46ce-a63a-7f4b62ce1442
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1660849057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1660849057
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.2002934622
Short name	T552
Test name
Test status
Simulation time	220716099 ps
CPU time	20.49 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:27:36 PM PDT 24
Peak memory	203284 kb
Host	smart-88ce46c1-f3d3-4ba7-b6c8-fc9c9f4efe14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2002934622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2002934622
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.3097934766
Short name	T86
Test name
Test status
Simulation time	4017194406 ps
CPU time	33.86 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	204424 kb
Host	smart-77d5b0be-985f-4623-bf54-7bc43608b9cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3097934766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3097934766
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2029321093
Short name	T536
Test name
Test status
Simulation time	29871390867 ps
CPU time	169.66 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:30:13 PM PDT 24
Peak memory	211508 kb
Host	smart-46aca2b9-34d9-4100-8167-3f95876f3ded
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029321093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2029321093
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.58478025
Short name	T6
Test name
Test status
Simulation time	30406480180 ps
CPU time	247.15 seconds
Started	Apr 21 12:27:21 PM PDT 24
Finished	Apr 21 12:31:29 PM PDT 24
Peak memory	205496 kb
Host	smart-54e681c2-fc44-4f02-b29f-cf15e8b4a7ff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=58478025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.58478025
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2274482459
Short name	T461
Test name
Test status
Simulation time	789255288 ps
CPU time	18.56 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	211528 kb
Host	smart-d6b8ca6f-f57c-4416-a0f5-a453a2c0bc1d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274482459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2274482459
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.632803650
Short name	T460
Test name
Test status
Simulation time	2338398379 ps
CPU time	34.48 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:27:51 PM PDT 24
Peak memory	211532 kb
Host	smart-9e696c4f-7669-4da5-ac33-1ac659d972bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=632803650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.632803650
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.1910234523
Short name	T252
Test name
Test status
Simulation time	126539554 ps
CPU time	3.27 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	203348 kb
Host	smart-96ff20c2-5a29-4c18-a430-89628a909b2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1910234523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1910234523
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2237666563
Short name	T663
Test name
Test status
Simulation time	6601846467 ps
CPU time	25.05 seconds
Started	Apr 21 12:27:22 PM PDT 24
Finished	Apr 21 12:27:47 PM PDT 24
Peak memory	203308 kb
Host	smart-a95d59c0-aa83-44ba-b819-7b4d7f94c17c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237666563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2237666563
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3857069282
Short name	T157
Test name
Test status
Simulation time	4150866836 ps
CPU time	32.47 seconds
Started	Apr 21 12:27:20 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	203400 kb
Host	smart-6d125245-1560-4f0f-bc2e-f987a12fc470
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3857069282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3857069282
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3993588557
Short name	T847
Test name
Test status
Simulation time	79132289 ps
CPU time	2.43 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:27:21 PM PDT 24
Peak memory	203280 kb
Host	smart-cf155ff7-d1f1-4204-ab13-b02ff5831c7f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993588557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3993588557
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.3269879407
Short name	T119
Test name
Test status
Simulation time	3646286257 ps
CPU time	105.77 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:29:02 PM PDT 24
Peak memory	211488 kb
Host	smart-ddc0de3c-b808-47a2-999e-6b5f8e5b810f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3269879407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3269879407
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3426560476
Short name	T753
Test name
Test status
Simulation time	6658834643 ps
CPU time	139.22 seconds
Started	Apr 21 12:27:16 PM PDT 24
Finished	Apr 21 12:29:36 PM PDT 24
Peak memory	205456 kb
Host	smart-afcdb0e5-fa4c-4408-bc04-9f4ddb8ccac7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3426560476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3426560476
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.58460657
Short name	T601
Test name
Test status
Simulation time	1264821896 ps
CPU time	66.73 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:28:23 PM PDT 24
Peak memory	207264 kb
Host	smart-e8ff052b-52e8-4843-b6bb-c5aa6dfdd217
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=58460657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_ reset.58460657
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2501342103
Short name	T591
Test name
Test status
Simulation time	10162154085 ps
CPU time	509.46 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:35:54 PM PDT 24
Peak memory	219904 kb
Host	smart-4de9d643-993f-4357-900f-590fc88773a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2501342103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.2501342103
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3280056490
Short name	T675
Test name
Test status
Simulation time	953992630 ps
CPU time	10.63 seconds
Started	Apr 21 12:27:22 PM PDT 24
Finished	Apr 21 12:27:33 PM PDT 24
Peak memory	204732 kb
Host	smart-76f55c46-2d1d-4957-891c-0a27487f3d45
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3280056490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3280056490
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3923268208
Short name	T402
Test name
Test status
Simulation time	423937657 ps
CPU time	33.64 seconds
Started	Apr 21 12:27:03 PM PDT 24
Finished	Apr 21 12:27:37 PM PDT 24
Peak memory	211532 kb
Host	smart-1c05b108-1eb4-49d2-92fe-e96b2b9ab787
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3923268208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3923268208
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2172357461
Short name	T400
Test name
Test status
Simulation time	21531366337 ps
CPU time	58.97 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	211460 kb
Host	smart-e145ea63-467c-469f-a1a7-381e8c5f4bb9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2172357461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2172357461
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.3194528691
Short name	T471
Test name
Test status
Simulation time	473575413 ps
CPU time	13.13 seconds
Started	Apr 21 12:26:33 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	203564 kb
Host	smart-53c26ac8-709b-469c-aea3-a006dd11a0b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3194528691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3194528691
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.3288714388
Short name	T499
Test name
Test status
Simulation time	1013353455 ps
CPU time	25.01 seconds
Started	Apr 21 12:26:36 PM PDT 24
Finished	Apr 21 12:27:01 PM PDT 24
Peak memory	211488 kb
Host	smart-3179a554-cb69-445f-b3d1-78b16132fcc9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288714388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3288714388
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2189205998
Short name	T180
Test name
Test status
Simulation time	58324084040 ps
CPU time	114.4 seconds
Started	Apr 21 12:26:34 PM PDT 24
Finished	Apr 21 12:28:29 PM PDT 24
Peak memory	204632 kb
Host	smart-25204236-c1ca-40dd-9a7b-17f19be855cf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189205998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2189205998
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.387908935
Short name	T166
Test name
Test status
Simulation time	17852218764 ps
CPU time	97.65 seconds
Started	Apr 21 12:26:34 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	211584 kb
Host	smart-647e8365-2bb7-4d74-b758-98ba3059d401
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=387908935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.387908935
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1185850271
Short name	T451
Test name
Test status
Simulation time	643659366 ps
CPU time	14.79 seconds
Started	Apr 21 12:26:57 PM PDT 24
Finished	Apr 21 12:27:12 PM PDT 24
Peak memory	211456 kb
Host	smart-d81be1e2-bf32-4680-86a0-8ea3cc9b3d6f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185850271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1185850271
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.3539913730
Short name	T666
Test name
Test status
Simulation time	507839410 ps
CPU time	8.11 seconds
Started	Apr 21 12:26:44 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	203352 kb
Host	smart-46ec1eb4-669c-4655-8ebf-cd77f8cd68fe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3539913730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3539913730
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.1057682274
Short name	T615
Test name
Test status
Simulation time	113696292 ps
CPU time	3.09 seconds
Started	Apr 21 12:26:57 PM PDT 24
Finished	Apr 21 12:27:01 PM PDT 24
Peak memory	203248 kb
Host	smart-2d2d40d0-2b49-4964-8f77-cc8aebeb7de7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1057682274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1057682274
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3444554223
Short name	T824
Test name
Test status
Simulation time	9265949062 ps
CPU time	33.59 seconds
Started	Apr 21 12:26:42 PM PDT 24
Finished	Apr 21 12:27:16 PM PDT 24
Peak memory	203308 kb
Host	smart-7792e39e-3709-417d-86f4-592822a74ce9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444554223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3444554223
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.287678482
Short name	T319
Test name
Test status
Simulation time	9315218199 ps
CPU time	34.55 seconds
Started	Apr 21 12:27:04 PM PDT 24
Finished	Apr 21 12:27:40 PM PDT 24
Peak memory	203400 kb
Host	smart-3d26d40f-5a8d-4a26-bcef-a53c680cbfdc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=287678482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.287678482
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.4009665067
Short name	T506
Test name
Test status
Simulation time	61805952 ps
CPU time	2.28 seconds
Started	Apr 21 12:26:55 PM PDT 24
Finished	Apr 21 12:26:58 PM PDT 24
Peak memory	203092 kb
Host	smart-f3f1bf91-8a3b-45a8-8fd1-7087243783a9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009665067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.4009665067
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.2369203382
Short name	T577
Test name
Test status
Simulation time	882893839 ps
CPU time	24.94 seconds
Started	Apr 21 12:26:38 PM PDT 24
Finished	Apr 21 12:27:04 PM PDT 24
Peak memory	206160 kb
Host	smart-3a7619af-b93f-4b89-a63c-0712a922957e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2369203382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2369203382
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.4009237959
Short name	T612
Test name
Test status
Simulation time	1325239433 ps
CPU time	32.09 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:27:23 PM PDT 24
Peak memory	204976 kb
Host	smart-a205fe18-ed12-49c5-ad3c-a7231e214b52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4009237959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4009237959
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3389592208
Short name	T125
Test name
Test status
Simulation time	21101125307 ps
CPU time	445.48 seconds
Started	Apr 21 12:26:46 PM PDT 24
Finished	Apr 21 12:34:11 PM PDT 24
Peak memory	209660 kb
Host	smart-234dbab5-dbf6-455b-92d0-e8afbbba7278
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3389592208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3389592208
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2069670106
Short name	T596
Test name
Test status
Simulation time	4838528789 ps
CPU time	453.06 seconds
Started	Apr 21 12:26:47 PM PDT 24
Finished	Apr 21 12:34:21 PM PDT 24
Peak memory	227168 kb
Host	smart-c1ab5a6d-a047-4dfc-a6ff-d2bda7b7d22b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2069670106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.2069670106
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1950403988
Short name	T520
Test name
Test status
Simulation time	67851404 ps
CPU time	4.21 seconds
Started	Apr 21 12:26:45 PM PDT 24
Finished	Apr 21 12:26:49 PM PDT 24
Peak memory	204684 kb
Host	smart-5c877805-d706-4d21-afb7-72cc4061f245
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1950403988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1950403988
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1214961134
Short name	T73
Test name
Test status
Simulation time	606657514 ps
CPU time	41.37 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:28:06 PM PDT 24
Peak memory	205764 kb
Host	smart-6fcf97ec-d5c6-4715-a906-8058c23cee4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1214961134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1214961134
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.610638008
Short name	T665
Test name
Test status
Simulation time	142456199181 ps
CPU time	338.86 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:33:09 PM PDT 24
Peak memory	211484 kb
Host	smart-b57f986b-f6d7-43d5-a32d-944abb8bf3eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=610638008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.610638008
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3347963888
Short name	T255
Test name
Test status
Simulation time	60756584 ps
CPU time	8.47 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:41 PM PDT 24
Peak memory	203548 kb
Host	smart-468e3980-1181-4c24-a65f-ebd83a94d12c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347963888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3347963888
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.3553626930
Short name	T898
Test name
Test status
Simulation time	826102485 ps
CPU time	17.23 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	203264 kb
Host	smart-3097ed14-1a5f-4ad6-ac60-5aa3adf283f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3553626930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3553626930
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.46025992
Short name	T478
Test name
Test status
Simulation time	965188864 ps
CPU time	27.79 seconds
Started	Apr 21 12:27:15 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	204720 kb
Host	smart-7570f66e-5037-4c6c-88cb-a4f0726852cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=46025992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.46025992
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1157358559
Short name	T652
Test name
Test status
Simulation time	14927551828 ps
CPU time	81.6 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:28:54 PM PDT 24
Peak memory	204692 kb
Host	smart-6d102ee0-343c-4e2d-acec-840df7a82775
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157358559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1157358559
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1490650713
Short name	T859
Test name
Test status
Simulation time	8068858200 ps
CPU time	42.13 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	204436 kb
Host	smart-b6d21bd5-8a89-4069-836d-656714f6d36e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1490650713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1490650713
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.519864138
Short name	T704
Test name
Test status
Simulation time	449290283 ps
CPU time	11.67 seconds
Started	Apr 21 12:27:20 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	211432 kb
Host	smart-93e953b3-c640-49a8-80c1-bf8e1cbaece0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519864138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.519864138
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.3536587649
Short name	T352
Test name
Test status
Simulation time	500047167 ps
CPU time	10.48 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:39 PM PDT 24
Peak memory	203316 kb
Host	smart-27f62c7e-12bf-4408-ae07-efd06dd3958d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3536587649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3536587649
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.3321257134
Short name	T649
Test name
Test status
Simulation time	712258606 ps
CPU time	3.91 seconds
Started	Apr 21 12:27:22 PM PDT 24
Finished	Apr 21 12:27:27 PM PDT 24
Peak memory	203236 kb
Host	smart-b7233b18-d346-4958-8bc2-6468f750a703
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3321257134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3321257134
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3610509314
Short name	T95
Test name
Test status
Simulation time	6015411458 ps
CPU time	27.29 seconds
Started	Apr 21 12:27:14 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	203412 kb
Host	smart-2a759093-976d-46be-9b84-6e8c55e2cf0b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610509314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3610509314
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.8998191
Short name	T597
Test name
Test status
Simulation time	3145046988 ps
CPU time	26.03 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:46 PM PDT 24
Peak memory	203320 kb
Host	smart-ab31b05a-ede9-49f9-bcba-87510a045615
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=8998191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.8998191
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2304452379
Short name	T367
Test name
Test status
Simulation time	41292841 ps
CPU time	2.21 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:27:28 PM PDT 24
Peak memory	203224 kb
Host	smart-47d0316c-1ea1-453a-b031-10883ab52f33
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304452379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2304452379
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.2563275747
Short name	T761
Test name
Test status
Simulation time	1372858167 ps
CPU time	126.88 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:29:33 PM PDT 24
Peak memory	206048 kb
Host	smart-9c86bee3-9d05-4816-a929-a3d2e9a5067a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2563275747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2563275747
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.4280668248
Short name	T468
Test name
Test status
Simulation time	16818422848 ps
CPU time	280.87 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:32:34 PM PDT 24
Peak memory	207308 kb
Host	smart-eccd682b-775f-486f-970b-e23194529a96
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4280668248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.4280668248
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3175681182
Short name	T327
Test name
Test status
Simulation time	677944612 ps
CPU time	166.34 seconds
Started	Apr 21 12:27:38 PM PDT 24
Finished	Apr 21 12:30:26 PM PDT 24
Peak memory	208352 kb
Host	smart-cb00cb5f-3e6d-4619-99ca-cf1f7ddc54c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175681182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.3175681182
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1705328837
Short name	T482
Test name
Test status
Simulation time	44021637 ps
CPU time	16.5 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:27:45 PM PDT 24
Peak memory	205140 kb
Host	smart-3c1e2aa1-69e4-41ad-82bb-61f821db3a3e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1705328837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1705328837
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3306813750
Short name	T739
Test name
Test status
Simulation time	1119453814 ps
CPU time	31.35 seconds
Started	Apr 21 12:27:32 PM PDT 24
Finished	Apr 21 12:28:04 PM PDT 24
Peak memory	211552 kb
Host	smart-17e7d2cb-321e-4724-a877-a7a7bea1d29e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3306813750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3306813750
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3888824201
Short name	T90
Test name
Test status
Simulation time	1906370576 ps
CPU time	44.08 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:28:18 PM PDT 24
Peak memory	211460 kb
Host	smart-e50ac08e-8630-4da2-9919-c5d64d6aa89c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3888824201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3888824201
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1761859231
Short name	T145
Test name
Test status
Simulation time	215013249508 ps
CPU time	577.94 seconds
Started	Apr 21 12:27:22 PM PDT 24
Finished	Apr 21 12:37:00 PM PDT 24
Peak memory	206916 kb
Host	smart-1039f58c-20f6-461b-80b5-32f372e2faa9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1761859231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1761859231
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.684673605
Short name	T861
Test name
Test status
Simulation time	97516426 ps
CPU time	7.42 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	203696 kb
Host	smart-bb3d9b8a-a315-438f-b1c2-b9133b2bfa44
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=684673605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.684673605
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.239174487
Short name	T668
Test name
Test status
Simulation time	432743955 ps
CPU time	11.45 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:27:37 PM PDT 24
Peak memory	203376 kb
Host	smart-58d4eec6-ed56-4fde-8d43-1dcdc7acdd63
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=239174487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.239174487
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.2567497737
Short name	T463
Test name
Test status
Simulation time	1747472954 ps
CPU time	20.12 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	211436 kb
Host	smart-04f81567-42e2-4aaf-9dcc-eda18f8fbca5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2567497737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2567497737
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2770055999
Short name	T289
Test name
Test status
Simulation time	5180603371 ps
CPU time	15.52 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	203412 kb
Host	smart-f9f98248-2cce-4ea7-8809-82e0323b61bf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770055999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2770055999
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2360224974
Short name	T55
Test name
Test status
Simulation time	31652735887 ps
CPU time	105.56 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:29:30 PM PDT 24
Peak memory	204820 kb
Host	smart-40f4516a-0eec-4148-8ca0-022a29d725ce
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2360224974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2360224974
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2618946090
Short name	T767
Test name
Test status
Simulation time	105838939 ps
CPU time	7.6 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:40 PM PDT 24
Peak memory	204560 kb
Host	smart-dd70f206-8339-4437-8f4b-b2204dfe1e79
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618946090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2618946090
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.591168812
Short name	T653
Test name
Test status
Simulation time	100583520 ps
CPU time	6.38 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	203568 kb
Host	smart-cb1543e0-d218-4358-a9c8-60883b3700ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=591168812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.591168812
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.973759541
Short name	T836
Test name
Test status
Simulation time	177128857 ps
CPU time	3.13 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:28 PM PDT 24
Peak memory	203340 kb
Host	smart-1484a9d7-4eb8-49ac-b88b-a7acaad246af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973759541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.973759541
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.406474239
Short name	T508
Test name
Test status
Simulation time	37990187878 ps
CPU time	56.05 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	203396 kb
Host	smart-8d94cf3c-0eb6-4e66-95d3-cf750c5aaef7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=406474239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.406474239
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2879155801
Short name	T490
Test name
Test status
Simulation time	17319780211 ps
CPU time	45.7 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	203352 kb
Host	smart-6c06977b-7997-46c6-8f4b-6fd053cf7249
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2879155801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2879155801
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1677964069
Short name	T786
Test name
Test status
Simulation time	57290673 ps
CPU time	2.14 seconds
Started	Apr 21 12:27:22 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	203220 kb
Host	smart-12c40e20-2678-4a3f-bcfc-d83765a7bded
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677964069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1677964069
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.1443863864
Short name	T301
Test name
Test status
Simulation time	1344649035 ps
CPU time	149.2 seconds
Started	Apr 21 12:27:23 PM PDT 24
Finished	Apr 21 12:29:53 PM PDT 24
Peak memory	207268 kb
Host	smart-546365fe-f0e1-4735-ae4a-2117f67af4f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443863864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1443863864
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2317113179
Short name	T12
Test name
Test status
Simulation time	194202707 ps
CPU time	21.9 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	211420 kb
Host	smart-736e0079-8e0e-4007-91ca-3abc30680158
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2317113179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2317113179
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3739827586
Short name	T529
Test name
Test status
Simulation time	1862092910 ps
CPU time	160.62 seconds
Started	Apr 21 12:27:34 PM PDT 24
Finished	Apr 21 12:30:15 PM PDT 24
Peak memory	209156 kb
Host	smart-951dae0f-38ea-4a7b-abaf-fe95f9bf195d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739827586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3739827586
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.824507741
Short name	T660
Test name
Test status
Simulation time	2761649913 ps
CPU time	348.91 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:33:18 PM PDT 24
Peak memory	226580 kb
Host	smart-881cc0f4-842b-40ba-b6cd-5fc1fc9ca89b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=824507741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_res et_error.824507741
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1026008421
Short name	T188
Test name
Test status
Simulation time	1162415749 ps
CPU time	24.92 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	211540 kb
Host	smart-868eb0a4-1c9e-4949-b0d8-74e7522afe85
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1026008421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1026008421
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3171245149
Short name	T101
Test name
Test status
Simulation time	2026345963 ps
CPU time	43.59 seconds
Started	Apr 21 12:27:20 PM PDT 24
Finished	Apr 21 12:28:04 PM PDT 24
Peak memory	211456 kb
Host	smart-e4760d77-83a3-4ed1-87f5-c2300e031114
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3171245149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3171245149
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.823406629
Short name	T159
Test name
Test status
Simulation time	35457145085 ps
CPU time	91.15 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:28:56 PM PDT 24
Peak memory	205764 kb
Host	smart-67ade37b-0d24-4848-8cde-ae4e5d0d9284
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=823406629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slo w_rsp.823406629
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3211292778
Short name	T312
Test name
Test status
Simulation time	12693694 ps
CPU time	1.72 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:27:28 PM PDT 24
Peak memory	203288 kb
Host	smart-33ae3575-9df3-4a37-a233-410884862465
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3211292778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3211292778
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.3548276623
Short name	T305
Test name
Test status
Simulation time	163651764 ps
CPU time	17.43 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:37 PM PDT 24
Peak memory	203472 kb
Host	smart-3ec821d1-08f6-4a28-8e6f-15a7e831f249
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3548276623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3548276623
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.1782155699
Short name	T735
Test name
Test status
Simulation time	246246733 ps
CPU time	12.38 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:41 PM PDT 24
Peak memory	211540 kb
Host	smart-e28d69c5-138c-4627-a728-39c5e6ce46f8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1782155699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1782155699
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.540016502
Short name	T715
Test name
Test status
Simulation time	19486519468 ps
CPU time	84.22 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:28:50 PM PDT 24
Peak memory	204580 kb
Host	smart-2f01dfca-4f64-410f-bae8-49cfb8bef854
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=540016502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.540016502
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3113379177
Short name	T3
Test name
Test status
Simulation time	34970107905 ps
CPU time	173.19 seconds
Started	Apr 21 12:27:22 PM PDT 24
Finished	Apr 21 12:30:16 PM PDT 24
Peak memory	204620 kb
Host	smart-874a655b-cc21-4acf-9b25-40d0b3ee954a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3113379177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3113379177
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.597509022
Short name	T822
Test name
Test status
Simulation time	13940617 ps
CPU time	2.12 seconds
Started	Apr 21 12:27:19 PM PDT 24
Finished	Apr 21 12:27:22 PM PDT 24
Peak memory	203336 kb
Host	smart-4024c25e-2c92-4e48-9dbe-541e6077da84
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597509022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.597509022
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.840847811
Short name	T458
Test name
Test status
Simulation time	154408107 ps
CPU time	6.77 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203248 kb
Host	smart-94524b6e-461d-46c5-b2c8-351c48d07345
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=840847811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.840847811
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.1605172697
Short name	T262
Test name
Test status
Simulation time	30246467 ps
CPU time	2.15 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	203544 kb
Host	smart-5a094677-9d58-4dcd-ad80-44724df0d843
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1605172697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1605172697
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3369070204
Short name	T44
Test name
Test status
Simulation time	19028619160 ps
CPU time	35.14 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:28:06 PM PDT 24
Peak memory	203316 kb
Host	smart-c2b9edec-a2dd-41b4-be3f-d105de6475cf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369070204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3369070204
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2120466453
Short name	T769
Test name
Test status
Simulation time	34407227 ps
CPU time	2.29 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	203244 kb
Host	smart-6763c65e-aac0-4efa-ad7f-3569c6bdf12f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120466453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2120466453
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.4040684799
Short name	T419
Test name
Test status
Simulation time	2163068133 ps
CPU time	119.33 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:29:19 PM PDT 24
Peak memory	209236 kb
Host	smart-6d49e8e5-af36-4a97-9638-a1e1db03dedb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040684799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.4040684799
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.4217267264
Short name	T441
Test name
Test status
Simulation time	591307948 ps
CPU time	61.72 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:53 PM PDT 24
Peak memory	205568 kb
Host	smart-dce8b3d2-e398-49db-b2da-49a23d4b8e7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4217267264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.4217267264
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3971640592
Short name	T227
Test name
Test status
Simulation time	3800902848 ps
CPU time	298.16 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:32:44 PM PDT 24
Peak memory	210084 kb
Host	smart-b345d599-19e3-4215-9fbb-29f704870399
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3971640592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3971640592
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1796664897
Short name	T900
Test name
Test status
Simulation time	303725785 ps
CPU time	97.24 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:29:08 PM PDT 24
Peak memory	209392 kb
Host	smart-a59805e0-9102-4665-bc42-7524d56ffbab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1796664897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.1796664897
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3371221463
Short name	T71
Test name
Test status
Simulation time	2668553713 ps
CPU time	22.71 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	211512 kb
Host	smart-a3e8df79-6c29-40d0-b07a-29b2c2868e8b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3371221463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3371221463
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1493959742
Short name	T386
Test name
Test status
Simulation time	179120471 ps
CPU time	6.44 seconds
Started	Apr 21 12:27:39 PM PDT 24
Finished	Apr 21 12:27:46 PM PDT 24
Peak memory	203660 kb
Host	smart-f2caa921-9fab-4e33-8a4a-f2fec87a4c56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1493959742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1493959742
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.481559744
Short name	T124
Test name
Test status
Simulation time	42150354324 ps
CPU time	367.35 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:33:38 PM PDT 24
Peak memory	206872 kb
Host	smart-7f909d02-3d54-4922-b2ee-32f98fd5a764
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=481559744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo w_rsp.481559744
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2321487148
Short name	T833
Test name
Test status
Simulation time	50081628 ps
CPU time	2.52 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	203300 kb
Host	smart-f0a39b46-376c-4a0e-a32c-85ee8f3963ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2321487148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2321487148
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.178334472
Short name	T751
Test name
Test status
Simulation time	503765396 ps
CPU time	10.26 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:01 PM PDT 24
Peak memory	203352 kb
Host	smart-cae04d4d-ce2d-4169-889b-31e3fa4cb2d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=178334472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.178334472
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.1032878710
Short name	T538
Test name
Test status
Simulation time	2567419470 ps
CPU time	24.54 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	204676 kb
Host	smart-6eb97a9a-e887-49b3-97bc-740b90f44fba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1032878710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1032878710
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3355073310
Short name	T416
Test name
Test status
Simulation time	23525894459 ps
CPU time	136.55 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:30:01 PM PDT 24
Peak memory	204616 kb
Host	smart-c22053d0-4da9-4a7b-8bc3-3477da1ba646
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355073310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3355073310
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3523300282
Short name	T835
Test name
Test status
Simulation time	24029034784 ps
CPU time	113.89 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:29:26 PM PDT 24
Peak memory	211792 kb
Host	smart-6b9b3092-fee6-43cf-84c3-b99518b4a023
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3523300282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3523300282
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3396088729
Short name	T70
Test name
Test status
Simulation time	169643707 ps
CPU time	21.33 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	211480 kb
Host	smart-01b0312b-f1e7-490c-ba06-3dd1beddfb71
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396088729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3396088729
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.2487048228
Short name	T882
Test name
Test status
Simulation time	111256365 ps
CPU time	2.49 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	203364 kb
Host	smart-88b56577-7531-4b1b-8c7b-69ec4ee72c68
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2487048228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2487048228
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.497788549
Short name	T685
Test name
Test status
Simulation time	29287215 ps
CPU time	2.33 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:27:33 PM PDT 24
Peak memory	203340 kb
Host	smart-b26aea1b-7e2f-4971-b2bf-1b0cea4a1f2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=497788549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.497788549
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.921715597
Short name	T112
Test name
Test status
Simulation time	6843924158 ps
CPU time	30.57 seconds
Started	Apr 21 12:27:41 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	203372 kb
Host	smart-55d21e8f-f3ec-40c6-a92f-7d1ef33d31f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=921715597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.921715597
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.961672880
Short name	T209
Test name
Test status
Simulation time	10454904450 ps
CPU time	33.97 seconds
Started	Apr 21 12:27:38 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	203324 kb
Host	smart-e4da743c-2402-4c8d-a55c-2589923ec23e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=961672880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.961672880
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3920973089
Short name	T21
Test name
Test status
Simulation time	38460884 ps
CPU time	2.08 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	203240 kb
Host	smart-bb633d14-41b2-4f9b-9920-bf44e094dd73
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920973089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3920973089
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.1840078793
Short name	T807
Test name
Test status
Simulation time	199272503 ps
CPU time	20.54 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	204504 kb
Host	smart-95cb29f9-48cf-45e2-9ce3-d03626575c4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840078793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1840078793
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1925405273
Short name	T75
Test name
Test status
Simulation time	3801143946 ps
CPU time	88.23 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:29:18 PM PDT 24
Peak memory	205256 kb
Host	smart-fc2290cc-2128-4e80-8608-0345696ecaf6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1925405273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1925405273
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3742218196
Short name	T500
Test name
Test status
Simulation time	928515170 ps
CPU time	215.97 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:31:07 PM PDT 24
Peak memory	209356 kb
Host	smart-19bca167-9df5-46d1-97f5-a7d1e30d77e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3742218196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3742218196
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3474645433
Short name	T244
Test name
Test status
Simulation time	4365669808 ps
CPU time	483.56 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:35:32 PM PDT 24
Peak memory	219812 kb
Host	smart-e8c7b1ab-bcd0-4882-9996-065583e0d856
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3474645433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.3474645433
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3745798986
Short name	T865
Test name
Test status
Simulation time	3715964644 ps
CPU time	35.57 seconds
Started	Apr 21 12:27:39 PM PDT 24
Finished	Apr 21 12:28:16 PM PDT 24
Peak memory	211600 kb
Host	smart-d3278af6-799c-4422-8468-cae020a1795f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745798986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3745798986
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1664083699
Short name	T563
Test name
Test status
Simulation time	482283154 ps
CPU time	17.22 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:27:49 PM PDT 24
Peak memory	204356 kb
Host	smart-0f686e05-8ead-4c78-9060-1095077738e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1664083699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1664083699
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.740606739
Short name	T469
Test name
Test status
Simulation time	101192134550 ps
CPU time	202.3 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:30:55 PM PDT 24
Peak memory	205888 kb
Host	smart-e848d1e8-87c0-4088-a6ca-b7cb22d0064e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=740606739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.740606739
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.434656957
Short name	T686
Test name
Test status
Simulation time	573145111 ps
CPU time	17.67 seconds
Started	Apr 21 12:27:35 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	203900 kb
Host	smart-8bdf18fc-c813-430d-9251-44cfb7f5e676
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=434656957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.434656957
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.3960025528
Short name	T283
Test name
Test status
Simulation time	485302889 ps
CPU time	9.12 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203308 kb
Host	smart-9ce24674-c8cf-4ace-a4e1-697357fb6a4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3960025528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3960025528
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.1086678833
Short name	T894
Test name
Test status
Simulation time	486223210 ps
CPU time	14.71 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:28:11 PM PDT 24
Peak memory	204336 kb
Host	smart-de8697c6-e491-4d69-b6d9-a4aa7d83b4d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1086678833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1086678833
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1010063671
Short name	T143
Test name
Test status
Simulation time	60633986722 ps
CPU time	157.96 seconds
Started	Apr 21 12:27:38 PM PDT 24
Finished	Apr 21 12:30:16 PM PDT 24
Peak memory	211512 kb
Host	smart-92bb9c82-5237-4b56-9c22-f76ca7db6ee4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010063671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1010063671
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2521426064
Short name	T509
Test name
Test status
Simulation time	83720335606 ps
CPU time	328.19 seconds
Started	Apr 21 12:27:38 PM PDT 24
Finished	Apr 21 12:33:07 PM PDT 24
Peak memory	205180 kb
Host	smart-cd327706-82fa-4c53-befd-ca2d76a77e34
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2521426064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2521426064
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3992844974
Short name	T177
Test name
Test status
Simulation time	192019231 ps
CPU time	27.54 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	204844 kb
Host	smart-eebdb653-9aa7-4ded-a231-3a07713e4393
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992844974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3992844974
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.3094717565
Short name	T606
Test name
Test status
Simulation time	1657744134 ps
CPU time	36.7 seconds
Started	Apr 21 12:27:36 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	203800 kb
Host	smart-67590b03-e517-4329-b122-c717d7a55d0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3094717565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3094717565
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.754743512
Short name	T219
Test name
Test status
Simulation time	236218895 ps
CPU time	3.25 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	203228 kb
Host	smart-ae522f94-47f9-4890-b4e4-2469151888ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=754743512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.754743512
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.139468123
Short name	T714
Test name
Test status
Simulation time	6781944990 ps
CPU time	28.43 seconds
Started	Apr 21 12:28:00 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	203352 kb
Host	smart-02113776-531a-47d6-96f1-e44836d89305
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=139468123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.139468123
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2476344122
Short name	T777
Test name
Test status
Simulation time	2022682060 ps
CPU time	20.1 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	203272 kb
Host	smart-362cf31b-2558-47d5-a592-9cc39e8df333
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2476344122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2476344122
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2926574132
Short name	T667
Test name
Test status
Simulation time	48638562 ps
CPU time	2.26 seconds
Started	Apr 21 12:27:26 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	203248 kb
Host	smart-f31fd4b3-dbeb-4f09-b0b4-d98b26857aab
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926574132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2926574132
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.2188082386
Short name	T498
Test name
Test status
Simulation time	1461377317 ps
CPU time	133.41 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:30:04 PM PDT 24
Peak memory	205492 kb
Host	smart-90ef227f-ba32-49d6-baa1-636ba91afc0d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2188082386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2188082386
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.51327448
Short name	T640
Test name
Test status
Simulation time	5746666452 ps
CPU time	163.1 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:30:11 PM PDT 24
Peak memory	209260 kb
Host	smart-a0b76df2-23b1-45f3-a773-9004b7abd422
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=51327448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.51327448
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3258758067
Short name	T243
Test name
Test status
Simulation time	462799644 ps
CPU time	208.78 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:30:59 PM PDT 24
Peak memory	208324 kb
Host	smart-f95cef9c-468a-490a-94b5-1257508eb52e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3258758067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3258758067
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.832740819
Short name	T543
Test name
Test status
Simulation time	169891776 ps
CPU time	67.65 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	208324 kb
Host	smart-fd95348c-4c41-47a9-829c-c3587f657c56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=832740819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.832740819
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1461926973
Short name	T518
Test name
Test status
Simulation time	74632166 ps
CPU time	6.05 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	204848 kb
Host	smart-f0151348-600e-4423-9086-e3363ab1b136
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1461926973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1461926973
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3180825156
Short name	T592
Test name
Test status
Simulation time	2122316481 ps
CPU time	44.11 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:28:10 PM PDT 24
Peak memory	211476 kb
Host	smart-e1d38da1-8fa5-4e07-84cc-c14ba69ad5ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180825156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3180825156
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.795598249
Short name	T93
Test name
Test status
Simulation time	140754133914 ps
CPU time	606.37 seconds
Started	Apr 21 12:27:39 PM PDT 24
Finished	Apr 21 12:37:46 PM PDT 24
Peak memory	205980 kb
Host	smart-76183944-7f8e-4268-8e52-1ede9c47e502
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=795598249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.795598249
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3381833501
Short name	T273
Test name
Test status
Simulation time	902153721 ps
CPU time	13.83 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	203356 kb
Host	smart-8a403d94-8a5c-4530-9d35-f70b31b90273
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381833501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3381833501
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.2233777009
Short name	T300
Test name
Test status
Simulation time	90398394 ps
CPU time	6.3 seconds
Started	Apr 21 12:27:42 PM PDT 24
Finished	Apr 21 12:27:49 PM PDT 24
Peak memory	203352 kb
Host	smart-88915c67-e719-433b-ac24-724940564259
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2233777009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2233777009
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.102057362
Short name	T198
Test name
Test status
Simulation time	868235431 ps
CPU time	27.69 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	211484 kb
Host	smart-ae3dd933-1cfd-4ce6-b9f1-e14d6aa77ff9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=102057362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.102057362
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2890215264
Short name	T56
Test name
Test status
Simulation time	9847643927 ps
CPU time	56.07 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:28:51 PM PDT 24
Peak memory	204808 kb
Host	smart-f8817405-5943-4f15-91e3-0b8c3b308373
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890215264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2890215264
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3106168692
Short name	T385
Test name
Test status
Simulation time	120011329158 ps
CPU time	291.32 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:32:38 PM PDT 24
Peak memory	211484 kb
Host	smart-3b55799e-5ae3-43a3-91eb-a21f985773b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3106168692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3106168692
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2280748785
Short name	T869
Test name
Test status
Simulation time	29792432 ps
CPU time	3.21 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:27:51 PM PDT 24
Peak memory	203968 kb
Host	smart-0f9a4190-b3d8-4d13-bff5-013f26f3db89
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280748785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2280748785
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.3425990028
Short name	T153
Test name
Test status
Simulation time	1697344850 ps
CPU time	35.13 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:28:25 PM PDT 24
Peak memory	203256 kb
Host	smart-8d0b625b-8a4b-452e-9b14-f3977678d05a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3425990028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3425990028
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.183659745
Short name	T867
Test name
Test status
Simulation time	23434099 ps
CPU time	2.04 seconds
Started	Apr 21 12:27:57 PM PDT 24
Finished	Apr 21 12:27:59 PM PDT 24
Peak memory	203312 kb
Host	smart-91b0b06f-1017-4308-bd38-49cad8900bfb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=183659745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.183659745
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2239484299
Short name	T424
Test name
Test status
Simulation time	4819485873 ps
CPU time	29.65 seconds
Started	Apr 21 12:27:42 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	203328 kb
Host	smart-9bc4a6a0-2988-4be3-8d94-9b51762a69cd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239484299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2239484299
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3810421260
Short name	T182
Test name
Test status
Simulation time	9173689878 ps
CPU time	28.15 seconds
Started	Apr 21 12:27:38 PM PDT 24
Finished	Apr 21 12:28:07 PM PDT 24
Peak memory	203296 kb
Host	smart-1685b5f5-d215-4e13-be2b-7a59a251c9ae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3810421260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3810421260
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.909509148
Short name	T885
Test name
Test status
Simulation time	140468265 ps
CPU time	2.19 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	203304 kb
Host	smart-aca9b012-25f1-4ae0-bb83-4e0c6918db1e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909509148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.909509148
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.1763485893
Short name	T590
Test name
Test status
Simulation time	1517196244 ps
CPU time	83.36 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:28:56 PM PDT 24
Peak memory	211532 kb
Host	smart-2d937eb9-624c-4f97-9403-f45ddd94910e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1763485893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1763485893
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3250461353
Short name	T551
Test name
Test status
Simulation time	2779601584 ps
CPU time	85.2 seconds
Started	Apr 21 12:27:37 PM PDT 24
Finished	Apr 21 12:29:02 PM PDT 24
Peak memory	205904 kb
Host	smart-f4dc41b4-c7ff-4886-8fe4-af1f0660eb1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3250461353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3250461353
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3964917204
Short name	T239
Test name
Test status
Simulation time	419660035 ps
CPU time	174.12 seconds
Started	Apr 21 12:27:37 PM PDT 24
Finished	Apr 21 12:30:32 PM PDT 24
Peak memory	208496 kb
Host	smart-662254c4-07ea-4a9e-b952-7d284322146c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3964917204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.3964917204
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2045795307
Short name	T476
Test name
Test status
Simulation time	2800437419 ps
CPU time	379.81 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:33:50 PM PDT 24
Peak memory	227644 kb
Host	smart-17bb3a47-8e50-48a3-aea3-56e9c0b1147d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2045795307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.2045795307
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2322329454
Short name	T425
Test name
Test status
Simulation time	14653310 ps
CPU time	1.83 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	203308 kb
Host	smart-8919d715-fc41-4881-a0e8-f838e9d81390
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322329454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2322329454
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2491646953
Short name	T496
Test name
Test status
Simulation time	103851585 ps
CPU time	18.24 seconds
Started	Apr 21 12:27:25 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	204484 kb
Host	smart-353b083f-8652-48f6-8f18-f780dfab9506
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2491646953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2491646953
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3629458826
Short name	T723
Test name
Test status
Simulation time	7982589825 ps
CPU time	58.03 seconds
Started	Apr 21 12:27:35 PM PDT 24
Finished	Apr 21 12:28:34 PM PDT 24
Peak memory	211460 kb
Host	smart-856b2a98-13ae-4d5d-bd7a-93b12cf9d9a3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3629458826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.3629458826
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3338441350
Short name	T647
Test name
Test status
Simulation time	247076394 ps
CPU time	14.59 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:28:04 PM PDT 24
Peak memory	203352 kb
Host	smart-8eea25e3-e6d7-4a13-b7d4-6d1d7e834b8e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3338441350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3338441350
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.2024471099
Short name	T67
Test name
Test status
Simulation time	1020567117 ps
CPU time	17.96 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:27:46 PM PDT 24
Peak memory	203260 kb
Host	smart-24b75c95-6750-4704-93d6-db391f135827
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2024471099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2024471099
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.2902479239
Short name	T713
Test name
Test status
Simulation time	93963616 ps
CPU time	10.56 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:02 PM PDT 24
Peak memory	211492 kb
Host	smart-8f4500cb-594d-4cd0-a6d8-fc8fa3af0d41
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2902479239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2902479239
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.603452158
Short name	T871
Test name
Test status
Simulation time	3892114497 ps
CPU time	12.36 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:04 PM PDT 24
Peak memory	203312 kb
Host	smart-96d0efe1-94f8-46fc-b223-ddba3af94eb1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=603452158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.603452158
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.696045315
Short name	T192
Test name
Test status
Simulation time	17264904271 ps
CPU time	179.96 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:30:27 PM PDT 24
Peak memory	204880 kb
Host	smart-b103e042-4723-4ca9-bbdf-0df9be7326df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=696045315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.696045315
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.227878514
Short name	T353
Test name
Test status
Simulation time	65613862 ps
CPU time	9.07 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	211424 kb
Host	smart-269ca80e-f7be-4f1d-afe9-bd93c3b4f3b6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227878514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.227878514
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.2625675363
Short name	T364
Test name
Test status
Simulation time	2244767469 ps
CPU time	22.15 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	203420 kb
Host	smart-e1f5d130-c33b-4986-9b7e-8b2fda406159
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2625675363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2625675363
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.2146681857
Short name	T811
Test name
Test status
Simulation time	146373402 ps
CPU time	3.4 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:32 PM PDT 24
Peak memory	203292 kb
Host	smart-0cf145d0-2696-47b7-9756-7887ef4ad599
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2146681857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2146681857
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3431023617
Short name	T176
Test name
Test status
Simulation time	6078856827 ps
CPU time	31.17 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:28:16 PM PDT 24
Peak memory	202632 kb
Host	smart-756c25dc-be53-413c-8868-a137c8ac57a6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431023617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3431023617
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3732163739
Short name	T763
Test name
Test status
Simulation time	7158538394 ps
CPU time	27.83 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:27:58 PM PDT 24
Peak memory	203348 kb
Host	smart-9b88bd43-092b-4a82-add6-5f1f0eaf71a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3732163739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3732163739
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1741169521
Short name	T746
Test name
Test status
Simulation time	108625048 ps
CPU time	2.13 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:31 PM PDT 24
Peak memory	203528 kb
Host	smart-1e248d62-4dde-4d08-ad6a-8c0433a8dda5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741169521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1741169521
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.1960574324
Short name	T147
Test name
Test status
Simulation time	4781411840 ps
CPU time	121.72 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:29:34 PM PDT 24
Peak memory	211592 kb
Host	smart-c5a2bd10-d463-4f90-9226-d5b3d1b8177a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1960574324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1960574324
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1737038476
Short name	T321
Test name
Test status
Simulation time	1283458364 ps
CPU time	94.39 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:29:06 PM PDT 24
Peak memory	205244 kb
Host	smart-232324ad-2c3e-49cf-a0b7-8c4186d009f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1737038476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1737038476
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3096849653
Short name	T358
Test name
Test status
Simulation time	3390498482 ps
CPU time	73.85 seconds
Started	Apr 21 12:27:44 PM PDT 24
Finished	Apr 21 12:28:59 PM PDT 24
Peak memory	207676 kb
Host	smart-e99c4a37-ceb7-4a9e-b9ea-fa16ca61969f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3096849653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.3096849653
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.420759218
Short name	T374
Test name
Test status
Simulation time	403291857 ps
CPU time	104.49 seconds
Started	Apr 21 12:28:04 PM PDT 24
Finished	Apr 21 12:29:49 PM PDT 24
Peak memory	209476 kb
Host	smart-c7dc5b1e-bea4-4588-9b64-ddcdb7b53a2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=420759218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.420759218
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1698864517
Short name	T578
Test name
Test status
Simulation time	134746638 ps
CPU time	13.05 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	204708 kb
Host	smart-07307687-db05-4ce7-827e-d6857425ad4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1698864517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1698864517
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3416833407
Short name	T218
Test name
Test status
Simulation time	991434127 ps
CPU time	40.55 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	211444 kb
Host	smart-1f09b724-a96a-45cb-87a0-417f3bc66011
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3416833407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3416833407
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2860697478
Short name	T122
Test name
Test status
Simulation time	96597999665 ps
CPU time	269.55 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:31:58 PM PDT 24
Peak memory	211492 kb
Host	smart-7f1756c2-e658-42cb-bd6c-22c00754b69e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2860697478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2860697478
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2627458183
Short name	T311
Test name
Test status
Simulation time	1362812642 ps
CPU time	18.41 seconds
Started	Apr 21 12:27:44 PM PDT 24
Finished	Apr 21 12:28:04 PM PDT 24
Peak memory	203732 kb
Host	smart-df24cff4-a18c-45d7-a269-93bd7ce389ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2627458183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2627458183
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.325432023
Short name	T384
Test name
Test status
Simulation time	187735133 ps
CPU time	7.46 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	203260 kb
Host	smart-840db004-560c-49a9-a0b6-976f91deae16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325432023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.325432023
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.2836614134
Short name	T581
Test name
Test status
Simulation time	335543227 ps
CPU time	24.01 seconds
Started	Apr 21 12:27:27 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	211496 kb
Host	smart-7e2fdb5e-4702-4d97-a216-18d8e38faefb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2836614134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2836614134
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1184468448
Short name	T174
Test name
Test status
Simulation time	16257146926 ps
CPU time	80.9 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:28:54 PM PDT 24
Peak memory	211556 kb
Host	smart-be8fc122-2f13-489b-8f10-07854f94b58f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184468448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1184468448
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.592878580
Short name	T230
Test name
Test status
Simulation time	64021572597 ps
CPU time	208.19 seconds
Started	Apr 21 12:27:37 PM PDT 24
Finished	Apr 21 12:31:06 PM PDT 24
Peak memory	211500 kb
Host	smart-96aa3b3a-c957-486f-8785-e9e26656db26
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=592878580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.592878580
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1541610593
Short name	T526
Test name
Test status
Simulation time	291013651 ps
CPU time	24.13 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:27:58 PM PDT 24
Peak memory	211440 kb
Host	smart-ee7eee81-1e01-4e5e-bb4b-76b19a0fbb42
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541610593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1541610593
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.1554804195
Short name	T257
Test name
Test status
Simulation time	103730945 ps
CPU time	7.76 seconds
Started	Apr 21 12:27:54 PM PDT 24
Finished	Apr 21 12:28:02 PM PDT 24
Peak memory	203872 kb
Host	smart-ed5fc5c6-ffe4-4a83-b9ca-6be6ff2e156b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1554804195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1554804195
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.2193139460
Short name	T698
Test name
Test status
Simulation time	231645220 ps
CPU time	3.05 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:27:37 PM PDT 24
Peak memory	203360 kb
Host	smart-5c4307d9-0635-48f8-9d61-360680b64083
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2193139460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2193139460
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1936437103
Short name	T437
Test name
Test status
Simulation time	16257868200 ps
CPU time	34.01 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:24 PM PDT 24
Peak memory	203344 kb
Host	smart-43e9cc71-e9da-46e6-b09b-c880582fb93b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936437103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1936437103
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1603250658
Short name	T497
Test name
Test status
Simulation time	21362686904 ps
CPU time	39.75 seconds
Started	Apr 21 12:27:28 PM PDT 24
Finished	Apr 21 12:28:08 PM PDT 24
Peak memory	203324 kb
Host	smart-ba466f65-90f2-430c-8854-6232618c1917
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1603250658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1603250658
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3469882619
Short name	T387
Test name
Test status
Simulation time	34582337 ps
CPU time	2.72 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:27:48 PM PDT 24
Peak memory	202456 kb
Host	smart-65ef2d6c-9242-45cf-856f-5cb2c677e3fe
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469882619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3469882619
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.2417644767
Short name	T874
Test name
Test status
Simulation time	2508936916 ps
CPU time	54.99 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:47 PM PDT 24
Peak memory	206128 kb
Host	smart-01006657-7530-4e92-8a6c-19420a789a35
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2417644767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2417644767
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.332128840
Short name	T749
Test name
Test status
Simulation time	1042744140 ps
CPU time	126.65 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:29:37 PM PDT 24
Peak memory	205372 kb
Host	smart-8c28c6f5-ad11-45c7-9cd1-424d4223f186
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=332128840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.332128840
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3659546204
Short name	T109
Test name
Test status
Simulation time	263659307 ps
CPU time	86.94 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:29:16 PM PDT 24
Peak memory	207904 kb
Host	smart-409b70ff-0fb7-4f28-b9bd-297fa53ac091
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3659546204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3659546204
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1869244478
Short name	T251
Test name
Test status
Simulation time	248032136 ps
CPU time	49.58 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	208852 kb
Host	smart-96292a2d-4f2b-4b9d-9a97-f6b59f02299c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1869244478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.1869244478
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2392381050
Short name	T395
Test name
Test status
Simulation time	21290010 ps
CPU time	2.02 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	203208 kb
Host	smart-c5ba3bab-7161-470b-976c-7107ec74f122
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2392381050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2392381050
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3304707021
Short name	T858
Test name
Test status
Simulation time	149531064 ps
CPU time	7.02 seconds
Started	Apr 21 12:27:56 PM PDT 24
Finished	Apr 21 12:28:03 PM PDT 24
Peak memory	203228 kb
Host	smart-30b6abdd-bf04-406b-ba1d-064d8f3e05db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3304707021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3304707021
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2295777428
Short name	T603
Test name
Test status
Simulation time	170172304649 ps
CPU time	553.66 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:37:00 PM PDT 24
Peak memory	206688 kb
Host	smart-4e24becc-76ca-4b24-abe7-579791896d03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2295777428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.2295777428
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3627567273
Short name	T755
Test name
Test status
Simulation time	38010649 ps
CPU time	3.73 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:27:51 PM PDT 24
Peak memory	203356 kb
Host	smart-99878ac3-889e-477f-a856-a53b77c4e5b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3627567273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3627567273
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.833632169
Short name	T415
Test name
Test status
Simulation time	2702709776 ps
CPU time	16.3 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:28:01 PM PDT 24
Peak memory	203300 kb
Host	smart-f2e76c9b-fa6e-47eb-a749-3aa0b8e1de4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833632169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.833632169
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.3152809141
Short name	T868
Test name
Test status
Simulation time	358663231 ps
CPU time	16 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	211492 kb
Host	smart-c52d8b29-85ed-4a7f-8e0e-69e71e4a1d7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3152809141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3152809141
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2741814118
Short name	T46
Test name
Test status
Simulation time	31876585514 ps
CPU time	176.73 seconds
Started	Apr 21 12:27:51 PM PDT 24
Finished	Apr 21 12:30:48 PM PDT 24
Peak memory	204696 kb
Host	smart-abeca47c-d957-45c3-8a7f-a55ada5cf0ef
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741814118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2741814118
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1692306859
Short name	T673
Test name
Test status
Simulation time	2485656713 ps
CPU time	25.62 seconds
Started	Apr 21 12:27:36 PM PDT 24
Finished	Apr 21 12:28:03 PM PDT 24
Peak memory	203620 kb
Host	smart-c74bb723-71b5-41a0-8118-9b220a45fffb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1692306859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1692306859
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.916334079
Short name	T282
Test name
Test status
Simulation time	39464623 ps
CPU time	5.22 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	211412 kb
Host	smart-7f734b36-d727-4223-b302-e90860587d03
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916334079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.916334079
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.197254421
Short name	T233
Test name
Test status
Simulation time	2579557020 ps
CPU time	26.82 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:28:14 PM PDT 24
Peak memory	203344 kb
Host	smart-dbdac5a4-bc99-4b6a-9ad6-91b61f6329d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=197254421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.197254421
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.2283402977
Short name	T80
Test name
Test status
Simulation time	384136866 ps
CPU time	3.25 seconds
Started	Apr 21 12:27:29 PM PDT 24
Finished	Apr 21 12:27:34 PM PDT 24
Peak memory	203344 kb
Host	smart-fc26e3e3-1013-40db-9a43-69df6b388c01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2283402977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2283402977
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2617541166
Short name	T429
Test name
Test status
Simulation time	12616023106 ps
CPU time	37.15 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:28:09 PM PDT 24
Peak memory	203344 kb
Host	smart-14eef022-bb67-4205-b511-80cc3d589f33
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617541166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2617541166
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3498348570
Short name	T574
Test name
Test status
Simulation time	2372898694 ps
CPU time	21.29 seconds
Started	Apr 21 12:28:14 PM PDT 24
Finished	Apr 21 12:28:36 PM PDT 24
Peak memory	203300 kb
Host	smart-c9c3df92-dbe6-4432-b943-2b90b336fa2a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3498348570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3498348570
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1511639410
Short name	T589
Test name
Test status
Simulation time	121640333 ps
CPU time	2.42 seconds
Started	Apr 21 12:27:39 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	203332 kb
Host	smart-d67c17d1-a58f-4287-9e5e-a65ee8f47897
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511639410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1511639410
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.2920128083
Short name	T91
Test name
Test status
Simulation time	12419260461 ps
CPU time	221.73 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:31:33 PM PDT 24
Peak memory	209656 kb
Host	smart-8bd9ef40-5516-48f2-a893-bf34ea04b44c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2920128083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2920128083
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1575654910
Short name	T392
Test name
Test status
Simulation time	423961903 ps
CPU time	13.43 seconds
Started	Apr 21 12:27:34 PM PDT 24
Finished	Apr 21 12:27:48 PM PDT 24
Peak memory	203300 kb
Host	smart-7f76fbd7-bfa3-41e4-8a81-3f24bf74e0c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1575654910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1575654910
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2848092078
Short name	T730
Test name
Test status
Simulation time	180919137 ps
CPU time	62.75 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:28:34 PM PDT 24
Peak memory	206352 kb
Host	smart-cac6aef6-20f4-4e3e-a273-eb99487f32f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2848092078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.2848092078
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3104772406
Short name	T433
Test name
Test status
Simulation time	1068663255 ps
CPU time	287.34 seconds
Started	Apr 21 12:27:30 PM PDT 24
Finished	Apr 21 12:32:19 PM PDT 24
Peak memory	219656 kb
Host	smart-ebbcc71e-86dc-4ca6-8eff-0626672d1e5f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3104772406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3104772406
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3091153657
Short name	T643
Test name
Test status
Simulation time	218706623 ps
CPU time	9.94 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	204928 kb
Host	smart-6a105848-4eee-4bc7-806d-dd1199c5a1a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3091153657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3091153657
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1285234054
Short name	T691
Test name
Test status
Simulation time	1461337976 ps
CPU time	40.23 seconds
Started	Apr 21 12:27:34 PM PDT 24
Finished	Apr 21 12:28:15 PM PDT 24
Peak memory	211444 kb
Host	smart-c3bd83e9-5f7a-4c30-ac96-e0764b002ab1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1285234054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1285234054
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1924881132
Short name	T237
Test name
Test status
Simulation time	257655205492 ps
CPU time	548.7 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:36:59 PM PDT 24
Peak memory	211612 kb
Host	smart-7ec94e87-cf5d-4602-81f1-780596274cc6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1924881132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1924881132
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.767825727
Short name	T853
Test name
Test status
Simulation time	196006785 ps
CPU time	12.14 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:44 PM PDT 24
Peak memory	202876 kb
Host	smart-6debfbf1-25c2-45fe-b0d0-cde99f2583fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=767825727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.767825727
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.1043094331
Short name	T545
Test name
Test status
Simulation time	152411133 ps
CPU time	10.59 seconds
Started	Apr 21 12:27:40 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	203272 kb
Host	smart-b9278210-f547-4272-9819-4b52222aeecf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1043094331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1043094331
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.2639370064
Short name	T569
Test name
Test status
Simulation time	523832389 ps
CPU time	21.46 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:27:55 PM PDT 24
Peak memory	211444 kb
Host	smart-3fee4c60-9f81-47bd-8329-8600602c51ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639370064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2639370064
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2267376241
Short name	T229
Test name
Test status
Simulation time	23975805659 ps
CPU time	47.47 seconds
Started	Apr 21 12:27:43 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	211592 kb
Host	smart-d4209dde-8cb6-4737-ab53-b534aad84d9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267376241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2267376241
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3083220932
Short name	T411
Test name
Test status
Simulation time	42845630742 ps
CPU time	285.03 seconds
Started	Apr 21 12:27:38 PM PDT 24
Finished	Apr 21 12:32:24 PM PDT 24
Peak memory	211552 kb
Host	smart-0cde041f-e0c4-48b7-837d-3058f5752294
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3083220932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3083220932
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2538097974
Short name	T444
Test name
Test status
Simulation time	58312265 ps
CPU time	10.2 seconds
Started	Apr 21 12:27:31 PM PDT 24
Finished	Apr 21 12:27:42 PM PDT 24
Peak memory	203736 kb
Host	smart-f01df1f3-354d-4b3f-917f-7d6b3e671865
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538097974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2538097974
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.677224774
Short name	T789
Test name
Test status
Simulation time	953073951 ps
CPU time	18.92 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:28:14 PM PDT 24
Peak memory	203368 kb
Host	smart-8dceef40-f606-43fa-bde2-e858f6818bdd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=677224774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.677224774
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.56342990
Short name	T199
Test name
Test status
Simulation time	389668900 ps
CPU time	3.2 seconds
Started	Apr 21 12:27:34 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	203304 kb
Host	smart-0d6311c9-3986-495a-8e39-e8749beae1f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=56342990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.56342990
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1317476898
Short name	T111
Test name
Test status
Simulation time	8085557219 ps
CPU time	31.26 seconds
Started	Apr 21 12:27:59 PM PDT 24
Finished	Apr 21 12:28:31 PM PDT 24
Peak memory	203392 kb
Host	smart-dc56625a-bdfa-4faa-8643-3cfc0671a1fe
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317476898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1317476898
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3612270975
Short name	T712
Test name
Test status
Simulation time	7404956372 ps
CPU time	39.07 seconds
Started	Apr 21 12:27:41 PM PDT 24
Finished	Apr 21 12:28:21 PM PDT 24
Peak memory	203336 kb
Host	smart-a6bf9c00-0cdd-435b-9cc9-28dabd0bfe70
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3612270975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3612270975
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1190476493
Short name	T531
Test name
Test status
Simulation time	25485588 ps
CPU time	2.12 seconds
Started	Apr 21 12:27:36 PM PDT 24
Finished	Apr 21 12:27:38 PM PDT 24
Peak memory	203220 kb
Host	smart-b0cfa4a6-9149-4ea4-b400-b5a59f9f5505
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190476493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1190476493
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.1462318688
Short name	T428
Test name
Test status
Simulation time	625978606 ps
CPU time	77.13 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:29:10 PM PDT 24
Peak memory	208344 kb
Host	smart-a5fb2e0f-9f16-40c5-baa0-8f98e07f9f77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1462318688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1462318688
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3146491907
Short name	T876
Test name
Test status
Simulation time	5789396116 ps
CPU time	114.72 seconds
Started	Apr 21 12:27:35 PM PDT 24
Finished	Apr 21 12:29:30 PM PDT 24
Peak memory	205940 kb
Host	smart-9988834e-b908-419a-84b1-53a07e9a5638
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3146491907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3146491907
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1915142228
Short name	T27
Test name
Test status
Simulation time	354354707 ps
CPU time	144.89 seconds
Started	Apr 21 12:27:54 PM PDT 24
Finished	Apr 21 12:30:19 PM PDT 24
Peak memory	208592 kb
Host	smart-7c0239b7-86c8-44fc-8704-fb8720e6d3ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1915142228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.1915142228
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.347372277
Short name	T247
Test name
Test status
Simulation time	2089268480 ps
CPU time	225.87 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:31:32 PM PDT 24
Peak memory	219668 kb
Host	smart-a6bc2198-3391-4f0e-bd7f-aec0a78f96d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=347372277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.347372277
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.727748869
Short name	T115
Test name
Test status
Simulation time	922273810 ps
CPU time	13.53 seconds
Started	Apr 21 12:27:40 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	211472 kb
Host	smart-ae070242-cf66-4256-9885-6fc91222a71e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=727748869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.727748869
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2162724871
Short name	T303
Test name
Test status
Simulation time	1456390548 ps
CPU time	53.92 seconds
Started	Apr 21 12:26:35 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	205480 kb
Host	smart-4b3e742b-49d3-475c-8d57-dc0acc5732e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2162724871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2162724871
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2547637294
Short name	T117
Test name
Test status
Simulation time	230665895602 ps
CPU time	772.75 seconds
Started	Apr 21 12:26:34 PM PDT 24
Finished	Apr 21 12:39:27 PM PDT 24
Peak memory	207348 kb
Host	smart-5464e8c9-946e-4498-a9db-e3bc279f6c03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2547637294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.2547637294
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.728207899
Short name	T614
Test name
Test status
Simulation time	18760797 ps
CPU time	1.75 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:26:47 PM PDT 24
Peak memory	203256 kb
Host	smart-f4b39a6f-f6a3-4e9f-a6a4-a27a0d35720b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=728207899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.728207899
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.2186474510
Short name	T873
Test name
Test status
Simulation time	641906592 ps
CPU time	13.12 seconds
Started	Apr 21 12:26:45 PM PDT 24
Finished	Apr 21 12:26:59 PM PDT 24
Peak memory	203212 kb
Host	smart-8e9c6356-f713-4acd-b13a-e1bcbcdb6399
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186474510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2186474510
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.1660292580
Short name	T608
Test name
Test status
Simulation time	123365804 ps
CPU time	16.19 seconds
Started	Apr 21 12:26:27 PM PDT 24
Finished	Apr 21 12:26:44 PM PDT 24
Peak memory	204572 kb
Host	smart-cc30e397-6a63-4e55-b351-2e3a92a75d71
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1660292580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1660292580
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2333060651
Short name	T442
Test name
Test status
Simulation time	20144531783 ps
CPU time	108.55 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:28:50 PM PDT 24
Peak memory	211488 kb
Host	smart-21d8e590-c205-4b70-bec2-c8ecbcae7140
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333060651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2333060651
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1901524350
Short name	T58
Test name
Test status
Simulation time	18162928687 ps
CPU time	144.91 seconds
Started	Apr 21 12:26:34 PM PDT 24
Finished	Apr 21 12:29:05 PM PDT 24
Peak memory	204808 kb
Host	smart-86169eb6-d87a-44f9-b1d9-f2cee09deb76
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1901524350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1901524350
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3723170960
Short name	T587
Test name
Test status
Simulation time	36275445 ps
CPU time	4.37 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	211504 kb
Host	smart-a56d7457-6973-4c5f-a68f-a80c8e2070f5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723170960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3723170960
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.3369688413
Short name	T84
Test name
Test status
Simulation time	2122160835 ps
CPU time	36.24 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	204088 kb
Host	smart-4d7958a2-39e8-4509-b0ea-ac1ef08fef09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3369688413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3369688413
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.3872938068
Short name	T60
Test name
Test status
Simulation time	157365103 ps
CPU time	3.17 seconds
Started	Apr 21 12:26:44 PM PDT 24
Finished	Apr 21 12:26:47 PM PDT 24
Peak memory	203268 kb
Host	smart-e2373502-689a-40a9-aae2-c644270a2b28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872938068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3872938068
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4232914287
Short name	T616
Test name
Test status
Simulation time	5503554626 ps
CPU time	28.21 seconds
Started	Apr 21 12:26:33 PM PDT 24
Finished	Apr 21 12:27:02 PM PDT 24
Peak memory	203388 kb
Host	smart-00a1cbf2-eae5-4ed7-af2d-206d4232dc37
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232914287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4232914287
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2946389024
Short name	T804
Test name
Test status
Simulation time	12443467211 ps
CPU time	38.04 seconds
Started	Apr 21 12:26:38 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203308 kb
Host	smart-1a2b3902-8563-4ef0-948b-b46bc45a8108
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2946389024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2946389024
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3586250107
Short name	T193
Test name
Test status
Simulation time	32670830 ps
CPU time	2.26 seconds
Started	Apr 21 12:26:34 PM PDT 24
Finished	Apr 21 12:26:37 PM PDT 24
Peak memory	203216 kb
Host	smart-a47bafe8-896a-4f7a-856e-df9d211a439c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586250107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3586250107
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.1563269787
Short name	T77
Test name
Test status
Simulation time	17497403070 ps
CPU time	239.99 seconds
Started	Apr 21 12:26:40 PM PDT 24
Finished	Apr 21 12:30:41 PM PDT 24
Peak memory	207440 kb
Host	smart-99fc0240-fca3-4550-9313-e441e47ce6f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563269787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1563269787
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1508868498
Short name	T699
Test name
Test status
Simulation time	5304361984 ps
CPU time	130.89 seconds
Started	Apr 21 12:26:33 PM PDT 24
Finished	Apr 21 12:28:44 PM PDT 24
Peak memory	207008 kb
Host	smart-341cdb7e-2c78-488b-8fb1-a09e38546948
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508868498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1508868498
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.428907728
Short name	T694
Test name
Test status
Simulation time	100389432 ps
CPU time	14.74 seconds
Started	Apr 21 12:26:36 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	205716 kb
Host	smart-7c766925-9217-4275-a64a-883c1e779fce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=428907728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.428907728
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1825347806
Short name	T236
Test name
Test status
Simulation time	1704027447 ps
CPU time	16.53 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:27:16 PM PDT 24
Peak memory	211464 kb
Host	smart-e8aea65c-d9ed-4500-bbc8-add07e132e56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1825347806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1825347806
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.424832072
Short name	T472
Test name
Test status
Simulation time	83348124 ps
CPU time	3.55 seconds
Started	Apr 21 12:27:36 PM PDT 24
Finished	Apr 21 12:27:40 PM PDT 24
Peak memory	203228 kb
Host	smart-0a4fd23f-4620-421c-97b3-41b2e420c458
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424832072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.424832072
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2796496666
Short name	T421
Test name
Test status
Simulation time	76889169364 ps
CPU time	612.38 seconds
Started	Apr 21 12:28:07 PM PDT 24
Finished	Apr 21 12:38:20 PM PDT 24
Peak memory	211604 kb
Host	smart-89390d01-3ece-466c-9fda-a4f9729ec2ab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2796496666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2796496666
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1716335362
Short name	T841
Test name
Test status
Simulation time	234819307 ps
CPU time	8.35 seconds
Started	Apr 21 12:28:00 PM PDT 24
Finished	Apr 21 12:28:09 PM PDT 24
Peak memory	203244 kb
Host	smart-f7404443-3a02-4d31-ab31-a1abfef35091
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1716335362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1716335362
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.3921374619
Short name	T483
Test name
Test status
Simulation time	770216105 ps
CPU time	23.01 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	203372 kb
Host	smart-e9189eec-b694-4378-b94e-5e090276a610
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3921374619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3921374619
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.588946349
Short name	T181
Test name
Test status
Simulation time	860388421 ps
CPU time	27.98 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:19 PM PDT 24
Peak memory	211384 kb
Host	smart-98af1da2-0480-4e59-9111-593fb3f5c6a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588946349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.588946349
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.403341815
Short name	T598
Test name
Test status
Simulation time	15768858548 ps
CPU time	83.89 seconds
Started	Apr 21 12:27:53 PM PDT 24
Finished	Apr 21 12:29:17 PM PDT 24
Peak memory	211488 kb
Host	smart-b90c26fe-ca05-4bdf-8663-ba4fc774e688
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=403341815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.403341815
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1829305479
Short name	T378
Test name
Test status
Simulation time	240527360464 ps
CPU time	452.1 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:35:19 PM PDT 24
Peak memory	204516 kb
Host	smart-b9a5eaf6-12e5-43f1-b0e0-d149d8e3c6f0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1829305479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1829305479
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3416086718
Short name	T772
Test name
Test status
Simulation time	177887946 ps
CPU time	18.34 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:28:06 PM PDT 24
Peak memory	211436 kb
Host	smart-dd630354-9c8a-4b9e-90ab-4f6c34dc9115
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416086718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3416086718
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.313509274
Short name	T136
Test name
Test status
Simulation time	48119806 ps
CPU time	2.4 seconds
Started	Apr 21 12:27:37 PM PDT 24
Finished	Apr 21 12:27:41 PM PDT 24
Peak memory	203228 kb
Host	smart-4f069e59-2a41-4cb9-9b2f-663fc9dc45a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313509274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.313509274
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.2959063938
Short name	T639
Test name
Test status
Simulation time	29011034 ps
CPU time	2.15 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:27:48 PM PDT 24
Peak memory	203252 kb
Host	smart-0ee96374-6d24-4f67-b72f-567d758b5839
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2959063938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2959063938
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2458094603
Short name	T594
Test name
Test status
Simulation time	4726772433 ps
CPU time	31.68 seconds
Started	Apr 21 12:27:51 PM PDT 24
Finished	Apr 21 12:28:23 PM PDT 24
Peak memory	203416 kb
Host	smart-77030fb1-4af6-4376-9eb4-6fecff97ff4e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458094603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2458094603
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3838470345
Short name	T701
Test name
Test status
Simulation time	8842278614 ps
CPU time	31.8 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:28:19 PM PDT 24
Peak memory	203320 kb
Host	smart-1fc5efca-0317-44f6-81cc-3dda2a2445fd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3838470345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3838470345
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3583678538
Short name	T813
Test name
Test status
Simulation time	31860162 ps
CPU time	2.2 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:27:49 PM PDT 24
Peak memory	203244 kb
Host	smart-11c65c84-93d9-45ac-8abf-3622ca63347f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583678538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3583678538
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.2881198301
Short name	T636
Test name
Test status
Simulation time	1899315633 ps
CPU time	114.21 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:29:45 PM PDT 24
Peak memory	209120 kb
Host	smart-5d2e5625-ed9f-456c-9f5d-cb4a65934a5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2881198301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2881198301
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3433948011
Short name	T413
Test name
Test status
Simulation time	4101083454 ps
CPU time	67.58 seconds
Started	Apr 21 12:27:35 PM PDT 24
Finished	Apr 21 12:28:43 PM PDT 24
Peak memory	205544 kb
Host	smart-b855f604-251e-4a6a-a570-389c77015533
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3433948011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3433948011
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.461588282
Short name	T721
Test name
Test status
Simulation time	8833244805 ps
CPU time	185.59 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:30:57 PM PDT 24
Peak memory	210872 kb
Host	smart-e37cac38-45da-4566-9e44-7dd630f91ac9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=461588282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res et_error.461588282
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1998532516
Short name	T347
Test name
Test status
Simulation time	89375589 ps
CPU time	4.45 seconds
Started	Apr 21 12:27:44 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	211464 kb
Host	smart-e829974e-c79c-4827-a144-ba0ab3da0305
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1998532516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1998532516
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.603566760
Short name	T479
Test name
Test status
Simulation time	130850764 ps
CPU time	4.17 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:27:55 PM PDT 24
Peak memory	203368 kb
Host	smart-6811abbf-7195-4435-a759-8c7b89895976
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=603566760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.603566760
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.174417512
Short name	T449
Test name
Test status
Simulation time	68953608894 ps
CPU time	609.89 seconds
Started	Apr 21 12:28:00 PM PDT 24
Finished	Apr 21 12:38:10 PM PDT 24
Peak memory	211588 kb
Host	smart-8e05462f-85e1-4740-b93c-50067c6f06a7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=174417512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.174417512
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1763331598
Short name	T525
Test name
Test status
Simulation time	12090155 ps
CPU time	1.8 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:27:57 PM PDT 24
Peak memory	203256 kb
Host	smart-e9a42dbf-8eb4-4a2f-bb6d-d5c47574582c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1763331598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1763331598
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.1028073648
Short name	T864
Test name
Test status
Simulation time	579999696 ps
CPU time	16.96 seconds
Started	Apr 21 12:27:37 PM PDT 24
Finished	Apr 21 12:27:55 PM PDT 24
Peak memory	203372 kb
Host	smart-102d7ebc-2331-42b0-a8c2-c86fc8b991af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028073648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1028073648
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.2794436103
Short name	T295
Test name
Test status
Simulation time	149526916 ps
CPU time	5.5 seconds
Started	Apr 21 12:28:04 PM PDT 24
Finished	Apr 21 12:28:10 PM PDT 24
Peak memory	203236 kb
Host	smart-acc4e430-ecdf-4ae0-9217-cec853ac5f18
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2794436103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2794436103
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.4262931539
Short name	T105
Test name
Test status
Simulation time	38513484305 ps
CPU time	241.86 seconds
Started	Apr 21 12:27:41 PM PDT 24
Finished	Apr 21 12:31:43 PM PDT 24
Peak memory	211480 kb
Host	smart-047e0086-dcd3-4eea-a712-bdf4c4e28690
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262931539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4262931539
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1996169640
Short name	T540
Test name
Test status
Simulation time	28623365349 ps
CPU time	207.28 seconds
Started	Apr 21 12:27:40 PM PDT 24
Finished	Apr 21 12:31:09 PM PDT 24
Peak memory	204892 kb
Host	smart-ef35496a-8f68-41e7-976b-f453685b0317
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1996169640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1996169640
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1821268284
Short name	T297
Test name
Test status
Simulation time	210393597 ps
CPU time	24.54 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:15 PM PDT 24
Peak memory	204368 kb
Host	smart-f2090872-60c5-469e-a74e-119f7ee2c9c6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821268284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1821268284
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.216399759
Short name	T503
Test name
Test status
Simulation time	1277609001 ps
CPU time	16.39 seconds
Started	Apr 21 12:27:40 PM PDT 24
Finished	Apr 21 12:27:57 PM PDT 24
Peak memory	211416 kb
Host	smart-e445960e-7397-4fec-9802-5b679361de74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=216399759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.216399759
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.4215236705
Short name	T676
Test name
Test status
Simulation time	31656572 ps
CPU time	2.38 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	203544 kb
Host	smart-fbecce6e-4c9b-4dd3-a319-c429f0ac7d90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4215236705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4215236705
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1193275111
Short name	T354
Test name
Test status
Simulation time	7533859189 ps
CPU time	31.63 seconds
Started	Apr 21 12:27:51 PM PDT 24
Finished	Apr 21 12:28:24 PM PDT 24
Peak memory	203316 kb
Host	smart-d84addb9-21da-4a78-8ff5-46e0d74afae6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193275111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1193275111
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.987908762
Short name	T765
Test name
Test status
Simulation time	17159730113 ps
CPU time	44.58 seconds
Started	Apr 21 12:28:04 PM PDT 24
Finished	Apr 21 12:28:49 PM PDT 24
Peak memory	203384 kb
Host	smart-f27d4430-34bf-445d-b919-6d38fead4267
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=987908762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.987908762
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2060863678
Short name	T453
Test name
Test status
Simulation time	40778250 ps
CPU time	2.05 seconds
Started	Apr 21 12:27:32 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203284 kb
Host	smart-2bc178aa-74c6-4f49-adbb-55791bdf8880
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060863678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2060863678
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.127632501
Short name	T164
Test name
Test status
Simulation time	5717096872 ps
CPU time	110.54 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:29:39 PM PDT 24
Peak memory	206328 kb
Host	smart-c33161cd-06ac-4f73-a17b-5d7a24839672
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=127632501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.127632501
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2211139202
Short name	T406
Test name
Test status
Simulation time	4521690405 ps
CPU time	142.2 seconds
Started	Apr 21 12:28:02 PM PDT 24
Finished	Apr 21 12:30:25 PM PDT 24
Peak memory	208488 kb
Host	smart-83ef63ad-362c-4272-9f9b-588226d47978
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2211139202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2211139202
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2477702156
Short name	T203
Test name
Test status
Simulation time	2245937032 ps
CPU time	376.07 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:34:03 PM PDT 24
Peak memory	208072 kb
Host	smart-7ce1f753-3e13-4257-a85c-657f28bd6b09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2477702156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.2477702156
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1243097833
Short name	T24
Test name
Test status
Simulation time	6321886440 ps
CPU time	209.21 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:31:15 PM PDT 24
Peak memory	211332 kb
Host	smart-3a84a93a-cf14-4179-ba0f-899dc6bef0c1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1243097833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1243097833
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4210710851
Short name	T774
Test name
Test status
Simulation time	2230868528 ps
CPU time	30.48 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:28:20 PM PDT 24
Peak memory	211592 kb
Host	smart-f9bb29a0-1217-412c-bb87-115f23ab0019
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4210710851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4210710851
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.4096203095
Short name	T155
Test name
Test status
Simulation time	243854714 ps
CPU time	31.57 seconds
Started	Apr 21 12:27:46 PM PDT 24
Finished	Apr 21 12:28:19 PM PDT 24
Peak memory	204856 kb
Host	smart-10d76240-caf9-41b3-a130-8a065a99cfb2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096203095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.4096203095
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3869235729
Short name	T492
Test name
Test status
Simulation time	30908805 ps
CPU time	4.64 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	203368 kb
Host	smart-67589374-e864-467c-b221-a722175a3bb1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3869235729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3869235729
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.1534220580
Short name	T393
Test name
Test status
Simulation time	207105313 ps
CPU time	20.47 seconds
Started	Apr 21 12:27:35 PM PDT 24
Finished	Apr 21 12:27:55 PM PDT 24
Peak memory	203296 kb
Host	smart-674b1d1d-959b-45da-95d5-81978b975833
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1534220580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1534220580
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.911455518
Short name	T708
Test name
Test status
Simulation time	730918241 ps
CPU time	13.61 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:05 PM PDT 24
Peak memory	204364 kb
Host	smart-463003b0-7554-441a-8df6-9be92e5ab9bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=911455518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.911455518
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1380906137
Short name	T582
Test name
Test status
Simulation time	27864642303 ps
CPU time	113.87 seconds
Started	Apr 21 12:27:33 PM PDT 24
Finished	Apr 21 12:29:27 PM PDT 24
Peak memory	205124 kb
Host	smart-4a1fc459-cb2c-454f-bb28-a6f8dff94fe3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380906137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1380906137
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.320616349
Short name	T759
Test name
Test status
Simulation time	11858689730 ps
CPU time	57.35 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:28:51 PM PDT 24
Peak memory	211580 kb
Host	smart-1a045fbe-909a-4316-a998-b1e1a046f266
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=320616349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.320616349
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2814251331
Short name	T286
Test name
Test status
Simulation time	122659520 ps
CPU time	11.58 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:27:59 PM PDT 24
Peak memory	204580 kb
Host	smart-e54dfa43-cf9a-49d3-b330-2d7eee3cef15
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814251331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2814251331
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.1910235143
Short name	T583
Test name
Test status
Simulation time	1836869004 ps
CPU time	24.21 seconds
Started	Apr 21 12:27:56 PM PDT 24
Finished	Apr 21 12:28:26 PM PDT 24
Peak memory	203840 kb
Host	smart-1ec7f6dc-6699-4575-82cf-50ed21a9e0dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1910235143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1910235143
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.2490742134
Short name	T185
Test name
Test status
Simulation time	50741713 ps
CPU time	2.26 seconds
Started	Apr 21 12:27:59 PM PDT 24
Finished	Apr 21 12:28:02 PM PDT 24
Peak memory	203212 kb
Host	smart-db6198ec-d85d-456d-a3fc-27c5f52bb05d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2490742134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2490742134
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.704292768
Short name	T783
Test name
Test status
Simulation time	17048335963 ps
CPU time	41.57 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	203400 kb
Host	smart-4c013d5f-5e27-4ac7-8526-502c503a0c44
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=704292768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.704292768
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3236053686
Short name	T294
Test name
Test status
Simulation time	10006830661 ps
CPU time	40.04 seconds
Started	Apr 21 12:27:54 PM PDT 24
Finished	Apr 21 12:28:35 PM PDT 24
Peak memory	203592 kb
Host	smart-cccd9875-2b09-48d1-817e-3d71c0bdc6bf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3236053686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3236053686
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3361449
Short name	T621
Test name
Test status
Simulation time	48193000 ps
CPU time	2.29 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:27:51 PM PDT 24
Peak memory	203312 kb
Host	smart-5216a678-35f4-4b84-bcd8-61b9357ed5e5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3361449
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2080646043
Short name	T845
Test name
Test status
Simulation time	3711366432 ps
CPU time	117.29 seconds
Started	Apr 21 12:27:54 PM PDT 24
Finished	Apr 21 12:29:52 PM PDT 24
Peak memory	208112 kb
Host	smart-b945b1e9-ede4-464c-b9e6-a0d666772e25
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2080646043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2080646043
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3074897632
Short name	T250
Test name
Test status
Simulation time	282134333 ps
CPU time	119.49 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:29:47 PM PDT 24
Peak memory	208420 kb
Host	smart-b965efbb-643c-4ad8-aea9-4c2d2f533795
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3074897632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3074897632
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1217046040
Short name	T248
Test name
Test status
Simulation time	1013289393 ps
CPU time	23.34 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:28:17 PM PDT 24
Peak memory	204028 kb
Host	smart-a8971002-20b7-4543-a4b5-329549cd4efc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1217046040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1217046040
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.769106066
Short name	T154
Test name
Test status
Simulation time	86580018 ps
CPU time	8.96 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:27:58 PM PDT 24
Peak memory	211508 kb
Host	smart-978325b1-43b1-4639-b40b-e24c706b6541
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=769106066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.769106066
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.341458899
Short name	T618
Test name
Test status
Simulation time	252224239 ps
CPU time	17.9 seconds
Started	Apr 21 12:27:51 PM PDT 24
Finished	Apr 21 12:28:10 PM PDT 24
Peak memory	211492 kb
Host	smart-1864060a-a5e2-40bd-b8cf-477cb1f56cd5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=341458899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.341458899
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1557730559
Short name	T76
Test name
Test status
Simulation time	34154293649 ps
CPU time	261.19 seconds
Started	Apr 21 12:27:53 PM PDT 24
Finished	Apr 21 12:32:15 PM PDT 24
Peak memory	211620 kb
Host	smart-36f11bbb-d8ba-4cdf-98fe-aec91821829b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1557730559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1557730559
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.823908689
Short name	T717
Test name
Test status
Simulation time	653223816 ps
CPU time	16.82 seconds
Started	Apr 21 12:27:57 PM PDT 24
Finished	Apr 21 12:28:19 PM PDT 24
Peak memory	203608 kb
Host	smart-7433cd7d-3147-4163-a4d2-7afa5f5a005d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=823908689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.823908689
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.2653922131
Short name	T334
Test name
Test status
Simulation time	59317077 ps
CPU time	6.28 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	203360 kb
Host	smart-48476fd5-a9c1-46fe-9496-e30385878410
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2653922131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2653922131
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.4011257754
Short name	T897
Test name
Test status
Simulation time	405362542 ps
CPU time	21.56 seconds
Started	Apr 21 12:28:07 PM PDT 24
Finished	Apr 21 12:28:29 PM PDT 24
Peak memory	211504 kb
Host	smart-dd617af7-6386-4c01-9a1c-275b53bac655
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4011257754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4011257754
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.619771950
Short name	T142
Test name
Test status
Simulation time	18438622711 ps
CPU time	93.18 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:29:22 PM PDT 24
Peak memory	204664 kb
Host	smart-32175199-0313-4fa2-9970-57c3bd900df1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=619771950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.619771950
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2444676471
Short name	T494
Test name
Test status
Simulation time	4537806642 ps
CPU time	20.91 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:28:14 PM PDT 24
Peak memory	204320 kb
Host	smart-f14bafd4-0cc5-4ffe-a9c8-32c5271fbc78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2444676471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2444676471
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3549855619
Short name	T369
Test name
Test status
Simulation time	294008320 ps
CPU time	21.26 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:28:08 PM PDT 24
Peak memory	204340 kb
Host	smart-fe65cc19-5e45-47d2-83db-c853bfec842b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549855619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3549855619
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.2194029932
Short name	T281
Test name
Test status
Simulation time	231074329 ps
CPU time	5.79 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:27:54 PM PDT 24
Peak memory	203292 kb
Host	smart-ec394a1a-83a9-4b40-97e7-1c81811a526f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2194029932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2194029932
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.1891293465
Short name	T792
Test name
Test status
Simulation time	352978563 ps
CPU time	3.36 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:28:01 PM PDT 24
Peak memory	203340 kb
Host	smart-638c1686-e561-4b98-a1eb-a5e11eea690b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1891293465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1891293465
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.878037978
Short name	T519
Test name
Test status
Simulation time	5571051226 ps
CPU time	30.73 seconds
Started	Apr 21 12:27:56 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	203392 kb
Host	smart-94500e7b-83d7-4736-ac91-3ef93bd2e1b4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=878037978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.878037978
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3403882097
Short name	T59
Test name
Test status
Simulation time	4592414310 ps
CPU time	22.12 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	203376 kb
Host	smart-9b7c5d2e-93cc-4884-af73-5524eceec489
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3403882097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3403882097
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.318960045
Short name	T840
Test name
Test status
Simulation time	86585208 ps
CPU time	1.9 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:27:51 PM PDT 24
Peak memory	203232 kb
Host	smart-db09a6da-7fcb-4a3b-9f90-457207ec76fb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318960045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.318960045
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.4217511109
Short name	T448
Test name
Test status
Simulation time	4651880987 ps
CPU time	105.27 seconds
Started	Apr 21 12:27:45 PM PDT 24
Finished	Apr 21 12:29:32 PM PDT 24
Peak memory	208744 kb
Host	smart-d39313c5-623c-4ede-bb5f-b904bbdd31eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4217511109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4217511109
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2956869654
Short name	T156
Test name
Test status
Simulation time	221803197 ps
CPU time	23.73 seconds
Started	Apr 21 12:28:02 PM PDT 24
Finished	Apr 21 12:28:26 PM PDT 24
Peak memory	204472 kb
Host	smart-178dda7f-f455-4f2f-82ab-8434de5d2ccb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2956869654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2956869654
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1124452927
Short name	T82
Test name
Test status
Simulation time	563882889 ps
CPU time	17.15 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:08 PM PDT 24
Peak memory	211440 kb
Host	smart-a71a869a-8ed8-4ffb-9386-aa51da807375
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1124452927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1124452927
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1829825887
Short name	T19
Test name
Test status
Simulation time	1925961246 ps
CPU time	41.11 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:28:29 PM PDT 24
Peak memory	211540 kb
Host	smart-c9998441-61f3-4328-9316-63a142d191b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1829825887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1829825887
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4227619544
Short name	T782
Test name
Test status
Simulation time	47740234804 ps
CPU time	356.53 seconds
Started	Apr 21 12:27:57 PM PDT 24
Finished	Apr 21 12:33:54 PM PDT 24
Peak memory	206380 kb
Host	smart-9c3b629f-7480-4b9c-bfab-7431f63f5865
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4227619544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.4227619544
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3455374263
Short name	T827
Test name
Test status
Simulation time	679575337 ps
CPU time	22.8 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	203300 kb
Host	smart-7b8f6ef0-3a15-4808-a732-b08a760d2a53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3455374263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3455374263
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.3981093542
Short name	T261
Test name
Test status
Simulation time	317219306 ps
CPU time	8.81 seconds
Started	Apr 21 12:27:57 PM PDT 24
Finished	Apr 21 12:28:11 PM PDT 24
Peak memory	203280 kb
Host	smart-0b372006-342f-473c-9349-9e871b2cb872
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3981093542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3981093542
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.850503824
Short name	T275
Test name
Test status
Simulation time	210520898 ps
CPU time	3.1 seconds
Started	Apr 21 12:27:53 PM PDT 24
Finished	Apr 21 12:27:57 PM PDT 24
Peak memory	203352 kb
Host	smart-c989ade5-ecd6-405e-a5a8-a4c40e94bd34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=850503824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.850503824
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4235788663
Short name	T656
Test name
Test status
Simulation time	16101141875 ps
CPU time	96.43 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:29:29 PM PDT 24
Peak memory	211484 kb
Host	smart-37f4816d-abac-4eb6-b6b6-d0944a8fed2e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235788663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4235788663
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2505142823
Short name	T575
Test name
Test status
Simulation time	3394499440 ps
CPU time	27.7 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:19 PM PDT 24
Peak memory	204016 kb
Host	smart-e42e2216-e9b7-44b1-8123-b150e8818a39
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2505142823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2505142823
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.467810870
Short name	T644
Test name
Test status
Simulation time	289361183 ps
CPU time	12.29 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:03 PM PDT 24
Peak memory	211524 kb
Host	smart-635656ce-a8a2-4a81-8f5f-c2bf76e9b1ed
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467810870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.467810870
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.1200658815
Short name	T258
Test name
Test status
Simulation time	481321609 ps
CPU time	10.62 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:01 PM PDT 24
Peak memory	203280 kb
Host	smart-aaa6e5bd-442b-4dd0-91e7-cb5f41bc90e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1200658815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1200658815
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.2330986819
Short name	T707
Test name
Test status
Simulation time	219352424 ps
CPU time	3.42 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	203248 kb
Host	smart-51192733-33eb-47ae-be69-dd2bbf1fe452
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2330986819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2330986819
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.338539863
Short name	T309
Test name
Test status
Simulation time	7609658665 ps
CPU time	36.14 seconds
Started	Apr 21 12:27:51 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	203416 kb
Host	smart-2eb7c876-1d0c-46f6-bf25-f17462e874c6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=338539863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.338539863
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.104216676
Short name	T422
Test name
Test status
Simulation time	7614738105 ps
CPU time	26.82 seconds
Started	Apr 21 12:27:50 PM PDT 24
Finished	Apr 21 12:28:18 PM PDT 24
Peak memory	203304 kb
Host	smart-5ba52c31-b2b2-4de2-acb3-71e48015da5b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=104216676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.104216676
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.475425202
Short name	T270
Test name
Test status
Simulation time	26854414 ps
CPU time	2.45 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:27:53 PM PDT 24
Peak memory	203220 kb
Host	smart-fd629d00-90ff-49a9-bf23-84d46f3b7825
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475425202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.475425202
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.3865085371
Short name	T126
Test name
Test status
Simulation time	6822548273 ps
CPU time	136.86 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:30:06 PM PDT 24
Peak memory	208992 kb
Host	smart-c5464fc4-429a-482b-a110-9460955c1674
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3865085371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3865085371
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1940612848
Short name	T637
Test name
Test status
Simulation time	597241880 ps
CPU time	194.51 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:31:07 PM PDT 24
Peak memory	208312 kb
Host	smart-dc2a530c-7d87-4eb8-bc4c-abc690d23fa8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1940612848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1940612848
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3719311292
Short name	T863
Test name
Test status
Simulation time	2048270029 ps
CPU time	121.44 seconds
Started	Apr 21 12:28:03 PM PDT 24
Finished	Apr 21 12:30:04 PM PDT 24
Peak memory	210240 kb
Host	smart-8cb97b9e-e534-42a6-b736-bff8149881a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3719311292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.3719311292
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2357046645
Short name	T47
Test name
Test status
Simulation time	1196139133 ps
CPU time	9.35 seconds
Started	Apr 21 12:27:58 PM PDT 24
Finished	Apr 21 12:28:07 PM PDT 24
Peak memory	211424 kb
Host	smart-21fd50cc-1cbe-4611-9604-86b9100f267e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2357046645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2357046645
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.562220819
Short name	T135
Test name
Test status
Simulation time	170697637 ps
CPU time	20.46 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:11 PM PDT 24
Peak memory	211540 kb
Host	smart-d2180060-1dc9-483f-acb1-de52d5947a7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=562220819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.562220819
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2773565434
Short name	T642
Test name
Test status
Simulation time	307369579482 ps
CPU time	678.48 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:39:11 PM PDT 24
Peak memory	207408 kb
Host	smart-228cb512-ee16-4052-af3e-9c9446c8f8ca
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2773565434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2773565434
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1017017409
Short name	T150
Test name
Test status
Simulation time	827860279 ps
CPU time	5.57 seconds
Started	Apr 21 12:28:05 PM PDT 24
Finished	Apr 21 12:28:11 PM PDT 24
Peak memory	203456 kb
Host	smart-c436e423-64a2-4222-ade3-e5b45216300d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1017017409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1017017409
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.2475748138
Short name	T558
Test name
Test status
Simulation time	564838602 ps
CPU time	18 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:28:14 PM PDT 24
Peak memory	203284 kb
Host	smart-443a0053-76a8-43fd-b3d2-3124fd027cb1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2475748138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2475748138
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.39787040
Short name	T743
Test name
Test status
Simulation time	1095695588 ps
CPU time	19.66 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	211436 kb
Host	smart-aa6c90c3-c68d-4ce1-90f0-adb2875cb795
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=39787040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.39787040
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.240945633
Short name	T151
Test name
Test status
Simulation time	53214959812 ps
CPU time	141.34 seconds
Started	Apr 21 12:28:00 PM PDT 24
Finished	Apr 21 12:30:22 PM PDT 24
Peak memory	204636 kb
Host	smart-4f8ba50f-56a4-4357-bebf-ebe9eaafa48b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=240945633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.240945633
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2043761759
Short name	T793
Test name
Test status
Simulation time	17278882063 ps
CPU time	111.48 seconds
Started	Apr 21 12:27:59 PM PDT 24
Finished	Apr 21 12:29:51 PM PDT 24
Peak memory	211564 kb
Host	smart-d8615fc1-f8fb-42ff-8929-62a6fb53602b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2043761759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2043761759
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.218266394
Short name	T539
Test name
Test status
Simulation time	323203334 ps
CPU time	25.05 seconds
Started	Apr 21 12:27:48 PM PDT 24
Finished	Apr 21 12:28:15 PM PDT 24
Peak memory	211440 kb
Host	smart-a6cbf794-b44c-4222-a6b1-f7d484ed232c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218266394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.218266394
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.1575371675
Short name	T348
Test name
Test status
Simulation time	252553185 ps
CPU time	4.83 seconds
Started	Apr 21 12:28:04 PM PDT 24
Finished	Apr 21 12:28:09 PM PDT 24
Peak memory	203252 kb
Host	smart-a2d5c143-10ba-4659-8118-876b6bfb0820
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1575371675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1575371675
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.3325957092
Short name	T50
Test name
Test status
Simulation time	803002223 ps
CPU time	3.41 seconds
Started	Apr 21 12:28:10 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	203336 kb
Host	smart-36d8d178-5002-49d1-b0cb-824f188e4a50
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3325957092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3325957092
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2350016733
Short name	T186
Test name
Test status
Simulation time	33446367835 ps
CPU time	43.78 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:28:41 PM PDT 24
Peak memory	203404 kb
Host	smart-7691cbff-2c24-4564-8677-8ed1587eae32
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350016733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2350016733
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2088410317
Short name	T168
Test name
Test status
Simulation time	26781720863 ps
CPU time	58.52 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:28:49 PM PDT 24
Peak memory	203404 kb
Host	smart-c4f259f7-7cd0-4478-b234-6504e4283c9d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2088410317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2088410317
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1633381886
Short name	T130
Test name
Test status
Simulation time	60430235 ps
CPU time	2.07 seconds
Started	Apr 21 12:27:49 PM PDT 24
Finished	Apr 21 12:27:52 PM PDT 24
Peak memory	203236 kb
Host	smart-9096601b-4d1d-4c7f-832a-6a0f35d28381
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633381886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1633381886
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.4139901467
Short name	T510
Test name
Test status
Simulation time	1166335862 ps
CPU time	17.24 seconds
Started	Apr 21 12:27:47 PM PDT 24
Finished	Apr 21 12:28:05 PM PDT 24
Peak memory	205120 kb
Host	smart-9af46495-7fb7-43d1-911a-b152945f232a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4139901467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4139901467
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.820561439
Short name	T377
Test name
Test status
Simulation time	4015369372 ps
CPU time	141.86 seconds
Started	Apr 21 12:27:53 PM PDT 24
Finished	Apr 21 12:30:15 PM PDT 24
Peak memory	208548 kb
Host	smart-001d0a5a-30a4-4167-9a82-d25ff72b817f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=820561439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.820561439
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4177085107
Short name	T828
Test name
Test status
Simulation time	1147072131 ps
CPU time	150.79 seconds
Started	Apr 21 12:28:05 PM PDT 24
Finished	Apr 21 12:30:36 PM PDT 24
Peak memory	209092 kb
Host	smart-6b57c12a-eb5e-4be0-b7fe-9683c325a4b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4177085107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.4177085107
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.4168263306
Short name	T240
Test name
Test status
Simulation time	600697926 ps
CPU time	128.56 seconds
Started	Apr 21 12:27:58 PM PDT 24
Finished	Apr 21 12:30:07 PM PDT 24
Peak memory	209908 kb
Host	smart-8da1a34a-c9ea-468f-90e7-ae4b5b953861
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4168263306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.4168263306
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.4145050539
Short name	T447
Test name
Test status
Simulation time	2078741991 ps
CPU time	28.2 seconds
Started	Apr 21 12:28:09 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	204896 kb
Host	smart-49a71533-ee95-4c95-aabe-371d8cfd6a48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145050539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4145050539
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2000267858
Short name	T133
Test name
Test status
Simulation time	26536210 ps
CPU time	5.09 seconds
Started	Apr 21 12:27:59 PM PDT 24
Finished	Apr 21 12:28:05 PM PDT 24
Peak memory	211440 kb
Host	smart-19d79ee0-0d5a-4984-847e-3c9322ac2d2c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2000267858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2000267858
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2004692545
Short name	T299
Test name
Test status
Simulation time	5293557294 ps
CPU time	41.85 seconds
Started	Apr 21 12:28:04 PM PDT 24
Finished	Apr 21 12:28:46 PM PDT 24
Peak memory	211468 kb
Host	smart-34cfedeb-d052-48b3-b612-65e84e1bc6b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2004692545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.2004692545
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3620575583
Short name	T265
Test name
Test status
Simulation time	427656189 ps
CPU time	8.61 seconds
Started	Apr 21 12:28:08 PM PDT 24
Finished	Apr 21 12:28:17 PM PDT 24
Peak memory	203668 kb
Host	smart-e7998b6d-f91f-4334-9aea-02210f143484
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3620575583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3620575583
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.2043692621
Short name	T803
Test name
Test status
Simulation time	734250156 ps
CPU time	4.33 seconds
Started	Apr 21 12:27:51 PM PDT 24
Finished	Apr 21 12:27:56 PM PDT 24
Peak memory	203268 kb
Host	smart-d6b49a91-7847-483f-b406-b4df47cefc1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2043692621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2043692621
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.218184688
Short name	T398
Test name
Test status
Simulation time	183003086 ps
CPU time	19.05 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:33 PM PDT 24
Peak memory	211536 kb
Host	smart-a785e00e-45d1-42e6-bc31-0d47aca27cc2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=218184688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.218184688
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1938925389
Short name	T884
Test name
Test status
Simulation time	80839888892 ps
CPU time	212.21 seconds
Started	Apr 21 12:29:10 PM PDT 24
Finished	Apr 21 12:32:43 PM PDT 24
Peak memory	211040 kb
Host	smart-dbcc2934-9fd0-4b21-a0a2-347a1613b806
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938925389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1938925389
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3922489842
Short name	T194
Test name
Test status
Simulation time	4357606930 ps
CPU time	27.2 seconds
Started	Apr 21 12:27:56 PM PDT 24
Finished	Apr 21 12:28:24 PM PDT 24
Peak memory	204512 kb
Host	smart-ec88aeba-f6fa-49a7-a47e-fa2a186c968e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3922489842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3922489842
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1625439869
Short name	T662
Test name
Test status
Simulation time	53482374 ps
CPU time	4.81 seconds
Started	Apr 21 12:27:54 PM PDT 24
Finished	Apr 21 12:27:59 PM PDT 24
Peak memory	204308 kb
Host	smart-9b52e6af-1122-4136-a738-c1d28547086b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625439869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1625439869
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2964367910
Short name	T800
Test name
Test status
Simulation time	1438607472 ps
CPU time	19.39 seconds
Started	Apr 21 12:27:52 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	203412 kb
Host	smart-ed2085a5-74f7-439a-b642-6da4a24e75c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964367910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2964367910
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.3347714001
Short name	T383
Test name
Test status
Simulation time	173252563 ps
CPU time	3.17 seconds
Started	Apr 21 12:29:11 PM PDT 24
Finished	Apr 21 12:29:14 PM PDT 24
Peak memory	202868 kb
Host	smart-73df70ca-dc41-411e-b925-7347a12ecb31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347714001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3347714001
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3352356490
Short name	T403
Test name
Test status
Simulation time	7023408880 ps
CPU time	37.31 seconds
Started	Apr 21 12:27:58 PM PDT 24
Finished	Apr 21 12:28:35 PM PDT 24
Peak memory	203300 kb
Host	smart-923f8019-6bf3-40c0-bb58-45393fc1a7ab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352356490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3352356490
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2115686432
Short name	T335
Test name
Test status
Simulation time	7836293415 ps
CPU time	32.99 seconds
Started	Apr 21 12:28:02 PM PDT 24
Finished	Apr 21 12:28:36 PM PDT 24
Peak memory	203324 kb
Host	smart-68a2d1bc-7f56-4f42-860d-04aa7ea63fe0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2115686432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2115686432
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.291993604
Short name	T862
Test name
Test status
Simulation time	58725704 ps
CPU time	2.55 seconds
Started	Apr 21 12:29:09 PM PDT 24
Finished	Apr 21 12:29:13 PM PDT 24
Peak memory	200644 kb
Host	smart-ca7e84ad-8b77-4320-b98e-12028c988f67
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291993604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.291993604
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.1399744676
Short name	T825
Test name
Test status
Simulation time	1368628725 ps
CPU time	100.53 seconds
Started	Apr 21 12:29:23 PM PDT 24
Finished	Apr 21 12:31:04 PM PDT 24
Peak memory	211296 kb
Host	smart-759c34eb-b3ef-485c-98dd-295b7a8163e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399744676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1399744676
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.829877180
Short name	T776
Test name
Test status
Simulation time	19058718106 ps
CPU time	280.69 seconds
Started	Apr 21 12:29:10 PM PDT 24
Finished	Apr 21 12:33:51 PM PDT 24
Peak memory	211764 kb
Host	smart-ccc30949-71ea-4643-bec4-8a0055da37e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=829877180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.829877180
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3746173033
Short name	T812
Test name
Test status
Simulation time	4367803958 ps
CPU time	88.49 seconds
Started	Apr 21 12:29:10 PM PDT 24
Finished	Apr 21 12:30:39 PM PDT 24
Peak memory	208804 kb
Host	smart-03eab6d7-0941-4aff-b097-6d812a91ef28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3746173033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.3746173033
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1524104921
Short name	T626
Test name
Test status
Simulation time	64037701 ps
CPU time	8.22 seconds
Started	Apr 21 12:29:09 PM PDT 24
Finished	Apr 21 12:29:18 PM PDT 24
Peak memory	202596 kb
Host	smart-6e767b34-c86e-4263-8f1f-b2d298e9d506
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1524104921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1524104921
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1622409264
Short name	T79
Test name
Test status
Simulation time	1281592741 ps
CPU time	55.4 seconds
Started	Apr 21 12:27:58 PM PDT 24
Finished	Apr 21 12:28:54 PM PDT 24
Peak memory	211456 kb
Host	smart-e38e3809-5c0a-45e0-8547-7b9de3a72f0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1622409264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1622409264
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.642858593
Short name	T107
Test name
Test status
Simulation time	69255245411 ps
CPU time	595.9 seconds
Started	Apr 21 12:28:07 PM PDT 24
Finished	Apr 21 12:38:03 PM PDT 24
Peak memory	211456 kb
Host	smart-74e7b714-4793-4fb0-8f48-2cd4c576a5e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=642858593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo w_rsp.642858593
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1921863758
Short name	T550
Test name
Test status
Simulation time	169350796 ps
CPU time	18.12 seconds
Started	Apr 21 12:28:02 PM PDT 24
Finished	Apr 21 12:28:21 PM PDT 24
Peak memory	203304 kb
Host	smart-760915fd-3975-40d8-9497-42f7f1f227c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1921863758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1921863758
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.3224268822
Short name	T317
Test name
Test status
Simulation time	471400153 ps
CPU time	14.27 seconds
Started	Apr 21 12:28:02 PM PDT 24
Finished	Apr 21 12:28:16 PM PDT 24
Peak memory	203360 kb
Host	smart-493d43ba-5c2f-4228-9564-31a086c136f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3224268822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3224268822
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.1823909713
Short name	T872
Test name
Test status
Simulation time	365166150 ps
CPU time	20.75 seconds
Started	Apr 21 12:27:53 PM PDT 24
Finished	Apr 21 12:28:14 PM PDT 24
Peak memory	204720 kb
Host	smart-6465bff4-0f26-47d3-ae93-c2e9c45ea17f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1823909713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1823909713
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3326638056
Short name	T376
Test name
Test status
Simulation time	71366178936 ps
CPU time	157.4 seconds
Started	Apr 21 12:28:04 PM PDT 24
Finished	Apr 21 12:30:42 PM PDT 24
Peak memory	204556 kb
Host	smart-51418cd8-38c4-4be2-a980-ac4c13f5d34d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326638056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3326638056
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.4241634943
Short name	T22
Test name
Test status
Simulation time	46625174892 ps
CPU time	259.16 seconds
Started	Apr 21 12:29:23 PM PDT 24
Finished	Apr 21 12:33:42 PM PDT 24
Peak memory	211340 kb
Host	smart-5e9e13ff-faea-4cf3-9257-f9fd86aafba5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4241634943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.4241634943
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.419860270
Short name	T809
Test name
Test status
Simulation time	163515068 ps
CPU time	20.46 seconds
Started	Apr 21 12:27:57 PM PDT 24
Finished	Apr 21 12:28:18 PM PDT 24
Peak memory	204596 kb
Host	smart-eebe3d2f-7384-4d7c-aa2b-b557073f7246
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419860270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.419860270
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.2035854657
Short name	T42
Test name
Test status
Simulation time	862476764 ps
CPU time	8.22 seconds
Started	Apr 21 12:28:08 PM PDT 24
Finished	Apr 21 12:28:16 PM PDT 24
Peak memory	203792 kb
Host	smart-8a2c99fc-d878-42f6-8f28-1f1537652146
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2035854657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2035854657
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.678328173
Short name	T63
Test name
Test status
Simulation time	882669478 ps
CPU time	4.15 seconds
Started	Apr 21 12:29:09 PM PDT 24
Finished	Apr 21 12:29:14 PM PDT 24
Peak memory	201168 kb
Host	smart-07b1393d-a6e9-4c15-b164-9a5ab0863233
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=678328173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.678328173
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2586273003
Short name	T742
Test name
Test status
Simulation time	5446516283 ps
CPU time	30.79 seconds
Started	Apr 21 12:27:54 PM PDT 24
Finished	Apr 21 12:28:26 PM PDT 24
Peak memory	203316 kb
Host	smart-127c087a-18e1-466b-b7a1-a46ee017df48
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586273003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2586273003
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3126095428
Short name	T72
Test name
Test status
Simulation time	13007694262 ps
CPU time	32.03 seconds
Started	Apr 21 12:27:54 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	203332 kb
Host	smart-d3b6be51-cf8a-48a0-8540-ab284dfd4860
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3126095428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3126095428
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1483973413
Short name	T692
Test name
Test status
Simulation time	57672002 ps
CPU time	1.99 seconds
Started	Apr 21 12:27:57 PM PDT 24
Finished	Apr 21 12:27:59 PM PDT 24
Peak memory	203252 kb
Host	smart-339b5c45-e238-49fd-aa23-5ad6e09ca27c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483973413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1483973413
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.265879852
Short name	T162
Test name
Test status
Simulation time	8364016487 ps
CPU time	90.98 seconds
Started	Apr 21 12:29:23 PM PDT 24
Finished	Apr 21 12:30:54 PM PDT 24
Peak memory	206096 kb
Host	smart-634c7ca0-2ac1-4ec5-ba0b-139807c16d01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=265879852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.265879852
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1475378968
Short name	T465
Test name
Test status
Simulation time	156701090 ps
CPU time	11.45 seconds
Started	Apr 21 12:29:09 PM PDT 24
Finished	Apr 21 12:29:21 PM PDT 24
Peak memory	200584 kb
Host	smart-89bac482-1224-4641-9139-98a0c3454ee5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1475378968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1475378968
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.863374721
Short name	T235
Test name
Test status
Simulation time	593327032 ps
CPU time	192.8 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:31:31 PM PDT 24
Peak memory	209036 kb
Host	smart-6e518e7e-5b59-4b6c-86f8-2cc929cbc4db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863374721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.863374721
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1956256702
Short name	T242
Test name
Test status
Simulation time	241074228 ps
CPU time	134.56 seconds
Started	Apr 21 12:27:59 PM PDT 24
Finished	Apr 21 12:30:14 PM PDT 24
Peak memory	210016 kb
Host	smart-70ebb4da-58a0-4107-ae84-e9ef66d9b2a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1956256702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1956256702
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2895617135
Short name	T158
Test name
Test status
Simulation time	909682545 ps
CPU time	17.2 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:28:13 PM PDT 24
Peak memory	204800 kb
Host	smart-2d933246-954b-4614-a15e-52271c06a101
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2895617135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2895617135
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2672667931
Short name	T785
Test name
Test status
Simulation time	192137798 ps
CPU time	11.63 seconds
Started	Apr 21 12:28:08 PM PDT 24
Finished	Apr 21 12:28:20 PM PDT 24
Peak memory	203376 kb
Host	smart-32a84eb5-5657-42d7-8859-6772db8a1359
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2672667931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2672667931
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1913628750
Short name	T488
Test name
Test status
Simulation time	37424119176 ps
CPU time	180.36 seconds
Started	Apr 21 12:27:55 PM PDT 24
Finished	Apr 21 12:30:56 PM PDT 24
Peak memory	211484 kb
Host	smart-3ff8ff25-0eb1-4af1-9ea4-d51bdd3c3af1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1913628750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1913628750
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.96236130
Short name	T600
Test name
Test status
Simulation time	265856645 ps
CPU time	7.57 seconds
Started	Apr 21 12:28:14 PM PDT 24
Finished	Apr 21 12:28:22 PM PDT 24
Peak memory	203512 kb
Host	smart-05c475b1-500b-4555-80a5-2e68287d2a5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=96236130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.96236130
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.2650835116
Short name	T5
Test name
Test status
Simulation time	202562288 ps
CPU time	8.28 seconds
Started	Apr 21 12:28:16 PM PDT 24
Finished	Apr 21 12:28:25 PM PDT 24
Peak memory	203252 kb
Host	smart-9de6f8ab-f5db-4dae-a3d6-b7c54b7eee90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2650835116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2650835116
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.945008374
Short name	T427
Test name
Test status
Simulation time	94521711 ps
CPU time	12.21 seconds
Started	Apr 21 12:28:17 PM PDT 24
Finished	Apr 21 12:28:29 PM PDT 24
Peak memory	204472 kb
Host	smart-72ee3f15-62ed-4182-80dd-532b07cebb25
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=945008374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.945008374
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.92932712
Short name	T108
Test name
Test status
Simulation time	148486440671 ps
CPU time	305.27 seconds
Started	Apr 21 12:27:59 PM PDT 24
Finished	Apr 21 12:33:05 PM PDT 24
Peak memory	211604 kb
Host	smart-0ca7c6a7-7f56-404f-b435-ba805e2833ea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=92932712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.92932712
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1041715585
Short name	T439
Test name
Test status
Simulation time	14259774277 ps
CPU time	135.37 seconds
Started	Apr 21 12:28:06 PM PDT 24
Finished	Apr 21 12:30:22 PM PDT 24
Peak memory	211592 kb
Host	smart-e99b9ee4-bb4d-4ba7-8008-9924d2d84a10
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1041715585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1041715585
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1753888712
Short name	T346
Test name
Test status
Simulation time	99664440 ps
CPU time	10.16 seconds
Started	Apr 21 12:28:10 PM PDT 24
Finished	Apr 21 12:28:21 PM PDT 24
Peak memory	211516 kb
Host	smart-761fa12f-aa90-459d-809f-6a6fa3cee9aa
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753888712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1753888712
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.723438883
Short name	T771
Test name
Test status
Simulation time	68806987 ps
CPU time	4.31 seconds
Started	Apr 21 12:28:00 PM PDT 24
Finished	Apr 21 12:28:05 PM PDT 24
Peak memory	203368 kb
Host	smart-e21ca154-d4d7-40db-8e73-0cb4fc75ebf9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=723438883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.723438883
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.2124662867
Short name	T630
Test name
Test status
Simulation time	47839458 ps
CPU time	2.55 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:23 PM PDT 24
Peak memory	203244 kb
Host	smart-e617d820-7400-4d86-addf-d0448d4cae27
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2124662867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2124662867
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.4217497579
Short name	T307
Test name
Test status
Simulation time	15171980851 ps
CPU time	30 seconds
Started	Apr 21 12:28:02 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	203408 kb
Host	smart-ff4e6e9f-4a2f-4263-8c21-abad65f4062b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217497579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.4217497579
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.902577437
Short name	T318
Test name
Test status
Simulation time	4680026336 ps
CPU time	36.33 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:50 PM PDT 24
Peak memory	203416 kb
Host	smart-e42fc51f-2c52-4ea3-aa2e-8245ba230982
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=902577437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.902577437
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2041837679
Short name	T371
Test name
Test status
Simulation time	42070277 ps
CPU time	2.46 seconds
Started	Apr 21 12:28:01 PM PDT 24
Finished	Apr 21 12:28:04 PM PDT 24
Peak memory	203340 kb
Host	smart-8ae72ac6-7bad-4680-9f1a-808fcbe4cb6d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041837679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2041837679
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.3012415662
Short name	T220
Test name
Test status
Simulation time	1873553737 ps
CPU time	75.82 seconds
Started	Apr 21 12:28:08 PM PDT 24
Finished	Apr 21 12:29:25 PM PDT 24
Peak memory	206284 kb
Host	smart-517fc3a5-7d25-47aa-9faa-cc5f7d3c9c6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3012415662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3012415662
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2939589313
Short name	T314
Test name
Test status
Simulation time	6781920933 ps
CPU time	218.49 seconds
Started	Apr 21 12:27:59 PM PDT 24
Finished	Apr 21 12:31:48 PM PDT 24
Peak memory	211556 kb
Host	smart-afe9b799-8a4f-4942-a302-2616091da00b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2939589313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2939589313
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2181668478
Short name	T547
Test name
Test status
Simulation time	7364745585 ps
CPU time	193.15 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:31:26 PM PDT 24
Peak memory	209148 kb
Host	smart-517dc5a7-996b-4e8b-ac3c-453a09c4b1cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2181668478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2181668478
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3503120493
Short name	T249
Test name
Test status
Simulation time	402754702 ps
CPU time	136.58 seconds
Started	Apr 21 12:28:09 PM PDT 24
Finished	Apr 21 12:30:26 PM PDT 24
Peak memory	210216 kb
Host	smart-bfa11ea0-d007-44bc-b8fb-1ec41148ba91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3503120493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.3503120493
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2974637332
Short name	T2
Test name
Test status
Simulation time	174608585 ps
CPU time	8.39 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	211404 kb
Host	smart-91b2d297-087a-4334-a96f-3cd116ee7814
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2974637332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2974637332
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1829482391
Short name	T432
Test name
Test status
Simulation time	732815319 ps
CPU time	29.91 seconds
Started	Apr 21 12:28:03 PM PDT 24
Finished	Apr 21 12:28:33 PM PDT 24
Peak memory	204244 kb
Host	smart-954c609d-f2ec-463f-a4b2-3b620a2247bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1829482391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1829482391
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3217275440
Short name	T593
Test name
Test status
Simulation time	133261005829 ps
CPU time	273.18 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:32:52 PM PDT 24
Peak memory	211504 kb
Host	smart-dbb14bcd-8528-4fcd-9086-1592f538733e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3217275440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3217275440
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.4200630913
Short name	T650
Test name
Test status
Simulation time	621244740 ps
CPU time	3.8 seconds
Started	Apr 21 12:28:07 PM PDT 24
Finished	Apr 21 12:28:11 PM PDT 24
Peak memory	203268 kb
Host	smart-8d776631-d4b7-4e05-9ee4-f24f6e0df9b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4200630913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.4200630913
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.531552043
Short name	T522
Test name
Test status
Simulation time	258679820 ps
CPU time	8.68 seconds
Started	Apr 21 12:28:03 PM PDT 24
Finished	Apr 21 12:28:18 PM PDT 24
Peak memory	203252 kb
Host	smart-126668a8-657f-4624-b5fb-64282ecfd24b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=531552043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.531552043
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.3039208978
Short name	T553
Test name
Test status
Simulation time	762917832 ps
CPU time	14.79 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:28:33 PM PDT 24
Peak memory	204604 kb
Host	smart-28749497-e4bf-442e-81ff-55e8e04b274c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3039208978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3039208978
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.4007369158
Short name	T568
Test name
Test status
Simulation time	51460609420 ps
CPU time	224.12 seconds
Started	Apr 21 12:28:09 PM PDT 24
Finished	Apr 21 12:31:53 PM PDT 24
Peak memory	211792 kb
Host	smart-dc75c694-1726-4c78-9b89-1772b2301a0b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007369158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.4007369158
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1061783027
Short name	T754
Test name
Test status
Simulation time	36475134758 ps
CPU time	217.09 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:31:58 PM PDT 24
Peak memory	204624 kb
Host	smart-c6b31ec9-87f0-4d86-b549-444e310eccf5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1061783027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1061783027
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2526368028
Short name	T464
Test name
Test status
Simulation time	20551547 ps
CPU time	2.11 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:28:15 PM PDT 24
Peak memory	203348 kb
Host	smart-fa8c53ba-2464-46a1-a5b7-c1878129ec45
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526368028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2526368028
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.3484564378
Short name	T234
Test name
Test status
Simulation time	5022877712 ps
CPU time	32.76 seconds
Started	Apr 21 12:28:15 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	211588 kb
Host	smart-d3869052-0698-41c6-af16-c74450ec3c08
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484564378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3484564378
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.376360161
Short name	T172
Test name
Test status
Simulation time	32628211 ps
CPU time	2.3 seconds
Started	Apr 21 12:28:08 PM PDT 24
Finished	Apr 21 12:28:11 PM PDT 24
Peak memory	203280 kb
Host	smart-fcd72e1b-24d4-44d4-80a1-b45a31a02f2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=376360161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.376360161
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2762463022
Short name	T573
Test name
Test status
Simulation time	5526451273 ps
CPU time	33.13 seconds
Started	Apr 21 12:28:00 PM PDT 24
Finished	Apr 21 12:28:34 PM PDT 24
Peak memory	203388 kb
Host	smart-095cbebb-8c66-417f-a707-105fef834927
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762463022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2762463022
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.530779750
Short name	T132
Test name
Test status
Simulation time	3262318886 ps
CPU time	27.87 seconds
Started	Apr 21 12:28:09 PM PDT 24
Finished	Apr 21 12:28:37 PM PDT 24
Peak memory	203408 kb
Host	smart-fc3dff82-370d-4f76-8585-68a8495c922d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=530779750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.530779750
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1883453729
Short name	T764
Test name
Test status
Simulation time	50979762 ps
CPU time	2 seconds
Started	Apr 21 12:28:04 PM PDT 24
Finished	Apr 21 12:28:07 PM PDT 24
Peak memory	203248 kb
Host	smart-d3acc6bd-f5a5-489c-a094-c7f8827ae20c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883453729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1883453729
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.2632174264
Short name	T214
Test name
Test status
Simulation time	1046699973 ps
CPU time	78.12 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:29:31 PM PDT 24
Peak memory	207948 kb
Host	smart-1481d2aa-d7d3-469e-a582-0976b117aa4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2632174264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2632174264
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1557012699
Short name	T287
Test name
Test status
Simulation time	5537591564 ps
CPU time	152.28 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:30:51 PM PDT 24
Peak memory	211580 kb
Host	smart-7b197502-97d9-4abc-8a5d-b11fac16c8ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1557012699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1557012699
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3085092016
Short name	T533
Test name
Test status
Simulation time	2565380887 ps
CPU time	355.5 seconds
Started	Apr 21 12:28:03 PM PDT 24
Finished	Apr 21 12:33:59 PM PDT 24
Peak memory	209604 kb
Host	smart-741a99f1-2677-468e-899a-3000d5d10dde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085092016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3085092016
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2200532243
Short name	T875
Test name
Test status
Simulation time	992594568 ps
CPU time	258.4 seconds
Started	Apr 21 12:28:08 PM PDT 24
Finished	Apr 21 12:32:27 PM PDT 24
Peak memory	219648 kb
Host	smart-fcdb6a92-616c-481b-a0ed-567483ac5e2c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200532243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2200532243
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2879905601
Short name	T541
Test name
Test status
Simulation time	202025056 ps
CPU time	5.25 seconds
Started	Apr 21 12:28:16 PM PDT 24
Finished	Apr 21 12:28:22 PM PDT 24
Peak memory	211524 kb
Host	smart-4205ad58-21fc-4d86-89c1-bd83a4c91f8e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2879905601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2879905601
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3624530012
Short name	T116
Test name
Test status
Simulation time	3318843520 ps
CPU time	62.03 seconds
Started	Apr 21 12:26:33 PM PDT 24
Finished	Apr 21 12:27:36 PM PDT 24
Peak memory	211528 kb
Host	smart-9814a429-7356-4bfa-b327-4037ef5d1d19
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3624530012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3624530012
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1818817210
Short name	T179
Test name
Test status
Simulation time	111079241819 ps
CPU time	277.63 seconds
Started	Apr 21 12:26:40 PM PDT 24
Finished	Apr 21 12:31:18 PM PDT 24
Peak memory	206372 kb
Host	smart-f52d4a36-6053-44a6-bb89-02ff48673d0a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1818817210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.1818817210
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.370312370
Short name	T620
Test name
Test status
Simulation time	128993099 ps
CPU time	3.42 seconds
Started	Apr 21 12:26:35 PM PDT 24
Finished	Apr 21 12:26:39 PM PDT 24
Peak memory	203268 kb
Host	smart-2e1b4a9b-1d8c-4839-b55a-53781814a543
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=370312370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.370312370
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.640005674
Short name	T557
Test name
Test status
Simulation time	2052424630 ps
CPU time	14.63 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:26:54 PM PDT 24
Peak memory	203560 kb
Host	smart-09e63714-3abe-4a27-b48b-fc30efd0b3b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=640005674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.640005674
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.2100597373
Short name	T280
Test name
Test status
Simulation time	528792939 ps
CPU time	20.6 seconds
Started	Apr 21 12:26:42 PM PDT 24
Finished	Apr 21 12:27:03 PM PDT 24
Peak memory	204724 kb
Host	smart-b7979d8c-a78b-42c5-9e53-8fcdc2036bb0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100597373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2100597373
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.956476562
Short name	T766
Test name
Test status
Simulation time	16217556852 ps
CPU time	107.97 seconds
Started	Apr 21 12:26:38 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	204956 kb
Host	smart-b0c6ae22-37b9-4415-86ff-a164712e7be1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=956476562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.956476562
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2968720946
Short name	T810
Test name
Test status
Simulation time	13307895846 ps
CPU time	99.58 seconds
Started	Apr 21 12:26:41 PM PDT 24
Finished	Apr 21 12:28:21 PM PDT 24
Peak memory	211580 kb
Host	smart-5374da4e-301f-4631-9c15-681fe9f2a989
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2968720946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2968720946
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.613610570
Short name	T846
Test name
Test status
Simulation time	194561178 ps
CPU time	19.77 seconds
Started	Apr 21 12:26:45 PM PDT 24
Finished	Apr 21 12:27:05 PM PDT 24
Peak memory	211500 kb
Host	smart-07499955-3960-400d-8aae-5cd57e77da21
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613610570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.613610570
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.3051856781
Short name	T579
Test name
Test status
Simulation time	374502550 ps
CPU time	14.16 seconds
Started	Apr 21 12:27:07 PM PDT 24
Finished	Apr 21 12:27:22 PM PDT 24
Peak memory	211520 kb
Host	smart-8cc04547-6ec9-4677-ad99-1d1ea76b662a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3051856781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3051856781
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.4090514557
Short name	T779
Test name
Test status
Simulation time	799421211 ps
CPU time	4.35 seconds
Started	Apr 21 12:26:47 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	203232 kb
Host	smart-7f5a0658-52d2-4f37-89cd-c0fd55c884fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090514557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4090514557
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2976967088
Short name	T532
Test name
Test status
Simulation time	9497947143 ps
CPU time	27.73 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:27:07 PM PDT 24
Peak memory	203296 kb
Host	smart-3ab1eb4c-6a13-4edc-937b-73537093dbb8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976967088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2976967088
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1021236173
Short name	T609
Test name
Test status
Simulation time	10781802547 ps
CPU time	25.62 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:27:05 PM PDT 24
Peak memory	203328 kb
Host	smart-bd0221d4-b205-4a8d-bc88-3e2b0deb4fdc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1021236173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1021236173
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1133629245
Short name	T674
Test name
Test status
Simulation time	24830661 ps
CPU time	2.39 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:27:03 PM PDT 24
Peak memory	203236 kb
Host	smart-bfe978bf-b0e7-453a-bc7e-7ef2f7c82fec
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133629245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1133629245
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.2351781774
Short name	T820
Test name
Test status
Simulation time	9152283428 ps
CPU time	149.66 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:29:21 PM PDT 24
Peak memory	209824 kb
Host	smart-c429bfb0-360e-46eb-b585-075ddb2abba3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2351781774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2351781774
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3566438146
Short name	T535
Test name
Test status
Simulation time	287188719 ps
CPU time	14.2 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:27:08 PM PDT 24
Peak memory	203724 kb
Host	smart-4da96e63-be0c-405d-ba86-4f588e88158a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3566438146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3566438146
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2809810965
Short name	T891
Test name
Test status
Simulation time	1143086056 ps
CPU time	415.3 seconds
Started	Apr 21 12:26:54 PM PDT 24
Finished	Apr 21 12:33:50 PM PDT 24
Peak memory	209712 kb
Host	smart-0b4889de-0518-4449-939f-f741333bc41d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2809810965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2809810965
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3253338741
Short name	T570
Test name
Test status
Simulation time	401650432 ps
CPU time	78.3 seconds
Started	Apr 21 12:27:05 PM PDT 24
Finished	Apr 21 12:28:23 PM PDT 24
Peak memory	208844 kb
Host	smart-ac28416c-70b9-4cb1-b193-ffe27bee026c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253338741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.3253338741
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.909285208
Short name	T725
Test name
Test status
Simulation time	57830621 ps
CPU time	2.4 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:26:42 PM PDT 24
Peak memory	203368 kb
Host	smart-dc215ecc-0636-4625-a153-b8e228ed3fcb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=909285208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.909285208
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3142502915
Short name	T462
Test name
Test status
Simulation time	169450011 ps
CPU time	11.9 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	211448 kb
Host	smart-ee38e7ab-65f2-4b64-b7d9-f3868b41cb4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142502915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3142502915
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2639700416
Short name	T324
Test name
Test status
Simulation time	153098589 ps
CPU time	14.55 seconds
Started	Apr 21 12:28:17 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	203260 kb
Host	smart-2059c0b2-9640-4c30-87fa-628578f733ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639700416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2639700416
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.1758179171
Short name	T423
Test name
Test status
Simulation time	242631359 ps
CPU time	7.64 seconds
Started	Apr 21 12:28:09 PM PDT 24
Finished	Apr 21 12:28:17 PM PDT 24
Peak memory	203348 kb
Host	smart-a93b2112-f97a-4e4e-936c-b44c67d7b0d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1758179171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1758179171
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.381144939
Short name	T796
Test name
Test status
Simulation time	140226867 ps
CPU time	12.51 seconds
Started	Apr 21 12:28:10 PM PDT 24
Finished	Apr 21 12:28:23 PM PDT 24
Peak memory	211392 kb
Host	smart-ab558fcf-495a-494d-8787-77fb638904ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=381144939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.381144939
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.449684013
Short name	T622
Test name
Test status
Simulation time	93868028962 ps
CPU time	272.73 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:32:45 PM PDT 24
Peak memory	205224 kb
Host	smart-aa7f741b-3215-4410-a306-1f8aca43ad69
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=449684013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.449684013
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3169870925
Short name	T259
Test name
Test status
Simulation time	72274060592 ps
CPU time	196.53 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:31:29 PM PDT 24
Peak memory	211592 kb
Host	smart-bd0e37ce-9263-4e4d-9459-cd5f39e5d8c0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3169870925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3169870925
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2495852260
Short name	T187
Test name
Test status
Simulation time	99913457 ps
CPU time	9.53 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:28:30 PM PDT 24
Peak memory	211536 kb
Host	smart-2ea7e504-37e9-4edf-b6ec-a1ac417d896b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495852260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2495852260
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.1259982808
Short name	T15
Test name
Test status
Simulation time	3154741509 ps
CPU time	32.7 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:28:45 PM PDT 24
Peak memory	203424 kb
Host	smart-2a01073f-1c92-4eda-b17e-8e9c16f3dc6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1259982808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1259982808
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.419829730
Short name	T331
Test name
Test status
Simulation time	382362305 ps
CPU time	3.47 seconds
Started	Apr 21 12:28:05 PM PDT 24
Finished	Apr 21 12:28:09 PM PDT 24
Peak memory	203288 kb
Host	smart-b5cccf27-e9f8-4ed8-a68b-cb4ba4ce0fca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=419829730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.419829730
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.709222300
Short name	T895
Test name
Test status
Simulation time	9945825629 ps
CPU time	26.78 seconds
Started	Apr 21 12:28:07 PM PDT 24
Finished	Apr 21 12:28:34 PM PDT 24
Peak memory	203392 kb
Host	smart-7eeff8f9-c54e-4821-b2c9-6998e8aae53b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=709222300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.709222300
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2446548859
Short name	T554
Test name
Test status
Simulation time	4502738165 ps
CPU time	18.55 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	203308 kb
Host	smart-69bf6f93-8d84-42f1-bbe6-1b6d924e71ed
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2446548859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2446548859
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.4107029326
Short name	T263
Test name
Test status
Simulation time	25606748 ps
CPU time	2.16 seconds
Started	Apr 21 12:28:15 PM PDT 24
Finished	Apr 21 12:28:18 PM PDT 24
Peak memory	203244 kb
Host	smart-80ff9598-86b7-41c7-9d31-f8de6eaf6fab
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107029326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.4107029326
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.1473533474
Short name	T484
Test name
Test status
Simulation time	2281111098 ps
CPU time	54.77 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:29:15 PM PDT 24
Peak memory	206208 kb
Host	smart-451860a6-cf28-4582-a3be-ca0f4486fc14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1473533474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1473533474
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1337312075
Short name	T559
Test name
Test status
Simulation time	278744395 ps
CPU time	20.02 seconds
Started	Apr 21 12:28:10 PM PDT 24
Finished	Apr 21 12:28:30 PM PDT 24
Peak memory	203428 kb
Host	smart-9757f34c-891b-4fa7-87c8-377656b95240
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1337312075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1337312075
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4111117587
Short name	T290
Test name
Test status
Simulation time	116882962 ps
CPU time	44.76 seconds
Started	Apr 21 12:28:11 PM PDT 24
Finished	Apr 21 12:28:57 PM PDT 24
Peak memory	206564 kb
Host	smart-29a32f45-8d76-42c5-bbe2-2d5a48b77f79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4111117587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.4111117587
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.92873404
Short name	T30
Test name
Test status
Simulation time	1317699199 ps
CPU time	179 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:31:18 PM PDT 24
Peak memory	210896 kb
Host	smart-3f2d8c74-9165-43cc-88dc-2a02daf4c9fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92873404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rese t_error.92873404
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3427570134
Short name	T333
Test name
Test status
Simulation time	571404436 ps
CPU time	19.52 seconds
Started	Apr 21 12:28:08 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	204948 kb
Host	smart-2168ad48-3989-4e2f-8701-56b718051430
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3427570134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3427570134
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3133019718
Short name	T896
Test name
Test status
Simulation time	822770775 ps
CPU time	31.54 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:54 PM PDT 24
Peak memory	205832 kb
Host	smart-d403daf9-ed72-47e7-9aa2-6cbb65745c47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3133019718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3133019718
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1193119297
Short name	T516
Test name
Test status
Simulation time	86139525916 ps
CPU time	414.77 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:35:08 PM PDT 24
Peak memory	211596 kb
Host	smart-8be27518-1592-40a7-bcd4-f85f63f5889c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1193119297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1193119297
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1446237598
Short name	T887
Test name
Test status
Simulation time	369613630 ps
CPU time	3.61 seconds
Started	Apr 21 12:28:14 PM PDT 24
Finished	Apr 21 12:28:18 PM PDT 24
Peak memory	203368 kb
Host	smart-18d691f9-f06c-4e71-aa56-e5cc13b347e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446237598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1446237598
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.1838586957
Short name	T332
Test name
Test status
Simulation time	699439796 ps
CPU time	14.97 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	203368 kb
Host	smart-e029bed2-ed5f-47b6-9ba2-3c300f54badd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1838586957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1838586957
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.1168315846
Short name	T215
Test name
Test status
Simulation time	1425559029 ps
CPU time	31.81 seconds
Started	Apr 21 12:28:11 PM PDT 24
Finished	Apr 21 12:28:43 PM PDT 24
Peak memory	204356 kb
Host	smart-5dd11856-bb26-4f6f-b77c-313952f672ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1168315846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1168315846
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1682571293
Short name	T672
Test name
Test status
Simulation time	3041146870 ps
CPU time	13.68 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	203316 kb
Host	smart-3fac6dac-2db3-4818-80f0-3d1edc2ba906
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682571293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1682571293
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.916851477
Short name	T97
Test name
Test status
Simulation time	38938710577 ps
CPU time	201.05 seconds
Started	Apr 21 12:28:16 PM PDT 24
Finished	Apr 21 12:31:37 PM PDT 24
Peak memory	211488 kb
Host	smart-c92aa8a3-2220-442d-a9d5-3a661b2b93d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=916851477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.916851477
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3003267314
Short name	T285
Test name
Test status
Simulation time	309553916 ps
CPU time	28.49 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:50 PM PDT 24
Peak memory	205224 kb
Host	smart-4dd89c00-66b5-42b8-951d-d0665ea4d93f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003267314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3003267314
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.3106041193
Short name	T211
Test name
Test status
Simulation time	791354127 ps
CPU time	16.16 seconds
Started	Apr 21 12:28:11 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	203340 kb
Host	smart-007d6cb8-134f-402f-a679-d0879d56e3e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3106041193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3106041193
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.2497915103
Short name	T693
Test name
Test status
Simulation time	36442518 ps
CPU time	2.12 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:24 PM PDT 24
Peak memory	203344 kb
Host	smart-ed8dd125-ae88-4260-b45b-32b825c344c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2497915103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2497915103
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.4249662135
Short name	T64
Test name
Test status
Simulation time	11599998632 ps
CPU time	26.86 seconds
Started	Apr 21 12:28:06 PM PDT 24
Finished	Apr 21 12:28:34 PM PDT 24
Peak memory	203304 kb
Host	smart-bfa77951-1ee8-4e1a-a298-e1c0677c938b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249662135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.4249662135
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3105985105
Short name	T260
Test name
Test status
Simulation time	4536671399 ps
CPU time	28.34 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:42 PM PDT 24
Peak memory	203360 kb
Host	smart-cf11cbce-f3e3-42b7-b446-6fc3c9efd534
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3105985105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3105985105
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1432221708
Short name	T646
Test name
Test status
Simulation time	44858059 ps
CPU time	2.67 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:28:22 PM PDT 24
Peak memory	203236 kb
Host	smart-5ed49b2e-b744-4f39-bb6d-efbb36183d05
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432221708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1432221708
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.3541716817
Short name	T102
Test name
Test status
Simulation time	9032632866 ps
CPU time	223.47 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:32:04 PM PDT 24
Peak memory	210272 kb
Host	smart-b2f26102-5f50-4246-868f-4edc13e575a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3541716817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3541716817
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.39785879
Short name	T702
Test name
Test status
Simulation time	3018853034 ps
CPU time	17.46 seconds
Started	Apr 21 12:28:15 PM PDT 24
Finished	Apr 21 12:28:33 PM PDT 24
Peak memory	203344 kb
Host	smart-3aee3f1b-866f-4da3-a74f-f71f6c009555
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=39785879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.39785879
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4203041789
Short name	T856
Test name
Test status
Simulation time	6573878 ps
CPU time	16.25 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:28:35 PM PDT 24
Peak memory	203344 kb
Host	smart-45413d88-2a51-492c-821f-789dbdec7e73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4203041789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.4203041789
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2557645203
Short name	T238
Test name
Test status
Simulation time	1674525309 ps
CPU time	285.8 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:33:05 PM PDT 24
Peak memory	219704 kb
Host	smart-39407f30-207f-44a4-9694-76d0aac9a62e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2557645203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2557645203
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.849956388
Short name	T161
Test name
Test status
Simulation time	24185876 ps
CPU time	3.67 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:26 PM PDT 24
Peak memory	211468 kb
Host	smart-d54ca9ed-0bc5-4c71-a96e-4576644dfa31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=849956388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.849956388
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3621863272
Short name	T160
Test name
Test status
Simulation time	111179621 ps
CPU time	9.89 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:31 PM PDT 24
Peak memory	211524 kb
Host	smart-187fb6d8-37b2-4577-afeb-11c775300cdc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3621863272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3621863272
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1676822967
Short name	T879
Test name
Test status
Simulation time	19985956190 ps
CPU time	121.54 seconds
Started	Apr 21 12:28:17 PM PDT 24
Finished	Apr 21 12:30:20 PM PDT 24
Peak memory	211564 kb
Host	smart-aa172abe-549f-4b82-8bd2-7e01856a5f80
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1676822967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.1676822967
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2458110323
Short name	T523
Test name
Test status
Simulation time	245948115 ps
CPU time	6.76 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	203260 kb
Host	smart-2e480722-d6d2-4d9f-90ab-0a7fe5f9494e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2458110323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2458110323
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.1695362493
Short name	T705
Test name
Test status
Simulation time	190730981 ps
CPU time	21.68 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:36 PM PDT 24
Peak memory	203452 kb
Host	smart-1a4cb61f-3700-48ff-be97-631c404a0253
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1695362493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1695362493
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.4127842344
Short name	T688
Test name
Test status
Simulation time	3372472813 ps
CPU time	30.42 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:28:50 PM PDT 24
Peak memory	204356 kb
Host	smart-27a2fa68-462c-4513-8eac-58518098a827
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4127842344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.4127842344
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2498053931
Short name	T16
Test name
Test status
Simulation time	73521779395 ps
CPU time	233.42 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:32:12 PM PDT 24
Peak memory	211496 kb
Host	smart-9bf4fb2b-76ff-4410-bb6c-91bd5b0d969d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498053931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2498053931
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3910426410
Short name	T48
Test name
Test status
Simulation time	11228477757 ps
CPU time	56.66 seconds
Started	Apr 21 12:28:10 PM PDT 24
Finished	Apr 21 12:29:08 PM PDT 24
Peak memory	204632 kb
Host	smart-4d7bfabf-c113-4bb8-9aeb-a8cf84350216
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3910426410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3910426410
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3465684274
Short name	T134
Test name
Test status
Simulation time	73021053 ps
CPU time	8.55 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:30 PM PDT 24
Peak memory	211524 kb
Host	smart-dd7d4e0e-0d61-4144-82e0-cb9388da786f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465684274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3465684274
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.1829542509
Short name	T320
Test name
Test status
Simulation time	990784843 ps
CPU time	12.92 seconds
Started	Apr 21 12:28:23 PM PDT 24
Finished	Apr 21 12:28:36 PM PDT 24
Peak memory	203272 kb
Host	smart-02914051-049f-4f27-bbd0-fd213479a581
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1829542509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1829542509
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.3583591842
Short name	T407
Test name
Test status
Simulation time	181404772 ps
CPU time	3.8 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:24 PM PDT 24
Peak memory	203256 kb
Host	smart-474c08cd-83b2-44da-baad-515ea56beda6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3583591842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3583591842
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1613851187
Short name	T756
Test name
Test status
Simulation time	21036963877 ps
CPU time	44.45 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:29:14 PM PDT 24
Peak memory	203400 kb
Host	smart-33d947f6-f500-4b92-9b38-946813076cce
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613851187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1613851187
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2353186750
Short name	T360
Test name
Test status
Simulation time	15154676683 ps
CPU time	36.52 seconds
Started	Apr 21 12:28:15 PM PDT 24
Finished	Apr 21 12:28:52 PM PDT 24
Peak memory	203360 kb
Host	smart-0cef30ae-844b-488d-8431-47aa522f23b5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2353186750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2353186750
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1313994503
Short name	T409
Test name
Test status
Simulation time	34123452 ps
CPU time	2.52 seconds
Started	Apr 21 12:28:12 PM PDT 24
Finished	Apr 21 12:28:15 PM PDT 24
Peak memory	203244 kb
Host	smart-34e77e03-22ff-4bc7-b185-e77178af041a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313994503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1313994503
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.621959780
Short name	T178
Test name
Test status
Simulation time	5305017077 ps
CPU time	142.87 seconds
Started	Apr 21 12:28:27 PM PDT 24
Finished	Apr 21 12:30:50 PM PDT 24
Peak memory	207944 kb
Host	smart-54ab290c-c4dc-4ad5-b3d3-32b27ed0dd7a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=621959780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.621959780
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.243881427
Short name	T37
Test name
Test status
Simulation time	1956881922 ps
CPU time	59.37 seconds
Started	Apr 21 12:28:17 PM PDT 24
Finished	Apr 21 12:29:17 PM PDT 24
Peak memory	204456 kb
Host	smart-1934a222-e82c-45a8-9c64-59155daa2d32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=243881427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.243881427
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3122835361
Short name	T607
Test name
Test status
Simulation time	153302246 ps
CPU time	125.3 seconds
Started	Apr 21 12:28:26 PM PDT 24
Finished	Apr 21 12:30:31 PM PDT 24
Peak memory	207968 kb
Host	smart-45b9fe35-d5f2-4102-b381-90ea5903a249
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3122835361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3122835361
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2261431873
Short name	T881
Test name
Test status
Simulation time	100146217 ps
CPU time	10.49 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:28:29 PM PDT 24
Peak memory	205008 kb
Host	smart-d9eabb6e-e494-4320-8e21-0418b9f66b1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261431873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2261431873
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1057360125
Short name	T475
Test name
Test status
Simulation time	38667086 ps
CPU time	7.37 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:30 PM PDT 24
Peak memory	203708 kb
Host	smart-80c900c5-a8b1-477b-830e-4478b75afe62
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1057360125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1057360125
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2718797796
Short name	T588
Test name
Test status
Simulation time	13263167567 ps
CPU time	26.82 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	203412 kb
Host	smart-13c63be5-7a5f-4967-8726-c13d9198085c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2718797796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.2718797796
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3376444212
Short name	T435
Test name
Test status
Simulation time	1794723171 ps
CPU time	26.86 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	203312 kb
Host	smart-84226598-d80c-401a-9730-90d5a82a8610
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3376444212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3376444212
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.1015535087
Short name	T474
Test name
Test status
Simulation time	635745953 ps
CPU time	15.76 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	203556 kb
Host	smart-6d8062f4-2b06-4996-b2ed-849eb65cc729
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1015535087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1015535087
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.2637702338
Short name	T222
Test name
Test status
Simulation time	764514629 ps
CPU time	24.53 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	211740 kb
Host	smart-81cdb3a2-127f-41ef-b188-18849dfeb73c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2637702338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2637702338
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2378573909
Short name	T459
Test name
Test status
Simulation time	70456363536 ps
CPU time	141.48 seconds
Started	Apr 21 12:28:17 PM PDT 24
Finished	Apr 21 12:30:39 PM PDT 24
Peak memory	211508 kb
Host	smart-705f645b-67cd-4b30-bac8-6c27ca61ecc1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378573909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2378573909
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.161612261
Short name	T146
Test name
Test status
Simulation time	59444420128 ps
CPU time	160.1 seconds
Started	Apr 21 12:28:11 PM PDT 24
Finished	Apr 21 12:30:51 PM PDT 24
Peak memory	211548 kb
Host	smart-2475a50d-78ee-4cb0-8a70-181c4be5b2ff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=161612261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.161612261
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3910589921
Short name	T329
Test name
Test status
Simulation time	73742140 ps
CPU time	11.11 seconds
Started	Apr 21 12:28:15 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	204364 kb
Host	smart-ae6e89d6-fc4c-46f8-8b22-910ab0d6ff37
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910589921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3910589921
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.1463694332
Short name	T399
Test name
Test status
Simulation time	1605826353 ps
CPU time	27.4 seconds
Started	Apr 21 12:28:16 PM PDT 24
Finished	Apr 21 12:28:44 PM PDT 24
Peak memory	203876 kb
Host	smart-3913508c-4ff1-4511-8bb5-36a44bcdd468
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1463694332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1463694332
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.3659705760
Short name	T633
Test name
Test status
Simulation time	140161979 ps
CPU time	2.93 seconds
Started	Apr 21 12:28:17 PM PDT 24
Finished	Apr 21 12:28:21 PM PDT 24
Peak memory	203340 kb
Host	smart-7999357f-e787-4f6e-bbf0-0bb62ad7f909
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3659705760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3659705760
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3015856171
Short name	T418
Test name
Test status
Simulation time	14225842386 ps
CPU time	34.26 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:28:54 PM PDT 24
Peak memory	203412 kb
Host	smart-d6dc1b37-9339-4295-a6e4-6d97b2b01b28
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015856171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3015856171
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1229703453
Short name	T682
Test name
Test status
Simulation time	4543363854 ps
CPU time	28.14 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:28:47 PM PDT 24
Peak memory	203308 kb
Host	smart-a04890e2-210a-4375-a94a-9461359db7e4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1229703453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1229703453
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2694501104
Short name	T336
Test name
Test status
Simulation time	55628777 ps
CPU time	2.29 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	203232 kb
Host	smart-5f1ffa43-b60e-4566-8d29-d5b1d203d973
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694501104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2694501104
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.2496340652
Short name	T94
Test name
Test status
Simulation time	2815694561 ps
CPU time	62.23 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:29:32 PM PDT 24
Peak memory	207236 kb
Host	smart-54b9a49d-82a9-40da-bd2d-0544bc72f223
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2496340652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2496340652
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2544920952
Short name	T489
Test name
Test status
Simulation time	686988809 ps
CPU time	29.64 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:28:59 PM PDT 24
Peak memory	204680 kb
Host	smart-0a8a83da-d30c-4afe-acba-b96f019c3de7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2544920952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2544920952
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1925323038
Short name	T709
Test name
Test status
Simulation time	7329085070 ps
CPU time	625.43 seconds
Started	Apr 21 12:28:31 PM PDT 24
Finished	Apr 21 12:38:57 PM PDT 24
Peak memory	219796 kb
Host	smart-bba4faed-b99a-4aae-a2ff-3db922e2f4eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1925323038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.1925323038
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1921191389
Short name	T40
Test name
Test status
Simulation time	7509927117 ps
CPU time	213.21 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:31:53 PM PDT 24
Peak memory	208204 kb
Host	smart-9d05b4b5-ae99-4e00-9f7e-24db467162b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1921191389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.1921191389
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2125240859
Short name	T555
Test name
Test status
Simulation time	110973407 ps
CPU time	6.83 seconds
Started	Apr 21 12:28:15 PM PDT 24
Finished	Apr 21 12:28:23 PM PDT 24
Peak memory	204724 kb
Host	smart-94a5c97f-f5a5-4050-9232-0a0b3d93ef72
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2125240859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2125240859
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.222056610
Short name	T127
Test name
Test status
Simulation time	1228941344 ps
CPU time	37.9 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:59 PM PDT 24
Peak memory	206024 kb
Host	smart-e0c7ff21-ee0e-4e20-aab4-b18f84e87bab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=222056610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.222056610
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.4128869896
Short name	T631
Test name
Test status
Simulation time	111190057210 ps
CPU time	557.62 seconds
Started	Apr 21 12:28:25 PM PDT 24
Finished	Apr 21 12:37:43 PM PDT 24
Peak memory	211560 kb
Host	smart-0c0f5626-6ff5-472c-b8fa-26d46ce5bb4d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4128869896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.4128869896
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1680730259
Short name	T293
Test name
Test status
Simulation time	258619538 ps
CPU time	18.76 seconds
Started	Apr 21 12:28:32 PM PDT 24
Finished	Apr 21 12:28:51 PM PDT 24
Peak memory	203344 kb
Host	smart-cf6df3ad-16e1-4de8-ad93-81d596f9e8e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680730259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1680730259
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.3043143878
Short name	T308
Test name
Test status
Simulation time	186853493 ps
CPU time	4.55 seconds
Started	Apr 21 12:28:14 PM PDT 24
Finished	Apr 21 12:28:19 PM PDT 24
Peak memory	203212 kb
Host	smart-e138bf3a-e7a6-404f-982d-bedfc4072f64
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3043143878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3043143878
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.3221064386
Short name	T18
Test name
Test status
Simulation time	138064268 ps
CPU time	14.75 seconds
Started	Apr 21 12:28:14 PM PDT 24
Finished	Apr 21 12:28:29 PM PDT 24
Peak memory	211472 kb
Host	smart-470a134e-3376-4555-9a3b-7b60930d52a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221064386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3221064386
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1572294831
Short name	T66
Test name
Test status
Simulation time	32880828450 ps
CPU time	105.67 seconds
Started	Apr 21 12:28:25 PM PDT 24
Finished	Apr 21 12:30:11 PM PDT 24
Peak memory	211480 kb
Host	smart-84a854d4-d28e-41a0-84af-b38022b7882b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572294831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1572294831
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3776050435
Short name	T51
Test name
Test status
Simulation time	19224230469 ps
CPU time	187.08 seconds
Started	Apr 21 12:28:30 PM PDT 24
Finished	Apr 21 12:31:38 PM PDT 24
Peak memory	204944 kb
Host	smart-ab0330eb-1557-49cf-b4f8-4a382ea51330
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3776050435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3776050435
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1538751340
Short name	T669
Test name
Test status
Simulation time	781143243 ps
CPU time	25.24 seconds
Started	Apr 21 12:28:27 PM PDT 24
Finished	Apr 21 12:28:52 PM PDT 24
Peak memory	211468 kb
Host	smart-725a5771-8e9e-43cc-81ea-4ea8a85ddab6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538751340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1538751340
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.3965643411
Short name	T852
Test name
Test status
Simulation time	1092157053 ps
CPU time	15.82 seconds
Started	Apr 21 12:29:39 PM PDT 24
Finished	Apr 21 12:29:55 PM PDT 24
Peak memory	202908 kb
Host	smart-ed0b58e9-a2fd-4974-b379-8af00c69e8a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3965643411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3965643411
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.1970924904
Short name	T274
Test name
Test status
Simulation time	41010143 ps
CPU time	2.29 seconds
Started	Apr 21 12:28:14 PM PDT 24
Finished	Apr 21 12:28:17 PM PDT 24
Peak memory	203276 kb
Host	smart-addca791-536e-41f7-abcb-b82a1531b38d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1970924904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1970924904
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1333297595
Short name	T877
Test name
Test status
Simulation time	5194688262 ps
CPU time	33.14 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:54 PM PDT 24
Peak memory	203308 kb
Host	smart-6880ceef-f973-4df4-a9c0-4ce2f261e96d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333297595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1333297595
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.270398914
Short name	T467
Test name
Test status
Simulation time	4348314488 ps
CPU time	28.26 seconds
Started	Apr 21 12:28:09 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	203332 kb
Host	smart-239bd190-1fb9-45b3-a1b4-a3987c216cae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=270398914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.270398914
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4221616706
Short name	T11
Test name
Test status
Simulation time	134689000 ps
CPU time	2.36 seconds
Started	Apr 21 12:28:09 PM PDT 24
Finished	Apr 21 12:28:12 PM PDT 24
Peak memory	203224 kb
Host	smart-4688a3bd-b2e3-4b5c-a377-c12e0eaf03b4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221616706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.4221616706
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.54028699
Short name	T366
Test name
Test status
Simulation time	137642172 ps
CPU time	3.7 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:24 PM PDT 24
Peak memory	203244 kb
Host	smart-d480f543-090f-4382-a2f4-29f1185c42dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=54028699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.54028699
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3356291346
Short name	T799
Test name
Test status
Simulation time	778015159 ps
CPU time	60.25 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:29:22 PM PDT 24
Peak memory	206992 kb
Host	smart-1011fb5a-8847-44ab-a097-61c1e5665ab6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3356291346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3356291346
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.582564527
Short name	T823
Test name
Test status
Simulation time	9807879093 ps
CPU time	263.37 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:32:45 PM PDT 24
Peak memory	219696 kb
Host	smart-e331a8f6-833f-4688-8e8c-77f72f1a6150
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=582564527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.582564527
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2575635930
Short name	T661
Test name
Test status
Simulation time	121226456 ps
CPU time	17.56 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:28:37 PM PDT 24
Peak memory	204964 kb
Host	smart-9a866db6-1336-4ea6-a488-bcf357eb2267
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2575635930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2575635930
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2899960253
Short name	T741
Test name
Test status
Simulation time	1316377324 ps
CPU time	41.95 seconds
Started	Apr 21 12:28:34 PM PDT 24
Finished	Apr 21 12:29:16 PM PDT 24
Peak memory	211440 kb
Host	smart-8e1f6c88-b96b-4fde-97c1-cc6f97013697
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2899960253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2899960253
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1714042575
Short name	T189
Test name
Test status
Simulation time	145159827377 ps
CPU time	680.64 seconds
Started	Apr 21 12:28:39 PM PDT 24
Finished	Apr 21 12:40:00 PM PDT 24
Peak memory	211504 kb
Host	smart-eeb4b6ee-8beb-4c52-9c51-3993e7371d27
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1714042575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1714042575
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2327594959
Short name	T515
Test name
Test status
Simulation time	526175251 ps
CPU time	16.09 seconds
Started	Apr 21 12:28:16 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	203736 kb
Host	smart-4bce5983-16dd-4903-9e35-e8e46d1efba5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2327594959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2327594959
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.3855946993
Short name	T635
Test name
Test status
Simulation time	116224391 ps
CPU time	11.35 seconds
Started	Apr 21 12:28:37 PM PDT 24
Finished	Apr 21 12:28:49 PM PDT 24
Peak memory	203268 kb
Host	smart-2abd4f71-ba31-411a-ab56-24d29deeaab4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3855946993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3855946993
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.3390942834
Short name	T62
Test name
Test status
Simulation time	351335421 ps
CPU time	12.23 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:35 PM PDT 24
Peak memory	204428 kb
Host	smart-3145144b-3795-4112-a5da-955292b720d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3390942834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3390942834
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.820598202
Short name	T610
Test name
Test status
Simulation time	48059353731 ps
CPU time	142.99 seconds
Started	Apr 21 12:28:17 PM PDT 24
Finished	Apr 21 12:30:41 PM PDT 24
Peak memory	204944 kb
Host	smart-823933c1-1443-4d60-a9a5-417ff0c5ade3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=820598202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.820598202
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2915879174
Short name	T470
Test name
Test status
Simulation time	38368662015 ps
CPU time	97.97 seconds
Started	Apr 21 12:28:14 PM PDT 24
Finished	Apr 21 12:29:53 PM PDT 24
Peak memory	204580 kb
Host	smart-3d8deb15-1fa7-4ef2-a535-238d80dab4a9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2915879174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2915879174
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.471058636
Short name	T527
Test name
Test status
Simulation time	194485043 ps
CPU time	8.96 seconds
Started	Apr 21 12:28:25 PM PDT 24
Finished	Apr 21 12:28:34 PM PDT 24
Peak memory	204540 kb
Host	smart-305e6519-76cb-4164-89ba-2cefe89d9f25
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471058636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.471058636
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.2792937779
Short name	T298
Test name
Test status
Simulation time	525172320 ps
CPU time	8.47 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:28:31 PM PDT 24
Peak memory	203304 kb
Host	smart-608f296e-d501-40f8-aad9-d994a4d044e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2792937779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2792937779
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.4255306026
Short name	T328
Test name
Test status
Simulation time	28879640 ps
CPU time	2.12 seconds
Started	Apr 21 12:28:28 PM PDT 24
Finished	Apr 21 12:28:30 PM PDT 24
Peak memory	203244 kb
Host	smart-acabab23-b371-46b3-9d44-5ab6c9c72832
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4255306026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4255306026
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.81274142
Short name	T625
Test name
Test status
Simulation time	6558034643 ps
CPU time	25.87 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:40 PM PDT 24
Peak memory	203356 kb
Host	smart-ec7f42c5-f72d-4933-8c5a-be287ced2b15
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=81274142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.81274142
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.802776545
Short name	T190
Test name
Test status
Simulation time	7694378119 ps
CPU time	36.5 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:59 PM PDT 24
Peak memory	203316 kb
Host	smart-5c94c07c-9553-475e-904d-95ecf1432bdd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=802776545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.802776545
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3913921244
Short name	T794
Test name
Test status
Simulation time	41995311 ps
CPU time	2.49 seconds
Started	Apr 21 12:28:13 PM PDT 24
Finished	Apr 21 12:28:16 PM PDT 24
Peak memory	203336 kb
Host	smart-2f32b261-0ad6-4222-aed2-08213a0b4156
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913921244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3913921244
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.2889965994
Short name	T17
Test name
Test status
Simulation time	783559196 ps
CPU time	115.1 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:30:15 PM PDT 24
Peak memory	206328 kb
Host	smart-249dfb57-a722-4fd9-8771-f39874bcec2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2889965994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2889965994
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3922923006
Short name	T14
Test name
Test status
Simulation time	10592313155 ps
CPU time	239.9 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:32:20 PM PDT 24
Peak memory	211496 kb
Host	smart-b4672fcb-dc9e-4977-a75a-eb21927be3d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3922923006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3922923006
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2450249470
Short name	T170
Test name
Test status
Simulation time	1775476541 ps
CPU time	359.05 seconds
Started	Apr 21 12:29:40 PM PDT 24
Finished	Apr 21 12:35:49 PM PDT 24
Peak memory	207824 kb
Host	smart-963e6f6a-da4a-4365-914c-7c5973a67358
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2450249470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.2450249470
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.4105388982
Short name	T39
Test name
Test status
Simulation time	255347964 ps
CPU time	96.32 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:29:57 PM PDT 24
Peak memory	208832 kb
Host	smart-61a361c4-0c88-4ed8-bea1-ae6f501e3c0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4105388982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.4105388982
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3994248269
Short name	T325
Test name
Test status
Simulation time	426335963 ps
CPU time	11.52 seconds
Started	Apr 21 12:28:36 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	211532 kb
Host	smart-89076450-62ce-4e9b-8600-c6cb65d4ad38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3994248269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3994248269
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1435257864
Short name	T113
Test name
Test status
Simulation time	1407970372 ps
CPU time	43.26 seconds
Started	Apr 21 12:28:23 PM PDT 24
Finished	Apr 21 12:29:07 PM PDT 24
Peak memory	205984 kb
Host	smart-338e3bed-c812-457b-a820-da655bd03919
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1435257864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1435257864
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1155145392
Short name	T438
Test name
Test status
Simulation time	51677576938 ps
CPU time	314.52 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:33:33 PM PDT 24
Peak memory	211536 kb
Host	smart-843aab08-fca9-43b9-9f9a-64fb243b6232
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1155145392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.1155145392
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2010760110
Short name	T420
Test name
Test status
Simulation time	132796722 ps
CPU time	17.52 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:40 PM PDT 24
Peak memory	203552 kb
Host	smart-245b2538-01b4-4ba7-b745-c31360936915
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2010760110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2010760110
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.3237934578
Short name	T700
Test name
Test status
Simulation time	72384822 ps
CPU time	3.11 seconds
Started	Apr 21 12:28:39 PM PDT 24
Finished	Apr 21 12:28:42 PM PDT 24
Peak memory	203256 kb
Host	smart-4743b40a-bc43-4d00-8079-cfa6ddbbc664
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3237934578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3237934578
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.2830481586
Short name	T65
Test name
Test status
Simulation time	353167273 ps
CPU time	4.72 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:28:24 PM PDT 24
Peak memory	203268 kb
Host	smart-2d068587-7533-4aca-86fc-725f43ce5546
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2830481586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2830481586
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1178389454
Short name	T790
Test name
Test status
Simulation time	36735248297 ps
CPU time	220.66 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:32:03 PM PDT 24
Peak memory	211476 kb
Host	smart-3a02a183-cc7d-47f9-95a3-fdda98f4e968
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178389454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1178389454
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2880393563
Short name	T501
Test name
Test status
Simulation time	19854366047 ps
CPU time	162.48 seconds
Started	Apr 21 12:29:21 PM PDT 24
Finished	Apr 21 12:32:05 PM PDT 24
Peak memory	210592 kb
Host	smart-8b805a07-2fb4-49a9-a3be-00a37b32313b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2880393563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2880393563
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1100005202
Short name	T671
Test name
Test status
Simulation time	115281932 ps
CPU time	18.13 seconds
Started	Apr 21 12:28:39 PM PDT 24
Finished	Apr 21 12:28:57 PM PDT 24
Peak memory	204728 kb
Host	smart-01e185f1-3254-4b7d-9422-f00c1139735a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100005202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1100005202
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.4191057477
Short name	T379
Test name
Test status
Simulation time	457699319 ps
CPU time	8.06 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:31 PM PDT 24
Peak memory	203252 kb
Host	smart-3c1275dd-9e04-4355-a070-c69fe8e10ef2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4191057477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.4191057477
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.2528693449
Short name	T562
Test name
Test status
Simulation time	37093508 ps
CPU time	2.3 seconds
Started	Apr 21 12:28:19 PM PDT 24
Finished	Apr 21 12:28:22 PM PDT 24
Peak memory	203244 kb
Host	smart-92086e9d-bab9-4c9b-9f82-d173c7363746
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2528693449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2528693449
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1599626711
Short name	T648
Test name
Test status
Simulation time	9247413439 ps
CPU time	29.67 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:28:52 PM PDT 24
Peak memory	203388 kb
Host	smart-d5395b74-97f1-4e71-a928-657a9fb3f530
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599626711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1599626711
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1782380988
Short name	T817
Test name
Test status
Simulation time	4496035401 ps
CPU time	27.05 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	203360 kb
Host	smart-4dccdfcd-144b-492a-9221-175229d08f47
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1782380988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1782380988
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1039659226
Short name	T291
Test name
Test status
Simulation time	73247191 ps
CPU time	2.19 seconds
Started	Apr 21 12:28:18 PM PDT 24
Finished	Apr 21 12:28:21 PM PDT 24
Peak memory	203216 kb
Host	smart-1018f229-6956-4bb7-9e17-7bbcba091013
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039659226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1039659226
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.3147634884
Short name	T128
Test name
Test status
Simulation time	8183844173 ps
CPU time	146.09 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:30:46 PM PDT 24
Peak memory	209240 kb
Host	smart-5baf9f21-d6d2-423b-880a-6175bc07b9b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3147634884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3147634884
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1279800816
Short name	T191
Test name
Test status
Simulation time	7467480959 ps
CPU time	172.64 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:31:14 PM PDT 24
Peak memory	208508 kb
Host	smart-6fb542e8-9559-45d1-a417-90cd5b089634
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1279800816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1279800816
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1773744121
Short name	T546
Test name
Test status
Simulation time	1242716076 ps
CPU time	277.68 seconds
Started	Apr 21 12:28:23 PM PDT 24
Finished	Apr 21 12:33:01 PM PDT 24
Peak memory	208388 kb
Host	smart-6388d765-83b1-446e-8ba8-98313de7a40f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773744121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1773744121
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.407541521
Short name	T572
Test name
Test status
Simulation time	130225971 ps
CPU time	15.09 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:28:44 PM PDT 24
Peak memory	205688 kb
Host	smart-db401c88-3019-4f7b-b287-635967e043c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=407541521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.407541521
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4036150031
Short name	T493
Test name
Test status
Simulation time	629368547 ps
CPU time	11.86 seconds
Started	Apr 21 12:28:26 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	204948 kb
Host	smart-54f616f9-3670-4dc8-9c31-dff2007edef7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4036150031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4036150031
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2307945437
Short name	T292
Test name
Test status
Simulation time	497283126 ps
CPU time	47.5 seconds
Started	Apr 21 12:28:38 PM PDT 24
Finished	Apr 21 12:29:26 PM PDT 24
Peak memory	205148 kb
Host	smart-d5a4eced-1945-47d4-b4fe-2de286f4524d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307945437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2307945437
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3826038245
Short name	T184
Test name
Test status
Simulation time	87923121369 ps
CPU time	483.28 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:36:24 PM PDT 24
Peak memory	206968 kb
Host	smart-6efc4efa-e9d8-41d2-a2c1-510c1c69317e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3826038245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3826038245
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2817981543
Short name	T414
Test name
Test status
Simulation time	235809554 ps
CPU time	13.69 seconds
Started	Apr 21 12:28:23 PM PDT 24
Finished	Apr 21 12:28:37 PM PDT 24
Peak memory	203364 kb
Host	smart-14321d8b-39fa-4724-af47-6720ef2986c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2817981543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2817981543
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.97826695
Short name	T632
Test name
Test status
Simulation time	65649633 ps
CPU time	2.67 seconds
Started	Apr 21 12:28:24 PM PDT 24
Finished	Apr 21 12:28:27 PM PDT 24
Peak memory	203356 kb
Host	smart-8788e0b3-dbab-4b95-b892-b44b632a066d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=97826695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.97826695
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.452460613
Short name	T832
Test name
Test status
Simulation time	612642352 ps
CPU time	26.08 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:49 PM PDT 24
Peak memory	211488 kb
Host	smart-b5141e95-37dc-46aa-909b-1b80c824d757
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=452460613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.452460613
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.964858748
Short name	T306
Test name
Test status
Simulation time	50974294127 ps
CPU time	120.23 seconds
Started	Apr 21 12:28:30 PM PDT 24
Finished	Apr 21 12:30:31 PM PDT 24
Peak memory	211580 kb
Host	smart-e43de2a6-caf3-486c-9fba-543765ec0c56
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=964858748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.964858748
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4226838242
Short name	T99
Test name
Test status
Simulation time	39037010269 ps
CPU time	167.97 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:31:18 PM PDT 24
Peak memory	204848 kb
Host	smart-9dbba851-dfed-4112-8580-3225d4016513
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4226838242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4226838242
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3664498730
Short name	T277
Test name
Test status
Simulation time	47321523 ps
CPU time	6.36 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:28:28 PM PDT 24
Peak memory	204348 kb
Host	smart-3a9e7087-0308-4a5e-8d1d-e61289f7dc3f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664498730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3664498730
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.2325521979
Short name	T417
Test name
Test status
Simulation time	2292338822 ps
CPU time	36.66 seconds
Started	Apr 21 12:28:20 PM PDT 24
Finished	Apr 21 12:29:02 PM PDT 24
Peak memory	211604 kb
Host	smart-f2c4216f-4253-4ecd-a606-2319295fe044
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2325521979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2325521979
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.280031342
Short name	T343
Test name
Test status
Simulation time	136888161 ps
CPU time	2.36 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:28:25 PM PDT 24
Peak memory	203340 kb
Host	smart-7583bd8b-251c-4617-9141-272bbd0d6880
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=280031342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.280031342
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2360131772
Short name	T323
Test name
Test status
Simulation time	6640661500 ps
CPU time	31.29 seconds
Started	Apr 21 12:28:28 PM PDT 24
Finished	Apr 21 12:29:00 PM PDT 24
Peak memory	203396 kb
Host	smart-aec7659f-f231-499c-b34d-d02a96762e86
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360131772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2360131772
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3477489980
Short name	T98
Test name
Test status
Simulation time	6392007473 ps
CPU time	34.93 seconds
Started	Apr 21 12:28:39 PM PDT 24
Finished	Apr 21 12:29:15 PM PDT 24
Peak memory	203288 kb
Host	smart-c05e5685-9313-403e-9a45-59906aa2b592
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3477489980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3477489980
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2638613630
Short name	T651
Test name
Test status
Simulation time	132164249 ps
CPU time	2.33 seconds
Started	Apr 21 12:28:39 PM PDT 24
Finished	Apr 21 12:28:41 PM PDT 24
Peak memory	203332 kb
Host	smart-bb17616a-c262-4e34-a28b-d1b56b2919b7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638613630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2638613630
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.756232298
Short name	T87
Test name
Test status
Simulation time	5589502614 ps
CPU time	51.05 seconds
Started	Apr 21 12:28:35 PM PDT 24
Finished	Apr 21 12:29:26 PM PDT 24
Peak memory	206724 kb
Host	smart-969cb41b-3994-442a-93a9-572f4246b3d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=756232298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.756232298
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3589934367
Short name	T544
Test name
Test status
Simulation time	14879134562 ps
CPU time	195.65 seconds
Started	Apr 21 12:28:28 PM PDT 24
Finished	Apr 21 12:31:44 PM PDT 24
Peak memory	205544 kb
Host	smart-80fa7a95-dec0-496d-9414-4871548d205c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3589934367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3589934367
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1795062051
Short name	T32
Test name
Test status
Simulation time	1066896947 ps
CPU time	257.59 seconds
Started	Apr 21 12:28:24 PM PDT 24
Finished	Apr 21 12:32:42 PM PDT 24
Peak memory	209056 kb
Host	smart-b8eb2eb4-2b37-4335-89ea-f923b568a7d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1795062051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1795062051
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3667848240
Short name	T410
Test name
Test status
Simulation time	423015804 ps
CPU time	122.65 seconds
Started	Apr 21 12:28:27 PM PDT 24
Finished	Apr 21 12:30:30 PM PDT 24
Peak memory	208596 kb
Host	smart-fe1d109a-8d38-4b96-bd91-d4cacac0d949
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3667848240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3667848240
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2588254696
Short name	T452
Test name
Test status
Simulation time	150662387 ps
CPU time	20.57 seconds
Started	Apr 21 12:28:25 PM PDT 24
Finished	Apr 21 12:28:46 PM PDT 24
Peak memory	211452 kb
Host	smart-3f8b10b0-1420-4af3-b73f-d9528d4995be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588254696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2588254696
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1326130020
Short name	T204
Test name
Test status
Simulation time	499134824 ps
CPU time	25.57 seconds
Started	Apr 21 12:28:27 PM PDT 24
Finished	Apr 21 12:28:53 PM PDT 24
Peak memory	203224 kb
Host	smart-5d3f8bba-770d-4455-9c88-2b4d5417f0b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1326130020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1326130020
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1133074325
Short name	T361
Test name
Test status
Simulation time	119537005663 ps
CPU time	309.58 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:33:39 PM PDT 24
Peak memory	206580 kb
Host	smart-abc0997a-0052-49fe-a050-ba766cde9c23
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1133074325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1133074325
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3131781827
Short name	T814
Test name
Test status
Simulation time	483380551 ps
CPU time	9.29 seconds
Started	Apr 21 12:28:37 PM PDT 24
Finished	Apr 21 12:28:46 PM PDT 24
Peak memory	203464 kb
Host	smart-9afde56b-f191-4247-8bfb-45278bc98397
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3131781827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3131781827
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.154809959
Short name	T440
Test name
Test status
Simulation time	285126748 ps
CPU time	19.15 seconds
Started	Apr 21 12:28:37 PM PDT 24
Finished	Apr 21 12:28:56 PM PDT 24
Peak memory	203360 kb
Host	smart-2b5e4621-8607-45ab-b9dc-aeed1579a1b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=154809959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.154809959
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.2903240222
Short name	T629
Test name
Test status
Simulation time	225728475 ps
CPU time	13.78 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:28:35 PM PDT 24
Peak memory	211436 kb
Host	smart-07a2d318-082d-482e-b0d3-5e027e9947f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2903240222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2903240222
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.548073129
Short name	T81
Test name
Test status
Simulation time	11557030915 ps
CPU time	56.88 seconds
Started	Apr 21 12:28:33 PM PDT 24
Finished	Apr 21 12:29:31 PM PDT 24
Peak memory	204644 kb
Host	smart-cad43e0d-657b-427e-867f-f10fc3772790
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=548073129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.548073129
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.140557380
Short name	T724
Test name
Test status
Simulation time	22927959316 ps
CPU time	112.25 seconds
Started	Apr 21 12:28:21 PM PDT 24
Finished	Apr 21 12:30:14 PM PDT 24
Peak memory	204828 kb
Host	smart-d29df8f6-fc00-4229-bd23-451a37cf49bd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=140557380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.140557380
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.793821233
Short name	T638
Test name
Test status
Simulation time	81096603 ps
CPU time	11.29 seconds
Started	Apr 21 12:29:40 PM PDT 24
Finished	Apr 21 12:29:52 PM PDT 24
Peak memory	211080 kb
Host	smart-a0154f18-c4b3-4ef0-a020-5aa4c27e9854
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793821233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.793821233
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.2829583856
Short name	T711
Test name
Test status
Simulation time	429218485 ps
CPU time	5.46 seconds
Started	Apr 21 12:29:40 PM PDT 24
Finished	Apr 21 12:29:46 PM PDT 24
Peak memory	202892 kb
Host	smart-36c14a38-e7ec-4e11-b163-1fba770b647c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2829583856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2829583856
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.1663706561
Short name	T781
Test name
Test status
Simulation time	184563207 ps
CPU time	2.95 seconds
Started	Apr 21 12:28:35 PM PDT 24
Finished	Apr 21 12:28:38 PM PDT 24
Peak memory	203336 kb
Host	smart-f98405fb-25fa-48da-a7e4-b4fff16ee6f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1663706561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1663706561
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.223123503
Short name	T345
Test name
Test status
Simulation time	11338682932 ps
CPU time	32.9 seconds
Started	Apr 21 12:28:36 PM PDT 24
Finished	Apr 21 12:29:10 PM PDT 24
Peak memory	203280 kb
Host	smart-329cfd17-0d28-41ba-b51c-bddf43b60e19
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=223123503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.223123503
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4215474482
Short name	T173
Test name
Test status
Simulation time	3053927053 ps
CPU time	21.4 seconds
Started	Apr 21 12:28:31 PM PDT 24
Finished	Apr 21 12:28:53 PM PDT 24
Peak memory	203352 kb
Host	smart-8a8b23e3-21a6-4f99-a386-d00c9d0d8254
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4215474482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4215474482
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2491736768
Short name	T141
Test name
Test status
Simulation time	29501753 ps
CPU time	2.4 seconds
Started	Apr 21 12:28:30 PM PDT 24
Finished	Apr 21 12:28:33 PM PDT 24
Peak memory	203308 kb
Host	smart-6ebb3bd8-e8b1-443e-abc9-63a27a7ae7d8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491736768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2491736768
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.4078864600
Short name	T131
Test name
Test status
Simulation time	2277298917 ps
CPU time	158.68 seconds
Started	Apr 21 12:28:27 PM PDT 24
Finished	Apr 21 12:31:06 PM PDT 24
Peak memory	209100 kb
Host	smart-902133b0-0016-4b54-91a8-a8a886651d17
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4078864600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.4078864600
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.417366390
Short name	T23
Test name
Test status
Simulation time	3955249654 ps
CPU time	75.17 seconds
Started	Apr 21 12:28:31 PM PDT 24
Finished	Apr 21 12:29:47 PM PDT 24
Peak memory	204624 kb
Host	smart-1aac20af-27af-4a84-8a1e-e4f92a0b3c5f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=417366390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.417366390
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2443495266
Short name	T29
Test name
Test status
Simulation time	824658377 ps
CPU time	321.62 seconds
Started	Apr 21 12:28:43 PM PDT 24
Finished	Apr 21 12:34:06 PM PDT 24
Peak memory	209548 kb
Host	smart-c0219459-4782-4468-b041-dec4b0646c0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2443495266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2443495266
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.286447776
Short name	T883
Test name
Test status
Simulation time	157630583 ps
CPU time	10.16 seconds
Started	Apr 21 12:28:28 PM PDT 24
Finished	Apr 21 12:28:39 PM PDT 24
Peak memory	204376 kb
Host	smart-159e4cfe-6106-4c62-a1bd-13c3197afd93
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=286447776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.286447776
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2034063109
Short name	T52
Test name
Test status
Simulation time	151833261 ps
CPU time	4.28 seconds
Started	Apr 21 12:29:39 PM PDT 24
Finished	Apr 21 12:29:44 PM PDT 24
Peak memory	202916 kb
Host	smart-5a19e436-352a-4a9d-a499-aaf14c14ca9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2034063109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2034063109
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1824408059
Short name	T103
Test name
Test status
Simulation time	282069813623 ps
CPU time	654.78 seconds
Started	Apr 21 12:28:22 PM PDT 24
Finished	Apr 21 12:39:17 PM PDT 24
Peak memory	211516 kb
Host	smart-cdce345e-ffd7-405e-b6e8-7dc75ec54271
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1824408059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.1824408059
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.724145969
Short name	T389
Test name
Test status
Simulation time	28841939 ps
CPU time	3.36 seconds
Started	Apr 21 12:28:26 PM PDT 24
Finished	Apr 21 12:28:30 PM PDT 24
Peak memory	203352 kb
Host	smart-059b34c0-703c-4c41-967d-9e12cb1faafd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=724145969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.724145969
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.2995516303
Short name	T816
Test name
Test status
Simulation time	173662039 ps
CPU time	6.17 seconds
Started	Apr 21 12:28:41 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	203256 kb
Host	smart-35ef00fc-2257-4cf2-a73e-6a215e7868aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2995516303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2995516303
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.2822982523
Short name	T118
Test name
Test status
Simulation time	269347318 ps
CPU time	4.5 seconds
Started	Apr 21 12:28:46 PM PDT 24
Finished	Apr 21 12:28:51 PM PDT 24
Peak memory	203724 kb
Host	smart-5ea37244-8d8b-483d-8073-b5facac0d933
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2822982523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2822982523
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2327982796
Short name	T267
Test name
Test status
Simulation time	12277706623 ps
CPU time	28.18 seconds
Started	Apr 21 12:28:23 PM PDT 24
Finished	Apr 21 12:28:52 PM PDT 24
Peak memory	203388 kb
Host	smart-13a2d65a-f50b-40fe-a965-85981cd0d0a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2327982796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2327982796
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2420777966
Short name	T791
Test name
Test status
Simulation time	243363368 ps
CPU time	15.67 seconds
Started	Apr 21 12:29:36 PM PDT 24
Finished	Apr 21 12:29:52 PM PDT 24
Peak memory	204184 kb
Host	smart-1e9ce939-12b8-4ccb-8275-e41705551dcc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420777966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2420777966
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.2720274967
Short name	T210
Test name
Test status
Simulation time	221670718 ps
CPU time	12.64 seconds
Started	Apr 21 12:28:33 PM PDT 24
Finished	Apr 21 12:28:46 PM PDT 24
Peak memory	203344 kb
Host	smart-0a784d46-7801-4bbe-8af6-983f6f0c33a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2720274967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2720274967
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.3281524124
Short name	T697
Test name
Test status
Simulation time	390831617 ps
CPU time	3.3 seconds
Started	Apr 21 12:29:39 PM PDT 24
Finished	Apr 21 12:29:43 PM PDT 24
Peak memory	202844 kb
Host	smart-c11b7658-fb2f-4395-aee1-fc880058589e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3281524124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3281524124
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3249308615
Short name	T330
Test name
Test status
Simulation time	11918692855 ps
CPU time	35.51 seconds
Started	Apr 21 12:28:29 PM PDT 24
Finished	Apr 21 12:29:05 PM PDT 24
Peak memory	203388 kb
Host	smart-876efd4b-81ad-49bf-b33f-71af1dbebf69
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249308615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3249308615
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2113955277
Short name	T456
Test name
Test status
Simulation time	12626538178 ps
CPU time	37.47 seconds
Started	Apr 21 12:29:44 PM PDT 24
Finished	Apr 21 12:30:22 PM PDT 24
Peak memory	203180 kb
Host	smart-6a5c6404-453d-4f19-b2e2-9f6d2c6028ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2113955277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2113955277
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.432629287
Short name	T744
Test name
Test status
Simulation time	64488203 ps
CPU time	2.26 seconds
Started	Apr 21 12:28:30 PM PDT 24
Finished	Apr 21 12:28:32 PM PDT 24
Peak memory	203336 kb
Host	smart-dc1a0f96-6c8e-4397-b47f-09777dab5a97
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432629287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.432629287
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.2203448536
Short name	T213
Test name
Test status
Simulation time	170112666 ps
CPU time	12.48 seconds
Started	Apr 21 12:28:37 PM PDT 24
Finished	Apr 21 12:28:50 PM PDT 24
Peak memory	205148 kb
Host	smart-eca243d3-1415-485e-8200-2ffc18a1d794
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2203448536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2203448536
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2631822140
Short name	T788
Test name
Test status
Simulation time	390977381 ps
CPU time	5.12 seconds
Started	Apr 21 12:28:26 PM PDT 24
Finished	Apr 21 12:28:31 PM PDT 24
Peak memory	203260 kb
Host	smart-ff0be3d2-4cb8-46a2-a6ca-9526c68c7728
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631822140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2631822140
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1464201836
Short name	T611
Test name
Test status
Simulation time	1248757619 ps
CPU time	123.55 seconds
Started	Apr 21 12:28:41 PM PDT 24
Finished	Apr 21 12:30:45 PM PDT 24
Peak memory	207920 kb
Host	smart-44a80d54-da3e-45f6-b3ea-90c7441dc0fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1464201836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1464201836
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.882461543
Short name	T41
Test name
Test status
Simulation time	2195430193 ps
CPU time	291.64 seconds
Started	Apr 21 12:28:28 PM PDT 24
Finished	Apr 21 12:33:20 PM PDT 24
Peak memory	220000 kb
Host	smart-8113ef7b-59ae-4a31-810b-4b52dc75603e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=882461543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res et_error.882461543
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3665666159
Short name	T57
Test name
Test status
Simulation time	558414993 ps
CPU time	8.48 seconds
Started	Apr 21 12:28:39 PM PDT 24
Finished	Apr 21 12:28:48 PM PDT 24
Peak memory	211476 kb
Host	smart-d4d4a191-74f2-4b7a-ae2b-05e885983c7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3665666159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3665666159
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2497700154
Short name	T599
Test name
Test status
Simulation time	183268459 ps
CPU time	14.55 seconds
Started	Apr 21 12:26:46 PM PDT 24
Finished	Apr 21 12:27:01 PM PDT 24
Peak memory	211532 kb
Host	smart-e97cd112-53b2-4df8-bc45-4d026d741a86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2497700154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2497700154
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1068628969
Short name	T268
Test name
Test status
Simulation time	144232958867 ps
CPU time	267.43 seconds
Started	Apr 21 12:26:40 PM PDT 24
Finished	Apr 21 12:31:08 PM PDT 24
Peak memory	206140 kb
Host	smart-f8ba1ee4-5289-4baa-b7b1-c8168b533b0e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1068628969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.1068628969
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4207638988
Short name	T512
Test name
Test status
Simulation time	78711233 ps
CPU time	3.16 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	203232 kb
Host	smart-0f550790-d8ee-4013-b796-a4c93925f9c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4207638988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4207638988
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.3288004331
Short name	T696
Test name
Test status
Simulation time	272317457 ps
CPU time	15.48 seconds
Started	Apr 21 12:26:50 PM PDT 24
Finished	Apr 21 12:27:06 PM PDT 24
Peak memory	203248 kb
Host	smart-b8b0de88-e410-4982-8790-cde485863859
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288004331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3288004331
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.2236471108
Short name	T521
Test name
Test status
Simulation time	812434341 ps
CPU time	11.34 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:26:59 PM PDT 24
Peak memory	204444 kb
Host	smart-5d004fd8-a1fa-42f4-bc8b-c91fa8a05b64
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2236471108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2236471108
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3526962990
Short name	T654
Test name
Test status
Simulation time	18060828084 ps
CPU time	82.56 seconds
Started	Apr 21 12:26:52 PM PDT 24
Finished	Apr 21 12:28:15 PM PDT 24
Peak memory	211488 kb
Host	smart-1e7b98dd-f197-471e-98a3-c940049f0e1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526962990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3526962990
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.217055618
Short name	T798
Test name
Test status
Simulation time	9384936978 ps
CPU time	66.86 seconds
Started	Apr 21 12:26:38 PM PDT 24
Finished	Apr 21 12:27:46 PM PDT 24
Peak memory	211552 kb
Host	smart-8b1acc88-79b3-4589-b0c8-b7dd387dfca1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=217055618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.217055618
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3423985025
Short name	T899
Test name
Test status
Simulation time	109452734 ps
CPU time	17.1 seconds
Started	Apr 21 12:26:55 PM PDT 24
Finished	Apr 21 12:27:18 PM PDT 24
Peak memory	204484 kb
Host	smart-ce420d9a-85e3-4812-b183-2e4328bd6bfd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423985025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3423985025
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.3780953088
Short name	T144
Test name
Test status
Simulation time	1416448967 ps
CPU time	22.06 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:27:22 PM PDT 24
Peak memory	203400 kb
Host	smart-c90fc85c-3514-4de0-b788-ecc6cb0d7911
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3780953088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3780953088
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.2889856542
Short name	T206
Test name
Test status
Simulation time	494104498 ps
CPU time	3.43 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	203336 kb
Host	smart-27247365-d096-4052-b43a-f54234bc66b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2889856542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2889856542
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3937614227
Short name	T851
Test name
Test status
Simulation time	5915386781 ps
CPU time	30.01 seconds
Started	Apr 21 12:26:41 PM PDT 24
Finished	Apr 21 12:27:12 PM PDT 24
Peak memory	203308 kb
Host	smart-05ce1c32-014c-4abf-b209-9cf0dca7207c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937614227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3937614227
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2771306473
Short name	T167
Test name
Test status
Simulation time	3059834356 ps
CPU time	28.37 seconds
Started	Apr 21 12:26:56 PM PDT 24
Finished	Apr 21 12:27:25 PM PDT 24
Peak memory	203324 kb
Host	smart-c6474750-7c87-4385-ade1-bf01803344af
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2771306473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2771306473
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1167396254
Short name	T780
Test name
Test status
Simulation time	55112822 ps
CPU time	2.34 seconds
Started	Apr 21 12:26:38 PM PDT 24
Finished	Apr 21 12:26:41 PM PDT 24
Peak memory	203236 kb
Host	smart-f3f1c2e2-04f3-480e-ba85-12ed4ab6cdfc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167396254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1167396254
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.589852288
Short name	T100
Test name
Test status
Simulation time	6945689937 ps
CPU time	95.5 seconds
Started	Apr 21 12:27:03 PM PDT 24
Finished	Apr 21 12:28:39 PM PDT 24
Peak memory	205744 kb
Host	smart-7c971d36-0ac9-4d4e-8e7e-77cd3c06fffc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=589852288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.589852288
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.953483850
Short name	T313
Test name
Test status
Simulation time	2191331561 ps
CPU time	119.38 seconds
Started	Apr 21 12:27:03 PM PDT 24
Finished	Apr 21 12:29:03 PM PDT 24
Peak memory	206432 kb
Host	smart-351ba824-5a40-48d7-b079-101ca6b96b09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=953483850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.953483850
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1211863194
Short name	T33
Test name
Test status
Simulation time	411126363 ps
CPU time	215.21 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:30:23 PM PDT 24
Peak memory	208540 kb
Host	smart-e4a1e165-b268-4d64-b3e6-cac2126f736c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1211863194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1211863194
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1504259710
Short name	T246
Test name
Test status
Simulation time	2498002871 ps
CPU time	217.95 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:30:40 PM PDT 24
Peak memory	220192 kb
Host	smart-66e2d9a4-563d-4a6d-8725-8b03ff021086
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1504259710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1504259710
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3290867385
Short name	T560
Test name
Test status
Simulation time	57235781 ps
CPU time	7.93 seconds
Started	Apr 21 12:27:04 PM PDT 24
Finished	Apr 21 12:27:12 PM PDT 24
Peak memory	211428 kb
Host	smart-5a2a9931-4523-4f3e-9409-f58a52c587b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3290867385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3290867385
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2533772728
Short name	T487
Test name
Test status
Simulation time	2171960111 ps
CPU time	28.37 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	211548 kb
Host	smart-6c712599-7ae8-420b-b62b-f41b7116416e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2533772728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2533772728
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3454516904
Short name	T726
Test name
Test status
Simulation time	3532201021 ps
CPU time	28.01 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	203412 kb
Host	smart-8208c73d-1247-4b35-91c1-07ca0e60d319
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3454516904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.3454516904
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1045683165
Short name	T207
Test name
Test status
Simulation time	594316643 ps
CPU time	14.03 seconds
Started	Apr 21 12:27:18 PM PDT 24
Finished	Apr 21 12:27:33 PM PDT 24
Peak memory	203896 kb
Host	smart-4d7d6615-2012-4b16-9ca8-0dabae5c4f31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1045683165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1045683165
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.1544970864
Short name	T890
Test name
Test status
Simulation time	280274073 ps
CPU time	7.6 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:26:56 PM PDT 24
Peak memory	203368 kb
Host	smart-cc545c8a-a5b3-42a8-b77e-90adae7724c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1544970864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1544970864
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.3039779990
Short name	T61
Test name
Test status
Simulation time	1406380463 ps
CPU time	17.16 seconds
Started	Apr 21 12:26:44 PM PDT 24
Finished	Apr 21 12:27:02 PM PDT 24
Peak memory	204600 kb
Host	smart-5a71965f-7aae-44f7-a407-c9e6b034ead9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3039779990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3039779990
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2690576850
Short name	T576
Test name
Test status
Simulation time	25511833375 ps
CPU time	147.7 seconds
Started	Apr 21 12:26:41 PM PDT 24
Finished	Apr 21 12:29:10 PM PDT 24
Peak memory	211476 kb
Host	smart-d5ff8f2c-c10d-4118-8998-939ce137c407
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690576850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2690576850
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2147501641
Short name	T225
Test name
Test status
Simulation time	25457420040 ps
CPU time	207.33 seconds
Started	Apr 21 12:26:58 PM PDT 24
Finished	Apr 21 12:30:26 PM PDT 24
Peak memory	211568 kb
Host	smart-0a555847-9ff5-4ed4-bbee-9cce00f2e9d0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2147501641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2147501641
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3715894965
Short name	T302
Test name
Test status
Simulation time	351708320 ps
CPU time	27.63 seconds
Started	Apr 21 12:26:56 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	205132 kb
Host	smart-be75a27f-d1ef-4825-93c1-fd687d655e6a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715894965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3715894965
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.2862262286
Short name	T284
Test name
Test status
Simulation time	323325178 ps
CPU time	5.3 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:26:45 PM PDT 24
Peak memory	203384 kb
Host	smart-2788734e-5b9f-4117-a8bb-6a18296d73ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2862262286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2862262286
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.3246511313
Short name	T604
Test name
Test status
Simulation time	27493777 ps
CPU time	2.13 seconds
Started	Apr 21 12:26:46 PM PDT 24
Finished	Apr 21 12:26:49 PM PDT 24
Peak memory	203344 kb
Host	smart-f94ab08b-a79b-408e-8417-04106f76bfcb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3246511313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3246511313
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3619986001
Short name	T831
Test name
Test status
Simulation time	5103046544 ps
CPU time	25.32 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203324 kb
Host	smart-1ba129eb-7269-4e0d-ba3d-571989af4d78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619986001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3619986001
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1135015974
Short name	T304
Test name
Test status
Simulation time	4641690662 ps
CPU time	26.63 seconds
Started	Apr 21 12:27:02 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	203336 kb
Host	smart-18fcd01b-f249-47e3-85a9-6f7d31e02b84
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1135015974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1135015974
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.974468993
Short name	T322
Test name
Test status
Simulation time	95186115 ps
CPU time	2.51 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:26:56 PM PDT 24
Peak memory	203248 kb
Host	smart-286c9d09-860c-4030-b85b-0c51cfbb75b0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974468993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.974468993
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.2864407034
Short name	T566
Test name
Test status
Simulation time	3938898573 ps
CPU time	59.18 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:27:39 PM PDT 24
Peak memory	206684 kb
Host	smart-b5e97c2a-273e-4247-85b5-2e7c4d793a57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2864407034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2864407034
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3638919778
Short name	T580
Test name
Test status
Simulation time	7992619515 ps
CPU time	201.73 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:30:10 PM PDT 24
Peak memory	206800 kb
Host	smart-031c9cda-f8da-4df5-ba86-b515616deb7c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3638919778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3638919778
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2098493795
Short name	T241
Test name
Test status
Simulation time	323329130 ps
CPU time	157.2 seconds
Started	Apr 21 12:26:52 PM PDT 24
Finished	Apr 21 12:29:30 PM PDT 24
Peak memory	208992 kb
Host	smart-1196d61c-042a-4437-8b40-9ccf76e1578a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2098493795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.2098493795
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1554217008
Short name	T401
Test name
Test status
Simulation time	65696982 ps
CPU time	10.82 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:27:05 PM PDT 24
Peak memory	203700 kb
Host	smart-3490c1e5-53d2-43e0-af04-6f9abb627af3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1554217008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1554217008
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2626809916
Short name	T68
Test name
Test status
Simulation time	161423499 ps
CPU time	5.88 seconds
Started	Apr 21 12:26:57 PM PDT 24
Finished	Apr 21 12:27:04 PM PDT 24
Peak memory	204364 kb
Host	smart-08481dc4-a298-4fd4-b40d-1dbc70196e49
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2626809916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2626809916
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1830383410
Short name	T775
Test name
Test status
Simulation time	4622635223 ps
CPU time	49.72 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:27:50 PM PDT 24
Peak memory	211496 kb
Host	smart-0dd475d2-d2f3-4ea4-9e89-e7ec7984fefe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1830383410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1830383410
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4085199633
Short name	T349
Test name
Test status
Simulation time	30029291108 ps
CPU time	254.65 seconds
Started	Apr 21 12:26:46 PM PDT 24
Finished	Apr 21 12:31:02 PM PDT 24
Peak memory	211596 kb
Host	smart-99419464-b3bd-4d9c-b667-520dee372369
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4085199633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.4085199633
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3503313253
Short name	T338
Test name
Test status
Simulation time	973587538 ps
CPU time	25.81 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	203972 kb
Host	smart-7c73d388-dfe2-40ec-b78a-54b4faaa8138
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3503313253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3503313253
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.3843503753
Short name	T627
Test name
Test status
Simulation time	132597018 ps
CPU time	10.86 seconds
Started	Apr 21 12:26:39 PM PDT 24
Finished	Apr 21 12:26:50 PM PDT 24
Peak memory	203252 kb
Host	smart-b0649621-460e-4e95-8041-4e60aedfef05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843503753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3843503753
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.757790263
Short name	T228
Test name
Test status
Simulation time	354224068 ps
CPU time	11.21 seconds
Started	Apr 21 12:27:05 PM PDT 24
Finished	Apr 21 12:27:17 PM PDT 24
Peak memory	211500 kb
Host	smart-3f5613b6-6efc-4426-8376-3bf737eac3b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=757790263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.757790263
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3665780076
Short name	T140
Test name
Test status
Simulation time	38907707893 ps
CPU time	232.79 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:30:46 PM PDT 24
Peak memory	211496 kb
Host	smart-5d5e748e-929d-4606-afdc-4de3b2b9a187
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665780076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3665780076
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3967866024
Short name	T524
Test name
Test status
Simulation time	2270743253 ps
CPU time	23.15 seconds
Started	Apr 21 12:26:38 PM PDT 24
Finished	Apr 21 12:27:02 PM PDT 24
Peak memory	203312 kb
Host	smart-ab90212f-8bdb-4528-9bfe-632409eb9255
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3967866024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3967866024
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3205182552
Short name	T357
Test name
Test status
Simulation time	209739931 ps
CPU time	5.31 seconds
Started	Apr 21 12:26:47 PM PDT 24
Finished	Apr 21 12:26:52 PM PDT 24
Peak memory	211420 kb
Host	smart-7ee08d16-4908-484b-a8a4-bbb4614098e6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205182552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3205182552
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.2619892260
Short name	T446
Test name
Test status
Simulation time	376972831 ps
CPU time	4.41 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:26:55 PM PDT 24
Peak memory	203360 kb
Host	smart-e32c9409-74e7-4e64-94ad-d008a340b408
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2619892260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2619892260
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.1775633410
Short name	T502
Test name
Test status
Simulation time	128427462 ps
CPU time	3.39 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:26:55 PM PDT 24
Peak memory	203232 kb
Host	smart-72ede95e-dcad-4d5f-9783-2062ac822631
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1775633410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1775633410
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.253904458
Short name	T843
Test name
Test status
Simulation time	7969537157 ps
CPU time	34.48 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203316 kb
Host	smart-c22a0d85-1ea3-4b51-9245-91c8b287b5eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=253904458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.253904458
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3909981827
Short name	T819
Test name
Test status
Simulation time	8984993986 ps
CPU time	33.23 seconds
Started	Apr 21 12:27:06 PM PDT 24
Finished	Apr 21 12:27:39 PM PDT 24
Peak memory	203408 kb
Host	smart-d6eb041a-3741-4525-95b8-ae6a4180957d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3909981827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3909981827
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3585840046
Short name	T733
Test name
Test status
Simulation time	34324832 ps
CPU time	2.26 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:26:56 PM PDT 24
Peak memory	203224 kb
Host	smart-a94a2502-4269-486a-a311-1a9f4f6c7841
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585840046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3585840046
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.612992361
Short name	T129
Test name
Test status
Simulation time	3869755191 ps
CPU time	138.22 seconds
Started	Apr 21 12:26:50 PM PDT 24
Finished	Apr 21 12:29:09 PM PDT 24
Peak memory	208344 kb
Host	smart-418241ef-f3e7-4ab2-aae2-49960b0f2e24
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=612992361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.612992361
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1780607778
Short name	T689
Test name
Test status
Simulation time	2749692774 ps
CPU time	61.01 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:27:49 PM PDT 24
Peak memory	205848 kb
Host	smart-d2b969e9-c446-436e-93e7-396b83e47a56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1780607778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1780607778
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1744602244
Short name	T778
Test name
Test status
Simulation time	775173968 ps
CPU time	259.31 seconds
Started	Apr 21 12:26:50 PM PDT 24
Finished	Apr 21 12:31:10 PM PDT 24
Peak memory	209688 kb
Host	smart-d09e585a-81a0-4315-9c43-75a3213d56eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1744602244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1744602244
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3760486943
Short name	T602
Test name
Test status
Simulation time	245525271 ps
CPU time	65.43 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:27:57 PM PDT 24
Peak memory	207224 kb
Host	smart-e530a35b-3dc0-4166-b046-013889961630
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3760486943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.3760486943
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2931412374
Short name	T152
Test name
Test status
Simulation time	1301359321 ps
CPU time	16.05 seconds
Started	Apr 21 12:27:12 PM PDT 24
Finished	Apr 21 12:27:29 PM PDT 24
Peak memory	204808 kb
Host	smart-0cf13d98-7ea9-489f-9a87-ffca7f467e20
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2931412374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2931412374
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3166125562
Short name	T120
Test name
Test status
Simulation time	214031501 ps
CPU time	6.5 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:27:08 PM PDT 24
Peak memory	203348 kb
Host	smart-881ac9db-1a7b-40e9-b993-8498644b251f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3166125562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3166125562
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2720418641
Short name	T773
Test name
Test status
Simulation time	18502322593 ps
CPU time	175.22 seconds
Started	Apr 21 12:27:24 PM PDT 24
Finished	Apr 21 12:30:20 PM PDT 24
Peak memory	211600 kb
Host	smart-c63f6b84-58c0-4239-89d2-d30a414bf101
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2720418641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.2720418641
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3959388906
Short name	T806
Test name
Test status
Simulation time	496096489 ps
CPU time	10.65 seconds
Started	Apr 21 12:26:47 PM PDT 24
Finished	Apr 21 12:26:58 PM PDT 24
Peak memory	203512 kb
Host	smart-2e025eed-baed-4973-9fa6-789eaf1dd1c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3959388906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3959388906
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.3546180363
Short name	T359
Test name
Test status
Simulation time	1193189699 ps
CPU time	21.87 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:27:15 PM PDT 24
Peak memory	203360 kb
Host	smart-d92fff2b-8da9-4db4-a262-d42c1b9c2235
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3546180363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3546180363
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.2472377880
Short name	T69
Test name
Test status
Simulation time	75101942 ps
CPU time	2.4 seconds
Started	Apr 21 12:27:09 PM PDT 24
Finished	Apr 21 12:27:12 PM PDT 24
Peak memory	203356 kb
Host	smart-21859d0d-df4c-43ff-8655-5464447dbbf7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2472377880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2472377880
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.603891803
Short name	T43
Test name
Test status
Simulation time	245544975053 ps
CPU time	373.66 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:33:14 PM PDT 24
Peak memory	211536 kb
Host	smart-e3203e36-06e8-4130-bf4a-bb529d67ae7d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=603891803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.603891803
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1470189658
Short name	T485
Test name
Test status
Simulation time	6759306710 ps
CPU time	47.98 seconds
Started	Apr 21 12:27:00 PM PDT 24
Finished	Apr 21 12:27:48 PM PDT 24
Peak memory	211516 kb
Host	smart-3f129a09-3f97-4c7a-b033-8898ae3a24d0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1470189658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1470189658
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3919478206
Short name	T365
Test name
Test status
Simulation time	217094252 ps
CPU time	21.2 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:27:30 PM PDT 24
Peak memory	211536 kb
Host	smart-80ab8500-df6a-4aa4-8940-d5d5645c82db
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919478206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3919478206
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.2059405738
Short name	T455
Test name
Test status
Simulation time	98876568 ps
CPU time	3.64 seconds
Started	Apr 21 12:26:44 PM PDT 24
Finished	Apr 21 12:26:48 PM PDT 24
Peak memory	203312 kb
Host	smart-abd14bc8-ad06-4d6a-b901-76408b65c1a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2059405738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2059405738
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.690299874
Short name	T645
Test name
Test status
Simulation time	448391360 ps
CPU time	4.3 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:27:06 PM PDT 24
Peak memory	203252 kb
Host	smart-4ee07325-9082-4148-962e-e516fed5f1b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=690299874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.690299874
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1688929288
Short name	T748
Test name
Test status
Simulation time	7009302304 ps
CPU time	25.14 seconds
Started	Apr 21 12:26:53 PM PDT 24
Finished	Apr 21 12:27:19 PM PDT 24
Peak memory	203312 kb
Host	smart-87eeb116-0dc8-44a3-b058-f1390c405e5d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688929288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1688929288
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.4060490584
Short name	T514
Test name
Test status
Simulation time	14691852838 ps
CPU time	35.09 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203396 kb
Host	smart-1187684a-6016-4837-a26c-88cc1a897aa8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4060490584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4060490584
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3588424055
Short name	T404
Test name
Test status
Simulation time	120775678 ps
CPU time	2.01 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:26:53 PM PDT 24
Peak memory	203236 kb
Host	smart-99815215-5744-4573-af86-6411821dcd02
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588424055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3588424055
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.412636802
Short name	T849
Test name
Test status
Simulation time	1541541040 ps
CPU time	149.09 seconds
Started	Apr 21 12:26:35 PM PDT 24
Finished	Apr 21 12:29:05 PM PDT 24
Peak memory	211556 kb
Host	smart-dcbdefdb-9412-43b2-9a72-9d6e4370bc9d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=412636802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.412636802
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1239731026
Short name	T548
Test name
Test status
Simulation time	934468681 ps
CPU time	79.12 seconds
Started	Apr 21 12:26:59 PM PDT 24
Finished	Apr 21 12:28:19 PM PDT 24
Peak memory	206044 kb
Host	smart-b7d26331-b96c-46f2-a918-daa3f387245e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1239731026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1239731026
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3975883240
Short name	T505
Test name
Test status
Simulation time	1344182080 ps
CPU time	184.26 seconds
Started	Apr 21 12:27:05 PM PDT 24
Finished	Apr 21 12:30:10 PM PDT 24
Peak memory	208568 kb
Host	smart-fc6c46e5-8f08-4d8f-9dc7-2c5c15254237
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3975883240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3975883240
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1914170910
Short name	T368
Test name
Test status
Simulation time	6387969023 ps
CPU time	343.67 seconds
Started	Apr 21 12:26:40 PM PDT 24
Finished	Apr 21 12:32:24 PM PDT 24
Peak memory	219708 kb
Host	smart-36dbc44d-7ebf-46c7-a61e-b53e1421bce0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1914170910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1914170910
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1580998245
Short name	T838
Test name
Test status
Simulation time	404698475 ps
CPU time	7.4 seconds
Started	Apr 21 12:26:52 PM PDT 24
Finished	Apr 21 12:27:00 PM PDT 24
Peak memory	204704 kb
Host	smart-f6e1db90-0b36-4f24-af3d-ea2a7bb487c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1580998245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1580998245
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.308134421
Short name	T362
Test name
Test status
Simulation time	495777217 ps
CPU time	32.35 seconds
Started	Apr 21 12:26:50 PM PDT 24
Finished	Apr 21 12:27:23 PM PDT 24
Peak memory	211444 kb
Host	smart-a6e31e72-1c7b-4ff7-bc9b-992505f3198b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=308134421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.308134421
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.542610484
Short name	T450
Test name
Test status
Simulation time	61253193288 ps
CPU time	203.06 seconds
Started	Apr 21 12:26:56 PM PDT 24
Finished	Apr 21 12:30:19 PM PDT 24
Peak memory	206216 kb
Host	smart-64747c42-abb5-42fa-8e5d-e2f74014010e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=542610484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow _rsp.542610484
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1208129429
Short name	T784
Test name
Test status
Simulation time	2297981275 ps
CPU time	32.41 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	204312 kb
Host	smart-521fbc78-d56b-445e-b63c-ee2523ad8afc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1208129429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1208129429
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.191855350
Short name	T623
Test name
Test status
Simulation time	346229270 ps
CPU time	14.32 seconds
Started	Apr 21 12:27:01 PM PDT 24
Finished	Apr 21 12:27:16 PM PDT 24
Peak memory	203300 kb
Host	smart-68ee7b8b-a54e-4dad-b47c-69a2aa8c73f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=191855350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.191855350
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.459057718
Short name	T740
Test name
Test status
Simulation time	113648706 ps
CPU time	15.32 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:27:24 PM PDT 24
Peak memory	204584 kb
Host	smart-ac8c76f6-3d6b-4046-8a42-f66541f7f7d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=459057718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.459057718
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.267375300
Short name	T878
Test name
Test status
Simulation time	135700054006 ps
CPU time	179.04 seconds
Started	Apr 21 12:27:13 PM PDT 24
Finished	Apr 21 12:30:12 PM PDT 24
Peak memory	204764 kb
Host	smart-8508de8b-e1cf-4b12-98a1-371cb9820fc9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=267375300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.267375300
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.4293563660
Short name	T815
Test name
Test status
Simulation time	82354093154 ps
CPU time	279.35 seconds
Started	Apr 21 12:26:58 PM PDT 24
Finished	Apr 21 12:31:37 PM PDT 24
Peak memory	204492 kb
Host	smart-8038b1cf-1a70-4cde-9b86-a9d939384967
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4293563660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.4293563660
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3079806408
Short name	T844
Test name
Test status
Simulation time	188404359 ps
CPU time	25.02 seconds
Started	Apr 21 12:27:02 PM PDT 24
Finished	Apr 21 12:27:27 PM PDT 24
Peak memory	211528 kb
Host	smart-18b26d58-cab8-43c6-88f9-05b46b86a340
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079806408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3079806408
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.3968635837
Short name	T556
Test name
Test status
Simulation time	1510103892 ps
CPU time	33.54 seconds
Started	Apr 21 12:26:57 PM PDT 24
Finished	Apr 21 12:27:31 PM PDT 24
Peak memory	203252 kb
Host	smart-f8e11c24-57c9-45d4-aa96-22f3b1971dbe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3968635837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3968635837
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.2066573167
Short name	T757
Test name
Test status
Simulation time	115805137 ps
CPU time	3.06 seconds
Started	Apr 21 12:27:04 PM PDT 24
Finished	Apr 21 12:27:08 PM PDT 24
Peak memory	203228 kb
Host	smart-f81069e9-3303-499d-bf28-7566633c2f43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2066573167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2066573167
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3102457820
Short name	T737
Test name
Test status
Simulation time	10899378287 ps
CPU time	28.84 seconds
Started	Apr 21 12:27:05 PM PDT 24
Finished	Apr 21 12:27:35 PM PDT 24
Peak memory	203316 kb
Host	smart-0b462091-1bb9-4060-b7cc-e14de166736c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102457820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3102457820
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.469544665
Short name	T565
Test name
Test status
Simulation time	8543824269 ps
CPU time	25.05 seconds
Started	Apr 21 12:26:48 PM PDT 24
Finished	Apr 21 12:27:14 PM PDT 24
Peak memory	203312 kb
Host	smart-1f57de61-6793-4502-959d-3a316972c34b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=469544665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.469544665
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.958433599
Short name	T678
Test name
Test status
Simulation time	40224946 ps
CPU time	2.12 seconds
Started	Apr 21 12:26:52 PM PDT 24
Finished	Apr 21 12:26:55 PM PDT 24
Peak memory	203268 kb
Host	smart-23ac45aa-6152-4f58-ad9a-73dd8a6d10f4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958433599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.958433599
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.1387016110
Short name	T171
Test name
Test status
Simulation time	924115710 ps
CPU time	89.59 seconds
Started	Apr 21 12:26:51 PM PDT 24
Finished	Apr 21 12:28:21 PM PDT 24
Peak memory	211472 kb
Host	smart-190042cd-7f89-4cc6-a823-c93a0c2e06c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1387016110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1387016110
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3246886260
Short name	T443
Test name
Test status
Simulation time	7154578403 ps
CPU time	113.79 seconds
Started	Apr 21 12:26:47 PM PDT 24
Finished	Apr 21 12:28:41 PM PDT 24
Peak memory	208320 kb
Host	smart-d7998ec6-cb42-4cc4-850f-70b37782738f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3246886260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3246886260
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1604250791
Short name	T217
Test name
Test status
Simulation time	2502859007 ps
CPU time	576.77 seconds
Started	Apr 21 12:27:08 PM PDT 24
Finished	Apr 21 12:36:46 PM PDT 24
Peak memory	209824 kb
Host	smart-0c0dd6a5-2de1-41a7-a756-f04af5fe3a1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1604250791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1604250791
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3983033622
Short name	T26
Test name
Test status
Simulation time	7361556464 ps
CPU time	151.5 seconds
Started	Apr 21 12:27:20 PM PDT 24
Finished	Apr 21 12:29:52 PM PDT 24
Peak memory	210108 kb
Host	smart-53783167-8190-4a98-a0a8-5988f05c8ceb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3983033622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.3983033622
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4236018518
Short name	T517
Test name
Test status
Simulation time	105320912 ps
CPU time	11.61 seconds
Started	Apr 21 12:27:06 PM PDT 24
Finished	Apr 21 12:27:19 PM PDT 24
Peak memory	211448 kb
Host	smart-fdd0ff8f-864a-4dad-88c3-cfbdf7142dbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4236018518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4236018518
Directory	/workspace/9.xbar_unmapped_addr/latest