Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1755	1			T3	30		T11	16		T15	18
all_values[1]	1759	1			T3	43		T11	7		T15	16
all_values[2]	1739	1			T3	29		T11	8		T14	3
all_values[3]	1748	1			T3	36		T11	5		T14	2
all_values[4]	1817	1			T3	39		T11	6		T14	1
all_values[5]	1719	1			T3	21		T11	5		T14	1
all_values[6]	1791	1			T3	28		T11	8		T14	3
all_values[7]	1758	1			T3	32		T11	8		T15	22
all_values[8]	1711	1			T3	30		T11	11		T14	2
all_values[9]	1698	1			T3	23		T11	16		T14	1
all_values[10]	1827	1			T3	30		T11	14		T14	1
all_values[11]	1885	1			T3	23		T11	8		T15	18
all_values[12]	1806	1			T3	37		T11	15		T15	22
all_values[13]	1795	1			T3	29		T11	8		T14	1
all_values[14]	1805	1			T3	30		T11	10		T15	13
all_values[15]	1794	1			T3	30		T11	8		T14	2
all_values[16]	1702	1			T3	36		T11	9		T15	12
all_values[17]	1833	1			T3	30		T11	11		T14	2
all_values[18]	1725	1			T3	34		T11	19		T14	1
all_values[19]	1776	1			T3	33		T11	9		T15	17
all_values[20]	1809	1			T3	31		T11	12		T14	1
all_values[21]	1842	1			T3	28		T11	13		T15	21
all_values[22]	1809	1			T3	28		T11	9		T14	2
all_values[23]	1810	1			T3	24		T11	17		T15	16
all_values[24]	1761	1			T3	27		T11	11		T14	1
all_values[25]	1756	1			T3	40		T11	7		T14	2
all_values[26]	1713	1			T3	34		T11	15		T14	1
all_values[27]	1699	1			T3	31		T11	6		T15	21
all_values[28]	1666	1			T3	20		T11	9		T14	1
all_values[29]	1763	1			T3	34		T11	9		T15	17
all_values[30]	1801	1			T3	41		T11	14		T14	1
all_values[31]	1830	1			T3	32		T11	11		T14	1
all_values[32]	1771	1			T3	26		T11	14		T14	5
all_values[33]	1770	1			T3	32		T11	15		T14	1
all_values[34]	1810	1			T3	31		T11	13		T14	1
all_values[35]	1739	1			T3	28		T11	14		T14	1
all_values[36]	1743	1			T3	24		T11	9		T15	11
all_values[37]	1732	1			T3	23		T11	12		T14	1
all_values[38]	1767	1			T3	34		T11	10		T14	1
all_values[39]	1821	1			T3	30		T11	11		T14	2
all_values[40]	1743	1			T3	36		T11	11		T14	1
all_values[41]	1804	1			T3	32		T11	8		T15	16
all_values[42]	1836	1			T3	34		T11	12		T14	2
all_values[43]	1760	1			T3	36		T11	13		T14	2
all_values[44]	1846	1			T3	30		T11	12		T15	10
all_values[45]	1784	1			T3	25		T11	7		T14	2
all_values[46]	1773	1			T3	35		T11	10		T14	1
all_values[47]	1776	1			T3	30		T11	9		T14	2
all_values[48]	1781	1			T3	32		T11	7		T15	14
all_values[49]	1680	1			T3	21		T11	4		T15	16
all_values[50]	1711	1			T3	26		T11	14		T14	1
all_values[51]	1830	1			T3	29		T11	14		T15	15
all_values[52]	1775	1			T3	28		T11	11		T15	21
all_values[53]	1795	1			T3	33		T11	12		T15	15
all_values[54]	1775	1			T3	23		T11	6		T14	1
all_values[55]	1784	1			T3	28		T11	16		T14	1
all_values[56]	1771	1			T3	31		T11	8		T14	3
all_values[57]	1732	1			T3	27		T11	9		T15	12
all_values[58]	1873	1			T3	30		T11	12		T14	3
all_values[59]	1770	1			T3	28		T11	12		T14	1
all_values[60]	1845	1			T3	32		T11	15		T14	2
all_values[61]	1741	1			T3	22		T11	9		T14	1
all_values[62]	1735	1			T3	23		T11	9		T14	2
all_values[63]	1767	1			T3	31		T11	15		T14	1