Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1804	1			T9	3		T19	27		T53	6
all_values[1]	1863	1			T9	7		T10	4		T19	27
all_values[2]	1728	1			T9	3		T10	1		T19	26
all_values[3]	1777	1			T9	3		T10	5		T19	36
all_values[4]	1766	1			T9	2		T10	4		T19	33
all_values[5]	1822	1			T9	8		T10	4		T19	26
all_values[6]	1822	1			T9	5		T10	4		T19	14
all_values[7]	1785	1			T9	6		T10	3		T19	25
all_values[8]	1790	1			T9	2		T10	3		T19	18
all_values[9]	1844	1			T9	5		T10	5		T19	26
all_values[10]	1778	1			T9	1		T19	28		T53	2
all_values[11]	1771	1			T9	5		T10	1		T19	23
all_values[12]	1805	1			T9	3		T19	32		T53	4
all_values[13]	1769	1			T9	5		T10	3		T19	39
all_values[14]	1867	1			T9	1		T10	1		T19	28
all_values[15]	1820	1			T9	5		T10	4		T19	29
all_values[16]	1858	1			T9	5		T10	1		T19	21
all_values[17]	1829	1			T9	3		T10	2		T19	34
all_values[18]	1855	1			T9	3		T10	3		T19	24
all_values[19]	1803	1			T9	4		T10	3		T19	31
all_values[20]	1767	1			T9	3		T10	1		T19	33
all_values[21]	1768	1			T9	4		T10	2		T19	26
all_values[22]	1790	1			T9	6		T10	2		T19	32
all_values[23]	1795	1			T9	6		T10	5		T19	38
all_values[24]	1773	1			T9	5		T10	4		T19	26
all_values[25]	1780	1			T9	2		T10	2		T19	25
all_values[26]	1779	1			T9	4		T10	4		T19	32
all_values[27]	1845	1			T9	7		T10	1		T19	25
all_values[28]	1742	1			T9	4		T10	1		T19	30
all_values[29]	1839	1			T9	1		T10	3		T19	31
all_values[30]	1848	1			T9	4		T10	2		T19	36
all_values[31]	1809	1			T9	6		T19	28		T53	5
all_values[32]	1897	1			T9	4		T10	4		T19	30
all_values[33]	1778	1			T9	8		T10	4		T19	21
all_values[34]	1819	1			T9	8		T10	2		T19	24
all_values[35]	1845	1			T9	4		T19	22		T53	5
all_values[36]	1803	1			T9	2		T10	5		T19	29
all_values[37]	1772	1			T9	5		T10	2		T19	31
all_values[38]	1757	1			T9	6		T10	4		T19	25
all_values[39]	1794	1			T9	5		T10	4		T19	24
all_values[40]	1933	1			T9	6		T10	4		T19	26
all_values[41]	1803	1			T9	3		T10	3		T19	22
all_values[42]	1882	1			T9	2		T10	2		T19	32
all_values[43]	1807	1			T9	4		T10	3		T19	22
all_values[44]	1795	1			T9	5		T10	2		T19	27
all_values[45]	1876	1			T9	6		T10	2		T19	32
all_values[46]	1810	1			T9	6		T19	26		T53	2
all_values[47]	1769	1			T9	5		T10	1		T19	30
all_values[48]	1895	1			T9	5		T10	2		T19	30
all_values[49]	1804	1			T9	3		T19	31		T53	7
all_values[50]	1761	1			T9	6		T10	1		T19	25
all_values[51]	1813	1			T9	10		T10	2		T19	23
all_values[52]	1839	1			T9	4		T10	1		T19	34
all_values[53]	1852	1			T9	2		T10	2		T19	24
all_values[54]	1826	1			T9	2		T10	1		T19	32
all_values[55]	1814	1			T9	1		T10	4		T19	23
all_values[56]	1825	1			T9	6		T10	1		T19	25
all_values[57]	1762	1			T9	6		T10	3		T19	32
all_values[58]	1792	1			T9	6		T19	26		T53	2
all_values[59]	1734	1			T9	2		T10	3		T19	36
all_values[60]	1818	1			T9	4		T10	4		T19	34
all_values[61]	1761	1			T9	5		T10	4		T19	26
all_values[62]	1777	1			T9	5		T10	5		T19	29
all_values[63]	1777	1			T9	2		T10	3		T19	34