Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 453 1 T1 3 T10 1 T16 1
all_values[1] 486 1 T1 2 T2 2 T16 1
all_values[2] 503 1 T1 4 T2 1 T19 2
all_values[3] 507 1 T1 1 T10 1 T19 3
all_values[4] 495 1 T1 3 T16 1 T17 1
all_values[5] 502 1 T1 3 T17 1 T19 1
all_values[6] 514 1 T1 2 T2 2 T10 2
all_values[7] 475 1 T1 2 T2 1 T10 1
all_values[8] 501 1 T1 3 T10 1 T16 1
all_values[9] 456 1 T1 3 T2 1 T16 2
all_values[10] 523 1 T1 2 T19 1 T31 12
all_values[11] 508 1 T1 1 T2 1 T15 2
all_values[12] 467 1 T1 2 T2 1 T19 5
all_values[13] 499 1 T1 1 T10 1 T15 2
all_values[14] 494 1 T1 5 T2 2 T10 1
all_values[15] 455 1 T1 4 T19 2 T31 7
all_values[16] 510 1 T1 2 T10 1 T15 1
all_values[17] 542 1 T1 4 T15 2 T16 1
all_values[18] 512 1 T1 3 T2 1 T16 1
all_values[19] 471 1 T1 2 T10 3 T15 1
all_values[20] 454 1 T1 1 T2 1 T19 9
all_values[21] 456 1 T1 4 T15 1 T16 1
all_values[22] 512 1 T2 1 T15 1 T16 1
all_values[23] 505 1 T1 5 T15 1 T16 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%