Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1658	1			T1	5		T4	1		T17	2
all_values[1]	1751	1			T1	2		T4	1		T17	2
all_values[2]	1628	1			T1	6		T4	1		T17	7
all_values[3]	1713	1			T1	11		T4	1		T18	1
all_values[4]	1753	1			T1	4		T17	1		T19	19
all_values[5]	1720	1			T1	7		T17	1		T18	1
all_values[6]	1714	1			T1	4		T4	2		T17	2
all_values[7]	1704	1			T1	2		T4	1		T17	1
all_values[8]	1743	1			T1	5		T4	1		T17	5
all_values[9]	1640	1			T1	9		T4	1		T17	3
all_values[10]	1729	1			T1	6		T4	1		T17	2
all_values[11]	1708	1			T1	8		T17	2		T18	1
all_values[12]	1742	1			T1	8		T4	2		T17	2
all_values[13]	1695	1			T1	6		T17	1		T18	1
all_values[14]	1763	1			T1	4		T4	1		T17	3
all_values[15]	1687	1			T1	2		T17	2		T19	23
all_values[16]	1726	1			T1	1		T4	2		T17	2
all_values[17]	1752	1			T1	4		T4	1		T17	1
all_values[18]	1744	1			T1	6		T4	1		T17	1
all_values[19]	1685	1			T1	4		T19	16		T31	21
all_values[20]	1786	1			T1	7		T4	2		T17	3
all_values[21]	1708	1			T1	3		T17	1		T19	19
all_values[22]	1798	1			T1	4		T4	2		T18	1
all_values[23]	1686	1			T1	7		T17	4		T18	1
all_values[24]	1654	1			T1	5		T4	3		T17	2
all_values[25]	1691	1			T1	7		T4	2		T17	2
all_values[26]	1713	1			T1	7		T4	1		T17	2
all_values[27]	1766	1			T1	7		T4	1		T17	1
all_values[28]	1767	1			T1	6		T4	2		T19	23
all_values[29]	1665	1			T1	8		T4	1		T17	5
all_values[30]	1725	1			T1	3		T4	2		T17	2
all_values[31]	1758	1			T1	5		T4	1		T19	17
all_values[32]	1712	1			T1	6		T4	2		T17	5
all_values[33]	1757	1			T1	6		T17	3		T19	22
all_values[34]	1778	1			T1	5		T17	2		T19	22
all_values[35]	1747	1			T1	7		T17	6		T19	18
all_values[36]	1760	1			T1	8		T4	2		T17	1
all_values[37]	1714	1			T1	6		T4	1		T17	2
all_values[38]	1713	1			T1	5		T4	3		T17	1
all_values[39]	1762	1			T1	4		T4	2		T17	2
all_values[40]	1727	1			T1	12		T17	2		T19	15
all_values[41]	1675	1			T1	6		T4	1		T17	6
all_values[42]	1763	1			T1	7		T4	1		T17	1
all_values[43]	1665	1			T1	5		T4	1		T17	2
all_values[44]	1737	1			T1	6		T4	1		T19	11
all_values[45]	1716	1			T1	6		T4	1		T17	2
all_values[46]	1768	1			T1	6		T4	1		T17	1
all_values[47]	1730	1			T1	6		T17	1		T19	14
all_values[48]	1820	1			T1	4		T17	1		T19	21
all_values[49]	1732	1			T1	4		T17	2		T19	29
all_values[50]	1758	1			T1	8		T17	2		T19	24
all_values[51]	1757	1			T1	7		T4	4		T17	1
all_values[52]	1649	1			T1	9		T4	1		T17	4
all_values[53]	1732	1			T1	5		T4	3		T17	3
all_values[54]	1743	1			T1	4		T17	2		T19	21
all_values[55]	1723	1			T1	4		T4	2		T17	2
all_values[56]	1732	1			T1	3		T4	1		T17	2
all_values[57]	1732	1			T1	5		T17	1		T19	17
all_values[58]	1643	1			T1	4		T17	2		T18	1
all_values[59]	1729	1			T1	6		T17	2		T19	18
all_values[60]	1685	1			T1	9		T17	1		T19	17
all_values[61]	1732	1			T1	5		T17	3		T19	22
all_values[62]	1695	1			T1	7		T17	2		T19	12
all_values[63]	1748	1			T1	8		T17	2		T19	17