Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	99.26	88.92	98.80		95.88	99.26	100.00

Total test records in report: 900

T758	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3787066110	Apr 28 12:47:19 PM PDT 24	Apr 28 12:50:34 PM PDT 24	590843042 ps
T759	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2286668502	Apr 28 12:46:51 PM PDT 24	Apr 28 12:47:43 PM PDT 24	135986037 ps
T760	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1062294841	Apr 28 12:48:03 PM PDT 24	Apr 28 12:48:32 PM PDT 24	896873885 ps
T761	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2531336117	Apr 28 12:46:48 PM PDT 24	Apr 28 12:46:58 PM PDT 24	763292831 ps
T762	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3193947932	Apr 28 12:48:53 PM PDT 24	Apr 28 12:49:42 PM PDT 24	13441751099 ps
T763	/workspace/coverage/xbar_build_mode/0.xbar_random.3559620465	Apr 28 12:47:01 PM PDT 24	Apr 28 12:47:08 PM PDT 24	322951089 ps
T764	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.470176282	Apr 28 12:47:31 PM PDT 24	Apr 28 12:51:11 PM PDT 24	7473880609 ps
T765	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2578390107	Apr 28 12:47:08 PM PDT 24	Apr 28 12:50:07 PM PDT 24	4036434107 ps
T766	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2192406393	Apr 28 12:48:32 PM PDT 24	Apr 28 12:48:55 PM PDT 24	1768328140 ps
T767	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.2459593001	Apr 28 12:49:19 PM PDT 24	Apr 28 12:49:45 PM PDT 24	1698144231 ps
T768	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1332245262	Apr 28 12:47:19 PM PDT 24	Apr 28 12:47:25 PM PDT 24	7539297 ps
T769	/workspace/coverage/xbar_build_mode/24.xbar_error_random.1515689988	Apr 28 12:48:10 PM PDT 24	Apr 28 12:48:15 PM PDT 24	150002507 ps
T770	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.3345262022	Apr 28 12:47:48 PM PDT 24	Apr 28 12:48:56 PM PDT 24	680323206 ps
T63	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.467811078	Apr 28 12:47:29 PM PDT 24	Apr 28 12:47:54 PM PDT 24	3394656849 ps
T771	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.658677782	Apr 28 12:48:32 PM PDT 24	Apr 28 12:49:08 PM PDT 24	76763758 ps
T772	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2333828819	Apr 28 12:49:31 PM PDT 24	Apr 28 12:49:33 PM PDT 24	38774574 ps
T773	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2098868647	Apr 28 12:49:27 PM PDT 24	Apr 28 12:51:47 PM PDT 24	25308193629 ps
T774	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2350377803	Apr 28 12:49:37 PM PDT 24	Apr 28 12:49:44 PM PDT 24	127226097 ps
T775	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.3237679186	Apr 28 12:48:39 PM PDT 24	Apr 28 12:48:42 PM PDT 24	70542698 ps
T776	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1345059571	Apr 28 12:47:41 PM PDT 24	Apr 28 12:50:49 PM PDT 24	571795518 ps
T777	/workspace/coverage/xbar_build_mode/17.xbar_same_source.511921478	Apr 28 12:47:39 PM PDT 24	Apr 28 12:47:46 PM PDT 24	623225710 ps
T778	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1942921842	Apr 28 12:50:04 PM PDT 24	Apr 28 12:50:29 PM PDT 24	4043347141 ps
T779	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3099333640	Apr 28 12:47:52 PM PDT 24	Apr 28 12:47:55 PM PDT 24	168360046 ps
T780	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3260654632	Apr 28 12:47:01 PM PDT 24	Apr 28 12:50:17 PM PDT 24	67239464844 ps
T781	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.629055546	Apr 28 12:47:02 PM PDT 24	Apr 28 12:47:29 PM PDT 24	640044713 ps
T782	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3424646938	Apr 28 12:46:42 PM PDT 24	Apr 28 12:47:06 PM PDT 24	274309225 ps
T783	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1307290887	Apr 28 12:49:32 PM PDT 24	Apr 28 12:51:24 PM PDT 24	540441284 ps
T784	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.260698687	Apr 28 12:47:20 PM PDT 24	Apr 28 12:56:10 PM PDT 24	97213362886 ps
T785	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.486286191	Apr 28 12:47:02 PM PDT 24	Apr 28 12:47:08 PM PDT 24	44462249 ps
T786	/workspace/coverage/xbar_build_mode/24.xbar_same_source.3160005008	Apr 28 12:48:09 PM PDT 24	Apr 28 12:48:29 PM PDT 24	340023625 ps
T787	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3412863587	Apr 28 12:47:34 PM PDT 24	Apr 28 12:47:54 PM PDT 24	952956724 ps
T788	/workspace/coverage/xbar_build_mode/8.xbar_smoke.3849909199	Apr 28 12:47:20 PM PDT 24	Apr 28 12:47:24 PM PDT 24	285952484 ps
T789	/workspace/coverage/xbar_build_mode/20.xbar_same_source.154185532	Apr 28 12:47:52 PM PDT 24	Apr 28 12:48:09 PM PDT 24	238771946 ps
T790	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.230468466	Apr 28 12:49:41 PM PDT 24	Apr 28 12:50:17 PM PDT 24	8482987238 ps
T791	/workspace/coverage/xbar_build_mode/12.xbar_random.2904820828	Apr 28 12:47:13 PM PDT 24	Apr 28 12:47:23 PM PDT 24	797753150 ps
T792	/workspace/coverage/xbar_build_mode/21.xbar_error_random.2622459826	Apr 28 12:47:54 PM PDT 24	Apr 28 12:48:10 PM PDT 24	204397815 ps
T793	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.247596642	Apr 28 12:49:15 PM PDT 24	Apr 28 12:49:48 PM PDT 24	374933591 ps
T794	/workspace/coverage/xbar_build_mode/37.xbar_random.537916399	Apr 28 12:49:12 PM PDT 24	Apr 28 12:49:15 PM PDT 24	43172413 ps
T795	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2567136396	Apr 28 12:47:50 PM PDT 24	Apr 28 12:48:17 PM PDT 24	918935112 ps
T194	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3871154171	Apr 28 12:47:36 PM PDT 24	Apr 28 12:51:05 PM PDT 24	1266886401 ps
T796	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1659509863	Apr 28 12:47:37 PM PDT 24	Apr 28 12:48:07 PM PDT 24	4563849119 ps
T797	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1049848242	Apr 28 12:47:02 PM PDT 24	Apr 28 12:47:18 PM PDT 24	510212883 ps
T798	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3758805502	Apr 28 12:48:47 PM PDT 24	Apr 28 12:51:40 PM PDT 24	28161585903 ps
T799	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1493194653	Apr 28 12:48:09 PM PDT 24	Apr 28 12:48:43 PM PDT 24	4062602763 ps
T800	/workspace/coverage/xbar_build_mode/48.xbar_smoke.219488388	Apr 28 12:50:18 PM PDT 24	Apr 28 12:50:22 PM PDT 24	1003543054 ps
T801	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.138076158	Apr 28 12:47:48 PM PDT 24	Apr 28 12:48:06 PM PDT 24	156887054 ps
T802	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.4081267447	Apr 28 12:46:51 PM PDT 24	Apr 28 12:46:55 PM PDT 24	175405477 ps
T803	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1902501643	Apr 28 12:49:49 PM PDT 24	Apr 28 12:50:12 PM PDT 24	7232104065 ps
T804	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.346101785	Apr 28 12:50:17 PM PDT 24	Apr 28 12:52:17 PM PDT 24	4364063921 ps
T805	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1069502274	Apr 28 12:48:11 PM PDT 24	Apr 28 12:49:30 PM PDT 24	259907234 ps
T806	/workspace/coverage/xbar_build_mode/49.xbar_random.877732971	Apr 28 12:50:23 PM PDT 24	Apr 28 12:50:45 PM PDT 24	518468792 ps
T807	/workspace/coverage/xbar_build_mode/9.xbar_smoke.1479474917	Apr 28 12:47:07 PM PDT 24	Apr 28 12:47:11 PM PDT 24	171077992 ps
T808	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1865021843	Apr 28 12:47:17 PM PDT 24	Apr 28 12:47:21 PM PDT 24	49381034 ps
T809	/workspace/coverage/xbar_build_mode/45.xbar_same_source.138809485	Apr 28 12:50:02 PM PDT 24	Apr 28 12:50:38 PM PDT 24	6225170465 ps
T810	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2666934883	Apr 28 12:48:41 PM PDT 24	Apr 28 12:53:17 PM PDT 24	153604890065 ps
T811	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2143989212	Apr 28 12:47:02 PM PDT 24	Apr 28 12:47:47 PM PDT 24	16562754800 ps
T812	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1899172655	Apr 28 12:47:58 PM PDT 24	Apr 28 12:48:48 PM PDT 24	7513323197 ps
T813	/workspace/coverage/xbar_build_mode/22.xbar_random.3780338366	Apr 28 12:48:00 PM PDT 24	Apr 28 12:48:34 PM PDT 24	668266543 ps
T814	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3741357758	Apr 28 12:49:28 PM PDT 24	Apr 28 12:59:47 PM PDT 24	76952106984 ps
T128	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3650020737	Apr 28 12:48:37 PM PDT 24	Apr 28 12:50:57 PM PDT 24	17947887865 ps
T815	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1103242823	Apr 28 12:49:14 PM PDT 24	Apr 28 12:50:08 PM PDT 24	1824886412 ps
T816	/workspace/coverage/xbar_build_mode/10.xbar_random.2662055342	Apr 28 12:47:04 PM PDT 24	Apr 28 12:47:21 PM PDT 24	568271476 ps
T817	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.793940075	Apr 28 12:46:51 PM PDT 24	Apr 28 12:47:22 PM PDT 24	11950997096 ps
T818	/workspace/coverage/xbar_build_mode/40.xbar_same_source.3302854349	Apr 28 12:49:35 PM PDT 24	Apr 28 12:49:51 PM PDT 24	2818703932 ps
T819	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3542221122	Apr 28 12:48:57 PM PDT 24	Apr 28 12:49:09 PM PDT 24	682505215 ps
T820	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1208421341	Apr 28 12:46:52 PM PDT 24	Apr 28 12:46:55 PM PDT 24	31794047 ps
T821	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3793289008	Apr 28 12:46:59 PM PDT 24	Apr 28 12:47:23 PM PDT 24	5097609537 ps
T822	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1199736568	Apr 28 12:49:04 PM PDT 24	Apr 28 12:51:29 PM PDT 24	539825986 ps
T823	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3560606837	Apr 28 12:47:35 PM PDT 24	Apr 28 12:53:21 PM PDT 24	37394215147 ps
T824	/workspace/coverage/xbar_build_mode/2.xbar_error_random.2302007794	Apr 28 12:46:48 PM PDT 24	Apr 28 12:47:05 PM PDT 24	283123696 ps
T825	/workspace/coverage/xbar_build_mode/2.xbar_same_source.2956415016	Apr 28 12:46:49 PM PDT 24	Apr 28 12:47:00 PM PDT 24	143150763 ps
T826	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3975071257	Apr 28 12:50:02 PM PDT 24	Apr 28 12:53:45 PM PDT 24	59894371613 ps
T827	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2083789846	Apr 28 12:47:13 PM PDT 24	Apr 28 12:47:16 PM PDT 24	44359865 ps
T828	/workspace/coverage/xbar_build_mode/16.xbar_smoke.524205972	Apr 28 12:47:33 PM PDT 24	Apr 28 12:47:37 PM PDT 24	408064535 ps
T829	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1132147713	Apr 28 12:46:48 PM PDT 24	Apr 28 12:47:25 PM PDT 24	7481215309 ps
T830	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3737278824	Apr 28 12:48:31 PM PDT 24	Apr 28 12:49:28 PM PDT 24	9288196663 ps
T831	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1651774473	Apr 28 12:49:02 PM PDT 24	Apr 28 12:49:06 PM PDT 24	70530745 ps
T832	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.652004288	Apr 28 12:47:55 PM PDT 24	Apr 28 12:48:19 PM PDT 24	665115294 ps
T833	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1547013344	Apr 28 12:48:59 PM PDT 24	Apr 28 12:49:13 PM PDT 24	625668358 ps
T834	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2492264258	Apr 28 12:48:17 PM PDT 24	Apr 28 12:48:20 PM PDT 24	27422638 ps
T835	/workspace/coverage/xbar_build_mode/46.xbar_same_source.2352987276	Apr 28 12:50:08 PM PDT 24	Apr 28 12:50:34 PM PDT 24	3873159636 ps
T836	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3720667321	Apr 28 12:49:47 PM PDT 24	Apr 28 12:49:51 PM PDT 24	41220848 ps
T837	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.630167891	Apr 28 12:49:11 PM PDT 24	Apr 28 12:50:54 PM PDT 24	19893994554 ps
T838	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1966049628	Apr 28 12:48:17 PM PDT 24	Apr 28 12:48:35 PM PDT 24	524663334 ps
T839	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3888801295	Apr 28 12:50:18 PM PDT 24	Apr 28 12:53:16 PM PDT 24	29174444202 ps
T840	/workspace/coverage/xbar_build_mode/20.xbar_smoke.3757705236	Apr 28 12:47:50 PM PDT 24	Apr 28 12:47:54 PM PDT 24	191956160 ps
T841	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3705730488	Apr 28 12:47:54 PM PDT 24	Apr 28 12:49:05 PM PDT 24	984425399 ps
T842	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1867151114	Apr 28 12:47:30 PM PDT 24	Apr 28 12:48:03 PM PDT 24	8095261078 ps
T843	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1848242016	Apr 28 12:47:03 PM PDT 24	Apr 28 12:50:44 PM PDT 24	4409929505 ps
T844	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.2301225708	Apr 28 12:47:38 PM PDT 24	Apr 28 12:48:03 PM PDT 24	526858624 ps
T845	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.504167792	Apr 28 12:49:58 PM PDT 24	Apr 28 12:50:56 PM PDT 24	2274845351 ps
T846	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.367499545	Apr 28 12:49:38 PM PDT 24	Apr 28 12:50:03 PM PDT 24	1305013486 ps
T847	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3619792051	Apr 28 12:50:24 PM PDT 24	Apr 28 12:50:27 PM PDT 24	47491926 ps
T848	/workspace/coverage/xbar_build_mode/47.xbar_smoke.2254339676	Apr 28 12:50:17 PM PDT 24	Apr 28 12:50:21 PM PDT 24	258106285 ps
T126	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3530782282	Apr 28 12:50:26 PM PDT 24	Apr 28 01:02:29 PM PDT 24	176206549219 ps
T849	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3823354972	Apr 28 12:49:22 PM PDT 24	Apr 28 12:49:37 PM PDT 24	512985197 ps
T850	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.628516018	Apr 28 12:47:38 PM PDT 24	Apr 28 12:47:43 PM PDT 24	33464019 ps
T851	/workspace/coverage/xbar_build_mode/18.xbar_same_source.1562751960	Apr 28 12:47:48 PM PDT 24	Apr 28 12:48:15 PM PDT 24	1333092794 ps
T852	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1643696849	Apr 28 12:47:14 PM PDT 24	Apr 28 12:52:49 PM PDT 24	6478557152 ps
T853	/workspace/coverage/xbar_build_mode/31.xbar_error_random.762873014	Apr 28 12:48:40 PM PDT 24	Apr 28 12:48:55 PM PDT 24	151867071 ps
T854	/workspace/coverage/xbar_build_mode/21.xbar_same_source.2187126987	Apr 28 12:47:55 PM PDT 24	Apr 28 12:48:10 PM PDT 24	1204291357 ps
T855	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.4168086704	Apr 28 12:47:03 PM PDT 24	Apr 28 12:47:10 PM PDT 24	32992838 ps
T856	/workspace/coverage/xbar_build_mode/45.xbar_smoke.2126457458	Apr 28 12:49:58 PM PDT 24	Apr 28 12:50:01 PM PDT 24	156933552 ps
T857	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.848858773	Apr 28 12:50:14 PM PDT 24	Apr 28 12:50:43 PM PDT 24	4724157678 ps
T858	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1291032587	Apr 28 12:48:13 PM PDT 24	Apr 28 12:48:34 PM PDT 24	875396251 ps
T859	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4017312470	Apr 28 12:50:09 PM PDT 24	Apr 28 12:58:01 PM PDT 24	47858059552 ps
T860	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.290735603	Apr 28 12:50:25 PM PDT 24	Apr 28 12:54:26 PM PDT 24	36154751951 ps
T861	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1062699464	Apr 28 12:48:21 PM PDT 24	Apr 28 12:51:54 PM PDT 24	33380647046 ps
T862	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2551602022	Apr 28 12:48:43 PM PDT 24	Apr 28 12:49:23 PM PDT 24	22017474826 ps
T863	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.4073667638	Apr 28 12:47:49 PM PDT 24	Apr 28 12:54:08 PM PDT 24	45596362579 ps
T864	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3082216700	Apr 28 12:48:26 PM PDT 24	Apr 28 12:48:37 PM PDT 24	304938323 ps
T865	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1463408686	Apr 28 12:50:27 PM PDT 24	Apr 28 12:50:56 PM PDT 24	2195858006 ps
T866	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3954633572	Apr 28 12:47:04 PM PDT 24	Apr 28 12:47:09 PM PDT 24	36724506 ps
T867	/workspace/coverage/xbar_build_mode/25.xbar_smoke.1630967210	Apr 28 12:48:07 PM PDT 24	Apr 28 12:48:11 PM PDT 24	448364765 ps
T868	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1005211611	Apr 28 12:46:49 PM PDT 24	Apr 28 12:50:35 PM PDT 24	26946092778 ps
T869	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3215053186	Apr 28 12:47:33 PM PDT 24	Apr 28 12:48:34 PM PDT 24	179442052 ps
T870	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3440638417	Apr 28 12:48:54 PM PDT 24	Apr 28 12:49:11 PM PDT 24	2328141126 ps
T871	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.220391921	Apr 28 12:49:22 PM PDT 24	Apr 28 12:52:45 PM PDT 24	1914006870 ps
T872	/workspace/coverage/xbar_build_mode/30.xbar_smoke.1215181522	Apr 28 12:48:31 PM PDT 24	Apr 28 12:48:34 PM PDT 24	67939836 ps
T873	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.321306932	Apr 28 12:48:48 PM PDT 24	Apr 28 12:50:49 PM PDT 24	879458019 ps
T874	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.4237510963	Apr 28 12:49:27 PM PDT 24	Apr 28 12:51:44 PM PDT 24	391927246 ps
T875	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2530352889	Apr 28 12:48:37 PM PDT 24	Apr 28 12:51:46 PM PDT 24	559701387 ps
T876	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2388383008	Apr 28 12:47:48 PM PDT 24	Apr 28 12:48:03 PM PDT 24	951822175 ps
T877	/workspace/coverage/xbar_build_mode/42.xbar_smoke.2896306347	Apr 28 12:49:38 PM PDT 24	Apr 28 12:49:42 PM PDT 24	296850730 ps
T878	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.414721251	Apr 28 12:49:54 PM PDT 24	Apr 28 12:50:21 PM PDT 24	8886245877 ps
T35	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3727252858	Apr 28 12:50:22 PM PDT 24	Apr 28 12:52:33 PM PDT 24	239101169 ps
T879	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.558006562	Apr 28 12:47:55 PM PDT 24	Apr 28 12:48:48 PM PDT 24	34401816634 ps
T214	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.229475385	Apr 28 12:49:57 PM PDT 24	Apr 28 12:50:26 PM PDT 24	909678857 ps
T880	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2393772054	Apr 28 12:50:28 PM PDT 24	Apr 28 12:52:08 PM PDT 24	16175847414 ps
T881	/workspace/coverage/xbar_build_mode/38.xbar_smoke.1461733629	Apr 28 12:49:19 PM PDT 24	Apr 28 12:49:23 PM PDT 24	135153573 ps
T882	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3714031768	Apr 28 12:49:03 PM PDT 24	Apr 28 12:49:06 PM PDT 24	23025001 ps
T883	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1437511744	Apr 28 12:48:17 PM PDT 24	Apr 28 12:49:55 PM PDT 24	375201516 ps
T884	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1042863355	Apr 28 12:47:15 PM PDT 24	Apr 28 12:50:07 PM PDT 24	27057894413 ps
T885	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2559246143	Apr 28 12:47:12 PM PDT 24	Apr 28 12:50:19 PM PDT 24	1369355157 ps
T886	/workspace/coverage/xbar_build_mode/5.xbar_error_random.1788504789	Apr 28 12:47:02 PM PDT 24	Apr 28 12:47:14 PM PDT 24	329801567 ps
T151	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3921579100	Apr 28 12:46:57 PM PDT 24	Apr 28 12:53:15 PM PDT 24	42286609800 ps
T887	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2511973289	Apr 28 12:49:34 PM PDT 24	Apr 28 12:49:58 PM PDT 24	4633566108 ps
T888	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.917891471	Apr 28 12:48:20 PM PDT 24	Apr 28 12:48:23 PM PDT 24	27821156 ps
T889	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3700115564	Apr 28 12:48:48 PM PDT 24	Apr 28 12:49:13 PM PDT 24	663662682 ps
T890	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1137603374	Apr 28 12:48:30 PM PDT 24	Apr 28 12:52:29 PM PDT 24	6687124378 ps
T891	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3419476853	Apr 28 12:50:18 PM PDT 24	Apr 28 12:50:47 PM PDT 24	12358746440 ps
T892	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.916291974	Apr 28 12:47:01 PM PDT 24	Apr 28 12:47:06 PM PDT 24	180583079 ps
T893	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1011811249	Apr 28 12:47:02 PM PDT 24	Apr 28 12:50:25 PM PDT 24	37284695644 ps
T894	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2804168166	Apr 28 12:49:36 PM PDT 24	Apr 28 12:55:02 PM PDT 24	8271861088 ps
T895	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3056829895	Apr 28 12:49:21 PM PDT 24	Apr 28 12:49:36 PM PDT 24	34851294 ps
T896	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2363120289	Apr 28 12:48:52 PM PDT 24	Apr 28 12:50:55 PM PDT 24	23850486889 ps
T897	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1792450770	Apr 28 12:50:03 PM PDT 24	Apr 28 12:50:06 PM PDT 24	38421997 ps
T898	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3941989800	Apr 28 12:47:38 PM PDT 24	Apr 28 12:48:03 PM PDT 24	5898910837 ps
T899	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.658502047	Apr 28 12:48:26 PM PDT 24	Apr 28 12:48:28 PM PDT 24	41233663 ps
T900	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.594284464	Apr 28 12:46:57 PM PDT 24	Apr 28 12:47:11 PM PDT 24	117887841 ps

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.378344394
Short name	T1
Test name
Test status
Simulation time	281176519 ps
CPU time	72.18 seconds
Started	Apr 28 12:49:46 PM PDT 24
Finished	Apr 28 12:50:59 PM PDT 24
Peak memory	207444 kb
Host	smart-9fb5f3a5-9cf0-4842-a21d-eebdf2953f9f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=378344394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res et_error.378344394
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.575897936
Short name	T74
Test name
Test status
Simulation time	191187051545 ps
CPU time	682.24 seconds
Started	Apr 28 12:49:31 PM PDT 24
Finished	Apr 28 01:00:54 PM PDT 24
Peak memory	211600 kb
Host	smart-b65994aa-df40-4510-b2c6-c07d1deb3968
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=575897936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo w_rsp.575897936
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1516511487
Short name	T2
Test name
Test status
Simulation time	87162983302 ps
CPU time	523.93 seconds
Started	Apr 28 12:48:02 PM PDT 24
Finished	Apr 28 12:56:47 PM PDT 24
Peak memory	211652 kb
Host	smart-b2e9d2e2-72d0-4108-8e9d-ceac0a750b66
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1516511487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.1516511487
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1468961349
Short name	T73
Test name
Test status
Simulation time	70202030214 ps
CPU time	602.67 seconds
Started	Apr 28 12:49:03 PM PDT 24
Finished	Apr 28 12:59:06 PM PDT 24
Peak memory	207092 kb
Host	smart-e66febd5-c6e3-43e6-9e29-6318513c7a9e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1468961349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.1468961349
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1000694346
Short name	T10
Test name
Test status
Simulation time	3942741199 ps
CPU time	41.68 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:47 PM PDT 24
Peak memory	205784 kb
Host	smart-131d1a7f-2300-4c13-8cbc-d0508050f65d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1000694346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1000694346
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.2614638107
Short name	T4
Test name
Test status
Simulation time	607196255 ps
CPU time	11.36 seconds
Started	Apr 28 12:49:29 PM PDT 24
Finished	Apr 28 12:49:41 PM PDT 24
Peak memory	204004 kb
Host	smart-ffcea40f-1ed4-4f2e-a1d5-3f11af9d61e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2614638107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2614638107
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3442791963
Short name	T31
Test name
Test status
Simulation time	19921612858 ps
CPU time	575.31 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:57:36 PM PDT 24
Peak memory	210076 kb
Host	smart-4d7f752c-ed2e-4de5-b00c-25b2245ac23d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3442791963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3442791963
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3878357986
Short name	T69
Test name
Test status
Simulation time	54968746467 ps
CPU time	254.85 seconds
Started	Apr 28 12:49:50 PM PDT 24
Finished	Apr 28 12:54:06 PM PDT 24
Peak memory	205256 kb
Host	smart-0181f54b-a9e4-4e48-843c-d383ab2ffd62
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878357986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3878357986
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.1899609545
Short name	T125
Test name
Test status
Simulation time	28302383393 ps
CPU time	322.4 seconds
Started	Apr 28 12:46:45 PM PDT 24
Finished	Apr 28 12:52:08 PM PDT 24
Peak memory	207404 kb
Host	smart-939fe597-a8ba-466d-a41a-46219e3e6c48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1899609545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1899609545
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3354634463
Short name	T111
Test name
Test status
Simulation time	2178080555 ps
CPU time	68.56 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:50:21 PM PDT 24
Peak memory	206460 kb
Host	smart-a146332c-31db-4f87-828a-0ebc46608bca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3354634463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3354634463
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1077324984
Short name	T169
Test name
Test status
Simulation time	982865389 ps
CPU time	191.32 seconds
Started	Apr 28 12:49:20 PM PDT 24
Finished	Apr 28 12:52:32 PM PDT 24
Peak memory	208704 kb
Host	smart-e2dc2618-b2b4-42f7-aa1f-2caa016906db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077324984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.1077324984
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.382967768
Short name	T78
Test name
Test status
Simulation time	222741520006 ps
CPU time	766.97 seconds
Started	Apr 28 12:50:17 PM PDT 24
Finished	Apr 28 01:03:05 PM PDT 24
Peak memory	207680 kb
Host	smart-6c084254-67de-4097-928c-c3dd60bd32e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=382967768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo w_rsp.382967768
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1467386325
Short name	T33
Test name
Test status
Simulation time	302279487 ps
CPU time	89.01 seconds
Started	Apr 28 12:46:55 PM PDT 24
Finished	Apr 28 12:48:24 PM PDT 24
Peak memory	208776 kb
Host	smart-47a8a742-3c68-4d00-a1d7-f1971872d904
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1467386325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1467386325
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.769965150
Short name	T543
Test name
Test status
Simulation time	901372622 ps
CPU time	179.1 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:50:54 PM PDT 24
Peak memory	211560 kb
Host	smart-1d3ce735-05b0-4c33-a1d5-00a3356f1954
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=769965150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res et_error.769965150
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.506406240
Short name	T21
Test name
Test status
Simulation time	10889731871 ps
CPU time	433.12 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	211068 kb
Host	smart-ebfa63bf-aa39-4b71-8eea-780fa5176066
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=506406240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand _reset.506406240
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4000459184
Short name	T32
Test name
Test status
Simulation time	5272118630 ps
CPU time	233.49 seconds
Started	Apr 28 12:48:38 PM PDT 24
Finished	Apr 28 12:52:32 PM PDT 24
Peak memory	210176 kb
Host	smart-b07103ad-ae82-4f5a-a73b-fb7e6a299669
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000459184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.4000459184
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.1528382451
Short name	T24
Test name
Test status
Simulation time	15867167418 ps
CPU time	170.56 seconds
Started	Apr 28 12:47:36 PM PDT 24
Finished	Apr 28 12:50:27 PM PDT 24
Peak memory	207692 kb
Host	smart-5801ed49-4131-4b4b-a25e-ffc9aa93cd98
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1528382451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1528382451
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3295822735
Short name	T34
Test name
Test status
Simulation time	13941897281 ps
CPU time	699.24 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:59:47 PM PDT 24
Peak memory	221088 kb
Host	smart-719316d9-2071-4e76-80ad-1af74ead6426
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3295822735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3295822735
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2458980405
Short name	T402
Test name
Test status
Simulation time	580626616 ps
CPU time	331.78 seconds
Started	Apr 28 12:47:14 PM PDT 24
Finished	Apr 28 12:52:48 PM PDT 24
Peak memory	208356 kb
Host	smart-12260c60-a5a1-4ed2-82ef-45359db0fce2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2458980405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2458980405
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1239446959
Short name	T137
Test name
Test status
Simulation time	80174258947 ps
CPU time	341.59 seconds
Started	Apr 28 12:47:31 PM PDT 24
Finished	Apr 28 12:53:13 PM PDT 24
Peak memory	206736 kb
Host	smart-b1b2d7ed-56e5-44b8-ba26-d0ea57a5f3e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1239446959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1239446959
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.4040430732
Short name	T337
Test name
Test status
Simulation time	36840854 ps
CPU time	7.17 seconds
Started	Apr 28 12:46:59 PM PDT 24
Finished	Apr 28 12:47:07 PM PDT 24
Peak memory	203528 kb
Host	smart-ed1e69c4-061f-460c-bdd7-242703e024fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040430732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.4040430732
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3921579100
Short name	T151
Test name
Test status
Simulation time	42286609800 ps
CPU time	377.5 seconds
Started	Apr 28 12:46:57 PM PDT 24
Finished	Apr 28 12:53:15 PM PDT 24
Peak memory	207108 kb
Host	smart-28407101-630e-447a-a243-28055ce85f2d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3921579100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.3921579100
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1396792798
Short name	T552
Test name
Test status
Simulation time	550397761 ps
CPU time	12.46 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:47:15 PM PDT 24
Peak memory	203620 kb
Host	smart-559bac8a-ad43-4a47-81e7-2d91db20aa28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1396792798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1396792798
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.1460765943
Short name	T437
Test name
Test status
Simulation time	936115617 ps
CPU time	29.14 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:47:11 PM PDT 24
Peak memory	203564 kb
Host	smart-67f13a32-db0e-4839-817a-61a721799c67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460765943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1460765943
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.3559620465
Short name	T763
Test name
Test status
Simulation time	322951089 ps
CPU time	6.81 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:47:08 PM PDT 24
Peak memory	211548 kb
Host	smart-7a1cda7c-3e36-45c8-ada6-9ef8a20966fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3559620465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3559620465
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.4216808404
Short name	T182
Test name
Test status
Simulation time	209502250958 ps
CPU time	248.46 seconds
Started	Apr 28 12:46:40 PM PDT 24
Finished	Apr 28 12:50:49 PM PDT 24
Peak memory	205084 kb
Host	smart-5b40352a-037a-440f-88e2-809ef62976bf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216808404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.4216808404
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1173941594
Short name	T190
Test name
Test status
Simulation time	44179590573 ps
CPU time	104.38 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:48:26 PM PDT 24
Peak memory	204908 kb
Host	smart-a10c53b9-666c-44d8-af05-80951af88e9e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1173941594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1173941594
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3424646938
Short name	T782
Test name
Test status
Simulation time	274309225 ps
CPU time	22.94 seconds
Started	Apr 28 12:46:42 PM PDT 24
Finished	Apr 28 12:47:06 PM PDT 24
Peak memory	204488 kb
Host	smart-f7a06055-8c57-4fee-8a15-98a376b6a91c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424646938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3424646938
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.2573553530
Short name	T121
Test name
Test status
Simulation time	344479208 ps
CPU time	19.07 seconds
Started	Apr 28 12:46:42 PM PDT 24
Finished	Apr 28 12:47:02 PM PDT 24
Peak memory	204204 kb
Host	smart-20314cd0-c583-4d2a-9a7f-801c9f27d915
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573553530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2573553530
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.2674073935
Short name	T342
Test name
Test status
Simulation time	182156069 ps
CPU time	3.78 seconds
Started	Apr 28 12:46:37 PM PDT 24
Finished	Apr 28 12:46:41 PM PDT 24
Peak memory	203464 kb
Host	smart-3a4d8e85-94b3-4b16-8f43-3eaebb4dea23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2674073935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2674073935
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3042688559
Short name	T380
Test name
Test status
Simulation time	8313331801 ps
CPU time	30.8 seconds
Started	Apr 28 12:46:59 PM PDT 24
Finished	Apr 28 12:47:30 PM PDT 24
Peak memory	203408 kb
Host	smart-8a1f5f83-6353-41e9-81b0-fe62f859c6df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042688559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3042688559
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3597354252
Short name	T447
Test name
Test status
Simulation time	13164653609 ps
CPU time	39.73 seconds
Started	Apr 28 12:46:55 PM PDT 24
Finished	Apr 28 12:47:35 PM PDT 24
Peak memory	203520 kb
Host	smart-4ca0523d-5d59-421e-b3d6-2119db9c7b64
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3597354252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3597354252
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3389778670
Short name	T324
Test name
Test status
Simulation time	39986723 ps
CPU time	2.24 seconds
Started	Apr 28 12:47:00 PM PDT 24
Finished	Apr 28 12:47:03 PM PDT 24
Peak memory	203376 kb
Host	smart-3e8144fe-2285-409a-82df-42f86f5b4303
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389778670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3389778670
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.2783826504
Short name	T81
Test name
Test status
Simulation time	4299574284 ps
CPU time	82.19 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:48:04 PM PDT 24
Peak memory	211632 kb
Host	smart-fe9b9e70-f128-48ac-b3fd-256ce1a0e106
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2783826504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2783826504
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1636268432
Short name	T273
Test name
Test status
Simulation time	2076935845 ps
CPU time	68.25 seconds
Started	Apr 28 12:46:42 PM PDT 24
Finished	Apr 28 12:47:51 PM PDT 24
Peak memory	205484 kb
Host	smart-8e0423fb-733f-42c9-b6b9-49e27793d5c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636268432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1636268432
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1457266260
Short name	T605
Test name
Test status
Simulation time	385557294 ps
CPU time	122.94 seconds
Started	Apr 28 12:46:59 PM PDT 24
Finished	Apr 28 12:49:03 PM PDT 24
Peak memory	208220 kb
Host	smart-f2a2b460-5caf-499c-91cb-f4a8785622bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1457266260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1457266260
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.326601340
Short name	T742
Test name
Test status
Simulation time	2586312749 ps
CPU time	327.08 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:52:28 PM PDT 24
Peak memory	219904 kb
Host	smart-5eaefa9c-d30e-4a8e-8d4a-2611fb5530c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=326601340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese t_error.326601340
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2531336117
Short name	T761
Test name
Test status
Simulation time	763292831 ps
CPU time	9.47 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:46:58 PM PDT 24
Peak memory	204784 kb
Host	smart-b14d842f-3f7c-40ce-938e-a65355435bd9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2531336117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2531336117
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.662707166
Short name	T740
Test name
Test status
Simulation time	175337197 ps
CPU time	25.51 seconds
Started	Apr 28 12:46:58 PM PDT 24
Finished	Apr 28 12:47:24 PM PDT 24
Peak memory	211596 kb
Host	smart-9aacd63c-9ac7-41c8-b10b-b6347ba57ac6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=662707166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.662707166
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.85311739
Short name	T596
Test name
Test status
Simulation time	88158410489 ps
CPU time	184.03 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:49:46 PM PDT 24
Peak memory	206176 kb
Host	smart-07b58a96-7345-442f-9111-faa342679422
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=85311739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.85311739
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1497882609
Short name	T265
Test name
Test status
Simulation time	1828255732 ps
CPU time	13.67 seconds
Started	Apr 28 12:46:54 PM PDT 24
Finished	Apr 28 12:47:08 PM PDT 24
Peak memory	203712 kb
Host	smart-5e897df0-d3cb-4f7e-adbe-29eaaac4ef04
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1497882609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1497882609
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.2279016426
Short name	T647
Test name
Test status
Simulation time	965380579 ps
CPU time	20.93 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:47:03 PM PDT 24
Peak memory	203360 kb
Host	smart-9ae4e46a-0b16-444d-b43e-48447bf43535
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2279016426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2279016426
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.3172109912
Short name	T94
Test name
Test status
Simulation time	143443009 ps
CPU time	14 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:47:04 PM PDT 24
Peak memory	211680 kb
Host	smart-bcfd260b-bf9c-45cc-888c-fc8999128cdf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3172109912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3172109912
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3260654632
Short name	T780
Test name
Test status
Simulation time	67239464844 ps
CPU time	194.73 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:50:17 PM PDT 24
Peak memory	211552 kb
Host	smart-a65975f9-d0ff-4d04-8eff-c9fcc7798aa9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260654632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3260654632
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.898660397
Short name	T106
Test name
Test status
Simulation time	15323656760 ps
CPU time	130.22 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:49:14 PM PDT 24
Peak memory	204676 kb
Host	smart-407cebd1-2fdf-4871-8441-5661e6d89d6d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=898660397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.898660397
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.594284464
Short name	T900
Test name
Test status
Simulation time	117887841 ps
CPU time	13.68 seconds
Started	Apr 28 12:46:57 PM PDT 24
Finished	Apr 28 12:47:11 PM PDT 24
Peak memory	204456 kb
Host	smart-637b4b9c-1bee-4c5c-9f90-30ffd57326e9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594284464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.594284464
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.1497991247
Short name	T731
Test name
Test status
Simulation time	147875038 ps
CPU time	10.9 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:15 PM PDT 24
Peak memory	203356 kb
Host	smart-b34e4c1f-28a1-4d01-985a-00dc9c8f45b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1497991247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1497991247
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.647607242
Short name	T620
Test name
Test status
Simulation time	72772916 ps
CPU time	2.1 seconds
Started	Apr 28 12:46:58 PM PDT 24
Finished	Apr 28 12:47:00 PM PDT 24
Peak memory	203496 kb
Host	smart-56eb1159-6f4d-477d-a7f9-d43011ab6bef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647607242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.647607242
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1336490534
Short name	T216
Test name
Test status
Simulation time	5489519729 ps
CPU time	31.25 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:47:13 PM PDT 24
Peak memory	203556 kb
Host	smart-f61be005-416c-45ab-abd5-b37e4a482074
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336490534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1336490534
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2937245771
Short name	T476
Test name
Test status
Simulation time	3502867097 ps
CPU time	32.16 seconds
Started	Apr 28 12:46:42 PM PDT 24
Finished	Apr 28 12:47:15 PM PDT 24
Peak memory	203568 kb
Host	smart-d600a8c9-695e-49b4-91cc-27748d4c518e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2937245771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2937245771
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1208421341
Short name	T820
Test name
Test status
Simulation time	31794047 ps
CPU time	2.63 seconds
Started	Apr 28 12:46:52 PM PDT 24
Finished	Apr 28 12:46:55 PM PDT 24
Peak memory	203380 kb
Host	smart-b29bbbfa-182c-4e5b-9875-ceb88af31c8a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208421341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1208421341
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.1908916472
Short name	T149
Test name
Test status
Simulation time	3230266672 ps
CPU time	66.25 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:47:49 PM PDT 24
Peak memory	205324 kb
Host	smart-5d17c3c2-d505-443d-809c-ab93d2dc0ba8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1908916472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1908916472
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2719410719
Short name	T690
Test name
Test status
Simulation time	226528148 ps
CPU time	14.01 seconds
Started	Apr 28 12:46:52 PM PDT 24
Finished	Apr 28 12:47:07 PM PDT 24
Peak memory	203544 kb
Host	smart-a255e836-31a9-449c-8588-d12d956a4933
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2719410719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2719410719
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2286668502
Short name	T759
Test name
Test status
Simulation time	135986037 ps
CPU time	50.03 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:43 PM PDT 24
Peak memory	206660 kb
Host	smart-448869c9-aeb4-4aed-b5e6-56ca15b0b56a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2286668502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.2286668502
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.811096066
Short name	T230
Test name
Test status
Simulation time	130210813 ps
CPU time	48.06 seconds
Started	Apr 28 12:46:42 PM PDT 24
Finished	Apr 28 12:47:31 PM PDT 24
Peak memory	208036 kb
Host	smart-50a89165-9923-450f-ba58-98e08c820c1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=811096066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.811096066
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2757773869
Short name	T279
Test name
Test status
Simulation time	1010226911 ps
CPU time	18.56 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:47:00 PM PDT 24
Peak memory	204748 kb
Host	smart-7dc40d50-a393-4af1-8159-09d4ebe8939d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2757773869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2757773869
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1931471582
Short name	T368
Test name
Test status
Simulation time	293168458 ps
CPU time	12.36 seconds
Started	Apr 28 12:47:08 PM PDT 24
Finished	Apr 28 12:47:22 PM PDT 24
Peak memory	211648 kb
Host	smart-9e1f4a8c-7648-4da9-8b6d-0953a6f06a04
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1931471582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1931471582
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2921803126
Short name	T646
Test name
Test status
Simulation time	73519042691 ps
CPU time	485.19 seconds
Started	Apr 28 12:47:08 PM PDT 24
Finished	Apr 28 12:55:14 PM PDT 24
Peak memory	206028 kb
Host	smart-62267e9c-d04d-4045-88ff-f1bba4f04942
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2921803126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2921803126
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1763498093
Short name	T736
Test name
Test status
Simulation time	1082544613 ps
CPU time	19.55 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:47:27 PM PDT 24
Peak memory	203828 kb
Host	smart-c0ec2241-6ca7-4be1-a1a9-d59df93e436f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1763498093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1763498093
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.3451974433
Short name	T711
Test name
Test status
Simulation time	483698498 ps
CPU time	23.44 seconds
Started	Apr 28 12:47:10 PM PDT 24
Finished	Apr 28 12:47:34 PM PDT 24
Peak memory	203588 kb
Host	smart-7a08f7c2-28fe-484d-98a2-c839cd656b5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3451974433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3451974433
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.2662055342
Short name	T816
Test name
Test status
Simulation time	568271476 ps
CPU time	14.38 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:21 PM PDT 24
Peak memory	204648 kb
Host	smart-12880b22-7826-4c60-974b-e9ecb2aedd11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662055342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2662055342
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1918964211
Short name	T138
Test name
Test status
Simulation time	4845484422 ps
CPU time	23.52 seconds
Started	Apr 28 12:47:16 PM PDT 24
Finished	Apr 28 12:47:41 PM PDT 24
Peak memory	204360 kb
Host	smart-0e2623c8-abfc-4cf2-90d3-6539cd27f996
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918964211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1918964211
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3486014460
Short name	T347
Test name
Test status
Simulation time	20360461180 ps
CPU time	147.45 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:49:45 PM PDT 24
Peak memory	205168 kb
Host	smart-b0a9328d-b2e4-4e15-bb68-9adfe10763cc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3486014460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3486014460
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2239775819
Short name	T281
Test name
Test status
Simulation time	26944843 ps
CPU time	2.25 seconds
Started	Apr 28 12:47:09 PM PDT 24
Finished	Apr 28 12:47:12 PM PDT 24
Peak memory	203724 kb
Host	smart-e64b4229-959d-4851-bc81-7544c8d97563
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239775819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2239775819
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.3786567075
Short name	T585
Test name
Test status
Simulation time	2478093476 ps
CPU time	22.06 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	204084 kb
Host	smart-2350d96c-98b4-45f2-9d8c-8cc169ee7167
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3786567075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3786567075
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.3030955227
Short name	T495
Test name
Test status
Simulation time	96854890 ps
CPU time	2.47 seconds
Started	Apr 28 12:47:09 PM PDT 24
Finished	Apr 28 12:47:12 PM PDT 24
Peak memory	203448 kb
Host	smart-f0af152e-3124-4fed-b7db-d0edc3cecf82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3030955227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3030955227
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1964920516
Short name	T468
Test name
Test status
Simulation time	5850417346 ps
CPU time	33.39 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:40 PM PDT 24
Peak memory	203484 kb
Host	smart-081bd076-a5ca-4614-b6c8-c1bd08892fec
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964920516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1964920516
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3555683066
Short name	T220
Test name
Test status
Simulation time	9326568802 ps
CPU time	34.06 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:40 PM PDT 24
Peak memory	203556 kb
Host	smart-859884fa-9b43-4be2-8a8e-df571c17d036
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3555683066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3555683066
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1865021843
Short name	T808
Test name
Test status
Simulation time	49381034 ps
CPU time	2.16 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:21 PM PDT 24
Peak memory	203456 kb
Host	smart-7e12f211-5d3c-42b8-aca4-e48e6e65a266
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865021843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1865021843
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.1152284539
Short name	T663
Test name
Test status
Simulation time	593729443 ps
CPU time	64.12 seconds
Started	Apr 28 12:47:07 PM PDT 24
Finished	Apr 28 12:48:12 PM PDT 24
Peak memory	206480 kb
Host	smart-d5b1c92b-8241-4f14-b09d-181d4b9bdc86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1152284539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1152284539
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4034620639
Short name	T459
Test name
Test status
Simulation time	6196045318 ps
CPU time	188.55 seconds
Started	Apr 28 12:47:06 PM PDT 24
Finished	Apr 28 12:50:16 PM PDT 24
Peak memory	210244 kb
Host	smart-e8ae58a9-183d-4195-8be1-074b5ed7ffa8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4034620639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4034620639
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1436380701
Short name	T231
Test name
Test status
Simulation time	1180841430 ps
CPU time	265.9 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:51:43 PM PDT 24
Peak memory	219972 kb
Host	smart-8aae5118-fe65-4dc2-ad1d-6a477e28c186
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1436380701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1436380701
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.4116688014
Short name	T305
Test name
Test status
Simulation time	1944188376 ps
CPU time	22.47 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	205180 kb
Host	smart-faae2717-86c4-45c2-b60e-b4cd2ae00654
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4116688014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4116688014
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3397173868
Short name	T170
Test name
Test status
Simulation time	93204838 ps
CPU time	15.4 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:33 PM PDT 24
Peak memory	205552 kb
Host	smart-e69072ef-5cd3-484b-b1b0-cab4250125dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3397173868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3397173868
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.153080694
Short name	T442
Test name
Test status
Simulation time	119158988287 ps
CPU time	621.92 seconds
Started	Apr 28 12:47:08 PM PDT 24
Finished	Apr 28 12:57:31 PM PDT 24
Peak memory	207668 kb
Host	smart-85fc15ed-0037-4b74-b516-137b3dd8eb9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=153080694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo w_rsp.153080694
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.41703452
Short name	T433
Test name
Test status
Simulation time	546442214 ps
CPU time	15.81 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:47:33 PM PDT 24
Peak memory	203548 kb
Host	smart-024a4dd3-bfde-43c1-a296-c3be6d4cde53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41703452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.41703452
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.1111752956
Short name	T472
Test name
Test status
Simulation time	188776469 ps
CPU time	19.81 seconds
Started	Apr 28 12:47:10 PM PDT 24
Finished	Apr 28 12:47:30 PM PDT 24
Peak memory	203436 kb
Host	smart-cf5daa33-63c0-4464-9f7c-1deb41fb649b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1111752956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1111752956
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.2846616240
Short name	T550
Test name
Test status
Simulation time	226876031 ps
CPU time	24.81 seconds
Started	Apr 28 12:47:13 PM PDT 24
Finished	Apr 28 12:47:39 PM PDT 24
Peak memory	211560 kb
Host	smart-597d8212-17b5-4a64-a381-d31d424e668d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2846616240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2846616240
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.262150571
Short name	T325
Test name
Test status
Simulation time	229184304981 ps
CPU time	338.63 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:52:57 PM PDT 24
Peak memory	204676 kb
Host	smart-0c413852-40a7-47cb-96b2-a3ab38e3131f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=262150571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.262150571
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2214339935
Short name	T47
Test name
Test status
Simulation time	34834335212 ps
CPU time	121.81 seconds
Started	Apr 28 12:47:21 PM PDT 24
Finished	Apr 28 12:49:23 PM PDT 24
Peak memory	205128 kb
Host	smart-e430458a-6efd-4a30-a17b-0f8ad3b0a6ab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2214339935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2214339935
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.4032165204
Short name	T691
Test name
Test status
Simulation time	201383031 ps
CPU time	9.9 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:28 PM PDT 24
Peak memory	204592 kb
Host	smart-563769b6-531d-4309-b120-4d57abeddb10
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032165204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4032165204
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.626996206
Short name	T734
Test name
Test status
Simulation time	457039275 ps
CPU time	17.76 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:36 PM PDT 24
Peak memory	203392 kb
Host	smart-9166dd8d-62d9-422a-a726-402ec7349847
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626996206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.626996206
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.2784473190
Short name	T66
Test name
Test status
Simulation time	161389103 ps
CPU time	3.5 seconds
Started	Apr 28 12:47:09 PM PDT 24
Finished	Apr 28 12:47:13 PM PDT 24
Peak memory	203456 kb
Host	smart-fb159def-810b-4828-add2-11eb090731c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2784473190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2784473190
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1953142666
Short name	T756
Test name
Test status
Simulation time	7288987777 ps
CPU time	30.68 seconds
Started	Apr 28 12:47:14 PM PDT 24
Finished	Apr 28 12:47:47 PM PDT 24
Peak memory	203412 kb
Host	smart-84e4be85-b65a-4276-a464-6ccb35160c6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953142666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1953142666
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3075302005
Short name	T655
Test name
Test status
Simulation time	3152453810 ps
CPU time	29.62 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:47:47 PM PDT 24
Peak memory	203552 kb
Host	smart-548cfd2f-aad5-4034-a545-1a4d4064e531
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3075302005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3075302005
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.571994622
Short name	T547
Test name
Test status
Simulation time	39394920 ps
CPU time	2.15 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:47:19 PM PDT 24
Peak memory	203320 kb
Host	smart-24b4b734-f60b-452d-b933-82ede202763e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571994622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.571994622
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.316628616
Short name	T640
Test name
Test status
Simulation time	7996427227 ps
CPU time	215.99 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:50:54 PM PDT 24
Peak memory	211728 kb
Host	smart-b7d2231d-82c6-442b-99cb-c6bd071cd200
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=316628616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.316628616
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.97460844
Short name	T238
Test name
Test status
Simulation time	921542976 ps
CPU time	21.19 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:40 PM PDT 24
Peak memory	204792 kb
Host	smart-60373635-b4cd-440d-a328-0ce129331e09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=97460844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.97460844
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3462667840
Short name	T211
Test name
Test status
Simulation time	228542366 ps
CPU time	84.02 seconds
Started	Apr 28 12:47:13 PM PDT 24
Finished	Apr 28 12:48:38 PM PDT 24
Peak memory	208108 kb
Host	smart-7d751d9d-9ca4-4816-bb7c-a4204ad702fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462667840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.3462667840
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1643696849
Short name	T852
Test name
Test status
Simulation time	6478557152 ps
CPU time	334.5 seconds
Started	Apr 28 12:47:14 PM PDT 24
Finished	Apr 28 12:52:49 PM PDT 24
Peak memory	220564 kb
Host	smart-1cffe465-2c6e-4cd8-a916-4a59b7903291
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1643696849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1643696849
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3920481209
Short name	T716
Test name
Test status
Simulation time	150593078 ps
CPU time	4.91 seconds
Started	Apr 28 12:47:18 PM PDT 24
Finished	Apr 28 12:47:24 PM PDT 24
Peak memory	204740 kb
Host	smart-91c324d8-aa45-4abf-8bc8-72fd3e2767e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3920481209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3920481209
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3384936122
Short name	T474
Test name
Test status
Simulation time	625296353 ps
CPU time	19.99 seconds
Started	Apr 28 12:47:11 PM PDT 24
Finished	Apr 28 12:47:32 PM PDT 24
Peak memory	205728 kb
Host	smart-18e4585a-3480-4da2-b3d0-d15cfbc68720
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3384936122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3384936122
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1139685569
Short name	T664
Test name
Test status
Simulation time	116911669006 ps
CPU time	478.34 seconds
Started	Apr 28 12:47:12 PM PDT 24
Finished	Apr 28 12:55:11 PM PDT 24
Peak memory	211708 kb
Host	smart-7427b9c0-dedb-4bba-89cf-a85b1ad7bd1a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1139685569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.1139685569
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.279003996
Short name	T303
Test name
Test status
Simulation time	127519707 ps
CPU time	8.75 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:27 PM PDT 24
Peak memory	203620 kb
Host	smart-1571ddca-1105-4a3d-9eb2-e60bc5adef0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=279003996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.279003996
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.1542588446
Short name	T565
Test name
Test status
Simulation time	24957449 ps
CPU time	2.9 seconds
Started	Apr 28 12:47:13 PM PDT 24
Finished	Apr 28 12:47:17 PM PDT 24
Peak memory	203312 kb
Host	smart-1d846ea3-2c62-4970-a7aa-a7818f1b29e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1542588446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1542588446
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.2904820828
Short name	T791
Test name
Test status
Simulation time	797753150 ps
CPU time	9.12 seconds
Started	Apr 28 12:47:13 PM PDT 24
Finished	Apr 28 12:47:23 PM PDT 24
Peak memory	204608 kb
Host	smart-5b87ca86-4072-4f20-8d03-22fd56a27cab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2904820828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2904820828
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2676956318
Short name	T551
Test name
Test status
Simulation time	21304978285 ps
CPU time	145.73 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:49:42 PM PDT 24
Peak memory	211716 kb
Host	smart-8cef3a0d-c1d9-4f60-bacd-119770cb75c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676956318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2676956318
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1686371220
Short name	T430
Test name
Test status
Simulation time	46380158234 ps
CPU time	232.07 seconds
Started	Apr 28 12:47:12 PM PDT 24
Finished	Apr 28 12:51:05 PM PDT 24
Peak memory	204708 kb
Host	smart-900f525d-60ca-4064-876a-5ca6be68a4e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1686371220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1686371220
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1880781391
Short name	T580
Test name
Test status
Simulation time	461206902 ps
CPU time	21.02 seconds
Started	Apr 28 12:47:14 PM PDT 24
Finished	Apr 28 12:47:37 PM PDT 24
Peak memory	211684 kb
Host	smart-4f890d24-9d1e-4a5f-beef-2bcba8390249
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880781391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1880781391
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.1352477446
Short name	T522
Test name
Test status
Simulation time	105351701 ps
CPU time	5.6 seconds
Started	Apr 28 12:47:13 PM PDT 24
Finished	Apr 28 12:47:20 PM PDT 24
Peak memory	204004 kb
Host	smart-7f35e2c1-7c71-45c9-9276-55b20babd059
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1352477446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1352477446
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.1085449360
Short name	T277
Test name
Test status
Simulation time	27041112 ps
CPU time	2.14 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:47:19 PM PDT 24
Peak memory	203484 kb
Host	smart-76fef595-ae54-4bfd-8b9b-a36f5fd1f112
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1085449360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1085449360
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.116307189
Short name	T326
Test name
Test status
Simulation time	5830051069 ps
CPU time	28.79 seconds
Started	Apr 28 12:47:16 PM PDT 24
Finished	Apr 28 12:47:46 PM PDT 24
Peak memory	203512 kb
Host	smart-67219af4-acd6-483d-9b0c-d8348d83e538
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=116307189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.116307189
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3804297986
Short name	T457
Test name
Test status
Simulation time	3614213428 ps
CPU time	24.54 seconds
Started	Apr 28 12:47:14 PM PDT 24
Finished	Apr 28 12:47:40 PM PDT 24
Peak memory	203524 kb
Host	smart-224035e3-85d9-4675-a686-a79aeea8fc81
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3804297986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3804297986
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2083789846
Short name	T827
Test name
Test status
Simulation time	44359865 ps
CPU time	2.2 seconds
Started	Apr 28 12:47:13 PM PDT 24
Finished	Apr 28 12:47:16 PM PDT 24
Peak memory	203376 kb
Host	smart-d99e187e-99a8-4943-b1c9-9490e442947c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083789846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2083789846
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.1389204972
Short name	T607
Test name
Test status
Simulation time	549333488 ps
CPU time	28.38 seconds
Started	Apr 28 12:47:20 PM PDT 24
Finished	Apr 28 12:47:49 PM PDT 24
Peak memory	206172 kb
Host	smart-b233a4c0-e18c-4dcb-ad9d-aabb27624805
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1389204972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1389204972
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.127637256
Short name	T537
Test name
Test status
Simulation time	10514301594 ps
CPU time	192.01 seconds
Started	Apr 28 12:47:19 PM PDT 24
Finished	Apr 28 12:50:32 PM PDT 24
Peak memory	211580 kb
Host	smart-1bdd1a66-9e5a-4d8a-8374-ed7d7a3c2506
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=127637256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.127637256
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1332245262
Short name	T768
Test name
Test status
Simulation time	7539297 ps
CPU time	5.76 seconds
Started	Apr 28 12:47:19 PM PDT 24
Finished	Apr 28 12:47:25 PM PDT 24
Peak memory	203400 kb
Host	smart-81feab22-1b11-41a2-944a-dc0d0210b949
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1332245262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1332245262
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3787066110
Short name	T758
Test name
Test status
Simulation time	590843042 ps
CPU time	194.03 seconds
Started	Apr 28 12:47:19 PM PDT 24
Finished	Apr 28 12:50:34 PM PDT 24
Peak memory	219872 kb
Host	smart-a4c85695-1a65-4368-87fc-61c97dc3db0d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3787066110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3787066110
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.4134616255
Short name	T558
Test name
Test status
Simulation time	96520659 ps
CPU time	11.8 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:30 PM PDT 24
Peak memory	211540 kb
Host	smart-d08b61f7-423e-4db5-a693-4289634a6a4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134616255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.4134616255
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3699147751
Short name	T473
Test name
Test status
Simulation time	1389057658 ps
CPU time	37.77 seconds
Started	Apr 28 12:47:19 PM PDT 24
Finished	Apr 28 12:47:58 PM PDT 24
Peak memory	205908 kb
Host	smart-cc5494d4-9d99-4dbf-8a26-a89bb7d9e96e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3699147751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3699147751
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.260698687
Short name	T784
Test name
Test status
Simulation time	97213362886 ps
CPU time	529.77 seconds
Started	Apr 28 12:47:20 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	211656 kb
Host	smart-28fce80e-71af-4feb-9453-b52756fdb44c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=260698687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo w_rsp.260698687
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3643668003
Short name	T494
Test name
Test status
Simulation time	602973812 ps
CPU time	18.54 seconds
Started	Apr 28 12:47:25 PM PDT 24
Finished	Apr 28 12:47:45 PM PDT 24
Peak memory	203476 kb
Host	smart-a723d91c-0f16-4275-9752-ddbe08a32ed2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3643668003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3643668003
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.4134498138
Short name	T614
Test name
Test status
Simulation time	1782360293 ps
CPU time	33.79 seconds
Started	Apr 28 12:47:23 PM PDT 24
Finished	Apr 28 12:47:57 PM PDT 24
Peak memory	203468 kb
Host	smart-4607ab91-007c-4cbf-80f4-f0fd142a61e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134498138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4134498138
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.2420613262
Short name	T606
Test name
Test status
Simulation time	245947050 ps
CPU time	4.97 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:23 PM PDT 24
Peak memory	204212 kb
Host	smart-c5346685-b3fa-4d31-9c91-579f69119216
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2420613262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2420613262
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2953526682
Short name	T339
Test name
Test status
Simulation time	117647354092 ps
CPU time	169.3 seconds
Started	Apr 28 12:47:18 PM PDT 24
Finished	Apr 28 12:50:08 PM PDT 24
Peak memory	204916 kb
Host	smart-fc1cc99a-4a05-4699-af26-8442345b456a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953526682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2953526682
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3492801303
Short name	T225
Test name
Test status
Simulation time	8153823304 ps
CPU time	69.45 seconds
Started	Apr 28 12:47:20 PM PDT 24
Finished	Apr 28 12:48:30 PM PDT 24
Peak memory	204776 kb
Host	smart-5541c5c0-d26a-478e-b11f-f4897f3032ea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3492801303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3492801303
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3172024094
Short name	T131
Test name
Test status
Simulation time	38731478 ps
CPU time	5.5 seconds
Started	Apr 28 12:47:20 PM PDT 24
Finished	Apr 28 12:47:26 PM PDT 24
Peak memory	204484 kb
Host	smart-4dd25823-2a23-4784-9ddd-95c18429c976
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172024094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3172024094
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.3712597273
Short name	T741
Test name
Test status
Simulation time	103685940 ps
CPU time	8.28 seconds
Started	Apr 28 12:47:21 PM PDT 24
Finished	Apr 28 12:47:30 PM PDT 24
Peak memory	203892 kb
Host	smart-1b64fef6-5dd6-4064-a80b-9086c5a13108
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3712597273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3712597273
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.1005101743
Short name	T603
Test name
Test status
Simulation time	137404281 ps
CPU time	2.91 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:22 PM PDT 24
Peak memory	203388 kb
Host	smart-7b89177c-639a-4cb5-abed-a9b2028376b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1005101743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1005101743
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2274374557
Short name	T745
Test name
Test status
Simulation time	6520887912 ps
CPU time	29.17 seconds
Started	Apr 28 12:47:18 PM PDT 24
Finished	Apr 28 12:47:48 PM PDT 24
Peak memory	203420 kb
Host	smart-b0bc8c24-f9a2-439e-8c31-ef611596cf78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274374557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2274374557
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2990478574
Short name	T406
Test name
Test status
Simulation time	16867291866 ps
CPU time	44.5 seconds
Started	Apr 28 12:47:19 PM PDT 24
Finished	Apr 28 12:48:04 PM PDT 24
Peak memory	203400 kb
Host	smart-3a065b08-5503-40e3-9bb7-7678c353a1d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2990478574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2990478574
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1904733870
Short name	T505
Test name
Test status
Simulation time	32989501 ps
CPU time	1.93 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:20 PM PDT 24
Peak memory	203452 kb
Host	smart-cab17f93-41c1-405b-a471-fee876ab9c1e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904733870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1904733870
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.1180802442
Short name	T575
Test name
Test status
Simulation time	242723004 ps
CPU time	19.82 seconds
Started	Apr 28 12:47:21 PM PDT 24
Finished	Apr 28 12:47:41 PM PDT 24
Peak memory	204944 kb
Host	smart-501cedba-96cd-46c4-9d12-4051d72b0d4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1180802442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1180802442
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2475035615
Short name	T386
Test name
Test status
Simulation time	1470107013 ps
CPU time	107.6 seconds
Started	Apr 28 12:47:22 PM PDT 24
Finished	Apr 28 12:49:10 PM PDT 24
Peak memory	211676 kb
Host	smart-a04874e6-14aa-48f7-83bd-5fb46b4fe9a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2475035615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2475035615
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.4087647467
Short name	T155
Test name
Test status
Simulation time	2636550823 ps
CPU time	228.93 seconds
Started	Apr 28 12:47:25 PM PDT 24
Finished	Apr 28 12:51:14 PM PDT 24
Peak memory	208480 kb
Host	smart-729e3574-1a68-471d-8d0e-e75e997b1d96
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4087647467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.4087647467
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4041995681
Short name	T588
Test name
Test status
Simulation time	4480476988 ps
CPU time	221.38 seconds
Started	Apr 28 12:47:33 PM PDT 24
Finished	Apr 28 12:51:15 PM PDT 24
Peak memory	219784 kb
Host	smart-11339f89-2d6a-404a-b4b6-5eddcfd214b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4041995681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.4041995681
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2977788846
Short name	T197
Test name
Test status
Simulation time	398809431 ps
CPU time	8.72 seconds
Started	Apr 28 12:47:35 PM PDT 24
Finished	Apr 28 12:47:45 PM PDT 24
Peak memory	204852 kb
Host	smart-d5b94246-9f40-408f-bc3f-46bc6cc07088
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2977788846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2977788846
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2773384823
Short name	T289
Test name
Test status
Simulation time	46098150 ps
CPU time	4.38 seconds
Started	Apr 28 12:47:32 PM PDT 24
Finished	Apr 28 12:47:37 PM PDT 24
Peak memory	203588 kb
Host	smart-44843a98-4eb9-4125-8ce5-d5ce32d09e76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2773384823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2773384823
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4003288207
Short name	T124
Test name
Test status
Simulation time	61155394409 ps
CPU time	300.87 seconds
Started	Apr 28 12:47:27 PM PDT 24
Finished	Apr 28 12:52:29 PM PDT 24
Peak memory	206008 kb
Host	smart-3b73bee1-b4ca-4c6c-951d-55ad541e1a44
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4003288207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.4003288207
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.276101073
Short name	T264
Test name
Test status
Simulation time	799679754 ps
CPU time	27.32 seconds
Started	Apr 28 12:47:32 PM PDT 24
Finished	Apr 28 12:48:00 PM PDT 24
Peak memory	203692 kb
Host	smart-ac079430-5f57-4900-996e-dc073c18575f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276101073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.276101073
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.2375022501
Short name	T359
Test name
Test status
Simulation time	884679777 ps
CPU time	28.31 seconds
Started	Apr 28 12:47:29 PM PDT 24
Finished	Apr 28 12:47:58 PM PDT 24
Peak memory	203416 kb
Host	smart-0a8f18de-5cf4-405e-95e7-a49e8b38122c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2375022501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2375022501
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.3278815907
Short name	T578
Test name
Test status
Simulation time	2398884349 ps
CPU time	19.62 seconds
Started	Apr 28 12:47:25 PM PDT 24
Finished	Apr 28 12:47:45 PM PDT 24
Peak memory	204788 kb
Host	smart-156cfafb-5107-4ad1-85d0-91f4062aa506
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3278815907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3278815907
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2612581165
Short name	T424
Test name
Test status
Simulation time	33891026214 ps
CPU time	73.46 seconds
Started	Apr 28 12:47:32 PM PDT 24
Finished	Apr 28 12:48:46 PM PDT 24
Peak memory	204780 kb
Host	smart-0f5303bc-cfb5-4a73-95ac-b272dd2be8fd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612581165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2612581165
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3445447308
Short name	T403
Test name
Test status
Simulation time	57568859393 ps
CPU time	163.78 seconds
Started	Apr 28 12:47:30 PM PDT 24
Finished	Apr 28 12:50:15 PM PDT 24
Peak memory	205344 kb
Host	smart-a7281d9b-f389-4af6-969e-3b74ec47f264
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3445447308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3445447308
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2989129590
Short name	T750
Test name
Test status
Simulation time	272904960 ps
CPU time	12.7 seconds
Started	Apr 28 12:47:27 PM PDT 24
Finished	Apr 28 12:47:40 PM PDT 24
Peak memory	211660 kb
Host	smart-8687de1f-9e91-45f1-aaea-b95d12846cf6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989129590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2989129590
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.3285164163
Short name	T313
Test name
Test status
Simulation time	3946262308 ps
CPU time	23.81 seconds
Started	Apr 28 12:47:25 PM PDT 24
Finished	Apr 28 12:47:50 PM PDT 24
Peak memory	204072 kb
Host	smart-b4db6338-e985-4fd7-b694-176c7d7485f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3285164163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3285164163
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.4243572247
Short name	T331
Test name
Test status
Simulation time	142809700 ps
CPU time	3.7 seconds
Started	Apr 28 12:47:30 PM PDT 24
Finished	Apr 28 12:47:35 PM PDT 24
Peak memory	203468 kb
Host	smart-dcb81f2c-c65e-4804-96a0-ca6a1840ba5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4243572247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.4243572247
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1867151114
Short name	T842
Test name
Test status
Simulation time	8095261078 ps
CPU time	32.11 seconds
Started	Apr 28 12:47:30 PM PDT 24
Finished	Apr 28 12:48:03 PM PDT 24
Peak memory	203436 kb
Host	smart-d9ba429f-0251-447a-98de-f582f24aa0e9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867151114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1867151114
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2259682484
Short name	T391
Test name
Test status
Simulation time	5427224149 ps
CPU time	35.98 seconds
Started	Apr 28 12:47:28 PM PDT 24
Finished	Apr 28 12:48:05 PM PDT 24
Peak memory	203452 kb
Host	smart-29c914b5-ed60-46ad-98fd-f33aceabd9e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2259682484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2259682484
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4236863601
Short name	T41
Test name
Test status
Simulation time	29234650 ps
CPU time	2.49 seconds
Started	Apr 28 12:47:31 PM PDT 24
Finished	Apr 28 12:47:34 PM PDT 24
Peak memory	203424 kb
Host	smart-68579dc5-6f30-410b-a405-f2ba53d9d35b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236863601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4236863601
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.2401744468
Short name	T153
Test name
Test status
Simulation time	883312119 ps
CPU time	107.55 seconds
Started	Apr 28 12:47:31 PM PDT 24
Finished	Apr 28 12:49:19 PM PDT 24
Peak memory	206844 kb
Host	smart-210c950e-cede-416f-878e-9fe0d5d23477
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401744468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2401744468
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3463618508
Short name	T336
Test name
Test status
Simulation time	238558592 ps
CPU time	24.25 seconds
Started	Apr 28 12:47:34 PM PDT 24
Finished	Apr 28 12:47:59 PM PDT 24
Peak memory	204792 kb
Host	smart-2b3a7d15-6143-4636-8f57-87e64b0ee24e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463618508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3463618508
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1607831319
Short name	T353
Test name
Test status
Simulation time	117439998 ps
CPU time	50.86 seconds
Started	Apr 28 12:47:28 PM PDT 24
Finished	Apr 28 12:48:20 PM PDT 24
Peak memory	208020 kb
Host	smart-fa3ea308-50cd-4d60-9cbe-c44b333f238b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1607831319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1607831319
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3164735578
Short name	T748
Test name
Test status
Simulation time	163421327 ps
CPU time	43.7 seconds
Started	Apr 28 12:47:35 PM PDT 24
Finished	Apr 28 12:48:20 PM PDT 24
Peak memory	207992 kb
Host	smart-488f89a4-c9ce-4f5f-ab41-9c5a6a935698
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3164735578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.3164735578
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1839697053
Short name	T203
Test name
Test status
Simulation time	1088260173 ps
CPU time	32.97 seconds
Started	Apr 28 12:47:27 PM PDT 24
Finished	Apr 28 12:48:01 PM PDT 24
Peak memory	205104 kb
Host	smart-11fc659b-844a-4c32-af87-ced18d4a54df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1839697053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1839697053
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.194675356
Short name	T49
Test name
Test status
Simulation time	772378421 ps
CPU time	31.14 seconds
Started	Apr 28 12:47:31 PM PDT 24
Finished	Apr 28 12:48:02 PM PDT 24
Peak memory	205776 kb
Host	smart-36b1412b-d9ab-43f6-bb3d-2f67ebbd02cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194675356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.194675356
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1184786420
Short name	T597
Test name
Test status
Simulation time	556198914 ps
CPU time	12.13 seconds
Started	Apr 28 12:47:31 PM PDT 24
Finished	Apr 28 12:47:44 PM PDT 24
Peak memory	203880 kb
Host	smart-19aba3f3-06cf-4a30-93a5-c1ff91ef5c97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1184786420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1184786420
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.3517922383
Short name	T308
Test name
Test status
Simulation time	433182538 ps
CPU time	11.07 seconds
Started	Apr 28 12:47:35 PM PDT 24
Finished	Apr 28 12:47:47 PM PDT 24
Peak memory	203388 kb
Host	smart-4a2dfbfb-011c-425f-8679-cc724cc0ddf0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3517922383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3517922383
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.1851855880
Short name	T673
Test name
Test status
Simulation time	98979036 ps
CPU time	11.94 seconds
Started	Apr 28 12:47:32 PM PDT 24
Finished	Apr 28 12:47:45 PM PDT 24
Peak memory	204484 kb
Host	smart-41606df6-16e4-48c6-a85f-8a3ea02e01ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1851855880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1851855880
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.389606006
Short name	T375
Test name
Test status
Simulation time	23729978534 ps
CPU time	126.57 seconds
Started	Apr 28 12:47:32 PM PDT 24
Finished	Apr 28 12:49:39 PM PDT 24
Peak memory	204836 kb
Host	smart-6d5069d5-f6f0-4cdf-95f0-ffca0f26fc6c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=389606006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.389606006
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3951343222
Short name	T259
Test name
Test status
Simulation time	3519121124 ps
CPU time	28.92 seconds
Started	Apr 28 12:47:34 PM PDT 24
Finished	Apr 28 12:48:04 PM PDT 24
Peak memory	204200 kb
Host	smart-d37d6fe3-cf91-4548-a73a-eff3839cbca0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3951343222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3951343222
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3323829685
Short name	T161
Test name
Test status
Simulation time	199333811 ps
CPU time	19.91 seconds
Started	Apr 28 12:47:29 PM PDT 24
Finished	Apr 28 12:47:50 PM PDT 24
Peak memory	204640 kb
Host	smart-581ea0f9-5218-4513-b6ee-b9be60d4c7af
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323829685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3323829685
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.3918337167
Short name	T18
Test name
Test status
Simulation time	60012453 ps
CPU time	2.62 seconds
Started	Apr 28 12:47:30 PM PDT 24
Finished	Apr 28 12:47:33 PM PDT 24
Peak memory	203484 kb
Host	smart-8f1e0f65-d741-4539-ac2a-d2891b66df2c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918337167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3918337167
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.2279065668
Short name	T246
Test name
Test status
Simulation time	158374821 ps
CPU time	2.96 seconds
Started	Apr 28 12:47:32 PM PDT 24
Finished	Apr 28 12:47:35 PM PDT 24
Peak memory	203396 kb
Host	smart-9588ccec-8606-4265-8c52-5dc550038bd2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2279065668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2279065668
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3685843269
Short name	T602
Test name
Test status
Simulation time	28281657680 ps
CPU time	41.5 seconds
Started	Apr 28 12:47:29 PM PDT 24
Finished	Apr 28 12:48:11 PM PDT 24
Peak memory	203500 kb
Host	smart-e395f97f-7b24-41c9-b3eb-66933bdbd40e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685843269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3685843269
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.467811078
Short name	T63
Test name
Test status
Simulation time	3394656849 ps
CPU time	23.82 seconds
Started	Apr 28 12:47:29 PM PDT 24
Finished	Apr 28 12:47:54 PM PDT 24
Peak memory	203532 kb
Host	smart-333b5a9a-0119-4e66-ad6f-9f563066158a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=467811078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.467811078
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1108179869
Short name	T397
Test name
Test status
Simulation time	156980477 ps
CPU time	2.36 seconds
Started	Apr 28 12:47:37 PM PDT 24
Finished	Apr 28 12:47:40 PM PDT 24
Peak memory	203348 kb
Host	smart-f99b96ec-2949-4752-88a5-1a36b622f600
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108179869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1108179869
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.470176282
Short name	T764
Test name
Test status
Simulation time	7473880609 ps
CPU time	219.01 seconds
Started	Apr 28 12:47:31 PM PDT 24
Finished	Apr 28 12:51:11 PM PDT 24
Peak memory	209320 kb
Host	smart-99643f33-0179-46a8-a8ba-419ca50a7814
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=470176282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.470176282
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3930977378
Short name	T210
Test name
Test status
Simulation time	53150925 ps
CPU time	25.9 seconds
Started	Apr 28 12:47:32 PM PDT 24
Finished	Apr 28 12:47:59 PM PDT 24
Peak memory	206620 kb
Host	smart-dfecebb8-a443-47a9-8b72-959b1ada5760
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930977378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3930977378
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3215053186
Short name	T869
Test name
Test status
Simulation time	179442052 ps
CPU time	60.37 seconds
Started	Apr 28 12:47:33 PM PDT 24
Finished	Apr 28 12:48:34 PM PDT 24
Peak memory	208056 kb
Host	smart-49e1da06-df89-41f3-aa25-7a437972e03a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215053186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3215053186
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1992415681
Short name	T75
Test name
Test status
Simulation time	1096118025 ps
CPU time	29.18 seconds
Started	Apr 28 12:47:34 PM PDT 24
Finished	Apr 28 12:48:04 PM PDT 24
Peak memory	204916 kb
Host	smart-4b173105-6d63-47dc-a5ba-35b0458cecd3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1992415681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1992415681
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2353964225
Short name	T608
Test name
Test status
Simulation time	247618657 ps
CPU time	4.39 seconds
Started	Apr 28 12:47:34 PM PDT 24
Finished	Apr 28 12:47:39 PM PDT 24
Peak memory	203424 kb
Host	smart-c020fc74-8267-40cd-bd7c-502282a368e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2353964225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2353964225
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3560606837
Short name	T823
Test name
Test status
Simulation time	37394215147 ps
CPU time	345.25 seconds
Started	Apr 28 12:47:35 PM PDT 24
Finished	Apr 28 12:53:21 PM PDT 24
Peak memory	206620 kb
Host	smart-b505ed3c-3ac3-4f3c-bd0f-093c9fdefbac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3560606837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3560606837
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3412863587
Short name	T787
Test name
Test status
Simulation time	952956724 ps
CPU time	19.38 seconds
Started	Apr 28 12:47:34 PM PDT 24
Finished	Apr 28 12:47:54 PM PDT 24
Peak memory	203924 kb
Host	smart-378e8b6f-4f38-461a-b29f-ede2a4747ff7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3412863587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3412863587
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.1970438398
Short name	T376
Test name
Test status
Simulation time	1678531434 ps
CPU time	27.43 seconds
Started	Apr 28 12:47:38 PM PDT 24
Finished	Apr 28 12:48:06 PM PDT 24
Peak memory	203492 kb
Host	smart-f9a5debd-7024-46b5-bf51-c963c182347a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1970438398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1970438398
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.2307433948
Short name	T196
Test name
Test status
Simulation time	583256646 ps
CPU time	12.06 seconds
Started	Apr 28 12:47:36 PM PDT 24
Finished	Apr 28 12:47:49 PM PDT 24
Peak memory	211524 kb
Host	smart-db652e38-d5a7-4d08-abc3-9445e5ef54a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307433948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2307433948
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.169846341
Short name	T86
Test name
Test status
Simulation time	53263136877 ps
CPU time	204.55 seconds
Started	Apr 28 12:47:36 PM PDT 24
Finished	Apr 28 12:51:02 PM PDT 24
Peak memory	204952 kb
Host	smart-3a7a11ab-7a3b-434c-a2b7-337482577501
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=169846341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.169846341
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2223384935
Short name	T513
Test name
Test status
Simulation time	17454634955 ps
CPU time	84.04 seconds
Started	Apr 28 12:47:41 PM PDT 24
Finished	Apr 28 12:49:05 PM PDT 24
Peak memory	204948 kb
Host	smart-26f393ef-dfa8-4c60-b55e-341fe492dbe0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2223384935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2223384935
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3537167089
Short name	T515
Test name
Test status
Simulation time	51552649 ps
CPU time	4.76 seconds
Started	Apr 28 12:47:40 PM PDT 24
Finished	Apr 28 12:47:45 PM PDT 24
Peak memory	204404 kb
Host	smart-7f61cb21-3531-47d1-9af2-ab9b7fe7b92a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537167089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3537167089
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.2174815185
Short name	T413
Test name
Test status
Simulation time	35698006 ps
CPU time	2.39 seconds
Started	Apr 28 12:47:35 PM PDT 24
Finished	Apr 28 12:47:39 PM PDT 24
Peak memory	203372 kb
Host	smart-1817283f-18f0-470d-ae09-4c19eff370f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2174815185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2174815185
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.524205972
Short name	T828
Test name
Test status
Simulation time	408064535 ps
CPU time	4.15 seconds
Started	Apr 28 12:47:33 PM PDT 24
Finished	Apr 28 12:47:37 PM PDT 24
Peak memory	203488 kb
Host	smart-3d01d60e-63e6-406f-a694-c815f7e028bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=524205972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.524205972
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.601085376
Short name	T725
Test name
Test status
Simulation time	6524403630 ps
CPU time	33.38 seconds
Started	Apr 28 12:47:33 PM PDT 24
Finished	Apr 28 12:48:07 PM PDT 24
Peak memory	203560 kb
Host	smart-a10eb244-30af-4a6e-a7bb-a61af5570c79
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=601085376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.601085376
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1659509863
Short name	T796
Test name
Test status
Simulation time	4563849119 ps
CPU time	30.22 seconds
Started	Apr 28 12:47:37 PM PDT 24
Finished	Apr 28 12:48:07 PM PDT 24
Peak memory	203396 kb
Host	smart-fa3772ee-a9f4-4f65-9b30-bfab6b2a6c5b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1659509863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1659509863
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.782095658
Short name	T165
Test name
Test status
Simulation time	31944573 ps
CPU time	2.63 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:47:46 PM PDT 24
Peak memory	203436 kb
Host	smart-7e539836-a2c4-4d48-b12d-64ce176dee09
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782095658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.782095658
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.2301225708
Short name	T844
Test name
Test status
Simulation time	526858624 ps
CPU time	23.72 seconds
Started	Apr 28 12:47:38 PM PDT 24
Finished	Apr 28 12:48:03 PM PDT 24
Peak memory	211560 kb
Host	smart-9219cb35-cab4-41ac-8b00-b943a6f63a16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2301225708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2301225708
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1946659416
Short name	T634
Test name
Test status
Simulation time	1142653790 ps
CPU time	113.54 seconds
Started	Apr 28 12:47:42 PM PDT 24
Finished	Apr 28 12:49:36 PM PDT 24
Peak memory	205140 kb
Host	smart-c9c13956-4505-4ec7-80f8-dcfc8fafccd8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1946659416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1946659416
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3871154171
Short name	T194
Test name
Test status
Simulation time	1266886401 ps
CPU time	208.44 seconds
Started	Apr 28 12:47:36 PM PDT 24
Finished	Apr 28 12:51:05 PM PDT 24
Peak memory	208096 kb
Host	smart-028dd06f-e736-466e-9a58-201167aae0c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3871154171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3871154171
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3629160700
Short name	T120
Test name
Test status
Simulation time	5641847304 ps
CPU time	176.26 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:50:40 PM PDT 24
Peak memory	211660 kb
Host	smart-a8f4e6b5-8602-4ba2-abd0-ca3e950d77aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3629160700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3629160700
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3135250892
Short name	T487
Test name
Test status
Simulation time	33477747 ps
CPU time	5.52 seconds
Started	Apr 28 12:47:39 PM PDT 24
Finished	Apr 28 12:47:45 PM PDT 24
Peak memory	211680 kb
Host	smart-07016ba0-2d14-46ea-8941-038a22e54254
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3135250892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3135250892
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1279897900
Short name	T183
Test name
Test status
Simulation time	171377310 ps
CPU time	13.27 seconds
Started	Apr 28 12:47:39 PM PDT 24
Finished	Apr 28 12:47:53 PM PDT 24
Peak memory	204464 kb
Host	smart-105cb380-f66e-4aca-a4c3-b5c222d31b9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1279897900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1279897900
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3166388164
Short name	T733
Test name
Test status
Simulation time	150759513791 ps
CPU time	619.58 seconds
Started	Apr 28 12:47:47 PM PDT 24
Finished	Apr 28 12:58:07 PM PDT 24
Peak memory	207128 kb
Host	smart-3d96cd18-9444-460f-8839-9e6ff38343c7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3166388164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3166388164
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3886751227
Short name	T204
Test name
Test status
Simulation time	128621293 ps
CPU time	11.8 seconds
Started	Apr 28 12:47:41 PM PDT 24
Finished	Apr 28 12:47:53 PM PDT 24
Peak memory	203596 kb
Host	smart-8c00666f-7274-478c-82e5-176e61fdf2ac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3886751227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3886751227
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.1783052070
Short name	T71
Test name
Test status
Simulation time	576108017 ps
CPU time	10.62 seconds
Started	Apr 28 12:47:46 PM PDT 24
Finished	Apr 28 12:47:57 PM PDT 24
Peak memory	203432 kb
Host	smart-5bf017e5-35b3-44aa-8229-20e3e8b6cf78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1783052070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1783052070
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.536231497
Short name	T425
Test name
Test status
Simulation time	5314085164 ps
CPU time	33.09 seconds
Started	Apr 28 12:47:45 PM PDT 24
Finished	Apr 28 12:48:19 PM PDT 24
Peak memory	205440 kb
Host	smart-1e9cf2ae-aa50-4926-8ffe-ee7c799a33a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=536231497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.536231497
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.766672356
Short name	T350
Test name
Test status
Simulation time	44447195228 ps
CPU time	214.92 seconds
Started	Apr 28 12:47:44 PM PDT 24
Finished	Apr 28 12:51:19 PM PDT 24
Peak memory	211704 kb
Host	smart-a6169bb3-a12f-447a-af33-a076d67fca98
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=766672356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.766672356
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.836470258
Short name	T458
Test name
Test status
Simulation time	29155569426 ps
CPU time	259.13 seconds
Started	Apr 28 12:47:39 PM PDT 24
Finished	Apr 28 12:51:59 PM PDT 24
Peak memory	205200 kb
Host	smart-fdb6da96-ccc4-4bb2-9972-c0002a8e1322
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=836470258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.836470258
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1917486291
Short name	T582
Test name
Test status
Simulation time	228549576 ps
CPU time	20.46 seconds
Started	Apr 28 12:47:39 PM PDT 24
Finished	Apr 28 12:48:00 PM PDT 24
Peak memory	204864 kb
Host	smart-4c8a40fe-b7eb-4d3e-8379-93fdcbe11de7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917486291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1917486291
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.511921478
Short name	T777
Test name
Test status
Simulation time	623225710 ps
CPU time	7.13 seconds
Started	Apr 28 12:47:39 PM PDT 24
Finished	Apr 28 12:47:46 PM PDT 24
Peak memory	203412 kb
Host	smart-bcd0a22c-57b8-4cfb-9005-95b55f1047dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=511921478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.511921478
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.1075167707
Short name	T621
Test name
Test status
Simulation time	29604628 ps
CPU time	2.21 seconds
Started	Apr 28 12:47:39 PM PDT 24
Finished	Apr 28 12:47:42 PM PDT 24
Peak memory	203344 kb
Host	smart-302beb67-bac9-4126-93ec-a692e0cac139
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1075167707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1075167707
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.673876889
Short name	T392
Test name
Test status
Simulation time	3927900366 ps
CPU time	24.43 seconds
Started	Apr 28 12:47:35 PM PDT 24
Finished	Apr 28 12:48:00 PM PDT 24
Peak memory	203428 kb
Host	smart-8c7a67e4-6b6e-4c5e-88a0-2d5f9970d769
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=673876889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.673876889
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.486323061
Short name	T680
Test name
Test status
Simulation time	3928747042 ps
CPU time	21.35 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:48:05 PM PDT 24
Peak memory	203392 kb
Host	smart-015ea6d8-905a-43d2-a0f2-b004cfb691c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=486323061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.486323061
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1026869471
Short name	T557
Test name
Test status
Simulation time	53078046 ps
CPU time	1.98 seconds
Started	Apr 28 12:47:34 PM PDT 24
Finished	Apr 28 12:47:37 PM PDT 24
Peak memory	203492 kb
Host	smart-a0db9287-4977-4aa0-b4e3-98f5c1226cd9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026869471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1026869471
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.3679919850
Short name	T436
Test name
Test status
Simulation time	6748164958 ps
CPU time	167.35 seconds
Started	Apr 28 12:47:45 PM PDT 24
Finished	Apr 28 12:50:33 PM PDT 24
Peak memory	207304 kb
Host	smart-a08fa6ef-3e17-4848-acdc-dd5e4a449168
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3679919850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3679919850
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.722297627
Short name	T506
Test name
Test status
Simulation time	13510604022 ps
CPU time	234.96 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:51:38 PM PDT 24
Peak memory	207144 kb
Host	smart-69133a69-1e20-43ff-b16d-9e2d79253058
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=722297627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.722297627
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1345059571
Short name	T776
Test name
Test status
Simulation time	571795518 ps
CPU time	187.55 seconds
Started	Apr 28 12:47:41 PM PDT 24
Finished	Apr 28 12:50:49 PM PDT 24
Peak memory	208820 kb
Host	smart-f882ebb5-f331-48b5-b797-5e1573b3e352
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1345059571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1345059571
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1467710964
Short name	T414
Test name
Test status
Simulation time	424390866 ps
CPU time	98.78 seconds
Started	Apr 28 12:47:46 PM PDT 24
Finished	Apr 28 12:49:25 PM PDT 24
Peak memory	209736 kb
Host	smart-ba2bd11a-0092-4e94-b215-aa5e209708db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1467710964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1467710964
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.291684796
Short name	T89
Test name
Test status
Simulation time	1709079770 ps
CPU time	19.04 seconds
Started	Apr 28 12:47:41 PM PDT 24
Finished	Apr 28 12:48:00 PM PDT 24
Peak memory	204768 kb
Host	smart-b3d8221d-cb22-4cd1-97a1-7fda30ada652
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291684796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.291684796
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.802893816
Short name	T180
Test name
Test status
Simulation time	6000893448 ps
CPU time	54.89 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:48:39 PM PDT 24
Peak memory	205760 kb
Host	smart-0fbf63e0-28dd-488b-93b3-049e0a669030
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=802893816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.802893816
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1334822471
Short name	T212
Test name
Test status
Simulation time	2755287175 ps
CPU time	25.97 seconds
Started	Apr 28 12:47:46 PM PDT 24
Finished	Apr 28 12:48:13 PM PDT 24
Peak memory	203644 kb
Host	smart-ef1e29b6-f7c4-43a6-ac2a-ca2878608d18
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1334822471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1334822471
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2388383008
Short name	T876
Test name
Test status
Simulation time	951822175 ps
CPU time	14.32 seconds
Started	Apr 28 12:47:48 PM PDT 24
Finished	Apr 28 12:48:03 PM PDT 24
Peak memory	203468 kb
Host	smart-4003e534-182e-4f58-a39e-5eea318c7b8e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388383008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2388383008
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.2175427127
Short name	T467
Test name
Test status
Simulation time	1684033838 ps
CPU time	18.35 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:48:03 PM PDT 24
Peak memory	203492 kb
Host	smart-fbae5333-6b6d-4bcd-994f-3c31faac48b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2175427127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2175427127
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.270837813
Short name	T13
Test name
Test status
Simulation time	95894969 ps
CPU time	13.28 seconds
Started	Apr 28 12:47:45 PM PDT 24
Finished	Apr 28 12:47:59 PM PDT 24
Peak memory	204480 kb
Host	smart-2776c0f1-e2c7-4193-b497-6c5f6522a637
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=270837813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.270837813
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.4061083564
Short name	T179
Test name
Test status
Simulation time	152556018280 ps
CPU time	233.25 seconds
Started	Apr 28 12:47:42 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	204748 kb
Host	smart-0395ed5c-f96c-4439-a7ee-9ac837ea4ec0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061083564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4061083564
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2278146857
Short name	T535
Test name
Test status
Simulation time	5403359194 ps
CPU time	53.14 seconds
Started	Apr 28 12:47:41 PM PDT 24
Finished	Apr 28 12:48:35 PM PDT 24
Peak memory	205032 kb
Host	smart-f8a28f63-6384-414f-98aa-8238fe7f712d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2278146857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2278146857
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.628516018
Short name	T850
Test name
Test status
Simulation time	33464019 ps
CPU time	4.3 seconds
Started	Apr 28 12:47:38 PM PDT 24
Finished	Apr 28 12:47:43 PM PDT 24
Peak memory	203996 kb
Host	smart-3b14611e-9018-431b-9633-633eead0dfc5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628516018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.628516018
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.1562751960
Short name	T851
Test name
Test status
Simulation time	1333092794 ps
CPU time	26.96 seconds
Started	Apr 28 12:47:48 PM PDT 24
Finished	Apr 28 12:48:15 PM PDT 24
Peak memory	203412 kb
Host	smart-ca60c42c-7bbc-462b-9875-3f0af4d86dcb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1562751960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1562751960
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.512986051
Short name	T708
Test name
Test status
Simulation time	35073854 ps
CPU time	1.91 seconds
Started	Apr 28 12:47:45 PM PDT 24
Finished	Apr 28 12:47:48 PM PDT 24
Peak memory	203332 kb
Host	smart-644f7c4f-8c63-4fff-9ce7-661fe8088dd8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=512986051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.512986051
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2850925105
Short name	T396
Test name
Test status
Simulation time	9200428735 ps
CPU time	31.32 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:48:15 PM PDT 24
Peak memory	203448 kb
Host	smart-4a135813-d5c7-4a07-8053-4319d30e4562
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850925105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2850925105
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3941989800
Short name	T898
Test name
Test status
Simulation time	5898910837 ps
CPU time	24.18 seconds
Started	Apr 28 12:47:38 PM PDT 24
Finished	Apr 28 12:48:03 PM PDT 24
Peak memory	203524 kb
Host	smart-5e5eec1c-1b51-478a-bba2-6bf53d8bc3a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3941989800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3941989800
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1618733844
Short name	T525
Test name
Test status
Simulation time	66317815 ps
CPU time	1.95 seconds
Started	Apr 28 12:47:39 PM PDT 24
Finished	Apr 28 12:47:42 PM PDT 24
Peak memory	203468 kb
Host	smart-370cbf05-84e5-467c-a294-a367e8a5daf8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618733844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1618733844
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.3345262022
Short name	T770
Test name
Test status
Simulation time	680323206 ps
CPU time	67.21 seconds
Started	Apr 28 12:47:48 PM PDT 24
Finished	Apr 28 12:48:56 PM PDT 24
Peak memory	207184 kb
Host	smart-619ef08f-0c24-4241-a2b3-bb1d86ab9ce8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345262022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3345262022
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1437954817
Short name	T669
Test name
Test status
Simulation time	3025819529 ps
CPU time	53.21 seconds
Started	Apr 28 12:47:44 PM PDT 24
Finished	Apr 28 12:48:38 PM PDT 24
Peak memory	205144 kb
Host	smart-33fdab83-8360-4e1d-b999-c16f60410160
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1437954817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1437954817
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3566082694
Short name	T338
Test name
Test status
Simulation time	7397565044 ps
CPU time	272.02 seconds
Started	Apr 28 12:47:42 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	209424 kb
Host	smart-8fa1bad7-b931-4efb-91ba-7f3b959aee3a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3566082694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3566082694
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2459564325
Short name	T236
Test name
Test status
Simulation time	199323201 ps
CPU time	53.86 seconds
Started	Apr 28 12:47:45 PM PDT 24
Finished	Apr 28 12:48:40 PM PDT 24
Peak memory	207432 kb
Host	smart-34d96cf9-1102-4223-991c-6a4f680402b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2459564325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2459564325
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3877603861
Short name	T398
Test name
Test status
Simulation time	968085035 ps
CPU time	21.92 seconds
Started	Apr 28 12:47:47 PM PDT 24
Finished	Apr 28 12:48:10 PM PDT 24
Peak memory	211628 kb
Host	smart-1ca75458-de29-43e3-b011-9cd691873d18
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3877603861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3877603861
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.906140246
Short name	T176
Test name
Test status
Simulation time	2761664712 ps
CPU time	59.46 seconds
Started	Apr 28 12:47:44 PM PDT 24
Finished	Apr 28 12:48:44 PM PDT 24
Peak memory	206412 kb
Host	smart-afdb3902-a018-43c9-a08b-2f67fb86c9dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=906140246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.906140246
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3338966551
Short name	T107
Test name
Test status
Simulation time	245379093296 ps
CPU time	676.6 seconds
Started	Apr 28 12:47:47 PM PDT 24
Finished	Apr 28 12:59:04 PM PDT 24
Peak memory	206172 kb
Host	smart-0752150c-ecf3-4cfa-a862-10151a971027
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3338966551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.3338966551
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.138076158
Short name	T801
Test name
Test status
Simulation time	156887054 ps
CPU time	18.11 seconds
Started	Apr 28 12:47:48 PM PDT 24
Finished	Apr 28 12:48:06 PM PDT 24
Peak memory	203952 kb
Host	smart-853f4599-5025-42f8-a03a-6612cee2ead5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=138076158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.138076158
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.800034253
Short name	T446
Test name
Test status
Simulation time	572250734 ps
CPU time	13.71 seconds
Started	Apr 28 12:47:45 PM PDT 24
Finished	Apr 28 12:47:59 PM PDT 24
Peak memory	203496 kb
Host	smart-8c8278bd-424d-4f7a-ba28-831f53219077
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=800034253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.800034253
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.2441619633
Short name	T709
Test name
Test status
Simulation time	1233950814 ps
CPU time	37.79 seconds
Started	Apr 28 12:47:46 PM PDT 24
Finished	Apr 28 12:48:24 PM PDT 24
Peak memory	211528 kb
Host	smart-193f2f76-9bc1-4cad-9c32-ef446b06cc2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2441619633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2441619633
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.967521235
Short name	T177
Test name
Test status
Simulation time	41086843403 ps
CPU time	77.48 seconds
Started	Apr 28 12:47:46 PM PDT 24
Finished	Apr 28 12:49:04 PM PDT 24
Peak memory	204884 kb
Host	smart-db11369a-3b5e-43f8-a122-b65b98b4a3a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=967521235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.967521235
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1688453041
Short name	T57
Test name
Test status
Simulation time	18651232979 ps
CPU time	146.24 seconds
Started	Apr 28 12:47:44 PM PDT 24
Finished	Apr 28 12:50:11 PM PDT 24
Peak memory	204868 kb
Host	smart-e8b18875-5334-4eca-8c88-daed35158cc4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1688453041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1688453041
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1392160070
Short name	T405
Test name
Test status
Simulation time	34883651 ps
CPU time	3.76 seconds
Started	Apr 28 12:47:46 PM PDT 24
Finished	Apr 28 12:47:51 PM PDT 24
Peak memory	204264 kb
Host	smart-2ab2b6ef-e3d4-4392-828c-2ad96a9a3eb5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392160070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1392160070
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.3873165385
Short name	T462
Test name
Test status
Simulation time	2060878377 ps
CPU time	21.44 seconds
Started	Apr 28 12:47:43 PM PDT 24
Finished	Apr 28 12:48:05 PM PDT 24
Peak memory	204120 kb
Host	smart-04482935-22e6-40d4-b272-958ad518db07
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3873165385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3873165385
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.461359389
Short name	T306
Test name
Test status
Simulation time	156114156 ps
CPU time	3.78 seconds
Started	Apr 28 12:47:44 PM PDT 24
Finished	Apr 28 12:47:48 PM PDT 24
Peak memory	203464 kb
Host	smart-4d6a98d7-d32c-4695-b379-22f118042df8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=461359389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.461359389
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3290416000
Short name	T749
Test name
Test status
Simulation time	40420547818 ps
CPU time	45.46 seconds
Started	Apr 28 12:47:42 PM PDT 24
Finished	Apr 28 12:48:28 PM PDT 24
Peak memory	203484 kb
Host	smart-0af10794-9821-4f1e-8a77-22b7e2bd8d5a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290416000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3290416000
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.290182190
Short name	T20
Test name
Test status
Simulation time	16110814577 ps
CPU time	39.36 seconds
Started	Apr 28 12:47:45 PM PDT 24
Finished	Apr 28 12:48:25 PM PDT 24
Peak memory	203552 kb
Host	smart-940e7a2d-61a7-4f93-b5c7-812525c4c096
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=290182190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.290182190
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3693325385
Short name	T471
Test name
Test status
Simulation time	36359758 ps
CPU time	1.9 seconds
Started	Apr 28 12:47:46 PM PDT 24
Finished	Apr 28 12:47:49 PM PDT 24
Peak memory	203392 kb
Host	smart-cf78b43e-bb22-460a-8257-8a2e157801d9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693325385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3693325385
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.4011328958
Short name	T679
Test name
Test status
Simulation time	935129987 ps
CPU time	95.62 seconds
Started	Apr 28 12:47:51 PM PDT 24
Finished	Apr 28 12:49:27 PM PDT 24
Peak memory	205972 kb
Host	smart-200792ca-ece0-4fd7-b9ea-456d551eed46
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4011328958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4011328958
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.909975628
Short name	T451
Test name
Test status
Simulation time	4575100880 ps
CPU time	50.25 seconds
Started	Apr 28 12:47:50 PM PDT 24
Finished	Apr 28 12:48:40 PM PDT 24
Peak memory	205176 kb
Host	smart-49194467-9bc5-4784-b768-660e74ed8c1f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=909975628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.909975628
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3388685418
Short name	T192
Test name
Test status
Simulation time	4124911173 ps
CPU time	345.59 seconds
Started	Apr 28 12:47:51 PM PDT 24
Finished	Apr 28 12:53:37 PM PDT 24
Peak memory	211756 kb
Host	smart-e1f030e5-6997-4bbb-954d-933dfb0155a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3388685418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.3388685418
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2371676423
Short name	T229
Test name
Test status
Simulation time	782294903 ps
CPU time	142.36 seconds
Started	Apr 28 12:47:51 PM PDT 24
Finished	Apr 28 12:50:14 PM PDT 24
Peak memory	210712 kb
Host	smart-18e9d8fb-dff9-441e-8e5f-199f08e37c97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2371676423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.2371676423
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3365470732
Short name	T394
Test name
Test status
Simulation time	376472965 ps
CPU time	13.31 seconds
Started	Apr 28 12:47:47 PM PDT 24
Finished	Apr 28 12:48:01 PM PDT 24
Peak memory	204964 kb
Host	smart-3b388b77-a918-4fc3-adec-380c564e0469
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3365470732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3365470732
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3022606540
Short name	T465
Test name
Test status
Simulation time	3185541372 ps
CPU time	54.74 seconds
Started	Apr 28 12:46:54 PM PDT 24
Finished	Apr 28 12:47:50 PM PDT 24
Peak memory	206340 kb
Host	smart-d0901768-7da3-426a-a493-4398ac91722d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3022606540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3022606540
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3988113843
Short name	T145
Test name
Test status
Simulation time	115361541521 ps
CPU time	438.74 seconds
Started	Apr 28 12:46:44 PM PDT 24
Finished	Apr 28 12:54:03 PM PDT 24
Peak memory	206800 kb
Host	smart-9e069f3e-a3a4-4327-a0ac-e12b485b7242
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3988113843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3988113843
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.200211568
Short name	T29
Test name
Test status
Simulation time	987124248 ps
CPU time	27.74 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:34 PM PDT 24
Peak memory	203848 kb
Host	smart-0276c7cf-4e5f-46da-9784-255110df7d6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=200211568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.200211568
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.2302007794
Short name	T824
Test name
Test status
Simulation time	283123696 ps
CPU time	16.6 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:47:05 PM PDT 24
Peak memory	203388 kb
Host	smart-b04dcea7-f7d0-46b6-b1f4-068a79391dc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2302007794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2302007794
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.464154885
Short name	T343
Test name
Test status
Simulation time	898981268 ps
CPU time	28.65 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:47:17 PM PDT 24
Peak memory	204364 kb
Host	smart-9eacc284-6087-40ed-82a7-d1317fad6a9f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464154885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.464154885
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3141194961
Short name	T746
Test name
Test status
Simulation time	64628951902 ps
CPU time	225.81 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:50:48 PM PDT 24
Peak memory	204608 kb
Host	smart-afd86d1d-7506-4513-a509-e70ba8c68828
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141194961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3141194961
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.240150257
Short name	T538
Test name
Test status
Simulation time	4826016473 ps
CPU time	33.42 seconds
Started	Apr 28 12:46:54 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	204496 kb
Host	smart-7da95e2c-23be-4681-a007-f11db7f92447
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=240150257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.240150257
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2203829810
Short name	T633
Test name
Test status
Simulation time	720595872 ps
CPU time	15.14 seconds
Started	Apr 28 12:46:44 PM PDT 24
Finished	Apr 28 12:47:00 PM PDT 24
Peak memory	204748 kb
Host	smart-0fabf77f-31e9-4fb2-9c04-97cde0211393
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203829810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2203829810
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.2956415016
Short name	T825
Test name
Test status
Simulation time	143150763 ps
CPU time	10.6 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:47:00 PM PDT 24
Peak memory	204016 kb
Host	smart-058696ec-2274-44ca-aaeb-1ba0202c9e80
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2956415016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2956415016
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.3554831146
Short name	T416
Test name
Test status
Simulation time	29386099 ps
CPU time	2.24 seconds
Started	Apr 28 12:46:41 PM PDT 24
Finished	Apr 28 12:46:45 PM PDT 24
Peak memory	203500 kb
Host	smart-c0664109-59c2-4a4a-b7fb-8cc3e99b4e18
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554831146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3554831146
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4292537293
Short name	T601
Test name
Test status
Simulation time	7032648808 ps
CPU time	25.64 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	203528 kb
Host	smart-721b1eec-ef10-4d83-88a4-4d4012f34437
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292537293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4292537293
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1132147713
Short name	T829
Test name
Test status
Simulation time	7481215309 ps
CPU time	36.82 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:47:25 PM PDT 24
Peak memory	203384 kb
Host	smart-a3afcbad-5fb6-4d79-8b3f-a3da3e91c438
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1132147713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1132147713
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2822483255
Short name	T274
Test name
Test status
Simulation time	123549588 ps
CPU time	2 seconds
Started	Apr 28 12:46:54 PM PDT 24
Finished	Apr 28 12:46:57 PM PDT 24
Peak memory	203472 kb
Host	smart-0e2a6e77-6823-4a26-be50-1879fe979d5a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822483255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2822483255
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.194050469
Short name	T609
Test name
Test status
Simulation time	7902713138 ps
CPU time	50.16 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:55 PM PDT 24
Peak memory	206296 kb
Host	smart-1feadff3-1226-4fce-a84c-94324861c068
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194050469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.194050469
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1783727007
Short name	T481
Test name
Test status
Simulation time	16821535196 ps
CPU time	252.45 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:51:03 PM PDT 24
Peak memory	207132 kb
Host	smart-78a78674-8eb3-433b-919b-158d1b23f33f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1783727007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1783727007
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2912645741
Short name	T164
Test name
Test status
Simulation time	4975502450 ps
CPU time	127.63 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	208544 kb
Host	smart-759f3196-628c-49ab-9ffe-bfa3ddb22a26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2912645741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.2912645741
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.381046289
Short name	T340
Test name
Test status
Simulation time	103983227 ps
CPU time	21.31 seconds
Started	Apr 28 12:46:47 PM PDT 24
Finished	Apr 28 12:47:09 PM PDT 24
Peak memory	205728 kb
Host	smart-73aa25ec-6f40-4407-b531-8bebeaec7525
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=381046289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.381046289
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.881086337
Short name	T135
Test name
Test status
Simulation time	2590779299 ps
CPU time	29.53 seconds
Started	Apr 28 12:46:47 PM PDT 24
Finished	Apr 28 12:47:17 PM PDT 24
Peak memory	204908 kb
Host	smart-38c6b93b-3942-4cd6-a85e-bcb773575846
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=881086337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.881086337
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3800421299
Short name	T15
Test name
Test status
Simulation time	1220177878 ps
CPU time	48.75 seconds
Started	Apr 28 12:47:49 PM PDT 24
Finished	Apr 28 12:48:38 PM PDT 24
Peak memory	205216 kb
Host	smart-2df975e8-109c-4eb6-af22-583bc290e50e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3800421299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3800421299
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.4073667638
Short name	T863
Test name
Test status
Simulation time	45596362579 ps
CPU time	379.3 seconds
Started	Apr 28 12:47:49 PM PDT 24
Finished	Apr 28 12:54:08 PM PDT 24
Peak memory	206088 kb
Host	smart-cb37f116-38bb-4b28-aefb-539898a94f80
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4073667638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.4073667638
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.486119536
Short name	T244
Test name
Test status
Simulation time	993967640 ps
CPU time	22.87 seconds
Started	Apr 28 12:47:56 PM PDT 24
Finished	Apr 28 12:48:19 PM PDT 24
Peak memory	203740 kb
Host	smart-5115e948-9965-4ef9-a813-3dcd183100db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=486119536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.486119536
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.524537336
Short name	T263
Test name
Test status
Simulation time	2015945318 ps
CPU time	30.44 seconds
Started	Apr 28 12:47:49 PM PDT 24
Finished	Apr 28 12:48:20 PM PDT 24
Peak memory	203364 kb
Host	smart-34ec192d-74cc-46e8-b255-6ee1e69be417
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=524537336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.524537336
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.3455238319
Short name	T5
Test name
Test status
Simulation time	56290776 ps
CPU time	8.37 seconds
Started	Apr 28 12:47:50 PM PDT 24
Finished	Apr 28 12:47:59 PM PDT 24
Peak memory	204500 kb
Host	smart-3687f789-2a20-4de5-8aa0-bf07b19802af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3455238319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3455238319
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3986451058
Short name	T88
Test name
Test status
Simulation time	27759602295 ps
CPU time	162.33 seconds
Started	Apr 28 12:47:48 PM PDT 24
Finished	Apr 28 12:50:31 PM PDT 24
Peak memory	205092 kb
Host	smart-788dac17-44a9-48cc-9f5b-3882dbfc431f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986451058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3986451058
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3435906637
Short name	T688
Test name
Test status
Simulation time	1429122297 ps
CPU time	9.46 seconds
Started	Apr 28 12:47:50 PM PDT 24
Finished	Apr 28 12:48:00 PM PDT 24
Peak memory	203468 kb
Host	smart-da26e53d-9179-4a5c-9351-34c3afa2a96f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3435906637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3435906637
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2567136396
Short name	T795
Test name
Test status
Simulation time	918935112 ps
CPU time	26.44 seconds
Started	Apr 28 12:47:50 PM PDT 24
Finished	Apr 28 12:48:17 PM PDT 24
Peak memory	211544 kb
Host	smart-927dbc52-2799-49e9-87a5-c4f4e69f5a88
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567136396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2567136396
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.154185532
Short name	T789
Test name
Test status
Simulation time	238771946 ps
CPU time	16.47 seconds
Started	Apr 28 12:47:52 PM PDT 24
Finished	Apr 28 12:48:09 PM PDT 24
Peak memory	203980 kb
Host	smart-b180c137-5fb3-4ac7-8e86-2c1a38f81d53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=154185532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.154185532
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.3757705236
Short name	T840
Test name
Test status
Simulation time	191956160 ps
CPU time	3.9 seconds
Started	Apr 28 12:47:50 PM PDT 24
Finished	Apr 28 12:47:54 PM PDT 24
Peak memory	203364 kb
Host	smart-5d485a5c-9c88-464e-a60d-995390f616db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3757705236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3757705236
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2976892515
Short name	T581
Test name
Test status
Simulation time	13002482100 ps
CPU time	27.46 seconds
Started	Apr 28 12:47:50 PM PDT 24
Finished	Apr 28 12:48:18 PM PDT 24
Peak memory	203420 kb
Host	smart-f7c810c9-9d16-49be-b52c-20f246ae354f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976892515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2976892515
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3690755200
Short name	T327
Test name
Test status
Simulation time	7822901201 ps
CPU time	31.27 seconds
Started	Apr 28 12:47:49 PM PDT 24
Finished	Apr 28 12:48:21 PM PDT 24
Peak memory	203416 kb
Host	smart-38212f30-06e1-4eac-8d98-4f2139a8e88a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3690755200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3690755200
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3425719271
Short name	T102
Test name
Test status
Simulation time	122866507 ps
CPU time	2.26 seconds
Started	Apr 28 12:47:51 PM PDT 24
Finished	Apr 28 12:47:54 PM PDT 24
Peak memory	203504 kb
Host	smart-585a4c42-70a6-4f97-bd5e-2495fc69a60f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425719271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3425719271
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.3706387134
Short name	T388
Test name
Test status
Simulation time	3747866913 ps
CPU time	106.65 seconds
Started	Apr 28 12:47:57 PM PDT 24
Finished	Apr 28 12:49:44 PM PDT 24
Peak memory	207300 kb
Host	smart-9e721a63-3143-4e58-b4f0-b2968b4cef57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706387134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3706387134
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.927696374
Short name	T278
Test name
Test status
Simulation time	1149111669 ps
CPU time	35.64 seconds
Started	Apr 28 12:47:55 PM PDT 24
Finished	Apr 28 12:48:31 PM PDT 24
Peak memory	203508 kb
Host	smart-87cd0f54-c737-457e-ae5a-333d696cdff8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=927696374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.927696374
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3222537167
Short name	T167
Test name
Test status
Simulation time	1682569135 ps
CPU time	218 seconds
Started	Apr 28 12:47:53 PM PDT 24
Finished	Apr 28 12:51:32 PM PDT 24
Peak memory	211672 kb
Host	smart-f48299f3-c64f-4c7f-a610-7cce1757ae98
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3222537167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.3222537167
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3773194957
Short name	T570
Test name
Test status
Simulation time	129944426 ps
CPU time	9.89 seconds
Started	Apr 28 12:47:47 PM PDT 24
Finished	Apr 28 12:47:58 PM PDT 24
Peak memory	204896 kb
Host	smart-b6f58911-bd80-4f29-a00c-680e11042cbf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3773194957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3773194957
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.760988052
Short name	T133
Test name
Test status
Simulation time	1355497240 ps
CPU time	33.42 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:48:28 PM PDT 24
Peak memory	206056 kb
Host	smart-a33b7487-dafd-4618-83d3-79c9d6c0e2e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=760988052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.760988052
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3468225723
Short name	T434
Test name
Test status
Simulation time	54265992922 ps
CPU time	439.87 seconds
Started	Apr 28 12:47:53 PM PDT 24
Finished	Apr 28 12:55:14 PM PDT 24
Peak memory	211560 kb
Host	smart-ec3c1cc1-7d1b-4d92-bd11-78b506495075
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3468225723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3468225723
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.652004288
Short name	T832
Test name
Test status
Simulation time	665115294 ps
CPU time	23.59 seconds
Started	Apr 28 12:47:55 PM PDT 24
Finished	Apr 28 12:48:19 PM PDT 24
Peak memory	203952 kb
Host	smart-8159e882-b99b-4b81-ba05-9997a484e841
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652004288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.652004288
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.2622459826
Short name	T792
Test name
Test status
Simulation time	204397815 ps
CPU time	14.41 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:48:10 PM PDT 24
Peak memory	203484 kb
Host	smart-4a789885-d658-4599-ba69-07fe27660785
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2622459826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2622459826
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.1086472174
Short name	T85
Test name
Test status
Simulation time	573727293 ps
CPU time	11.29 seconds
Started	Apr 28 12:47:53 PM PDT 24
Finished	Apr 28 12:48:06 PM PDT 24
Peak memory	204460 kb
Host	smart-25a7cb22-1d60-4717-b46f-0a2f1ce70bfd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1086472174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1086472174
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3476441336
Short name	T173
Test name
Test status
Simulation time	49273832686 ps
CPU time	252.28 seconds
Started	Apr 28 12:47:57 PM PDT 24
Finished	Apr 28 12:52:09 PM PDT 24
Peak memory	205128 kb
Host	smart-e0fc837f-996f-4ce3-83dd-8ab938fc6240
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476441336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3476441336
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3167145135
Short name	T23
Test name
Test status
Simulation time	47920075237 ps
CPU time	182.47 seconds
Started	Apr 28 12:47:57 PM PDT 24
Finished	Apr 28 12:51:00 PM PDT 24
Peak memory	204688 kb
Host	smart-981d4d8b-598c-43ca-80e9-ae3580f6a1c2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3167145135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3167145135
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3376114051
Short name	T441
Test name
Test status
Simulation time	88154241 ps
CPU time	12.42 seconds
Started	Apr 28 12:47:57 PM PDT 24
Finished	Apr 28 12:48:10 PM PDT 24
Peak memory	204560 kb
Host	smart-759af3c7-c6f5-4672-a036-b9a096a44406
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376114051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3376114051
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.2187126987
Short name	T854
Test name
Test status
Simulation time	1204291357 ps
CPU time	13.71 seconds
Started	Apr 28 12:47:55 PM PDT 24
Finished	Apr 28 12:48:10 PM PDT 24
Peak memory	203464 kb
Host	smart-c77c1fa3-58de-4f49-bcbf-afcd79635639
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187126987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2187126987
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.1105048766
Short name	T627
Test name
Test status
Simulation time	50166239 ps
CPU time	2.35 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:47:58 PM PDT 24
Peak memory	203352 kb
Host	smart-b8f5145b-92c8-4295-873d-f2afbdd4d11f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1105048766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1105048766
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.558006562
Short name	T879
Test name
Test status
Simulation time	34401816634 ps
CPU time	52.46 seconds
Started	Apr 28 12:47:55 PM PDT 24
Finished	Apr 28 12:48:48 PM PDT 24
Peak memory	203392 kb
Host	smart-9245d50c-39dd-485e-b418-c02c7dd4f2d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=558006562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.558006562
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2741344354
Short name	T208
Test name
Test status
Simulation time	2978821375 ps
CPU time	24.39 seconds
Started	Apr 28 12:47:53 PM PDT 24
Finished	Apr 28 12:48:19 PM PDT 24
Peak memory	203448 kb
Host	smart-86f180d1-b01d-465b-bfe7-aaaa3e5d06c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2741344354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2741344354
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3099333640
Short name	T779
Test name
Test status
Simulation time	168360046 ps
CPU time	2.26 seconds
Started	Apr 28 12:47:52 PM PDT 24
Finished	Apr 28 12:47:55 PM PDT 24
Peak memory	203492 kb
Host	smart-75771fac-4cc6-468a-b23f-b6b45c27643b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099333640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3099333640
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.3064188821
Short name	T134
Test name
Test status
Simulation time	7138640371 ps
CPU time	165.58 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:50:40 PM PDT 24
Peak memory	211708 kb
Host	smart-88b86da2-221e-4544-ad2f-e0480946c9f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3064188821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3064188821
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3705730488
Short name	T841
Test name
Test status
Simulation time	984425399 ps
CPU time	69.86 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:49:05 PM PDT 24
Peak memory	205184 kb
Host	smart-1ddcf8b0-e137-4529-b115-d212c81d9dbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3705730488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3705730488
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.102712778
Short name	T460
Test name
Test status
Simulation time	12863275847 ps
CPU time	369.45 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	219808 kb
Host	smart-c9c89594-225b-46de-b975-d90ba802f367
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=102712778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand _reset.102712778
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.22958519
Short name	T234
Test name
Test status
Simulation time	4588638338 ps
CPU time	150.27 seconds
Started	Apr 28 12:47:55 PM PDT 24
Finished	Apr 28 12:50:26 PM PDT 24
Peak memory	211640 kb
Host	smart-f131bb93-3778-4ba1-9373-275a5f84e85f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=22958519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rese t_error.22958519
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3604187130
Short name	T150
Test name
Test status
Simulation time	980788558 ps
CPU time	28.49 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:48:24 PM PDT 24
Peak memory	205248 kb
Host	smart-0f023b5c-e88e-4999-8c24-830f7f08dcd6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3604187130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3604187130
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1899172655
Short name	T812
Test name
Test status
Simulation time	7513323197 ps
CPU time	49.6 seconds
Started	Apr 28 12:47:58 PM PDT 24
Finished	Apr 28 12:48:48 PM PDT 24
Peak memory	211612 kb
Host	smart-ac700870-9749-4d81-9978-3da18fac7a9d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1899172655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1899172655
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1922886787
Short name	T572
Test name
Test status
Simulation time	13560754110 ps
CPU time	84.15 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:49:25 PM PDT 24
Peak memory	211620 kb
Host	smart-a6d5b2ed-09d4-4f24-b3f3-fa48240b16f2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1922886787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.1922886787
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2906490457
Short name	T623
Test name
Test status
Simulation time	703099622 ps
CPU time	7.75 seconds
Started	Apr 28 12:48:01 PM PDT 24
Finished	Apr 28 12:48:10 PM PDT 24
Peak memory	203368 kb
Host	smart-9eceaf30-6236-4641-9085-64d18cc17542
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2906490457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2906490457
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.2986941162
Short name	T730
Test name
Test status
Simulation time	204685706 ps
CPU time	19.7 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:48:21 PM PDT 24
Peak memory	203484 kb
Host	smart-89334cf3-eee4-4ce8-8f33-2122bf881c32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2986941162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2986941162
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.3780338366
Short name	T813
Test name
Test status
Simulation time	668266543 ps
CPU time	33.1 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:48:34 PM PDT 24
Peak memory	211660 kb
Host	smart-1b788410-43f4-468a-8e17-12edcf0f5e38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3780338366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3780338366
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.919218858
Short name	T87
Test name
Test status
Simulation time	35448108821 ps
CPU time	117.68 seconds
Started	Apr 28 12:47:58 PM PDT 24
Finished	Apr 28 12:49:56 PM PDT 24
Peak memory	205000 kb
Host	smart-68547208-3c71-4f64-9b4f-3d8bd4a79ffd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=919218858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.919218858
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1326437019
Short name	T118
Test name
Test status
Simulation time	17029401727 ps
CPU time	150.84 seconds
Started	Apr 28 12:48:01 PM PDT 24
Finished	Apr 28 12:50:33 PM PDT 24
Peak memory	204768 kb
Host	smart-f7377e22-70ee-434d-a8ab-85521f3b3bc1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1326437019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1326437019
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.979340892
Short name	T568
Test name
Test status
Simulation time	297544705 ps
CPU time	22.23 seconds
Started	Apr 28 12:48:01 PM PDT 24
Finished	Apr 28 12:48:24 PM PDT 24
Peak memory	204924 kb
Host	smart-ebb9550a-0818-4158-82ca-f85c433bcd7c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979340892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.979340892
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.1021926868
Short name	T123
Test name
Test status
Simulation time	78038003 ps
CPU time	2.05 seconds
Started	Apr 28 12:47:59 PM PDT 24
Finished	Apr 28 12:48:02 PM PDT 24
Peak memory	203524 kb
Host	smart-79b50fd9-8139-41dd-9151-7bb1d87ea473
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1021926868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1021926868
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.2203960042
Short name	T562
Test name
Test status
Simulation time	465252776 ps
CPU time	3.24 seconds
Started	Apr 28 12:47:55 PM PDT 24
Finished	Apr 28 12:47:59 PM PDT 24
Peak memory	203504 kb
Host	smart-b3879c7a-4233-458a-8024-f0f64dac7989
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2203960042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2203960042
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.186137999
Short name	T42
Test name
Test status
Simulation time	12085267696 ps
CPU time	23.72 seconds
Started	Apr 28 12:48:01 PM PDT 24
Finished	Apr 28 12:48:25 PM PDT 24
Peak memory	203532 kb
Host	smart-9e3d1505-6dfb-4d26-8877-9689f08e7ea7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=186137999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.186137999
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1350235878
Short name	T381
Test name
Test status
Simulation time	8989569753 ps
CPU time	30.86 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:48:32 PM PDT 24
Peak memory	203504 kb
Host	smart-09a955f4-3ca6-4bcb-8dd6-3488f678a84c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1350235878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1350235878
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.324895952
Short name	T318
Test name
Test status
Simulation time	79562506 ps
CPU time	2.41 seconds
Started	Apr 28 12:47:54 PM PDT 24
Finished	Apr 28 12:47:58 PM PDT 24
Peak memory	203388 kb
Host	smart-4c241565-2655-407e-b6fe-eb3c6a1cb39a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324895952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.324895952
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.996622941
Short name	T146
Test name
Test status
Simulation time	7810359024 ps
CPU time	234.74 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:51:56 PM PDT 24
Peak memory	207464 kb
Host	smart-e09f5a6d-1b1e-4948-802d-3271bc011538
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=996622941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.996622941
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3906008404
Short name	T555
Test name
Test status
Simulation time	2451573021 ps
CPU time	201.71 seconds
Started	Apr 28 12:47:59 PM PDT 24
Finished	Apr 28 12:51:21 PM PDT 24
Peak memory	211708 kb
Host	smart-4ff121ae-4423-433d-b908-527076b60943
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906008404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3906008404
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3126499582
Short name	T715
Test name
Test status
Simulation time	2163900425 ps
CPU time	290.42 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:52:51 PM PDT 24
Peak memory	211752 kb
Host	smart-efa06874-fd63-4c4f-b34e-0bc56e4a998c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3126499582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3126499582
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.255645563
Short name	T122
Test name
Test status
Simulation time	677880049 ps
CPU time	5.55 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:48:06 PM PDT 24
Peak memory	204744 kb
Host	smart-aee65509-f353-419c-a30b-8cb285a017b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=255645563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.255645563
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3635149164
Short name	T454
Test name
Test status
Simulation time	310255910 ps
CPU time	16.88 seconds
Started	Apr 28 12:48:04 PM PDT 24
Finished	Apr 28 12:48:21 PM PDT 24
Peak memory	204680 kb
Host	smart-ce1dacee-7b1e-4e06-8761-e887b7890975
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635149164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3635149164
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.202411386
Short name	T652
Test name
Test status
Simulation time	290962304 ps
CPU time	10.41 seconds
Started	Apr 28 12:48:03 PM PDT 24
Finished	Apr 28 12:48:14 PM PDT 24
Peak memory	203388 kb
Host	smart-8f562fb9-4f46-4f4e-9385-be788ee4739d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=202411386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.202411386
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.926122097
Short name	T7
Test name
Test status
Simulation time	2032729928 ps
CPU time	22.54 seconds
Started	Apr 28 12:48:08 PM PDT 24
Finished	Apr 28 12:48:31 PM PDT 24
Peak memory	203396 kb
Host	smart-3d195705-76e1-4022-b77d-90685b5b9a6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=926122097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.926122097
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.1545087011
Short name	T639
Test name
Test status
Simulation time	2732617375 ps
CPU time	22.12 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:48:30 PM PDT 24
Peak memory	204636 kb
Host	smart-8c6e5db5-3379-4384-862f-860560c81ebd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1545087011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1545087011
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.696790961
Short name	T453
Test name
Test status
Simulation time	28945676760 ps
CPU time	195.97 seconds
Started	Apr 28 12:48:05 PM PDT 24
Finished	Apr 28 12:51:21 PM PDT 24
Peak memory	204784 kb
Host	smart-3bf7d707-0936-4cb6-a342-beded3d12f47
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=696790961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.696790961
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2033886931
Short name	T292
Test name
Test status
Simulation time	21813663586 ps
CPU time	169.01 seconds
Started	Apr 28 12:48:03 PM PDT 24
Finished	Apr 28 12:50:53 PM PDT 24
Peak memory	204876 kb
Host	smart-2c3414b6-657c-4e48-8caf-d7f7507607f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2033886931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2033886931
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2357401058
Short name	T630
Test name
Test status
Simulation time	50199702 ps
CPU time	7.49 seconds
Started	Apr 28 12:48:02 PM PDT 24
Finished	Apr 28 12:48:10 PM PDT 24
Peak memory	204540 kb
Host	smart-dbd8789e-8803-43da-aea8-53adbd481cbb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357401058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2357401058
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.152595429
Short name	T320
Test name
Test status
Simulation time	403021007 ps
CPU time	14.22 seconds
Started	Apr 28 12:48:05 PM PDT 24
Finished	Apr 28 12:48:20 PM PDT 24
Peak memory	211536 kb
Host	smart-ad8fe49e-65b3-4799-9889-2990462187a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=152595429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.152595429
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.1393530866
Short name	T593
Test name
Test status
Simulation time	504699637 ps
CPU time	3.95 seconds
Started	Apr 28 12:48:01 PM PDT 24
Finished	Apr 28 12:48:06 PM PDT 24
Peak memory	203332 kb
Host	smart-8a71b0a3-50c5-4260-94e0-f8219df5d67e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1393530866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1393530866
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1190369562
Short name	T316
Test name
Test status
Simulation time	7266447938 ps
CPU time	34.27 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:48:35 PM PDT 24
Peak memory	203452 kb
Host	smart-207b00f1-6cac-4af1-944d-2d9b22bed04b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190369562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1190369562
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.503953594
Short name	T43
Test name
Test status
Simulation time	2710156414 ps
CPU time	24.88 seconds
Started	Apr 28 12:48:02 PM PDT 24
Finished	Apr 28 12:48:28 PM PDT 24
Peak memory	203508 kb
Host	smart-12f5d455-fd60-429e-8a2a-ed897da61828
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=503953594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.503953594
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.960892587
Short name	T364
Test name
Test status
Simulation time	38433233 ps
CPU time	2.79 seconds
Started	Apr 28 12:48:00 PM PDT 24
Finished	Apr 28 12:48:04 PM PDT 24
Peak memory	203452 kb
Host	smart-03de1155-00b0-4082-92d5-56d781fbe726
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960892587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.960892587
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.3489821590
Short name	T526
Test name
Test status
Simulation time	2684100422 ps
CPU time	171.59 seconds
Started	Apr 28 12:48:05 PM PDT 24
Finished	Apr 28 12:50:57 PM PDT 24
Peak memory	210240 kb
Host	smart-507088d4-0286-492f-bb74-e298e73b5fb5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3489821590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3489821590
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3993854896
Short name	T528
Test name
Test status
Simulation time	2779620663 ps
CPU time	70.96 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:49:19 PM PDT 24
Peak memory	205408 kb
Host	smart-80f8cd51-e0d7-46cf-91d0-27a88c8bd1c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3993854896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3993854896
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.690662750
Short name	T371
Test name
Test status
Simulation time	284412278 ps
CPU time	71.55 seconds
Started	Apr 28 12:48:02 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	207800 kb
Host	smart-d6d05271-34c3-46b3-a55c-54cce0a0c9ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=690662750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.690662750
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.772912056
Short name	T235
Test name
Test status
Simulation time	3656537637 ps
CPU time	299.08 seconds
Started	Apr 28 12:48:04 PM PDT 24
Finished	Apr 28 12:53:04 PM PDT 24
Peak memory	220016 kb
Host	smart-4dfd308f-29c3-4179-9c3e-edab442a728a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=772912056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.772912056
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2627631506
Short name	T70
Test name
Test status
Simulation time	358808562 ps
CPU time	13.04 seconds
Started	Apr 28 12:48:03 PM PDT 24
Finished	Apr 28 12:48:17 PM PDT 24
Peak memory	204900 kb
Host	smart-b5b3f071-ab1e-4df9-95b6-303aebde8318
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2627631506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2627631506
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2435051649
Short name	T222
Test name
Test status
Simulation time	617822065 ps
CPU time	10.05 seconds
Started	Apr 28 12:48:06 PM PDT 24
Finished	Apr 28 12:48:17 PM PDT 24
Peak memory	204120 kb
Host	smart-7d83af4a-7440-4204-95ce-75bc53548d2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2435051649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2435051649
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.682256230
Short name	T92
Test name
Test status
Simulation time	69705224932 ps
CPU time	255.63 seconds
Started	Apr 28 12:48:02 PM PDT 24
Finished	Apr 28 12:52:18 PM PDT 24
Peak memory	205864 kb
Host	smart-0ee32de0-58a1-408a-97b5-e00f39802019
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=682256230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.682256230
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1911478503
Short name	T369
Test name
Test status
Simulation time	35633368 ps
CPU time	3.79 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:48:11 PM PDT 24
Peak memory	203588 kb
Host	smart-13c8b665-9a61-43c2-8000-3a36b96efaa7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1911478503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1911478503
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.1515689988
Short name	T769
Test name
Test status
Simulation time	150002507 ps
CPU time	3.61 seconds
Started	Apr 28 12:48:10 PM PDT 24
Finished	Apr 28 12:48:15 PM PDT 24
Peak memory	203392 kb
Host	smart-fdced83f-3952-428c-abbd-957d3685e4e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515689988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1515689988
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.3986660382
Short name	T529
Test name
Test status
Simulation time	216825217 ps
CPU time	5.39 seconds
Started	Apr 28 12:48:09 PM PDT 24
Finished	Apr 28 12:48:15 PM PDT 24
Peak memory	203408 kb
Host	smart-3d81f400-0038-4ece-98d0-ca9e376a9e1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3986660382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3986660382
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.367304880
Short name	T421
Test name
Test status
Simulation time	8797015121 ps
CPU time	48.42 seconds
Started	Apr 28 12:48:08 PM PDT 24
Finished	Apr 28 12:48:57 PM PDT 24
Peak memory	204620 kb
Host	smart-d23049e5-a2e8-43af-982d-be7e98a67360
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=367304880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.367304880
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1307621259
Short name	T260
Test name
Test status
Simulation time	12480544007 ps
CPU time	56 seconds
Started	Apr 28 12:48:03 PM PDT 24
Finished	Apr 28 12:48:59 PM PDT 24
Peak memory	211744 kb
Host	smart-fffbd74e-614f-4f71-abee-a6b0bd636646
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1307621259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1307621259
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1062294841
Short name	T760
Test name
Test status
Simulation time	896873885 ps
CPU time	29.23 seconds
Started	Apr 28 12:48:03 PM PDT 24
Finished	Apr 28 12:48:32 PM PDT 24
Peak memory	204956 kb
Host	smart-e43b3a19-62aa-4550-8f3c-78222a720501
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062294841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1062294841
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.3160005008
Short name	T786
Test name
Test status
Simulation time	340023625 ps
CPU time	19.63 seconds
Started	Apr 28 12:48:09 PM PDT 24
Finished	Apr 28 12:48:29 PM PDT 24
Peak memory	203408 kb
Host	smart-7e797d9f-81dc-4308-8350-eff9f0ced500
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3160005008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3160005008
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.2424448621
Short name	T540
Test name
Test status
Simulation time	154480582 ps
CPU time	3.32 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:48:11 PM PDT 24
Peak memory	203440 kb
Host	smart-caf1366d-a117-49ad-8d46-27428e927fb9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2424448621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2424448621
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3060968300
Short name	T295
Test name
Test status
Simulation time	12825113476 ps
CPU time	30.9 seconds
Started	Apr 28 12:48:02 PM PDT 24
Finished	Apr 28 12:48:33 PM PDT 24
Peak memory	203536 kb
Host	smart-f8dd4cd2-18d1-4959-a843-304d399dd3b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060968300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3060968300
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1493194653
Short name	T799
Test name
Test status
Simulation time	4062602763 ps
CPU time	32.72 seconds
Started	Apr 28 12:48:09 PM PDT 24
Finished	Apr 28 12:48:43 PM PDT 24
Peak memory	203456 kb
Host	smart-3ea5cd3e-31cc-495d-ae89-0c84139b78df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1493194653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1493194653
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3339728527
Short name	T241
Test name
Test status
Simulation time	74502079 ps
CPU time	2.41 seconds
Started	Apr 28 12:48:04 PM PDT 24
Finished	Apr 28 12:48:07 PM PDT 24
Peak memory	203396 kb
Host	smart-62ff3358-1886-413e-b63e-41ff15617055
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339728527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3339728527
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.1033624560
Short name	T427
Test name
Test status
Simulation time	809756168 ps
CPU time	31.04 seconds
Started	Apr 28 12:48:10 PM PDT 24
Finished	Apr 28 12:48:42 PM PDT 24
Peak memory	211680 kb
Host	smart-7e2d2069-fdeb-4f2f-9c2a-4fdcffbe03b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1033624560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1033624560
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1499661844
Short name	T275
Test name
Test status
Simulation time	5576558370 ps
CPU time	64.06 seconds
Started	Apr 28 12:48:06 PM PDT 24
Finished	Apr 28 12:49:11 PM PDT 24
Peak memory	204964 kb
Host	smart-1f124b6e-e91d-4abd-9de3-a911c64a0718
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1499661844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1499661844
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.652558126
Short name	T186
Test name
Test status
Simulation time	266750642 ps
CPU time	66.35 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:49:14 PM PDT 24
Peak memory	206816 kb
Host	smart-bd877609-3a8f-4c76-acf8-cf7147fb18f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652558126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.652558126
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.648733334
Short name	T355
Test name
Test status
Simulation time	24306490 ps
CPU time	3.36 seconds
Started	Apr 28 12:48:08 PM PDT 24
Finished	Apr 28 12:48:11 PM PDT 24
Peak memory	204492 kb
Host	smart-36feba71-8561-4385-aa5b-d0db8eb8d88e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=648733334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.648733334
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2380111435
Short name	T642
Test name
Test status
Simulation time	2161935761 ps
CPU time	43.15 seconds
Started	Apr 28 12:48:10 PM PDT 24
Finished	Apr 28 12:48:54 PM PDT 24
Peak memory	205180 kb
Host	smart-c906aca0-2681-4e5b-b81f-40203fe64b3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2380111435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2380111435
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.270586165
Short name	T722
Test name
Test status
Simulation time	34130078736 ps
CPU time	300.38 seconds
Started	Apr 28 12:48:09 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	206084 kb
Host	smart-49ca6571-552c-47c0-b6e3-6b0379869522
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=270586165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.270586165
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3778994197
Short name	T648
Test name
Test status
Simulation time	853878178 ps
CPU time	17.54 seconds
Started	Apr 28 12:48:15 PM PDT 24
Finished	Apr 28 12:48:33 PM PDT 24
Peak memory	203436 kb
Host	smart-1af6b221-6981-40fe-b557-1441cd0f6a3b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3778994197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3778994197
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.810240470
Short name	T613
Test name
Test status
Simulation time	3174830650 ps
CPU time	31.14 seconds
Started	Apr 28 12:48:11 PM PDT 24
Finished	Apr 28 12:48:43 PM PDT 24
Peak memory	203548 kb
Host	smart-522b2d47-f50c-4576-a1d3-9ae27aa56c46
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=810240470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.810240470
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.1916266974
Short name	T253
Test name
Test status
Simulation time	242693196 ps
CPU time	6.48 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:48:14 PM PDT 24
Peak memory	211528 kb
Host	smart-9f4142ed-e564-4b23-881a-988d8ca16d6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1916266974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1916266974
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.47992935
Short name	T46
Test name
Test status
Simulation time	241562459806 ps
CPU time	320.96 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:53:28 PM PDT 24
Peak memory	205788 kb
Host	smart-1500a059-362e-49a6-abe4-70107ee19855
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=47992935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.47992935
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2718745753
Short name	T12
Test name
Test status
Simulation time	7598346339 ps
CPU time	54.71 seconds
Started	Apr 28 12:48:05 PM PDT 24
Finished	Apr 28 12:49:00 PM PDT 24
Peak memory	204640 kb
Host	smart-aad059ee-5b6d-41e3-a5ad-03a8a1c3b443
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2718745753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2718745753
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.676603825
Short name	T293
Test name
Test status
Simulation time	111149283 ps
CPU time	15.29 seconds
Started	Apr 28 12:48:11 PM PDT 24
Finished	Apr 28 12:48:27 PM PDT 24
Peak memory	204600 kb
Host	smart-ae7d87b2-3e7b-4aa0-9cb0-93a5a6319f5f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676603825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.676603825
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.632298485
Short name	T372
Test name
Test status
Simulation time	429067733 ps
CPU time	19.61 seconds
Started	Apr 28 12:48:10 PM PDT 24
Finished	Apr 28 12:48:31 PM PDT 24
Peak memory	204064 kb
Host	smart-f711b1db-d87c-4f69-bc35-fb701e07ac6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=632298485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.632298485
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.1630967210
Short name	T867
Test name
Test status
Simulation time	448364765 ps
CPU time	3.21 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:48:11 PM PDT 24
Peak memory	203368 kb
Host	smart-17878144-d00f-40ac-b9db-b5716bf9043b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1630967210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1630967210
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3533299526
Short name	T411
Test name
Test status
Simulation time	13010183255 ps
CPU time	29.45 seconds
Started	Apr 28 12:48:10 PM PDT 24
Finished	Apr 28 12:48:40 PM PDT 24
Peak memory	203440 kb
Host	smart-7f753103-084d-47f9-8d57-7e80571f8e52
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533299526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3533299526
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3879306833
Short name	T352
Test name
Test status
Simulation time	3790914100 ps
CPU time	23.39 seconds
Started	Apr 28 12:48:07 PM PDT 24
Finished	Apr 28 12:48:31 PM PDT 24
Peak memory	203552 kb
Host	smart-66b55a11-7d2d-4cd1-8861-34859b46787c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3879306833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3879306833
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.637635613
Short name	T439
Test name
Test status
Simulation time	59739269 ps
CPU time	1.9 seconds
Started	Apr 28 12:48:08 PM PDT 24
Finished	Apr 28 12:48:10 PM PDT 24
Peak memory	203460 kb
Host	smart-32fd5df9-965e-4d84-85ad-00665582c460
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637635613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.637635613
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.542422364
Short name	T401
Test name
Test status
Simulation time	1732728885 ps
CPU time	57.75 seconds
Started	Apr 28 12:48:20 PM PDT 24
Finished	Apr 28 12:49:18 PM PDT 24
Peak memory	207212 kb
Host	smart-1bd75909-1ade-44e9-b3f1-f2386ce9c883
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=542422364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.542422364
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2654889647
Short name	T718
Test name
Test status
Simulation time	6549123400 ps
CPU time	72.49 seconds
Started	Apr 28 12:48:14 PM PDT 24
Finished	Apr 28 12:49:27 PM PDT 24
Peak memory	205328 kb
Host	smart-bdca588c-c6cc-48e8-bac8-22143f2dd0d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2654889647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2654889647
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1069502274
Short name	T805
Test name
Test status
Simulation time	259907234 ps
CPU time	77.92 seconds
Started	Apr 28 12:48:11 PM PDT 24
Finished	Apr 28 12:49:30 PM PDT 24
Peak memory	208444 kb
Host	smart-0343135e-6425-4683-99a7-b8af694dd65a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1069502274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1069502274
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1523281292
Short name	T463
Test name
Test status
Simulation time	17462900378 ps
CPU time	521.97 seconds
Started	Apr 28 12:48:12 PM PDT 24
Finished	Apr 28 12:56:54 PM PDT 24
Peak memory	219844 kb
Host	smart-b5cf2c27-7d67-42b4-adb0-6193c3089ba9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1523281292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1523281292
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3128126653
Short name	T395
Test name
Test status
Simulation time	117015872 ps
CPU time	12.95 seconds
Started	Apr 28 12:48:13 PM PDT 24
Finished	Apr 28 12:48:26 PM PDT 24
Peak memory	205068 kb
Host	smart-1d519d15-9ff7-4738-9048-fc01f7326ac3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3128126653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3128126653
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.238332185
Short name	T435
Test name
Test status
Simulation time	36781449 ps
CPU time	7.67 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:48:25 PM PDT 24
Peak memory	204440 kb
Host	smart-37b2bc17-ef74-4b34-8b78-b1f546e7bbfb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=238332185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.238332185
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.53447232
Short name	T215
Test name
Test status
Simulation time	6743263139 ps
CPU time	35.32 seconds
Started	Apr 28 12:48:15 PM PDT 24
Finished	Apr 28 12:48:51 PM PDT 24
Peak memory	204148 kb
Host	smart-08525d8e-b0f1-4a80-b6ac-9b19cc19ef7e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=53447232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow _rsp.53447232
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1966049628
Short name	T838
Test name
Test status
Simulation time	524663334 ps
CPU time	17.55 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:48:35 PM PDT 24
Peak memory	203764 kb
Host	smart-55dcd21e-7270-4fac-9e34-81b0e1cafc5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1966049628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1966049628
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.4078610436
Short name	T300
Test name
Test status
Simulation time	739393339 ps
CPU time	18.58 seconds
Started	Apr 28 12:48:16 PM PDT 24
Finished	Apr 28 12:48:35 PM PDT 24
Peak memory	203376 kb
Host	smart-c688abf4-22c0-4757-b3ea-0aea50321226
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4078610436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.4078610436
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.1720045496
Short name	T452
Test name
Test status
Simulation time	158092935 ps
CPU time	10.51 seconds
Started	Apr 28 12:48:11 PM PDT 24
Finished	Apr 28 12:48:22 PM PDT 24
Peak memory	204460 kb
Host	smart-b1eb5e70-f2dc-45a5-a756-30f30cdefc00
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1720045496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1720045496
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3676507714
Short name	T116
Test name
Test status
Simulation time	3974974368 ps
CPU time	24.35 seconds
Started	Apr 28 12:48:20 PM PDT 24
Finished	Apr 28 12:48:45 PM PDT 24
Peak memory	203536 kb
Host	smart-a47b57ad-73ea-4db9-a12f-1d5ebfb650c8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676507714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3676507714
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3590242622
Short name	T600
Test name
Test status
Simulation time	117255162112 ps
CPU time	294.68 seconds
Started	Apr 28 12:48:11 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	205376 kb
Host	smart-4a3153ac-cbe2-425f-b240-d790a741204c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3590242622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3590242622
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1291032587
Short name	T858
Test name
Test status
Simulation time	875396251 ps
CPU time	20.75 seconds
Started	Apr 28 12:48:13 PM PDT 24
Finished	Apr 28 12:48:34 PM PDT 24
Peak memory	204564 kb
Host	smart-f789521f-78b5-4784-8231-c67867d62351
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291032587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1291032587
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.4251628644
Short name	T268
Test name
Test status
Simulation time	2227417841 ps
CPU time	33.48 seconds
Started	Apr 28 12:48:16 PM PDT 24
Finished	Apr 28 12:48:50 PM PDT 24
Peak memory	203548 kb
Host	smart-3a19b919-df72-4a70-9ac7-5806f25b1122
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4251628644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4251628644
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.1655858081
Short name	T423
Test name
Test status
Simulation time	625573226 ps
CPU time	4.2 seconds
Started	Apr 28 12:48:19 PM PDT 24
Finished	Apr 28 12:48:24 PM PDT 24
Peak memory	203476 kb
Host	smart-88042d9c-d6bf-45a7-8378-0ca713e8b495
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1655858081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1655858081
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2946933423
Short name	T329
Test name
Test status
Simulation time	3819079009 ps
CPU time	21.98 seconds
Started	Apr 28 12:48:19 PM PDT 24
Finished	Apr 28 12:48:42 PM PDT 24
Peak memory	203520 kb
Host	smart-169a89e1-2be4-4899-8690-2b338815519c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946933423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2946933423
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2175497817
Short name	T379
Test name
Test status
Simulation time	3977297247 ps
CPU time	31.12 seconds
Started	Apr 28 12:48:12 PM PDT 24
Finished	Apr 28 12:48:43 PM PDT 24
Peak memory	203520 kb
Host	smart-309b418f-7e11-47a5-ae8d-c170022d6b1c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2175497817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2175497817
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.917891471
Short name	T888
Test name
Test status
Simulation time	27821156 ps
CPU time	2.37 seconds
Started	Apr 28 12:48:20 PM PDT 24
Finished	Apr 28 12:48:23 PM PDT 24
Peak memory	203480 kb
Host	smart-c8beff71-65b0-4175-b769-1219a93045ad
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917891471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.917891471
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.2013527921
Short name	T517
Test name
Test status
Simulation time	804112028 ps
CPU time	104.4 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:50:02 PM PDT 24
Peak memory	209276 kb
Host	smart-684ef6ee-4f0a-4748-a615-bff993fe57d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2013527921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2013527921
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1322223594
Short name	T448
Test name
Test status
Simulation time	978382611 ps
CPU time	9.51 seconds
Started	Apr 28 12:48:16 PM PDT 24
Finished	Apr 28 12:48:26 PM PDT 24
Peak memory	203504 kb
Host	smart-35571d5e-6b10-4123-ab3f-7f631e7fde90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322223594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1322223594
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.934625915
Short name	T323
Test name
Test status
Simulation time	435043206 ps
CPU time	124.72 seconds
Started	Apr 28 12:48:19 PM PDT 24
Finished	Apr 28 12:50:24 PM PDT 24
Peak memory	208048 kb
Host	smart-e5ffaacb-0ba6-482d-9373-50212d06baa6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=934625915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.934625915
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1437511744
Short name	T883
Test name
Test status
Simulation time	375201516 ps
CPU time	96.75 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:49:55 PM PDT 24
Peak memory	209524 kb
Host	smart-a13ff04a-f0e1-44e6-bc0c-fa8b21e46e2d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1437511744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1437511744
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1536635501
Short name	T626
Test name
Test status
Simulation time	105335744 ps
CPU time	4.19 seconds
Started	Apr 28 12:48:18 PM PDT 24
Finished	Apr 28 12:48:23 PM PDT 24
Peak memory	204608 kb
Host	smart-d22abe48-bdd3-48a0-933b-ee0fd4f85685
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1536635501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1536635501
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1670307947
Short name	T108
Test name
Test status
Simulation time	3403920778 ps
CPU time	50.77 seconds
Started	Apr 28 12:48:20 PM PDT 24
Finished	Apr 28 12:49:12 PM PDT 24
Peak memory	211736 kb
Host	smart-f5a37213-fc4f-4af2-8f7e-464aa7cf1e27
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1670307947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1670307947
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2045472124
Short name	T509
Test name
Test status
Simulation time	43776389009 ps
CPU time	253.63 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	206028 kb
Host	smart-591a8ce5-531e-48a4-98b0-0febc467c644
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2045472124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2045472124
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2758445633
Short name	T635
Test name
Test status
Simulation time	502949252 ps
CPU time	19.85 seconds
Started	Apr 28 12:48:23 PM PDT 24
Finished	Apr 28 12:48:43 PM PDT 24
Peak memory	203644 kb
Host	smart-b74d7240-687f-47b2-8b4b-74e6262dd10d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758445633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2758445633
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.300460824
Short name	T354
Test name
Test status
Simulation time	834465916 ps
CPU time	33.27 seconds
Started	Apr 28 12:48:24 PM PDT 24
Finished	Apr 28 12:48:58 PM PDT 24
Peak memory	203676 kb
Host	smart-c91d5e84-d73a-4463-ab22-14c6584ef6b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=300460824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.300460824
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.2205160528
Short name	T656
Test name
Test status
Simulation time	873995467 ps
CPU time	28.61 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:48:46 PM PDT 24
Peak memory	204452 kb
Host	smart-6cd9e41c-7965-4da0-bacb-c65e24ea15c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2205160528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2205160528
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3520271858
Short name	T175
Test name
Test status
Simulation time	25193746065 ps
CPU time	132.67 seconds
Started	Apr 28 12:48:16 PM PDT 24
Finished	Apr 28 12:50:29 PM PDT 24
Peak memory	205040 kb
Host	smart-6290228a-1383-4835-89f6-9478e5449f11
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520271858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3520271858
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2786279514
Short name	T195
Test name
Test status
Simulation time	8158706372 ps
CPU time	60.12 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:49:18 PM PDT 24
Peak memory	211592 kb
Host	smart-1cffbf65-3e90-4f6a-88f4-e4e9a9a3a31b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2786279514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2786279514
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1071312243
Short name	T573
Test name
Test status
Simulation time	261907878 ps
CPU time	23.71 seconds
Started	Apr 28 12:48:18 PM PDT 24
Finished	Apr 28 12:48:42 PM PDT 24
Peak memory	211560 kb
Host	smart-13010c17-ee07-44f0-a062-1e92870bd481
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071312243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1071312243
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.1164987419
Short name	T486
Test name
Test status
Simulation time	3687303807 ps
CPU time	31.3 seconds
Started	Apr 28 12:48:22 PM PDT 24
Finished	Apr 28 12:48:53 PM PDT 24
Peak memory	204196 kb
Host	smart-7001897a-b1ad-44f1-89ba-d7d7da095e4c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1164987419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1164987419
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.981377679
Short name	T516
Test name
Test status
Simulation time	120834772 ps
CPU time	3.58 seconds
Started	Apr 28 12:48:16 PM PDT 24
Finished	Apr 28 12:48:20 PM PDT 24
Peak memory	203500 kb
Host	smart-b504c554-c985-48c4-ab04-6fb4e0a910da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981377679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.981377679
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3934898521
Short name	T332
Test name
Test status
Simulation time	5761693809 ps
CPU time	33.38 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:48:51 PM PDT 24
Peak memory	203364 kb
Host	smart-07dac7ef-8f7c-4e2d-9a27-2797df3aa4a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934898521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3934898521
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2727785563
Short name	T478
Test name
Test status
Simulation time	15137756674 ps
CPU time	37.47 seconds
Started	Apr 28 12:48:16 PM PDT 24
Finished	Apr 28 12:48:54 PM PDT 24
Peak memory	203416 kb
Host	smart-ff03039e-b1dd-4739-b55a-502749bbf395
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2727785563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2727785563
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2492264258
Short name	T834
Test name
Test status
Simulation time	27422638 ps
CPU time	1.96 seconds
Started	Apr 28 12:48:17 PM PDT 24
Finished	Apr 28 12:48:20 PM PDT 24
Peak memory	203316 kb
Host	smart-0ebd59fa-10ed-4edd-a000-32142f7b40b0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492264258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2492264258
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.3157187074
Short name	T624
Test name
Test status
Simulation time	3735825313 ps
CPU time	34.39 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:48:56 PM PDT 24
Peak memory	206760 kb
Host	smart-0eee7f9e-017d-4376-9efb-4053b6c34f14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157187074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3157187074
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3950727894
Short name	T99
Test name
Test status
Simulation time	1252401531 ps
CPU time	40.79 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:49:02 PM PDT 24
Peak memory	206604 kb
Host	smart-81348062-7345-4e3a-9ea7-f7b76cee2a6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3950727894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3950727894
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2086223794
Short name	T362
Test name
Test status
Simulation time	671078995 ps
CPU time	221.64 seconds
Started	Apr 28 12:48:24 PM PDT 24
Finished	Apr 28 12:52:06 PM PDT 24
Peak memory	209236 kb
Host	smart-73b7cc23-4f20-414a-ad4e-3ce265deeb24
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2086223794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.2086223794
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3058500035
Short name	T247
Test name
Test status
Simulation time	8396395 ps
CPU time	5.08 seconds
Started	Apr 28 12:48:23 PM PDT 24
Finished	Apr 28 12:48:29 PM PDT 24
Peak memory	203304 kb
Host	smart-35a9797c-7dab-460c-b2af-076d9ca3e4a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3058500035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.3058500035
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.844504388
Short name	T299
Test name
Test status
Simulation time	1752989794 ps
CPU time	20.92 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:48:43 PM PDT 24
Peak memory	204836 kb
Host	smart-82b2fee3-ffd2-4a06-a48f-36789a5bc0d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=844504388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.844504388
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2852845592
Short name	T310
Test name
Test status
Simulation time	1084864737 ps
CPU time	22.74 seconds
Started	Apr 28 12:48:23 PM PDT 24
Finished	Apr 28 12:48:46 PM PDT 24
Peak memory	211576 kb
Host	smart-ba7f7456-09e9-4009-9cd8-8e1f9634d010
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2852845592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2852845592
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1503690425
Short name	T189
Test name
Test status
Simulation time	69353897865 ps
CPU time	325.95 seconds
Started	Apr 28 12:48:24 PM PDT 24
Finished	Apr 28 12:53:51 PM PDT 24
Peak memory	211772 kb
Host	smart-8d8a65ae-5ae4-44c5-b6ff-682edd0df685
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1503690425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.1503690425
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3082216700
Short name	T864
Test name
Test status
Simulation time	304938323 ps
CPU time	10.18 seconds
Started	Apr 28 12:48:26 PM PDT 24
Finished	Apr 28 12:48:37 PM PDT 24
Peak memory	203648 kb
Host	smart-fc75e820-5fc5-4682-8ab8-36a3b8430153
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3082216700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3082216700
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.101473266
Short name	T206
Test name
Test status
Simulation time	990551775 ps
CPU time	12.55 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:48:34 PM PDT 24
Peak memory	203364 kb
Host	smart-e23a72cc-2e0c-48aa-a538-9b3a2fe9624e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=101473266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.101473266
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.1073421668
Short name	T53
Test name
Test status
Simulation time	82174439 ps
CPU time	2.73 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:48:24 PM PDT 24
Peak memory	203472 kb
Host	smart-43a19ce1-77e6-485e-8b5c-c81a05bf5dc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1073421668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1073421668
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.616446649
Short name	T56
Test name
Test status
Simulation time	17047076910 ps
CPU time	105.03 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:50:06 PM PDT 24
Peak memory	204600 kb
Host	smart-9a1359f2-2b62-4d89-aeca-f2c1863ef7f7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=616446649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.616446649
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1062699464
Short name	T861
Test name
Test status
Simulation time	33380647046 ps
CPU time	212.46 seconds
Started	Apr 28 12:48:21 PM PDT 24
Finished	Apr 28 12:51:54 PM PDT 24
Peak memory	211604 kb
Host	smart-69e835ac-fd94-4ace-a4d5-788771b3cac7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1062699464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1062699464
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.511813427
Short name	T382
Test name
Test status
Simulation time	73933073 ps
CPU time	6.56 seconds
Started	Apr 28 12:48:23 PM PDT 24
Finished	Apr 28 12:48:30 PM PDT 24
Peak memory	204448 kb
Host	smart-d67724d8-5051-44b3-a465-83eba0270058
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511813427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.511813427
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.992957831
Short name	T724
Test name
Test status
Simulation time	829642260 ps
CPU time	14.29 seconds
Started	Apr 28 12:48:22 PM PDT 24
Finished	Apr 28 12:48:36 PM PDT 24
Peak memory	204172 kb
Host	smart-07840b77-78f2-4ec7-ac77-d314d86f0728
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992957831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.992957831
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.2745956877
Short name	T631
Test name
Test status
Simulation time	98702101 ps
CPU time	2.9 seconds
Started	Apr 28 12:48:23 PM PDT 24
Finished	Apr 28 12:48:26 PM PDT 24
Peak memory	203320 kb
Host	smart-e8e2db28-7976-4455-84ad-a72e87dd3e1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2745956877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2745956877
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1640883893
Short name	T287
Test name
Test status
Simulation time	9643074729 ps
CPU time	33.15 seconds
Started	Apr 28 12:48:20 PM PDT 24
Finished	Apr 28 12:48:54 PM PDT 24
Peak memory	203492 kb
Host	smart-78c116b2-71f1-42d0-9673-00e84f60289d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640883893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1640883893
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2419999252
Short name	T349
Test name
Test status
Simulation time	25153920881 ps
CPU time	50.62 seconds
Started	Apr 28 12:48:24 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	203408 kb
Host	smart-20b3a5b1-f43b-4e19-8bab-07cac2fa9f3f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2419999252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2419999252
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.4134088636
Short name	T632
Test name
Test status
Simulation time	32738184 ps
CPU time	2.1 seconds
Started	Apr 28 12:48:24 PM PDT 24
Finished	Apr 28 12:48:27 PM PDT 24
Peak memory	203484 kb
Host	smart-b64f97c3-1d33-4df9-8d85-d88d056c7690
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134088636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.4134088636
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.338623936
Short name	T79
Test name
Test status
Simulation time	4448833803 ps
CPU time	33.01 seconds
Started	Apr 28 12:48:26 PM PDT 24
Finished	Apr 28 12:48:59 PM PDT 24
Peak memory	205964 kb
Host	smart-bcb2e417-87e2-4da3-89a7-8b1e0a1edd51
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=338623936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.338623936
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.700502537
Short name	T288
Test name
Test status
Simulation time	548608774 ps
CPU time	41.46 seconds
Started	Apr 28 12:48:27 PM PDT 24
Finished	Apr 28 12:49:08 PM PDT 24
Peak memory	204468 kb
Host	smart-7da6a565-e0f7-4600-8d7e-09d2c13f3fa6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=700502537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.700502537
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.369572825
Short name	T226
Test name
Test status
Simulation time	784010159 ps
CPU time	282.89 seconds
Started	Apr 28 12:48:27 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	208700 kb
Host	smart-14a2444b-59fc-4591-821b-774df244ab9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=369572825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.369572825
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1009501810
Short name	T461
Test name
Test status
Simulation time	5136198397 ps
CPU time	478.98 seconds
Started	Apr 28 12:48:26 PM PDT 24
Finished	Apr 28 12:56:25 PM PDT 24
Peak memory	224840 kb
Host	smart-3808a24f-e81d-4e56-a64c-026f5f3f7026
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1009501810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1009501810
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3411428703
Short name	T489
Test name
Test status
Simulation time	103341997 ps
CPU time	11.98 seconds
Started	Apr 28 12:48:24 PM PDT 24
Finished	Apr 28 12:48:36 PM PDT 24
Peak memory	204772 kb
Host	smart-c2f911e3-68da-4d72-a951-1ee784aaf4ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3411428703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3411428703
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3342547446
Short name	T16
Test name
Test status
Simulation time	498146228 ps
CPU time	42.43 seconds
Started	Apr 28 12:48:30 PM PDT 24
Finished	Apr 28 12:49:13 PM PDT 24
Peak memory	204380 kb
Host	smart-9af7ea51-c601-41ad-9824-bb556e083bb3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3342547446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3342547446
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2906795077
Short name	T83
Test name
Test status
Simulation time	64914337990 ps
CPU time	557.55 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:57:55 PM PDT 24
Peak memory	207048 kb
Host	smart-8193a1a1-dd7b-4588-a6ee-5b83c0b289cd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2906795077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2906795077
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1226527546
Short name	T444
Test name
Test status
Simulation time	770709637 ps
CPU time	24.32 seconds
Started	Apr 28 12:48:31 PM PDT 24
Finished	Apr 28 12:48:56 PM PDT 24
Peak memory	204036 kb
Host	smart-b744da87-d4af-40f1-b840-15bc930961b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1226527546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1226527546
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.3990541254
Short name	T612
Test name
Test status
Simulation time	740801366 ps
CPU time	26.28 seconds
Started	Apr 28 12:48:31 PM PDT 24
Finished	Apr 28 12:48:58 PM PDT 24
Peak memory	203312 kb
Host	smart-a60bf311-b2de-420c-a4b7-3dbc4e87eac9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3990541254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3990541254
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.3078052318
Short name	T224
Test name
Test status
Simulation time	2019412735 ps
CPU time	32.15 seconds
Started	Apr 28 12:48:28 PM PDT 24
Finished	Apr 28 12:49:00 PM PDT 24
Peak memory	204748 kb
Host	smart-6dd0e89f-87dd-442a-902a-d1d099c234a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3078052318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3078052318
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3737278824
Short name	T830
Test name
Test status
Simulation time	9288196663 ps
CPU time	56.68 seconds
Started	Apr 28 12:48:31 PM PDT 24
Finished	Apr 28 12:49:28 PM PDT 24
Peak memory	204812 kb
Host	smart-e42d4696-4e49-46aa-b32d-74885f59b850
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737278824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3737278824
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2561251289
Short name	T440
Test name
Test status
Simulation time	142249943810 ps
CPU time	331.94 seconds
Started	Apr 28 12:48:39 PM PDT 24
Finished	Apr 28 12:54:12 PM PDT 24
Peak memory	205220 kb
Host	smart-bcaf045b-269a-4cba-96f2-021b353d43d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2561251289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2561251289
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.404506075
Short name	T668
Test name
Test status
Simulation time	128151265 ps
CPU time	7.99 seconds
Started	Apr 28 12:48:32 PM PDT 24
Finished	Apr 28 12:48:40 PM PDT 24
Peak memory	211648 kb
Host	smart-20a515ce-1158-4839-8a88-9028a9a642ba
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404506075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.404506075
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.1704362929
Short name	T101
Test name
Test status
Simulation time	582157614 ps
CPU time	5.58 seconds
Started	Apr 28 12:48:31 PM PDT 24
Finished	Apr 28 12:48:37 PM PDT 24
Peak memory	203460 kb
Host	smart-02a37fda-c8a4-43a1-90d2-a5d936aa9f33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1704362929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1704362929
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.946169409
Short name	T583
Test name
Test status
Simulation time	43101043 ps
CPU time	2.03 seconds
Started	Apr 28 12:48:32 PM PDT 24
Finished	Apr 28 12:48:35 PM PDT 24
Peak memory	203428 kb
Host	smart-85a2e1b8-3554-4916-8b7a-90a408d8968a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=946169409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.946169409
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1933225661
Short name	T158
Test name
Test status
Simulation time	13164599582 ps
CPU time	34.62 seconds
Started	Apr 28 12:48:25 PM PDT 24
Finished	Apr 28 12:49:00 PM PDT 24
Peak memory	203460 kb
Host	smart-d4270ded-c200-4072-8b90-0235fd2ac473
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933225661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1933225661
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.8289116
Short name	T520
Test name
Test status
Simulation time	3816524944 ps
CPU time	32.83 seconds
Started	Apr 28 12:48:26 PM PDT 24
Finished	Apr 28 12:48:59 PM PDT 24
Peak memory	203440 kb
Host	smart-d8a3f8b3-db34-4aba-9468-fc0a0eaf8865
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=8289116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.8289116
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.658502047
Short name	T899
Test name
Test status
Simulation time	41233663 ps
CPU time	2.07 seconds
Started	Apr 28 12:48:26 PM PDT 24
Finished	Apr 28 12:48:28 PM PDT 24
Peak memory	203476 kb
Host	smart-63d411cb-ad47-49fe-9bca-4333070c4786
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658502047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.658502047
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.4224541540
Short name	T129
Test name
Test status
Simulation time	3452146094 ps
CPU time	130.63 seconds
Started	Apr 28 12:48:32 PM PDT 24
Finished	Apr 28 12:50:43 PM PDT 24
Peak memory	206748 kb
Host	smart-d70f8851-110b-4b45-9839-067919a07f6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4224541540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4224541540
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1383190682
Short name	T477
Test name
Test status
Simulation time	1977870063 ps
CPU time	123.64 seconds
Started	Apr 28 12:48:34 PM PDT 24
Finished	Apr 28 12:50:38 PM PDT 24
Peak memory	208484 kb
Host	smart-711e0a94-ecf7-4c20-8e49-a2b1139b25e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1383190682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1383190682
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1137603374
Short name	T890
Test name
Test status
Simulation time	6687124378 ps
CPU time	238.45 seconds
Started	Apr 28 12:48:30 PM PDT 24
Finished	Apr 28 12:52:29 PM PDT 24
Peak memory	208752 kb
Host	smart-a2d08250-d13f-4ac1-8866-2728f7f348bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1137603374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.1137603374
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.658677782
Short name	T771
Test name
Test status
Simulation time	76763758 ps
CPU time	35.47 seconds
Started	Apr 28 12:48:32 PM PDT 24
Finished	Apr 28 12:49:08 PM PDT 24
Peak memory	206292 kb
Host	smart-aa887302-9086-4b39-a928-72d047d70c09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=658677782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.658677782
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2192406393
Short name	T766
Test name
Test status
Simulation time	1768328140 ps
CPU time	22.9 seconds
Started	Apr 28 12:48:32 PM PDT 24
Finished	Apr 28 12:48:55 PM PDT 24
Peak memory	205328 kb
Host	smart-a4bafa41-bed0-429d-b4c2-7558d8b25776
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192406393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2192406393
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.118999101
Short name	T188
Test name
Test status
Simulation time	16007375192 ps
CPU time	151.85 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:49:34 PM PDT 24
Peak memory	206312 kb
Host	smart-317759a7-b0b0-4671-8680-5d7e31489e7f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=118999101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow _rsp.118999101
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.629055546
Short name	T781
Test name
Test status
Simulation time	640044713 ps
CPU time	25.82 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	204044 kb
Host	smart-1426d678-dc9a-4d56-97b9-0d1abdd7af86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=629055546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.629055546
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.839873316
Short name	T240
Test name
Test status
Simulation time	249535291 ps
CPU time	9.7 seconds
Started	Apr 28 12:46:45 PM PDT 24
Finished	Apr 28 12:46:55 PM PDT 24
Peak memory	203456 kb
Host	smart-16f6aba1-1f1f-48e6-8aae-3a8b47d33f58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=839873316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.839873316
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.1191449363
Short name	T650
Test name
Test status
Simulation time	30414078 ps
CPU time	3.34 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:46:52 PM PDT 24
Peak memory	203884 kb
Host	smart-acf35ca2-f996-4876-a142-a11744fea347
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1191449363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1191449363
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1011811249
Short name	T893
Test name
Test status
Simulation time	37284695644 ps
CPU time	199.55 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:50:25 PM PDT 24
Peak memory	204940 kb
Host	smart-b40a2058-22c7-419e-8c65-e1e5bdb9d9ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011811249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1011811249
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1735989626
Short name	T61
Test name
Test status
Simulation time	42229443948 ps
CPU time	156.71 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:49:26 PM PDT 24
Peak memory	204960 kb
Host	smart-7239b251-41a1-4035-9271-cd275f6af5e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1735989626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1735989626
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1958077090
Short name	T11
Test name
Test status
Simulation time	191357887 ps
CPU time	7.85 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:46:57 PM PDT 24
Peak memory	204532 kb
Host	smart-f9e8626c-a210-4ac5-82d2-e92827cd8e07
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958077090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1958077090
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.209570010
Short name	T498
Test name
Test status
Simulation time	680114841 ps
CPU time	8.62 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:15 PM PDT 24
Peak memory	203312 kb
Host	smart-f121986e-a0c7-4f69-b07a-c72081f31ba9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=209570010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.209570010
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.3276866169
Short name	T163
Test name
Test status
Simulation time	128638897 ps
CPU time	2.04 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:47:05 PM PDT 24
Peak memory	203440 kb
Host	smart-c22351e2-6ccb-476e-8ec7-88b934e3f870
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3276866169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3276866169
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1311439133
Short name	T258
Test name
Test status
Simulation time	14213403003 ps
CPU time	43.24 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:50 PM PDT 24
Peak memory	203452 kb
Host	smart-fa052a56-cfc5-4688-8441-2151ccae2a6c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311439133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1311439133
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1850869271
Short name	T341
Test name
Test status
Simulation time	3147858848 ps
CPU time	27.67 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:34 PM PDT 24
Peak memory	203412 kb
Host	smart-9e476fbd-47e1-488e-a144-c2e39662d607
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1850869271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1850869271
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2129998931
Short name	T628
Test name
Test status
Simulation time	25755378 ps
CPU time	2.28 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:09 PM PDT 24
Peak memory	203484 kb
Host	smart-8e265bee-6f88-49af-8ccf-7450298180f8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129998931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2129998931
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.922338362
Short name	T514
Test name
Test status
Simulation time	7204675413 ps
CPU time	230.69 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:50:56 PM PDT 24
Peak memory	207516 kb
Host	smart-fb8c44c5-204c-41ed-a120-bfab2eeeb105
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=922338362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.922338362
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4102812472
Short name	T544
Test name
Test status
Simulation time	9506415466 ps
CPU time	146.86 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:49:17 PM PDT 24
Peak memory	208196 kb
Host	smart-afdb1374-6415-402d-b51d-42d5bb9f4e83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4102812472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4102812472
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.64598465
Short name	T187
Test name
Test status
Simulation time	3784453355 ps
CPU time	359.94 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:53:06 PM PDT 24
Peak memory	208344 kb
Host	smart-f0dc456e-1eb0-4093-b675-e9f1161b6d45
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=64598465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_r eset.64598465
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1848242016
Short name	T843
Test name
Test status
Simulation time	4409929505 ps
CPU time	218.46 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:50:44 PM PDT 24
Peak memory	219932 kb
Host	smart-48bd4336-3dfe-49cb-8132-d192607d6911
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1848242016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1848242016
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.529553976
Short name	T98
Test name
Test status
Simulation time	204855826 ps
CPU time	7.88 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:00 PM PDT 24
Peak memory	211632 kb
Host	smart-e71883cf-ebd2-426d-b9c8-7dd39005a0b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=529553976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.529553976
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3134827463
Short name	T58
Test name
Test status
Simulation time	6672856914 ps
CPU time	42.51 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:49:20 PM PDT 24
Peak memory	205464 kb
Host	smart-3e86cbd6-572e-4b3f-97e0-4c413cb6dfde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3134827463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3134827463
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3650020737
Short name	T128
Test name
Test status
Simulation time	17947887865 ps
CPU time	138.71 seconds
Started	Apr 28 12:48:37 PM PDT 24
Finished	Apr 28 12:50:57 PM PDT 24
Peak memory	206284 kb
Host	smart-b624d2cc-26b1-4969-a447-ac159a295790
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3650020737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.3650020737
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2735194866
Short name	T239
Test name
Test status
Simulation time	355137738 ps
CPU time	12.43 seconds
Started	Apr 28 12:48:35 PM PDT 24
Finished	Apr 28 12:48:48 PM PDT 24
Peak memory	203660 kb
Host	smart-142de94f-2523-4be1-93ae-01e7005288bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2735194866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2735194866
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.395875002
Short name	T504
Test name
Test status
Simulation time	1143706649 ps
CPU time	32.14 seconds
Started	Apr 28 12:48:39 PM PDT 24
Finished	Apr 28 12:49:12 PM PDT 24
Peak memory	203440 kb
Host	smart-7ee8d8f8-8f52-4c5b-bec2-0ed7aef1ab99
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=395875002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.395875002
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.3721317099
Short name	T55
Test name
Test status
Simulation time	1213847428 ps
CPU time	28.96 seconds
Started	Apr 28 12:48:32 PM PDT 24
Finished	Apr 28 12:49:02 PM PDT 24
Peak memory	205028 kb
Host	smart-183e5a8d-9cee-4762-90a1-705fac620bf6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3721317099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3721317099
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2813432165
Short name	T148
Test name
Test status
Simulation time	92576305304 ps
CPU time	155.75 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:51:13 PM PDT 24
Peak memory	211696 kb
Host	smart-206a1642-eaae-4931-8b4b-0c06f6be3d18
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813432165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2813432165
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3287045717
Short name	T377
Test name
Test status
Simulation time	20823053488 ps
CPU time	145.64 seconds
Started	Apr 28 12:48:34 PM PDT 24
Finished	Apr 28 12:51:00 PM PDT 24
Peak memory	205172 kb
Host	smart-0922dd6c-1137-4b5c-a376-e48764ec3d21
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3287045717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3287045717
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.4018974780
Short name	T703
Test name
Test status
Simulation time	133008981 ps
CPU time	22.91 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:49:00 PM PDT 24
Peak memory	204964 kb
Host	smart-58847ef2-d962-448f-9642-31a9582ccb1f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018974780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.4018974780
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.862410157
Short name	T304
Test name
Test status
Simulation time	25434296 ps
CPU time	2.08 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:48:39 PM PDT 24
Peak memory	203376 kb
Host	smart-4da5fb34-82ab-45ec-a647-a192d7a3e1d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=862410157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.862410157
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.1215181522
Short name	T872
Test name
Test status
Simulation time	67939836 ps
CPU time	2.39 seconds
Started	Apr 28 12:48:31 PM PDT 24
Finished	Apr 28 12:48:34 PM PDT 24
Peak memory	203296 kb
Host	smart-9df0857d-2bc4-440c-a391-d5d98cd1b923
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1215181522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1215181522
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2389274602
Short name	T657
Test name
Test status
Simulation time	9041930157 ps
CPU time	29.75 seconds
Started	Apr 28 12:48:31 PM PDT 24
Finished	Apr 28 12:49:02 PM PDT 24
Peak memory	203396 kb
Host	smart-f0b194f5-cb43-441b-a1c5-c167b37df120
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389274602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2389274602
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2645329430
Short name	T428
Test name
Test status
Simulation time	4389813277 ps
CPU time	29.43 seconds
Started	Apr 28 12:48:31 PM PDT 24
Finished	Apr 28 12:49:01 PM PDT 24
Peak memory	203556 kb
Host	smart-a2a3253b-8ab9-4f09-b3cb-252760347cb8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2645329430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2645329430
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2615331328
Short name	T599
Test name
Test status
Simulation time	23810211 ps
CPU time	2.17 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:48:39 PM PDT 24
Peak memory	203484 kb
Host	smart-398b9ff7-f9e6-4614-8add-95f8a96faa13
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615331328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2615331328
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.1474845032
Short name	T507
Test name
Test status
Simulation time	2055561273 ps
CPU time	48.46 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:49:26 PM PDT 24
Peak memory	206616 kb
Host	smart-51285ae8-14b6-497b-9c9a-4ea8f2768a6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1474845032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1474845032
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3252231411
Short name	T28
Test name
Test status
Simulation time	9887632998 ps
CPU time	229.72 seconds
Started	Apr 28 12:48:39 PM PDT 24
Finished	Apr 28 12:52:29 PM PDT 24
Peak memory	209140 kb
Host	smart-42400b2a-2585-4f89-8b46-9849bbe69033
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3252231411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3252231411
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2530352889
Short name	T875
Test name
Test status
Simulation time	559701387 ps
CPU time	188.09 seconds
Started	Apr 28 12:48:37 PM PDT 24
Finished	Apr 28 12:51:46 PM PDT 24
Peak memory	211656 kb
Host	smart-89202594-3a6f-4a32-af83-2c1d8867f4aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2530352889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2530352889
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.3237679186
Short name	T775
Test name
Test status
Simulation time	70542698 ps
CPU time	2.16 seconds
Started	Apr 28 12:48:39 PM PDT 24
Finished	Apr 28 12:48:42 PM PDT 24
Peak memory	203476 kb
Host	smart-00cebb3c-5cc1-46b5-ac1c-bf845f645aa4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3237679186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3237679186
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.158519776
Short name	T127
Test name
Test status
Simulation time	1170746816 ps
CPU time	26.69 seconds
Started	Apr 28 12:48:41 PM PDT 24
Finished	Apr 28 12:49:09 PM PDT 24
Peak memory	211592 kb
Host	smart-64187ad4-b356-4380-b950-138f20344976
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=158519776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.158519776
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2666934883
Short name	T810
Test name
Test status
Simulation time	153604890065 ps
CPU time	275.02 seconds
Started	Apr 28 12:48:41 PM PDT 24
Finished	Apr 28 12:53:17 PM PDT 24
Peak memory	211716 kb
Host	smart-bdd54340-7537-42c1-a274-73d060e647f0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2666934883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2666934883
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.369616043
Short name	T524
Test name
Test status
Simulation time	421899552 ps
CPU time	6.61 seconds
Started	Apr 28 12:48:40 PM PDT 24
Finished	Apr 28 12:48:48 PM PDT 24
Peak memory	203476 kb
Host	smart-c8f20e49-6bdf-4b5e-b901-87c638842e88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=369616043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.369616043
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.762873014
Short name	T853
Test name
Test status
Simulation time	151867071 ps
CPU time	13.87 seconds
Started	Apr 28 12:48:40 PM PDT 24
Finished	Apr 28 12:48:55 PM PDT 24
Peak memory	203400 kb
Host	smart-c89e1739-3393-4200-857e-43c69b0749d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=762873014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.762873014
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.285504805
Short name	T700
Test name
Test status
Simulation time	2402270408 ps
CPU time	13.82 seconds
Started	Apr 28 12:48:35 PM PDT 24
Finished	Apr 28 12:48:49 PM PDT 24
Peak memory	204548 kb
Host	smart-8468e5d3-eb76-4ad9-aa2e-898068528baa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285504805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.285504805
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.204488957
Short name	T714
Test name
Test status
Simulation time	25099794827 ps
CPU time	134.01 seconds
Started	Apr 28 12:48:38 PM PDT 24
Finished	Apr 28 12:50:52 PM PDT 24
Peak memory	204812 kb
Host	smart-2c308054-b980-45da-8b4f-0dc763e7505a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=204488957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.204488957
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.519845143
Short name	T62
Test name
Test status
Simulation time	5215347608 ps
CPU time	28.48 seconds
Started	Apr 28 12:48:37 PM PDT 24
Finished	Apr 28 12:49:07 PM PDT 24
Peak memory	204556 kb
Host	smart-4d93b28f-3dbd-418d-a579-8a9ab4ea8a82
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=519845143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.519845143
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3295150385
Short name	T500
Test name
Test status
Simulation time	117706666 ps
CPU time	18.51 seconds
Started	Apr 28 12:48:37 PM PDT 24
Finished	Apr 28 12:48:57 PM PDT 24
Peak memory	211680 kb
Host	smart-8dd59905-45d3-46ff-b609-ff1b6d993539
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295150385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3295150385
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.1900442912
Short name	T661
Test name
Test status
Simulation time	760086707 ps
CPU time	16.52 seconds
Started	Apr 28 12:48:41 PM PDT 24
Finished	Apr 28 12:48:58 PM PDT 24
Peak memory	204148 kb
Host	smart-d35d8fa3-6b40-4d52-a1b2-c8df8d888184
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1900442912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1900442912
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.3362322805
Short name	T638
Test name
Test status
Simulation time	31572672 ps
CPU time	2.2 seconds
Started	Apr 28 12:48:34 PM PDT 24
Finished	Apr 28 12:48:36 PM PDT 24
Peak memory	203440 kb
Host	smart-5e02e24a-a7f7-415d-9513-b04ff94b735a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3362322805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3362322805
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1993057834
Short name	T654
Test name
Test status
Simulation time	28700915794 ps
CPU time	43.14 seconds
Started	Apr 28 12:48:35 PM PDT 24
Finished	Apr 28 12:49:19 PM PDT 24
Peak memory	203432 kb
Host	smart-699cd6e8-5b5a-4967-8087-1f3f63c97331
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993057834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1993057834
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3188578798
Short name	T641
Test name
Test status
Simulation time	5043276003 ps
CPU time	27.96 seconds
Started	Apr 28 12:48:36 PM PDT 24
Finished	Apr 28 12:49:05 PM PDT 24
Peak memory	203552 kb
Host	smart-a08d8e17-84e1-41be-a57b-9ed823011ceb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3188578798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3188578798
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1370251660
Short name	T518
Test name
Test status
Simulation time	43243129 ps
CPU time	2.23 seconds
Started	Apr 28 12:48:35 PM PDT 24
Finished	Apr 28 12:48:38 PM PDT 24
Peak memory	203380 kb
Host	smart-be3c8ac7-7a7f-4767-a781-f0c724ce6fb7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370251660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1370251660
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.1055470381
Short name	T480
Test name
Test status
Simulation time	2117757913 ps
CPU time	72.99 seconds
Started	Apr 28 12:48:41 PM PDT 24
Finished	Apr 28 12:49:54 PM PDT 24
Peak memory	206756 kb
Host	smart-df7cf4e0-727c-48ac-8f4b-e001ae6cff99
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055470381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1055470381
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1376932305
Short name	T390
Test name
Test status
Simulation time	1097281530 ps
CPU time	33.54 seconds
Started	Apr 28 12:48:41 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	205008 kb
Host	smart-b887a825-335a-407c-9234-703cce78d107
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1376932305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1376932305
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2784317382
Short name	T26
Test name
Test status
Simulation time	3989595607 ps
CPU time	148.01 seconds
Started	Apr 28 12:48:40 PM PDT 24
Finished	Apr 28 12:51:09 PM PDT 24
Peak memory	206704 kb
Host	smart-31e99670-97d4-49c8-8887-3430e8afba58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2784317382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.2784317382
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4201766916
Short name	T616
Test name
Test status
Simulation time	9949671050 ps
CPU time	339.35 seconds
Started	Apr 28 12:48:40 PM PDT 24
Finished	Apr 28 12:54:20 PM PDT 24
Peak memory	224464 kb
Host	smart-f5d7f31a-06db-443f-bd4c-fb9f9a668c82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4201766916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.4201766916
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.429216319
Short name	T470
Test name
Test status
Simulation time	455670704 ps
CPU time	5.58 seconds
Started	Apr 28 12:48:40 PM PDT 24
Finished	Apr 28 12:48:46 PM PDT 24
Peak memory	211544 kb
Host	smart-d074e2d2-a97c-4f1d-872a-9e91e92d7727
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=429216319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.429216319
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3702602239
Short name	T213
Test name
Test status
Simulation time	6507234898 ps
CPU time	43.05 seconds
Started	Apr 28 12:48:46 PM PDT 24
Finished	Apr 28 12:49:29 PM PDT 24
Peak memory	205132 kb
Host	smart-a684c32e-9366-4397-97ab-c6e633ca828c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3702602239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3702602239
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2314924076
Short name	T726
Test name
Test status
Simulation time	69306884526 ps
CPU time	580.09 seconds
Started	Apr 28 12:48:46 PM PDT 24
Finished	Apr 28 12:58:26 PM PDT 24
Peak memory	211740 kb
Host	smart-898174e9-75e7-4cad-af0d-b9eef439454d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2314924076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2314924076
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3700115564
Short name	T889
Test name
Test status
Simulation time	663662682 ps
CPU time	24.66 seconds
Started	Apr 28 12:48:48 PM PDT 24
Finished	Apr 28 12:49:13 PM PDT 24
Peak memory	203736 kb
Host	smart-4ee9246e-73ea-419d-b986-f3094cb3610a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3700115564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3700115564
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.1570314153
Short name	T252
Test name
Test status
Simulation time	3664966400 ps
CPU time	33.43 seconds
Started	Apr 28 12:48:46 PM PDT 24
Finished	Apr 28 12:49:20 PM PDT 24
Peak memory	203512 kb
Host	smart-9fc0a82b-eb63-4e11-a883-c4296215da98
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1570314153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1570314153
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.535247275
Short name	T283
Test name
Test status
Simulation time	300866180 ps
CPU time	26.39 seconds
Started	Apr 28 12:48:43 PM PDT 24
Finished	Apr 28 12:49:10 PM PDT 24
Peak memory	204988 kb
Host	smart-3aba1583-e257-4ed9-b8c1-f8b39230677f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=535247275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.535247275
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1640769737
Short name	T142
Test name
Test status
Simulation time	63512474587 ps
CPU time	143.7 seconds
Started	Apr 28 12:48:41 PM PDT 24
Finished	Apr 28 12:51:06 PM PDT 24
Peak memory	205100 kb
Host	smart-ad4da034-e0a7-46f2-9727-bccb0a3bb9e7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640769737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1640769737
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3758805502
Short name	T798
Test name
Test status
Simulation time	28161585903 ps
CPU time	172.49 seconds
Started	Apr 28 12:48:47 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	204932 kb
Host	smart-2a8b4692-7371-4212-92c4-c494bd31cd64
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3758805502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3758805502
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.540780448
Short name	T408
Test name
Test status
Simulation time	553329571 ps
CPU time	23.51 seconds
Started	Apr 28 12:48:44 PM PDT 24
Finished	Apr 28 12:49:08 PM PDT 24
Peak memory	204880 kb
Host	smart-04f8f05f-04ad-45c0-a188-eda321a0b979
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540780448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.540780448
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.736618550
Short name	T227
Test name
Test status
Simulation time	512568200 ps
CPU time	11.61 seconds
Started	Apr 28 12:48:48 PM PDT 24
Finished	Apr 28 12:48:59 PM PDT 24
Peak memory	203388 kb
Host	smart-f6fb4a25-4735-4c11-a24b-a2705e003df4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=736618550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.736618550
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.2413220568
Short name	T345
Test name
Test status
Simulation time	72227579 ps
CPU time	2.27 seconds
Started	Apr 28 12:48:42 PM PDT 24
Finished	Apr 28 12:48:45 PM PDT 24
Peak memory	203332 kb
Host	smart-1e4e4f1a-4afc-4704-bf50-66a9fa6a19ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2413220568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2413220568
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3727896843
Short name	T692
Test name
Test status
Simulation time	14971386817 ps
CPU time	32.77 seconds
Started	Apr 28 12:48:41 PM PDT 24
Finished	Apr 28 12:49:14 PM PDT 24
Peak memory	203492 kb
Host	smart-0bef7a36-a65f-4d0d-8c7b-921342577f5f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727896843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3727896843
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2551602022
Short name	T862
Test name
Test status
Simulation time	22017474826 ps
CPU time	39.58 seconds
Started	Apr 28 12:48:43 PM PDT 24
Finished	Apr 28 12:49:23 PM PDT 24
Peak memory	203556 kb
Host	smart-742be024-a8ee-4e01-83f2-d0695ba03870
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2551602022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2551602022
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1101765032
Short name	T384
Test name
Test status
Simulation time	57152349 ps
CPU time	2.52 seconds
Started	Apr 28 12:48:42 PM PDT 24
Finished	Apr 28 12:48:45 PM PDT 24
Peak memory	203364 kb
Host	smart-74147241-83e8-412e-a5f6-d69d7dfb23d8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101765032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1101765032
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.951788044
Short name	T689
Test name
Test status
Simulation time	6837547370 ps
CPU time	192.14 seconds
Started	Apr 28 12:48:50 PM PDT 24
Finished	Apr 28 12:52:02 PM PDT 24
Peak memory	210560 kb
Host	smart-cf16c119-6924-4121-bd6d-0ca9162cf4dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=951788044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.951788044
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.321306932
Short name	T873
Test name
Test status
Simulation time	879458019 ps
CPU time	120.39 seconds
Started	Apr 28 12:48:48 PM PDT 24
Finished	Apr 28 12:50:49 PM PDT 24
Peak memory	207752 kb
Host	smart-e0a06c09-9547-4bad-8c5d-d8acc4850751
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=321306932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.321306932
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2827214970
Short name	T39
Test name
Test status
Simulation time	11226996223 ps
CPU time	557.15 seconds
Started	Apr 28 12:48:46 PM PDT 24
Finished	Apr 28 12:58:03 PM PDT 24
Peak memory	211724 kb
Host	smart-971c5641-73c5-49d2-9fad-697f56e314a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2827214970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2827214970
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3326747308
Short name	T594
Test name
Test status
Simulation time	704583008 ps
CPU time	213.81 seconds
Started	Apr 28 12:48:47 PM PDT 24
Finished	Apr 28 12:52:21 PM PDT 24
Peak memory	211348 kb
Host	smart-67194183-1a13-4622-9f06-e44ebc5bf0da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3326747308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.3326747308
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3912052708
Short name	T563
Test name
Test status
Simulation time	304420567 ps
CPU time	12.53 seconds
Started	Apr 28 12:48:47 PM PDT 24
Finished	Apr 28 12:49:00 PM PDT 24
Peak memory	204976 kb
Host	smart-1e27e896-3f85-47ef-9c2d-32fedb0b5af9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3912052708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3912052708
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.2063646175
Short name	T707
Test name
Test status
Simulation time	663086415 ps
CPU time	9.92 seconds
Started	Apr 28 12:48:52 PM PDT 24
Finished	Apr 28 12:49:02 PM PDT 24
Peak memory	204080 kb
Host	smart-1ca7e5ea-0b63-4111-8148-dcc6ed4ed862
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2063646175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2063646175
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1382004163
Short name	T67
Test name
Test status
Simulation time	175139597882 ps
CPU time	557.09 seconds
Started	Apr 28 12:48:53 PM PDT 24
Finished	Apr 28 12:58:10 PM PDT 24
Peak memory	205988 kb
Host	smart-f5c7448b-85d9-40b0-a98c-b305f3669fc4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1382004163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1382004163
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3440638417
Short name	T870
Test name
Test status
Simulation time	2328141126 ps
CPU time	17.03 seconds
Started	Apr 28 12:48:54 PM PDT 24
Finished	Apr 28 12:49:11 PM PDT 24
Peak memory	203740 kb
Host	smart-398a9ded-c005-4fce-bfd1-d83a9f821366
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440638417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3440638417
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.935139514
Short name	T659
Test name
Test status
Simulation time	152382569 ps
CPU time	5.38 seconds
Started	Apr 28 12:48:54 PM PDT 24
Finished	Apr 28 12:49:00 PM PDT 24
Peak memory	203476 kb
Host	smart-1b98c271-64df-42f7-9f65-1f7c3aae3608
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=935139514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.935139514
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.1839629255
Short name	T217
Test name
Test status
Simulation time	65140351 ps
CPU time	6.15 seconds
Started	Apr 28 12:48:52 PM PDT 24
Finished	Apr 28 12:48:59 PM PDT 24
Peak memory	204552 kb
Host	smart-e69f99b6-7940-4e4e-9756-6199109cd52c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1839629255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1839629255
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2363120289
Short name	T896
Test name
Test status
Simulation time	23850486889 ps
CPU time	122.7 seconds
Started	Apr 28 12:48:52 PM PDT 24
Finished	Apr 28 12:50:55 PM PDT 24
Peak memory	211648 kb
Host	smart-c3cda7e3-49d3-4cca-95c3-916ee6fdc3ae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363120289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2363120289
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3193947932
Short name	T762
Test name
Test status
Simulation time	13441751099 ps
CPU time	49.12 seconds
Started	Apr 28 12:48:53 PM PDT 24
Finished	Apr 28 12:49:42 PM PDT 24
Peak memory	204784 kb
Host	smart-93ca9704-798e-472b-a314-acbf9b40e474
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3193947932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3193947932
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.160137736
Short name	T178
Test name
Test status
Simulation time	397501980 ps
CPU time	9.29 seconds
Started	Apr 28 12:48:53 PM PDT 24
Finished	Apr 28 12:49:02 PM PDT 24
Peak memory	204720 kb
Host	smart-7d1bdd15-21e9-4a69-bb7b-d41059bdfb4e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160137736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.160137736
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.3798333194
Short name	T296
Test name
Test status
Simulation time	34656654 ps
CPU time	2.83 seconds
Started	Apr 28 12:48:51 PM PDT 24
Finished	Apr 28 12:48:55 PM PDT 24
Peak memory	203588 kb
Host	smart-ec7c7b63-daf4-4b10-867d-151e6889947a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3798333194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3798333194
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.2050933384
Short name	T319
Test name
Test status
Simulation time	191164061 ps
CPU time	3.64 seconds
Started	Apr 28 12:48:53 PM PDT 24
Finished	Apr 28 12:48:57 PM PDT 24
Peak memory	203468 kb
Host	smart-6c70c95c-44c5-4b98-a958-cc45691d250b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2050933384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2050933384
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.627765803
Short name	T482
Test name
Test status
Simulation time	5583298702 ps
CPU time	28.05 seconds
Started	Apr 28 12:49:21 PM PDT 24
Finished	Apr 28 12:49:49 PM PDT 24
Peak memory	203416 kb
Host	smart-5bb3a8f3-9c0f-43fa-90c9-0458cf21e0c4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=627765803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.627765803
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.972500821
Short name	T675
Test name
Test status
Simulation time	7943526050 ps
CPU time	37.26 seconds
Started	Apr 28 12:48:53 PM PDT 24
Finished	Apr 28 12:49:31 PM PDT 24
Peak memory	203532 kb
Host	smart-9d638fd8-fa87-4602-b295-fb65df62abfd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=972500821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.972500821
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2731462806
Short name	T269
Test name
Test status
Simulation time	71537634 ps
CPU time	2.65 seconds
Started	Apr 28 12:48:53 PM PDT 24
Finished	Apr 28 12:48:57 PM PDT 24
Peak memory	203396 kb
Host	smart-c24e88e4-bbf4-4e90-94fb-81c9889fed36
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731462806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2731462806
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.2414955245
Short name	T114
Test name
Test status
Simulation time	8339071104 ps
CPU time	271.24 seconds
Started	Apr 28 12:48:52 PM PDT 24
Finished	Apr 28 12:53:24 PM PDT 24
Peak memory	211740 kb
Host	smart-272a4c89-29a9-44fc-beb0-9d773473d452
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2414955245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2414955245
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1821422929
Short name	T95
Test name
Test status
Simulation time	389450176 ps
CPU time	12.51 seconds
Started	Apr 28 12:48:51 PM PDT 24
Finished	Apr 28 12:49:04 PM PDT 24
Peak memory	203440 kb
Host	smart-3bd1ebba-9801-4970-905a-a7cb7b42df13
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1821422929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1821422929
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.4091099079
Short name	T301
Test name
Test status
Simulation time	3051039188 ps
CPU time	120.79 seconds
Started	Apr 28 12:48:52 PM PDT 24
Finished	Apr 28 12:50:53 PM PDT 24
Peak memory	206624 kb
Host	smart-aa4f2b3c-6e02-4e0e-970e-8d9c44fdcc70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091099079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.4091099079
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.18007617
Short name	T117
Test name
Test status
Simulation time	54413304 ps
CPU time	14.49 seconds
Started	Apr 28 12:48:52 PM PDT 24
Finished	Apr 28 12:49:07 PM PDT 24
Peak memory	204732 kb
Host	smart-c033fdf4-818d-4792-b695-edc380ff914e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=18007617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rese t_error.18007617
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.947298957
Short name	T534
Test name
Test status
Simulation time	284625028 ps
CPU time	7.95 seconds
Started	Apr 28 12:48:51 PM PDT 24
Finished	Apr 28 12:48:59 PM PDT 24
Peak memory	211520 kb
Host	smart-a59fb0da-9498-4e3a-bcf8-27a396c103e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=947298957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.947298957
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2830208157
Short name	T697
Test name
Test status
Simulation time	215299701 ps
CPU time	10.01 seconds
Started	Apr 28 12:48:55 PM PDT 24
Finished	Apr 28 12:49:06 PM PDT 24
Peak memory	211632 kb
Host	smart-d9b80bab-884d-4c67-b0f9-d652f1503c0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2830208157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2830208157
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4146394308
Short name	T658
Test name
Test status
Simulation time	8026411963 ps
CPU time	36.74 seconds
Started	Apr 28 12:48:55 PM PDT 24
Finished	Apr 28 12:49:33 PM PDT 24
Peak memory	204012 kb
Host	smart-5ba2e096-885c-4dcd-9d58-3d80f3055234
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4146394308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.4146394308
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3542221122
Short name	T819
Test name
Test status
Simulation time	682505215 ps
CPU time	11.26 seconds
Started	Apr 28 12:48:57 PM PDT 24
Finished	Apr 28 12:49:09 PM PDT 24
Peak memory	203648 kb
Host	smart-7b1dcf03-4a4b-4301-b0a2-01afdf768605
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3542221122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3542221122
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.18993479
Short name	T37
Test name
Test status
Simulation time	790387042 ps
CPU time	14.31 seconds
Started	Apr 28 12:48:57 PM PDT 24
Finished	Apr 28 12:49:12 PM PDT 24
Peak memory	203448 kb
Host	smart-b32521c9-ab5f-4637-a40c-66d2f0168d31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=18993479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.18993479
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.2930508132
Short name	T201
Test name
Test status
Simulation time	1118862355 ps
CPU time	35.75 seconds
Started	Apr 28 12:49:00 PM PDT 24
Finished	Apr 28 12:49:36 PM PDT 24
Peak memory	204468 kb
Host	smart-efff5888-fead-4dd7-9969-84bb787be949
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2930508132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2930508132
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.372161012
Short name	T256
Test name
Test status
Simulation time	61992109919 ps
CPU time	142.98 seconds
Started	Apr 28 12:48:55 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	204832 kb
Host	smart-79fdeb83-9b58-4ac5-89ba-1bf60338e028
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=372161012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.372161012
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2624214735
Short name	T694
Test name
Test status
Simulation time	11580543554 ps
CPU time	104.13 seconds
Started	Apr 28 12:49:00 PM PDT 24
Finished	Apr 28 12:50:44 PM PDT 24
Peak memory	205032 kb
Host	smart-8b2a6ced-670d-4401-9dfc-a43263373f27
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2624214735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2624214735
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1547013344
Short name	T833
Test name
Test status
Simulation time	625668358 ps
CPU time	13.11 seconds
Started	Apr 28 12:48:59 PM PDT 24
Finished	Apr 28 12:49:13 PM PDT 24
Peak memory	204472 kb
Host	smart-265b7adf-3c6f-4845-9f04-63bfdd0a1f12
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547013344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1547013344
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.3053529154
Short name	T193
Test name
Test status
Simulation time	665037339 ps
CPU time	9.04 seconds
Started	Apr 28 12:48:59 PM PDT 24
Finished	Apr 28 12:49:09 PM PDT 24
Peak memory	203832 kb
Host	smart-36e092b4-3f80-4950-9ee9-5d72b59a8b38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3053529154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3053529154
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.1480153704
Short name	T286
Test name
Test status
Simulation time	35006761 ps
CPU time	2.4 seconds
Started	Apr 28 12:48:56 PM PDT 24
Finished	Apr 28 12:48:59 PM PDT 24
Peak memory	203436 kb
Host	smart-eb7f7e5a-e3ca-49c7-aa3b-374f63dd6284
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1480153704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1480153704
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2822036287
Short name	T321
Test name
Test status
Simulation time	33427290949 ps
CPU time	46.76 seconds
Started	Apr 28 12:48:56 PM PDT 24
Finished	Apr 28 12:49:43 PM PDT 24
Peak memory	203412 kb
Host	smart-5cb41f8b-91c3-42f9-a9c8-8365659249c6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822036287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2822036287
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2742011301
Short name	T532
Test name
Test status
Simulation time	2486060400 ps
CPU time	22.58 seconds
Started	Apr 28 12:48:56 PM PDT 24
Finished	Apr 28 12:49:19 PM PDT 24
Peak memory	203424 kb
Host	smart-75231fe6-c217-4103-8f27-c6d97d999848
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2742011301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2742011301
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.690684423
Short name	T469
Test name
Test status
Simulation time	30693240 ps
CPU time	2.13 seconds
Started	Apr 28 12:48:55 PM PDT 24
Finished	Apr 28 12:48:57 PM PDT 24
Peak memory	203340 kb
Host	smart-192fd608-9c00-4d18-925c-0176e91c3c66
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690684423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.690684423
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.3721859797
Short name	T330
Test name
Test status
Simulation time	619089514 ps
CPU time	61.71 seconds
Started	Apr 28 12:48:57 PM PDT 24
Finished	Apr 28 12:49:59 PM PDT 24
Peak memory	211540 kb
Host	smart-952970f4-a3c9-4cca-a3ea-4559d887c015
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3721859797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3721859797
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1265619127
Short name	T560
Test name
Test status
Simulation time	854950953 ps
CPU time	79.38 seconds
Started	Apr 28 12:48:55 PM PDT 24
Finished	Apr 28 12:50:15 PM PDT 24
Peak memory	206636 kb
Host	smart-be742609-635c-4dfa-9391-658f6b96e7bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1265619127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1265619127
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1965270769
Short name	T22
Test name
Test status
Simulation time	3749003391 ps
CPU time	200.32 seconds
Started	Apr 28 12:48:56 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	210912 kb
Host	smart-fcb8e35d-cc95-4cd1-99ee-6883e3f6e75e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1965270769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1965270769
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2303248475
Short name	T536
Test name
Test status
Simulation time	490875399 ps
CPU time	112.94 seconds
Started	Apr 28 12:48:57 PM PDT 24
Finished	Apr 28 12:50:51 PM PDT 24
Peak memory	210456 kb
Host	smart-0b1da311-a04b-46d4-838e-6d5bdd807cac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2303248475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.2303248475
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1729905075
Short name	T147
Test name
Test status
Simulation time	2700397479 ps
CPU time	28.47 seconds
Started	Apr 28 12:48:56 PM PDT 24
Finished	Apr 28 12:49:25 PM PDT 24
Peak memory	204868 kb
Host	smart-73dc863c-3505-40a8-8461-951c959a37a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1729905075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1729905075
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.4212207654
Short name	T546
Test name
Test status
Simulation time	2503366949 ps
CPU time	41 seconds
Started	Apr 28 12:49:09 PM PDT 24
Finished	Apr 28 12:49:51 PM PDT 24
Peak memory	206312 kb
Host	smart-670c6589-df90-480f-b178-4990e1592071
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4212207654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4212207654
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1651774473
Short name	T831
Test name
Test status
Simulation time	70530745 ps
CPU time	3.4 seconds
Started	Apr 28 12:49:02 PM PDT 24
Finished	Apr 28 12:49:06 PM PDT 24
Peak memory	203340 kb
Host	smart-5494573d-010a-4c31-84dd-9b7b62d2bc7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1651774473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1651774473
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.419908091
Short name	T143
Test name
Test status
Simulation time	188260414 ps
CPU time	13.62 seconds
Started	Apr 28 12:49:01 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	203444 kb
Host	smart-4e8c9f29-a057-4329-977e-7abf41d6b01e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=419908091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.419908091
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.1680525015
Short name	T370
Test name
Test status
Simulation time	104347348 ps
CPU time	11.89 seconds
Started	Apr 28 12:49:01 PM PDT 24
Finished	Apr 28 12:49:13 PM PDT 24
Peak memory	211672 kb
Host	smart-9198ad17-063e-4b50-a038-170376ff46b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680525015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1680525015
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1824089481
Short name	T519
Test name
Test status
Simulation time	22779151245 ps
CPU time	98.21 seconds
Started	Apr 28 12:49:02 PM PDT 24
Finished	Apr 28 12:50:41 PM PDT 24
Peak memory	205044 kb
Host	smart-0ca18f52-1495-430e-9025-ccff3a755a55
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824089481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1824089481
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.612372578
Short name	T64
Test name
Test status
Simulation time	9304175535 ps
CPU time	63.13 seconds
Started	Apr 28 12:49:01 PM PDT 24
Finished	Apr 28 12:50:04 PM PDT 24
Peak memory	204960 kb
Host	smart-8ebd3975-5687-42e6-858b-25e57d1d1bcb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=612372578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.612372578
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3714031768
Short name	T882
Test name
Test status
Simulation time	23025001 ps
CPU time	2.13 seconds
Started	Apr 28 12:49:03 PM PDT 24
Finished	Apr 28 12:49:06 PM PDT 24
Peak memory	203560 kb
Host	smart-b76ac3ff-1e29-46b4-bf0b-3425b6c73e99
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714031768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3714031768
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.958247294
Short name	T455
Test name
Test status
Simulation time	187100314 ps
CPU time	15.39 seconds
Started	Apr 28 12:49:04 PM PDT 24
Finished	Apr 28 12:49:20 PM PDT 24
Peak memory	204040 kb
Host	smart-5650390a-8b2d-40a1-90a5-dd349213e9a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=958247294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.958247294
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.1456790202
Short name	T687
Test name
Test status
Simulation time	42376684 ps
CPU time	2.61 seconds
Started	Apr 28 12:49:02 PM PDT 24
Finished	Apr 28 12:49:05 PM PDT 24
Peak memory	203440 kb
Host	smart-d30fbb90-fbd6-4512-bcb0-c954e199701f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456790202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1456790202
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1983483030
Short name	T564
Test name
Test status
Simulation time	11978331090 ps
CPU time	34.21 seconds
Started	Apr 28 12:49:02 PM PDT 24
Finished	Apr 28 12:49:36 PM PDT 24
Peak memory	203520 kb
Host	smart-67ec30bd-7862-4bac-a2f0-d26a20817f9a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983483030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1983483030
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1887507786
Short name	T698
Test name
Test status
Simulation time	15557491407 ps
CPU time	40.53 seconds
Started	Apr 28 12:49:05 PM PDT 24
Finished	Apr 28 12:49:45 PM PDT 24
Peak memory	203460 kb
Host	smart-a3273976-514c-4136-ba94-11a6e70c2a03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1887507786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1887507786
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2486853973
Short name	T747
Test name
Test status
Simulation time	63411247 ps
CPU time	2.1 seconds
Started	Apr 28 12:49:02 PM PDT 24
Finished	Apr 28 12:49:05 PM PDT 24
Peak memory	203396 kb
Host	smart-67d8fad3-8c7a-49fd-a55a-e2a9cae88fcf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486853973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2486853973
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.3399866862
Short name	T701
Test name
Test status
Simulation time	1483001952 ps
CPU time	49.58 seconds
Started	Apr 28 12:49:02 PM PDT 24
Finished	Apr 28 12:49:52 PM PDT 24
Peak memory	206496 kb
Host	smart-f937e910-5323-402c-a3ee-e963e912c5ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3399866862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3399866862
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.870703109
Short name	T302
Test name
Test status
Simulation time	5085726848 ps
CPU time	187.77 seconds
Started	Apr 28 12:49:05 PM PDT 24
Finished	Apr 28 12:52:13 PM PDT 24
Peak memory	210152 kb
Host	smart-fbd17062-20fb-44aa-9d6b-1eb64092733f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=870703109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.870703109
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1199736568
Short name	T822
Test name
Test status
Simulation time	539825986 ps
CPU time	144.61 seconds
Started	Apr 28 12:49:04 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	208184 kb
Host	smart-17eb832b-e36e-4a9d-96fb-de81a1756582
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1199736568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1199736568
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.4055528882
Short name	T232
Test name
Test status
Simulation time	16278886736 ps
CPU time	412.97 seconds
Started	Apr 28 12:49:07 PM PDT 24
Finished	Apr 28 12:56:00 PM PDT 24
Peak memory	223564 kb
Host	smart-238695e3-3039-4649-af60-e52b335bca07
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4055528882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.4055528882
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3794396796
Short name	T317
Test name
Test status
Simulation time	325467731 ps
CPU time	3.96 seconds
Started	Apr 28 12:49:01 PM PDT 24
Finished	Apr 28 12:49:05 PM PDT 24
Peak memory	211700 kb
Host	smart-3b893200-15d7-42f3-8242-97dcf20ba918
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3794396796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3794396796
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3489007573
Short name	T113
Test name
Test status
Simulation time	117602220308 ps
CPU time	367.92 seconds
Started	Apr 28 12:49:08 PM PDT 24
Finished	Apr 28 12:55:17 PM PDT 24
Peak memory	206480 kb
Host	smart-4a220462-ac29-4f41-b8a2-e63c45cd790d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3489007573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.3489007573
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2861340299
Short name	T729
Test name
Test status
Simulation time	147495664 ps
CPU time	13.77 seconds
Started	Apr 28 12:49:08 PM PDT 24
Finished	Apr 28 12:49:22 PM PDT 24
Peak memory	203592 kb
Host	smart-c6b2675d-8f9b-4f1a-92d0-d32c37916651
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2861340299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2861340299
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.4216591627
Short name	T254
Test name
Test status
Simulation time	577610653 ps
CPU time	17.2 seconds
Started	Apr 28 12:49:06 PM PDT 24
Finished	Apr 28 12:49:23 PM PDT 24
Peak memory	203472 kb
Host	smart-5935e9a1-41c9-4087-b59d-cb8a162c2e74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4216591627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4216591627
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.355398082
Short name	T399
Test name
Test status
Simulation time	76527844 ps
CPU time	8.17 seconds
Started	Apr 28 12:49:08 PM PDT 24
Finished	Apr 28 12:49:17 PM PDT 24
Peak memory	204552 kb
Host	smart-0343e131-bcfd-42bf-af65-62ffa0ae7469
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=355398082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.355398082
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2678181500
Short name	T285
Test name
Test status
Simulation time	25696007179 ps
CPU time	125.88 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	204832 kb
Host	smart-a0f9eada-5ce7-4348-a3eb-5c63f67840a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678181500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2678181500
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2998932086
Short name	T450
Test name
Test status
Simulation time	17416139201 ps
CPU time	103.49 seconds
Started	Apr 28 12:49:09 PM PDT 24
Finished	Apr 28 12:50:53 PM PDT 24
Peak memory	204724 kb
Host	smart-92e7d179-6d9a-4557-8aea-3a62d4d3b672
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2998932086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2998932086
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1487226379
Short name	T185
Test name
Test status
Simulation time	123831683 ps
CPU time	14.94 seconds
Started	Apr 28 12:49:11 PM PDT 24
Finished	Apr 28 12:49:26 PM PDT 24
Peak memory	204596 kb
Host	smart-fdb7d3a3-223d-4b3d-9208-6b6d4b02eb38
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487226379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1487226379
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.22851636
Short name	T367
Test name
Test status
Simulation time	499778404 ps
CPU time	20.35 seconds
Started	Apr 28 12:49:06 PM PDT 24
Finished	Apr 28 12:49:27 PM PDT 24
Peak memory	204092 kb
Host	smart-c8065fa7-f719-480c-abe9-802d8955d68e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=22851636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.22851636
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.1029783164
Short name	T162
Test name
Test status
Simulation time	138555353 ps
CPU time	3.6 seconds
Started	Apr 28 12:49:08 PM PDT 24
Finished	Apr 28 12:49:13 PM PDT 24
Peak memory	203492 kb
Host	smart-968e3d82-9648-4e55-828b-2e428ac4ff40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1029783164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1029783164
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3462196219
Short name	T619
Test name
Test status
Simulation time	4383767850 ps
CPU time	25.38 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:49:37 PM PDT 24
Peak memory	203500 kb
Host	smart-a1b2ccc7-a4a8-42b7-a93b-e30eb2363500
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462196219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3462196219
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2136429291
Short name	T604
Test name
Test status
Simulation time	3745492368 ps
CPU time	32.76 seconds
Started	Apr 28 12:49:11 PM PDT 24
Finished	Apr 28 12:49:44 PM PDT 24
Peak memory	203364 kb
Host	smart-de12c634-90d8-4663-89ae-619fd79cde15
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2136429291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2136429291
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3290355431
Short name	T464
Test name
Test status
Simulation time	30165021 ps
CPU time	2.24 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	203484 kb
Host	smart-d194a2ba-202f-4387-9180-003554dbe5a7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290355431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3290355431
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.2763921473
Short name	T181
Test name
Test status
Simulation time	877426954 ps
CPU time	92.95 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:50:46 PM PDT 24
Peak memory	206952 kb
Host	smart-83e63259-4f1f-4d67-bc2e-c95f9bd1e6e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2763921473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2763921473
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2452781144
Short name	T432
Test name
Test status
Simulation time	12828002898 ps
CPU time	203.08 seconds
Started	Apr 28 12:49:15 PM PDT 24
Finished	Apr 28 12:52:39 PM PDT 24
Peak memory	209076 kb
Host	smart-a5893737-9811-4f7c-9ac5-48bb4cbe5499
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2452781144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2452781144
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3661686959
Short name	T713
Test name
Test status
Simulation time	3722045616 ps
CPU time	378.1 seconds
Started	Apr 28 12:49:08 PM PDT 24
Finished	Apr 28 12:55:26 PM PDT 24
Peak memory	210172 kb
Host	smart-3dee1c59-80ba-4203-b62a-a029aa9fee29
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3661686959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3661686959
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1103242823
Short name	T815
Test name
Test status
Simulation time	1824886412 ps
CPU time	53.64 seconds
Started	Apr 28 12:49:14 PM PDT 24
Finished	Apr 28 12:50:08 PM PDT 24
Peak memory	207340 kb
Host	smart-8903dadf-0c34-43fd-a099-9ebf6c4579df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1103242823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.1103242823
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3150277701
Short name	T671
Test name
Test status
Simulation time	246077780 ps
CPU time	5.76 seconds
Started	Apr 28 12:49:09 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	204592 kb
Host	smart-65030c45-76f3-46e6-8203-1ea6fdf1f1af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3150277701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3150277701
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.247596642
Short name	T793
Test name
Test status
Simulation time	374933591 ps
CPU time	33.02 seconds
Started	Apr 28 12:49:15 PM PDT 24
Finished	Apr 28 12:49:48 PM PDT 24
Peak memory	211684 kb
Host	smart-2a3d28f0-a195-48ca-adda-039db8ac3185
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=247596642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.247596642
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1486301096
Short name	T144
Test name
Test status
Simulation time	26121789227 ps
CPU time	224.73 seconds
Started	Apr 28 12:49:14 PM PDT 24
Finished	Apr 28 12:52:59 PM PDT 24
Peak memory	205900 kb
Host	smart-09fec30f-f984-49e3-954e-2a0bb98eeb4f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1486301096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1486301096
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.4244106301
Short name	T629
Test name
Test status
Simulation time	50622569 ps
CPU time	2.61 seconds
Started	Apr 28 12:49:13 PM PDT 24
Finished	Apr 28 12:49:16 PM PDT 24
Peak memory	203432 kb
Host	smart-5288f512-a42a-46f6-934c-3a5b7e0343f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4244106301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.4244106301
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.1980507684
Short name	T622
Test name
Test status
Simulation time	2535511818 ps
CPU time	14.19 seconds
Started	Apr 28 12:49:13 PM PDT 24
Finished	Apr 28 12:49:28 PM PDT 24
Peak memory	203432 kb
Host	smart-b46cbdf1-020b-4d1e-bc4e-eca9d9ced72e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1980507684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1980507684
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.537916399
Short name	T794
Test name
Test status
Simulation time	43172413 ps
CPU time	2.54 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	203468 kb
Host	smart-b81df57c-7552-4037-971a-7250739eb745
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=537916399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.537916399
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.630167891
Short name	T837
Test name
Test status
Simulation time	19893994554 ps
CPU time	103.3 seconds
Started	Apr 28 12:49:11 PM PDT 24
Finished	Apr 28 12:50:54 PM PDT 24
Peak memory	211724 kb
Host	smart-9b611a27-3b41-4d68-83e6-e046850c8bda
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=630167891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.630167891
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3844170835
Short name	T566
Test name
Test status
Simulation time	198614839086 ps
CPU time	405.94 seconds
Started	Apr 28 12:49:13 PM PDT 24
Finished	Apr 28 12:55:59 PM PDT 24
Peak memory	204740 kb
Host	smart-20aa4cdf-9e55-49d9-922b-808d1775c955
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3844170835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3844170835
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2344063039
Short name	T617
Test name
Test status
Simulation time	91414934 ps
CPU time	13.89 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:49:27 PM PDT 24
Peak memory	204612 kb
Host	smart-3afe832a-ffe8-45ba-b14e-2cc8a3c1ed42
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344063039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2344063039
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.862495933
Short name	T36
Test name
Test status
Simulation time	9244387151 ps
CPU time	35.33 seconds
Started	Apr 28 12:49:15 PM PDT 24
Finished	Apr 28 12:49:51 PM PDT 24
Peak memory	211640 kb
Host	smart-d120c0da-2c87-4627-ab6f-65d27127476a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=862495933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.862495933
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.670753597
Short name	T6
Test name
Test status
Simulation time	148654979 ps
CPU time	3.68 seconds
Started	Apr 28 12:49:11 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	203372 kb
Host	smart-2326c487-f8d4-4b4d-a740-191ba6bfb958
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=670753597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.670753597
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3289414477
Short name	T344
Test name
Test status
Simulation time	7925087852 ps
CPU time	29.53 seconds
Started	Apr 28 12:49:13 PM PDT 24
Finished	Apr 28 12:49:43 PM PDT 24
Peak memory	203364 kb
Host	smart-348bb2fb-f4d0-4f2b-9a71-767b11e9b2a8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289414477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3289414477
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3027391756
Short name	T356
Test name
Test status
Simulation time	7242905999 ps
CPU time	30.87 seconds
Started	Apr 28 12:49:13 PM PDT 24
Finished	Apr 28 12:49:44 PM PDT 24
Peak memory	203436 kb
Host	smart-abdece1c-958c-46d5-ba2a-3d86abb40e8b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3027391756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3027391756
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3063739924
Short name	T643
Test name
Test status
Simulation time	131054068 ps
CPU time	2.31 seconds
Started	Apr 28 12:49:12 PM PDT 24
Finished	Apr 28 12:49:15 PM PDT 24
Peak memory	203440 kb
Host	smart-72256b60-db72-4f7b-a063-80506bdc4d0a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063739924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3063739924
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.2459593001
Short name	T767
Test name
Test status
Simulation time	1698144231 ps
CPU time	25.48 seconds
Started	Apr 28 12:49:19 PM PDT 24
Finished	Apr 28 12:49:45 PM PDT 24
Peak memory	211592 kb
Host	smart-b2a50340-aaf6-4c00-9a0e-e8da5bd825a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2459593001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2459593001
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.309031426
Short name	T27
Test name
Test status
Simulation time	3474372715 ps
CPU time	53.84 seconds
Started	Apr 28 12:49:18 PM PDT 24
Finished	Apr 28 12:50:12 PM PDT 24
Peak memory	205152 kb
Host	smart-a46866d2-ce93-49f0-8748-3c5aee7ce5d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=309031426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.309031426
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1302770411
Short name	T681
Test name
Test status
Simulation time	372046467 ps
CPU time	127.63 seconds
Started	Apr 28 12:49:16 PM PDT 24
Finished	Apr 28 12:51:24 PM PDT 24
Peak memory	209948 kb
Host	smart-a2373710-938a-44d3-9249-e9008e2cd423
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1302770411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1302770411
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1374368744
Short name	T312
Test name
Test status
Simulation time	1537674090 ps
CPU time	25.92 seconds
Started	Apr 28 12:49:15 PM PDT 24
Finished	Apr 28 12:49:41 PM PDT 24
Peak memory	205128 kb
Host	smart-92d6e2f1-52fa-4bcd-9fea-b3cbc0ac0d9f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1374368744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1374368744
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.365882813
Short name	T554
Test name
Test status
Simulation time	1527973592 ps
CPU time	35.22 seconds
Started	Apr 28 12:49:17 PM PDT 24
Finished	Apr 28 12:49:52 PM PDT 24
Peak memory	204824 kb
Host	smart-f92e8f9e-e9f0-479b-ab10-0d56e2e299f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=365882813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.365882813
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2308143916
Short name	T104
Test name
Test status
Simulation time	39629516500 ps
CPU time	175.28 seconds
Started	Apr 28 12:49:18 PM PDT 24
Finished	Apr 28 12:52:14 PM PDT 24
Peak memory	205904 kb
Host	smart-5d76be1f-896b-46b3-a46d-adc896dcf41d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2308143916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2308143916
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3823354972
Short name	T849
Test name
Test status
Simulation time	512985197 ps
CPU time	15.07 seconds
Started	Apr 28 12:49:22 PM PDT 24
Finished	Apr 28 12:49:37 PM PDT 24
Peak memory	203772 kb
Host	smart-7d7a58d2-db22-465b-90f5-49e2a1ccb2df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3823354972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3823354972
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.3191371869
Short name	T420
Test name
Test status
Simulation time	932827442 ps
CPU time	24.86 seconds
Started	Apr 28 12:49:16 PM PDT 24
Finished	Apr 28 12:49:41 PM PDT 24
Peak memory	203492 kb
Host	smart-f0f4ffad-cfec-4389-a66e-94b6531762c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3191371869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3191371869
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.3180127482
Short name	T531
Test name
Test status
Simulation time	227088516 ps
CPU time	29.7 seconds
Started	Apr 28 12:49:16 PM PDT 24
Finished	Apr 28 12:49:47 PM PDT 24
Peak memory	211576 kb
Host	smart-f41b95ed-127d-4138-9ad6-e46d9f8f8ccc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180127482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3180127482
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1304343041
Short name	T590
Test name
Test status
Simulation time	11168408906 ps
CPU time	45.32 seconds
Started	Apr 28 12:49:20 PM PDT 24
Finished	Apr 28 12:50:06 PM PDT 24
Peak memory	204608 kb
Host	smart-7a15855a-dc1e-47cd-8609-f4b5d3f4a8c5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304343041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1304343041
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.311147218
Short name	T720
Test name
Test status
Simulation time	144490236909 ps
CPU time	319.49 seconds
Started	Apr 28 12:49:19 PM PDT 24
Finished	Apr 28 12:54:39 PM PDT 24
Peak memory	211616 kb
Host	smart-45855084-b0db-4101-aad2-4238b9270df4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=311147218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.311147218
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2896873706
Short name	T696
Test name
Test status
Simulation time	14037422 ps
CPU time	1.77 seconds
Started	Apr 28 12:49:16 PM PDT 24
Finished	Apr 28 12:49:18 PM PDT 24
Peak memory	203404 kb
Host	smart-e0bf8c4e-6b19-49b0-8d15-5f555537a896
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896873706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2896873706
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.629907739
Short name	T662
Test name
Test status
Simulation time	871265205 ps
CPU time	19.88 seconds
Started	Apr 28 12:49:16 PM PDT 24
Finished	Apr 28 12:49:37 PM PDT 24
Peak memory	211512 kb
Host	smart-d61e6dc4-cb57-4a9d-a33c-d2b2495b78ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=629907739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.629907739
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.1461733629
Short name	T881
Test name
Test status
Simulation time	135153573 ps
CPU time	2.97 seconds
Started	Apr 28 12:49:19 PM PDT 24
Finished	Apr 28 12:49:23 PM PDT 24
Peak memory	203320 kb
Host	smart-65f3a472-3ffb-4df1-9386-6d283e2d9576
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1461733629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1461733629
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.752650378
Short name	T366
Test name
Test status
Simulation time	9277463678 ps
CPU time	31.37 seconds
Started	Apr 28 12:49:17 PM PDT 24
Finished	Apr 28 12:49:49 PM PDT 24
Peak memory	203548 kb
Host	smart-e54b524d-6881-4a55-bab5-a54cee327d0c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=752650378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.752650378
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.513454525
Short name	T328
Test name
Test status
Simulation time	7271160761 ps
CPU time	36.46 seconds
Started	Apr 28 12:49:17 PM PDT 24
Finished	Apr 28 12:49:54 PM PDT 24
Peak memory	203544 kb
Host	smart-da686720-21e6-432c-88af-35703a3d647c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=513454525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.513454525
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1232459241
Short name	T51
Test name
Test status
Simulation time	49346746 ps
CPU time	2.37 seconds
Started	Apr 28 12:49:20 PM PDT 24
Finished	Apr 28 12:49:23 PM PDT 24
Peak memory	203364 kb
Host	smart-900cd760-0082-4c55-8ee8-25dfc101eac2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232459241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1232459241
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.220391921
Short name	T871
Test name
Test status
Simulation time	1914006870 ps
CPU time	203.28 seconds
Started	Apr 28 12:49:22 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	206916 kb
Host	smart-31c3225b-77d6-4bab-aaf4-3575e8b72354
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=220391921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.220391921
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3847242364
Short name	T17
Test name
Test status
Simulation time	2840577174 ps
CPU time	69.01 seconds
Started	Apr 28 12:49:23 PM PDT 24
Finished	Apr 28 12:50:32 PM PDT 24
Peak memory	205668 kb
Host	smart-c85652a9-9eb8-4029-ac74-e0cfe78d1636
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3847242364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3847242364
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3056829895
Short name	T895
Test name
Test status
Simulation time	34851294 ps
CPU time	14.11 seconds
Started	Apr 28 12:49:21 PM PDT 24
Finished	Apr 28 12:49:36 PM PDT 24
Peak memory	206288 kb
Host	smart-37456509-7e00-4160-ac01-58ce32f4f385
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3056829895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.3056829895
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.278372766
Short name	T490
Test name
Test status
Simulation time	1677539575 ps
CPU time	267.72 seconds
Started	Apr 28 12:49:23 PM PDT 24
Finished	Apr 28 12:53:51 PM PDT 24
Peak memory	211360 kb
Host	smart-c66a5234-9443-4bd5-a0c1-79c33551249f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=278372766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res et_error.278372766
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1060487105
Short name	T449
Test name
Test status
Simulation time	177852187 ps
CPU time	19.67 seconds
Started	Apr 28 12:49:18 PM PDT 24
Finished	Apr 28 12:49:38 PM PDT 24
Peak memory	204812 kb
Host	smart-66303feb-f91b-4103-9775-9a0c2b5c2b28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1060487105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1060487105
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1754016287
Short name	T527
Test name
Test status
Simulation time	1425584071 ps
CPU time	27.68 seconds
Started	Apr 28 12:49:30 PM PDT 24
Finished	Apr 28 12:49:58 PM PDT 24
Peak memory	211660 kb
Host	smart-102d5371-072c-45e7-aab7-723b9964a681
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1754016287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1754016287
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3741357758
Short name	T814
Test name
Test status
Simulation time	76952106984 ps
CPU time	618.06 seconds
Started	Apr 28 12:49:28 PM PDT 24
Finished	Apr 28 12:59:47 PM PDT 24
Peak memory	211544 kb
Host	smart-88e57d1c-a466-4a99-b4ed-476c25c36ae2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3741357758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3741357758
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2622209888
Short name	T685
Test name
Test status
Simulation time	507923616 ps
CPU time	12.46 seconds
Started	Apr 28 12:49:30 PM PDT 24
Finished	Apr 28 12:49:43 PM PDT 24
Peak memory	203276 kb
Host	smart-fa7be9dd-6a3a-4822-8964-bb9acc54d378
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2622209888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2622209888
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.4176209803
Short name	T267
Test name
Test status
Simulation time	423695264 ps
CPU time	10.97 seconds
Started	Apr 28 12:49:30 PM PDT 24
Finished	Apr 28 12:49:42 PM PDT 24
Peak memory	203272 kb
Host	smart-3ce0a414-5edb-4763-b1d2-e51a06516b58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176209803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4176209803
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.782842238
Short name	T752
Test name
Test status
Simulation time	1097136318 ps
CPU time	32.18 seconds
Started	Apr 28 12:49:29 PM PDT 24
Finished	Apr 28 12:50:02 PM PDT 24
Peak memory	204740 kb
Host	smart-424f228d-49f8-4f9d-89e2-19f4adc86bab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=782842238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.782842238
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2098868647
Short name	T773
Test name
Test status
Simulation time	25308193629 ps
CPU time	140.1 seconds
Started	Apr 28 12:49:27 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	205044 kb
Host	smart-1a5cfefd-fe76-4bc0-9437-cd5302c30fd4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098868647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2098868647
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2289761986
Short name	T502
Test name
Test status
Simulation time	17465938386 ps
CPU time	149.89 seconds
Started	Apr 28 12:49:28 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	205080 kb
Host	smart-9bbdf929-5362-47de-8da7-3ed3a42a6ade
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2289761986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2289761986
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.4233318732
Short name	T250
Test name
Test status
Simulation time	234282347 ps
CPU time	21.98 seconds
Started	Apr 28 12:49:29 PM PDT 24
Finished	Apr 28 12:49:51 PM PDT 24
Peak memory	204764 kb
Host	smart-04cffa82-6d69-42f2-8556-dc19f25ef03c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233318732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.4233318732
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.3330151906
Short name	T431
Test name
Test status
Simulation time	315223602 ps
CPU time	3.85 seconds
Started	Apr 28 12:49:22 PM PDT 24
Finished	Apr 28 12:49:26 PM PDT 24
Peak memory	203352 kb
Host	smart-aa8dd435-a32f-4f71-98da-e33f70323305
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3330151906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3330151906
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2215753092
Short name	T493
Test name
Test status
Simulation time	23628505229 ps
CPU time	34.35 seconds
Started	Apr 28 12:49:23 PM PDT 24
Finished	Apr 28 12:49:58 PM PDT 24
Peak memory	203536 kb
Host	smart-3c6f0b5d-2f0d-460f-80ce-0f7d650eed81
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215753092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2215753092
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2308024423
Short name	T693
Test name
Test status
Simulation time	3164654738 ps
CPU time	21.8 seconds
Started	Apr 28 12:49:23 PM PDT 24
Finished	Apr 28 12:49:45 PM PDT 24
Peak memory	203548 kb
Host	smart-985b8a7d-8e34-434e-8d0e-e36c2f42238c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2308024423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2308024423
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2517656901
Short name	T410
Test name
Test status
Simulation time	32607797 ps
CPU time	2.2 seconds
Started	Apr 28 12:49:23 PM PDT 24
Finished	Apr 28 12:49:25 PM PDT 24
Peak memory	203300 kb
Host	smart-c82cd46e-bc60-459f-80ea-d6edbf09a43a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517656901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2517656901
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.1450834042
Short name	T556
Test name
Test status
Simulation time	5786217418 ps
CPU time	28.74 seconds
Started	Apr 28 12:49:29 PM PDT 24
Finished	Apr 28 12:49:58 PM PDT 24
Peak memory	205220 kb
Host	smart-0c494222-c9ff-4742-b23b-63db60d7abf4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1450834042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1450834042
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3788449572
Short name	T276
Test name
Test status
Simulation time	543199160 ps
CPU time	15.18 seconds
Started	Apr 28 12:49:26 PM PDT 24
Finished	Apr 28 12:49:42 PM PDT 24
Peak memory	204508 kb
Host	smart-bca18573-9425-406b-8b7e-0c98f2b2ec0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788449572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3788449572
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3126915791
Short name	T19
Test name
Test status
Simulation time	479485812 ps
CPU time	213.35 seconds
Started	Apr 28 12:49:27 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	209600 kb
Host	smart-cafe4c17-c0c0-4aee-b0fe-56be163b44b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3126915791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3126915791
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.4237510963
Short name	T874
Test name
Test status
Simulation time	391927246 ps
CPU time	135.98 seconds
Started	Apr 28 12:49:27 PM PDT 24
Finished	Apr 28 12:51:44 PM PDT 24
Peak memory	210652 kb
Host	smart-09081cf5-dfa8-4b8a-b4ec-4bafe8d39e48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4237510963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.4237510963
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3746533097
Short name	T533
Test name
Test status
Simulation time	946511911 ps
CPU time	27.29 seconds
Started	Apr 28 12:49:27 PM PDT 24
Finished	Apr 28 12:49:55 PM PDT 24
Peak memory	211556 kb
Host	smart-c668cf5d-8314-4704-9583-79fc0c1935d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3746533097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3746533097
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.916291974
Short name	T892
Test name
Test status
Simulation time	180583079 ps
CPU time	3.28 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:47:06 PM PDT 24
Peak memory	203392 kb
Host	smart-7f283178-6a0c-4f70-ba65-e4eb09de8ed0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=916291974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.916291974
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.4269871989
Short name	T80
Test name
Test status
Simulation time	22517972486 ps
CPU time	222.09 seconds
Started	Apr 28 12:46:45 PM PDT 24
Finished	Apr 28 12:50:28 PM PDT 24
Peak memory	206528 kb
Host	smart-f2845094-e169-4351-a7d6-67beaaafaedb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4269871989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.4269871989
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2401349191
Short name	T548
Test name
Test status
Simulation time	731597429 ps
CPU time	29.77 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:47:20 PM PDT 24
Peak memory	204136 kb
Host	smart-8fae5530-d880-48c0-8004-df967f079111
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401349191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2401349191
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.336584283
Short name	T245
Test name
Test status
Simulation time	1419797207 ps
CPU time	11.49 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:47:01 PM PDT 24
Peak memory	203316 kb
Host	smart-b204a24e-6917-49b8-8b28-ef70669addc1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=336584283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.336584283
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.3916851976
Short name	T132
Test name
Test status
Simulation time	129800240 ps
CPU time	13.29 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:17 PM PDT 24
Peak memory	204584 kb
Host	smart-d4c2a7ec-f78b-4077-a075-253d3e7b73d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3916851976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3916851976
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2143989212
Short name	T811
Test name
Test status
Simulation time	16562754800 ps
CPU time	43.17 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:47 PM PDT 24
Peak memory	204772 kb
Host	smart-a0ed0fc0-813c-4c9e-8197-ccd68f492917
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143989212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2143989212
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1059306099
Short name	T223
Test name
Test status
Simulation time	12654381115 ps
CPU time	79.59 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:48:09 PM PDT 24
Peak memory	204756 kb
Host	smart-6b6bb32c-4da0-440e-bbdd-2bde299fc565
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1059306099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1059306099
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1229015935
Short name	T160
Test name
Test status
Simulation time	29147331 ps
CPU time	3.36 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:08 PM PDT 24
Peak memory	203500 kb
Host	smart-daf4fd53-2fb0-4a11-9901-8a13c661d7a6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229015935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1229015935
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.1510901592
Short name	T365
Test name
Test status
Simulation time	471183234 ps
CPU time	12.92 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:05 PM PDT 24
Peak memory	203480 kb
Host	smart-b75df236-0b8d-4578-a0d5-4a0353d645e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1510901592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1510901592
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.4061685276
Short name	T159
Test name
Test status
Simulation time	52348492 ps
CPU time	2.3 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:46:52 PM PDT 24
Peak memory	203360 kb
Host	smart-0a4216d3-e416-4c02-868e-a967cc031cb1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4061685276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4061685276
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.414797826
Short name	T348
Test name
Test status
Simulation time	10402519993 ps
CPU time	33.09 seconds
Started	Apr 28 12:46:45 PM PDT 24
Finished	Apr 28 12:47:19 PM PDT 24
Peak memory	203532 kb
Host	smart-d3c6a6a2-3731-4abd-b3b6-b3992ca37d33
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=414797826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.414797826
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1678407305
Short name	T712
Test name
Test status
Simulation time	4203801540 ps
CPU time	26.97 seconds
Started	Apr 28 12:46:47 PM PDT 24
Finished	Apr 28 12:47:15 PM PDT 24
Peak memory	203440 kb
Host	smart-e9f90f4b-6ef7-4f16-8c5a-f08be026d53d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1678407305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1678407305
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2571214680
Short name	T589
Test name
Test status
Simulation time	26114310 ps
CPU time	2.45 seconds
Started	Apr 28 12:46:48 PM PDT 24
Finished	Apr 28 12:46:50 PM PDT 24
Peak memory	203376 kb
Host	smart-599f0111-dd61-4f4d-b1ee-a6ad1b676478
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571214680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2571214680
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1173546420
Short name	T666
Test name
Test status
Simulation time	4155521554 ps
CPU time	80.87 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:48:27 PM PDT 24
Peak memory	205860 kb
Host	smart-0d005b04-1a84-403f-a7cc-b1016d24599f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173546420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1173546420
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1894733081
Short name	T645
Test name
Test status
Simulation time	13656967444 ps
CPU time	363.29 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	210536 kb
Host	smart-aa5bde63-a6d3-4356-bde8-0aa34805fee8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1894733081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.1894733081
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.796661320
Short name	T233
Test name
Test status
Simulation time	326836166 ps
CPU time	39.12 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:44 PM PDT 24
Peak memory	206356 kb
Host	smart-e969545f-681b-404a-a5e1-2d247f16c34d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796661320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.796661320
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3133518894
Short name	T496
Test name
Test status
Simulation time	34704617 ps
CPU time	4.83 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:11 PM PDT 24
Peak memory	211568 kb
Host	smart-b51b75cc-0a18-4477-9b1c-c605ed3cd704
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3133518894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3133518894
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.612764287
Short name	T574
Test name
Test status
Simulation time	496839092 ps
CPU time	41.56 seconds
Started	Apr 28 12:49:32 PM PDT 24
Finished	Apr 28 12:50:14 PM PDT 24
Peak memory	206692 kb
Host	smart-624a211f-dea2-42c2-aaba-09fdef823e69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=612764287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.612764287
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3582781527
Short name	T569
Test name
Test status
Simulation time	4577804256 ps
CPU time	28.8 seconds
Started	Apr 28 12:49:34 PM PDT 24
Finished	Apr 28 12:50:03 PM PDT 24
Peak memory	211588 kb
Host	smart-d1e0025f-7780-48cd-b6e5-0e18e1f6568d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582781527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3582781527
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.725655276
Short name	T311
Test name
Test status
Simulation time	642325659 ps
CPU time	21.11 seconds
Started	Apr 28 12:49:31 PM PDT 24
Finished	Apr 28 12:49:52 PM PDT 24
Peak memory	203560 kb
Host	smart-309a735e-a5f8-43a3-af2f-b42de0a8256b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=725655276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.725655276
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.1328596377
Short name	T48
Test name
Test status
Simulation time	1886520554 ps
CPU time	34.54 seconds
Started	Apr 28 12:49:32 PM PDT 24
Finished	Apr 28 12:50:07 PM PDT 24
Peak memory	211624 kb
Host	smart-5385fe5e-ca77-4df1-8524-4df84e976c2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1328596377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1328596377
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1753868022
Short name	T754
Test name
Test status
Simulation time	148995362725 ps
CPU time	194.27 seconds
Started	Apr 28 12:49:33 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	204696 kb
Host	smart-d6ac7ff0-5525-47d2-873a-2dace5be90cc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753868022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1753868022
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2707084979
Short name	T103
Test name
Test status
Simulation time	13863765487 ps
CPU time	98.49 seconds
Started	Apr 28 12:49:32 PM PDT 24
Finished	Apr 28 12:51:11 PM PDT 24
Peak memory	211740 kb
Host	smart-76dd7156-5aff-4b58-9cb9-c1b05a250deb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2707084979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2707084979
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2350377803
Short name	T774
Test name
Test status
Simulation time	127226097 ps
CPU time	5.86 seconds
Started	Apr 28 12:49:37 PM PDT 24
Finished	Apr 28 12:49:44 PM PDT 24
Peak memory	211680 kb
Host	smart-def64cf3-e42d-472a-b3a9-cb72429c0ad0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350377803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2350377803
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.3302854349
Short name	T818
Test name
Test status
Simulation time	2818703932 ps
CPU time	16.21 seconds
Started	Apr 28 12:49:35 PM PDT 24
Finished	Apr 28 12:49:51 PM PDT 24
Peak memory	203888 kb
Host	smart-4b2778f1-ae3b-44be-99a2-6f2adfbdb467
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3302854349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3302854349
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.1084721157
Short name	T50
Test name
Test status
Simulation time	153106039 ps
CPU time	3.8 seconds
Started	Apr 28 12:49:26 PM PDT 24
Finished	Apr 28 12:49:31 PM PDT 24
Peak memory	203484 kb
Host	smart-0fe13695-2905-46d4-b66a-dac717cf8824
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1084721157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1084721157
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.4195242182
Short name	T415
Test name
Test status
Simulation time	4774576575 ps
CPU time	29.29 seconds
Started	Apr 28 12:49:31 PM PDT 24
Finished	Apr 28 12:50:01 PM PDT 24
Peak memory	203512 kb
Host	smart-3d95e138-7a5d-47a0-bdf3-bfc3f517287b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195242182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.4195242182
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2511973289
Short name	T887
Test name
Test status
Simulation time	4633566108 ps
CPU time	23.92 seconds
Started	Apr 28 12:49:34 PM PDT 24
Finished	Apr 28 12:49:58 PM PDT 24
Peak memory	203456 kb
Host	smart-76cd5ca8-698b-42d6-ab6d-1e1d1ceb8dd8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2511973289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2511973289
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2158423465
Short name	T205
Test name
Test status
Simulation time	27914946 ps
CPU time	2.24 seconds
Started	Apr 28 12:49:33 PM PDT 24
Finished	Apr 28 12:49:35 PM PDT 24
Peak memory	203468 kb
Host	smart-e0f2eb95-8b99-49a2-934a-5319ecaefd3d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158423465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2158423465
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.3728145217
Short name	T91
Test name
Test status
Simulation time	10261902738 ps
CPU time	285.71 seconds
Started	Apr 28 12:49:34 PM PDT 24
Finished	Apr 28 12:54:20 PM PDT 24
Peak memory	207608 kb
Host	smart-b07b15a0-039b-4a4b-9b4c-66630b8f1d37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3728145217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3728145217
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2881490391
Short name	T618
Test name
Test status
Simulation time	5610903775 ps
CPU time	176.07 seconds
Started	Apr 28 12:49:31 PM PDT 24
Finished	Apr 28 12:52:28 PM PDT 24
Peak memory	206820 kb
Host	smart-8d991556-5b2a-43f7-9aab-50d2ec897f50
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2881490391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2881490391
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4205185777
Short name	T743
Test name
Test status
Simulation time	27259158 ps
CPU time	24.46 seconds
Started	Apr 28 12:49:37 PM PDT 24
Finished	Apr 28 12:50:02 PM PDT 24
Peak memory	206336 kb
Host	smart-40d104cc-35b0-44cc-badd-d2bfb22f97cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4205185777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.4205185777
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1307290887
Short name	T783
Test name
Test status
Simulation time	540441284 ps
CPU time	111.29 seconds
Started	Apr 28 12:49:32 PM PDT 24
Finished	Apr 28 12:51:24 PM PDT 24
Peak memory	208688 kb
Host	smart-ebbc2536-24af-42d3-a1a6-cd903137213d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1307290887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.1307290887
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1605238140
Short name	T335
Test name
Test status
Simulation time	78506113 ps
CPU time	6.63 seconds
Started	Apr 28 12:49:31 PM PDT 24
Finished	Apr 28 12:49:38 PM PDT 24
Peak memory	204720 kb
Host	smart-ae0f77ce-d015-4741-9293-447a9de9ad9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1605238140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1605238140
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1993591536
Short name	T54
Test name
Test status
Simulation time	4723807320 ps
CPU time	65.49 seconds
Started	Apr 28 12:49:36 PM PDT 24
Finished	Apr 28 12:50:43 PM PDT 24
Peak memory	206804 kb
Host	smart-80f19b4b-002e-41b4-89ec-2dc43dcaea30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1993591536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1993591536
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2453855847
Short name	T412
Test name
Test status
Simulation time	5148444796 ps
CPU time	29.18 seconds
Started	Apr 28 12:49:38 PM PDT 24
Finished	Apr 28 12:50:07 PM PDT 24
Peak memory	203948 kb
Host	smart-e680b67f-a1f7-4d87-ba6a-4b079443e43d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2453855847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.2453855847
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1950582500
Short name	T271
Test name
Test status
Simulation time	189757861 ps
CPU time	5.11 seconds
Started	Apr 28 12:49:36 PM PDT 24
Finished	Apr 28 12:49:41 PM PDT 24
Peak memory	203580 kb
Host	smart-09e565fa-076c-45c0-be40-78448a1f467b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1950582500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1950582500
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.1042840416
Short name	T400
Test name
Test status
Simulation time	379896233 ps
CPU time	8.73 seconds
Started	Apr 28 12:49:37 PM PDT 24
Finished	Apr 28 12:49:47 PM PDT 24
Peak memory	203348 kb
Host	smart-a027d2da-d45c-422c-9e4c-180db7cf572f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1042840416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1042840416
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.3879228243
Short name	T383
Test name
Test status
Simulation time	97027280 ps
CPU time	12.77 seconds
Started	Apr 28 12:49:37 PM PDT 24
Finished	Apr 28 12:49:50 PM PDT 24
Peak memory	204616 kb
Host	smart-03aa5fb5-c0d4-4ed2-8b53-b9c661721db4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3879228243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3879228243
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3386661507
Short name	T59
Test name
Test status
Simulation time	113443968084 ps
CPU time	198.83 seconds
Started	Apr 28 12:49:37 PM PDT 24
Finished	Apr 28 12:52:56 PM PDT 24
Peak memory	204612 kb
Host	smart-5ec9d01f-dd79-4d39-b4fe-79d0a33e7b81
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386661507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3386661507
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1816844474
Short name	T695
Test name
Test status
Simulation time	12368116845 ps
CPU time	71.53 seconds
Started	Apr 28 12:49:37 PM PDT 24
Finished	Apr 28 12:50:49 PM PDT 24
Peak memory	204868 kb
Host	smart-4646cfc4-5f6d-49a1-99cb-b9c24008329a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1816844474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1816844474
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3450449112
Short name	T199
Test name
Test status
Simulation time	245674221 ps
CPU time	24.16 seconds
Started	Apr 28 12:49:38 PM PDT 24
Finished	Apr 28 12:50:03 PM PDT 24
Peak memory	204796 kb
Host	smart-ca7a5651-72d7-413f-862d-1e497f3cd3c4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450449112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3450449112
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.4251779481
Short name	T171
Test name
Test status
Simulation time	1129787435 ps
CPU time	18.88 seconds
Started	Apr 28 12:49:38 PM PDT 24
Finished	Apr 28 12:49:58 PM PDT 24
Peak memory	204188 kb
Host	smart-8f96f805-acc4-49a7-861a-fb3a676d1a17
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4251779481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.4251779481
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.1440783435
Short name	T257
Test name
Test status
Simulation time	133017568 ps
CPU time	3.21 seconds
Started	Apr 28 12:49:31 PM PDT 24
Finished	Apr 28 12:49:34 PM PDT 24
Peak memory	203396 kb
Host	smart-d73301ff-b5e9-4902-8b67-9f78f86fd1c1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1440783435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1440783435
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.868964901
Short name	T503
Test name
Test status
Simulation time	4910978118 ps
CPU time	28.6 seconds
Started	Apr 28 12:49:36 PM PDT 24
Finished	Apr 28 12:50:06 PM PDT 24
Peak memory	203552 kb
Host	smart-cd627d2c-0aaf-488f-8fe6-21789f7cd8ef
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=868964901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.868964901
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.301964981
Short name	T559
Test name
Test status
Simulation time	5251028095 ps
CPU time	26.49 seconds
Started	Apr 28 12:49:33 PM PDT 24
Finished	Apr 28 12:50:00 PM PDT 24
Peak memory	203456 kb
Host	smart-64b56fca-3877-4c72-b11a-0b1c7cddb87e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=301964981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.301964981
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2333828819
Short name	T772
Test name
Test status
Simulation time	38774574 ps
CPU time	2.4 seconds
Started	Apr 28 12:49:31 PM PDT 24
Finished	Apr 28 12:49:33 PM PDT 24
Peak memory	203456 kb
Host	smart-a86bcd38-f01d-4744-b721-6e0b009a1a06
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333828819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2333828819
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.152416591
Short name	T706
Test name
Test status
Simulation time	1227787285 ps
CPU time	182.89 seconds
Started	Apr 28 12:49:36 PM PDT 24
Finished	Apr 28 12:52:39 PM PDT 24
Peak memory	206100 kb
Host	smart-33474791-728b-4963-837d-beabd0380efb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=152416591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.152416591
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.735470811
Short name	T251
Test name
Test status
Simulation time	793765096 ps
CPU time	16.09 seconds
Started	Apr 28 12:49:36 PM PDT 24
Finished	Apr 28 12:49:53 PM PDT 24
Peak memory	203912 kb
Host	smart-c7e38958-23f6-4057-be79-0cd07b9f1a86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=735470811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.735470811
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3960213956
Short name	T721
Test name
Test status
Simulation time	88158155 ps
CPU time	18.64 seconds
Started	Apr 28 12:49:37 PM PDT 24
Finished	Apr 28 12:49:56 PM PDT 24
Peak memory	205484 kb
Host	smart-b22ebe04-7453-4669-a15e-85c58a846899
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3960213956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.3960213956
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2804168166
Short name	T894
Test name
Test status
Simulation time	8271861088 ps
CPU time	324.87 seconds
Started	Apr 28 12:49:36 PM PDT 24
Finished	Apr 28 12:55:02 PM PDT 24
Peak memory	219880 kb
Host	smart-6104dc63-87cb-40c0-98a8-d192ad21f962
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2804168166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2804168166
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.367499545
Short name	T846
Test name
Test status
Simulation time	1305013486 ps
CPU time	24.16 seconds
Started	Apr 28 12:49:38 PM PDT 24
Finished	Apr 28 12:50:03 PM PDT 24
Peak memory	205004 kb
Host	smart-98866fa7-d826-48c8-8960-be0aa9892c30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=367499545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.367499545
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3615282745
Short name	T291
Test name
Test status
Simulation time	788114906 ps
CPU time	40.24 seconds
Started	Apr 28 12:49:40 PM PDT 24
Finished	Apr 28 12:50:21 PM PDT 24
Peak memory	204916 kb
Host	smart-92491941-b7cf-476c-acdc-0a396332c0c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3615282745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3615282745
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2211397233
Short name	T100
Test name
Test status
Simulation time	115609822154 ps
CPU time	742.17 seconds
Started	Apr 28 12:49:40 PM PDT 24
Finished	Apr 28 01:02:03 PM PDT 24
Peak memory	207692 kb
Host	smart-57d5dd4b-5cdf-467b-9c99-31a9c212077a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2211397233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2211397233
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2237654341
Short name	T393
Test name
Test status
Simulation time	684317987 ps
CPU time	22.4 seconds
Started	Apr 28 12:49:41 PM PDT 24
Finished	Apr 28 12:50:04 PM PDT 24
Peak memory	203572 kb
Host	smart-8c2e7762-29a7-4356-aacb-9c64f2de1256
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2237654341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2237654341
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.987057175
Short name	T728
Test name
Test status
Simulation time	188354986 ps
CPU time	10.25 seconds
Started	Apr 28 12:49:41 PM PDT 24
Finished	Apr 28 12:49:52 PM PDT 24
Peak memory	203340 kb
Host	smart-e52bcb92-4ee5-4fa1-be3c-a20478df8431
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987057175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.987057175
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.1833510490
Short name	T8
Test name
Test status
Simulation time	71399800 ps
CPU time	7.21 seconds
Started	Apr 28 12:49:41 PM PDT 24
Finished	Apr 28 12:49:49 PM PDT 24
Peak memory	211684 kb
Host	smart-5b4bacaf-4e1f-4dfe-a0e6-6c70df6fe475
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1833510490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1833510490
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2658862563
Short name	T93
Test name
Test status
Simulation time	166399081478 ps
CPU time	333 seconds
Started	Apr 28 12:49:41 PM PDT 24
Finished	Apr 28 12:55:15 PM PDT 24
Peak memory	204640 kb
Host	smart-1c98fe85-58da-4730-8885-803a137b810e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658862563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2658862563
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3871888886
Short name	T45
Test name
Test status
Simulation time	15802478189 ps
CPU time	32.51 seconds
Started	Apr 28 12:49:42 PM PDT 24
Finished	Apr 28 12:50:15 PM PDT 24
Peak memory	203568 kb
Host	smart-71eff192-c2cc-4b4c-abbc-11e969b1e08e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3871888886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3871888886
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.307087002
Short name	T191
Test name
Test status
Simulation time	108319733 ps
CPU time	18.35 seconds
Started	Apr 28 12:49:42 PM PDT 24
Finished	Apr 28 12:50:01 PM PDT 24
Peak memory	204728 kb
Host	smart-8b7c6b1b-c4e7-4262-a2ea-459d13058ad8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307087002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.307087002
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.1232144665
Short name	T719
Test name
Test status
Simulation time	208847101 ps
CPU time	4.83 seconds
Started	Apr 28 12:49:40 PM PDT 24
Finished	Apr 28 12:49:46 PM PDT 24
Peak memory	203436 kb
Host	smart-336f18d6-bd75-4929-872d-5cd975e049fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1232144665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1232144665
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.2896306347
Short name	T877
Test name
Test status
Simulation time	296850730 ps
CPU time	3.42 seconds
Started	Apr 28 12:49:38 PM PDT 24
Finished	Apr 28 12:49:42 PM PDT 24
Peak memory	203488 kb
Host	smart-9735adf1-19f3-472e-8aec-e17ec355ce55
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2896306347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2896306347
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.230468466
Short name	T790
Test name
Test status
Simulation time	8482987238 ps
CPU time	35.31 seconds
Started	Apr 28 12:49:41 PM PDT 24
Finished	Apr 28 12:50:17 PM PDT 24
Peak memory	203412 kb
Host	smart-af3f0fef-be75-416e-b210-9621c98bd4be
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=230468466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.230468466
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3173530435
Short name	T491
Test name
Test status
Simulation time	18059269981 ps
CPU time	29 seconds
Started	Apr 28 12:49:40 PM PDT 24
Finished	Apr 28 12:50:10 PM PDT 24
Peak memory	203456 kb
Host	smart-9a8e0bc8-2352-4ca0-a5fd-b18dac5c74c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3173530435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3173530435
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.966771544
Short name	T483
Test name
Test status
Simulation time	26208313 ps
CPU time	2.24 seconds
Started	Apr 28 12:49:41 PM PDT 24
Finished	Apr 28 12:49:44 PM PDT 24
Peak memory	203332 kb
Host	smart-c09ceb64-fb74-4126-8821-737d201d4723
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966771544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.966771544
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.2816548840
Short name	T374
Test name
Test status
Simulation time	7945617680 ps
CPU time	231.65 seconds
Started	Apr 28 12:49:44 PM PDT 24
Finished	Apr 28 12:53:36 PM PDT 24
Peak memory	207524 kb
Host	smart-d9f53d98-83ac-493f-ac7d-95271290d96d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2816548840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2816548840
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2953984076
Short name	T389
Test name
Test status
Simulation time	2729258306 ps
CPU time	113.97 seconds
Started	Apr 28 12:49:46 PM PDT 24
Finished	Apr 28 12:51:41 PM PDT 24
Peak memory	206656 kb
Host	smart-c5e47aa2-b645-46d6-933c-a428babce867
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2953984076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2953984076
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2630255267
Short name	T38
Test name
Test status
Simulation time	408622244 ps
CPU time	138.31 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:52:08 PM PDT 24
Peak memory	207236 kb
Host	smart-845d0911-ec72-4eb7-8aa1-ff8d5c8460e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2630255267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.2630255267
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3671462799
Short name	T157
Test name
Test status
Simulation time	693759682 ps
CPU time	14.73 seconds
Started	Apr 28 12:49:40 PM PDT 24
Finished	Apr 28 12:49:56 PM PDT 24
Peak memory	204948 kb
Host	smart-67638185-be01-4b7f-b9af-a3bdd58dab6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3671462799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3671462799
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.174916515
Short name	T156
Test name
Test status
Simulation time	1479153750 ps
CPU time	37.12 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:50:27 PM PDT 24
Peak memory	211528 kb
Host	smart-761a11d4-078a-4a7c-869b-ac46c46b955e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=174916515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.174916515
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.728964384
Short name	T110
Test name
Test status
Simulation time	248429162348 ps
CPU time	838.81 seconds
Started	Apr 28 12:49:47 PM PDT 24
Finished	Apr 28 01:03:47 PM PDT 24
Peak memory	206072 kb
Host	smart-2f64e2b9-e2bd-4eaf-b588-51f7f9cc2c43
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=728964384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo w_rsp.728964384
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3284067145
Short name	T611
Test name
Test status
Simulation time	144266258 ps
CPU time	4.18 seconds
Started	Apr 28 12:49:46 PM PDT 24
Finished	Apr 28 12:49:51 PM PDT 24
Peak memory	203748 kb
Host	smart-b5dde43f-1164-442e-b523-0bd8959571bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3284067145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3284067145
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.895637975
Short name	T649
Test name
Test status
Simulation time	1613316096 ps
CPU time	32.59 seconds
Started	Apr 28 12:49:49 PM PDT 24
Finished	Apr 28 12:50:23 PM PDT 24
Peak memory	203352 kb
Host	smart-1e633dc2-edc8-4217-94d0-18e99392734b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=895637975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.895637975
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.1624821079
Short name	T14
Test name
Test status
Simulation time	757018873 ps
CPU time	29.54 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:50:19 PM PDT 24
Peak memory	204496 kb
Host	smart-28f89589-56b9-4fdb-94bc-c99e21a03724
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1624821079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1624821079
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.729052889
Short name	T615
Test name
Test status
Simulation time	4344442860 ps
CPU time	15.83 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:50:05 PM PDT 24
Peak memory	203568 kb
Host	smart-8327e5db-8a04-4386-a9dd-42cf1e819a22
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=729052889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.729052889
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3205378868
Short name	T667
Test name
Test status
Simulation time	290925893 ps
CPU time	24.18 seconds
Started	Apr 28 12:49:47 PM PDT 24
Finished	Apr 28 12:50:12 PM PDT 24
Peak memory	204504 kb
Host	smart-18279de9-2fed-464e-93e7-6afabeaf6ebb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205378868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3205378868
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.2827546152
Short name	T407
Test name
Test status
Simulation time	952037841 ps
CPU time	15.83 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:50:05 PM PDT 24
Peak memory	203448 kb
Host	smart-2df48fe2-1f6f-4d8e-86e5-29773b70e4fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2827546152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2827546152
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.1191887214
Short name	T152
Test name
Test status
Simulation time	417584385 ps
CPU time	3.86 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:49:54 PM PDT 24
Peak memory	203492 kb
Host	smart-db1e5d68-33f0-4228-8034-e8f96041a398
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1191887214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1191887214
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1902501643
Short name	T803
Test name
Test status
Simulation time	7232104065 ps
CPU time	22.12 seconds
Started	Apr 28 12:49:49 PM PDT 24
Finished	Apr 28 12:50:12 PM PDT 24
Peak memory	203408 kb
Host	smart-3503a70e-0361-4da8-a699-4dae6fbb92b2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902501643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1902501643
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.883975269
Short name	T315
Test name
Test status
Simulation time	24044497726 ps
CPU time	46.52 seconds
Started	Apr 28 12:49:46 PM PDT 24
Finished	Apr 28 12:50:33 PM PDT 24
Peak memory	203452 kb
Host	smart-d979af97-51d1-42cf-99eb-162420256d25
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=883975269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.883975269
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3720667321
Short name	T836
Test name
Test status
Simulation time	41220848 ps
CPU time	2.39 seconds
Started	Apr 28 12:49:47 PM PDT 24
Finished	Apr 28 12:49:51 PM PDT 24
Peak memory	203328 kb
Host	smart-53ca1ab6-18af-4bf8-85f4-a4f124390e0e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720667321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3720667321
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.85057409
Short name	T77
Test name
Test status
Simulation time	6532733450 ps
CPU time	200.04 seconds
Started	Apr 28 12:49:50 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	209324 kb
Host	smart-4265494a-21d7-424c-adaa-02b454850053
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=85057409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.85057409
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3499442904
Short name	T174
Test name
Test status
Simulation time	19826720622 ps
CPU time	208.78 seconds
Started	Apr 28 12:49:48 PM PDT 24
Finished	Apr 28 12:53:18 PM PDT 24
Peak memory	209544 kb
Host	smart-5377d5b9-e723-41ff-8a65-1616a640a893
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3499442904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3499442904
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3342558860
Short name	T492
Test name
Test status
Simulation time	481467241 ps
CPU time	92.38 seconds
Started	Apr 28 12:49:47 PM PDT 24
Finished	Apr 28 12:51:20 PM PDT 24
Peak memory	210432 kb
Host	smart-30cd3e14-1645-4edf-91c0-4cccb9a356ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3342558860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3342558860
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.471540880
Short name	T284
Test name
Test status
Simulation time	408121489 ps
CPU time	12.4 seconds
Started	Apr 28 12:49:50 PM PDT 24
Finished	Apr 28 12:50:04 PM PDT 24
Peak memory	204768 kb
Host	smart-0c3384d2-d488-4143-a848-a924357e054b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=471540880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.471540880
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.534482953
Short name	T262
Test name
Test status
Simulation time	362374369 ps
CPU time	37.18 seconds
Started	Apr 28 12:49:51 PM PDT 24
Finished	Apr 28 12:50:29 PM PDT 24
Peak memory	205572 kb
Host	smart-cd473577-6f90-4fc1-be1d-2984979ff634
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=534482953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.534482953
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1794999510
Short name	T545
Test name
Test status
Simulation time	72636503921 ps
CPU time	465.34 seconds
Started	Apr 28 12:49:54 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	211576 kb
Host	smart-1eb54184-1439-4404-b7a7-65a8d90b1a32
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1794999510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.1794999510
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2348455385
Short name	T351
Test name
Test status
Simulation time	71203123 ps
CPU time	9.5 seconds
Started	Apr 28 12:49:51 PM PDT 24
Finished	Apr 28 12:50:01 PM PDT 24
Peak memory	203764 kb
Host	smart-c253a139-315b-4ae4-a1af-b6f8e7a677e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348455385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2348455385
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.453360667
Short name	T456
Test name
Test status
Simulation time	17144298 ps
CPU time	2.01 seconds
Started	Apr 28 12:49:53 PM PDT 24
Finished	Apr 28 12:49:56 PM PDT 24
Peak memory	203316 kb
Host	smart-c19fe81c-3dbf-4a5a-ba51-b396f819e0ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=453360667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.453360667
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.1493278833
Short name	T307
Test name
Test status
Simulation time	1647682887 ps
CPU time	27.05 seconds
Started	Apr 28 12:49:53 PM PDT 24
Finished	Apr 28 12:50:20 PM PDT 24
Peak memory	204832 kb
Host	smart-2f18fb9a-5421-4bd3-9c3a-9790d4ca9841
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1493278833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1493278833
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.551586623
Short name	T438
Test name
Test status
Simulation time	5336714946 ps
CPU time	14.35 seconds
Started	Apr 28 12:49:56 PM PDT 24
Finished	Apr 28 12:50:11 PM PDT 24
Peak memory	203400 kb
Host	smart-75d04ee3-5b69-4c72-a29f-d351a9adf943
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=551586623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.551586623
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3301914712
Short name	T90
Test name
Test status
Simulation time	95247721838 ps
CPU time	297.75 seconds
Started	Apr 28 12:49:51 PM PDT 24
Finished	Apr 28 12:54:49 PM PDT 24
Peak memory	204808 kb
Host	smart-32e18fc8-db13-4298-9b0f-d3045660bbbd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3301914712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3301914712
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1487409914
Short name	T677
Test name
Test status
Simulation time	328389249 ps
CPU time	26.29 seconds
Started	Apr 28 12:49:53 PM PDT 24
Finished	Apr 28 12:50:20 PM PDT 24
Peak memory	204700 kb
Host	smart-66afd916-d0f9-451a-b80a-0781e118f311
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487409914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1487409914
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.1456805610
Short name	T592
Test name
Test status
Simulation time	197038169 ps
CPU time	18.1 seconds
Started	Apr 28 12:49:52 PM PDT 24
Finished	Apr 28 12:50:11 PM PDT 24
Peak memory	211656 kb
Host	smart-1da8e09a-b23b-4dc2-a47f-0eff5325916e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456805610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1456805610
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.1979223178
Short name	T140
Test name
Test status
Simulation time	417127831 ps
CPU time	3.45 seconds
Started	Apr 28 12:49:51 PM PDT 24
Finished	Apr 28 12:49:55 PM PDT 24
Peak memory	203356 kb
Host	smart-358fbd79-00e0-4de9-9466-4bffe7c90968
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1979223178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1979223178
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.414721251
Short name	T878
Test name
Test status
Simulation time	8886245877 ps
CPU time	26.34 seconds
Started	Apr 28 12:49:54 PM PDT 24
Finished	Apr 28 12:50:21 PM PDT 24
Peak memory	203424 kb
Host	smart-5d33c99c-335e-4a3f-8601-268bd71b4953
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=414721251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.414721251
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.252022046
Short name	T52
Test name
Test status
Simulation time	5333095723 ps
CPU time	22.96 seconds
Started	Apr 28 12:49:52 PM PDT 24
Finished	Apr 28 12:50:16 PM PDT 24
Peak memory	203552 kb
Host	smart-ad046fb2-5103-45b6-966e-eadde80f0606
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=252022046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.252022046
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1905749265
Short name	T512
Test name
Test status
Simulation time	56810324 ps
CPU time	2 seconds
Started	Apr 28 12:49:52 PM PDT 24
Finished	Apr 28 12:49:55 PM PDT 24
Peak memory	203396 kb
Host	smart-bf6ca398-8368-4347-b01c-ac5a41f9fb7c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905749265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1905749265
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.2515712021
Short name	T357
Test name
Test status
Simulation time	1374230502 ps
CPU time	88.78 seconds
Started	Apr 28 12:49:51 PM PDT 24
Finished	Apr 28 12:51:20 PM PDT 24
Peak memory	211648 kb
Host	smart-1b299986-e23a-408d-840d-3f12dc233f21
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2515712021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2515712021
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.504167792
Short name	T845
Test name
Test status
Simulation time	2274845351 ps
CPU time	58.34 seconds
Started	Apr 28 12:49:58 PM PDT 24
Finished	Apr 28 12:50:56 PM PDT 24
Peak memory	205704 kb
Host	smart-27ee38c7-e073-41e3-ad68-493bdfc6136d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=504167792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.504167792
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3082601742
Short name	T139
Test name
Test status
Simulation time	407523670 ps
CPU time	114.62 seconds
Started	Apr 28 12:50:00 PM PDT 24
Finished	Apr 28 12:51:55 PM PDT 24
Peak memory	207868 kb
Host	smart-2f446bfd-3f07-4668-981e-4d454bf2bfec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3082601742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3082601742
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.4182610338
Short name	T479
Test name
Test status
Simulation time	778579094 ps
CPU time	173.11 seconds
Started	Apr 28 12:49:59 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	211572 kb
Host	smart-8a61e194-85f9-45a0-a409-e47889ef963f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4182610338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.4182610338
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3554140742
Short name	T755
Test name
Test status
Simulation time	440789115 ps
CPU time	16.65 seconds
Started	Apr 28 12:49:54 PM PDT 24
Finished	Apr 28 12:50:11 PM PDT 24
Peak memory	205036 kb
Host	smart-42d382e4-dea9-4235-9df3-ec66b32334be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554140742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3554140742
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.229475385
Short name	T214
Test name
Test status
Simulation time	909678857 ps
CPU time	28.38 seconds
Started	Apr 28 12:49:57 PM PDT 24
Finished	Apr 28 12:50:26 PM PDT 24
Peak memory	205188 kb
Host	smart-7a8c5a53-a91f-4016-a263-ec45798a0369
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=229475385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.229475385
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1893948891
Short name	T683
Test name
Test status
Simulation time	82321029721 ps
CPU time	658.76 seconds
Started	Apr 28 12:49:59 PM PDT 24
Finished	Apr 28 01:00:58 PM PDT 24
Peak memory	207084 kb
Host	smart-06c8b160-2451-448d-a799-2e73bacf1a98
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1893948891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1893948891
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4110143079
Short name	T732
Test name
Test status
Simulation time	498495856 ps
CPU time	18.39 seconds
Started	Apr 28 12:50:03 PM PDT 24
Finished	Apr 28 12:50:22 PM PDT 24
Peak memory	203692 kb
Host	smart-979102d7-82eb-47d3-a3d7-be814dba4d44
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4110143079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4110143079
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.1151674813
Short name	T637
Test name
Test status
Simulation time	245314545 ps
CPU time	20.02 seconds
Started	Apr 28 12:50:03 PM PDT 24
Finished	Apr 28 12:50:23 PM PDT 24
Peak memory	203400 kb
Host	smart-6e23b8bd-6826-45ec-99d6-da4315fdb9fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1151674813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1151674813
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.2957829336
Short name	T136
Test name
Test status
Simulation time	1677569859 ps
CPU time	26.98 seconds
Started	Apr 28 12:49:58 PM PDT 24
Finished	Apr 28 12:50:26 PM PDT 24
Peak memory	204500 kb
Host	smart-cb36d8bf-613e-46c6-bd1c-dd2a62320dad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2957829336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2957829336
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1797371227
Short name	T542
Test name
Test status
Simulation time	2942715849 ps
CPU time	19.53 seconds
Started	Apr 28 12:49:58 PM PDT 24
Finished	Apr 28 12:50:18 PM PDT 24
Peak memory	203784 kb
Host	smart-9efd6b81-323b-4839-9244-6f0a2ce51307
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797371227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1797371227
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3975071257
Short name	T826
Test name
Test status
Simulation time	59894371613 ps
CPU time	222.42 seconds
Started	Apr 28 12:50:02 PM PDT 24
Finished	Apr 28 12:53:45 PM PDT 24
Peak memory	204872 kb
Host	smart-84e8a302-2766-4817-8829-9d0fb919a107
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3975071257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3975071257
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3775259222
Short name	T266
Test name
Test status
Simulation time	134636181 ps
CPU time	11.69 seconds
Started	Apr 28 12:49:58 PM PDT 24
Finished	Apr 28 12:50:10 PM PDT 24
Peak memory	204704 kb
Host	smart-8d8542b2-edb0-46a0-bb46-9feb3b78462d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775259222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3775259222
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.138809485
Short name	T809
Test name
Test status
Simulation time	6225170465 ps
CPU time	35.73 seconds
Started	Apr 28 12:50:02 PM PDT 24
Finished	Apr 28 12:50:38 PM PDT 24
Peak memory	211704 kb
Host	smart-114c3049-9f07-43dc-bd8a-f7fec35a0126
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=138809485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.138809485
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.2126457458
Short name	T856
Test name
Test status
Simulation time	156933552 ps
CPU time	2.74 seconds
Started	Apr 28 12:49:58 PM PDT 24
Finished	Apr 28 12:50:01 PM PDT 24
Peak memory	203364 kb
Host	smart-1a559c1d-9e59-4bb6-a785-470b6cae19ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2126457458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2126457458
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1590976815
Short name	T219
Test name
Test status
Simulation time	33034194345 ps
CPU time	48.19 seconds
Started	Apr 28 12:50:00 PM PDT 24
Finished	Apr 28 12:50:48 PM PDT 24
Peak memory	203392 kb
Host	smart-914181cb-39c8-42b5-9fbf-14a46072390b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590976815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1590976815
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1837061167
Short name	T705
Test name
Test status
Simulation time	10665249987 ps
CPU time	37.69 seconds
Started	Apr 28 12:50:00 PM PDT 24
Finished	Apr 28 12:50:38 PM PDT 24
Peak memory	203380 kb
Host	smart-b615b7fe-66b2-4311-86f1-464d97d1f561
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1837061167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1837061167
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1081286178
Short name	T385
Test name
Test status
Simulation time	24047568 ps
CPU time	2.03 seconds
Started	Apr 28 12:49:57 PM PDT 24
Finished	Apr 28 12:49:59 PM PDT 24
Peak memory	203360 kb
Host	smart-08f0a522-2cbd-4485-940b-9b35c2f65b78
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081286178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1081286178
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.500812698
Short name	T753
Test name
Test status
Simulation time	1774726371 ps
CPU time	174.11 seconds
Started	Apr 28 12:50:02 PM PDT 24
Finished	Apr 28 12:52:56 PM PDT 24
Peak memory	211504 kb
Host	smart-a352c2b2-fa82-4e60-aac4-2eb0bc9f9e3e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=500812698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.500812698
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1359092649
Short name	T499
Test name
Test status
Simulation time	3305929265 ps
CPU time	123.72 seconds
Started	Apr 28 12:50:07 PM PDT 24
Finished	Apr 28 12:52:11 PM PDT 24
Peak memory	208884 kb
Host	smart-cdec0d91-efd2-46ed-98f0-7d3c93985967
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1359092649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1359092649
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1420777918
Short name	T584
Test name
Test status
Simulation time	474709684 ps
CPU time	123.01 seconds
Started	Apr 28 12:50:02 PM PDT 24
Finished	Apr 28 12:52:05 PM PDT 24
Peak memory	207268 kb
Host	smart-ec0365f8-f781-44cb-969d-4931b984db4b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1420777918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1420777918
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3073917340
Short name	T360
Test name
Test status
Simulation time	1955466023 ps
CPU time	107.88 seconds
Started	Apr 28 12:50:08 PM PDT 24
Finished	Apr 28 12:51:56 PM PDT 24
Peak memory	208480 kb
Host	smart-8b41c674-d2fa-4cfb-8ef2-203a0fd5bdca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3073917340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3073917340
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3271647955
Short name	T373
Test name
Test status
Simulation time	922746479 ps
CPU time	19.27 seconds
Started	Apr 28 12:50:08 PM PDT 24
Finished	Apr 28 12:50:28 PM PDT 24
Peak memory	204968 kb
Host	smart-dacf33b6-4fe6-4349-b201-fc27767abdfa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3271647955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3271647955
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2342848876
Short name	T115
Test name
Test status
Simulation time	2441289462 ps
CPU time	79.64 seconds
Started	Apr 28 12:50:09 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	207228 kb
Host	smart-e78fcaa9-631e-45d0-a956-0a954f78262e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2342848876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2342848876
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4017312470
Short name	T859
Test name
Test status
Simulation time	47858059552 ps
CPU time	472.36 seconds
Started	Apr 28 12:50:09 PM PDT 24
Finished	Apr 28 12:58:01 PM PDT 24
Peak memory	207216 kb
Host	smart-f2a068cc-754f-43e4-a195-14334e4b3baf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4017312470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.4017312470
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2970018755
Short name	T404
Test name
Test status
Simulation time	397647727 ps
CPU time	8.88 seconds
Started	Apr 28 12:50:14 PM PDT 24
Finished	Apr 28 12:50:23 PM PDT 24
Peak memory	203712 kb
Host	smart-a8ae23b2-6963-4c67-9ef4-fdd80970ce5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970018755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2970018755
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.414634094
Short name	T68
Test name
Test status
Simulation time	1089639330 ps
CPU time	16.72 seconds
Started	Apr 28 12:50:08 PM PDT 24
Finished	Apr 28 12:50:26 PM PDT 24
Peak memory	203496 kb
Host	smart-91987cb7-5e3f-4473-896a-4ae6fcc7ce76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=414634094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.414634094
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.208251185
Short name	T76
Test name
Test status
Simulation time	351186448 ps
CPU time	9.47 seconds
Started	Apr 28 12:50:02 PM PDT 24
Finished	Apr 28 12:50:12 PM PDT 24
Peak memory	204564 kb
Host	smart-27490d87-eb6b-4a76-8a63-bbf5348916ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=208251185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.208251185
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.52807060
Short name	T418
Test name
Test status
Simulation time	17346228994 ps
CPU time	69.6 seconds
Started	Apr 28 12:50:10 PM PDT 24
Finished	Apr 28 12:51:20 PM PDT 24
Peak memory	204680 kb
Host	smart-4c35c6af-4c9e-4157-bf42-878ba7a240dc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=52807060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.52807060
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3039320041
Short name	T702
Test name
Test status
Simulation time	11321849474 ps
CPU time	109.49 seconds
Started	Apr 28 12:50:08 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	205148 kb
Host	smart-5a035ed3-220e-4d86-9edc-884d7d1fa448
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3039320041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3039320041
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.804458392
Short name	T488
Test name
Test status
Simulation time	26254736 ps
CPU time	3.35 seconds
Started	Apr 28 12:50:09 PM PDT 24
Finished	Apr 28 12:50:13 PM PDT 24
Peak memory	204068 kb
Host	smart-28bb9c1f-9f19-4628-908f-4c149fde1cfe
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804458392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.804458392
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.2352987276
Short name	T835
Test name
Test status
Simulation time	3873159636 ps
CPU time	25.13 seconds
Started	Apr 28 12:50:08 PM PDT 24
Finished	Apr 28 12:50:34 PM PDT 24
Peak memory	203608 kb
Host	smart-fb30b0b5-e5d1-4a3b-8906-e38634072de5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2352987276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2352987276
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.3118132625
Short name	T674
Test name
Test status
Simulation time	35875205 ps
CPU time	2.33 seconds
Started	Apr 28 12:50:03 PM PDT 24
Finished	Apr 28 12:50:05 PM PDT 24
Peak memory	203368 kb
Host	smart-46747899-434c-4197-8391-93024e186e59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118132625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3118132625
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1609355266
Short name	T426
Test name
Test status
Simulation time	9872401840 ps
CPU time	27.71 seconds
Started	Apr 28 12:50:04 PM PDT 24
Finished	Apr 28 12:50:32 PM PDT 24
Peak memory	203532 kb
Host	smart-2852ea21-f492-4cce-8a50-02d432e24483
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609355266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1609355266
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1942921842
Short name	T778
Test name
Test status
Simulation time	4043347141 ps
CPU time	24.09 seconds
Started	Apr 28 12:50:04 PM PDT 24
Finished	Apr 28 12:50:29 PM PDT 24
Peak memory	203536 kb
Host	smart-c46c0200-8a9e-45e6-9e6d-a809a70d5676
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1942921842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1942921842
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1792450770
Short name	T897
Test name
Test status
Simulation time	38421997 ps
CPU time	2.12 seconds
Started	Apr 28 12:50:03 PM PDT 24
Finished	Apr 28 12:50:06 PM PDT 24
Peak memory	203484 kb
Host	smart-84a5a4b2-dc88-4ba5-9260-07928af249eb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792450770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1792450770
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.3551452490
Short name	T198
Test name
Test status
Simulation time	377762988 ps
CPU time	40.43 seconds
Started	Apr 28 12:50:15 PM PDT 24
Finished	Apr 28 12:50:56 PM PDT 24
Peak memory	206120 kb
Host	smart-3a723e6a-1d70-48f5-b64b-8b3251580bdd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3551452490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3551452490
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.293597950
Short name	T660
Test name
Test status
Simulation time	1132220145 ps
CPU time	106.2 seconds
Started	Apr 28 12:50:13 PM PDT 24
Finished	Apr 28 12:52:00 PM PDT 24
Peak memory	211536 kb
Host	smart-88ed481d-9e44-4c65-b3b2-309c212f49da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=293597950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.293597950
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2229091449
Short name	T651
Test name
Test status
Simulation time	6371526381 ps
CPU time	320.84 seconds
Started	Apr 28 12:50:17 PM PDT 24
Finished	Apr 28 12:55:38 PM PDT 24
Peak memory	211004 kb
Host	smart-f2c2a639-e106-4448-914f-ca3957506263
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2229091449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.2229091449
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.349434578
Short name	T154
Test name
Test status
Simulation time	5750367235 ps
CPU time	179.15 seconds
Started	Apr 28 12:50:13 PM PDT 24
Finished	Apr 28 12:53:13 PM PDT 24
Peak memory	210248 kb
Host	smart-2e99e8c5-2a6c-48c5-9f38-d57b42e59b88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=349434578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.349434578
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1912342341
Short name	T571
Test name
Test status
Simulation time	1339227866 ps
CPU time	30.21 seconds
Started	Apr 28 12:50:08 PM PDT 24
Finished	Apr 28 12:50:39 PM PDT 24
Peak memory	205116 kb
Host	smart-cc3803e0-a246-4db4-adfb-9e8880adb944
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1912342341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1912342341
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1984518942
Short name	T105
Test name
Test status
Simulation time	138018717 ps
CPU time	6.32 seconds
Started	Apr 28 12:50:13 PM PDT 24
Finished	Apr 28 12:50:20 PM PDT 24
Peak memory	204464 kb
Host	smart-049e4deb-68d4-43ed-9d7e-32af048a78aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1984518942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1984518942
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1777917216
Short name	T686
Test name
Test status
Simulation time	9705517102 ps
CPU time	32.8 seconds
Started	Apr 28 12:50:12 PM PDT 24
Finished	Apr 28 12:50:45 PM PDT 24
Peak memory	203996 kb
Host	smart-523da984-22aa-4645-8e4f-886e171267ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1777917216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.1777917216
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2177333738
Short name	T9
Test name
Test status
Simulation time	207266730 ps
CPU time	9.5 seconds
Started	Apr 28 12:50:20 PM PDT 24
Finished	Apr 28 12:50:30 PM PDT 24
Peak memory	203832 kb
Host	smart-e60d650c-7a9b-4795-b784-5ed042b362e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2177333738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2177333738
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.3348653532
Short name	T541
Test name
Test status
Simulation time	335272718 ps
CPU time	12.77 seconds
Started	Apr 28 12:50:13 PM PDT 24
Finished	Apr 28 12:50:27 PM PDT 24
Peak memory	203404 kb
Host	smart-feee6ec8-ccae-4774-98bc-2df9138aa2f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3348653532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3348653532
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.695396141
Short name	T704
Test name
Test status
Simulation time	1758381697 ps
CPU time	29.85 seconds
Started	Apr 28 12:50:15 PM PDT 24
Finished	Apr 28 12:50:46 PM PDT 24
Peak memory	204600 kb
Host	smart-97b35c1e-0bd9-4c47-b79d-561858c16e22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695396141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.695396141
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.620550402
Short name	T378
Test name
Test status
Simulation time	38409145240 ps
CPU time	186.47 seconds
Started	Apr 28 12:50:15 PM PDT 24
Finished	Apr 28 12:53:22 PM PDT 24
Peak memory	204924 kb
Host	smart-f82af5a1-06d1-43fe-bc81-a3f196600000
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=620550402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.620550402
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4155649205
Short name	T218
Test name
Test status
Simulation time	22469614557 ps
CPU time	199.82 seconds
Started	Apr 28 12:50:15 PM PDT 24
Finished	Apr 28 12:53:36 PM PDT 24
Peak memory	205652 kb
Host	smart-f7ef8918-723a-4d21-b70a-0a569da1e7c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4155649205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4155649205
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3776664539
Short name	T119
Test name
Test status
Simulation time	48331651 ps
CPU time	5.95 seconds
Started	Apr 28 12:50:16 PM PDT 24
Finished	Apr 28 12:50:22 PM PDT 24
Peak memory	204624 kb
Host	smart-076a4efd-1006-4a34-9ec8-d7014c770350
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776664539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3776664539
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.1226518706
Short name	T530
Test name
Test status
Simulation time	762037802 ps
CPU time	13.51 seconds
Started	Apr 28 12:50:14 PM PDT 24
Finished	Apr 28 12:50:28 PM PDT 24
Peak memory	204076 kb
Host	smart-750dfee0-c9d3-4a4c-9ced-fb89296ee350
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1226518706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1226518706
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.2254339676
Short name	T848
Test name
Test status
Simulation time	258106285 ps
CPU time	3.14 seconds
Started	Apr 28 12:50:17 PM PDT 24
Finished	Apr 28 12:50:21 PM PDT 24
Peak memory	203484 kb
Host	smart-295fea53-afcc-45d3-b9af-c0412a185b6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2254339676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2254339676
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.848858773
Short name	T857
Test name
Test status
Simulation time	4724157678 ps
CPU time	28.48 seconds
Started	Apr 28 12:50:14 PM PDT 24
Finished	Apr 28 12:50:43 PM PDT 24
Peak memory	203532 kb
Host	smart-6340bc90-0cb2-421b-987c-0e1dd2b12e37
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=848858773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.848858773
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3610298922
Short name	T682
Test name
Test status
Simulation time	2155180934 ps
CPU time	20.58 seconds
Started	Apr 28 12:50:13 PM PDT 24
Finished	Apr 28 12:50:35 PM PDT 24
Peak memory	203456 kb
Host	smart-a2de2149-ce61-4c23-8210-8942b69351a8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3610298922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3610298922
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.108500176
Short name	T738
Test name
Test status
Simulation time	38908085 ps
CPU time	2.43 seconds
Started	Apr 28 12:50:15 PM PDT 24
Finished	Apr 28 12:50:19 PM PDT 24
Peak memory	203380 kb
Host	smart-93593288-76f9-4090-b5b5-671055d1712f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108500176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.108500176
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.3608667499
Short name	T333
Test name
Test status
Simulation time	8002688634 ps
CPU time	54.05 seconds
Started	Apr 28 12:50:17 PM PDT 24
Finished	Apr 28 12:51:11 PM PDT 24
Peak memory	205892 kb
Host	smart-a741e1b2-cb05-444e-b2eb-e7da67af8d1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3608667499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3608667499
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2664573040
Short name	T653
Test name
Test status
Simulation time	4242781671 ps
CPU time	107.69 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:52:07 PM PDT 24
Peak memory	205304 kb
Host	smart-b18afa6a-fc0d-459c-93cd-ee4f3b43ce67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664573040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2664573040
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3083405778
Short name	T96
Test name
Test status
Simulation time	260575607 ps
CPU time	96.52 seconds
Started	Apr 28 12:50:16 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	208040 kb
Host	smart-93d45cbf-17d5-49e3-b6c1-e2089bda5256
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3083405778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.3083405778
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.346101785
Short name	T804
Test name
Test status
Simulation time	4364063921 ps
CPU time	119.55 seconds
Started	Apr 28 12:50:17 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	209052 kb
Host	smart-9de4d118-998f-47eb-a6f5-8493c041c978
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=346101785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_res et_error.346101785
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.726944430
Short name	T30
Test name
Test status
Simulation time	44856788 ps
CPU time	4.95 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:50:23 PM PDT 24
Peak memory	204936 kb
Host	smart-0720f9cf-18aa-4f5c-8442-4d98d8902e3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726944430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.726944430
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.4040708606
Short name	T475
Test name
Test status
Simulation time	56136614 ps
CPU time	7 seconds
Started	Apr 28 12:50:20 PM PDT 24
Finished	Apr 28 12:50:28 PM PDT 24
Peak memory	204536 kb
Host	smart-d0ab094e-67fd-49f4-9013-5fbd721fd064
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040708606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.4040708606
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3619792051
Short name	T847
Test name
Test status
Simulation time	47491926 ps
CPU time	2.17 seconds
Started	Apr 28 12:50:24 PM PDT 24
Finished	Apr 28 12:50:27 PM PDT 24
Peak memory	203476 kb
Host	smart-110c494a-e560-4f5a-b014-55869f4856b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3619792051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3619792051
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.2457335297
Short name	T363
Test name
Test status
Simulation time	84962422 ps
CPU time	6.73 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:50:26 PM PDT 24
Peak memory	203492 kb
Host	smart-8bf44569-dc7b-4bfc-a4c0-5aceedeab6c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2457335297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2457335297
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.2242906245
Short name	T419
Test name
Test status
Simulation time	216114991 ps
CPU time	26.11 seconds
Started	Apr 28 12:50:20 PM PDT 24
Finished	Apr 28 12:50:47 PM PDT 24
Peak memory	204840 kb
Host	smart-8491dee6-d5dc-4e30-884d-c4e4034de34b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2242906245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2242906245
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3888801295
Short name	T839
Test name
Test status
Simulation time	29174444202 ps
CPU time	177.28 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	204696 kb
Host	smart-0a324ff0-8305-40ac-9243-0d9fc04cc0c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888801295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3888801295
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3202447360
Short name	T484
Test name
Test status
Simulation time	31632430515 ps
CPU time	220.99 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:54:00 PM PDT 24
Peak memory	211728 kb
Host	smart-124ac18f-21fd-40f8-84d5-a510c770cee2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3202447360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3202447360
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3892358066
Short name	T684
Test name
Test status
Simulation time	176061280 ps
CPU time	6.9 seconds
Started	Apr 28 12:50:20 PM PDT 24
Finished	Apr 28 12:50:28 PM PDT 24
Peak memory	204572 kb
Host	smart-136afdc4-cd26-4c22-a2ee-5248f589c770
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892358066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3892358066
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.3015608990
Short name	T261
Test name
Test status
Simulation time	130411200 ps
CPU time	9 seconds
Started	Apr 28 12:50:19 PM PDT 24
Finished	Apr 28 12:50:28 PM PDT 24
Peak memory	203500 kb
Host	smart-24c393d4-9048-4762-9031-5df0808c39d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3015608990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3015608990
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.219488388
Short name	T800
Test name
Test status
Simulation time	1003543054 ps
CPU time	3.57 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:50:22 PM PDT 24
Peak memory	203452 kb
Host	smart-37e1c80c-c151-4720-a54e-df2221fca384
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=219488388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.219488388
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3419476853
Short name	T891
Test name
Test status
Simulation time	12358746440 ps
CPU time	27.55 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:50:47 PM PDT 24
Peak memory	203424 kb
Host	smart-692cb345-deff-4630-91f7-a119747e1fd8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419476853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3419476853
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3545166432
Short name	T60
Test name
Test status
Simulation time	22864990364 ps
CPU time	39.65 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:50:59 PM PDT 24
Peak memory	203368 kb
Host	smart-0374929a-0ddc-42d0-90dd-cc39cfa42141
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3545166432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3545166432
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3212884124
Short name	T358
Test name
Test status
Simulation time	29161994 ps
CPU time	2.37 seconds
Started	Apr 28 12:50:20 PM PDT 24
Finished	Apr 28 12:50:22 PM PDT 24
Peak memory	203484 kb
Host	smart-6a1d3d23-1fe3-4cca-9a36-28ab22894af7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212884124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3212884124
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.530087931
Short name	T739
Test name
Test status
Simulation time	5194036308 ps
CPU time	65.8 seconds
Started	Apr 28 12:50:23 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	207752 kb
Host	smart-a3949fc2-7504-469b-903d-0293b021d7a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=530087931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.530087931
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.290735603
Short name	T860
Test name
Test status
Simulation time	36154751951 ps
CPU time	241.53 seconds
Started	Apr 28 12:50:25 PM PDT 24
Finished	Apr 28 12:54:26 PM PDT 24
Peak memory	209084 kb
Host	smart-557df92e-bea3-4153-9903-ca629ad2f263
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=290735603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.290735603
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3727252858
Short name	T35
Test name
Test status
Simulation time	239101169 ps
CPU time	130.92 seconds
Started	Apr 28 12:50:22 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	207844 kb
Host	smart-20e8c15c-3207-4b36-917d-743ee4d28989
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3727252858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3727252858
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1856085924
Short name	T723
Test name
Test status
Simulation time	8694402456 ps
CPU time	308 seconds
Started	Apr 28 12:50:28 PM PDT 24
Finished	Apr 28 12:55:37 PM PDT 24
Peak memory	219948 kb
Host	smart-916f5b82-3926-4697-9697-19f92ba43c92
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1856085924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1856085924
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3254880506
Short name	T511
Test name
Test status
Simulation time	700406607 ps
CPU time	20.23 seconds
Started	Apr 28 12:50:18 PM PDT 24
Finished	Apr 28 12:50:39 PM PDT 24
Peak memory	204880 kb
Host	smart-2fa53fb9-3834-4f33-8cad-5a901dd8ab4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3254880506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3254880506
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1463408686
Short name	T865
Test name
Test status
Simulation time	2195858006 ps
CPU time	28.37 seconds
Started	Apr 28 12:50:27 PM PDT 24
Finished	Apr 28 12:50:56 PM PDT 24
Peak memory	205964 kb
Host	smart-4dd1449f-90c7-4ff9-8d7c-1cfb08c3d2ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1463408686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1463408686
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3530782282
Short name	T126
Test name
Test status
Simulation time	176206549219 ps
CPU time	722.7 seconds
Started	Apr 28 12:50:26 PM PDT 24
Finished	Apr 28 01:02:29 PM PDT 24
Peak memory	207572 kb
Host	smart-6380a573-0095-409b-a257-fc3108d2c2b6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3530782282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.3530782282
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2065340568
Short name	T429
Test name
Test status
Simulation time	729860816 ps
CPU time	15.16 seconds
Started	Apr 28 12:50:26 PM PDT 24
Finished	Apr 28 12:50:42 PM PDT 24
Peak memory	203488 kb
Host	smart-a6895158-9763-4068-bcd3-04a157a4d387
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2065340568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2065340568
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.3374088412
Short name	T625
Test name
Test status
Simulation time	316487335 ps
CPU time	18.65 seconds
Started	Apr 28 12:50:27 PM PDT 24
Finished	Apr 28 12:50:46 PM PDT 24
Peak memory	203420 kb
Host	smart-7ad24b67-b24e-4418-9ce5-863b642bbdd3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3374088412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3374088412
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.877732971
Short name	T806
Test name
Test status
Simulation time	518468792 ps
CPU time	22.02 seconds
Started	Apr 28 12:50:23 PM PDT 24
Finished	Apr 28 12:50:45 PM PDT 24
Peak memory	204560 kb
Host	smart-11b39c17-aec8-4a10-aecd-1d1dda19c4f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=877732971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.877732971
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2393772054
Short name	T880
Test name
Test status
Simulation time	16175847414 ps
CPU time	99.61 seconds
Started	Apr 28 12:50:28 PM PDT 24
Finished	Apr 28 12:52:08 PM PDT 24
Peak memory	204804 kb
Host	smart-762d8bb3-4d15-4f43-8b13-f09a76323546
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393772054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2393772054
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4131037908
Short name	T44
Test name
Test status
Simulation time	8312091485 ps
CPU time	71.63 seconds
Started	Apr 28 12:50:29 PM PDT 24
Finished	Apr 28 12:51:41 PM PDT 24
Peak memory	204628 kb
Host	smart-c3048a9c-ff68-4c21-8a11-7eb365d801a2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4131037908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4131037908
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3831971771
Short name	T501
Test name
Test status
Simulation time	45311414 ps
CPU time	5.52 seconds
Started	Apr 28 12:50:23 PM PDT 24
Finished	Apr 28 12:50:29 PM PDT 24
Peak memory	211520 kb
Host	smart-76d1a24d-b0a6-4782-809f-7929182ff68e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831971771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3831971771
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.2808220593
Short name	T221
Test name
Test status
Simulation time	325763341 ps
CPU time	13.12 seconds
Started	Apr 28 12:50:28 PM PDT 24
Finished	Apr 28 12:50:41 PM PDT 24
Peak memory	203984 kb
Host	smart-c1740931-39d4-45df-bdeb-c6b1e9e97889
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2808220593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2808220593
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.2520254516
Short name	T521
Test name
Test status
Simulation time	123221361 ps
CPU time	3.59 seconds
Started	Apr 28 12:50:25 PM PDT 24
Finished	Apr 28 12:50:29 PM PDT 24
Peak memory	203380 kb
Host	smart-3b82a5cb-62a8-455f-98b7-4fd1387b9115
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2520254516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2520254516
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2184926343
Short name	T699
Test name
Test status
Simulation time	15881101372 ps
CPU time	34.92 seconds
Started	Apr 28 12:50:23 PM PDT 24
Finished	Apr 28 12:50:59 PM PDT 24
Peak memory	203396 kb
Host	smart-effd91c2-4b3f-43b4-ba5a-df15f9c9b8f4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184926343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2184926343
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.684648314
Short name	T678
Test name
Test status
Simulation time	5753503487 ps
CPU time	29.83 seconds
Started	Apr 28 12:50:23 PM PDT 24
Finished	Apr 28 12:50:53 PM PDT 24
Peak memory	203552 kb
Host	smart-032b84f7-56ee-4442-8968-851e701f67e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=684648314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.684648314
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.39046101
Short name	T636
Test name
Test status
Simulation time	29281595 ps
CPU time	2.45 seconds
Started	Apr 28 12:50:22 PM PDT 24
Finished	Apr 28 12:50:24 PM PDT 24
Peak memory	203460 kb
Host	smart-2b45aff6-0b03-4fe1-b0eb-efd39a1fa5fe
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.39046101
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.3017316386
Short name	T443
Test name
Test status
Simulation time	7116029906 ps
CPU time	220.12 seconds
Started	Apr 28 12:50:29 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	207336 kb
Host	smart-1dbab83b-8a72-42bf-9299-ee6facf70113
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3017316386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3017316386
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.556998036
Short name	T294
Test name
Test status
Simulation time	1924671277 ps
CPU time	45.32 seconds
Started	Apr 28 12:50:29 PM PDT 24
Finished	Apr 28 12:51:15 PM PDT 24
Peak memory	205096 kb
Host	smart-7cedcc3c-9818-4a5f-bd29-70a81cf10ec1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=556998036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.556998036
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1833092895
Short name	T586
Test name
Test status
Simulation time	83869595 ps
CPU time	14.35 seconds
Started	Apr 28 12:50:29 PM PDT 24
Finished	Apr 28 12:50:44 PM PDT 24
Peak memory	206308 kb
Host	smart-4b3c7b5b-13c4-493d-ab84-f07d7e47c1a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1833092895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1833092895
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1836287485
Short name	T466
Test name
Test status
Simulation time	2262926462 ps
CPU time	140.97 seconds
Started	Apr 28 12:50:26 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	209848 kb
Host	smart-3652296a-aac4-4e4c-9b00-3c710f920843
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1836287485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.1836287485
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2990997817
Short name	T322
Test name
Test status
Simulation time	106726333 ps
CPU time	12.12 seconds
Started	Apr 28 12:50:29 PM PDT 24
Finished	Apr 28 12:50:41 PM PDT 24
Peak memory	211548 kb
Host	smart-d7220ef9-ec33-4b55-914d-7636ce0c218e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990997817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2990997817
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.486286191
Short name	T785
Test name
Test status
Simulation time	44462249 ps
CPU time	3.44 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:08 PM PDT 24
Peak memory	203444 kb
Host	smart-0d2e19ca-192a-4611-9e0e-d45e272f487e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=486286191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.486286191
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3003744900
Short name	T523
Test name
Test status
Simulation time	76851927967 ps
CPU time	606.75 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:57:12 PM PDT 24
Peak memory	211684 kb
Host	smart-61d97180-e6e7-4aa5-b01f-4124f384fe9f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3003744900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3003744900
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4090694107
Short name	T727
Test name
Test status
Simulation time	558575217 ps
CPU time	18.06 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:10 PM PDT 24
Peak memory	204232 kb
Host	smart-50fb4b77-9c08-48f8-9e5d-a78cfb77c7f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090694107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4090694107
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.1788504789
Short name	T886
Test name
Test status
Simulation time	329801567 ps
CPU time	9.18 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:14 PM PDT 24
Peak memory	203380 kb
Host	smart-e11b2707-5975-4b3f-89d8-af483443f01c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1788504789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1788504789
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.3241727646
Short name	T309
Test name
Test status
Simulation time	2066781850 ps
CPU time	32.87 seconds
Started	Apr 28 12:46:53 PM PDT 24
Finished	Apr 28 12:47:27 PM PDT 24
Peak memory	204720 kb
Host	smart-11276831-7776-4194-830f-187ca4a1d36e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3241727646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3241727646
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2990662357
Short name	T314
Test name
Test status
Simulation time	27381575676 ps
CPU time	175.99 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:50:02 PM PDT 24
Peak memory	204680 kb
Host	smart-175df39a-f465-434c-96a4-956eafc158ce
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990662357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2990662357
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2844623136
Short name	T112
Test name
Test status
Simulation time	41533496038 ps
CPU time	262.13 seconds
Started	Apr 28 12:46:50 PM PDT 24
Finished	Apr 28 12:51:13 PM PDT 24
Peak memory	205032 kb
Host	smart-ff925fe7-941c-4d26-b35a-a776c9bcace3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2844623136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2844623136
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2286043755
Short name	T744
Test name
Test status
Simulation time	404243002 ps
CPU time	24.85 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:17 PM PDT 24
Peak memory	204800 kb
Host	smart-cc431f98-aabd-48f2-9a85-cb9b2af2b818
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286043755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2286043755
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.2651603234
Short name	T243
Test name
Test status
Simulation time	651687191 ps
CPU time	21.7 seconds
Started	Apr 28 12:46:53 PM PDT 24
Finished	Apr 28 12:47:16 PM PDT 24
Peak memory	204092 kb
Host	smart-2f716fe1-2393-4de8-a19e-ef630bc40500
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2651603234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2651603234
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.3830377681
Short name	T207
Test name
Test status
Simulation time	26484728 ps
CPU time	2.34 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:08 PM PDT 24
Peak memory	203336 kb
Host	smart-1d59596c-fc84-40ed-bdf2-cc9f30a0da84
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3830377681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3830377681
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.793940075
Short name	T817
Test name
Test status
Simulation time	11950997096 ps
CPU time	29.56 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:22 PM PDT 24
Peak memory	203504 kb
Host	smart-8336958a-b514-49be-b7c3-02a6f5782097
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=793940075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.793940075
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2826301950
Short name	T757
Test name
Test status
Simulation time	6301932671 ps
CPU time	34.71 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:47:25 PM PDT 24
Peak memory	203524 kb
Host	smart-0b730ae2-5af4-4233-8272-c92fbb52858c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2826301950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2826301950
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.504290963
Short name	T209
Test name
Test status
Simulation time	45039796 ps
CPU time	2.27 seconds
Started	Apr 28 12:46:50 PM PDT 24
Finished	Apr 28 12:46:54 PM PDT 24
Peak memory	203480 kb
Host	smart-af557066-c427-4700-b0a2-7b219fccdf27
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504290963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.504290963
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.1474986138
Short name	T84
Test name
Test status
Simulation time	5810378079 ps
CPU time	212.73 seconds
Started	Apr 28 12:46:56 PM PDT 24
Finished	Apr 28 12:50:30 PM PDT 24
Peak memory	211696 kb
Host	smart-b4ee5c17-999b-4ed5-9529-550070490591
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1474986138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1474986138
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4127184736
Short name	T361
Test name
Test status
Simulation time	6688740159 ps
CPU time	173.95 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:49:57 PM PDT 24
Peak memory	206720 kb
Host	smart-df38fa0e-13dd-4cb3-bc03-e901963181ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4127184736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4127184736
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2111498339
Short name	T497
Test name
Test status
Simulation time	2976100524 ps
CPU time	447.98 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:54:34 PM PDT 24
Peak memory	208772 kb
Host	smart-b18d681e-a758-4ea6-83e3-f1d9d60ae80e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2111498339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2111498339
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2655371443
Short name	T40
Test name
Test status
Simulation time	211160476 ps
CPU time	70.95 seconds
Started	Apr 28 12:46:53 PM PDT 24
Finished	Apr 28 12:48:04 PM PDT 24
Peak memory	208248 kb
Host	smart-e5fdacde-80de-4157-a0b9-ad1a3bb751f8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2655371443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.2655371443
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2637222135
Short name	T280
Test name
Test status
Simulation time	31537401 ps
CPU time	1.91 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:46:54 PM PDT 24
Peak memory	203488 kb
Host	smart-23c41128-1e36-4f2e-af70-33cc8427b4fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2637222135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2637222135
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1501335072
Short name	T200
Test name
Test status
Simulation time	1356393444 ps
CPU time	22.79 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:30 PM PDT 24
Peak memory	205856 kb
Host	smart-fdf1fc48-c40c-4cdb-8a4b-21b725ce7812
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1501335072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1501335072
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1005211611
Short name	T868
Test name
Test status
Simulation time	26946092778 ps
CPU time	225.3 seconds
Started	Apr 28 12:46:49 PM PDT 24
Finished	Apr 28 12:50:35 PM PDT 24
Peak memory	205988 kb
Host	smart-3910403d-b415-497f-a9ce-e0ebdc83320a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1005211611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1005211611
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2102915006
Short name	T65
Test name
Test status
Simulation time	52596564 ps
CPU time	2.33 seconds
Started	Apr 28 12:46:50 PM PDT 24
Finished	Apr 28 12:46:54 PM PDT 24
Peak memory	203500 kb
Host	smart-a6a4f6ed-7a10-4ac4-9683-14a1a9774a2d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2102915006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2102915006
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.424509704
Short name	T591
Test name
Test status
Simulation time	7335448042 ps
CPU time	37.17 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:43 PM PDT 24
Peak memory	203764 kb
Host	smart-9b1c8ca3-77c8-4006-921f-f11005aa2789
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424509704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.424509704
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.1637294814
Short name	T579
Test name
Test status
Simulation time	946114324 ps
CPU time	22.51 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	211524 kb
Host	smart-8e3d4509-b37a-46dc-9c8d-c99ffba245f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1637294814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1637294814
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.645566108
Short name	T97
Test name
Test status
Simulation time	58378775829 ps
CPU time	109.18 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:48:55 PM PDT 24
Peak memory	204688 kb
Host	smart-36b5e3fe-9c61-4c65-8c14-307bdffe5e59
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=645566108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.645566108
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1073070533
Short name	T130
Test name
Test status
Simulation time	25020675057 ps
CPU time	209.56 seconds
Started	Apr 28 12:46:53 PM PDT 24
Finished	Apr 28 12:50:23 PM PDT 24
Peak memory	211652 kb
Host	smart-d0f44c04-6cd8-4ef5-8176-35f45fedefb4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1073070533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1073070533
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1990064954
Short name	T270
Test name
Test status
Simulation time	44998811 ps
CPU time	4.55 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:10 PM PDT 24
Peak memory	204396 kb
Host	smart-8ae35678-d73a-4a70-8a99-c86961874ab5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990064954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1990064954
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.3563462083
Short name	T553
Test name
Test status
Simulation time	1251969829 ps
CPU time	27.12 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:20 PM PDT 24
Peak memory	211644 kb
Host	smart-34d9ebb7-a8c2-409f-bfb4-5362ca483ac0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3563462083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3563462083
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.4289445043
Short name	T510
Test name
Test status
Simulation time	111866423 ps
CPU time	3.06 seconds
Started	Apr 28 12:46:50 PM PDT 24
Finished	Apr 28 12:46:54 PM PDT 24
Peak memory	203468 kb
Host	smart-79bac5db-74a8-4475-9385-680dbfd89e5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4289445043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.4289445043
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4255926163
Short name	T272
Test name
Test status
Simulation time	7237237760 ps
CPU time	32.83 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:47:25 PM PDT 24
Peak memory	203556 kb
Host	smart-0fb25ebf-7f7a-4c89-83cd-0ad7dbb813c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255926163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4255926163
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3810305391
Short name	T577
Test name
Test status
Simulation time	4376819632 ps
CPU time	35.26 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:41 PM PDT 24
Peak memory	203560 kb
Host	smart-b9b8fea4-f135-4c95-aaa2-fbf33218b52e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3810305391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3810305391
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.4081267447
Short name	T802
Test name
Test status
Simulation time	175405477 ps
CPU time	2.5 seconds
Started	Apr 28 12:46:51 PM PDT 24
Finished	Apr 28 12:46:55 PM PDT 24
Peak memory	203364 kb
Host	smart-159740ac-c552-4d9e-97e8-1a69338dc28a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081267447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4081267447
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.1032489082
Short name	T737
Test name
Test status
Simulation time	809208576 ps
CPU time	68.96 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:48:16 PM PDT 24
Peak memory	206872 kb
Host	smart-10eff155-11d7-4054-adce-9eeb303023b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1032489082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1032489082
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1110492945
Short name	T610
Test name
Test status
Simulation time	6143414349 ps
CPU time	208.78 seconds
Started	Apr 28 12:46:56 PM PDT 24
Finished	Apr 28 12:50:25 PM PDT 24
Peak memory	206948 kb
Host	smart-58b19464-8558-4289-aedc-9f041ea9e840
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1110492945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1110492945
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1228725590
Short name	T82
Test name
Test status
Simulation time	4335744243 ps
CPU time	173.9 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:50:01 PM PDT 24
Peak memory	209584 kb
Host	smart-12e0d38f-e3ea-466b-935f-8698324d462b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228725590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1228725590
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3152994343
Short name	T297
Test name
Test status
Simulation time	335426382 ps
CPU time	12.69 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:47:20 PM PDT 24
Peak memory	211524 kb
Host	smart-fc640beb-b222-4201-bc32-ed62d1d4b985
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3152994343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3152994343
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.352535376
Short name	T735
Test name
Test status
Simulation time	37362333 ps
CPU time	5.59 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:12 PM PDT 24
Peak memory	203872 kb
Host	smart-66391a6a-0bea-47a2-899c-28bf9b43a232
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=352535376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.352535376
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3974118740
Short name	T109
Test name
Test status
Simulation time	398076400987 ps
CPU time	714.17 seconds
Started	Apr 28 12:46:55 PM PDT 24
Finished	Apr 28 12:58:50 PM PDT 24
Peak memory	211732 kb
Host	smart-25c4b81c-9dc5-430f-8985-19ca107e9b78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3974118740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3974118740
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2907534234
Short name	T255
Test name
Test status
Simulation time	785071100 ps
CPU time	26.08 seconds
Started	Apr 28 12:47:08 PM PDT 24
Finished	Apr 28 12:47:35 PM PDT 24
Peak memory	204148 kb
Host	smart-a1c9bff8-86f5-45fe-aa22-6b47716718e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2907534234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2907534234
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.3480115766
Short name	T508
Test name
Test status
Simulation time	665726491 ps
CPU time	22.33 seconds
Started	Apr 28 12:47:00 PM PDT 24
Finished	Apr 28 12:47:23 PM PDT 24
Peak memory	203488 kb
Host	smart-61b76a79-97fc-402d-9891-bf54effed200
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3480115766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3480115766
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.163636740
Short name	T409
Test name
Test status
Simulation time	255319042 ps
CPU time	2.86 seconds
Started	Apr 28 12:46:54 PM PDT 24
Finished	Apr 28 12:46:58 PM PDT 24
Peak memory	203500 kb
Host	smart-c6dd4055-9bd1-444f-90e7-806192c36948
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=163636740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.163636740
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.4244813833
Short name	T539
Test name
Test status
Simulation time	15138764152 ps
CPU time	53.5 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:48:01 PM PDT 24
Peak memory	211588 kb
Host	smart-ca630499-a169-4caa-9832-7ba5802e0601
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244813833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4244813833
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1135700641
Short name	T561
Test name
Test status
Simulation time	50949183859 ps
CPU time	202.61 seconds
Started	Apr 28 12:46:55 PM PDT 24
Finished	Apr 28 12:50:18 PM PDT 24
Peak memory	205100 kb
Host	smart-4a65fcb4-40d3-4a97-b185-134e5ab876c6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1135700641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1135700641
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1341824897
Short name	T3
Test name
Test status
Simulation time	1147600076 ps
CPU time	30.27 seconds
Started	Apr 28 12:46:53 PM PDT 24
Finished	Apr 28 12:47:24 PM PDT 24
Peak memory	204660 kb
Host	smart-5a570304-8062-4513-8170-e34c502adc9c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341824897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1341824897
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.1112813656
Short name	T248
Test name
Test status
Simulation time	345086295 ps
CPU time	16.57 seconds
Started	Apr 28 12:46:54 PM PDT 24
Finished	Apr 28 12:47:12 PM PDT 24
Peak memory	204076 kb
Host	smart-8a12987d-b948-4e9c-a4c8-ee5d346c089f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1112813656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1112813656
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.2341373646
Short name	T334
Test name
Test status
Simulation time	310527709 ps
CPU time	3.3 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:09 PM PDT 24
Peak memory	203352 kb
Host	smart-6acfc57e-6c61-46ba-987e-9826d7d5385b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2341373646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2341373646
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1522838708
Short name	T387
Test name
Test status
Simulation time	5572583644 ps
CPU time	33.07 seconds
Started	Apr 28 12:46:55 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	203556 kb
Host	smart-95f4c375-af54-486c-9bab-b7f9f5626830
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522838708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1522838708
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3170434679
Short name	T346
Test name
Test status
Simulation time	13963103983 ps
CPU time	37.29 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:44 PM PDT 24
Peak memory	203364 kb
Host	smart-a4722e0a-0064-41bc-a4df-e44721d80848
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3170434679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3170434679
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3954633572
Short name	T866
Test name
Test status
Simulation time	36724506 ps
CPU time	2.28 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:09 PM PDT 24
Peak memory	203484 kb
Host	smart-00b3c890-efb6-409d-9943-761451d3cdcd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954633572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3954633572
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.1584948383
Short name	T168
Test name
Test status
Simulation time	1731175914 ps
CPU time	40.32 seconds
Started	Apr 28 12:47:00 PM PDT 24
Finished	Apr 28 12:47:41 PM PDT 24
Peak memory	205652 kb
Host	smart-e11f9fb6-c3d0-41f4-9e35-bd096aa1b6a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1584948383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1584948383
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1597058902
Short name	T25
Test name
Test status
Simulation time	242838745 ps
CPU time	18.33 seconds
Started	Apr 28 12:47:12 PM PDT 24
Finished	Apr 28 12:47:32 PM PDT 24
Peak memory	204508 kb
Host	smart-b997d384-9890-49ee-a2af-21c6cd6f8f6c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1597058902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1597058902
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.173344510
Short name	T672
Test name
Test status
Simulation time	6471087178 ps
CPU time	197.8 seconds
Started	Apr 28 12:47:10 PM PDT 24
Finished	Apr 28 12:50:29 PM PDT 24
Peak memory	209636 kb
Host	smart-4936afc0-dd33-4ab4-a22a-db678ce4b9ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173344510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.173344510
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2578390107
Short name	T765
Test name
Test status
Simulation time	4036434107 ps
CPU time	178.53 seconds
Started	Apr 28 12:47:08 PM PDT 24
Finished	Apr 28 12:50:07 PM PDT 24
Peak memory	210772 kb
Host	smart-f3f8da32-d89d-4797-b640-f946cae041f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2578390107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2578390107
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.4168086704
Short name	T855
Test name
Test status
Simulation time	32992838 ps
CPU time	3.99 seconds
Started	Apr 28 12:47:03 PM PDT 24
Finished	Apr 28 12:47:10 PM PDT 24
Peak memory	204832 kb
Host	smart-132c1dd6-7164-4d89-8556-6fb75955a4de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4168086704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4168086704
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1419627136
Short name	T644
Test name
Test status
Simulation time	1689382005 ps
CPU time	51.66 seconds
Started	Apr 28 12:47:10 PM PDT 24
Finished	Apr 28 12:48:03 PM PDT 24
Peak memory	211564 kb
Host	smart-20b9debb-4974-4e11-885e-797835ec244e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1419627136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1419627136
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3199457856
Short name	T228
Test name
Test status
Simulation time	93482584377 ps
CPU time	352.91 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:53:11 PM PDT 24
Peak memory	206816 kb
Host	smart-866dd5ff-73af-4179-be89-9e6f18811911
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3199457856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3199457856
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1049848242
Short name	T797
Test name
Test status
Simulation time	510212883 ps
CPU time	14.62 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:47:18 PM PDT 24
Peak memory	203632 kb
Host	smart-2803b9fe-008d-41e4-a999-eb1fa3e6cd22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1049848242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1049848242
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.3101373470
Short name	T576
Test name
Test status
Simulation time	1230563632 ps
CPU time	28.09 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:47:31 PM PDT 24
Peak memory	203476 kb
Host	smart-7b05b073-1e8a-4c06-b129-3b53a0de2fab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3101373470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3101373470
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.2322010632
Short name	T676
Test name
Test status
Simulation time	717583601 ps
CPU time	23.32 seconds
Started	Apr 28 12:47:07 PM PDT 24
Finished	Apr 28 12:47:31 PM PDT 24
Peak memory	204492 kb
Host	smart-072b8bc4-be7f-4012-a26d-b47c044d399e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322010632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2322010632
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3640021485
Short name	T172
Test name
Test status
Simulation time	32432013426 ps
CPU time	203.9 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:50:26 PM PDT 24
Peak memory	205584 kb
Host	smart-c60d85ab-9203-43c2-bb00-2c651a622acf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640021485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3640021485
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2249401020
Short name	T417
Test name
Test status
Simulation time	7512962433 ps
CPU time	35.52 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:47:52 PM PDT 24
Peak memory	204704 kb
Host	smart-e744f515-94ed-40a5-baa0-ba4903c436f2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2249401020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2249401020
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1087314653
Short name	T595
Test name
Test status
Simulation time	238868865 ps
CPU time	25.93 seconds
Started	Apr 28 12:47:08 PM PDT 24
Finished	Apr 28 12:47:35 PM PDT 24
Peak memory	204592 kb
Host	smart-38ece032-b01d-48e5-83ff-29f69106962e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087314653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1087314653
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.2360864490
Short name	T422
Test name
Test status
Simulation time	177748672 ps
CPU time	11.47 seconds
Started	Apr 28 12:47:05 PM PDT 24
Finished	Apr 28 12:47:18 PM PDT 24
Peak memory	203408 kb
Host	smart-978a551d-ecfc-4576-91da-a9e711d15140
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2360864490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2360864490
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.3849909199
Short name	T788
Test name
Test status
Simulation time	285952484 ps
CPU time	3.41 seconds
Started	Apr 28 12:47:20 PM PDT 24
Finished	Apr 28 12:47:24 PM PDT 24
Peak memory	203360 kb
Host	smart-4e4d5e7a-4299-48b2-aace-3ada4625651f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3849909199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3849909199
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2566753871
Short name	T717
Test name
Test status
Simulation time	9424882271 ps
CPU time	33.35 seconds
Started	Apr 28 12:47:13 PM PDT 24
Finished	Apr 28 12:47:47 PM PDT 24
Peak memory	203536 kb
Host	smart-cd2e98dd-8db1-4624-8ae9-5974c663ec9f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566753871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2566753871
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3793289008
Short name	T821
Test name
Test status
Simulation time	5097609537 ps
CPU time	23.84 seconds
Started	Apr 28 12:46:59 PM PDT 24
Finished	Apr 28 12:47:23 PM PDT 24
Peak memory	203520 kb
Host	smart-7e2f72e3-373b-4c99-8e4a-d5fe9e7078f2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3793289008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3793289008
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1971548871
Short name	T485
Test name
Test status
Simulation time	27412873 ps
CPU time	2.1 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:47:19 PM PDT 24
Peak memory	203316 kb
Host	smart-bb5ae6c8-c894-40c4-bad5-21bdf2606243
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971548871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1971548871
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.249407087
Short name	T184
Test name
Test status
Simulation time	1638526055 ps
CPU time	137.84 seconds
Started	Apr 28 12:47:20 PM PDT 24
Finished	Apr 28 12:49:39 PM PDT 24
Peak memory	209736 kb
Host	smart-f4947fc4-bbed-4b28-8bb5-517228ad2aa4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=249407087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.249407087
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.966062972
Short name	T587
Test name
Test status
Simulation time	1481175123 ps
CPU time	157.81 seconds
Started	Apr 28 12:47:00 PM PDT 24
Finished	Apr 28 12:49:38 PM PDT 24
Peak memory	209756 kb
Host	smart-0034fe4a-f982-43f9-95db-8f82b58fc2df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=966062972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.966062972
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.256635371
Short name	T166
Test name
Test status
Simulation time	4358149639 ps
CPU time	437.14 seconds
Started	Apr 28 12:47:02 PM PDT 24
Finished	Apr 28 12:54:20 PM PDT 24
Peak memory	211692 kb
Host	smart-11d515a8-3591-43d2-aafd-8b6cadea4049
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=256635371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_ reset.256635371
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2559246143
Short name	T885
Test name
Test status
Simulation time	1369355157 ps
CPU time	185.47 seconds
Started	Apr 28 12:47:12 PM PDT 24
Finished	Apr 28 12:50:19 PM PDT 24
Peak memory	211544 kb
Host	smart-fb8343ca-fa8f-4ccc-bf8e-d093a61feddd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2559246143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2559246143
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1012503663
Short name	T282
Test name
Test status
Simulation time	299792779 ps
CPU time	12.53 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:47:15 PM PDT 24
Peak memory	204832 kb
Host	smart-86ba934f-d0a9-4848-810d-af5930b25521
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1012503663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1012503663
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2101545565
Short name	T549
Test name
Test status
Simulation time	36434474 ps
CPU time	6.4 seconds
Started	Apr 28 12:47:08 PM PDT 24
Finished	Apr 28 12:47:15 PM PDT 24
Peak memory	204132 kb
Host	smart-094a2ba9-e5f5-4df9-a749-da963e8043e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2101545565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2101545565
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1042863355
Short name	T884
Test name
Test status
Simulation time	27057894413 ps
CPU time	170.07 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:50:07 PM PDT 24
Peak memory	206196 kb
Host	smart-c6511bec-e440-43c9-afe8-48ea8a5392a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1042863355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.1042863355
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3164190969
Short name	T598
Test name
Test status
Simulation time	139511805 ps
CPU time	5.5 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:12 PM PDT 24
Peak memory	203484 kb
Host	smart-27aee964-b536-49c2-8cf1-5f2c3219f8a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3164190969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3164190969
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.931595035
Short name	T72
Test name
Test status
Simulation time	312789574 ps
CPU time	15.3 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:22 PM PDT 24
Peak memory	203460 kb
Host	smart-036abbf0-9563-4fc2-9d43-6c14c89a07f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931595035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.931595035
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.3593168968
Short name	T202
Test name
Test status
Simulation time	1825527866 ps
CPU time	10.86 seconds
Started	Apr 28 12:47:16 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	211616 kb
Host	smart-b0b38e04-3553-4b28-ba84-ea2959682ce8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3593168968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3593168968
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3047759046
Short name	T141
Test name
Test status
Simulation time	32215439139 ps
CPU time	146.41 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:49:44 PM PDT 24
Peak memory	204704 kb
Host	smart-3c89b030-2ec8-46fd-a5df-e335088f1489
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047759046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3047759046
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1872398458
Short name	T751
Test name
Test status
Simulation time	5907484500 ps
CPU time	57.36 seconds
Started	Apr 28 12:47:14 PM PDT 24
Finished	Apr 28 12:48:14 PM PDT 24
Peak memory	205100 kb
Host	smart-a3ab6412-8077-4f83-8ddc-5ffe4eaac31a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1872398458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1872398458
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2651323242
Short name	T710
Test name
Test status
Simulation time	288932969 ps
CPU time	21.04 seconds
Started	Apr 28 12:47:06 PM PDT 24
Finished	Apr 28 12:47:28 PM PDT 24
Peak memory	204620 kb
Host	smart-e326394e-5279-403c-b4d4-4d71a615ff56
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651323242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2651323242
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.3118296300
Short name	T298
Test name
Test status
Simulation time	233556457 ps
CPU time	14.68 seconds
Started	Apr 28 12:47:07 PM PDT 24
Finished	Apr 28 12:47:22 PM PDT 24
Peak memory	203896 kb
Host	smart-050f5c12-0ac5-4162-ae42-4f5f48e9bc36
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118296300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3118296300
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.1479474917
Short name	T807
Test name
Test status
Simulation time	171077992 ps
CPU time	3.59 seconds
Started	Apr 28 12:47:07 PM PDT 24
Finished	Apr 28 12:47:11 PM PDT 24
Peak memory	203500 kb
Host	smart-bb8842d2-c27b-4734-abf4-e82998b32c79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1479474917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1479474917
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.962595554
Short name	T567
Test name
Test status
Simulation time	7818197607 ps
CPU time	32.13 seconds
Started	Apr 28 12:47:04 PM PDT 24
Finished	Apr 28 12:47:38 PM PDT 24
Peak memory	203544 kb
Host	smart-afcdc6a0-a3e1-4a19-94fe-fe073eb2e453
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=962595554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.962595554
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3101857817
Short name	T665
Test name
Test status
Simulation time	5858055509 ps
CPU time	34.29 seconds
Started	Apr 28 12:47:16 PM PDT 24
Finished	Apr 28 12:47:52 PM PDT 24
Peak memory	203464 kb
Host	smart-e4128334-b75d-4616-868a-6d5c2915a80a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3101857817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3101857817
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4009891807
Short name	T249
Test name
Test status
Simulation time	57557981 ps
CPU time	2.26 seconds
Started	Apr 28 12:47:17 PM PDT 24
Finished	Apr 28 12:47:21 PM PDT 24
Peak memory	203468 kb
Host	smart-d7e926b2-9ea8-4814-9220-e47b4b11b1fd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009891807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4009891807
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.3869148988
Short name	T445
Test name
Test status
Simulation time	4932116897 ps
CPU time	195.7 seconds
Started	Apr 28 12:47:09 PM PDT 24
Finished	Apr 28 12:50:26 PM PDT 24
Peak memory	209764 kb
Host	smart-e0429cee-a60f-47f2-a261-cacf8de6c8bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3869148988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3869148988
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.4036170617
Short name	T290
Test name
Test status
Simulation time	8375191007 ps
CPU time	192.36 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:50:30 PM PDT 24
Peak memory	208064 kb
Host	smart-6b6f6a4a-a8ec-4630-8fef-6290f29cc699
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4036170617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4036170617
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1402296556
Short name	T670
Test name
Test status
Simulation time	274207705 ps
CPU time	179.34 seconds
Started	Apr 28 12:47:01 PM PDT 24
Finished	Apr 28 12:50:01 PM PDT 24
Peak memory	208104 kb
Host	smart-555fd8bb-9b2d-4fcb-8772-3b17b8c09a19
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1402296556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1402296556
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1978793675
Short name	T242
Test name
Test status
Simulation time	1120859720 ps
CPU time	89.86 seconds
Started	Apr 28 12:47:19 PM PDT 24
Finished	Apr 28 12:48:50 PM PDT 24
Peak memory	209364 kb
Host	smart-d608192f-ccea-42fe-ac17-274d19dfd271
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1978793675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1978793675
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2261306061
Short name	T237
Test name
Test status
Simulation time	201253426 ps
CPU time	12.14 seconds
Started	Apr 28 12:47:15 PM PDT 24
Finished	Apr 28 12:47:29 PM PDT 24
Peak memory	204916 kb
Host	smart-2a8e5059-5192-40db-8def-b35bd840403d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261306061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2261306061
Directory	/workspace/9.xbar_unmapped_addr/latest