Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1802	1			T11	11		T14	21		T18	1
all_values[1]	1848	1			T11	17		T21	3		T14	16
all_values[2]	1841	1			T11	10		T21	1		T14	19
all_values[3]	1829	1			T11	15		T21	1		T14	11
all_values[4]	1826	1			T11	16		T21	3		T14	18
all_values[5]	1873	1			T11	10		T14	22		T19	37
all_values[6]	1930	1			T11	12		T21	4		T14	22
all_values[7]	1844	1			T11	17		T21	2		T14	19
all_values[8]	1922	1			T11	8		T21	3		T14	19
all_values[9]	1780	1			T11	7		T21	3		T14	17
all_values[10]	1806	1			T11	9		T14	11		T19	31
all_values[11]	1797	1			T11	8		T21	2		T14	22
all_values[12]	1861	1			T11	10		T14	17		T19	33
all_values[13]	1870	1			T11	14		T21	1		T14	16
all_values[14]	1877	1			T11	12		T21	1		T14	17
all_values[15]	1873	1			T11	10		T21	1		T14	17
all_values[16]	1833	1			T11	7		T21	1		T14	16
all_values[17]	1810	1			T11	13		T21	2		T14	14
all_values[18]	1887	1			T11	19		T21	3		T14	13
all_values[19]	1805	1			T11	8		T21	2		T14	18
all_values[20]	1821	1			T11	7		T21	2		T14	17
all_values[21]	1802	1			T11	8		T21	2		T14	15
all_values[22]	1819	1			T11	12		T21	4		T14	19
all_values[23]	1791	1			T11	13		T21	2		T14	16
all_values[24]	1875	1			T11	8		T21	1		T14	19
all_values[25]	1887	1			T11	16		T14	19		T19	29
all_values[26]	1900	1			T11	15		T14	15		T18	1
all_values[27]	1855	1			T11	6		T14	16		T18	1
all_values[28]	1757	1			T11	13		T14	16		T19	29
all_values[29]	1806	1			T11	12		T21	2		T14	14
all_values[30]	1858	1			T11	12		T21	2		T14	27
all_values[31]	1779	1			T11	13		T21	3		T14	20
all_values[32]	1874	1			T11	12		T21	5		T14	5
all_values[33]	1841	1			T11	19		T21	2		T14	18
all_values[34]	1892	1			T11	7		T14	25		T18	2
all_values[35]	1903	1			T11	13		T21	3		T14	20
all_values[36]	1797	1			T11	18		T21	1		T14	19
all_values[37]	1828	1			T11	14		T21	2		T14	11
all_values[38]	1858	1			T11	15		T14	9		T16	1
all_values[39]	1844	1			T11	13		T14	26		T16	1
all_values[40]	1819	1			T11	19		T21	2		T14	17
all_values[41]	1825	1			T11	13		T21	2		T14	27
all_values[42]	1741	1			T11	14		T14	15		T18	1
all_values[43]	1829	1			T11	10		T14	15		T19	38
all_values[44]	1803	1			T11	8		T21	1		T14	18
all_values[45]	1867	1			T11	12		T21	1		T14	15
all_values[46]	1820	1			T11	13		T21	2		T14	18
all_values[47]	1930	1			T11	12		T14	21		T18	2
all_values[48]	1891	1			T11	14		T21	1		T14	20
all_values[49]	1733	1			T11	16		T21	2		T14	18
all_values[50]	1804	1			T11	13		T21	3		T14	16
all_values[51]	1889	1			T11	14		T21	1		T14	13
all_values[52]	1914	1			T11	14		T21	1		T14	17
all_values[53]	1771	1			T11	14		T21	2		T14	20
all_values[54]	1905	1			T11	8		T14	33		T18	1
all_values[55]	1794	1			T11	14		T14	18		T19	34
all_values[56]	1921	1			T11	9		T14	17		T16	3
all_values[57]	1854	1			T11	12		T21	3		T14	19
all_values[58]	1910	1			T11	12		T21	3		T14	14
all_values[59]	1930	1			T11	16		T21	1		T14	18
all_values[60]	1850	1			T11	12		T21	3		T14	23
all_values[61]	1866	1			T11	14		T14	20		T18	2
all_values[62]	1774	1			T11	10		T21	2		T14	7
all_values[63]	1851	1			T11	13		T14	19		T18	2