Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1724	1			T1	1		T2	3		T3	3
all_values[1]	1734	1			T2	2		T3	3		T4	7
all_values[2]	1720	1			T2	1		T4	7		T16	2
all_values[3]	1732	1			T1	3		T3	1		T4	8
all_values[4]	1735	1			T1	3		T2	1		T3	3
all_values[5]	1760	1			T1	1		T2	3		T4	3
all_values[6]	1718	1			T1	1		T2	2		T3	4
all_values[7]	1739	1			T3	3		T4	2		T16	4
all_values[8]	1763	1			T2	5		T3	4		T4	2
all_values[9]	1745	1			T2	3		T3	4		T4	6
all_values[10]	1763	1			T2	1		T4	4		T16	3
all_values[11]	1791	1			T1	2		T2	1		T3	2
all_values[12]	1728	1			T1	2		T2	1		T3	3
all_values[13]	1685	1			T1	1		T2	1		T3	1
all_values[14]	1620	1			T1	1		T2	2		T3	3
all_values[15]	1697	1			T1	2		T2	3		T3	2
all_values[16]	1776	1			T2	1		T4	1		T16	1
all_values[17]	1733	1			T1	2		T2	1		T3	3
all_values[18]	1725	1			T2	4		T3	3		T4	6
all_values[19]	1788	1			T1	2		T2	2		T3	2
all_values[20]	1743	1			T1	1		T2	4		T3	1
all_values[21]	1734	1			T2	3		T3	2		T4	4
all_values[22]	1635	1			T1	1		T2	1		T3	2
all_values[23]	1654	1			T2	2		T3	4		T4	1
all_values[24]	1738	1			T1	1		T2	1		T3	3
all_values[25]	1738	1			T2	1		T3	1		T4	6
all_values[26]	1755	1			T2	3		T3	2		T4	6
all_values[27]	1737	1			T1	1		T2	2		T4	4
all_values[28]	1762	1			T2	1		T3	2		T4	4
all_values[29]	1723	1			T2	2		T4	3		T16	1
all_values[30]	1755	1			T4	5		T16	2		T19	1
all_values[31]	1704	1			T1	1		T2	1		T3	2
all_values[32]	1750	1			T1	2		T3	1		T4	5
all_values[33]	1745	1			T1	1		T2	1		T3	3
all_values[34]	1742	1			T2	3		T3	3		T4	4
all_values[35]	1685	1			T2	2		T3	3		T4	9
all_values[36]	1713	1			T1	1		T2	2		T3	2
all_values[37]	1745	1			T1	1		T3	1		T4	4
all_values[38]	1752	1			T1	1		T2	1		T3	3
all_values[39]	1780	1			T1	3		T2	3		T3	3
all_values[40]	1735	1			T1	1		T2	2		T3	2
all_values[41]	1729	1			T3	2		T4	6		T16	1
all_values[42]	1736	1			T3	2		T4	5		T16	3
all_values[43]	1732	1			T1	2		T2	2		T3	1
all_values[44]	1674	1			T2	3		T4	5		T16	2
all_values[45]	1781	1			T1	1		T2	3		T3	2
all_values[46]	1835	1			T1	1		T2	5		T3	3
all_values[47]	1730	1			T1	1		T2	4		T4	5
all_values[48]	1716	1			T2	4		T3	2		T4	6
all_values[49]	1728	1			T2	4		T3	3		T4	5
all_values[50]	1761	1			T2	1		T4	5		T16	1
all_values[51]	1700	1			T2	3		T3	2		T4	3
all_values[52]	1691	1			T1	3		T2	2		T3	1
all_values[53]	1754	1			T1	1		T2	1		T3	4
all_values[54]	1782	1			T2	4		T3	1		T4	1
all_values[55]	1660	1			T1	1		T4	4		T16	1
all_values[56]	1746	1			T2	3		T3	4		T4	5
all_values[57]	1730	1			T1	1		T2	2		T3	3
all_values[58]	1774	1			T1	1		T2	1		T3	1
all_values[59]	1742	1			T1	1		T2	3		T3	2
all_values[60]	1745	1			T2	2		T3	2		T4	2
all_values[61]	1680	1			T1	2		T2	2		T4	6
all_values[62]	1704	1			T2	1		T4	3		T16	1
all_values[63]	1784	1			T1	1		T3	1		T4	4