Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1660	1			T13	2		T20	13		T25	15
all_values[1]	1622	1			T13	7		T20	19		T65	1
all_values[2]	1643	1			T13	6		T20	22		T65	4
all_values[3]	1638	1			T13	5		T20	14		T25	13
all_values[4]	1656	1			T13	8		T20	12		T65	3
all_values[5]	1587	1			T13	5		T20	17		T65	3
all_values[6]	1699	1			T13	5		T20	16		T65	2
all_values[7]	1613	1			T13	4		T20	11		T65	1
all_values[8]	1667	1			T13	6		T20	14		T65	2
all_values[9]	1662	1			T13	8		T20	10		T25	19
all_values[10]	1702	1			T13	10		T20	12		T65	1
all_values[11]	1593	1			T13	4		T20	14		T25	22
all_values[12]	1668	1			T13	8		T20	19		T65	2
all_values[13]	1639	1			T13	7		T20	15		T65	4
all_values[14]	1597	1			T13	8		T20	16		T65	5
all_values[15]	1629	1			T13	7		T20	17		T65	1
all_values[16]	1727	1			T13	11		T20	11		T65	2
all_values[17]	1654	1			T13	5		T20	17		T65	1
all_values[18]	1643	1			T13	7		T20	9		T65	4
all_values[19]	1605	1			T13	7		T20	13		T65	2
all_values[20]	1726	1			T13	11		T20	23		T65	1
all_values[21]	1646	1			T13	9		T20	21		T65	4
all_values[22]	1592	1			T13	4		T20	21		T25	18
all_values[23]	1700	1			T13	5		T20	9		T65	3
all_values[24]	1658	1			T13	6		T20	14		T25	21
all_values[25]	1678	1			T13	8		T20	17		T25	21
all_values[26]	1617	1			T13	5		T20	9		T65	1
all_values[27]	1705	1			T13	7		T20	22		T65	2
all_values[28]	1669	1			T13	5		T20	10		T65	2
all_values[29]	1673	1			T13	10		T20	18		T65	5
all_values[30]	1649	1			T13	8		T20	15		T65	1
all_values[31]	1683	1			T13	4		T20	20		T65	4
all_values[32]	1658	1			T13	7		T20	14		T65	3
all_values[33]	1684	1			T13	5		T20	19		T65	2
all_values[34]	1637	1			T13	4		T20	23		T65	1
all_values[35]	1573	1			T13	4		T20	12		T65	3
all_values[36]	1685	1			T13	6		T20	15		T25	16
all_values[37]	1603	1			T13	7		T20	14		T65	1
all_values[38]	1604	1			T13	8		T20	18		T65	4
all_values[39]	1677	1			T13	4		T20	10		T65	3
all_values[40]	1633	1			T13	3		T20	20		T25	10
all_values[41]	1708	1			T13	2		T20	11		T65	4
all_values[42]	1679	1			T13	3		T20	18		T65	5
all_values[43]	1634	1			T13	8		T20	20		T65	3
all_values[44]	1601	1			T13	4		T20	14		T25	13
all_values[45]	1652	1			T13	5		T20	21		T25	11
all_values[46]	1644	1			T13	6		T20	21		T65	1
all_values[47]	1679	1			T13	5		T20	10		T65	3
all_values[48]	1695	1			T13	3		T20	13		T65	1
all_values[49]	1673	1			T13	6		T20	20		T65	1
all_values[50]	1647	1			T13	9		T20	19		T65	1
all_values[51]	1600	1			T13	4		T20	24		T65	1
all_values[52]	1648	1			T13	4		T20	14		T65	3
all_values[53]	1690	1			T13	8		T20	9		T65	1
all_values[54]	1628	1			T13	10		T20	18		T65	3
all_values[55]	1731	1			T13	10		T20	16		T65	2
all_values[56]	1694	1			T13	6		T20	21		T65	2
all_values[57]	1625	1			T13	3		T20	19		T65	4
all_values[58]	1626	1			T13	5		T20	10		T25	10
all_values[59]	1679	1			T13	10		T20	12		T65	2
all_values[60]	1634	1			T13	4		T20	23		T65	1
all_values[61]	1636	1			T13	6		T20	18		T65	2
all_values[62]	1649	1			T13	3		T20	13		T65	4
all_values[63]	1583	1			T13	6		T20	12		T65	2