Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 480 1 T3 6 T8 1 T15 1
all_values[1] 494 1 T3 2 T8 2 T15 1
all_values[2] 509 1 T3 6 T8 3 T17 1
all_values[3] 504 1 T3 4 T8 3 T15 1
all_values[4] 476 1 T3 1 T8 2 T15 2
all_values[5] 499 1 T3 7 T8 3 T17 3
all_values[6] 475 1 T3 5 T8 2 T17 1
all_values[7] 443 1 T3 3 T8 4 T17 1
all_values[8] 459 1 T8 5 T17 3 T18 1
all_values[9] 459 1 T3 6 T8 3 T15 3
all_values[10] 493 1 T3 3 T8 3 T15 2
all_values[11] 444 1 T3 1 T8 3 T18 1
all_values[12] 454 1 T3 3 T15 1 T18 1
all_values[13] 489 1 T3 6 T8 3 T15 3
all_values[14] 507 1 T3 6 T8 2 T15 1
all_values[15] 439 1 T3 6 T8 1 T15 1
all_values[16] 433 1 T3 4 T8 1 T18 1
all_values[17] 456 1 T3 6 T8 1 T17 1
all_values[18] 505 1 T3 4 T8 3 T17 2
all_values[19] 509 1 T3 10 T15 1 T74 1
all_values[20] 479 1 T3 9 T8 1 T15 1
all_values[21] 467 1 T3 3 T8 2 T17 1
all_values[22] 460 1 T3 3 T8 4 T15 1
all_values[23] 469 1 T3 5 T8 2 T15 1

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