Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1643	1			T3	7		T8	5		T15	5
all_values[1]	1619	1			T3	6		T8	2		T15	6
all_values[2]	1759	1			T3	9		T8	4		T15	11
all_values[3]	1675	1			T3	7		T8	4		T15	6
all_values[4]	1684	1			T3	10		T8	4		T15	10
all_values[5]	1638	1			T3	11		T8	3		T15	8
all_values[6]	1671	1			T3	10		T8	5		T15	4
all_values[7]	1641	1			T3	9		T8	2		T15	9
all_values[8]	1752	1			T3	11		T15	11		T18	1
all_values[9]	1686	1			T3	8		T8	6		T15	3
all_values[10]	1594	1			T3	15		T8	1		T15	6
all_values[11]	1683	1			T3	13		T8	2		T15	5
all_values[12]	1687	1			T3	16		T8	2		T15	8
all_values[13]	1743	1			T3	14		T8	3		T15	10
all_values[14]	1677	1			T3	12		T8	1		T15	6
all_values[15]	1660	1			T3	14		T8	1		T15	4
all_values[16]	1651	1			T3	5		T8	5		T15	6
all_values[17]	1560	1			T3	13		T8	1		T15	7
all_values[18]	1671	1			T3	8		T8	4		T15	6
all_values[19]	1681	1			T3	9		T8	3		T15	9
all_values[20]	1622	1			T3	8		T8	4		T15	4
all_values[21]	1670	1			T3	14		T8	4		T15	10
all_values[22]	1669	1			T3	12		T8	3		T15	11
all_values[23]	1676	1			T3	12		T8	5		T15	9
all_values[24]	1665	1			T3	7		T8	4		T15	8
all_values[25]	1668	1			T3	14		T8	3		T15	10
all_values[26]	1656	1			T3	16		T8	5		T15	4
all_values[27]	1694	1			T3	10		T8	1		T15	8
all_values[28]	1671	1			T3	12		T8	3		T15	6
all_values[29]	1688	1			T3	6		T8	5		T15	13
all_values[30]	1665	1			T3	9		T15	11		T18	2
all_values[31]	1722	1			T3	13		T15	9		T18	2
all_values[32]	1721	1			T3	18		T8	5		T15	5
all_values[33]	1674	1			T3	10		T8	2		T15	12
all_values[34]	1745	1			T3	10		T8	3		T15	3
all_values[35]	1673	1			T3	9		T8	3		T15	11
all_values[36]	1642	1			T3	10		T8	2		T15	6
all_values[37]	1587	1			T3	13		T8	6		T15	8
all_values[38]	1747	1			T3	7		T8	2		T15	7
all_values[39]	1656	1			T3	11		T8	7		T15	4
all_values[40]	1640	1			T3	11		T8	4		T15	10
all_values[41]	1712	1			T3	12		T8	5		T15	8
all_values[42]	1668	1			T3	14		T8	2		T15	7
all_values[43]	1682	1			T3	11		T8	3		T15	8
all_values[44]	1600	1			T3	11		T8	3		T15	5
all_values[45]	1706	1			T3	12		T8	3		T15	11
all_values[46]	1665	1			T3	7		T8	6		T15	11
all_values[47]	1627	1			T3	6		T8	2		T15	8
all_values[48]	1649	1			T3	6		T8	4		T15	6
all_values[49]	1737	1			T3	9		T8	2		T15	7
all_values[50]	1642	1			T3	9		T8	2		T15	3
all_values[51]	1648	1			T3	11		T8	2		T15	12
all_values[52]	1733	1			T3	11		T8	3		T15	9
all_values[53]	1635	1			T3	11		T8	3		T15	5
all_values[54]	1718	1			T3	8		T8	3		T15	9
all_values[55]	1811	1			T3	9		T8	4		T15	10
all_values[56]	1618	1			T3	12		T8	2		T15	11
all_values[57]	1612	1			T3	9		T8	3		T15	5
all_values[58]	1672	1			T3	9		T8	3		T15	5
all_values[59]	1683	1			T3	4		T8	1		T15	8
all_values[60]	1610	1			T3	4		T8	2		T15	7
all_values[61]	1593	1			T3	8		T8	4		T15	5
all_values[62]	1630	1			T3	7		T8	3		T15	4
all_values[63]	1632	1			T3	11		T8	4		T15	9