Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.02 99.26 88.92 98.80 95.88 99.26 100.00


Total test records in report: 900
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T766 /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3449816529 May 07 12:45:29 PM PDT 24 May 07 12:45:41 PM PDT 24 157339952 ps
T767 /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2660262800 May 07 12:46:26 PM PDT 24 May 07 12:46:30 PM PDT 24 29114428 ps
T768 /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3359001772 May 07 12:46:34 PM PDT 24 May 07 12:47:40 PM PDT 24 2735003261 ps
T68 /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1693177560 May 07 12:45:07 PM PDT 24 May 07 12:50:23 PM PDT 24 149029364492 ps
T769 /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.765004234 May 07 12:44:58 PM PDT 24 May 07 12:45:01 PM PDT 24 92514328 ps
T770 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3289329234 May 07 12:46:30 PM PDT 24 May 07 12:57:14 PM PDT 24 163442432410 ps
T69 /workspace/coverage/xbar_build_mode/35.xbar_smoke.3159250942 May 07 12:45:57 PM PDT 24 May 07 12:46:02 PM PDT 24 139832163 ps
T771 /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1019066280 May 07 12:45:30 PM PDT 24 May 07 12:47:43 PM PDT 24 28733676878 ps
T772 /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.490850000 May 07 12:44:38 PM PDT 24 May 07 12:44:42 PM PDT 24 38092852 ps
T773 /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.976462374 May 07 12:45:38 PM PDT 24 May 07 12:45:58 PM PDT 24 801196379 ps
T774 /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.162463366 May 07 12:45:30 PM PDT 24 May 07 12:47:54 PM PDT 24 23058179986 ps
T775 /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1994181644 May 07 12:44:41 PM PDT 24 May 07 12:46:05 PM PDT 24 2318816170 ps
T776 /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2279989021 May 07 12:45:07 PM PDT 24 May 07 12:45:16 PM PDT 24 141014484 ps
T777 /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3960332321 May 07 12:45:26 PM PDT 24 May 07 12:50:22 PM PDT 24 5045109043 ps
T253 /workspace/coverage/xbar_build_mode/44.xbar_random.3783259943 May 07 12:46:30 PM PDT 24 May 07 12:47:06 PM PDT 24 1817021009 ps
T778 /workspace/coverage/xbar_build_mode/8.xbar_error_random.2743734957 May 07 12:45:09 PM PDT 24 May 07 12:45:22 PM PDT 24 133688228 ps
T779 /workspace/coverage/xbar_build_mode/44.xbar_same_source.195499071 May 07 12:46:25 PM PDT 24 May 07 12:46:41 PM PDT 24 755360351 ps
T780 /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3087657323 May 07 12:45:08 PM PDT 24 May 07 12:45:24 PM PDT 24 479982352 ps
T781 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3824174665 May 07 12:46:40 PM PDT 24 May 07 12:46:51 PM PDT 24 123239709 ps
T43 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.439263973 May 07 12:45:04 PM PDT 24 May 07 12:47:15 PM PDT 24 467154572 ps
T249 /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2276339302 May 07 12:45:53 PM PDT 24 May 07 12:46:29 PM PDT 24 4915901814 ps
T782 /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2807719326 May 07 12:44:56 PM PDT 24 May 07 12:46:13 PM PDT 24 43393605201 ps
T783 /workspace/coverage/xbar_build_mode/2.xbar_same_source.2861194855 May 07 12:44:40 PM PDT 24 May 07 12:44:47 PM PDT 24 715184428 ps
T784 /workspace/coverage/xbar_build_mode/37.xbar_error_random.2060747397 May 07 12:46:06 PM PDT 24 May 07 12:46:24 PM PDT 24 185576965 ps
T785 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.124749293 May 07 12:45:06 PM PDT 24 May 07 12:50:45 PM PDT 24 5837607709 ps
T786 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3172864700 May 07 12:44:38 PM PDT 24 May 07 12:48:25 PM PDT 24 7958552559 ps
T242 /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1333351156 May 07 12:46:24 PM PDT 24 May 07 12:48:55 PM PDT 24 18155988057 ps
T787 /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3394880148 May 07 12:45:31 PM PDT 24 May 07 12:46:05 PM PDT 24 5992799886 ps
T788 /workspace/coverage/xbar_build_mode/43.xbar_error_random.216173822 May 07 12:46:23 PM PDT 24 May 07 12:46:47 PM PDT 24 2644427803 ps
T789 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.612475776 May 07 12:45:12 PM PDT 24 May 07 12:48:56 PM PDT 24 9691752196 ps
T790 /workspace/coverage/xbar_build_mode/33.xbar_smoke.1418801171 May 07 12:45:53 PM PDT 24 May 07 12:45:57 PM PDT 24 96680835 ps
T791 /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3598598825 May 07 12:46:39 PM PDT 24 May 07 12:49:27 PM PDT 24 20828515997 ps
T792 /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.377290633 May 07 12:44:33 PM PDT 24 May 07 12:47:09 PM PDT 24 18939923747 ps
T793 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3170131114 May 07 12:45:29 PM PDT 24 May 07 12:51:36 PM PDT 24 8090778987 ps
T794 /workspace/coverage/xbar_build_mode/25.xbar_error_random.1904307603 May 07 12:45:29 PM PDT 24 May 07 12:45:54 PM PDT 24 163693130 ps
T795 /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.331932703 May 07 12:45:45 PM PDT 24 May 07 12:45:49 PM PDT 24 39103503 ps
T796 /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.580650148 May 07 12:45:11 PM PDT 24 May 07 12:53:17 PM PDT 24 47014996110 ps
T797 /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3516108357 May 07 12:45:59 PM PDT 24 May 07 12:46:41 PM PDT 24 7735664383 ps
T798 /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1327542679 May 07 12:45:27 PM PDT 24 May 07 12:50:20 PM PDT 24 3937163577 ps
T799 /workspace/coverage/xbar_build_mode/15.xbar_error_random.993843206 May 07 12:45:11 PM PDT 24 May 07 12:45:38 PM PDT 24 1035361676 ps
T800 /workspace/coverage/xbar_build_mode/21.xbar_random.472895468 May 07 12:45:10 PM PDT 24 May 07 12:45:40 PM PDT 24 797539715 ps
T801 /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3588652693 May 07 12:45:11 PM PDT 24 May 07 12:45:23 PM PDT 24 67547848 ps
T802 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.566745421 May 07 12:45:02 PM PDT 24 May 07 12:45:14 PM PDT 24 961066565 ps
T803 /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1455409699 May 07 12:45:23 PM PDT 24 May 07 12:46:00 PM PDT 24 11294862876 ps
T148 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3231678367 May 07 12:44:54 PM PDT 24 May 07 12:55:07 PM PDT 24 98038134949 ps
T804 /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.3106002959 May 07 12:45:24 PM PDT 24 May 07 12:45:37 PM PDT 24 2081381053 ps
T805 /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.667655604 May 07 12:45:25 PM PDT 24 May 07 12:47:29 PM PDT 24 31178366427 ps
T213 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.511259273 May 07 12:46:46 PM PDT 24 May 07 12:47:49 PM PDT 24 1316701812 ps
T806 /workspace/coverage/xbar_build_mode/44.xbar_error_random.2860980377 May 07 12:46:24 PM PDT 24 May 07 12:46:55 PM PDT 24 838070428 ps
T807 /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1002293685 May 07 12:46:12 PM PDT 24 May 07 12:46:39 PM PDT 24 707882226 ps
T808 /workspace/coverage/xbar_build_mode/12.xbar_stress_all.94954168 May 07 12:45:17 PM PDT 24 May 07 12:46:52 PM PDT 24 3750101060 ps
T809 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3631903551 May 07 12:45:26 PM PDT 24 May 07 12:47:55 PM PDT 24 333231317 ps
T810 /workspace/coverage/xbar_build_mode/6.xbar_error_random.952926389 May 07 12:45:10 PM PDT 24 May 07 12:45:33 PM PDT 24 993450360 ps
T136 /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1339843212 May 07 12:44:57 PM PDT 24 May 07 12:49:45 PM PDT 24 9096011327 ps
T811 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3746248609 May 07 12:46:38 PM PDT 24 May 07 12:46:58 PM PDT 24 203948446 ps
T812 /workspace/coverage/xbar_build_mode/29.xbar_random.944835741 May 07 12:45:37 PM PDT 24 May 07 12:46:05 PM PDT 24 591146161 ps
T813 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3001357475 May 07 12:45:11 PM PDT 24 May 07 12:52:33 PM PDT 24 63574966886 ps
T814 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1208542324 May 07 12:45:38 PM PDT 24 May 07 12:46:34 PM PDT 24 1620598964 ps
T815 /workspace/coverage/xbar_build_mode/25.xbar_random.959642906 May 07 12:45:29 PM PDT 24 May 07 12:45:45 PM PDT 24 108536193 ps
T816 /workspace/coverage/xbar_build_mode/48.xbar_random.3102619041 May 07 12:46:42 PM PDT 24 May 07 12:46:56 PM PDT 24 412808895 ps
T817 /workspace/coverage/xbar_build_mode/42.xbar_stress_all.245157118 May 07 12:46:20 PM PDT 24 May 07 12:48:54 PM PDT 24 1536144744 ps
T818 /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.374972883 May 07 12:44:31 PM PDT 24 May 07 12:45:20 PM PDT 24 6716377048 ps
T819 /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1217382639 May 07 12:45:11 PM PDT 24 May 07 12:45:20 PM PDT 24 81596084 ps
T820 /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.148835543 May 07 12:46:10 PM PDT 24 May 07 12:46:35 PM PDT 24 2537951991 ps
T821 /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3245275097 May 07 12:46:32 PM PDT 24 May 07 12:46:47 PM PDT 24 130889263 ps
T822 /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2052173428 May 07 12:45:57 PM PDT 24 May 07 12:46:17 PM PDT 24 1291017979 ps
T823 /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2776276383 May 07 12:46:34 PM PDT 24 May 07 12:46:39 PM PDT 24 40063478 ps
T824 /workspace/coverage/xbar_build_mode/25.xbar_same_source.3152981980 May 07 12:45:38 PM PDT 24 May 07 12:46:02 PM PDT 24 5508811667 ps
T825 /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1826987984 May 07 12:45:17 PM PDT 24 May 07 12:45:25 PM PDT 24 54053664 ps
T826 /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3168137224 May 07 12:46:11 PM PDT 24 May 07 12:47:07 PM PDT 24 22710472962 ps
T827 /workspace/coverage/xbar_build_mode/16.xbar_same_source.3638992159 May 07 12:45:15 PM PDT 24 May 07 12:45:41 PM PDT 24 2329165271 ps
T828 /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1162037957 May 07 12:45:33 PM PDT 24 May 07 12:45:55 PM PDT 24 133177777 ps
T829 /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2868517207 May 07 12:45:58 PM PDT 24 May 07 12:46:52 PM PDT 24 21335063095 ps
T830 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2026691874 May 07 12:45:00 PM PDT 24 May 07 12:46:59 PM PDT 24 7810221870 ps
T149 /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1490943814 May 07 12:46:02 PM PDT 24 May 07 12:50:59 PM PDT 24 12348760125 ps
T831 /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1188413851 May 07 12:45:12 PM PDT 24 May 07 12:45:46 PM PDT 24 7272424626 ps
T832 /workspace/coverage/xbar_build_mode/32.xbar_same_source.1375376266 May 07 12:45:52 PM PDT 24 May 07 12:46:09 PM PDT 24 2140668346 ps
T153 /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.1267264164 May 07 12:45:49 PM PDT 24 May 07 12:47:10 PM PDT 24 32556721867 ps
T833 /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1645982121 May 07 12:45:08 PM PDT 24 May 07 12:45:46 PM PDT 24 15212447832 ps
T834 /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2601296426 May 07 12:45:29 PM PDT 24 May 07 12:45:37 PM PDT 24 18513212 ps
T835 /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1240320848 May 07 12:46:12 PM PDT 24 May 07 12:46:54 PM PDT 24 9496265722 ps
T836 /workspace/coverage/xbar_build_mode/29.xbar_error_random.1879198501 May 07 12:45:47 PM PDT 24 May 07 12:46:12 PM PDT 24 884576235 ps
T837 /workspace/coverage/xbar_build_mode/44.xbar_smoke.2264562467 May 07 12:46:24 PM PDT 24 May 07 12:46:27 PM PDT 24 53039904 ps
T838 /workspace/coverage/xbar_build_mode/13.xbar_error_random.3463809354 May 07 12:45:07 PM PDT 24 May 07 12:45:19 PM PDT 24 14643664 ps
T839 /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.625608752 May 07 12:44:34 PM PDT 24 May 07 12:44:40 PM PDT 24 114395901 ps
T840 /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3433409229 May 07 12:45:29 PM PDT 24 May 07 12:47:28 PM PDT 24 32545013224 ps
T841 /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1257198289 May 07 12:45:29 PM PDT 24 May 07 12:45:35 PM PDT 24 46051631 ps
T267 /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4070888415 May 07 12:45:13 PM PDT 24 May 07 12:49:32 PM PDT 24 114905764426 ps
T842 /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1825338205 May 07 12:45:45 PM PDT 24 May 07 12:46:17 PM PDT 24 5868896389 ps
T843 /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2981921823 May 07 12:46:09 PM PDT 24 May 07 12:46:33 PM PDT 24 232541546 ps
T172 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3479994886 May 07 12:46:19 PM PDT 24 May 07 12:53:36 PM PDT 24 18527321425 ps
T844 /workspace/coverage/xbar_build_mode/22.xbar_same_source.118155128 May 07 12:45:27 PM PDT 24 May 07 12:45:46 PM PDT 24 495193208 ps
T845 /workspace/coverage/xbar_build_mode/42.xbar_same_source.2619751271 May 07 12:46:18 PM PDT 24 May 07 12:46:38 PM PDT 24 246235527 ps
T846 /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.916725267 May 07 12:46:10 PM PDT 24 May 07 12:46:21 PM PDT 24 72880585 ps
T847 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.451003334 May 07 12:46:12 PM PDT 24 May 07 12:53:42 PM PDT 24 115055164394 ps
T848 /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2691114393 May 07 12:44:51 PM PDT 24 May 07 12:45:16 PM PDT 24 1903738753 ps
T849 /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3380663265 May 07 12:46:42 PM PDT 24 May 07 12:48:52 PM PDT 24 24925666365 ps
T850 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1521159720 May 07 12:45:28 PM PDT 24 May 07 12:46:24 PM PDT 24 101826506 ps
T851 /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2673110824 May 07 12:45:32 PM PDT 24 May 07 12:45:54 PM PDT 24 324612885 ps
T852 /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3593989966 May 07 12:45:26 PM PDT 24 May 07 12:46:08 PM PDT 24 6181599640 ps
T853 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2107591709 May 07 12:46:04 PM PDT 24 May 07 12:51:41 PM PDT 24 2292955506 ps
T854 /workspace/coverage/xbar_build_mode/10.xbar_error_random.4290318644 May 07 12:45:04 PM PDT 24 May 07 12:45:23 PM PDT 24 175641840 ps
T855 /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.175714394 May 07 12:45:29 PM PDT 24 May 07 12:45:38 PM PDT 24 106863142 ps
T856 /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2894945001 May 07 12:46:39 PM PDT 24 May 07 12:50:19 PM PDT 24 6737833322 ps
T857 /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3021267416 May 07 12:45:23 PM PDT 24 May 07 12:45:28 PM PDT 24 29198466 ps
T858 /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3169549364 May 07 12:44:34 PM PDT 24 May 07 12:47:54 PM PDT 24 24339527445 ps
T859 /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3896249942 May 07 12:46:39 PM PDT 24 May 07 12:50:05 PM PDT 24 27921610519 ps
T860 /workspace/coverage/xbar_build_mode/39.xbar_random.3916268798 May 07 12:46:11 PM PDT 24 May 07 12:46:47 PM PDT 24 991649879 ps
T861 /workspace/coverage/xbar_build_mode/0.xbar_random.3495808477 May 07 12:44:41 PM PDT 24 May 07 12:45:11 PM PDT 24 672919754 ps
T862 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2867092070 May 07 12:45:12 PM PDT 24 May 07 12:46:18 PM PDT 24 8032977516 ps
T863 /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2022885199 May 07 12:46:03 PM PDT 24 May 07 12:46:29 PM PDT 24 567003383 ps
T864 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1513851570 May 07 12:45:29 PM PDT 24 May 07 12:46:32 PM PDT 24 848379565 ps
T865 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3173008573 May 07 12:46:24 PM PDT 24 May 07 12:50:13 PM PDT 24 3108280240 ps
T866 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2562040720 May 07 12:46:02 PM PDT 24 May 07 12:47:01 PM PDT 24 2866702668 ps
T867 /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1536647952 May 07 12:45:20 PM PDT 24 May 07 12:46:09 PM PDT 24 417468075 ps
T868 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1555764482 May 07 12:45:31 PM PDT 24 May 07 12:48:04 PM PDT 24 14757882507 ps
T869 /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1782196361 May 07 12:44:55 PM PDT 24 May 07 12:45:11 PM PDT 24 1127839496 ps
T870 /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2597272378 May 07 12:45:22 PM PDT 24 May 07 12:56:41 PM PDT 24 73902699355 ps
T152 /workspace/coverage/xbar_build_mode/23.xbar_smoke.982754302 May 07 12:45:28 PM PDT 24 May 07 12:45:36 PM PDT 24 216033801 ps
T871 /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2440697753 May 07 12:46:18 PM PDT 24 May 07 12:50:17 PM PDT 24 39043759175 ps
T872 /workspace/coverage/xbar_build_mode/24.xbar_error_random.1209314398 May 07 12:45:23 PM PDT 24 May 07 12:45:32 PM PDT 24 188859337 ps
T173 /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2800857506 May 07 12:45:58 PM PDT 24 May 07 12:55:05 PM PDT 24 147770986816 ps
T873 /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1171281658 May 07 12:46:38 PM PDT 24 May 07 12:49:19 PM PDT 24 33634065811 ps
T874 /workspace/coverage/xbar_build_mode/34.xbar_same_source.1594463771 May 07 12:45:56 PM PDT 24 May 07 12:46:13 PM PDT 24 241644781 ps
T875 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2732645970 May 07 12:46:35 PM PDT 24 May 07 12:52:48 PM PDT 24 94270047244 ps
T876 /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2774994105 May 07 12:45:51 PM PDT 24 May 07 12:45:54 PM PDT 24 23901929 ps
T877 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4091740676 May 07 12:45:46 PM PDT 24 May 07 12:52:13 PM PDT 24 2964061301 ps
T878 /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3835446104 May 07 12:46:20 PM PDT 24 May 07 12:47:47 PM PDT 24 2992434132 ps
T879 /workspace/coverage/xbar_build_mode/16.xbar_error_random.1409613867 May 07 12:45:11 PM PDT 24 May 07 12:45:16 PM PDT 24 16793286 ps
T880 /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2258841431 May 07 12:45:29 PM PDT 24 May 07 12:46:08 PM PDT 24 265136959 ps
T881 /workspace/coverage/xbar_build_mode/12.xbar_same_source.2556727059 May 07 12:45:12 PM PDT 24 May 07 12:45:22 PM PDT 24 85873732 ps
T882 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.877118635 May 07 12:45:09 PM PDT 24 May 07 12:47:20 PM PDT 24 1414780592 ps
T883 /workspace/coverage/xbar_build_mode/27.xbar_error_random.2746770670 May 07 12:45:31 PM PDT 24 May 07 12:45:38 PM PDT 24 57721754 ps
T884 /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1863080608 May 07 12:45:27 PM PDT 24 May 07 12:45:33 PM PDT 24 38732169 ps
T885 /workspace/coverage/xbar_build_mode/48.xbar_same_source.2359698266 May 07 12:46:40 PM PDT 24 May 07 12:47:00 PM PDT 24 264569825 ps
T886 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2359732433 May 07 12:46:22 PM PDT 24 May 07 12:49:56 PM PDT 24 2509145139 ps
T887 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1863618159 May 07 12:45:24 PM PDT 24 May 07 12:47:25 PM PDT 24 765328102 ps
T888 /workspace/coverage/xbar_build_mode/25.xbar_stress_all.4111257248 May 07 12:45:36 PM PDT 24 May 07 12:48:32 PM PDT 24 7107178937 ps
T889 /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.69970071 May 07 12:45:20 PM PDT 24 May 07 12:45:25 PM PDT 24 16348021 ps
T890 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1065953903 May 07 12:45:17 PM PDT 24 May 07 12:46:53 PM PDT 24 11049443794 ps
T891 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.551071232 May 07 12:45:16 PM PDT 24 May 07 12:45:32 PM PDT 24 74662039 ps
T892 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3823683618 May 07 12:45:14 PM PDT 24 May 07 12:45:58 PM PDT 24 201110793 ps
T893 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3835768078 May 07 12:45:32 PM PDT 24 May 07 12:45:53 PM PDT 24 758534221 ps
T894 /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2040891038 May 07 12:45:13 PM PDT 24 May 07 12:46:36 PM PDT 24 10243252581 ps
T895 /workspace/coverage/xbar_build_mode/45.xbar_random.2668383400 May 07 12:46:26 PM PDT 24 May 07 12:46:41 PM PDT 24 122180045 ps
T896 /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3885434120 May 07 12:44:46 PM PDT 24 May 07 12:46:27 PM PDT 24 4342339552 ps
T897 /workspace/coverage/xbar_build_mode/0.xbar_same_source.2640500938 May 07 12:44:34 PM PDT 24 May 07 12:45:02 PM PDT 24 1251175361 ps
T898 /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3029023442 May 07 12:46:07 PM PDT 24 May 07 12:49:20 PM PDT 24 46281785568 ps
T899 /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1137544665 May 07 12:44:44 PM PDT 24 May 07 12:44:48 PM PDT 24 230673567 ps
T900 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.677928378 May 07 12:45:52 PM PDT 24 May 07 12:46:22 PM PDT 24 4006542596 ps

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.810061914
Short name T8
Test name
Test status
Simulation time 7293163254 ps
CPU time 277.19 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:50:59 PM PDT 24
Peak memory 211756 kb
Host smart-b500785b-7f2b-4a37-ad62-522bf7c13fb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=810061914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.810061914
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3519399783
Short name T5
Test name
Test status
Simulation time 50064799933 ps
CPU time 464.66 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:52:58 PM PDT 24
Peak memory 207264 kb
Host smart-4f51f414-855c-43d7-9860-efef8290bcf2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3519399783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.3519399783
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2660637829
Short name T190
Test name
Test status
Simulation time 136861479852 ps
CPU time 723.83 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:57:18 PM PDT 24
Peak memory 207560 kb
Host smart-5a794b4d-8c80-4a10-8605-0baf8045508f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2660637829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.2660637829
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.360052981
Short name T109
Test name
Test status
Simulation time 25490826415 ps
CPU time 222.04 seconds
Started May 07 12:46:13 PM PDT 24
Finished May 07 12:49:57 PM PDT 24
Peak memory 206084 kb
Host smart-99c1dfb0-4c92-4142-9ca9-0ebe865bd82d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=360052981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.360052981
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3572879236
Short name T83
Test name
Test status
Simulation time 2338022469 ps
CPU time 58.2 seconds
Started May 07 12:46:40 PM PDT 24
Finished May 07 12:47:40 PM PDT 24
Peak memory 206352 kb
Host smart-0ea5282b-7005-424f-b4d6-1ed0d4fdfa49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3572879236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3572879236
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1631146030
Short name T3
Test name
Test status
Simulation time 804051151 ps
CPU time 171.28 seconds
Started May 07 12:45:18 PM PDT 24
Finished May 07 12:48:12 PM PDT 24
Peak memory 208252 kb
Host smart-ffef709c-9fb4-4e42-8124-19c5b5c5bf68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1631146030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.1631146030
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.663571712
Short name T84
Test name
Test status
Simulation time 6656246564 ps
CPU time 225.01 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:48:59 PM PDT 24
Peak memory 207504 kb
Host smart-32adc8dc-ea42-4d68-af86-89a89d72ad6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=663571712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.663571712
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1774113084
Short name T49
Test name
Test status
Simulation time 27517443882 ps
CPU time 123.41 seconds
Started May 07 12:44:45 PM PDT 24
Finished May 07 12:46:50 PM PDT 24
Peak memory 211752 kb
Host smart-03312f99-aaf2-4523-b1e6-b24e968de2cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774113084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1774113084
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2902874890
Short name T80
Test name
Test status
Simulation time 1709282115 ps
CPU time 44.9 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:46:14 PM PDT 24
Peak memory 206352 kb
Host smart-d79d7c9f-74a0-4125-90c0-bce9b198c6fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2902874890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2902874890
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.20666518
Short name T28
Test name
Test status
Simulation time 14893947494 ps
CPU time 358 seconds
Started May 07 12:46:05 PM PDT 24
Finished May 07 12:52:04 PM PDT 24
Peak memory 219976 kb
Host smart-ca39a9dd-f5d9-482a-8888-f4e8f40deb99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20666518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rese
t_error.20666518
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.823352799
Short name T126
Test name
Test status
Simulation time 5032507543 ps
CPU time 187.99 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:48:17 PM PDT 24
Peak memory 210132 kb
Host smart-f46f237b-413b-46b7-a6ce-74f58bb856eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=823352799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.823352799
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1920458852
Short name T30
Test name
Test status
Simulation time 1707513596 ps
CPU time 246.67 seconds
Started May 07 12:46:34 PM PDT 24
Finished May 07 12:50:43 PM PDT 24
Peak memory 219888 kb
Host smart-2aef7f8b-023d-49c2-bada-99bc42a36a60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1920458852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1920458852
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.86744386
Short name T265
Test name
Test status
Simulation time 536143710 ps
CPU time 169.6 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:48:07 PM PDT 24
Peak memory 208552 kb
Host smart-58f24668-4ca8-4b0b-bdf3-283074dbd930
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86744386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_r
eset.86744386
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2770177714
Short name T283
Test name
Test status
Simulation time 974575284 ps
CPU time 136.49 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:48:56 PM PDT 24
Peak memory 210060 kb
Host smart-1d6a5cfe-468f-4a4c-a8a6-7fe382e4c12a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2770177714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.2770177714
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.598038779
Short name T72
Test name
Test status
Simulation time 154517375 ps
CPU time 11.65 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:45:41 PM PDT 24
Peak memory 204712 kb
Host smart-6b6592f1-4226-40b5-8261-20ba1d843796
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598038779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.598038779
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3298745462
Short name T25
Test name
Test status
Simulation time 1157914993 ps
CPU time 344.46 seconds
Started May 07 12:45:37 PM PDT 24
Finished May 07 12:51:23 PM PDT 24
Peak memory 219912 kb
Host smart-383ce917-08c2-4fb2-a7e9-0a28af0c3713
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3298745462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.3298745462
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3243755037
Short name T272
Test name
Test status
Simulation time 8287456536 ps
CPU time 91.15 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:46:05 PM PDT 24
Peak memory 207488 kb
Host smart-1530f4c5-f104-4e4f-a851-5db62d7cbb58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3243755037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3243755037
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1921253268
Short name T39
Test name
Test status
Simulation time 4175189284 ps
CPU time 184.45 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:48:37 PM PDT 24
Peak memory 208464 kb
Host smart-3521bad9-f00c-4e70-97f5-1a940a8fe9ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1921253268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.1921253268
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.439263973
Short name T43
Test name
Test status
Simulation time 467154572 ps
CPU time 129.86 seconds
Started May 07 12:45:04 PM PDT 24
Finished May 07 12:47:15 PM PDT 24
Peak memory 207860 kb
Host smart-7f338796-949d-4d5c-9991-d6868b5c33c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=439263973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_
reset.439263973
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1080668760
Short name T698
Test name
Test status
Simulation time 2445316126 ps
CPU time 57.15 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:45:34 PM PDT 24
Peak memory 206488 kb
Host smart-48c65aff-4520-49d8-85e3-9126ab6bdd7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1080668760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1080668760
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2892025285
Short name T530
Test name
Test status
Simulation time 52616250339 ps
CPU time 473.25 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:52:31 PM PDT 24
Peak memory 207092 kb
Host smart-03b5d48f-ff8f-4ea1-98b7-c1ba24c70da4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2892025285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2892025285
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2325705097
Short name T455
Test name
Test status
Simulation time 1011789834 ps
CPU time 28.94 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:45:02 PM PDT 24
Peak memory 203672 kb
Host smart-d2bd97b2-f18e-4742-bd3b-9fdbda8455d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2325705097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2325705097
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.659527055
Short name T388
Test name
Test status
Simulation time 213604031 ps
CPU time 20.81 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:52 PM PDT 24
Peak memory 203520 kb
Host smart-a190cd72-8275-4625-94e3-d0c44957fce1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=659527055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.659527055
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3495808477
Short name T861
Test name
Test status
Simulation time 672919754 ps
CPU time 28.11 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 204912 kb
Host smart-55ddafff-4741-4453-b7a3-720eb1390dd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3495808477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3495808477
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.260963693
Short name T268
Test name
Test status
Simulation time 18539635318 ps
CPU time 71.23 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:45:47 PM PDT 24
Peak memory 211536 kb
Host smart-8dfb53e9-0176-49a5-8880-a80356212a21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=260963693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.260963693
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.341290239
Short name T67
Test name
Test status
Simulation time 215476111 ps
CPU time 28.65 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:45:07 PM PDT 24
Peak memory 204584 kb
Host smart-11423e20-f3e8-4275-973a-a8f3d9e095e8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341290239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.341290239
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.2640500938
Short name T897
Test name
Test status
Simulation time 1251175361 ps
CPU time 25.41 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:45:02 PM PDT 24
Peak memory 203548 kb
Host smart-268d433d-3548-4aa5-841e-76465b2a8262
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2640500938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2640500938
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.1622580168
Short name T66
Test name
Test status
Simulation time 272577055 ps
CPU time 3.66 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:44:42 PM PDT 24
Peak memory 203496 kb
Host smart-69a1e9ac-bec4-4214-804c-0643a26996fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1622580168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1622580168
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.4028003542
Short name T684
Test name
Test status
Simulation time 4755565373 ps
CPU time 28.27 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:45:17 PM PDT 24
Peak memory 203576 kb
Host smart-43693000-8c9f-4e93-8f2c-1e2571ff0376
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028003542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4028003542
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.217750800
Short name T477
Test name
Test status
Simulation time 4213238123 ps
CPU time 36.57 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:45:15 PM PDT 24
Peak memory 203560 kb
Host smart-e6ce288c-b4d6-4e9e-a425-0d9ab1aae68b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=217750800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.217750800
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2690485231
Short name T10
Test name
Test status
Simulation time 25935471 ps
CPU time 2.03 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:31 PM PDT 24
Peak memory 203484 kb
Host smart-7484de15-0f98-4834-8501-4321bfcfb218
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690485231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2690485231
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.1033537603
Short name T502
Test name
Test status
Simulation time 11527011650 ps
CPU time 241.13 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:48:36 PM PDT 24
Peak memory 210864 kb
Host smart-6e39b4d0-54f3-4c4f-a4ad-b8beb17689b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1033537603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1033537603
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.961699380
Short name T526
Test name
Test status
Simulation time 6238269 ps
CPU time 0.76 seconds
Started May 07 12:44:38 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 195228 kb
Host smart-179126d2-e045-49e4-b07a-35e3db5a411e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=961699380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.961699380
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3577569570
Short name T135
Test name
Test status
Simulation time 4285613124 ps
CPU time 380.97 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:51:03 PM PDT 24
Peak memory 210256 kb
Host smart-7846c409-b20c-49b6-b814-c172de3d7778
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3577569570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.3577569570
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3405400427
Short name T429
Test name
Test status
Simulation time 3754438197 ps
CPU time 464.61 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:52:22 PM PDT 24
Peak memory 219936 kb
Host smart-846dee8b-f49d-4379-8775-96d2037a3c37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3405400427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.3405400427
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.86708850
Short name T396
Test name
Test status
Simulation time 41214307 ps
CPU time 5.82 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 204908 kb
Host smart-7fe8d2f9-f4f9-44b1-bda1-38f55042f48b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86708850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.86708850
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.780178540
Short name T124
Test name
Test status
Simulation time 2007590046 ps
CPU time 41.25 seconds
Started May 07 12:44:43 PM PDT 24
Finished May 07 12:45:25 PM PDT 24
Peak memory 205132 kb
Host smart-bb01a204-2b64-4910-8073-e86e14a4d45b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=780178540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.780178540
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2653790142
Short name T228
Test name
Test status
Simulation time 32122053430 ps
CPU time 301.39 seconds
Started May 07 12:44:37 PM PDT 24
Finished May 07 12:49:41 PM PDT 24
Peak memory 211756 kb
Host smart-3dcf5288-9551-4c21-ba93-0366c47fff94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2653790142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.2653790142
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1262204559
Short name T104
Test name
Test status
Simulation time 32859109 ps
CPU time 3.33 seconds
Started May 07 12:44:39 PM PDT 24
Finished May 07 12:44:44 PM PDT 24
Peak memory 203552 kb
Host smart-532c266d-f363-4809-9932-4b221c897c81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262204559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1262204559
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.120923431
Short name T705
Test name
Test status
Simulation time 222288088 ps
CPU time 23.64 seconds
Started May 07 12:44:46 PM PDT 24
Finished May 07 12:45:10 PM PDT 24
Peak memory 203596 kb
Host smart-f6b41181-16fd-45b2-9d49-552caef40061
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=120923431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.120923431
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.3499849504
Short name T233
Test name
Test status
Simulation time 227039968 ps
CPU time 24.38 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:45:02 PM PDT 24
Peak memory 204912 kb
Host smart-8ab6896a-eaee-4ff9-8be9-99ad1f8bb047
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3499849504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3499849504
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2579150413
Short name T693
Test name
Test status
Simulation time 65585931954 ps
CPU time 182.28 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:47:34 PM PDT 24
Peak memory 205304 kb
Host smart-52a82315-3858-410f-8125-cb4d6090c403
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579150413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2579150413
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.374972883
Short name T818
Test name
Test status
Simulation time 6716377048 ps
CPU time 46.74 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 204848 kb
Host smart-3072e0e9-8f0b-4979-ae99-17fc988ba6e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=374972883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.374972883
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1047333372
Short name T746
Test name
Test status
Simulation time 58384246 ps
CPU time 4.55 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:42 PM PDT 24
Peak memory 204280 kb
Host smart-e4c2e437-a90a-42d0-8ef8-cc63d4b8a68b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047333372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1047333372
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.3218932756
Short name T270
Test name
Test status
Simulation time 1627471383 ps
CPU time 16.58 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:45:05 PM PDT 24
Peak memory 204012 kb
Host smart-c8ad73c4-8674-45e7-a4c9-dc84676e6b33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3218932756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3218932756
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.1638359707
Short name T321
Test name
Test status
Simulation time 250668809 ps
CPU time 3.49 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:41 PM PDT 24
Peak memory 203496 kb
Host smart-8107e300-2832-471f-959a-c8d81dc605a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1638359707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1638359707
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2311744436
Short name T271
Test name
Test status
Simulation time 17749602803 ps
CPU time 41.53 seconds
Started May 07 12:44:49 PM PDT 24
Finished May 07 12:45:32 PM PDT 24
Peak memory 203352 kb
Host smart-626f9bdb-aab9-4cb0-96b6-fd28622edef3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311744436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2311744436
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1726588064
Short name T470
Test name
Test status
Simulation time 3563721752 ps
CPU time 26.61 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:45:05 PM PDT 24
Peak memory 203568 kb
Host smart-1d29df12-6200-4a0b-87a3-72659b38f9d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1726588064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1726588064
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2034503708
Short name T521
Test name
Test status
Simulation time 32204781 ps
CPU time 2.42 seconds
Started May 07 12:44:53 PM PDT 24
Finished May 07 12:44:56 PM PDT 24
Peak memory 203400 kb
Host smart-40635eb3-2dd0-4c0c-9627-44307a749452
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034503708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2034503708
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3169549364
Short name T858
Test name
Test status
Simulation time 24339527445 ps
CPU time 197.52 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:47:54 PM PDT 24
Peak memory 207544 kb
Host smart-08b05e6f-9d23-434a-b39e-59b89bcf1b88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3169549364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3169549364
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1508689958
Short name T739
Test name
Test status
Simulation time 43850812 ps
CPU time 7.43 seconds
Started May 07 12:44:46 PM PDT 24
Finished May 07 12:44:54 PM PDT 24
Peak memory 206048 kb
Host smart-265c98f4-bbd9-4ad3-934a-a89107ec0c2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1508689958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.1508689958
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1698818897
Short name T7
Test name
Test status
Simulation time 17279675 ps
CPU time 7.56 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:44 PM PDT 24
Peak memory 204388 kb
Host smart-5d7a3da9-6a72-461d-9715-19c8c0e6b159
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698818897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.1698818897
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1473666040
Short name T6
Test name
Test status
Simulation time 576285810 ps
CPU time 19.78 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:44:58 PM PDT 24
Peak memory 205148 kb
Host smart-f9664c96-5dc6-4ddf-81ea-f7aecd2fcb51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1473666040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1473666040
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3368849659
Short name T370
Test name
Test status
Simulation time 28133430 ps
CPU time 4.69 seconds
Started May 07 12:45:24 PM PDT 24
Finished May 07 12:45:31 PM PDT 24
Peak memory 203632 kb
Host smart-fc881f4f-c248-4334-bbbd-a3125b67c48a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3368849659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3368849659
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1128653905
Short name T577
Test name
Test status
Simulation time 595593725 ps
CPU time 18.14 seconds
Started May 07 12:45:00 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203656 kb
Host smart-05e7bba5-df10-4170-b77a-c1b5269e09e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1128653905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1128653905
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.4290318644
Short name T854
Test name
Test status
Simulation time 175641840 ps
CPU time 17.82 seconds
Started May 07 12:45:04 PM PDT 24
Finished May 07 12:45:23 PM PDT 24
Peak memory 203512 kb
Host smart-95a94762-de53-4b45-835b-88b993cdf1ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4290318644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4290318644
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.3099986880
Short name T731
Test name
Test status
Simulation time 60941655 ps
CPU time 7.72 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:18 PM PDT 24
Peak memory 211644 kb
Host smart-d67785fe-a63f-4d6b-8c92-96f5d6460c98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3099986880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3099986880
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3998961201
Short name T663
Test name
Test status
Simulation time 72219994763 ps
CPU time 267.15 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:49:47 PM PDT 24
Peak memory 204836 kb
Host smart-23ed223b-ba5a-42b6-9857-4445b1c81b6d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998961201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3998961201
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3164583416
Short name T339
Test name
Test status
Simulation time 25983357855 ps
CPU time 238.18 seconds
Started May 07 12:44:52 PM PDT 24
Finished May 07 12:48:51 PM PDT 24
Peak memory 211756 kb
Host smart-3aef8b74-a571-4469-9b8a-aa2c1eee9aef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3164583416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3164583416
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1826987984
Short name T825
Test name
Test status
Simulation time 54053664 ps
CPU time 5.58 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:45:25 PM PDT 24
Peak memory 204512 kb
Host smart-5ff2c00b-09b4-4bff-9786-2f8a02b028fb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826987984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1826987984
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.3851404086
Short name T360
Test name
Test status
Simulation time 72431604 ps
CPU time 5.98 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:45:27 PM PDT 24
Peak memory 203540 kb
Host smart-150fa07d-30c1-4a67-bfc7-9a1d3733389c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3851404086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3851404086
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.3622264051
Short name T221
Test name
Test status
Simulation time 425628013 ps
CPU time 3.62 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:14 PM PDT 24
Peak memory 203492 kb
Host smart-74dbd920-5ed2-425f-8d9d-3a4c83b40309
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3622264051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3622264051
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1199431171
Short name T393
Test name
Test status
Simulation time 6292512823 ps
CPU time 34.22 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:52 PM PDT 24
Peak memory 203536 kb
Host smart-6f8b86f2-02d6-48ce-a492-901493c2458b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199431171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1199431171
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1188413851
Short name T831
Test name
Test status
Simulation time 7272424626 ps
CPU time 32.21 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:46 PM PDT 24
Peak memory 203532 kb
Host smart-98aee97b-ec78-40a4-b338-3bd2c8470364
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1188413851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1188413851
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3556235128
Short name T303
Test name
Test status
Simulation time 35614952 ps
CPU time 2.17 seconds
Started May 07 12:44:55 PM PDT 24
Finished May 07 12:44:58 PM PDT 24
Peak memory 203484 kb
Host smart-d779e3fb-6f63-49e4-9f69-a01484ad298f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556235128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3556235128
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3273344501
Short name T185
Test name
Test status
Simulation time 2388076770 ps
CPU time 59.98 seconds
Started May 07 12:44:44 PM PDT 24
Finished May 07 12:45:45 PM PDT 24
Peak memory 205924 kb
Host smart-26563982-b874-4051-8bf5-41ab9069224b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3273344501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3273344501
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.996166153
Short name T451
Test name
Test status
Simulation time 10966569427 ps
CPU time 394.34 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:51:45 PM PDT 24
Peak memory 213648 kb
Host smart-854db598-df95-4f28-a384-7aa906072ce2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=996166153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.996166153
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3864262644
Short name T664
Test name
Test status
Simulation time 2394982189 ps
CPU time 520.5 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:54:01 PM PDT 24
Peak memory 220020 kb
Host smart-18b078ba-ac54-4e3a-8bee-1fc7aeefd120
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3864262644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.3864262644
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.216568805
Short name T273
Test name
Test status
Simulation time 7581876077 ps
CPU time 257.12 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:49:09 PM PDT 24
Peak memory 222488 kb
Host smart-2bac577e-27a6-41a1-b609-d000c1c18a0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=216568805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_res
et_error.216568805
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2126910663
Short name T193
Test name
Test status
Simulation time 348124515 ps
CPU time 20.75 seconds
Started May 07 12:45:01 PM PDT 24
Finished May 07 12:45:22 PM PDT 24
Peak memory 204940 kb
Host smart-f9814710-d47f-416b-9241-37a071ce7b2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2126910663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2126910663
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.597754766
Short name T628
Test name
Test status
Simulation time 2825211892 ps
CPU time 57.34 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:46:14 PM PDT 24
Peak memory 206596 kb
Host smart-150acc0d-0397-4cb1-bba5-c9054162d65b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=597754766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.597754766
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.580650148
Short name T796
Test name
Test status
Simulation time 47014996110 ps
CPU time 483.49 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:53:17 PM PDT 24
Peak memory 211752 kb
Host smart-b7598414-cc99-48db-bee6-aa57e076d750
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=580650148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo
w_rsp.580650148
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4200379818
Short name T368
Test name
Test status
Simulation time 1755703881 ps
CPU time 18.37 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:30 PM PDT 24
Peak memory 203808 kb
Host smart-eab6179c-cb28-4c70-9539-c7d9d057070e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4200379818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4200379818
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.503553953
Short name T216
Test name
Test status
Simulation time 236792331 ps
CPU time 4.28 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:45:17 PM PDT 24
Peak memory 203548 kb
Host smart-cdabf339-25af-496a-bed7-b35291bf8cf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=503553953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.503553953
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.2397706645
Short name T106
Test name
Test status
Simulation time 980121571 ps
CPU time 35.43 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:45:33 PM PDT 24
Peak memory 204616 kb
Host smart-a237651f-5246-4ea5-9cac-b30430041e6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2397706645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2397706645
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.4001894035
Short name T264
Test name
Test status
Simulation time 21352180618 ps
CPU time 110.84 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:47:19 PM PDT 24
Peak memory 211828 kb
Host smart-45b37bcc-ca59-41d6-bcc0-d728779c8237
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001894035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4001894035
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.17423789
Short name T107
Test name
Test status
Simulation time 57844902682 ps
CPU time 223.1 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:48:56 PM PDT 24
Peak memory 211744 kb
Host smart-2e807d6c-d851-416c-9854-1a0854a121da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=17423789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.17423789
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1690471455
Short name T363
Test name
Test status
Simulation time 330840952 ps
CPU time 20.89 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 211600 kb
Host smart-7a18b046-885e-420e-b39c-b12a4815dc55
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690471455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1690471455
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.3591693455
Short name T489
Test name
Test status
Simulation time 4996274286 ps
CPU time 18.7 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:29 PM PDT 24
Peak memory 211720 kb
Host smart-d173b42a-7c7a-4b7a-9a62-07b4835cde64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3591693455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3591693455
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.3860879382
Short name T490
Test name
Test status
Simulation time 179973685 ps
CPU time 3.77 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 203500 kb
Host smart-c9c64755-73f1-49ed-812e-45d0d907fab4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3860879382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3860879382
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4209962972
Short name T357
Test name
Test status
Simulation time 43613694433 ps
CPU time 55.15 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 203564 kb
Host smart-bdcff766-fb2e-4d6d-9abd-9a1797d1f29b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209962972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4209962972
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3998346358
Short name T439
Test name
Test status
Simulation time 3224281183 ps
CPU time 25.99 seconds
Started May 07 12:44:58 PM PDT 24
Finished May 07 12:45:25 PM PDT 24
Peak memory 203460 kb
Host smart-ba8458d4-51e9-4c31-b451-1fc96bac0f46
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3998346358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3998346358
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.4103548397
Short name T734
Test name
Test status
Simulation time 78714331 ps
CPU time 2.39 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:09 PM PDT 24
Peak memory 203504 kb
Host smart-e8a25beb-1768-47cc-a5be-f39d09fa2a1e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103548397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.4103548397
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1256201492
Short name T210
Test name
Test status
Simulation time 3591862151 ps
CPU time 124.49 seconds
Started May 07 12:44:59 PM PDT 24
Finished May 07 12:47:04 PM PDT 24
Peak memory 208904 kb
Host smart-dd8643ae-cf37-4b1a-8baa-5c5a9353b847
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1256201492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1256201492
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1132462144
Short name T689
Test name
Test status
Simulation time 2562499598 ps
CPU time 69.43 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:46:16 PM PDT 24
Peak memory 204056 kb
Host smart-c8152ed3-bb09-48a1-88f3-b7803e10d250
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1132462144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1132462144
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2842628392
Short name T402
Test name
Test status
Simulation time 591886634 ps
CPU time 161.21 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:47:50 PM PDT 24
Peak memory 208240 kb
Host smart-04af00cc-66ad-4a0f-bf1d-83efb8c650da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2842628392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.2842628392
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2867092070
Short name T862
Test name
Test status
Simulation time 8032977516 ps
CPU time 63.21 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 207668 kb
Host smart-0765cc75-527e-4ee8-aba2-dca82a8fd13b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2867092070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.2867092070
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.389920326
Short name T570
Test name
Test status
Simulation time 210360238 ps
CPU time 12.54 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:28 PM PDT 24
Peak memory 205060 kb
Host smart-eba3593e-28d0-40d0-bc67-d35676789e3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=389920326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.389920326
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.619923532
Short name T518
Test name
Test status
Simulation time 472311981 ps
CPU time 17.91 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:29 PM PDT 24
Peak memory 211656 kb
Host smart-6aea26e5-041c-4c83-892b-a6d1928e911c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=619923532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.619923532
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.516537228
Short name T245
Test name
Test status
Simulation time 102744661698 ps
CPU time 308.35 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:50:23 PM PDT 24
Peak memory 206648 kb
Host smart-0dcd5b72-508c-45bf-b5e6-505785354548
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=516537228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slo
w_rsp.516537228
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1293855830
Short name T407
Test name
Test status
Simulation time 163824418 ps
CPU time 15.77 seconds
Started May 07 12:45:18 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 203968 kb
Host smart-085af20e-9d71-42b5-9f77-3d6ea283fb88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1293855830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1293855830
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.3903526601
Short name T614
Test name
Test status
Simulation time 63797426 ps
CPU time 9.42 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:16 PM PDT 24
Peak memory 203500 kb
Host smart-6d19f62a-21ce-4bb3-bcc9-817bfc92c452
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3903526601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3903526601
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.851702238
Short name T616
Test name
Test status
Simulation time 3283486888 ps
CPU time 28.62 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:56 PM PDT 24
Peak memory 204736 kb
Host smart-e41f491b-0461-49ba-86e8-f8a5e7183e84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=851702238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.851702238
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2029641369
Short name T462
Test name
Test status
Simulation time 42034755873 ps
CPU time 248.01 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:49:24 PM PDT 24
Peak memory 204996 kb
Host smart-59955751-1761-4cee-b010-b5291d9fc150
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029641369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2029641369
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2458429240
Short name T661
Test name
Test status
Simulation time 18761820495 ps
CPU time 191.43 seconds
Started May 07 12:45:18 PM PDT 24
Finished May 07 12:48:33 PM PDT 24
Peak memory 205084 kb
Host smart-179a97cc-97a0-4b62-8891-6bd35d9a30a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2458429240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2458429240
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1217382639
Short name T819
Test name
Test status
Simulation time 81596084 ps
CPU time 7.2 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 204648 kb
Host smart-9262d509-b1e7-4821-9c32-0c76cc302005
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217382639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1217382639
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.2556727059
Short name T881
Test name
Test status
Simulation time 85873732 ps
CPU time 7.02 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:22 PM PDT 24
Peak memory 203508 kb
Host smart-118cddf6-31d9-4d29-949e-d5447317a482
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2556727059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2556727059
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.172500389
Short name T326
Test name
Test status
Simulation time 165249686 ps
CPU time 3.12 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:13 PM PDT 24
Peak memory 203464 kb
Host smart-fb0ed1c1-8a50-4fff-8516-0d651a637053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=172500389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.172500389
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1722195865
Short name T300
Test name
Test status
Simulation time 5794286583 ps
CPU time 32.77 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:48 PM PDT 24
Peak memory 203588 kb
Host smart-d7daf856-32db-4029-8480-b070d8919b4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722195865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1722195865
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3705295084
Short name T495
Test name
Test status
Simulation time 9960035616 ps
CPU time 30.52 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203576 kb
Host smart-bcb8465a-9d72-4e32-8875-217960038010
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3705295084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3705295084
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.353746057
Short name T120
Test name
Test status
Simulation time 36598959 ps
CPU time 2.44 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:45:26 PM PDT 24
Peak memory 203464 kb
Host smart-54479f28-9361-4fdb-9ee1-919ce9ccfdad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353746057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.353746057
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.94954168
Short name T808
Test name
Test status
Simulation time 3750101060 ps
CPU time 91.33 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:46:52 PM PDT 24
Peak memory 205960 kb
Host smart-a6b3e02f-629f-435e-982b-8540d17f1d87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94954168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.94954168
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2026691874
Short name T830
Test name
Test status
Simulation time 7810221870 ps
CPU time 118.26 seconds
Started May 07 12:45:00 PM PDT 24
Finished May 07 12:46:59 PM PDT 24
Peak memory 206688 kb
Host smart-e0e4e4cc-8db5-4a87-aa29-0edf3fd54469
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2026691874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2026691874
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3336089763
Short name T453
Test name
Test status
Simulation time 1242400000 ps
CPU time 70.47 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 207784 kb
Host smart-5bb156c8-d564-42f9-8629-293e13439614
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3336089763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.3336089763
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3588652693
Short name T801
Test name
Test status
Simulation time 67547848 ps
CPU time 9.21 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:23 PM PDT 24
Peak memory 205020 kb
Host smart-f7d9c1e2-782d-457b-8e4b-bff62042dd66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3588652693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3588652693
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2779941749
Short name T700
Test name
Test status
Simulation time 684433186 ps
CPU time 38.83 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:45:59 PM PDT 24
Peak memory 211680 kb
Host smart-61992aac-b92b-4c86-a4e4-ddb4304e161e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2779941749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2779941749
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2721469611
Short name T605
Test name
Test status
Simulation time 102628118 ps
CPU time 5.34 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 203780 kb
Host smart-9cd0ddd2-214c-4c55-96e3-7a074cc1eef5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2721469611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2721469611
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.3463809354
Short name T838
Test name
Test status
Simulation time 14643664 ps
CPU time 2.23 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203496 kb
Host smart-8f2261de-2cfc-4dcf-bf34-05da05a14886
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3463809354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3463809354
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.96789501
Short name T154
Test name
Test status
Simulation time 401362656 ps
CPU time 14.73 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:25 PM PDT 24
Peak memory 204536 kb
Host smart-38a8a727-a4dc-408e-9344-bae14968e1d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96789501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.96789501
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3693332550
Short name T657
Test name
Test status
Simulation time 11155169243 ps
CPU time 64.29 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:46:11 PM PDT 24
Peak memory 211736 kb
Host smart-81cf682d-02a5-40b4-80b9-11728c0471f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693332550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3693332550
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1040695182
Short name T182
Test name
Test status
Simulation time 20976974526 ps
CPU time 155.01 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:47:43 PM PDT 24
Peak memory 205292 kb
Host smart-58fb9709-9e59-4e5e-afcd-d70d30fea3c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1040695182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1040695182
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2342075688
Short name T359
Test name
Test status
Simulation time 208279188 ps
CPU time 6.42 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:34 PM PDT 24
Peak memory 211672 kb
Host smart-fee7d3af-b919-49b0-90ec-85cacdaed1e9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342075688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2342075688
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.3931973026
Short name T205
Test name
Test status
Simulation time 437854301 ps
CPU time 12.38 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 204084 kb
Host smart-0cfe4179-3902-471e-8a50-127630e80393
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3931973026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3931973026
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.209527017
Short name T459
Test name
Test status
Simulation time 170187511 ps
CPU time 3.64 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 203448 kb
Host smart-c231b99f-bb43-4cf1-a9b3-479077a9563a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=209527017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.209527017
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.777971207
Short name T617
Test name
Test status
Simulation time 8705302048 ps
CPU time 33 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:42 PM PDT 24
Peak memory 203560 kb
Host smart-3ae5634c-8655-46f8-9266-c135e20a007c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=777971207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.777971207
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3582096773
Short name T100
Test name
Test status
Simulation time 12827615582 ps
CPU time 30.17 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 203516 kb
Host smart-eae9ff02-15d4-4d22-8765-fcc08244f199
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3582096773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3582096773
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2055717360
Short name T513
Test name
Test status
Simulation time 68936013 ps
CPU time 2.58 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:45:15 PM PDT 24
Peak memory 203488 kb
Host smart-66ca8bb4-bd43-40c3-a52f-5097dc25a18e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055717360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2055717360
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3638276117
Short name T145
Test name
Test status
Simulation time 6039499200 ps
CPU time 131 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:47:21 PM PDT 24
Peak memory 211736 kb
Host smart-ecf9de78-2d37-436b-9a0f-c7800990aa48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3638276117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3638276117
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.112172399
Short name T156
Test name
Test status
Simulation time 9114232386 ps
CPU time 187.97 seconds
Started May 07 12:45:18 PM PDT 24
Finished May 07 12:48:29 PM PDT 24
Peak memory 209396 kb
Host smart-ec7462d7-de42-48e8-9078-f997249e7c44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112172399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.112172399
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1884640418
Short name T252
Test name
Test status
Simulation time 10137344206 ps
CPU time 403.76 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:51:55 PM PDT 24
Peak memory 208616 kb
Host smart-8314ab69-3127-4e4b-8d4a-cafc8d98584d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1884640418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.1884640418
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3558553369
Short name T552
Test name
Test status
Simulation time 498263176 ps
CPU time 151.11 seconds
Started May 07 12:45:21 PM PDT 24
Finished May 07 12:47:54 PM PDT 24
Peak memory 211676 kb
Host smart-e8cf9018-c6bf-4d76-9973-342d9a981747
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558553369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.3558553369
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.4123435478
Short name T171
Test name
Test status
Simulation time 909788973 ps
CPU time 16.9 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:34 PM PDT 24
Peak memory 204960 kb
Host smart-837a98bb-b9b4-4715-b032-24ebd61ee611
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4123435478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4123435478
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.297079672
Short name T760
Test name
Test status
Simulation time 863219063 ps
CPU time 18.53 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:29 PM PDT 24
Peak memory 204384 kb
Host smart-7b5e07b4-c2ff-4bd0-9252-7560362a6f00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=297079672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.297079672
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.375974146
Short name T708
Test name
Test status
Simulation time 148902909543 ps
CPU time 690.91 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:56:40 PM PDT 24
Peak memory 207596 kb
Host smart-4de5fd85-c0dc-40bc-89f8-52355828cdb8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=375974146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slo
w_rsp.375974146
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2728486173
Short name T557
Test name
Test status
Simulation time 1924810777 ps
CPU time 29.82 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 203804 kb
Host smart-d20d4ad1-2a91-44bb-9222-e3ac760319d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2728486173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2728486173
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.841300598
Short name T505
Test name
Test status
Simulation time 106111773 ps
CPU time 9.96 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:27 PM PDT 24
Peak memory 203504 kb
Host smart-8861a661-86cb-4b58-85e1-90c7c55eee37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=841300598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.841300598
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.1204483606
Short name T524
Test name
Test status
Simulation time 1722158011 ps
CPU time 12.13 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 204604 kb
Host smart-0c10ac9f-ab72-4d3b-9001-1371f43db3f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1204483606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1204483606
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3972012160
Short name T32
Test name
Test status
Simulation time 33118347880 ps
CPU time 199.83 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:48:34 PM PDT 24
Peak memory 211752 kb
Host smart-728db797-5f42-4b0e-b100-c7cd83bb5a74
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972012160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3972012160
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2040891038
Short name T894
Test name
Test status
Simulation time 10243252581 ps
CPU time 80.33 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 204824 kb
Host smart-2f3e41c3-3f59-4698-b597-1ff3733b2168
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2040891038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2040891038
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.69970071
Short name T889
Test name
Test status
Simulation time 16348021 ps
CPU time 2.5 seconds
Started May 07 12:45:20 PM PDT 24
Finished May 07 12:45:25 PM PDT 24
Peak memory 203412 kb
Host smart-dc93cb0e-179f-46ab-8edf-d574b6b2fb2c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69970071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.69970071
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1482605798
Short name T380
Test name
Test status
Simulation time 94302952 ps
CPU time 7.11 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 203516 kb
Host smart-9761d108-42d1-4062-91e0-b26b557fd4d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1482605798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1482605798
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.1907328593
Short name T79
Test name
Test status
Simulation time 224931250 ps
CPU time 4.06 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:45:33 PM PDT 24
Peak memory 203480 kb
Host smart-1b9b9b7a-af7c-463a-9238-53560f580856
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1907328593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1907328593
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3871978973
Short name T713
Test name
Test status
Simulation time 6180891639 ps
CPU time 31.99 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 203540 kb
Host smart-2317fb7e-2b4f-4024-bc44-c71116215e5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871978973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3871978973
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1798939026
Short name T312
Test name
Test status
Simulation time 8676612208 ps
CPU time 33.2 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 203460 kb
Host smart-1a02f7c0-21f0-44c3-aaaf-83e3a8725939
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1798939026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1798939026
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1415612619
Short name T232
Test name
Test status
Simulation time 24377364 ps
CPU time 2.06 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:13 PM PDT 24
Peak memory 203476 kb
Host smart-883ce2fb-0609-4611-9877-71e556f2fd16
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415612619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1415612619
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2115626062
Short name T638
Test name
Test status
Simulation time 3668191842 ps
CPU time 103.07 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:46:53 PM PDT 24
Peak memory 208104 kb
Host smart-df959bfd-a1ab-43d4-96ad-40d178f6ae1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2115626062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2115626062
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1065953903
Short name T890
Test name
Test status
Simulation time 11049443794 ps
CPU time 92.81 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:46:53 PM PDT 24
Peak memory 205436 kb
Host smart-6af0e4dc-6b5c-4e27-b2c5-cab4fdce2d00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1065953903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1065953903
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3594004897
Short name T186
Test name
Test status
Simulation time 3621803280 ps
CPU time 360.46 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:51:31 PM PDT 24
Peak memory 208376 kb
Host smart-558863f6-1475-42bf-9473-2b0883d54b1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3594004897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.3594004897
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2879258495
Short name T615
Test name
Test status
Simulation time 256083925 ps
CPU time 54.96 seconds
Started May 07 12:45:20 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 208400 kb
Host smart-cdef7208-77eb-4b07-a177-8bde9a1fa119
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2879258495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.2879258495
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.57861027
Short name T409
Test name
Test status
Simulation time 69149461 ps
CPU time 2.73 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:17 PM PDT 24
Peak memory 203496 kb
Host smart-aeecaf12-cefe-4779-8ee2-df9179f14962
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57861027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.57861027
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2279989021
Short name T776
Test name
Test status
Simulation time 141014484 ps
CPU time 7.31 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:16 PM PDT 24
Peak memory 204476 kb
Host smart-6e86b803-c1e1-4f65-9364-ffde82bf1bf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2279989021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2279989021
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1165696623
Short name T196
Test name
Test status
Simulation time 49196713418 ps
CPU time 133.79 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:47:45 PM PDT 24
Peak memory 206112 kb
Host smart-1374b25d-a7a4-4455-8a42-21f1ecdf5bc2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1165696623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1165696623
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2804003125
Short name T297
Test name
Test status
Simulation time 54650449 ps
CPU time 3.49 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 203592 kb
Host smart-7902f221-2390-403d-b891-e7dc710bb610
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2804003125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2804003125
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.993843206
Short name T799
Test name
Test status
Simulation time 1035361676 ps
CPU time 24.99 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203656 kb
Host smart-47e89db1-1046-4dc6-92bb-1e61ccab8f87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=993843206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.993843206
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.3569164551
Short name T254
Test name
Test status
Simulation time 260399653 ps
CPU time 26.81 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:45:51 PM PDT 24
Peak memory 204720 kb
Host smart-991fe9b6-1e04-47d9-b919-cd559d31a3dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3569164551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3569164551
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2133241546
Short name T500
Test name
Test status
Simulation time 95552145748 ps
CPU time 207.55 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:48:58 PM PDT 24
Peak memory 205284 kb
Host smart-10ec4b9d-a4e1-4629-bcce-46578431d24e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133241546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2133241546
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1778265929
Short name T309
Test name
Test status
Simulation time 18434466091 ps
CPU time 114.42 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:47:04 PM PDT 24
Peak memory 204468 kb
Host smart-61179aae-6841-4bce-8836-11f2f74b77f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1778265929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1778265929
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2869601787
Short name T637
Test name
Test status
Simulation time 472205833 ps
CPU time 20.81 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:45:46 PM PDT 24
Peak memory 204520 kb
Host smart-8529eab7-3ae0-4919-a2a0-6a0295aa068e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869601787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2869601787
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.782016746
Short name T529
Test name
Test status
Simulation time 1206009618 ps
CPU time 24.65 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:34 PM PDT 24
Peak memory 203272 kb
Host smart-bbf6f99e-8619-434f-82bb-74f5dadf1433
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=782016746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.782016746
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.1247050060
Short name T603
Test name
Test status
Simulation time 1097477905 ps
CPU time 5.21 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:45:31 PM PDT 24
Peak memory 203492 kb
Host smart-4b2e1eb4-10d8-4e31-b149-d122b16ce2a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1247050060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1247050060
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.4041833446
Short name T494
Test name
Test status
Simulation time 6670746513 ps
CPU time 30.22 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 203516 kb
Host smart-ebda358a-a0a6-454c-9fb3-1c98d744119b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041833446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.4041833446
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.206941008
Short name T204
Test name
Test status
Simulation time 3886645643 ps
CPU time 29 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:57 PM PDT 24
Peak memory 203560 kb
Host smart-bee3ec6e-32c3-452e-8918-0c9420b7b828
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=206941008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.206941008
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.822958916
Short name T314
Test name
Test status
Simulation time 49198481 ps
CPU time 2.36 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 203488 kb
Host smart-4322e4ef-da43-43fd-b4f1-5168fdf82634
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822958916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.822958916
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.880442438
Short name T531
Test name
Test status
Simulation time 6017744289 ps
CPU time 215.61 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:48:45 PM PDT 24
Peak memory 208864 kb
Host smart-57a7f72f-acbc-432f-a728-60fd9b66aa75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=880442438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.880442438
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.877118635
Short name T882
Test name
Test status
Simulation time 1414780592 ps
CPU time 129.07 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:47:20 PM PDT 24
Peak memory 209092 kb
Host smart-fec4cd35-f8da-45fc-98a4-b26b0488eb38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=877118635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.877118635
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1219679343
Short name T738
Test name
Test status
Simulation time 436735172 ps
CPU time 152.36 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:48:03 PM PDT 24
Peak memory 208144 kb
Host smart-caa0e998-8082-447b-8bc8-19d961147a12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1219679343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.1219679343
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.435354017
Short name T35
Test name
Test status
Simulation time 531159339 ps
CPU time 163.35 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:47:52 PM PDT 24
Peak memory 210860 kb
Host smart-f6672cea-5fce-4894-b8b8-4ad07d3c8033
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=435354017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res
et_error.435354017
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1808444141
Short name T720
Test name
Test status
Simulation time 202071407 ps
CPU time 11.33 seconds
Started May 07 12:45:19 PM PDT 24
Finished May 07 12:45:33 PM PDT 24
Peak memory 204896 kb
Host smart-93b5cf92-36c4-479c-8739-65184f86c364
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1808444141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1808444141
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1846013926
Short name T346
Test name
Test status
Simulation time 168123560 ps
CPU time 11.06 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:45:41 PM PDT 24
Peak memory 211692 kb
Host smart-08587088-069f-4e88-aa46-2953142e6b45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846013926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1846013926
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1039423730
Short name T144
Test name
Test status
Simulation time 43658608313 ps
CPU time 398.07 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:51:49 PM PDT 24
Peak memory 211656 kb
Host smart-e63a9974-fe76-46f4-bade-5d6645239c0c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1039423730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.1039423730
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.318719155
Short name T397
Test name
Test status
Simulation time 274088172 ps
CPU time 5.44 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203556 kb
Host smart-812c127b-c17a-4cdb-ba48-fafdc1ecd09f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=318719155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.318719155
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.1409613867
Short name T879
Test name
Test status
Simulation time 16793286 ps
CPU time 2.14 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:16 PM PDT 24
Peak memory 203516 kb
Host smart-4626c667-503c-431a-8ba6-707454234309
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1409613867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1409613867
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.184418822
Short name T246
Test name
Test status
Simulation time 561156738 ps
CPU time 19.35 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:48 PM PDT 24
Peak memory 204532 kb
Host smart-5fb88c08-028e-442c-8e7a-b3b5b026c0be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=184418822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.184418822
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.198782974
Short name T146
Test name
Test status
Simulation time 82941745133 ps
CPU time 211.43 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:48:50 PM PDT 24
Peak memory 204708 kb
Host smart-ae0fa207-aaa6-44cb-994e-18f1342e4f5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=198782974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.198782974
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1693177560
Short name T68
Test name
Test status
Simulation time 149029364492 ps
CPU time 314.02 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:50:23 PM PDT 24
Peak memory 205644 kb
Host smart-c0db8f1b-570d-401a-9ea9-489e69f72676
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1693177560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1693177560
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.252421228
Short name T722
Test name
Test status
Simulation time 391542306 ps
CPU time 9.08 seconds
Started May 07 12:45:03 PM PDT 24
Finished May 07 12:45:14 PM PDT 24
Peak memory 204640 kb
Host smart-441ce6d3-2982-487c-b8dc-af19cc975e3c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252421228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.252421228
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.3638992159
Short name T827
Test name
Test status
Simulation time 2329165271 ps
CPU time 23.43 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:41 PM PDT 24
Peak memory 204260 kb
Host smart-8e24d02f-b037-4e3c-8f45-50901bfe1c1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3638992159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3638992159
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.2173001904
Short name T36
Test name
Test status
Simulation time 202555515 ps
CPU time 3.34 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:13 PM PDT 24
Peak memory 203476 kb
Host smart-894d5aa5-2a00-4f2b-bbe8-94b78d2cfcac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2173001904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2173001904
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1645982121
Short name T833
Test name
Test status
Simulation time 15212447832 ps
CPU time 36.77 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:46 PM PDT 24
Peak memory 203576 kb
Host smart-503e8547-c4b4-41ce-afb2-cad28c742750
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645982121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1645982121
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2280878224
Short name T588
Test name
Test status
Simulation time 5319911650 ps
CPU time 33.28 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 203556 kb
Host smart-afc1c168-2410-48c3-a741-ae7cba81b0f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2280878224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2280878224
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1172235264
Short name T704
Test name
Test status
Simulation time 50258678 ps
CPU time 2.43 seconds
Started May 07 12:45:04 PM PDT 24
Finished May 07 12:45:07 PM PDT 24
Peak memory 203400 kb
Host smart-edcf81cd-1ee3-4d5a-a083-abd7b6582da4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172235264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1172235264
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1536647952
Short name T867
Test name
Test status
Simulation time 417468075 ps
CPU time 46.46 seconds
Started May 07 12:45:20 PM PDT 24
Finished May 07 12:46:09 PM PDT 24
Peak memory 205668 kb
Host smart-419edf98-afab-4718-9b26-bad398aab7d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1536647952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1536647952
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.440806285
Short name T27
Test name
Test status
Simulation time 4420096090 ps
CPU time 72.87 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 205540 kb
Host smart-f9c71daf-8ad4-4740-b24e-a2ccb689e68a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=440806285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.440806285
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3169734617
Short name T247
Test name
Test status
Simulation time 243507153 ps
CPU time 75.02 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:46:27 PM PDT 24
Peak memory 208444 kb
Host smart-6b55fb14-9803-4a7e-938f-8d5dcea755dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3169734617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.3169734617
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.612475776
Short name T789
Test name
Test status
Simulation time 9691752196 ps
CPU time 221.69 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:48:56 PM PDT 24
Peak memory 211004 kb
Host smart-fed71b80-f0f2-44df-a974-6194a727de96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=612475776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res
et_error.612475776
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3564232032
Short name T498
Test name
Test status
Simulation time 17462156 ps
CPU time 1.86 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203488 kb
Host smart-145776fc-10c7-46b5-8650-be93670c4e95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3564232032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3564232032
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2536169777
Short name T33
Test name
Test status
Simulation time 213019650 ps
CPU time 9.37 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 204040 kb
Host smart-268ddcaf-e759-411d-b24d-349818ef0815
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2536169777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2536169777
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3001357475
Short name T813
Test name
Test status
Simulation time 63574966886 ps
CPU time 439.09 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:52:33 PM PDT 24
Peak memory 207236 kb
Host smart-3b6fce04-9ee7-4d19-9803-dd27ab47ff59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3001357475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.3001357475
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2048653134
Short name T378
Test name
Test status
Simulation time 481050882 ps
CPU time 15.64 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:29 PM PDT 24
Peak memory 203892 kb
Host smart-a2999487-299a-4a71-90c4-020097dd1049
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2048653134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2048653134
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.12604770
Short name T479
Test name
Test status
Simulation time 757784520 ps
CPU time 14.31 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 203524 kb
Host smart-6dc8c629-d4aa-4937-9298-3fd3e6627b63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12604770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.12604770
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.2710367135
Short name T560
Test name
Test status
Simulation time 26581945 ps
CPU time 3.77 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:45:28 PM PDT 24
Peak memory 204148 kb
Host smart-8e156a33-fdb5-4679-8636-9b84f547978a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2710367135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2710367135
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1041455167
Short name T758
Test name
Test status
Simulation time 253050658493 ps
CPU time 341.47 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:50:54 PM PDT 24
Peak memory 205700 kb
Host smart-5a4d7924-749d-4386-ac7b-36ee65e9d66c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041455167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1041455167
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4070888415
Short name T267
Test name
Test status
Simulation time 114905764426 ps
CPU time 257.17 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:49:32 PM PDT 24
Peak memory 204852 kb
Host smart-c7d72946-7a58-4d88-9da9-adef36f3ad9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4070888415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4070888415
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.134240607
Short name T38
Test name
Test status
Simulation time 75789621 ps
CPU time 6.11 seconds
Started May 07 12:45:19 PM PDT 24
Finished May 07 12:45:28 PM PDT 24
Peak memory 211696 kb
Host smart-25fdfada-fb86-4459-a23d-2171459e311c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134240607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.134240607
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.82381604
Short name T408
Test name
Test status
Simulation time 899283227 ps
CPU time 19.37 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:35 PM PDT 24
Peak memory 203516 kb
Host smart-e941c443-0432-4240-98ca-2ec1b9e54286
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82381604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.82381604
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2690612948
Short name T673
Test name
Test status
Simulation time 358814375 ps
CPU time 3.99 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:15 PM PDT 24
Peak memory 203468 kb
Host smart-b6a4b79e-83bf-45b0-a321-757364c06493
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2690612948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2690612948
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2223243432
Short name T337
Test name
Test status
Simulation time 5510796964 ps
CPU time 27.56 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:43 PM PDT 24
Peak memory 203556 kb
Host smart-128a9291-495e-4c98-8b31-538a85fdda94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223243432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2223243432
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3940090240
Short name T533
Test name
Test status
Simulation time 13556975474 ps
CPU time 36.24 seconds
Started May 07 12:45:01 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203564 kb
Host smart-0c0ed710-f1de-4653-a457-beb92055cbb6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3940090240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3940090240
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1447798798
Short name T446
Test name
Test status
Simulation time 28005529 ps
CPU time 2.27 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:13 PM PDT 24
Peak memory 203504 kb
Host smart-36838884-3ca0-4483-a991-7f839028fc84
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447798798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1447798798
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2468956971
Short name T317
Test name
Test status
Simulation time 2087589341 ps
CPU time 102.39 seconds
Started May 07 12:45:18 PM PDT 24
Finished May 07 12:47:03 PM PDT 24
Peak memory 205460 kb
Host smart-b6044618-68b2-429d-a121-059bd6c391c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2468956971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2468956971
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3631377393
Short name T593
Test name
Test status
Simulation time 16955823 ps
CPU time 29.47 seconds
Started May 07 12:45:16 PM PDT 24
Finished May 07 12:45:49 PM PDT 24
Peak memory 207068 kb
Host smart-03a8aee4-82f6-4dab-a233-1ec950e80ba5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3631377393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.3631377393
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2307405479
Short name T41
Test name
Test status
Simulation time 2112301542 ps
CPU time 385.99 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:51:39 PM PDT 24
Peak memory 219796 kb
Host smart-6e753d0f-99f6-49bb-ab74-1a2bbe79d69f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2307405479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.2307405479
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2509053902
Short name T331
Test name
Test status
Simulation time 1442318793 ps
CPU time 19.21 seconds
Started May 07 12:45:20 PM PDT 24
Finished May 07 12:45:42 PM PDT 24
Peak memory 205184 kb
Host smart-ff895528-43d5-4b60-aa7c-f6f747a174ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2509053902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2509053902
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3963090539
Short name T444
Test name
Test status
Simulation time 3765405097 ps
CPU time 27.01 seconds
Started May 07 12:45:18 PM PDT 24
Finished May 07 12:45:48 PM PDT 24
Peak memory 203656 kb
Host smart-52e36b42-a88a-453a-a17f-0b7fbc5e3085
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3963090539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.3963090539
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.4067135208
Short name T261
Test name
Test status
Simulation time 16957034 ps
CPU time 1.79 seconds
Started May 07 12:45:37 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 203464 kb
Host smart-fcd51e03-c9a2-4d44-b9a5-393cdcb693e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4067135208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4067135208
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.3339936040
Short name T543
Test name
Test status
Simulation time 1407056189 ps
CPU time 22.24 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:56 PM PDT 24
Peak memory 203520 kb
Host smart-ccbda341-38c1-4b6c-ac71-f501943578a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3339936040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3339936040
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.2961422828
Short name T639
Test name
Test status
Simulation time 1017506262 ps
CPU time 25.8 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:41 PM PDT 24
Peak memory 211676 kb
Host smart-480ea128-b014-4eff-bd5d-b9ed41155ef6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2961422828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2961422828
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.4004694584
Short name T110
Test name
Test status
Simulation time 45752775628 ps
CPU time 204.82 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:48:56 PM PDT 24
Peak memory 205324 kb
Host smart-4024d1b5-b016-4ec2-9997-66945b725aaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004694584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4004694584
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.667655604
Short name T805
Test name
Test status
Simulation time 31178366427 ps
CPU time 121.32 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:47:29 PM PDT 24
Peak memory 204956 kb
Host smart-2e6601ee-f629-4d5f-baa4-070155c5d3aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=667655604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.667655604
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2244037893
Short name T411
Test name
Test status
Simulation time 151180102 ps
CPU time 21.15 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:30 PM PDT 24
Peak memory 204996 kb
Host smart-99a8ab08-4c56-48f3-a816-1abf3d2bbfb0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244037893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2244037893
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.468912853
Short name T412
Test name
Test status
Simulation time 3570249505 ps
CPU time 12.15 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 204072 kb
Host smart-5cb8936d-a12f-4a6a-a968-b4fd60428a16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=468912853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.468912853
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.3561785304
Short name T511
Test name
Test status
Simulation time 203801024 ps
CPU time 3.66 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203492 kb
Host smart-e11d4a35-c979-49ff-b9f6-973cfb7b8daa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3561785304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3561785304
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.702301689
Short name T715
Test name
Test status
Simulation time 11385963118 ps
CPU time 27.78 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:55 PM PDT 24
Peak memory 203544 kb
Host smart-5d31f39a-0cc8-4e1e-a69a-082971b9a69b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=702301689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.702301689
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1568228372
Short name T81
Test name
Test status
Simulation time 17804717432 ps
CPU time 38.17 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:45:51 PM PDT 24
Peak memory 203564 kb
Host smart-2974668b-f54b-4034-bc5c-86c7b2f3ba55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1568228372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1568228372
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.4140898226
Short name T642
Test name
Test status
Simulation time 44582210 ps
CPU time 2.09 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:18 PM PDT 24
Peak memory 203508 kb
Host smart-bd89d488-83b4-4d64-9505-00c8326090e1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140898226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.4140898226
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.826406697
Short name T443
Test name
Test status
Simulation time 34450650 ps
CPU time 2.28 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:45:27 PM PDT 24
Peak memory 203496 kb
Host smart-b5a91962-9b59-4f67-94f9-e0d30fc1f9c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=826406697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.826406697
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3584658993
Short name T555
Test name
Test status
Simulation time 2488747988 ps
CPU time 47.52 seconds
Started May 07 12:45:14 PM PDT 24
Finished May 07 12:46:04 PM PDT 24
Peak memory 205424 kb
Host smart-ea9d1f88-9fa5-4fd6-b383-24c79b60f6c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3584658993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3584658993
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2712627924
Short name T188
Test name
Test status
Simulation time 129239076 ps
CPU time 68.52 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:46:23 PM PDT 24
Peak memory 207920 kb
Host smart-93247404-6f7e-48cf-b895-473a168efbf0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2712627924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.2712627924
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2758679407
Short name T404
Test name
Test status
Simulation time 65854134 ps
CPU time 14.41 seconds
Started May 07 12:45:20 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 204928 kb
Host smart-f76d4e37-5a41-4ce5-9c6e-f7893b2d2752
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2758679407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.2758679407
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1231180875
Short name T714
Test name
Test status
Simulation time 582400419 ps
CPU time 14.47 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:43 PM PDT 24
Peak memory 205004 kb
Host smart-5fd84b23-d952-417d-b613-6cb7211c40b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1231180875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1231180875
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1227161019
Short name T415
Test name
Test status
Simulation time 1278020266 ps
CPU time 41.49 seconds
Started May 07 12:45:24 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 205836 kb
Host smart-be37ca6c-2565-47a7-995b-bf4bca4e7c8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1227161019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1227161019
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2597272378
Short name T870
Test name
Test status
Simulation time 73902699355 ps
CPU time 676.8 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:56:41 PM PDT 24
Peak memory 207412 kb
Host smart-d8d0dbf1-d0be-4454-a85d-3c867cea2546
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2597272378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.2597272378
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2952142130
Short name T307
Test name
Test status
Simulation time 185250284 ps
CPU time 3.42 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:31 PM PDT 24
Peak memory 203492 kb
Host smart-a2f6fd91-b9e5-4901-9b33-f7fece0b85c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2952142130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2952142130
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.385044228
Short name T356
Test name
Test status
Simulation time 737437257 ps
CPU time 23.93 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:52 PM PDT 24
Peak memory 203480 kb
Host smart-d6ed2056-28b6-49b3-8d76-1b6e378f00f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=385044228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.385044228
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.2365395375
Short name T155
Test name
Test status
Simulation time 503811115 ps
CPU time 22.81 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:43 PM PDT 24
Peak memory 204600 kb
Host smart-1ef2f6eb-802f-428d-96b3-d83547c56af1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2365395375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2365395375
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.3106002959
Short name T804
Test name
Test status
Simulation time 2081381053 ps
CPU time 9.98 seconds
Started May 07 12:45:24 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 203500 kb
Host smart-4e3fd4c5-0b63-4d18-9b39-550aa9ca0250
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106002959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3106002959
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3357341947
Short name T58
Test name
Test status
Simulation time 22388864107 ps
CPU time 88.87 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:46:41 PM PDT 24
Peak memory 205012 kb
Host smart-0761f99d-5aea-4bfe-8055-a5e06e9680e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3357341947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3357341947
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.384447576
Short name T454
Test name
Test status
Simulation time 420993437 ps
CPU time 21.89 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:56 PM PDT 24
Peak memory 204644 kb
Host smart-497f5c88-10ac-4f33-aaf7-ff818afcd537
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384447576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.384447576
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.3676668005
Short name T653
Test name
Test status
Simulation time 1071931247 ps
CPU time 20.38 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:51 PM PDT 24
Peak memory 203468 kb
Host smart-d0323946-9d26-4d48-bc40-c6c9fc6470c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3676668005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3676668005
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2071124427
Short name T532
Test name
Test status
Simulation time 36187266 ps
CPU time 2.31 seconds
Started May 07 12:45:21 PM PDT 24
Finished May 07 12:45:26 PM PDT 24
Peak memory 203412 kb
Host smart-23b62e03-bd85-4479-9cc7-abfe00b19d4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2071124427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2071124427
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2956879601
Short name T525
Test name
Test status
Simulation time 4285553128 ps
CPU time 25.6 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 203464 kb
Host smart-020ebe00-799c-4c0d-89e6-190578a90fd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956879601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2956879601
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.448617300
Short name T392
Test name
Test status
Simulation time 5633532867 ps
CPU time 30.21 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:46:04 PM PDT 24
Peak memory 203572 kb
Host smart-28cdb3b9-d4d1-42ef-a89a-b6f1ef0615ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=448617300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.448617300
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.956319929
Short name T75
Test name
Test status
Simulation time 41616832 ps
CPU time 2.24 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203476 kb
Host smart-6817e843-8407-437d-94fc-a454047686c8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956319929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.956319929
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3865409849
Short name T96
Test name
Test status
Simulation time 6906386424 ps
CPU time 163.97 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:48:17 PM PDT 24
Peak memory 209176 kb
Host smart-69c03bf9-3206-46d6-9a31-3bd101cd4948
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3865409849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3865409849
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2618179580
Short name T434
Test name
Test status
Simulation time 674980225 ps
CPU time 73.52 seconds
Started May 07 12:45:34 PM PDT 24
Finished May 07 12:46:50 PM PDT 24
Peak memory 207252 kb
Host smart-6f42e219-1553-40b7-980f-41ea5d36f56a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2618179580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2618179580
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.654066416
Short name T285
Test name
Test status
Simulation time 3040224844 ps
CPU time 334.29 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:51:03 PM PDT 24
Peak memory 208464 kb
Host smart-a987ecc5-44f2-41b7-a149-49aaf1228a8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=654066416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand
_reset.654066416
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1513851570
Short name T864
Test name
Test status
Simulation time 848379565 ps
CPU time 58.28 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:46:32 PM PDT 24
Peak memory 207320 kb
Host smart-73d652eb-32ac-4747-9ea9-ca4af421478b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513851570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.1513851570
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.551071232
Short name T891
Test name
Test status
Simulation time 74662039 ps
CPU time 12.96 seconds
Started May 07 12:45:16 PM PDT 24
Finished May 07 12:45:32 PM PDT 24
Peak memory 204884 kb
Host smart-d60d4ddf-e259-4762-bfcf-cac7db67592b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=551071232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.551071232
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.708462846
Short name T328
Test name
Test status
Simulation time 1405533701 ps
CPU time 50.02 seconds
Started May 07 12:45:03 PM PDT 24
Finished May 07 12:45:54 PM PDT 24
Peak memory 211672 kb
Host smart-625bbab9-6b6f-49ff-a440-082293904e00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=708462846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.708462846
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3628617769
Short name T579
Test name
Test status
Simulation time 57464889598 ps
CPU time 396.28 seconds
Started May 07 12:44:38 PM PDT 24
Finished May 07 12:51:16 PM PDT 24
Peak memory 206052 kb
Host smart-5a2de423-1acb-48d7-b174-c91b0aee3eb3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3628617769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.3628617769
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.143023171
Short name T341
Test name
Test status
Simulation time 70552595 ps
CPU time 6.48 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:44:58 PM PDT 24
Peak memory 203620 kb
Host smart-0a5438c2-b9d1-4073-bd65-d40d052df2f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=143023171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.143023171
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.2403245809
Short name T200
Test name
Test status
Simulation time 324823426 ps
CPU time 25.19 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:45:01 PM PDT 24
Peak memory 203912 kb
Host smart-13b5672d-88e8-48f5-afff-e06a10850baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2403245809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2403245809
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.4235458986
Short name T428
Test name
Test status
Simulation time 102724880 ps
CPU time 13.19 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:48 PM PDT 24
Peak memory 211676 kb
Host smart-7aff21a6-34d4-416f-8d90-04ddc79dab42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4235458986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.4235458986
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3186266282
Short name T395
Test name
Test status
Simulation time 65166357579 ps
CPU time 162.52 seconds
Started May 07 12:44:42 PM PDT 24
Finished May 07 12:47:25 PM PDT 24
Peak memory 204832 kb
Host smart-a2451ac3-0e66-431a-84b3-1a03ee7e0346
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186266282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3186266282
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.879080984
Short name T102
Test name
Test status
Simulation time 23321756579 ps
CPU time 75.87 seconds
Started May 07 12:44:44 PM PDT 24
Finished May 07 12:46:01 PM PDT 24
Peak memory 204864 kb
Host smart-e5c34c1b-5935-44df-b087-3f5f122a810b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=879080984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.879080984
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.639022529
Short name T733
Test name
Test status
Simulation time 226744979 ps
CPU time 24.64 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:45:13 PM PDT 24
Peak memory 205040 kb
Host smart-d6738ed5-b7d6-43f1-9496-4ca90c71d77c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639022529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.639022529
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.2861194855
Short name T783
Test name
Test status
Simulation time 715184428 ps
CPU time 5.47 seconds
Started May 07 12:44:40 PM PDT 24
Finished May 07 12:44:47 PM PDT 24
Peak memory 203500 kb
Host smart-05b40919-41d2-45a1-8b94-42e2a0eaa820
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2861194855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2861194855
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.270551320
Short name T236
Test name
Test status
Simulation time 461958201 ps
CPU time 3.9 seconds
Started May 07 12:44:42 PM PDT 24
Finished May 07 12:44:47 PM PDT 24
Peak memory 203468 kb
Host smart-1d5eb17e-6426-4785-863e-e19e4b2add1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=270551320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.270551320
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.531695559
Short name T425
Test name
Test status
Simulation time 14681208332 ps
CPU time 35.53 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:47 PM PDT 24
Peak memory 203588 kb
Host smart-e85feaaf-b951-4c73-9958-021ba4911499
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=531695559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.531695559
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1018946186
Short name T56
Test name
Test status
Simulation time 24901700979 ps
CPU time 52.51 seconds
Started May 07 12:44:45 PM PDT 24
Finished May 07 12:45:39 PM PDT 24
Peak memory 203276 kb
Host smart-bbf1f29c-44e5-4781-85ca-2415b57c279c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1018946186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1018946186
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.490850000
Short name T772
Test name
Test status
Simulation time 38092852 ps
CPU time 2.22 seconds
Started May 07 12:44:38 PM PDT 24
Finished May 07 12:44:42 PM PDT 24
Peak memory 203672 kb
Host smart-540fb1e4-ddaa-4205-aa28-82ee11478e78
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490850000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.490850000
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1529806877
Short name T630
Test name
Test status
Simulation time 24440136562 ps
CPU time 260.27 seconds
Started May 07 12:45:01 PM PDT 24
Finished May 07 12:49:23 PM PDT 24
Peak memory 207416 kb
Host smart-26f39f51-08bd-4782-a041-679614c173fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1529806877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1529806877
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3172864700
Short name T786
Test name
Test status
Simulation time 7958552559 ps
CPU time 224.96 seconds
Started May 07 12:44:38 PM PDT 24
Finished May 07 12:48:25 PM PDT 24
Peak memory 210064 kb
Host smart-823d0a59-1c26-4320-b519-8d706884a4c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3172864700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3172864700
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1681872492
Short name T22
Test name
Test status
Simulation time 4578644732 ps
CPU time 317.59 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:49:54 PM PDT 24
Peak memory 211676 kb
Host smart-021256a2-0859-4afb-92f4-ce1a655eead6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1681872492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.1681872492
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.715040766
Short name T501
Test name
Test status
Simulation time 9470891552 ps
CPU time 126.23 seconds
Started May 07 12:44:49 PM PDT 24
Finished May 07 12:46:56 PM PDT 24
Peak memory 209988 kb
Host smart-a5931802-6823-4f94-9937-da586c956a96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=715040766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese
t_error.715040766
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3138092649
Short name T176
Test name
Test status
Simulation time 119399610 ps
CPU time 13.49 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 211668 kb
Host smart-7cc61a0e-67cf-4d26-8c33-9a5601fae74d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3138092649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3138092649
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3579160232
Short name T421
Test name
Test status
Simulation time 190843580 ps
CPU time 16.83 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:27 PM PDT 24
Peak memory 205788 kb
Host smart-108a5d93-46fb-498d-91ba-7708015eb215
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3579160232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3579160232
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2662663820
Short name T59
Test name
Test status
Simulation time 74938528835 ps
CPU time 424.82 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:52:22 PM PDT 24
Peak memory 207172 kb
Host smart-b9da02af-776d-4e05-b2bb-3f0b2b596331
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2662663820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.2662663820
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.4135437092
Short name T667
Test name
Test status
Simulation time 302312482 ps
CPU time 9.88 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 203888 kb
Host smart-47c00a39-92d2-489e-bc1b-ef7ee966bd4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4135437092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.4135437092
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.672154467
Short name T591
Test name
Test status
Simulation time 642480776 ps
CPU time 15.52 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:27 PM PDT 24
Peak memory 203504 kb
Host smart-7d569de5-ba47-42b4-bf0c-92c30867092b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=672154467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.672154467
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.439463775
Short name T318
Test name
Test status
Simulation time 80032184 ps
CPU time 5.36 seconds
Started May 07 12:45:19 PM PDT 24
Finished May 07 12:45:27 PM PDT 24
Peak memory 204548 kb
Host smart-01d30dc1-574c-4981-96db-79e53aa5e8d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=439463775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.439463775
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.4123722918
Short name T70
Test name
Test status
Simulation time 42239241885 ps
CPU time 230.13 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:49:01 PM PDT 24
Peak memory 211660 kb
Host smart-a91a57bb-3756-49f6-a16a-81aca69494c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123722918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4123722918
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3433409229
Short name T840
Test name
Test status
Simulation time 32545013224 ps
CPU time 114.93 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:47:28 PM PDT 24
Peak memory 204768 kb
Host smart-a7e82557-38c1-455f-b35a-55767d3c0295
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3433409229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3433409229
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3220246134
Short name T466
Test name
Test status
Simulation time 49508787 ps
CPU time 6.47 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 204620 kb
Host smart-44d72c50-c874-4bfb-8102-2bade4d8bf8c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220246134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3220246134
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.1383103633
Short name T237
Test name
Test status
Simulation time 404417159 ps
CPU time 7.74 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:45:32 PM PDT 24
Peak memory 203940 kb
Host smart-ba3abef1-a45a-4a14-a677-9b963aba6727
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1383103633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1383103633
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.663201671
Short name T710
Test name
Test status
Simulation time 138266500 ps
CPU time 3.56 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:45:18 PM PDT 24
Peak memory 203476 kb
Host smart-503ca847-b75e-44ec-b729-0ac96c3bbb5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=663201671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.663201671
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1913604266
Short name T76
Test name
Test status
Simulation time 4540703788 ps
CPU time 27.38 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:45:57 PM PDT 24
Peak memory 203564 kb
Host smart-0619f1f3-1c1e-4943-be1d-0d0f448c22d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913604266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1913604266
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3593989966
Short name T852
Test name
Test status
Simulation time 6181599640 ps
CPU time 37.98 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 203536 kb
Host smart-eed36557-7b32-41b6-9abb-4ab588e1149d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3593989966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3593989966
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2074637841
Short name T327
Test name
Test status
Simulation time 23789802 ps
CPU time 2.31 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:13 PM PDT 24
Peak memory 203488 kb
Host smart-d519e949-367b-43da-8749-6733341e14e6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074637841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2074637841
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3889911194
Short name T244
Test name
Test status
Simulation time 1877245103 ps
CPU time 22.93 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:54 PM PDT 24
Peak memory 205200 kb
Host smart-51d328ee-8763-48c5-9259-5a7692bfd665
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3889911194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3889911194
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3013372829
Short name T42
Test name
Test status
Simulation time 9046027825 ps
CPU time 205.74 seconds
Started May 07 12:45:14 PM PDT 24
Finished May 07 12:48:43 PM PDT 24
Peak memory 207044 kb
Host smart-dfe2b35f-4953-44da-ac27-ed6ee8673485
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3013372829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3013372829
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1807661824
Short name T608
Test name
Test status
Simulation time 33090788 ps
CPU time 20.5 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:54 PM PDT 24
Peak memory 205584 kb
Host smart-2f8f096c-425a-4599-9522-59d6af3d1cae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1807661824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.1807661824
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3087657323
Short name T780
Test name
Test status
Simulation time 479982352 ps
CPU time 13.18 seconds
Started May 07 12:45:08 PM PDT 24
Finished May 07 12:45:24 PM PDT 24
Peak memory 204952 kb
Host smart-7cffc356-36d5-4322-9871-1e5fe551a33c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3087657323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3087657323
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3999721164
Short name T545
Test name
Test status
Simulation time 2833167302 ps
CPU time 48.78 seconds
Started May 07 12:45:17 PM PDT 24
Finished May 07 12:46:09 PM PDT 24
Peak memory 206496 kb
Host smart-8bd1be7e-fa84-4f85-b9e3-c44c1f3179bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3999721164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3999721164
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2313414334
Short name T646
Test name
Test status
Simulation time 35173021757 ps
CPU time 226.44 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:49:16 PM PDT 24
Peak memory 211752 kb
Host smart-47e521fd-2330-4232-98b3-a85e2eb3d1c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2313414334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.2313414334
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2121152482
Short name T123
Test name
Test status
Simulation time 683639029 ps
CPU time 19.12 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:53 PM PDT 24
Peak memory 203684 kb
Host smart-56f1e782-b28f-41ab-97e9-7a0cd1abf1eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2121152482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2121152482
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3516988796
Short name T440
Test name
Test status
Simulation time 2486426727 ps
CPU time 16.33 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:45:53 PM PDT 24
Peak memory 203476 kb
Host smart-41640d9b-81e0-4f9e-a336-3af9a739df15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3516988796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3516988796
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.472895468
Short name T800
Test name
Test status
Simulation time 797539715 ps
CPU time 27.38 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 204972 kb
Host smart-b7b7f549-273e-4323-a73b-2d11b4bf8794
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=472895468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.472895468
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2549577541
Short name T217
Test name
Test status
Simulation time 107098841118 ps
CPU time 293.22 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:50:18 PM PDT 24
Peak memory 205408 kb
Host smart-76628275-5d6b-4c28-8ef8-da8dcb6d2a71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549577541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2549577541
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2901369363
Short name T208
Test name
Test status
Simulation time 213405175802 ps
CPU time 381.99 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:52:06 PM PDT 24
Peak memory 205544 kb
Host smart-6b277f8b-6c06-42b1-ac91-c41b48d0450a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2901369363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2901369363
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.428952766
Short name T711
Test name
Test status
Simulation time 80876926 ps
CPU time 7.25 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:42 PM PDT 24
Peak memory 204632 kb
Host smart-dcc8deba-809e-4e6e-ac8f-040a33630ae7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428952766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.428952766
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.717561058
Short name T34
Test name
Test status
Simulation time 796307372 ps
CPU time 17.96 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:51 PM PDT 24
Peak memory 203528 kb
Host smart-ad232e98-14c9-4a8f-b8a2-c4e09f8eb6bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=717561058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.717561058
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.2995780370
Short name T394
Test name
Test status
Simulation time 678897521 ps
CPU time 4.18 seconds
Started May 07 12:45:33 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 203472 kb
Host smart-6b824b95-2e81-4753-9114-34227e663759
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2995780370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2995780370
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2676407825
Short name T344
Test name
Test status
Simulation time 6464941877 ps
CPU time 30.01 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203556 kb
Host smart-de127b9f-7d5e-4933-b87f-a17c2c10d11a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676407825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2676407825
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2730531846
Short name T643
Test name
Test status
Simulation time 3460262241 ps
CPU time 31.78 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203548 kb
Host smart-643239d7-bc5c-4615-b6c5-ecc3c5326c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2730531846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2730531846
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3021267416
Short name T857
Test name
Test status
Simulation time 29198466 ps
CPU time 2.34 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:45:28 PM PDT 24
Peak memory 203492 kb
Host smart-65851678-29e6-4793-bbab-a30d494fab47
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021267416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3021267416
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1327542679
Short name T798
Test name
Test status
Simulation time 3937163577 ps
CPU time 290.28 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:50:20 PM PDT 24
Peak memory 207244 kb
Host smart-0dc5bd5b-8ce2-4976-8aba-fea9531fbd6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1327542679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1327542679
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1926151412
Short name T74
Test name
Test status
Simulation time 1484254131 ps
CPU time 85.94 seconds
Started May 07 12:45:31 PM PDT 24
Finished May 07 12:47:01 PM PDT 24
Peak memory 208780 kb
Host smart-a677d1ed-5d1a-4288-91f7-09ab47583905
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1926151412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1926151412
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3151262822
Short name T697
Test name
Test status
Simulation time 189444069 ps
CPU time 50.03 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:46:27 PM PDT 24
Peak memory 206872 kb
Host smart-0611986d-ab86-4fdf-aa95-ad68a1396a73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3151262822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.3151262822
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.4035251863
Short name T280
Test name
Test status
Simulation time 13531799573 ps
CPU time 308.53 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:50:39 PM PDT 24
Peak memory 211692 kb
Host smart-9c2f9c41-df4c-435d-97bc-fc6b200b7ef1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4035251863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.4035251863
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3449816529
Short name T766
Test name
Test status
Simulation time 157339952 ps
CPU time 6.82 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:41 PM PDT 24
Peak memory 211652 kb
Host smart-58b8ced2-e1b0-4ac5-be02-c1f9f96d7e7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3449816529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3449816529
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3620995972
Short name T587
Test name
Test status
Simulation time 305760389 ps
CPU time 28.33 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:59 PM PDT 24
Peak memory 204996 kb
Host smart-287db4ec-9456-4ab8-8a09-72ab68918051
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3620995972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3620995972
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1593106643
Short name T181
Test name
Test status
Simulation time 70525004610 ps
CPU time 581.55 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:55:18 PM PDT 24
Peak memory 207216 kb
Host smart-9195cebe-8555-4201-aa8e-f6a9ccf45b34
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1593106643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.1593106643
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.689349086
Short name T101
Test name
Test status
Simulation time 111918826 ps
CPU time 13.07 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:31 PM PDT 24
Peak memory 203500 kb
Host smart-d11e8965-0c0d-4dad-923b-9599b43e9760
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=689349086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.689349086
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.2891518442
Short name T677
Test name
Test status
Simulation time 386234398 ps
CPU time 7.65 seconds
Started May 07 12:45:34 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 203504 kb
Host smart-f6c0a4b2-4d91-48cc-9a15-4890c375e6b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2891518442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2891518442
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.4124566852
Short name T376
Test name
Test status
Simulation time 313938598 ps
CPU time 5.11 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:39 PM PDT 24
Peak memory 203868 kb
Host smart-7ae0af98-3a2f-408c-9621-c47c73198f93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4124566852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.4124566852
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2227858589
Short name T452
Test name
Test status
Simulation time 91058890284 ps
CPU time 247.92 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:49:36 PM PDT 24
Peak memory 205324 kb
Host smart-89bf05c8-9329-449d-907e-10110add8cb9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227858589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2227858589
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1929883383
Short name T621
Test name
Test status
Simulation time 24993561123 ps
CPU time 148.71 seconds
Started May 07 12:45:20 PM PDT 24
Finished May 07 12:47:51 PM PDT 24
Peak memory 211652 kb
Host smart-4df13bb1-c5d8-424a-bd97-bad3b51f255b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1929883383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1929883383
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.118155128
Short name T844
Test name
Test status
Simulation time 495193208 ps
CPU time 15.13 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:46 PM PDT 24
Peak memory 204264 kb
Host smart-44f11000-bb45-478d-b068-641be0327123
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=118155128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.118155128
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.361746377
Short name T482
Test name
Test status
Simulation time 36488079 ps
CPU time 2.46 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:45:35 PM PDT 24
Peak memory 203468 kb
Host smart-db119463-fc97-4041-8af3-0beac16ce321
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=361746377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.361746377
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3304648506
Short name T140
Test name
Test status
Simulation time 22320538577 ps
CPU time 42.46 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:46:20 PM PDT 24
Peak memory 203504 kb
Host smart-8ef876dc-e030-4a81-ae66-5f3d7d3441da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304648506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3304648506
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2177703175
Short name T654
Test name
Test status
Simulation time 10619980337 ps
CPU time 34.41 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203536 kb
Host smart-cd4f1fa6-7d74-4796-bb39-4b0df6a423da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2177703175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2177703175
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1863080608
Short name T884
Test name
Test status
Simulation time 38732169 ps
CPU time 2.4 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:33 PM PDT 24
Peak memory 203516 kb
Host smart-cb08b09a-8a99-424c-85ca-5b1d0e442792
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863080608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1863080608
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3585196415
Short name T125
Test name
Test status
Simulation time 32003545604 ps
CPU time 222.87 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:49:14 PM PDT 24
Peak memory 207300 kb
Host smart-5bea9326-1333-4934-abfd-c90ce6f75db9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585196415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3585196415
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3419468206
Short name T606
Test name
Test status
Simulation time 5222341042 ps
CPU time 189.07 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:48:43 PM PDT 24
Peak memory 209480 kb
Host smart-8445ead8-e646-43cd-8915-2dad613cfe74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3419468206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3419468206
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.4141498047
Short name T113
Test name
Test status
Simulation time 4800799059 ps
CPU time 155.79 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:48:05 PM PDT 24
Peak memory 208816 kb
Host smart-a2a91b7b-37c5-4c4a-9789-9a669cb1cb92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4141498047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.4141498047
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1863618159
Short name T887
Test name
Test status
Simulation time 765328102 ps
CPU time 118.75 seconds
Started May 07 12:45:24 PM PDT 24
Finished May 07 12:47:25 PM PDT 24
Peak memory 210004 kb
Host smart-f272f199-78fa-4d9e-831d-217ab45a0770
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1863618159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.1863618159
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1656209050
Short name T725
Test name
Test status
Simulation time 365045720 ps
CPU time 21.01 seconds
Started May 07 12:45:32 PM PDT 24
Finished May 07 12:45:57 PM PDT 24
Peak memory 211676 kb
Host smart-64c1f729-6458-42f0-9707-e93a0e877da6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1656209050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1656209050
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1789381674
Short name T581
Test name
Test status
Simulation time 1518106681 ps
CPU time 37.04 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:46:06 PM PDT 24
Peak memory 204532 kb
Host smart-e288e8f1-47a9-4336-ad0d-737a5ede0b2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1789381674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1789381674
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.450814700
Short name T757
Test name
Test status
Simulation time 151502504949 ps
CPU time 583.28 seconds
Started May 07 12:45:24 PM PDT 24
Finished May 07 12:55:09 PM PDT 24
Peak memory 207328 kb
Host smart-a30adf77-a8d1-4035-95f3-76bb9c64dd74
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=450814700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo
w_rsp.450814700
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3197760856
Short name T626
Test name
Test status
Simulation time 512970789 ps
CPU time 11.61 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:45:49 PM PDT 24
Peak memory 203928 kb
Host smart-78f445b4-945c-45ae-b25f-0510fb689a63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3197760856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3197760856
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.3451298778
Short name T450
Test name
Test status
Simulation time 162077905 ps
CPU time 15.84 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:51 PM PDT 24
Peak memory 203600 kb
Host smart-12f54773-c9ca-468a-b5d7-60f2ed34b4ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3451298778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3451298778
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.1067488047
Short name T379
Test name
Test status
Simulation time 4192613840 ps
CPU time 37.15 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 205004 kb
Host smart-abcd0c8b-3cd5-462d-9171-359291d5c1cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1067488047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1067488047
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1930294358
Short name T390
Test name
Test status
Simulation time 38018109675 ps
CPU time 219.89 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:49:12 PM PDT 24
Peak memory 211756 kb
Host smart-5aae4879-f690-4146-b03b-429a4938acf0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930294358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1930294358
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2001550570
Short name T134
Test name
Test status
Simulation time 80513054138 ps
CPU time 268.28 seconds
Started May 07 12:45:39 PM PDT 24
Finished May 07 12:50:08 PM PDT 24
Peak memory 205604 kb
Host smart-8ab56510-56b9-4dd0-be5f-3fb3bd64b063
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2001550570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2001550570
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3696751414
Short name T675
Test name
Test status
Simulation time 79963530 ps
CPU time 12.01 seconds
Started May 07 12:45:31 PM PDT 24
Finished May 07 12:45:47 PM PDT 24
Peak memory 211720 kb
Host smart-78eb8e87-8786-47a8-8cc7-6f822660d68f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696751414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3696751414
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.3003679701
Short name T748
Test name
Test status
Simulation time 206013218 ps
CPU time 5.63 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 203568 kb
Host smart-7adaa75b-dba8-4ab2-ae74-2a10de40b4c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3003679701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3003679701
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.982754302
Short name T152
Test name
Test status
Simulation time 216033801 ps
CPU time 3.49 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:45:36 PM PDT 24
Peak memory 203388 kb
Host smart-e270aa76-f576-4588-85b5-4eacfe1f4f59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=982754302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.982754302
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2228642266
Short name T52
Test name
Test status
Simulation time 12428529658 ps
CPU time 27.85 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203460 kb
Host smart-586f3f22-37ee-42b8-8091-ecc6190c0de6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228642266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2228642266
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3110261717
Short name T493
Test name
Test status
Simulation time 4907177924 ps
CPU time 28.21 seconds
Started May 07 12:45:44 PM PDT 24
Finished May 07 12:46:13 PM PDT 24
Peak memory 203504 kb
Host smart-664df97b-b908-44a6-9346-038051de3313
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3110261717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3110261717
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1627589809
Short name T718
Test name
Test status
Simulation time 23250160 ps
CPU time 2.34 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 203676 kb
Host smart-b58e4e40-5100-4a2d-b84d-a5c8ba6471df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627589809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1627589809
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2873953094
Short name T740
Test name
Test status
Simulation time 4522551423 ps
CPU time 87.31 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:47:00 PM PDT 24
Peak memory 208272 kb
Host smart-01630882-74bb-4474-83ab-43883183652e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2873953094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2873953094
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3504932056
Short name T522
Test name
Test status
Simulation time 15769734784 ps
CPU time 190.88 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:48:41 PM PDT 24
Peak memory 209424 kb
Host smart-54420e2e-a811-4710-a063-019e6c987017
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3504932056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3504932056
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3631903551
Short name T809
Test name
Test status
Simulation time 333231317 ps
CPU time 146.26 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:47:55 PM PDT 24
Peak memory 208560 kb
Host smart-cc7afab2-4f60-4044-8ae6-cae5ac6bf76e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3631903551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.3631903551
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1126944998
Short name T282
Test name
Test status
Simulation time 425585628 ps
CPU time 129.13 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:47:34 PM PDT 24
Peak memory 211052 kb
Host smart-8feb99b8-028c-4116-8623-58fcd1d002a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1126944998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.1126944998
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1725806884
Short name T456
Test name
Test status
Simulation time 3478599323 ps
CPU time 30.21 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 205340 kb
Host smart-d2f2a43b-22f3-40af-9a47-76b761a15b79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1725806884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1725806884
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2601296426
Short name T834
Test name
Test status
Simulation time 18513212 ps
CPU time 2.86 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 203504 kb
Host smart-e34bc1e0-5025-4669-952a-39661f34cde9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2601296426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2601296426
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3124737711
Short name T150
Test name
Test status
Simulation time 109671024203 ps
CPU time 371.32 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:51:43 PM PDT 24
Peak memory 206964 kb
Host smart-80e01251-a502-43f9-9fbf-3279720d0f86
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3124737711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.3124737711
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.153323080
Short name T732
Test name
Test status
Simulation time 564331112 ps
CPU time 13.22 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203500 kb
Host smart-ec97b905-8ca5-4bbe-b213-d2b99a5f861f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=153323080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.153323080
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1209314398
Short name T872
Test name
Test status
Simulation time 188859337 ps
CPU time 7.6 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:45:32 PM PDT 24
Peak memory 203516 kb
Host smart-c5bb80a8-e560-457a-a114-22867123d039
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1209314398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1209314398
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.3201203094
Short name T558
Test name
Test status
Simulation time 24246238 ps
CPU time 2.13 seconds
Started May 07 12:45:40 PM PDT 24
Finished May 07 12:45:43 PM PDT 24
Peak memory 203480 kb
Host smart-9ec32ba5-2251-4c98-b0e1-d06f86241580
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3201203094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3201203094
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3078508903
Short name T717
Test name
Test status
Simulation time 21607135538 ps
CPU time 99.03 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:47:14 PM PDT 24
Peak memory 211668 kb
Host smart-ed894244-10ba-4fbc-9063-d5ce645788f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078508903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3078508903
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.318646570
Short name T183
Test name
Test status
Simulation time 53273841831 ps
CPU time 95.15 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:46:59 PM PDT 24
Peak memory 204856 kb
Host smart-67f8f053-43b6-4b17-a0ca-1ed051f5896d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=318646570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.318646570
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2619242530
Short name T330
Test name
Test status
Simulation time 43797601 ps
CPU time 5.96 seconds
Started May 07 12:45:41 PM PDT 24
Finished May 07 12:45:48 PM PDT 24
Peak memory 204596 kb
Host smart-e654953e-5e81-4a8c-9d88-08217dd5c323
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619242530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2619242530
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.1811868015
Short name T230
Test name
Test status
Simulation time 250726297 ps
CPU time 19.73 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:45:49 PM PDT 24
Peak memory 204536 kb
Host smart-135d5562-0be8-4245-9d8e-885af561471f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1811868015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1811868015
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.184224261
Short name T262
Test name
Test status
Simulation time 384475356 ps
CPU time 3.51 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203288 kb
Host smart-7f635424-853c-404c-8742-f0f8914c2718
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=184224261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.184224261
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1174761595
Short name T716
Test name
Test status
Simulation time 9143666118 ps
CPU time 34.9 seconds
Started May 07 12:45:33 PM PDT 24
Finished May 07 12:46:11 PM PDT 24
Peak memory 203560 kb
Host smart-e691ffde-1ebc-44ce-b6dc-f2dc979c557f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174761595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1174761595
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2095387864
Short name T178
Test name
Test status
Simulation time 5389042988 ps
CPU time 35.03 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:51 PM PDT 24
Peak memory 203536 kb
Host smart-61fef323-b4ea-414a-b7ad-3efb9a46f9f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2095387864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2095387864
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1257198289
Short name T841
Test name
Test status
Simulation time 46051631 ps
CPU time 1.82 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:35 PM PDT 24
Peak memory 203504 kb
Host smart-a6bd99c1-5451-4587-9712-859ed2e9b445
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257198289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1257198289
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.188439767
Short name T723
Test name
Test status
Simulation time 1286425065 ps
CPU time 130.1 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:47:43 PM PDT 24
Peak memory 207076 kb
Host smart-0c07873c-bda8-4f52-b047-8836a9cef954
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=188439767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.188439767
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2309702322
Short name T724
Test name
Test status
Simulation time 1622990848 ps
CPU time 80.77 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:46:54 PM PDT 24
Peak memory 206216 kb
Host smart-1799053f-0567-4335-b39d-30680b683055
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2309702322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2309702322
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2523330714
Short name T91
Test name
Test status
Simulation time 256625096 ps
CPU time 84.46 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:46:54 PM PDT 24
Peak memory 207944 kb
Host smart-d296edab-88ab-43e1-8747-e2b1faa3e246
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2523330714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.2523330714
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3514399735
Short name T29
Test name
Test status
Simulation time 22349561 ps
CPU time 19.66 seconds
Started May 07 12:45:33 PM PDT 24
Finished May 07 12:45:56 PM PDT 24
Peak memory 204932 kb
Host smart-58193576-4753-44b1-8da3-d771b90bbf58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3514399735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.3514399735
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.994314943
Short name T410
Test name
Test status
Simulation time 3884550086 ps
CPU time 29.87 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:46:00 PM PDT 24
Peak memory 204828 kb
Host smart-38f78e07-3db8-4229-9dd6-39feca2bab4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=994314943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.994314943
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.965871601
Short name T177
Test name
Test status
Simulation time 410042006 ps
CPU time 13.68 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:45 PM PDT 24
Peak memory 205388 kb
Host smart-15970e19-d76b-4f93-b284-1ab844136f1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=965871601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.965871601
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3761406773
Short name T103
Test name
Test status
Simulation time 14651216688 ps
CPU time 63.32 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 204652 kb
Host smart-bc8c2488-8861-43d2-ac24-829196abae04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3761406773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.3761406773
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3292292248
Short name T549
Test name
Test status
Simulation time 108234901 ps
CPU time 4.81 seconds
Started May 07 12:45:47 PM PDT 24
Finished May 07 12:45:52 PM PDT 24
Peak memory 203584 kb
Host smart-73c212f7-39ef-4efb-80fc-9ce0623248eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3292292248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3292292248
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.1904307603
Short name T794
Test name
Test status
Simulation time 163693130 ps
CPU time 21.46 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:54 PM PDT 24
Peak memory 203728 kb
Host smart-11e3087a-c22f-4372-8f3e-3c594a62ec76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1904307603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1904307603
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.959642906
Short name T815
Test name
Test status
Simulation time 108536193 ps
CPU time 11.71 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:45 PM PDT 24
Peak memory 211652 kb
Host smart-9720c5dd-28be-4476-bd2d-e17ed3c99766
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=959642906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.959642906
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2209531553
Short name T668
Test name
Test status
Simulation time 125794397590 ps
CPU time 234.84 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:49:24 PM PDT 24
Peak memory 204912 kb
Host smart-fced56a7-a8cc-4430-b698-431283a94f05
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209531553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2209531553
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1275947439
Short name T139
Test name
Test status
Simulation time 73816404365 ps
CPU time 222.14 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:49:15 PM PDT 24
Peak memory 204640 kb
Host smart-eb539d6b-4c5d-49c4-a1f3-4045f3512eb2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1275947439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1275947439
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2428760136
Short name T583
Test name
Test status
Simulation time 562958971 ps
CPU time 23.52 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:57 PM PDT 24
Peak memory 204924 kb
Host smart-8952c358-63dd-42b0-aa1e-16631b6364e6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428760136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2428760136
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.3152981980
Short name T824
Test name
Test status
Simulation time 5508811667 ps
CPU time 22.6 seconds
Started May 07 12:45:38 PM PDT 24
Finished May 07 12:46:02 PM PDT 24
Peak memory 211728 kb
Host smart-230969db-e9bb-4c18-aedc-3a070113b34e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3152981980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3152981980
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.883104922
Short name T416
Test name
Test status
Simulation time 261808563 ps
CPU time 4.1 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203484 kb
Host smart-ec02cf95-36b0-4e66-bd49-ffcdc61aebe0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=883104922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.883104922
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2060009453
Short name T625
Test name
Test status
Simulation time 31378596792 ps
CPU time 53.72 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:46:22 PM PDT 24
Peak memory 204080 kb
Host smart-2e8ae41c-62ca-4071-80d2-2938e02165f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060009453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2060009453
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1819821725
Short name T220
Test name
Test status
Simulation time 5873395186 ps
CPU time 34.14 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203564 kb
Host smart-2851dc23-2253-40d9-b5db-352dc978578c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1819821725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1819821725
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1058748683
Short name T239
Test name
Test status
Simulation time 38994153 ps
CPU time 2.08 seconds
Started May 07 12:45:22 PM PDT 24
Finished May 07 12:45:26 PM PDT 24
Peak memory 203508 kb
Host smart-78d8a36e-7651-487b-986a-1742bf6485f1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058748683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1058748683
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.4111257248
Short name T888
Test name
Test status
Simulation time 7107178937 ps
CPU time 174.1 seconds
Started May 07 12:45:36 PM PDT 24
Finished May 07 12:48:32 PM PDT 24
Peak memory 209216 kb
Host smart-0a951a02-c79a-48f9-a3c2-411dd4e6b697
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111257248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.4111257248
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2814210833
Short name T745
Test name
Test status
Simulation time 176148644 ps
CPU time 16.51 seconds
Started May 07 12:45:33 PM PDT 24
Finished May 07 12:45:53 PM PDT 24
Peak memory 211676 kb
Host smart-59944f00-623d-4641-a2ff-bbbb5c7f3f52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2814210833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2814210833
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3960332321
Short name T777
Test name
Test status
Simulation time 5045109043 ps
CPU time 291.89 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:50:22 PM PDT 24
Peak memory 210272 kb
Host smart-e909a555-9eff-447c-8ac2-1c21889e0445
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3960332321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.3960332321
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.448302785
Short name T692
Test name
Test status
Simulation time 16847513 ps
CPU time 9.12 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:45:41 PM PDT 24
Peak memory 204112 kb
Host smart-fbb58622-3980-4295-a587-07a862eaed3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=448302785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res
et_error.448302785
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.10626811
Short name T65
Test name
Test status
Simulation time 1277033002 ps
CPU time 21.52 seconds
Started May 07 12:45:25 PM PDT 24
Finished May 07 12:45:49 PM PDT 24
Peak memory 205052 kb
Host smart-d7b36a4b-ade5-412f-9fca-cafead368ea2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10626811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.10626811
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2258841431
Short name T880
Test name
Test status
Simulation time 265136959 ps
CPU time 33.64 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 204904 kb
Host smart-8ba40a64-8980-46b6-b151-d7900ef147c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2258841431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2258841431
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3468269012
Short name T547
Test name
Test status
Simulation time 85480852556 ps
CPU time 265.54 seconds
Started May 07 12:45:44 PM PDT 24
Finished May 07 12:50:11 PM PDT 24
Peak memory 211760 kb
Host smart-dc9463d5-bee3-4c2c-ae95-f330971dd723
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3468269012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.3468269012
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3722438595
Short name T311
Test name
Test status
Simulation time 561074577 ps
CPU time 17.55 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:46:00 PM PDT 24
Peak memory 203604 kb
Host smart-690f6aee-e6f1-4d1a-b9c3-048ca7092d94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3722438595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3722438595
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.1900256705
Short name T292
Test name
Test status
Simulation time 739435193 ps
CPU time 20.9 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:55 PM PDT 24
Peak memory 203596 kb
Host smart-5c1a1647-1b6d-487e-9f7c-c881f735e155
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1900256705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1900256705
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3063263066
Short name T157
Test name
Test status
Simulation time 159315511 ps
CPU time 18.03 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:50 PM PDT 24
Peak memory 211672 kb
Host smart-2bcb845f-118a-418d-9770-d1ede5b0f9b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3063263066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3063263066
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.278375664
Short name T293
Test name
Test status
Simulation time 16397978002 ps
CPU time 49.98 seconds
Started May 07 12:45:32 PM PDT 24
Finished May 07 12:46:25 PM PDT 24
Peak memory 211732 kb
Host smart-ffdfcaab-9da1-4933-a536-a663c820e8b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=278375664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.278375664
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.979120099
Short name T132
Test name
Test status
Simulation time 34808109610 ps
CPU time 254.85 seconds
Started May 07 12:45:32 PM PDT 24
Finished May 07 12:49:51 PM PDT 24
Peak memory 211752 kb
Host smart-e3838ab6-0843-48cc-b573-f264d336409e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=979120099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.979120099
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3316543577
Short name T71
Test name
Test status
Simulation time 174078819 ps
CPU time 25.31 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:58 PM PDT 24
Peak memory 204952 kb
Host smart-e9b37e01-704d-4bce-98a9-366e9e9de6a9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316543577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3316543577
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.483457377
Short name T366
Test name
Test status
Simulation time 470513860 ps
CPU time 17.54 seconds
Started May 07 12:45:32 PM PDT 24
Finished May 07 12:45:53 PM PDT 24
Peak memory 204152 kb
Host smart-09d68c7c-bf32-48e1-9b44-dd3af3d99ecc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=483457377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.483457377
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.1670831796
Short name T572
Test name
Test status
Simulation time 399435151 ps
CPU time 3.94 seconds
Started May 07 12:45:47 PM PDT 24
Finished May 07 12:45:52 PM PDT 24
Peak memory 203480 kb
Host smart-2e6654ea-6fa6-4e57-8e66-53cdbd06b0d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1670831796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1670831796
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.206817333
Short name T640
Test name
Test status
Simulation time 28461173683 ps
CPU time 34.58 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:46:09 PM PDT 24
Peak memory 203548 kb
Host smart-d1140831-7813-42f0-8bda-0b4e346dfc0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=206817333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.206817333
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3846242130
Short name T741
Test name
Test status
Simulation time 2411897989 ps
CPU time 22.41 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:57 PM PDT 24
Peak memory 203628 kb
Host smart-59178a8e-8da6-4610-9990-9120504014cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3846242130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3846242130
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4115266483
Short name T46
Test name
Test status
Simulation time 109065774 ps
CPU time 2.6 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:45:46 PM PDT 24
Peak memory 203508 kb
Host smart-4aa3aacc-c793-4bd5-a935-316a99eeaa1b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115266483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4115266483
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.844786973
Short name T481
Test name
Test status
Simulation time 609720750 ps
CPU time 27.98 seconds
Started May 07 12:45:38 PM PDT 24
Finished May 07 12:46:07 PM PDT 24
Peak memory 205644 kb
Host smart-2734c637-f1ac-4f2a-b779-6b8d79fcdf00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=844786973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.844786973
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1555764482
Short name T868
Test name
Test status
Simulation time 14757882507 ps
CPU time 148.95 seconds
Started May 07 12:45:31 PM PDT 24
Finished May 07 12:48:04 PM PDT 24
Peak memory 206804 kb
Host smart-dd3800fb-6e44-429e-b31e-b862542de870
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1555764482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1555764482
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.4044902229
Short name T141
Test name
Test status
Simulation time 160707315 ps
CPU time 63.58 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 207960 kb
Host smart-65bd6007-897c-4705-9773-73235747bb95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4044902229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.4044902229
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2679576394
Short name T735
Test name
Test status
Simulation time 360248613 ps
CPU time 13.22 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:45:50 PM PDT 24
Peak memory 204588 kb
Host smart-767fc852-6457-431f-b2f5-f960ab33f4f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2679576394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2679576394
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2690292754
Short name T93
Test name
Test status
Simulation time 3508196309 ps
CPU time 40.94 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:46:10 PM PDT 24
Peak memory 206064 kb
Host smart-55ac3f78-a388-4b48-9641-75e25d8275eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2690292754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2690292754
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1081488835
Short name T274
Test name
Test status
Simulation time 24967993261 ps
CPU time 186.52 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:48:41 PM PDT 24
Peak memory 206000 kb
Host smart-1b302ab8-3ce2-4eb8-8171-ddedcef69235
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1081488835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.1081488835
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.324216477
Short name T347
Test name
Test status
Simulation time 388972303 ps
CPU time 9.64 seconds
Started May 07 12:45:31 PM PDT 24
Finished May 07 12:45:45 PM PDT 24
Peak memory 203500 kb
Host smart-80138084-2049-416a-9b14-7e0a44fa27d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=324216477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.324216477
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.2746770670
Short name T883
Test name
Test status
Simulation time 57721754 ps
CPU time 2.63 seconds
Started May 07 12:45:31 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203488 kb
Host smart-d9de94b5-f968-46f4-9061-84339b512d70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2746770670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2746770670
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.4119362145
Short name T417
Test name
Test status
Simulation time 184667614 ps
CPU time 17.06 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:50 PM PDT 24
Peak memory 204640 kb
Host smart-079ed965-e3f7-4abc-bbf8-ced346486f2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4119362145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.4119362145
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1019066280
Short name T771
Test name
Test status
Simulation time 28733676878 ps
CPU time 128.8 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:47:43 PM PDT 24
Peak memory 204968 kb
Host smart-d154c4de-b6b8-4585-a0e2-b795d2ad4f23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019066280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1019066280
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1259816704
Short name T694
Test name
Test status
Simulation time 24987957508 ps
CPU time 181.46 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:48:38 PM PDT 24
Peak memory 205432 kb
Host smart-c0a25b83-1338-473e-a5a1-eeb0c0fcb6a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1259816704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1259816704
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1162037957
Short name T828
Test name
Test status
Simulation time 133177777 ps
CPU time 18.84 seconds
Started May 07 12:45:33 PM PDT 24
Finished May 07 12:45:55 PM PDT 24
Peak memory 211868 kb
Host smart-6dde0097-630e-46f4-9944-bd60d22ef5d7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162037957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1162037957
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.3755044102
Short name T487
Test name
Test status
Simulation time 3372195486 ps
CPU time 23.29 seconds
Started May 07 12:45:40 PM PDT 24
Finished May 07 12:46:04 PM PDT 24
Peak memory 203668 kb
Host smart-4dc6e281-0ac7-49de-8098-2ac584c511f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3755044102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3755044102
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.2188408824
Short name T241
Test name
Test status
Simulation time 28163107 ps
CPU time 2.25 seconds
Started May 07 12:45:36 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 203500 kb
Host smart-4feac714-7af5-4163-bbee-b9228a57a309
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2188408824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2188408824
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.697039491
Short name T350
Test name
Test status
Simulation time 29191350677 ps
CPU time 35.65 seconds
Started May 07 12:45:41 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 203548 kb
Host smart-e22e1bc5-3300-4186-bcd5-8fad0ecb59bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=697039491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.697039491
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2829360160
Short name T369
Test name
Test status
Simulation time 4075861097 ps
CPU time 30.6 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203552 kb
Host smart-d49b9bf9-6467-4f4c-a017-e5d91016a5d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2829360160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2829360160
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.216558619
Short name T338
Test name
Test status
Simulation time 25563891 ps
CPU time 2.02 seconds
Started May 07 12:45:39 PM PDT 24
Finished May 07 12:45:42 PM PDT 24
Peak memory 203500 kb
Host smart-c3ebc8df-7444-4f16-a086-4a00160cd936
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216558619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.216558619
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1927206521
Short name T127
Test name
Test status
Simulation time 32882775431 ps
CPU time 232.27 seconds
Started May 07 12:45:31 PM PDT 24
Finished May 07 12:49:27 PM PDT 24
Peak memory 210000 kb
Host smart-8a386daa-01f4-41e8-8354-d47149e56fbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1927206521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1927206521
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3876252216
Short name T436
Test name
Test status
Simulation time 3473133192 ps
CPU time 89.43 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:47:03 PM PDT 24
Peak memory 207920 kb
Host smart-74b289ce-a5f8-4c4e-bddc-353244a3be10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3876252216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3876252216
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1521159720
Short name T850
Test name
Test status
Simulation time 101826506 ps
CPU time 51.53 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:46:24 PM PDT 24
Peak memory 208556 kb
Host smart-b66cc869-c1f8-4292-8a5e-b7d02711f9cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1521159720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.1521159720
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3170131114
Short name T793
Test name
Test status
Simulation time 8090778987 ps
CPU time 362.01 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:51:36 PM PDT 24
Peak memory 219904 kb
Host smart-b90fee99-8797-44fc-94a6-1cc3a2bd52f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3170131114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.3170131114
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.619042073
Short name T184
Test name
Test status
Simulation time 1645800263 ps
CPU time 15.86 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:45:59 PM PDT 24
Peak memory 204932 kb
Host smart-45ae9aed-0ffd-4fa5-afe1-d682937e5fd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=619042073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.619042073
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1040578919
Short name T503
Test name
Test status
Simulation time 1295623547 ps
CPU time 55.8 seconds
Started May 07 12:45:46 PM PDT 24
Finished May 07 12:46:43 PM PDT 24
Peak memory 205564 kb
Host smart-6def067d-5a27-4482-a6d4-0db6d8160916
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1040578919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1040578919
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4269703385
Short name T517
Test name
Test status
Simulation time 84179539981 ps
CPU time 440.43 seconds
Started May 07 12:45:44 PM PDT 24
Finished May 07 12:53:05 PM PDT 24
Peak memory 211704 kb
Host smart-5df88ca7-4317-402f-86be-9cdf7971a7ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4269703385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.4269703385
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.421316822
Short name T433
Test name
Test status
Simulation time 222497703 ps
CPU time 8.12 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:45:51 PM PDT 24
Peak memory 203464 kb
Host smart-9c408038-b4de-4f16-8eb2-0ee1b30c73d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=421316822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.421316822
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.380496452
Short name T635
Test name
Test status
Simulation time 63048644 ps
CPU time 2.73 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 203460 kb
Host smart-42d89abd-4193-4a56-9d2a-727e545bc78f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=380496452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.380496452
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.4157238549
Short name T645
Test name
Test status
Simulation time 861350440 ps
CPU time 19.7 seconds
Started May 07 12:45:39 PM PDT 24
Finished May 07 12:46:00 PM PDT 24
Peak memory 211616 kb
Host smart-649c9bf9-b842-40f2-bbfd-d28e4d0e5f57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4157238549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4157238549
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.475352239
Short name T257
Test name
Test status
Simulation time 9184290926 ps
CPU time 52.29 seconds
Started May 07 12:45:35 PM PDT 24
Finished May 07 12:46:30 PM PDT 24
Peak memory 204636 kb
Host smart-e5eba039-1727-4cd1-88fb-90023384025f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=475352239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.475352239
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.40746784
Short name T559
Test name
Test status
Simulation time 52140909426 ps
CPU time 173.21 seconds
Started May 07 12:45:51 PM PDT 24
Finished May 07 12:48:45 PM PDT 24
Peak memory 211756 kb
Host smart-99b0f6cc-42a9-436c-97e1-8ec45ddec42a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=40746784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.40746784
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.175714394
Short name T855
Test name
Test status
Simulation time 106863142 ps
CPU time 4.49 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 204188 kb
Host smart-07f0d8d9-1740-4738-ad38-b89f89b5c66f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175714394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.175714394
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.962991787
Short name T568
Test name
Test status
Simulation time 1120269727 ps
CPU time 19.45 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 204140 kb
Host smart-67ec7dc9-e8c6-418a-b64e-c825e70f56e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=962991787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.962991787
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.2176203698
Short name T159
Test name
Test status
Simulation time 28036126 ps
CPU time 2.47 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:33 PM PDT 24
Peak memory 203520 kb
Host smart-b6ebfc9e-27a1-4717-80ff-eb24dd91d20c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2176203698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2176203698
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3394880148
Short name T787
Test name
Test status
Simulation time 5992799886 ps
CPU time 30.73 seconds
Started May 07 12:45:31 PM PDT 24
Finished May 07 12:46:05 PM PDT 24
Peak memory 203508 kb
Host smart-4b423200-d858-4de0-833d-5709221b62d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394880148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3394880148
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1278520852
Short name T400
Test name
Test status
Simulation time 14026795454 ps
CPU time 34 seconds
Started May 07 12:45:29 PM PDT 24
Finished May 07 12:46:07 PM PDT 24
Peak memory 203560 kb
Host smart-3e1cb186-d7d2-41d5-bf55-89d54291f4a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1278520852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1278520852
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2941508326
Short name T755
Test name
Test status
Simulation time 55451940 ps
CPU time 2.39 seconds
Started May 07 12:45:26 PM PDT 24
Finished May 07 12:45:32 PM PDT 24
Peak memory 203500 kb
Host smart-d7f14009-dd40-4945-a7ae-a9c01b1f3581
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941508326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2941508326
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1303891276
Short name T18
Test name
Test status
Simulation time 2744324487 ps
CPU time 56.36 seconds
Started May 07 12:45:45 PM PDT 24
Finished May 07 12:46:43 PM PDT 24
Peak memory 205844 kb
Host smart-3d115c22-3e1c-46c2-bce7-b6028d3e87eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1303891276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1303891276
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3835768078
Short name T893
Test name
Test status
Simulation time 758534221 ps
CPU time 17.24 seconds
Started May 07 12:45:32 PM PDT 24
Finished May 07 12:45:53 PM PDT 24
Peak memory 203872 kb
Host smart-3c6adfea-8ce6-499b-982d-0e665b5d65f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3835768078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3835768078
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2559949384
Short name T175
Test name
Test status
Simulation time 1452439903 ps
CPU time 117.87 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:47:32 PM PDT 24
Peak memory 206444 kb
Host smart-565e80b5-06f4-48d4-bc79-fd8b8224bf98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2559949384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.2559949384
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3629037860
Short name T279
Test name
Test status
Simulation time 155274877 ps
CPU time 26.34 seconds
Started May 07 12:45:45 PM PDT 24
Finished May 07 12:46:12 PM PDT 24
Peak memory 205548 kb
Host smart-5b32a41b-bc00-4f15-8f4c-ed579c508f42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3629037860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.3629037860
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3193477042
Short name T158
Test name
Test status
Simulation time 735053079 ps
CPU time 5.5 seconds
Started May 07 12:45:34 PM PDT 24
Finished May 07 12:45:42 PM PDT 24
Peak memory 204596 kb
Host smart-d615660c-eeb3-4fd1-b6c2-e40ec4ea4c01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193477042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3193477042
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1208542324
Short name T814
Test name
Test status
Simulation time 1620598964 ps
CPU time 54.71 seconds
Started May 07 12:45:38 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 206744 kb
Host smart-7ee23470-63ea-4132-b1dc-c5af2f9e6b96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1208542324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1208542324
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1392780156
Short name T212
Test name
Test status
Simulation time 37006683060 ps
CPU time 227.41 seconds
Started May 07 12:45:48 PM PDT 24
Finished May 07 12:49:37 PM PDT 24
Peak memory 206028 kb
Host smart-dda938a7-9c6a-46d0-97d6-d5194e56665f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1392780156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.1392780156
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2421612920
Short name T655
Test name
Test status
Simulation time 173544922 ps
CPU time 13.82 seconds
Started May 07 12:45:53 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 203648 kb
Host smart-f0d97be7-bbbd-490d-912e-f57114d428ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2421612920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2421612920
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.1879198501
Short name T836
Test name
Test status
Simulation time 884576235 ps
CPU time 24.04 seconds
Started May 07 12:45:47 PM PDT 24
Finished May 07 12:46:12 PM PDT 24
Peak memory 203580 kb
Host smart-ee9423ec-b160-426f-b4f0-06223dc50ee4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1879198501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1879198501
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.944835741
Short name T812
Test name
Test status
Simulation time 591146161 ps
CPU time 26.72 seconds
Started May 07 12:45:37 PM PDT 24
Finished May 07 12:46:05 PM PDT 24
Peak memory 204900 kb
Host smart-803951c3-2c5b-4282-8c69-b5285423aa2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=944835741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.944835741
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.162463366
Short name T774
Test name
Test status
Simulation time 23058179986 ps
CPU time 140.39 seconds
Started May 07 12:45:30 PM PDT 24
Finished May 07 12:47:54 PM PDT 24
Peak memory 205040 kb
Host smart-0a95a146-b8d5-4efe-9bb7-0b3c61913403
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=162463366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.162463366
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.173724558
Short name T166
Test name
Test status
Simulation time 51063838393 ps
CPU time 213.43 seconds
Started May 07 12:45:28 PM PDT 24
Finished May 07 12:49:06 PM PDT 24
Peak memory 204884 kb
Host smart-c81ad398-5eda-4300-bec4-3b12acc59457
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=173724558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.173724558
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2673110824
Short name T851
Test name
Test status
Simulation time 324612885 ps
CPU time 17.96 seconds
Started May 07 12:45:32 PM PDT 24
Finished May 07 12:45:54 PM PDT 24
Peak memory 204904 kb
Host smart-84ef0414-7e3d-4c9e-af21-ab752a06e9b9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673110824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2673110824
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1894941023
Short name T476
Test name
Test status
Simulation time 246398574 ps
CPU time 15.39 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:45:59 PM PDT 24
Peak memory 203536 kb
Host smart-e9e144fd-71cc-490a-817f-cf08d4335d86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1894941023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1894941023
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.1687251081
Short name T353
Test name
Test status
Simulation time 295575165 ps
CPU time 3.11 seconds
Started May 07 12:45:46 PM PDT 24
Finished May 07 12:45:50 PM PDT 24
Peak memory 203492 kb
Host smart-97fe5bfa-e02c-4ecc-94ba-3c90bf912487
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1687251081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1687251081
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3078209180
Short name T403
Test name
Test status
Simulation time 15317448816 ps
CPU time 33.07 seconds
Started May 07 12:45:24 PM PDT 24
Finished May 07 12:46:00 PM PDT 24
Peak memory 203576 kb
Host smart-c8a14385-3c12-4250-bc94-68c8df5461fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078209180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3078209180
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1825338205
Short name T842
Test name
Test status
Simulation time 5868896389 ps
CPU time 30.25 seconds
Started May 07 12:45:45 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 203532 kb
Host smart-3ddf1471-d7e8-4f8a-ab91-32917632596c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1825338205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1825338205
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2355872621
Short name T295
Test name
Test status
Simulation time 46295598 ps
CPU time 2.63 seconds
Started May 07 12:45:38 PM PDT 24
Finished May 07 12:45:42 PM PDT 24
Peak memory 203508 kb
Host smart-a28e1fc2-c458-4e46-9d67-ca79ce21f06f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355872621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2355872621
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1817267084
Short name T699
Test name
Test status
Simulation time 10353455177 ps
CPU time 216.59 seconds
Started May 07 12:45:53 PM PDT 24
Finished May 07 12:49:31 PM PDT 24
Peak memory 211756 kb
Host smart-a9274c23-1870-47f1-ae1c-a24f57517fe2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1817267084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1817267084
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.4127224946
Short name T629
Test name
Test status
Simulation time 5222856901 ps
CPU time 37.77 seconds
Started May 07 12:45:50 PM PDT 24
Finished May 07 12:46:29 PM PDT 24
Peak memory 204012 kb
Host smart-b2c68512-1050-48d4-9eb7-78c887c019cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4127224946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.4127224946
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3780532374
Short name T596
Test name
Test status
Simulation time 5099790849 ps
CPU time 594.79 seconds
Started May 07 12:45:48 PM PDT 24
Finished May 07 12:55:44 PM PDT 24
Peak memory 219976 kb
Host smart-4871ba18-4582-4fb2-8dd6-b78c394a2b2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3780532374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.3780532374
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.4120335557
Short name T690
Test name
Test status
Simulation time 95707736 ps
CPU time 35.48 seconds
Started May 07 12:45:43 PM PDT 24
Finished May 07 12:46:20 PM PDT 24
Peak memory 206204 kb
Host smart-d8e6f04b-ae1d-48ba-92b9-efb9f6563f47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4120335557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.4120335557
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.976462374
Short name T773
Test name
Test status
Simulation time 801196379 ps
CPU time 18.52 seconds
Started May 07 12:45:38 PM PDT 24
Finished May 07 12:45:58 PM PDT 24
Peak memory 205296 kb
Host smart-7ff89b20-97a3-4725-99bd-7066ad7b3241
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976462374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.976462374
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2345906142
Short name T50
Test name
Test status
Simulation time 81675168 ps
CPU time 5.02 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:41 PM PDT 24
Peak memory 203612 kb
Host smart-e80d146c-14fc-4820-be7d-858efe88dc7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2345906142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2345906142
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.907283325
Short name T701
Test name
Test status
Simulation time 39863968160 ps
CPU time 336.33 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:50:18 PM PDT 24
Peak memory 211668 kb
Host smart-d55bbd3b-26de-4c9b-9a1a-8ec349d70402
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=907283325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow
_rsp.907283325
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.661544740
Short name T308
Test name
Test status
Simulation time 459759070 ps
CPU time 14.48 seconds
Started May 07 12:44:49 PM PDT 24
Finished May 07 12:45:05 PM PDT 24
Peak memory 203480 kb
Host smart-a449597c-9b61-47ed-8c81-7445865f0f10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=661544740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.661544740
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.3365345885
Short name T659
Test name
Test status
Simulation time 589537732 ps
CPU time 20.62 seconds
Started May 07 12:44:38 PM PDT 24
Finished May 07 12:45:01 PM PDT 24
Peak memory 203496 kb
Host smart-f78429d8-a7c7-4eb0-b0c3-55434c0331fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3365345885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3365345885
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.1810348095
Short name T523
Test name
Test status
Simulation time 29872864 ps
CPU time 3.53 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:45:01 PM PDT 24
Peak memory 203872 kb
Host smart-fd58db49-8853-47af-8dea-79563c45bcd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1810348095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1810348095
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2378273406
Short name T240
Test name
Test status
Simulation time 94997703456 ps
CPU time 273.24 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:49:43 PM PDT 24
Peak memory 204944 kb
Host smart-eeb63e7b-433e-48ec-8ee1-a437ece529dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378273406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2378273406
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.224149611
Short name T55
Test name
Test status
Simulation time 22674475165 ps
CPU time 180.03 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:47:55 PM PDT 24
Peak memory 205028 kb
Host smart-f3f422bd-dfc5-44c1-ad4e-e9ced4bc6b2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=224149611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.224149611
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.4094624292
Short name T9
Test name
Test status
Simulation time 234048015 ps
CPU time 29 seconds
Started May 07 12:44:40 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 211672 kb
Host smart-9de33708-5895-4978-87ac-ea6ca7d79c8e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094624292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.4094624292
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.829256073
Short name T340
Test name
Test status
Simulation time 713814612 ps
CPU time 10.02 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:45:05 PM PDT 24
Peak memory 203952 kb
Host smart-9199838e-9d9b-4e47-b403-bf6e5ae53a6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=829256073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.829256073
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.1535452569
Short name T475
Test name
Test status
Simulation time 172867797 ps
CPU time 3.33 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:45 PM PDT 24
Peak memory 203488 kb
Host smart-14d66f48-7418-4a18-95ee-7f3d71e5031f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1535452569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1535452569
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.423425738
Short name T634
Test name
Test status
Simulation time 4948027349 ps
CPU time 26.29 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:45:02 PM PDT 24
Peak memory 203568 kb
Host smart-45c2c179-d378-4d05-aed3-5927d56cf3fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=423425738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.423425738
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1905180600
Short name T381
Test name
Test status
Simulation time 11411324357 ps
CPU time 37.06 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:45:32 PM PDT 24
Peak memory 203612 kb
Host smart-a9b78ea7-2701-4f06-9c5b-8336491d1c40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1905180600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1905180600
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.625608752
Short name T839
Test name
Test status
Simulation time 114395901 ps
CPU time 2.53 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 203420 kb
Host smart-f22c539a-1008-48d0-9090-97cdfb10e73c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625608752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.625608752
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1733885730
Short name T499
Test name
Test status
Simulation time 1211195299 ps
CPU time 42.02 seconds
Started May 07 12:44:45 PM PDT 24
Finished May 07 12:45:28 PM PDT 24
Peak memory 207008 kb
Host smart-a9efc048-b23d-4739-8afb-2a58cf26697e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1733885730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1733885730
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4220427612
Short name T276
Test name
Test status
Simulation time 6459022350 ps
CPU time 184.04 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:48:02 PM PDT 24
Peak memory 209848 kb
Host smart-d16f084a-07be-4c54-80e7-0b8acb2ba541
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4220427612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4220427612
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1909807427
Short name T622
Test name
Test status
Simulation time 1429752848 ps
CPU time 168.03 seconds
Started May 07 12:44:49 PM PDT 24
Finished May 07 12:47:38 PM PDT 24
Peak memory 211144 kb
Host smart-64027da0-8540-49d4-9ba3-16f72f53f174
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1909807427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1909807427
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1872357345
Short name T465
Test name
Test status
Simulation time 550685119 ps
CPU time 16.77 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:44:55 PM PDT 24
Peak memory 204952 kb
Host smart-b0c75f92-0221-4f01-91b1-07a147bdd753
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1872357345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1872357345
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2077509872
Short name T680
Test name
Test status
Simulation time 1507875171 ps
CPU time 30.59 seconds
Started May 07 12:45:51 PM PDT 24
Finished May 07 12:46:23 PM PDT 24
Peak memory 205568 kb
Host smart-483395c5-9d2f-4eea-a85e-92f0fed40f2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2077509872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2077509872
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3841111028
Short name T278
Test name
Test status
Simulation time 221208608953 ps
CPU time 730.29 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:57:53 PM PDT 24
Peak memory 211724 kb
Host smart-3cd73105-45b5-4e20-aef4-1c988c685cea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3841111028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.3841111028
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2273321706
Short name T117
Test name
Test status
Simulation time 358249971 ps
CPU time 13.26 seconds
Started May 07 12:45:55 PM PDT 24
Finished May 07 12:46:09 PM PDT 24
Peak memory 203656 kb
Host smart-07e4db8e-9421-48f7-81bc-dede7072d446
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2273321706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2273321706
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.2202012821
Short name T13
Test name
Test status
Simulation time 291774839 ps
CPU time 15.79 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:45:59 PM PDT 24
Peak memory 203512 kb
Host smart-d70cb2c7-17b1-4a2a-9ba6-53852f7937a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2202012821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2202012821
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.1931516093
Short name T105
Test name
Test status
Simulation time 500120085 ps
CPU time 11.89 seconds
Started May 07 12:45:50 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 204648 kb
Host smart-0ef1c053-9c91-479e-90ca-520d54707262
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1931516093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1931516093
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1841150068
Short name T442
Test name
Test status
Simulation time 48460893064 ps
CPU time 140.09 seconds
Started May 07 12:45:50 PM PDT 24
Finished May 07 12:48:12 PM PDT 24
Peak memory 204808 kb
Host smart-da71bac6-770f-452b-aa30-79a5dc13a7db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841150068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1841150068
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.701901153
Short name T20
Test name
Test status
Simulation time 63512213377 ps
CPU time 249.44 seconds
Started May 07 12:45:46 PM PDT 24
Finished May 07 12:49:57 PM PDT 24
Peak memory 205280 kb
Host smart-b874c7e4-22ea-454b-b4fc-52869213cd29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=701901153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.701901153
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2885653668
Short name T712
Test name
Test status
Simulation time 137037863 ps
CPU time 12.62 seconds
Started May 07 12:45:44 PM PDT 24
Finished May 07 12:45:58 PM PDT 24
Peak memory 211684 kb
Host smart-67fc69fe-39ed-4f5d-981b-b2de628ee2e9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885653668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2885653668
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.452034185
Short name T419
Test name
Test status
Simulation time 821209164 ps
CPU time 9.95 seconds
Started May 07 12:45:44 PM PDT 24
Finished May 07 12:45:55 PM PDT 24
Peak memory 203412 kb
Host smart-d50525e9-d809-448b-922e-e6b0d4368813
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=452034185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.452034185
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.2851648893
Short name T492
Test name
Test status
Simulation time 188077302 ps
CPU time 3.38 seconds
Started May 07 12:45:44 PM PDT 24
Finished May 07 12:45:49 PM PDT 24
Peak memory 203484 kb
Host smart-ac786103-f44e-4c93-9e2b-3eb1381a6806
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2851648893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2851648893
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2770660835
Short name T291
Test name
Test status
Simulation time 12684176375 ps
CPU time 38.75 seconds
Started May 07 12:45:48 PM PDT 24
Finished May 07 12:46:28 PM PDT 24
Peak memory 203544 kb
Host smart-c5d5bb4f-93b4-4308-9d49-7c7e4572f33e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770660835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2770660835
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.591179664
Short name T432
Test name
Test status
Simulation time 3616119667 ps
CPU time 26.45 seconds
Started May 07 12:45:49 PM PDT 24
Finished May 07 12:46:16 PM PDT 24
Peak memory 203576 kb
Host smart-acb987d4-d214-451c-9a07-f344cb669b17
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=591179664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.591179664
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.331932703
Short name T795
Test name
Test status
Simulation time 39103503 ps
CPU time 2.32 seconds
Started May 07 12:45:45 PM PDT 24
Finished May 07 12:45:49 PM PDT 24
Peak memory 203472 kb
Host smart-c9928809-890a-4c62-b0c3-654bab90d3d6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331932703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.331932703
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1882186290
Short name T37
Test name
Test status
Simulation time 5063927461 ps
CPU time 119.45 seconds
Started May 07 12:45:55 PM PDT 24
Finished May 07 12:47:56 PM PDT 24
Peak memory 207092 kb
Host smart-81785c04-895f-4dff-abbc-17961e3e55cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1882186290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1882186290
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1384603051
Short name T15
Test name
Test status
Simulation time 7644054040 ps
CPU time 256.59 seconds
Started May 07 12:45:46 PM PDT 24
Finished May 07 12:50:04 PM PDT 24
Peak memory 210340 kb
Host smart-b633bd7d-7eaa-42e1-aa1a-e44f70c729c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1384603051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1384603051
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4091740676
Short name T877
Test name
Test status
Simulation time 2964061301 ps
CPU time 385.42 seconds
Started May 07 12:45:46 PM PDT 24
Finished May 07 12:52:13 PM PDT 24
Peak memory 220000 kb
Host smart-ff328c98-61aa-4ed5-bbe8-1faafa92626e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4091740676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.4091740676
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3415210722
Short name T687
Test name
Test status
Simulation time 6008295043 ps
CPU time 294.92 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:50:38 PM PDT 24
Peak memory 220940 kb
Host smart-6c45f476-421b-4251-8e44-b808435b86e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3415210722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.3415210722
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2539275439
Short name T681
Test name
Test status
Simulation time 40616784 ps
CPU time 5.14 seconds
Started May 07 12:45:42 PM PDT 24
Finished May 07 12:45:48 PM PDT 24
Peak memory 211688 kb
Host smart-62722c9f-351c-422c-acea-587905909032
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2539275439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2539275439
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.126617672
Short name T51
Test name
Test status
Simulation time 1513886000 ps
CPU time 41.17 seconds
Started May 07 12:45:56 PM PDT 24
Finished May 07 12:46:39 PM PDT 24
Peak memory 211432 kb
Host smart-73eb6acf-5e43-4512-a96e-36cbe2e50e11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=126617672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.126617672
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2800857506
Short name T173
Test name
Test status
Simulation time 147770986816 ps
CPU time 544.78 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:55:05 PM PDT 24
Peak memory 207100 kb
Host smart-28f9f1ba-7d6d-4f52-a771-bb49c63fe58e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2800857506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.2800857506
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3491056742
Short name T752
Test name
Test status
Simulation time 146316411 ps
CPU time 7.24 seconds
Started May 07 12:45:52 PM PDT 24
Finished May 07 12:46:01 PM PDT 24
Peak memory 203424 kb
Host smart-3d48104d-1b8f-4d90-a2e4-97c6696bb519
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3491056742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3491056742
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.3818856249
Short name T447
Test name
Test status
Simulation time 209963816 ps
CPU time 23.89 seconds
Started May 07 12:45:48 PM PDT 24
Finished May 07 12:46:13 PM PDT 24
Peak memory 203704 kb
Host smart-38246081-1904-47b0-845e-80869dc2596e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3818856249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3818856249
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.3765387036
Short name T108
Test name
Test status
Simulation time 195311583 ps
CPU time 9.41 seconds
Started May 07 12:45:50 PM PDT 24
Finished May 07 12:46:01 PM PDT 24
Peak memory 211640 kb
Host smart-34b114a6-812a-4de2-a518-fa915ccc3220
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3765387036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3765387036
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.613047724
Short name T167
Test name
Test status
Simulation time 30212483953 ps
CPU time 65.4 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:47:05 PM PDT 24
Peak memory 204684 kb
Host smart-ab1b5cc3-d34b-4bfb-ab41-df0f560a3cb5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=613047724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.613047724
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2391996123
Short name T313
Test name
Test status
Simulation time 60998197871 ps
CPU time 218.53 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:49:39 PM PDT 24
Peak memory 205032 kb
Host smart-1bf0b454-b208-4aa3-ae9f-c5ba2fee8e7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2391996123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2391996123
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1712638479
Short name T540
Test name
Test status
Simulation time 50493521 ps
CPU time 4.36 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:04 PM PDT 24
Peak memory 204280 kb
Host smart-31c51c49-ecd5-4c81-a064-8446e49b63de
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712638479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1712638479
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.3598028660
Short name T325
Test name
Test status
Simulation time 52540542 ps
CPU time 2.79 seconds
Started May 07 12:45:46 PM PDT 24
Finished May 07 12:45:50 PM PDT 24
Peak memory 203612 kb
Host smart-900bbfd4-4910-4343-88a0-0ab89cdc60dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3598028660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3598028660
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.696682271
Short name T491
Test name
Test status
Simulation time 190251439 ps
CPU time 3.79 seconds
Started May 07 12:45:49 PM PDT 24
Finished May 07 12:45:55 PM PDT 24
Peak memory 203468 kb
Host smart-82d2bc90-5c54-4c11-919c-5ae6e9efc36d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=696682271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.696682271
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1905054347
Short name T255
Test name
Test status
Simulation time 5178388571 ps
CPU time 27.5 seconds
Started May 07 12:45:50 PM PDT 24
Finished May 07 12:46:19 PM PDT 24
Peak memory 203576 kb
Host smart-4d048977-7ec3-4c26-8eb1-4807696a9dfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905054347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1905054347
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2868517207
Short name T829
Test name
Test status
Simulation time 21335063095 ps
CPU time 51.93 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:52 PM PDT 24
Peak memory 203548 kb
Host smart-99d9388d-8f75-4c67-8bbe-5be36c817866
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2868517207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2868517207
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1360865876
Short name T750
Test name
Test status
Simulation time 58320183 ps
CPU time 2.37 seconds
Started May 07 12:45:49 PM PDT 24
Finished May 07 12:45:53 PM PDT 24
Peak memory 203472 kb
Host smart-96a9e0f8-2762-4d18-83f5-b8659ad31d21
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360865876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1360865876
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2616694687
Short name T77
Test name
Test status
Simulation time 4143066836 ps
CPU time 138.69 seconds
Started May 07 12:45:53 PM PDT 24
Finished May 07 12:48:13 PM PDT 24
Peak memory 205868 kb
Host smart-94769dde-c5aa-4d6c-8449-e33842518d10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2616694687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2616694687
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.417842880
Short name T275
Test name
Test status
Simulation time 4882725266 ps
CPU time 85.99 seconds
Started May 07 12:45:52 PM PDT 24
Finished May 07 12:47:19 PM PDT 24
Peak memory 204944 kb
Host smart-e6ab2315-7bca-40d7-93c9-0cbcad7ccadf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=417842880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.417842880
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2027290014
Short name T112
Test name
Test status
Simulation time 5159289672 ps
CPU time 310.95 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:51:11 PM PDT 24
Peak memory 209824 kb
Host smart-fd97e805-05b0-4eea-9062-b80c14d05394
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2027290014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.2027290014
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3307214916
Short name T604
Test name
Test status
Simulation time 34707116 ps
CPU time 16.02 seconds
Started May 07 12:45:54 PM PDT 24
Finished May 07 12:46:11 PM PDT 24
Peak memory 205432 kb
Host smart-6da0472d-9967-4ade-9c92-aaff75c7830a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3307214916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.3307214916
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1967198746
Short name T441
Test name
Test status
Simulation time 368990523 ps
CPU time 16.11 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:16 PM PDT 24
Peak memory 204948 kb
Host smart-2047ca0d-e767-4a68-98f5-b442e4c39210
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1967198746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1967198746
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.677928378
Short name T900
Test name
Test status
Simulation time 4006542596 ps
CPU time 28.91 seconds
Started May 07 12:45:52 PM PDT 24
Finished May 07 12:46:22 PM PDT 24
Peak memory 204784 kb
Host smart-7a933212-d7fd-4e8c-b59f-4402a7c73742
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=677928378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.677928378
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3542713911
Short name T82
Test name
Test status
Simulation time 72550277784 ps
CPU time 614.27 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:56:16 PM PDT 24
Peak memory 206160 kb
Host smart-851411c2-d35f-4939-b7d8-bf1d758286be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3542713911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.3542713911
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2052173428
Short name T822
Test name
Test status
Simulation time 1291017979 ps
CPU time 18.21 seconds
Started May 07 12:45:57 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 203988 kb
Host smart-624336fe-82c3-44f2-9661-fb957709f5a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2052173428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2052173428
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.1316697868
Short name T21
Test name
Test status
Simulation time 3219298261 ps
CPU time 28.08 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:46:33 PM PDT 24
Peak memory 203572 kb
Host smart-c32de3d2-c4d0-4335-a299-f3d16e414c3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1316697868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1316697868
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.315596583
Short name T57
Test name
Test status
Simulation time 103379735 ps
CPU time 16.54 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 204868 kb
Host smart-89cb5bbc-9266-4eff-b97d-cae3190d122e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=315596583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.315596583
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3643065603
Short name T631
Test name
Test status
Simulation time 32725825511 ps
CPU time 143.61 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:48:26 PM PDT 24
Peak memory 211704 kb
Host smart-49e7e59d-95ad-4e3c-a33d-7dc872154adb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643065603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3643065603
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4237968414
Short name T563
Test name
Test status
Simulation time 29329282072 ps
CPU time 249.65 seconds
Started May 07 12:45:55 PM PDT 24
Finished May 07 12:50:06 PM PDT 24
Peak memory 204804 kb
Host smart-5f3d096b-b356-4ca5-891a-8f41882af2a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4237968414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.4237968414
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1805885414
Short name T702
Test name
Test status
Simulation time 172274267 ps
CPU time 12.77 seconds
Started May 07 12:45:49 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 204708 kb
Host smart-8a8b213e-52ec-42f5-97af-1f0c870a2899
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805885414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1805885414
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.1375376266
Short name T832
Test name
Test status
Simulation time 2140668346 ps
CPU time 15.73 seconds
Started May 07 12:45:52 PM PDT 24
Finished May 07 12:46:09 PM PDT 24
Peak memory 203908 kb
Host smart-41ba4255-6db0-49e7-a9aa-98e86dd542ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1375376266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1375376266
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.172279655
Short name T656
Test name
Test status
Simulation time 63932847 ps
CPU time 2.05 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:02 PM PDT 24
Peak memory 203476 kb
Host smart-d3af88f2-e23c-4b7e-9c4a-c531c34ed574
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=172279655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.172279655
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1351990824
Short name T203
Test name
Test status
Simulation time 7693607490 ps
CPU time 31.27 seconds
Started May 07 12:45:48 PM PDT 24
Finished May 07 12:46:21 PM PDT 24
Peak memory 203456 kb
Host smart-3ecfe31c-9a18-40ac-81a5-f4d95ce24392
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351990824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1351990824
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.594808865
Short name T527
Test name
Test status
Simulation time 4594366294 ps
CPU time 35.97 seconds
Started May 07 12:45:50 PM PDT 24
Finished May 07 12:46:27 PM PDT 24
Peak memory 203512 kb
Host smart-f1dcb939-6e4a-4a96-8c93-244809e94bd7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=594808865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.594808865
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.64285946
Short name T383
Test name
Test status
Simulation time 45771762 ps
CPU time 2.01 seconds
Started May 07 12:45:54 PM PDT 24
Finished May 07 12:45:57 PM PDT 24
Peak memory 203500 kb
Host smart-b5fbbcf9-7167-45ad-a905-dd491d5d5aa5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64285946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.64285946
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2895133855
Short name T114
Test name
Test status
Simulation time 15025920152 ps
CPU time 271.16 seconds
Started May 07 12:45:55 PM PDT 24
Finished May 07 12:50:27 PM PDT 24
Peak memory 211688 kb
Host smart-cf9d30aa-1ea5-4096-b753-326952fc1ab5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2895133855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2895133855
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1810201662
Short name T354
Test name
Test status
Simulation time 1004152749 ps
CPU time 64.86 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:47:09 PM PDT 24
Peak memory 204556 kb
Host smart-02b45450-42f2-4986-9f7d-a83f48c109c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1810201662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1810201662
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2559750705
Short name T536
Test name
Test status
Simulation time 781446724 ps
CPU time 230.71 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:49:56 PM PDT 24
Peak memory 209360 kb
Host smart-5470438b-9f49-4df9-beb2-7289b6f52a8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2559750705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.2559750705
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2287555410
Short name T764
Test name
Test status
Simulation time 10714315429 ps
CPU time 172.47 seconds
Started May 07 12:45:52 PM PDT 24
Finished May 07 12:48:45 PM PDT 24
Peak memory 210336 kb
Host smart-a82d6620-de45-492a-a1e9-c0d7c4a5aaf0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2287555410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.2287555410
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2984375146
Short name T238
Test name
Test status
Simulation time 3041254429 ps
CPU time 21.7 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:21 PM PDT 24
Peak memory 205196 kb
Host smart-dbe8e48e-4ae5-4dad-8167-60cc1e864092
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2984375146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2984375146
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1409498649
Short name T206
Test name
Test status
Simulation time 470038619 ps
CPU time 41.7 seconds
Started May 07 12:45:52 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 204588 kb
Host smart-03fc8457-a282-466e-acfa-c0143883e493
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1409498649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1409498649
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2233544293
Short name T565
Test name
Test status
Simulation time 25555326490 ps
CPU time 107.6 seconds
Started May 07 12:45:55 PM PDT 24
Finished May 07 12:47:43 PM PDT 24
Peak memory 205856 kb
Host smart-b8b6bf47-d0f8-428b-8f90-fd95aab1eae2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2233544293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.2233544293
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.4203435751
Short name T497
Test name
Test status
Simulation time 104049278 ps
CPU time 13.39 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 203504 kb
Host smart-baa71f27-0f6f-43f1-a118-de820f0a5a85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4203435751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.4203435751
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.2410956447
Short name T334
Test name
Test status
Simulation time 490360083 ps
CPU time 17.85 seconds
Started May 07 12:45:57 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 203504 kb
Host smart-170a768d-d4dd-4804-8a44-ab9e350f9040
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2410956447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2410956447
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.3095065344
Short name T168
Test name
Test status
Simulation time 79945880 ps
CPU time 7.49 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 204588 kb
Host smart-8db7878e-9509-47cc-8f16-abe7133c0f0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3095065344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3095065344
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.1267264164
Short name T153
Test name
Test status
Simulation time 32556721867 ps
CPU time 79.48 seconds
Started May 07 12:45:49 PM PDT 24
Finished May 07 12:47:10 PM PDT 24
Peak memory 204868 kb
Host smart-11e17aa2-1804-4003-9e8c-02cbb0ab582c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267264164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1267264164
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.733974308
Short name T610
Test name
Test status
Simulation time 24401606303 ps
CPU time 142.56 seconds
Started May 07 12:45:55 PM PDT 24
Finished May 07 12:48:19 PM PDT 24
Peak memory 204940 kb
Host smart-274ef5e4-3f45-4bbc-b828-ae75a32a14ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=733974308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.733974308
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3035553848
Short name T219
Test name
Test status
Simulation time 70953405 ps
CPU time 3.49 seconds
Started May 07 12:46:06 PM PDT 24
Finished May 07 12:46:11 PM PDT 24
Peak memory 204120 kb
Host smart-b7dcae14-59f8-4cdb-8ab3-9718eb1e081d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035553848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3035553848
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.4091769883
Short name T384
Test name
Test status
Simulation time 5061679805 ps
CPU time 29.5 seconds
Started May 07 12:45:54 PM PDT 24
Finished May 07 12:46:24 PM PDT 24
Peak memory 211756 kb
Host smart-bd0c57e4-1ce3-413a-a862-094308e5b014
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4091769883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4091769883
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.1418801171
Short name T790
Test name
Test status
Simulation time 96680835 ps
CPU time 2.34 seconds
Started May 07 12:45:53 PM PDT 24
Finished May 07 12:45:57 PM PDT 24
Peak memory 203472 kb
Host smart-d9ff6f64-a984-4f9a-8cce-d6881ebb4baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1418801171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1418801171
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2356916419
Short name T405
Test name
Test status
Simulation time 13276839490 ps
CPU time 33.77 seconds
Started May 07 12:45:54 PM PDT 24
Finished May 07 12:46:28 PM PDT 24
Peak memory 203576 kb
Host smart-228b13f9-8917-45d6-a577-6f0e2eea5e6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356916419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2356916419
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.4026242312
Short name T320
Test name
Test status
Simulation time 20420693414 ps
CPU time 53.44 seconds
Started May 07 12:45:53 PM PDT 24
Finished May 07 12:46:48 PM PDT 24
Peak memory 203576 kb
Host smart-0ee5e646-3614-4164-935b-0499fb6c2c6d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4026242312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.4026242312
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2262301390
Short name T382
Test name
Test status
Simulation time 21222884 ps
CPU time 2.11 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:06 PM PDT 24
Peak memory 203504 kb
Host smart-9d486a39-c2f6-4bf7-b1b2-0e6981f41fb4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262301390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2262301390
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.4176698095
Short name T336
Test name
Test status
Simulation time 1697286735 ps
CPU time 79.48 seconds
Started May 07 12:45:57 PM PDT 24
Finished May 07 12:47:18 PM PDT 24
Peak memory 206776 kb
Host smart-8e99f9dd-bd74-43c4-bb82-89233095f518
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4176698095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4176698095
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2562040720
Short name T866
Test name
Test status
Simulation time 2866702668 ps
CPU time 56.07 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:47:01 PM PDT 24
Peak memory 205144 kb
Host smart-a7fcdf2b-a589-4632-a6e7-fb48e4ed5635
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2562040720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2562040720
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3930548413
Short name T31
Test name
Test status
Simulation time 777616916 ps
CPU time 108.57 seconds
Started May 07 12:45:54 PM PDT 24
Finished May 07 12:47:43 PM PDT 24
Peak memory 208400 kb
Host smart-a3756ffc-8115-4f8d-b281-e2c1ec7fe297
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3930548413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3930548413
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2668674026
Short name T590
Test name
Test status
Simulation time 30577114 ps
CPU time 23.55 seconds
Started May 07 12:45:54 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 205784 kb
Host smart-f2aee4f0-d1a8-47db-b362-31bc8875058c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2668674026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.2668674026
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.998591412
Short name T567
Test name
Test status
Simulation time 420329816 ps
CPU time 8.21 seconds
Started May 07 12:45:49 PM PDT 24
Finished May 07 12:45:59 PM PDT 24
Peak memory 204988 kb
Host smart-6676bf0e-a86e-47c6-8a61-c17c21a0462e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=998591412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.998591412
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2022885199
Short name T863
Test name
Test status
Simulation time 567003383 ps
CPU time 23.78 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:46:29 PM PDT 24
Peak memory 204736 kb
Host smart-07627360-21cc-4a37-82b4-ea378b72cc45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2022885199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2022885199
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2227131031
Short name T636
Test name
Test status
Simulation time 24680733092 ps
CPU time 161.92 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:48:43 PM PDT 24
Peak memory 206108 kb
Host smart-cca2ac61-d2d1-4d2c-884f-1988005687dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2227131031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.2227131031
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4261122838
Short name T542
Test name
Test status
Simulation time 307760798 ps
CPU time 9.34 seconds
Started May 07 12:45:57 PM PDT 24
Finished May 07 12:46:07 PM PDT 24
Peak memory 203744 kb
Host smart-24b6c8c2-e85f-47e0-834e-4d40047a2ae5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4261122838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.4261122838
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.1802868255
Short name T633
Test name
Test status
Simulation time 393589638 ps
CPU time 12.97 seconds
Started May 07 12:46:08 PM PDT 24
Finished May 07 12:46:23 PM PDT 24
Peak memory 203412 kb
Host smart-086ad159-2da9-4cf1-b848-4465745e1858
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1802868255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1802868255
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.1258781408
Short name T137
Test name
Test status
Simulation time 317250470 ps
CPU time 10.28 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:46:12 PM PDT 24
Peak memory 204584 kb
Host smart-9a7926c6-71e4-47bf-853f-9a2011651bce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1258781408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1258781408
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.63009459
Short name T585
Test name
Test status
Simulation time 35688590603 ps
CPU time 144.39 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:48:30 PM PDT 24
Peak memory 204740 kb
Host smart-7d8c173f-0e07-49c3-b073-5c2052f6f27a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=63009459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.63009459
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.547616854
Short name T602
Test name
Test status
Simulation time 45437651711 ps
CPU time 143.71 seconds
Started May 07 12:46:01 PM PDT 24
Finished May 07 12:48:27 PM PDT 24
Peak memory 204940 kb
Host smart-54fdc5c3-fdaf-4e25-acb0-5280aee17602
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=547616854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.547616854
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3430851655
Short name T352
Test name
Test status
Simulation time 60982001 ps
CPU time 2.94 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:07 PM PDT 24
Peak memory 203484 kb
Host smart-e10ac405-a5d0-4a20-8bcc-c17565fc851a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430851655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3430851655
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.1594463771
Short name T874
Test name
Test status
Simulation time 241644781 ps
CPU time 14.88 seconds
Started May 07 12:45:56 PM PDT 24
Finished May 07 12:46:13 PM PDT 24
Peak memory 204180 kb
Host smart-fecebcf1-029c-41ae-9a78-609fc2b3af2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1594463771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1594463771
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.1310810086
Short name T480
Test name
Test status
Simulation time 40829268 ps
CPU time 2.15 seconds
Started May 07 12:46:01 PM PDT 24
Finished May 07 12:46:05 PM PDT 24
Peak memory 203464 kb
Host smart-97990469-7170-4e58-8713-c998a04b143c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1310810086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1310810086
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3558188288
Short name T685
Test name
Test status
Simulation time 9937688668 ps
CPU time 31.1 seconds
Started May 07 12:46:00 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 203576 kb
Host smart-87b066ff-b01e-4c82-b7ff-b1a075f0ca96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558188288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3558188288
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2276339302
Short name T249
Test name
Test status
Simulation time 4915901814 ps
CPU time 34.22 seconds
Started May 07 12:45:53 PM PDT 24
Finished May 07 12:46:29 PM PDT 24
Peak memory 203528 kb
Host smart-f1dabf6d-308a-4850-b3e7-ac3f8875dc27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2276339302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2276339302
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2774994105
Short name T876
Test name
Test status
Simulation time 23901929 ps
CPU time 2.32 seconds
Started May 07 12:45:51 PM PDT 24
Finished May 07 12:45:54 PM PDT 24
Peak memory 203580 kb
Host smart-7f8f4ea5-bba8-4fac-b05d-048024b33c2e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774994105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2774994105
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.4197512397
Short name T703
Test name
Test status
Simulation time 823718988 ps
CPU time 51.19 seconds
Started May 07 12:46:00 PM PDT 24
Finished May 07 12:46:54 PM PDT 24
Peak memory 205872 kb
Host smart-b30338de-065e-4ee1-9d06-9f3a0f378e80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4197512397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.4197512397
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2171957008
Short name T372
Test name
Test status
Simulation time 1058721410 ps
CPU time 81.83 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:47:21 PM PDT 24
Peak memory 206396 kb
Host smart-5f214f33-0a6d-406e-b371-e618be6a8725
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2171957008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2171957008
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3468503007
Short name T550
Test name
Test status
Simulation time 418182197 ps
CPU time 134.69 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:48:20 PM PDT 24
Peak memory 208424 kb
Host smart-fc84ff93-ed0b-404c-8496-80d927715bbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3468503007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.3468503007
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1211298391
Short name T696
Test name
Test status
Simulation time 4412099303 ps
CPU time 199.44 seconds
Started May 07 12:46:00 PM PDT 24
Finished May 07 12:49:22 PM PDT 24
Peak memory 211180 kb
Host smart-d8bcf9d2-879f-41d6-9567-ce74da7b1073
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1211298391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1211298391
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3655099772
Short name T260
Test name
Test status
Simulation time 82587280 ps
CPU time 3.78 seconds
Started May 07 12:46:08 PM PDT 24
Finished May 07 12:46:13 PM PDT 24
Peak memory 204660 kb
Host smart-543365c6-360f-4c1c-bb90-0d966ce50f0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3655099772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3655099772
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.204582193
Short name T695
Test name
Test status
Simulation time 2878237342 ps
CPU time 39.69 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:40 PM PDT 24
Peak memory 206156 kb
Host smart-3840960f-6384-48bf-8276-c8a7a723c105
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=204582193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.204582193
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3568892133
Short name T151
Test name
Test status
Simulation time 19973622524 ps
CPU time 188.27 seconds
Started May 07 12:45:57 PM PDT 24
Finished May 07 12:49:07 PM PDT 24
Peak memory 205996 kb
Host smart-cdf77f20-f643-4a2a-b1c9-32aab500c160
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3568892133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.3568892133
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2271409549
Short name T721
Test name
Test status
Simulation time 91148847 ps
CPU time 6.12 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:11 PM PDT 24
Peak memory 203608 kb
Host smart-1d243fc2-0051-4434-bbb7-348fde1ff67b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2271409549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2271409549
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3677994066
Short name T218
Test name
Test status
Simulation time 116900928 ps
CPU time 2.89 seconds
Started May 07 12:46:01 PM PDT 24
Finished May 07 12:46:06 PM PDT 24
Peak memory 203500 kb
Host smart-b3eea5cf-07d0-423c-9873-d5cb8f1d9773
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3677994066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3677994066
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.1306998719
Short name T95
Test name
Test status
Simulation time 1109075781 ps
CPU time 35.22 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:40 PM PDT 24
Peak memory 204916 kb
Host smart-d666cd93-3a7b-4bbf-8511-6097a4f6e8ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1306998719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1306998719
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.794504298
Short name T4
Test name
Test status
Simulation time 3705993655 ps
CPU time 23.21 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:28 PM PDT 24
Peak memory 204112 kb
Host smart-b245d510-fa0f-44dd-880f-0001d380f63c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=794504298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.794504298
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2847754424
Short name T469
Test name
Test status
Simulation time 26284594816 ps
CPU time 114.17 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:47:59 PM PDT 24
Peak memory 204684 kb
Host smart-2a93c5f8-46b1-4a7b-96a9-8b4ea7359844
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2847754424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2847754424
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3338490127
Short name T16
Test name
Test status
Simulation time 105164271 ps
CPU time 12.68 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 204628 kb
Host smart-6905f2b1-5a47-43a1-8c0d-4d3bfb8555ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338490127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3338490127
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.3221713938
Short name T650
Test name
Test status
Simulation time 1483655066 ps
CPU time 20.46 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:25 PM PDT 24
Peak memory 204224 kb
Host smart-a8c4e428-0c4c-4993-b61d-28d79ca205d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3221713938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3221713938
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.3159250942
Short name T69
Test name
Test status
Simulation time 139832163 ps
CPU time 3.94 seconds
Started May 07 12:45:57 PM PDT 24
Finished May 07 12:46:02 PM PDT 24
Peak memory 203444 kb
Host smart-039e6f42-7ff3-4fcf-a5c6-14d3a9e1c0b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3159250942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3159250942
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1877200138
Short name T709
Test name
Test status
Simulation time 6064619731 ps
CPU time 34.08 seconds
Started May 07 12:46:00 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 203560 kb
Host smart-bcda66f5-4758-4044-bd61-fedff846f69d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877200138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1877200138
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3516108357
Short name T797
Test name
Test status
Simulation time 7735664383 ps
CPU time 39.53 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:46:41 PM PDT 24
Peak memory 203716 kb
Host smart-135f7ec9-66d1-440c-b134-142c117db727
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3516108357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3516108357
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1793379100
Short name T431
Test name
Test status
Simulation time 40351082 ps
CPU time 2.35 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203508 kb
Host smart-194c2c6d-b4c9-4eed-9654-9ca90c5643e5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793379100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1793379100
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1490943814
Short name T149
Test name
Test status
Simulation time 12348760125 ps
CPU time 295.54 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:50:59 PM PDT 24
Peak memory 211760 kb
Host smart-91e7a194-6a6d-45c9-aa9b-668a45909115
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1490943814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1490943814
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1254568471
Short name T119
Test name
Test status
Simulation time 2049986143 ps
CPU time 120.05 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:48:04 PM PDT 24
Peak memory 206980 kb
Host smart-b7856208-acd1-40fc-8f12-547136d74f5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1254568471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1254568471
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.928012165
Short name T707
Test name
Test status
Simulation time 8267331352 ps
CPU time 315.14 seconds
Started May 07 12:46:07 PM PDT 24
Finished May 07 12:51:24 PM PDT 24
Peak memory 210880 kb
Host smart-0ffee167-3aa6-4e71-8227-f06a2feae61b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928012165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand
_reset.928012165
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.253438193
Short name T142
Test name
Test status
Simulation time 137497030 ps
CPU time 63.12 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:47:09 PM PDT 24
Peak memory 207260 kb
Host smart-2636587e-2c1d-422c-b518-45aaf40e38ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=253438193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res
et_error.253438193
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.4057570170
Short name T438
Test name
Test status
Simulation time 52012637 ps
CPU time 4.81 seconds
Started May 07 12:45:58 PM PDT 24
Finished May 07 12:46:04 PM PDT 24
Peak memory 204508 kb
Host smart-698763b0-7816-43f4-9f8e-498fc5ea759b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4057570170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4057570170
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1943967004
Short name T688
Test name
Test status
Simulation time 2537495915 ps
CPU time 36.8 seconds
Started May 07 12:46:00 PM PDT 24
Finished May 07 12:46:39 PM PDT 24
Peak memory 211740 kb
Host smart-c9eea42b-86fa-4c51-b164-7a7c62c9cad8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1943967004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1943967004
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3877183207
Short name T742
Test name
Test status
Simulation time 79075308641 ps
CPU time 247.15 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:50:11 PM PDT 24
Peak memory 206404 kb
Host smart-0c382b78-1339-4303-89f2-cbb703947cb1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3877183207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.3877183207
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.916725267
Short name T846
Test name
Test status
Simulation time 72880585 ps
CPU time 10.03 seconds
Started May 07 12:46:10 PM PDT 24
Finished May 07 12:46:21 PM PDT 24
Peak memory 203816 kb
Host smart-a1980fcc-797c-49a9-85aa-b6745c0998b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=916725267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.916725267
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2008464572
Short name T607
Test name
Test status
Simulation time 23173446 ps
CPU time 2.83 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 203468 kb
Host smart-288d810d-2b6f-49f4-a695-37ac637a97af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2008464572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2008464572
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.2124050073
Short name T665
Test name
Test status
Simulation time 856909154 ps
CPU time 28.95 seconds
Started May 07 12:46:00 PM PDT 24
Finished May 07 12:46:31 PM PDT 24
Peak memory 204920 kb
Host smart-8a1e49d1-3dc8-446d-8d6a-711e0e09179c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2124050073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2124050073
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3029023442
Short name T898
Test name
Test status
Simulation time 46281785568 ps
CPU time 192.27 seconds
Started May 07 12:46:07 PM PDT 24
Finished May 07 12:49:20 PM PDT 24
Peak memory 204652 kb
Host smart-c2ea6c20-3ee9-4711-bf89-3f6119023001
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029023442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3029023442
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.97626623
Short name T584
Test name
Test status
Simulation time 159301704253 ps
CPU time 259.29 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:50:24 PM PDT 24
Peak memory 205428 kb
Host smart-5b7f56c0-8fa7-4192-8620-639bf34fda83
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=97626623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.97626623
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2714890519
Short name T48
Test name
Test status
Simulation time 194598799 ps
CPU time 19.58 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:24 PM PDT 24
Peak memory 204732 kb
Host smart-56b57af6-c9d3-4213-9baa-a186ce59f20f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714890519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2714890519
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.684042499
Short name T296
Test name
Test status
Simulation time 324223848 ps
CPU time 19.49 seconds
Started May 07 12:46:07 PM PDT 24
Finished May 07 12:46:28 PM PDT 24
Peak memory 203556 kb
Host smart-33fb23ee-f4d8-4d29-bd7c-eb05ab9389d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=684042499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.684042499
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.1590371901
Short name T730
Test name
Test status
Simulation time 405872090 ps
CPU time 3.38 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:46:05 PM PDT 24
Peak memory 203636 kb
Host smart-a47ffcf4-2b33-42f3-97d7-6efdd08bdf30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1590371901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1590371901
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.149259420
Short name T301
Test name
Test status
Simulation time 22249248009 ps
CPU time 30.91 seconds
Started May 07 12:46:01 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 203552 kb
Host smart-94748c4e-0f91-43a0-b5ed-9db280dc5e9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=149259420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.149259420
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3354288468
Short name T138
Test name
Test status
Simulation time 7156253988 ps
CPU time 31.01 seconds
Started May 07 12:46:02 PM PDT 24
Finished May 07 12:46:35 PM PDT 24
Peak memory 203508 kb
Host smart-a1c95169-526b-4898-a7e1-1cfdbd6a85ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3354288468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3354288468
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1710304393
Short name T364
Test name
Test status
Simulation time 45461377 ps
CPU time 2.21 seconds
Started May 07 12:45:59 PM PDT 24
Finished May 07 12:46:03 PM PDT 24
Peak memory 203580 kb
Host smart-93efb2d9-2c49-4d68-b8d0-e56c7e5d710a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710304393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1710304393
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.457404577
Short name T160
Test name
Test status
Simulation time 2869156943 ps
CPU time 58.88 seconds
Started May 07 12:46:09 PM PDT 24
Finished May 07 12:47:09 PM PDT 24
Peak memory 207996 kb
Host smart-11ecb955-56a9-40d5-9422-f6f270324471
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=457404577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.457404577
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.929872251
Short name T315
Test name
Test status
Simulation time 2159858742 ps
CPU time 98.51 seconds
Started May 07 12:46:05 PM PDT 24
Finished May 07 12:47:45 PM PDT 24
Peak memory 206640 kb
Host smart-b1848639-bae1-428d-a738-dd051a3b559b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=929872251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.929872251
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.839081039
Short name T284
Test name
Test status
Simulation time 211591292 ps
CPU time 62.09 seconds
Started May 07 12:46:05 PM PDT 24
Finished May 07 12:47:08 PM PDT 24
Peak memory 207016 kb
Host smart-d63a3dab-d266-4b59-bc5c-e54136d9d2b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=839081039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand
_reset.839081039
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1548739263
Short name T496
Test name
Test status
Simulation time 916707877 ps
CPU time 29.81 seconds
Started May 07 12:46:05 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 204772 kb
Host smart-22113e39-db2f-4a80-87ea-6c2330b05929
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1548739263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1548739263
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.931966635
Short name T611
Test name
Test status
Simulation time 371728232 ps
CPU time 41.8 seconds
Started May 07 12:46:09 PM PDT 24
Finished May 07 12:46:52 PM PDT 24
Peak memory 206636 kb
Host smart-a90d7ac1-e369-43e6-a5e1-32f23710063a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=931966635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.931966635
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1174678787
Short name T163
Test name
Test status
Simulation time 115056347623 ps
CPU time 616.18 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:56:22 PM PDT 24
Peak memory 206132 kb
Host smart-f41d9305-abe6-4b18-ba6d-b6decc53ed56
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1174678787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1174678787
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.935248078
Short name T737
Test name
Test status
Simulation time 104561889 ps
CPU time 10.71 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 203824 kb
Host smart-6c4103ce-c503-4519-a3e2-3e8897d35b8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=935248078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.935248078
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.2060747397
Short name T784
Test name
Test status
Simulation time 185576965 ps
CPU time 16.71 seconds
Started May 07 12:46:06 PM PDT 24
Finished May 07 12:46:24 PM PDT 24
Peak memory 203544 kb
Host smart-80ed9a09-81ee-473b-a042-99765f71e307
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2060747397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2060747397
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.2549374943
Short name T250
Test name
Test status
Simulation time 388620649 ps
CPU time 11.35 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 211572 kb
Host smart-0eeb4b5f-d4fb-42c5-b788-9f09f9802954
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2549374943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2549374943
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.473885024
Short name T60
Test name
Test status
Simulation time 58553861784 ps
CPU time 166.04 seconds
Started May 07 12:46:08 PM PDT 24
Finished May 07 12:48:55 PM PDT 24
Peak memory 204608 kb
Host smart-4c228c1c-c640-4019-8ff8-08ceed5f3b26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=473885024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.473885024
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.879901746
Short name T266
Test name
Test status
Simulation time 17101809658 ps
CPU time 133.38 seconds
Started May 07 12:46:03 PM PDT 24
Finished May 07 12:48:18 PM PDT 24
Peak memory 205100 kb
Host smart-097d86e3-fd1b-46c7-90ea-6de6f6fa2a88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=879901746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.879901746
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2981921823
Short name T843
Test name
Test status
Simulation time 232541546 ps
CPU time 22.76 seconds
Started May 07 12:46:09 PM PDT 24
Finished May 07 12:46:33 PM PDT 24
Peak memory 204604 kb
Host smart-31223c6b-2030-47a0-8603-e8bf70a1d361
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981921823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2981921823
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.652551408
Short name T223
Test name
Test status
Simulation time 3056487870 ps
CPU time 28.97 seconds
Started May 07 12:46:05 PM PDT 24
Finished May 07 12:46:35 PM PDT 24
Peak memory 203628 kb
Host smart-409dd774-ff3f-46fd-8942-25b73819860a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=652551408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.652551408
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.1931509634
Short name T199
Test name
Test status
Simulation time 31550382 ps
CPU time 2.16 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:46:08 PM PDT 24
Peak memory 203456 kb
Host smart-e7d04338-6860-43b5-94d9-f8c82d5b9d10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1931509634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1931509634
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3507884192
Short name T269
Test name
Test status
Simulation time 5969620174 ps
CPU time 36.2 seconds
Started May 07 12:46:06 PM PDT 24
Finished May 07 12:46:44 PM PDT 24
Peak memory 203536 kb
Host smart-bb08a1d6-bbba-4a01-a22e-25765bf884f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507884192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3507884192
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.4080491128
Short name T576
Test name
Test status
Simulation time 19076571389 ps
CPU time 32.95 seconds
Started May 07 12:46:05 PM PDT 24
Finished May 07 12:46:40 PM PDT 24
Peak memory 203540 kb
Host smart-d80bec31-5a42-4861-be7b-2ddb764382be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4080491128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4080491128
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3723805138
Short name T520
Test name
Test status
Simulation time 115794221 ps
CPU time 2.04 seconds
Started May 07 12:46:07 PM PDT 24
Finished May 07 12:46:11 PM PDT 24
Peak memory 203500 kb
Host smart-ebb82196-b586-40f4-9099-a69564b57f20
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723805138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3723805138
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3240784419
Short name T90
Test name
Test status
Simulation time 4928696939 ps
CPU time 109.41 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:48:04 PM PDT 24
Peak memory 211736 kb
Host smart-0bc4cc8f-b8e5-448d-a81a-f6ebfe771419
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3240784419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3240784419
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.755576890
Short name T649
Test name
Test status
Simulation time 531155222 ps
CPU time 35.2 seconds
Started May 07 12:46:07 PM PDT 24
Finished May 07 12:46:43 PM PDT 24
Peak memory 204668 kb
Host smart-ae12a05b-dba6-4456-a846-4d21eea3e5a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=755576890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.755576890
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3035048675
Short name T115
Test name
Test status
Simulation time 7746843272 ps
CPU time 192.86 seconds
Started May 07 12:46:08 PM PDT 24
Finished May 07 12:49:22 PM PDT 24
Peak memory 208624 kb
Host smart-a9819142-2c55-4f44-b04a-bd97f453deec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3035048675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.3035048675
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2107591709
Short name T853
Test name
Test status
Simulation time 2292955506 ps
CPU time 335.37 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:51:41 PM PDT 24
Peak memory 219956 kb
Host smart-e559450c-97f2-48bd-84a1-d214c902f3f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2107591709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.2107591709
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1697472129
Short name T422
Test name
Test status
Simulation time 184815557 ps
CPU time 13.73 seconds
Started May 07 12:46:08 PM PDT 24
Finished May 07 12:46:23 PM PDT 24
Peak memory 211572 kb
Host smart-df3f18b9-5c69-493d-8082-140877354573
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1697472129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1697472129
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.323153973
Short name T17
Test name
Test status
Simulation time 2416658718 ps
CPU time 73.11 seconds
Started May 07 12:46:08 PM PDT 24
Finished May 07 12:47:22 PM PDT 24
Peak memory 206656 kb
Host smart-d05f8051-2df8-4792-81f6-33eb789823b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=323153973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.323153973
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.451003334
Short name T847
Test name
Test status
Simulation time 115055164394 ps
CPU time 447.63 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:53:42 PM PDT 24
Peak memory 207112 kb
Host smart-2c681b3c-da62-4620-a914-d84cc6ff1687
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=451003334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slo
w_rsp.451003334
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1253081119
Short name T122
Test name
Test status
Simulation time 63489927 ps
CPU time 3.59 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 203600 kb
Host smart-fecf54b6-f61c-4e46-8294-e1f21d5d9c45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1253081119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1253081119
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2181594267
Short name T471
Test name
Test status
Simulation time 139188364 ps
CPU time 4.32 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 203420 kb
Host smart-8ab254b4-b3fe-438e-a36e-f3eed353364d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2181594267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2181594267
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3821571812
Short name T430
Test name
Test status
Simulation time 232270243 ps
CPU time 24.05 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:38 PM PDT 24
Peak memory 211676 kb
Host smart-0e17434d-e850-4294-a4c1-0cb1051a69fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3821571812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3821571812
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2815700572
Short name T601
Test name
Test status
Simulation time 66372398881 ps
CPU time 239.52 seconds
Started May 07 12:46:06 PM PDT 24
Finished May 07 12:50:07 PM PDT 24
Peak memory 205388 kb
Host smart-94b81b79-fa7e-4ee6-9e20-edd43b9711b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815700572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2815700572
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1506020458
Short name T335
Test name
Test status
Simulation time 10304210600 ps
CPU time 46.28 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:47:01 PM PDT 24
Peak memory 204792 kb
Host smart-45446a83-f981-4e6a-9251-74f43cce18c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1506020458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1506020458
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.715251143
Short name T365
Test name
Test status
Simulation time 98602364 ps
CPU time 10.17 seconds
Started May 07 12:46:05 PM PDT 24
Finished May 07 12:46:17 PM PDT 24
Peak memory 204768 kb
Host smart-a98802a3-47e9-4963-a383-5b74a0e86a8d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715251143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.715251143
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.805807002
Short name T759
Test name
Test status
Simulation time 295642010 ps
CPU time 18.49 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:32 PM PDT 24
Peak memory 203548 kb
Host smart-a3516ebc-a636-4659-8eab-8fbf4ec8190a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=805807002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.805807002
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.688704997
Short name T761
Test name
Test status
Simulation time 33260643 ps
CPU time 2.24 seconds
Started May 07 12:46:08 PM PDT 24
Finished May 07 12:46:12 PM PDT 24
Peak memory 203388 kb
Host smart-570ba78a-f05e-40c1-aed9-55c321c09e89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=688704997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.688704997
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3326389453
Short name T564
Test name
Test status
Simulation time 6152372943 ps
CPU time 32.2 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:46:37 PM PDT 24
Peak memory 203564 kb
Host smart-f1f8d216-ebb7-4810-aead-b041771001be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326389453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3326389453
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.570633206
Short name T258
Test name
Test status
Simulation time 3405980154 ps
CPU time 33.68 seconds
Started May 07 12:46:04 PM PDT 24
Finished May 07 12:46:40 PM PDT 24
Peak memory 203536 kb
Host smart-42f2a633-4480-46a7-8764-4879a4b84786
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=570633206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.570633206
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2263301764
Short name T435
Test name
Test status
Simulation time 40377611 ps
CPU time 2.43 seconds
Started May 07 12:46:10 PM PDT 24
Finished May 07 12:46:13 PM PDT 24
Peak memory 203508 kb
Host smart-0b5bed84-dba0-4697-8f89-6b55176bbedd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263301764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2263301764
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1856810532
Short name T89
Test name
Test status
Simulation time 4508543317 ps
CPU time 48.49 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:47:02 PM PDT 24
Peak memory 206572 kb
Host smart-6e86c462-2f02-415c-889d-470fef82712e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1856810532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1856810532
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2101454553
Short name T259
Test name
Test status
Simulation time 3815310872 ps
CPU time 76.99 seconds
Started May 07 12:46:10 PM PDT 24
Finished May 07 12:47:28 PM PDT 24
Peak memory 206208 kb
Host smart-af42e3d4-af1e-4f0e-bceb-10c936d926d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2101454553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2101454553
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.346989038
Short name T612
Test name
Test status
Simulation time 89157685 ps
CPU time 20.17 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:33 PM PDT 24
Peak memory 205916 kb
Host smart-dea0c110-afea-4c22-9bfa-bb8daab57220
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=346989038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand
_reset.346989038
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3633810458
Short name T23
Test name
Test status
Simulation time 4153324768 ps
CPU time 226.78 seconds
Started May 07 12:46:13 PM PDT 24
Finished May 07 12:50:02 PM PDT 24
Peak memory 211708 kb
Host smart-4ea8da30-c835-4cdf-bb0a-31a0d852222c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3633810458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3633810458
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.729577971
Short name T600
Test name
Test status
Simulation time 42191805 ps
CPU time 5.26 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:19 PM PDT 24
Peak memory 211708 kb
Host smart-34f966c9-6555-4d22-a7f5-91c4de6179c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=729577971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.729577971
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3517063066
Short name T256
Test name
Test status
Simulation time 179794937 ps
CPU time 22.9 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:37 PM PDT 24
Peak memory 204324 kb
Host smart-46222cb7-4911-4a5d-b518-7c7823fc86ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3517063066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3517063066
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1367847647
Short name T227
Test name
Test status
Simulation time 57964833843 ps
CPU time 147.45 seconds
Started May 07 12:46:14 PM PDT 24
Finished May 07 12:48:43 PM PDT 24
Peak memory 206208 kb
Host smart-1f704a54-00cb-4ebf-8e4a-783039e641da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1367847647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.1367847647
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2272561281
Short name T753
Test name
Test status
Simulation time 1641348372 ps
CPU time 17.31 seconds
Started May 07 12:46:10 PM PDT 24
Finished May 07 12:46:29 PM PDT 24
Peak memory 203712 kb
Host smart-27683f99-685c-490e-aad6-b1e5029c5387
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2272561281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2272561281
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.3672245008
Short name T351
Test name
Test status
Simulation time 2049380242 ps
CPU time 25.41 seconds
Started May 07 12:46:10 PM PDT 24
Finished May 07 12:46:37 PM PDT 24
Peak memory 203516 kb
Host smart-852eea77-42e2-4c38-a6df-def3aa399139
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3672245008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3672245008
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.3916268798
Short name T860
Test name
Test status
Simulation time 991649879 ps
CPU time 35.3 seconds
Started May 07 12:46:11 PM PDT 24
Finished May 07 12:46:47 PM PDT 24
Peak memory 211668 kb
Host smart-1374c284-661e-4b35-8ca0-11a31cd9e2f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3916268798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3916268798
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.969311707
Short name T251
Test name
Test status
Simulation time 115616992824 ps
CPU time 247.27 seconds
Started May 07 12:46:13 PM PDT 24
Finished May 07 12:50:22 PM PDT 24
Peak memory 204840 kb
Host smart-0248b696-27b6-4ff9-ac67-23024283b94c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=969311707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.969311707
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2799401899
Short name T133
Test name
Test status
Simulation time 44325052865 ps
CPU time 198.19 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:49:32 PM PDT 24
Peak memory 205400 kb
Host smart-8ecb31a1-fb87-460f-96fc-3f23059b68a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2799401899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2799401899
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.4188598771
Short name T510
Test name
Test status
Simulation time 82095875 ps
CPU time 11.95 seconds
Started May 07 12:46:14 PM PDT 24
Finished May 07 12:46:27 PM PDT 24
Peak memory 204688 kb
Host smart-d698e9eb-2a00-4a21-a4f5-34f4ac1d2b04
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188598771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.4188598771
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.2165274598
Short name T546
Test name
Test status
Simulation time 437861453 ps
CPU time 5.28 seconds
Started May 07 12:46:14 PM PDT 24
Finished May 07 12:46:21 PM PDT 24
Peak memory 203512 kb
Host smart-eaf0de25-a304-4962-9e35-89cefc2a1156
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2165274598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2165274598
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.4071763077
Short name T569
Test name
Test status
Simulation time 453394775 ps
CPU time 3.48 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:16 PM PDT 24
Peak memory 203436 kb
Host smart-195eec55-412c-40e1-b346-9b9ef9f2b2fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4071763077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.4071763077
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3993956614
Short name T306
Test name
Test status
Simulation time 7009131781 ps
CPU time 29.84 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:44 PM PDT 24
Peak memory 203564 kb
Host smart-56b1e0a1-b6d3-4f20-a18e-5bac5c86b5b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993956614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3993956614
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3168137224
Short name T826
Test name
Test status
Simulation time 22710472962 ps
CPU time 54.35 seconds
Started May 07 12:46:11 PM PDT 24
Finished May 07 12:47:07 PM PDT 24
Peak memory 203552 kb
Host smart-b9ab616c-34c9-453c-9e62-98f020a12431
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3168137224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3168137224
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2360437512
Short name T427
Test name
Test status
Simulation time 24419583 ps
CPU time 1.92 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:15 PM PDT 24
Peak memory 203508 kb
Host smart-b7c02763-01bf-43c6-887b-7c45f7aeac4a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360437512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2360437512
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3251209625
Short name T19
Test name
Test status
Simulation time 7613764035 ps
CPU time 169.66 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:49:04 PM PDT 24
Peak memory 208768 kb
Host smart-df529c4f-bf6e-4f13-a744-7bb4eb50867f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3251209625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3251209625
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1607775298
Short name T332
Test name
Test status
Simulation time 1704689036 ps
CPU time 111.98 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:48:05 PM PDT 24
Peak memory 211664 kb
Host smart-68156ae9-1009-4ab3-b1f1-bbde333bd7c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1607775298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1607775298
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.47738577
Short name T248
Test name
Test status
Simulation time 5323860060 ps
CPU time 306.49 seconds
Started May 07 12:46:13 PM PDT 24
Finished May 07 12:51:22 PM PDT 24
Peak memory 210256 kb
Host smart-ce5225d2-d16a-4e2b-8477-e9a338cd0c32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47738577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_
reset.47738577
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.766571191
Short name T361
Test name
Test status
Simulation time 337617611 ps
CPU time 90.48 seconds
Started May 07 12:46:11 PM PDT 24
Finished May 07 12:47:43 PM PDT 24
Peak memory 208464 kb
Host smart-550852a0-1da7-43a7-a362-8e51c600eca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=766571191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.766571191
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1002293685
Short name T807
Test name
Test status
Simulation time 707882226 ps
CPU time 24.58 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:39 PM PDT 24
Peak memory 205256 kb
Host smart-33c16d10-43c9-4a6a-821d-13d5fb6533b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002293685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1002293685
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2554481111
Short name T129
Test name
Test status
Simulation time 1705569464 ps
CPU time 58.79 seconds
Started May 07 12:44:40 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 206164 kb
Host smart-d12c161c-6271-460d-8a7f-41bcaee3a760
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2554481111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2554481111
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.164841250
Short name T669
Test name
Test status
Simulation time 28495811742 ps
CPU time 274.01 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:49:13 PM PDT 24
Peak memory 211756 kb
Host smart-63e08500-35ef-4a1e-9ab7-c3d5b60facbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=164841250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow
_rsp.164841250
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.90133349
Short name T398
Test name
Test status
Simulation time 1143963632 ps
CPU time 22.32 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:45:00 PM PDT 24
Peak memory 204064 kb
Host smart-075aca7d-8027-4330-b202-6cef62c0557a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=90133349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.90133349
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3480960279
Short name T170
Test name
Test status
Simulation time 1146640293 ps
CPU time 33.45 seconds
Started May 07 12:45:02 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 203600 kb
Host smart-e7a5e085-4189-4e8d-806a-b85104bec24d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3480960279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3480960279
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.3273533405
Short name T556
Test name
Test status
Simulation time 171818916 ps
CPU time 15.28 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:45:10 PM PDT 24
Peak memory 204604 kb
Host smart-b61360dd-7062-4e74-b119-147ffbfcec4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3273533405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3273533405
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3178373593
Short name T187
Test name
Test status
Simulation time 41212429251 ps
CPU time 153.87 seconds
Started May 07 12:44:37 PM PDT 24
Finished May 07 12:47:13 PM PDT 24
Peak memory 204912 kb
Host smart-47bbfb1b-2ec1-425b-b7d8-cfeb834fa5ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178373593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3178373593
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2577029397
Short name T691
Test name
Test status
Simulation time 6399661723 ps
CPU time 45.26 seconds
Started May 07 12:44:45 PM PDT 24
Finished May 07 12:45:31 PM PDT 24
Peak memory 211568 kb
Host smart-303705c0-4130-4896-b988-8e54892dba2c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2577029397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2577029397
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2428125688
Short name T299
Test name
Test status
Simulation time 343494506 ps
CPU time 18.17 seconds
Started May 07 12:44:47 PM PDT 24
Finished May 07 12:45:06 PM PDT 24
Peak memory 204788 kb
Host smart-c9df5f95-2fe9-444b-b725-c48cb8f54522
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428125688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2428125688
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.3619846067
Short name T235
Test name
Test status
Simulation time 1336255249 ps
CPU time 17.65 seconds
Started May 07 12:44:49 PM PDT 24
Finished May 07 12:45:08 PM PDT 24
Peak memory 203568 kb
Host smart-780ae724-ad79-425b-827e-c95fcdbd2c0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3619846067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3619846067
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1241575399
Short name T457
Test name
Test status
Simulation time 103455974 ps
CPU time 2.18 seconds
Started May 07 12:44:37 PM PDT 24
Finished May 07 12:44:41 PM PDT 24
Peak memory 203472 kb
Host smart-7982f91a-41e7-47a1-a333-324c8fd126e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1241575399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1241575399
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1598509250
Short name T54
Test name
Test status
Simulation time 7009337752 ps
CPU time 26.31 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:45:08 PM PDT 24
Peak memory 203556 kb
Host smart-e780c684-6ad4-40f9-98d1-48008d10ae18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598509250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1598509250
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3504977132
Short name T333
Test name
Test status
Simulation time 3849097587 ps
CPU time 32.49 seconds
Started May 07 12:44:37 PM PDT 24
Finished May 07 12:45:12 PM PDT 24
Peak memory 203540 kb
Host smart-a2d08442-bfb4-4a6c-a876-167265b12524
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3504977132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3504977132
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3094962924
Short name T537
Test name
Test status
Simulation time 41891304 ps
CPU time 2.36 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 203480 kb
Host smart-c42b1100-fe3d-43ca-ba79-001ed7b86567
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094962924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3094962924
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3885434120
Short name T896
Test name
Test status
Simulation time 4342339552 ps
CPU time 99.92 seconds
Started May 07 12:44:46 PM PDT 24
Finished May 07 12:46:27 PM PDT 24
Peak memory 209580 kb
Host smart-5a9121d4-a0de-4501-aa69-d79a3eddbb8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3885434120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3885434120
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1008056022
Short name T682
Test name
Test status
Simulation time 3276992162 ps
CPU time 81.26 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:45:56 PM PDT 24
Peak memory 206400 kb
Host smart-735a635d-1a15-4961-89cf-a4d7bfd33320
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1008056022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1008056022
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2441797788
Short name T683
Test name
Test status
Simulation time 4164054048 ps
CPU time 139.66 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:47:02 PM PDT 24
Peak memory 208672 kb
Host smart-c33eaf5a-645e-44e9-a102-2ca75a662a69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2441797788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.2441797788
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2304649382
Short name T26
Test name
Test status
Simulation time 10936304911 ps
CPU time 218.52 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:48:34 PM PDT 24
Peak memory 211760 kb
Host smart-6c1c2c16-c90f-49f7-8edc-7e03e8958319
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2304649382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.2304649382
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3550116569
Short name T575
Test name
Test status
Simulation time 491197131 ps
CPU time 20.13 seconds
Started May 07 12:44:42 PM PDT 24
Finished May 07 12:45:03 PM PDT 24
Peak memory 205128 kb
Host smart-990dc7f9-b6d5-46a1-aae6-13582615ea0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3550116569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3550116569
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3488756303
Short name T706
Test name
Test status
Simulation time 1171399530 ps
CPU time 21.42 seconds
Started May 07 12:46:13 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 205600 kb
Host smart-ac9d833f-8607-43e9-b215-ba98a1304287
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3488756303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3488756303
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4033019580
Short name T562
Test name
Test status
Simulation time 437234724 ps
CPU time 16.64 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:46:38 PM PDT 24
Peak memory 203940 kb
Host smart-614596bc-cd90-4e17-b0ac-0c8760ab3887
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4033019580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4033019580
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2060429543
Short name T582
Test name
Test status
Simulation time 849115153 ps
CPU time 17.6 seconds
Started May 07 12:46:11 PM PDT 24
Finished May 07 12:46:30 PM PDT 24
Peak memory 203496 kb
Host smart-f8831d2e-52bf-419b-b9dc-66f98ddfd6bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2060429543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2060429543
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.1558520707
Short name T87
Test name
Test status
Simulation time 3418261130 ps
CPU time 40.31 seconds
Started May 07 12:46:14 PM PDT 24
Finished May 07 12:46:56 PM PDT 24
Peak memory 205156 kb
Host smart-fbaf167f-aef5-43c7-a70c-7a1a48432411
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1558520707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1558520707
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2844908959
Short name T508
Test name
Test status
Simulation time 36935507010 ps
CPU time 190.38 seconds
Started May 07 12:46:13 PM PDT 24
Finished May 07 12:49:25 PM PDT 24
Peak memory 204720 kb
Host smart-6aa25d13-34e6-471a-b4fd-1946a8658f0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844908959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2844908959
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.148835543
Short name T820
Test name
Test status
Simulation time 2537951991 ps
CPU time 24.37 seconds
Started May 07 12:46:10 PM PDT 24
Finished May 07 12:46:35 PM PDT 24
Peak memory 204148 kb
Host smart-d3370f7a-53a5-4e1e-9b4c-8bc2c407cf95
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=148835543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.148835543
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2539848142
Short name T143
Test name
Test status
Simulation time 239903565 ps
CPU time 19.39 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 204516 kb
Host smart-cda56cf9-93c3-4707-a31a-4a172be025df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539848142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2539848142
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2596589654
Short name T488
Test name
Test status
Simulation time 507427414 ps
CPU time 10.13 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:23 PM PDT 24
Peak memory 204176 kb
Host smart-0e94fbd8-9f36-49da-972b-53ddb0dfffee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2596589654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2596589654
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.3793554214
Short name T580
Test name
Test status
Simulation time 24387459 ps
CPU time 2.25 seconds
Started May 07 12:46:14 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 203492 kb
Host smart-5ecf1995-c283-466b-ae18-a12468ab693d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3793554214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3793554214
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1417291620
Short name T302
Test name
Test status
Simulation time 3270187415 ps
CPU time 21.36 seconds
Started May 07 12:46:11 PM PDT 24
Finished May 07 12:46:33 PM PDT 24
Peak memory 203352 kb
Host smart-ebd96d86-5e1a-46e2-8039-3f781ffb0bb4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417291620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1417291620
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1240320848
Short name T835
Test name
Test status
Simulation time 9496265722 ps
CPU time 39.91 seconds
Started May 07 12:46:12 PM PDT 24
Finished May 07 12:46:54 PM PDT 24
Peak memory 203540 kb
Host smart-c38287cf-b264-4b49-9fef-69a9a693a831
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1240320848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1240320848
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2900152822
Short name T294
Test name
Test status
Simulation time 50674275 ps
CPU time 2.51 seconds
Started May 07 12:46:13 PM PDT 24
Finished May 07 12:46:18 PM PDT 24
Peak memory 203508 kb
Host smart-cf2085d3-911c-4e0e-8d4b-13d86ae5f93a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900152822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2900152822
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.930156208
Short name T538
Test name
Test status
Simulation time 10107862221 ps
CPU time 304.91 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:51:29 PM PDT 24
Peak memory 211760 kb
Host smart-4dfa03d2-bfdd-47b4-a878-893474f9dee4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=930156208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.930156208
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3251378264
Short name T561
Test name
Test status
Simulation time 7723653 ps
CPU time 1.91 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:46:25 PM PDT 24
Peak memory 203276 kb
Host smart-8b2e85bb-f5aa-41eb-8bcd-a21452a7d0ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3251378264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.3251378264
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.763942437
Short name T225
Test name
Test status
Simulation time 143968683 ps
CPU time 61.41 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:47:21 PM PDT 24
Peak memory 206780 kb
Host smart-b6fae6b5-87c8-4438-bbc0-a686e79e2ffb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=763942437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res
et_error.763942437
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.671017794
Short name T674
Test name
Test status
Simulation time 617852054 ps
CPU time 14.8 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 211688 kb
Host smart-b8b88507-b4b2-4d0d-9303-3c84f5ac5056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=671017794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.671017794
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1645645749
Short name T660
Test name
Test status
Simulation time 1937052836 ps
CPU time 48.87 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:47:09 PM PDT 24
Peak memory 206292 kb
Host smart-de31a0b1-de5d-4505-8016-423da142b9fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1645645749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1645645749
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3008614086
Short name T728
Test name
Test status
Simulation time 14247823691 ps
CPU time 83.77 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:47:44 PM PDT 24
Peak memory 205612 kb
Host smart-22ad2889-35c0-433e-8da4-c803d0ce5d6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3008614086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.3008614086
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1540161766
Short name T14
Test name
Test status
Simulation time 1024136184 ps
CPU time 22.88 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:46:47 PM PDT 24
Peak memory 203704 kb
Host smart-1d943240-aecc-4105-a36d-7fe3010cc991
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1540161766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1540161766
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.2772544832
Short name T641
Test name
Test status
Simulation time 85937631 ps
CPU time 10.8 seconds
Started May 07 12:46:21 PM PDT 24
Finished May 07 12:46:34 PM PDT 24
Peak memory 203524 kb
Host smart-3442aaca-9f5b-4856-8b1d-1cabfa78733a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2772544832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2772544832
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.3978298325
Short name T747
Test name
Test status
Simulation time 4328990565 ps
CPU time 31.44 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:46:53 PM PDT 24
Peak memory 204984 kb
Host smart-0ea0c813-2b3f-417c-ad1d-d6ba77f7b346
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3978298325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3978298325
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3625494695
Short name T586
Test name
Test status
Simulation time 13081971230 ps
CPU time 52.63 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:47:13 PM PDT 24
Peak memory 204920 kb
Host smart-71514b73-c71e-489a-91ae-2fbfc20c8f1d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625494695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3625494695
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1190384955
Short name T509
Test name
Test status
Simulation time 22329868387 ps
CPU time 152.92 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:48:54 PM PDT 24
Peak memory 211716 kb
Host smart-8882a8f5-b202-4862-9f7b-d6c1cd3e498e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1190384955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1190384955
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2243796300
Short name T78
Test name
Test status
Simulation time 181976038 ps
CPU time 14.68 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 204636 kb
Host smart-11e188c9-60f2-4fd9-b9f8-3c43993a77e9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243796300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2243796300
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.2786833565
Short name T743
Test name
Test status
Simulation time 257435591 ps
CPU time 6.14 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:46:25 PM PDT 24
Peak memory 203608 kb
Host smart-132669dd-3351-4d9a-87e3-84b829c734c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2786833565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2786833565
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.3239827788
Short name T234
Test name
Test status
Simulation time 226825034 ps
CPU time 3.26 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:46:24 PM PDT 24
Peak memory 203388 kb
Host smart-7c286c21-9e89-468b-bd99-9e15491b1297
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3239827788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3239827788
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2431450291
Short name T226
Test name
Test status
Simulation time 29900137147 ps
CPU time 43.65 seconds
Started May 07 12:46:21 PM PDT 24
Finished May 07 12:47:06 PM PDT 24
Peak memory 203560 kb
Host smart-4adc873d-5144-4d96-a143-c5d2f93f8416
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431450291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2431450291
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1706326418
Short name T222
Test name
Test status
Simulation time 8432175898 ps
CPU time 36.34 seconds
Started May 07 12:46:21 PM PDT 24
Finished May 07 12:46:59 PM PDT 24
Peak memory 203556 kb
Host smart-ffe0b559-c073-457f-af1e-8e1e08099b2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1706326418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1706326418
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2660262800
Short name T767
Test name
Test status
Simulation time 29114428 ps
CPU time 2.07 seconds
Started May 07 12:46:26 PM PDT 24
Finished May 07 12:46:30 PM PDT 24
Peak memory 203504 kb
Host smart-cd4cead2-a694-4a07-8569-16041a5acbec
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660262800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2660262800
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1732304005
Short name T484
Test name
Test status
Simulation time 985043493 ps
CPU time 65.46 seconds
Started May 07 12:46:21 PM PDT 24
Finished May 07 12:47:29 PM PDT 24
Peak memory 207992 kb
Host smart-fc5ab6bb-f704-41a0-8c36-a3bd3b3083e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1732304005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1732304005
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3835446104
Short name T878
Test name
Test status
Simulation time 2992434132 ps
CPU time 84.44 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:47:47 PM PDT 24
Peak memory 205312 kb
Host smart-9e321705-2fdf-48c9-a112-1b5623a73f7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3835446104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3835446104
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3501524302
Short name T24
Test name
Test status
Simulation time 5309630738 ps
CPU time 245.84 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:50:29 PM PDT 24
Peak memory 211676 kb
Host smart-ac5aabc6-31eb-43a2-ad89-979732f5886f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3501524302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3501524302
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2212301072
Short name T165
Test name
Test status
Simulation time 9953457129 ps
CPU time 183.93 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:49:25 PM PDT 24
Peak memory 211768 kb
Host smart-07a650d5-8680-46c7-8727-b41136e02ebf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2212301072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2212301072
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1720642227
Short name T592
Test name
Test status
Simulation time 343504696 ps
CPU time 6.75 seconds
Started May 07 12:46:21 PM PDT 24
Finished May 07 12:46:29 PM PDT 24
Peak memory 204796 kb
Host smart-468dac52-ef63-440e-af59-33429b91252f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1720642227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1720642227
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1940068743
Short name T169
Test name
Test status
Simulation time 2985297998 ps
CPU time 61.93 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:47:22 PM PDT 24
Peak memory 206228 kb
Host smart-c003f28f-ca69-4c8a-a5a0-3f503d0fa86d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1940068743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1940068743
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3841588507
Short name T211
Test name
Test status
Simulation time 40239191583 ps
CPU time 245.57 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:50:29 PM PDT 24
Peak memory 206812 kb
Host smart-c7dda658-52d3-485c-91ad-919d4cc10d8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3841588507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.3841588507
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.995507703
Short name T573
Test name
Test status
Simulation time 26476796 ps
CPU time 4.24 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:46:23 PM PDT 24
Peak memory 203684 kb
Host smart-354c9b26-9d76-4568-a428-3e5580913753
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=995507703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.995507703
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.2466964391
Short name T751
Test name
Test status
Simulation time 15640076 ps
CPU time 2.09 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:46:26 PM PDT 24
Peak memory 203324 kb
Host smart-ec95a09d-6154-4b7f-96ce-806e421a2208
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2466964391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2466964391
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.983139258
Short name T756
Test name
Test status
Simulation time 296218357 ps
CPU time 2.86 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:46:29 PM PDT 24
Peak memory 203468 kb
Host smart-bad71411-900b-455a-a077-47d45d9ec255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=983139258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.983139258
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3295898581
Short name T544
Test name
Test status
Simulation time 61027625221 ps
CPU time 224.86 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:50:07 PM PDT 24
Peak memory 204792 kb
Host smart-1c6922b2-c2ad-428e-873b-9b4fdccf34f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295898581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3295898581
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2440697753
Short name T871
Test name
Test status
Simulation time 39043759175 ps
CPU time 237.28 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:50:17 PM PDT 24
Peak memory 211760 kb
Host smart-bf14d52c-9dd7-42d7-937a-d2471d2752c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2440697753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2440697753
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2999606651
Short name T504
Test name
Test status
Simulation time 147216705 ps
CPU time 18.98 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:46:40 PM PDT 24
Peak memory 204896 kb
Host smart-cc75301e-81d6-4160-a054-23c3d6684725
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999606651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2999606651
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.2619751271
Short name T845
Test name
Test status
Simulation time 246235527 ps
CPU time 18.54 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:46:38 PM PDT 24
Peak memory 204236 kb
Host smart-3d90590a-50c1-4b07-a4ac-153ce65b8f0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2619751271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2619751271
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.2162831655
Short name T45
Test name
Test status
Simulation time 61146581 ps
CPU time 2.7 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:46:22 PM PDT 24
Peak memory 203480 kb
Host smart-8fb24161-bfb7-4900-a3b1-1de42b2456c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2162831655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2162831655
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1789257293
Short name T377
Test name
Test status
Simulation time 7819366129 ps
CPU time 37.42 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:46:59 PM PDT 24
Peak memory 203628 kb
Host smart-baa670c9-f896-42a6-b7df-cebce92c4a68
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789257293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1789257293
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3968086199
Short name T627
Test name
Test status
Simulation time 6171923992 ps
CPU time 34.38 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:47:00 PM PDT 24
Peak memory 203536 kb
Host smart-d2cd8bb5-9ee7-4fd4-ba4f-38db27d06496
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3968086199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3968086199
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3560478761
Short name T541
Test name
Test status
Simulation time 108199062 ps
CPU time 3.11 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:46:25 PM PDT 24
Peak memory 203516 kb
Host smart-806ab35f-1ef7-4a6e-88a7-ca74fd896e68
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560478761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3560478761
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.245157118
Short name T817
Test name
Test status
Simulation time 1536144744 ps
CPU time 152.41 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:48:54 PM PDT 24
Peak memory 209176 kb
Host smart-fba6f7d3-ed4f-4c78-aa18-962fa06c0cc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=245157118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.245157118
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2914166692
Short name T648
Test name
Test status
Simulation time 9085366105 ps
CPU time 195.89 seconds
Started May 07 12:46:18 PM PDT 24
Finished May 07 12:49:35 PM PDT 24
Peak memory 206756 kb
Host smart-eed11a48-4e48-4283-83ef-c5d7f5dab98d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2914166692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2914166692
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3479994886
Short name T172
Test name
Test status
Simulation time 18527321425 ps
CPU time 434.08 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:53:36 PM PDT 24
Peak memory 208712 kb
Host smart-43a956e9-a4ef-4505-9be3-82d3fb8e9e4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3479994886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.3479994886
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2359732433
Short name T886
Test name
Test status
Simulation time 2509145139 ps
CPU time 211.97 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:49:56 PM PDT 24
Peak memory 213136 kb
Host smart-44732ea2-2cd6-4a8a-84e4-0df236eb4025
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2359732433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.2359732433
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2429122568
Short name T62
Test name
Test status
Simulation time 901271986 ps
CPU time 26.38 seconds
Started May 07 12:46:21 PM PDT 24
Finished May 07 12:46:49 PM PDT 24
Peak memory 205076 kb
Host smart-261c3098-f110-4269-b387-4f91435e364b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2429122568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2429122568
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.4043761821
Short name T519
Test name
Test status
Simulation time 413242357 ps
CPU time 9.86 seconds
Started May 07 12:46:26 PM PDT 24
Finished May 07 12:46:37 PM PDT 24
Peak memory 211668 kb
Host smart-999733d2-84a1-4c20-951c-4acd4420e2b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4043761821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4043761821
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1441365489
Short name T749
Test name
Test status
Simulation time 174113959989 ps
CPU time 650.38 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:57:25 PM PDT 24
Peak memory 206068 kb
Host smart-bc1f02e4-fd91-4a1f-ab32-ee8ee394543b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1441365489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.1441365489
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2834469098
Short name T1
Test name
Test status
Simulation time 341958612 ps
CPU time 7.86 seconds
Started May 07 12:46:26 PM PDT 24
Finished May 07 12:46:35 PM PDT 24
Peak memory 203660 kb
Host smart-98b93440-b6f3-44cb-98ae-3038196d590c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2834469098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2834469098
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.216173822
Short name T788
Test name
Test status
Simulation time 2644427803 ps
CPU time 22.12 seconds
Started May 07 12:46:23 PM PDT 24
Finished May 07 12:46:47 PM PDT 24
Peak memory 203560 kb
Host smart-4bf3c305-b20e-4055-934a-08ecfbef97c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=216173822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.216173822
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.3953650785
Short name T597
Test name
Test status
Simulation time 1162452287 ps
CPU time 31.71 seconds
Started May 07 12:46:21 PM PDT 24
Finished May 07 12:46:55 PM PDT 24
Peak memory 204392 kb
Host smart-889e5b1f-526e-4b83-952b-aa991c9dbc33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3953650785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3953650785
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3147566450
Short name T362
Test name
Test status
Simulation time 40256937274 ps
CPU time 84.81 seconds
Started May 07 12:46:26 PM PDT 24
Finished May 07 12:47:52 PM PDT 24
Peak memory 211760 kb
Host smart-6583e476-1d2b-4523-885b-f1b834c58978
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147566450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3147566450
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1333351156
Short name T242
Test name
Test status
Simulation time 18155988057 ps
CPU time 149.63 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:48:55 PM PDT 24
Peak memory 204760 kb
Host smart-5cc182bf-6d98-4760-8528-a7e3f86b86a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1333351156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1333351156
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1986022648
Short name T548
Test name
Test status
Simulation time 386617778 ps
CPU time 30.51 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:46:51 PM PDT 24
Peak memory 205372 kb
Host smart-492dcaa1-6d7b-4bae-8967-e8a4bdddabb9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986022648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1986022648
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.2944767042
Short name T214
Test name
Test status
Simulation time 1021787204 ps
CPU time 23.62 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:46:48 PM PDT 24
Peak memory 203532 kb
Host smart-ae92ac2b-4476-4e62-91a0-fec5f009d722
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2944767042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2944767042
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.3337933586
Short name T355
Test name
Test status
Simulation time 35295495 ps
CPU time 2.73 seconds
Started May 07 12:46:25 PM PDT 24
Finished May 07 12:46:29 PM PDT 24
Peak memory 203464 kb
Host smart-2e2d9e11-a62f-4b48-872c-30137b98ea9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3337933586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3337933586
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1441517466
Short name T73
Test name
Test status
Simulation time 11067276893 ps
CPU time 34.35 seconds
Started May 07 12:46:20 PM PDT 24
Finished May 07 12:46:57 PM PDT 24
Peak memory 203460 kb
Host smart-8efe1e0d-9ba5-4ee4-a7dd-0039c3491d8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441517466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1441517466
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1270644165
Short name T63
Test name
Test status
Simulation time 5371582285 ps
CPU time 27.51 seconds
Started May 07 12:46:19 PM PDT 24
Finished May 07 12:46:49 PM PDT 24
Peak memory 203508 kb
Host smart-28753ad9-5e0a-41de-932c-ef5c772d5bcb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1270644165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1270644165
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2731313938
Short name T11
Test name
Test status
Simulation time 149078059 ps
CPU time 2.54 seconds
Started May 07 12:46:22 PM PDT 24
Finished May 07 12:46:26 PM PDT 24
Peak memory 203420 kb
Host smart-b1ff5f5e-efb1-4a2a-9926-bc42ddd2368c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731313938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2731313938
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1282607001
Short name T624
Test name
Test status
Simulation time 8237468935 ps
CPU time 253.49 seconds
Started May 07 12:46:27 PM PDT 24
Finished May 07 12:50:42 PM PDT 24
Peak memory 209580 kb
Host smart-cd9359f7-ccf0-4732-b5ec-a738bc6ec947
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1282607001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1282607001
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2527471602
Short name T277
Test name
Test status
Simulation time 1606615299 ps
CPU time 45.04 seconds
Started May 07 12:46:27 PM PDT 24
Finished May 07 12:47:13 PM PDT 24
Peak memory 204176 kb
Host smart-736769ff-7016-4599-bfd8-e5eb292c8350
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2527471602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2527471602
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3926549888
Short name T483
Test name
Test status
Simulation time 315579551 ps
CPU time 99.18 seconds
Started May 07 12:46:23 PM PDT 24
Finished May 07 12:48:04 PM PDT 24
Peak memory 208460 kb
Host smart-82676246-4610-430d-9bc6-926fee1a6a69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3926549888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.3926549888
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3173008573
Short name T865
Test name
Test status
Simulation time 3108280240 ps
CPU time 227.69 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:50:13 PM PDT 24
Peak memory 219952 kb
Host smart-27fbc7c6-b7b8-4022-843b-95873bbd1216
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3173008573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.3173008573
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1715997229
Short name T445
Test name
Test status
Simulation time 52424798 ps
CPU time 7.08 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:41 PM PDT 24
Peak memory 205092 kb
Host smart-ea224fb0-6758-44e0-9fde-ff709842d0a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1715997229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1715997229
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1912026684
Short name T662
Test name
Test status
Simulation time 217476516 ps
CPU time 10.68 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 204528 kb
Host smart-824a294a-12e0-45fe-a081-032c796ffd94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1912026684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1912026684
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3289329234
Short name T770
Test name
Test status
Simulation time 163442432410 ps
CPU time 643.38 seconds
Started May 07 12:46:30 PM PDT 24
Finished May 07 12:57:14 PM PDT 24
Peak memory 211720 kb
Host smart-006371c7-67c3-4486-90de-13967e1c8859
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3289329234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.3289329234
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3575463021
Short name T322
Test name
Test status
Simulation time 120450775 ps
CPU time 2.61 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:46:28 PM PDT 24
Peak memory 203488 kb
Host smart-7fb81245-7b8e-44bd-b62d-c365a8a185b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3575463021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3575463021
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.2860980377
Short name T806
Test name
Test status
Simulation time 838070428 ps
CPU time 29.29 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:46:55 PM PDT 24
Peak memory 203604 kb
Host smart-e6fe5a56-5ab1-487b-9424-13ce392b6e80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2860980377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2860980377
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.3783259943
Short name T253
Test name
Test status
Simulation time 1817021009 ps
CPU time 34.89 seconds
Started May 07 12:46:30 PM PDT 24
Finished May 07 12:47:06 PM PDT 24
Peak memory 204564 kb
Host smart-d0487e4a-cd6a-4c9a-ac0b-b41b34d7950a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3783259943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3783259943
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1985988332
Short name T385
Test name
Test status
Simulation time 62062023815 ps
CPU time 185.8 seconds
Started May 07 12:46:23 PM PDT 24
Finished May 07 12:49:31 PM PDT 24
Peak memory 204840 kb
Host smart-2ba919e3-64b5-4b1e-b5ae-bc62be172c40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985988332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1985988332
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1777692347
Short name T618
Test name
Test status
Simulation time 84040787393 ps
CPU time 195.25 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:49:40 PM PDT 24
Peak memory 205040 kb
Host smart-9bb501d7-434d-4709-8ec6-c33f3bea3283
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1777692347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1777692347
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3245275097
Short name T821
Test name
Test status
Simulation time 130889263 ps
CPU time 12.72 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:47 PM PDT 24
Peak memory 204592 kb
Host smart-f6b9fb2c-dfc7-4618-b950-6359a8ed6500
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245275097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3245275097
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.195499071
Short name T779
Test name
Test status
Simulation time 755360351 ps
CPU time 15.07 seconds
Started May 07 12:46:25 PM PDT 24
Finished May 07 12:46:41 PM PDT 24
Peak memory 203536 kb
Host smart-8ddf4a3d-7d03-4d94-b529-5514cfc835bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=195499071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.195499071
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.2264562467
Short name T837
Test name
Test status
Simulation time 53039904 ps
CPU time 2.41 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:46:27 PM PDT 24
Peak memory 203472 kb
Host smart-939e6dbf-f9ca-40d7-aa7e-e89c6eefb3d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2264562467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2264562467
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1104774076
Short name T437
Test name
Test status
Simulation time 6706469419 ps
CPU time 30.17 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:47:04 PM PDT 24
Peak memory 202948 kb
Host smart-5cfdfe76-6dbd-4604-b3a3-fb63ef02d497
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104774076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1104774076
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.271038747
Short name T726
Test name
Test status
Simulation time 3633966127 ps
CPU time 27.41 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:46:52 PM PDT 24
Peak memory 203544 kb
Host smart-23f86e57-6039-4db3-8d91-2ee02e9f115b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=271038747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.271038747
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3917883552
Short name T229
Test name
Test status
Simulation time 23580621 ps
CPU time 2.14 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 203500 kb
Host smart-3b1f848e-2310-4612-9bc2-4dee117c5617
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917883552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3917883552
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.698322415
Short name T323
Test name
Test status
Simulation time 241948861 ps
CPU time 25.54 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:47:00 PM PDT 24
Peak memory 205984 kb
Host smart-b2c7675d-7a17-4de3-ab4f-e9873c049816
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=698322415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.698322415
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3537715043
Short name T386
Test name
Test status
Simulation time 1372168771 ps
CPU time 109.7 seconds
Started May 07 12:46:24 PM PDT 24
Finished May 07 12:48:15 PM PDT 24
Peak memory 206544 kb
Host smart-a0ea39ad-2467-405c-b76e-6963926e145c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3537715043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3537715043
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3728354829
Short name T192
Test name
Test status
Simulation time 6998109884 ps
CPU time 370 seconds
Started May 07 12:46:27 PM PDT 24
Finished May 07 12:52:38 PM PDT 24
Peak memory 211760 kb
Host smart-24182c5d-dd29-4d81-b7a5-d4ea85b9e93e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3728354829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.3728354829
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3218220545
Short name T670
Test name
Test status
Simulation time 1254715424 ps
CPU time 307.7 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:51:42 PM PDT 24
Peak memory 219868 kb
Host smart-28e17942-543c-48f1-a71c-dd6d61d167d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3218220545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.3218220545
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.122808180
Short name T329
Test name
Test status
Simulation time 51037354 ps
CPU time 2.48 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:37 PM PDT 24
Peak memory 203484 kb
Host smart-33c28b67-3b9b-4661-8c1a-ca67cf400607
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=122808180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.122808180
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2732645970
Short name T875
Test name
Test status
Simulation time 94270047244 ps
CPU time 371.61 seconds
Started May 07 12:46:35 PM PDT 24
Finished May 07 12:52:48 PM PDT 24
Peak memory 206764 kb
Host smart-a1a9b3aa-2f92-4701-b5de-a80b83a2db19
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2732645970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.2732645970
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1571396940
Short name T672
Test name
Test status
Simulation time 107954095 ps
CPU time 12.28 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:46:48 PM PDT 24
Peak memory 203816 kb
Host smart-560043b4-27d4-4c2e-b9b0-886e9c2911f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1571396940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1571396940
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.1286802829
Short name T367
Test name
Test status
Simulation time 253135372 ps
CPU time 20.12 seconds
Started May 07 12:46:31 PM PDT 24
Finished May 07 12:46:52 PM PDT 24
Peak memory 203520 kb
Host smart-7104f472-d896-4f0b-b2f0-9a44010b9112
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1286802829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1286802829
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.2668383400
Short name T895
Test name
Test status
Simulation time 122180045 ps
CPU time 13.31 seconds
Started May 07 12:46:26 PM PDT 24
Finished May 07 12:46:41 PM PDT 24
Peak memory 204760 kb
Host smart-76dcba68-61fd-461f-bbf5-9216ef3a74ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2668383400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2668383400
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3807154851
Short name T53
Test name
Test status
Simulation time 44829205692 ps
CPU time 152.06 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:49:07 PM PDT 24
Peak memory 205196 kb
Host smart-ea7c5541-9cdf-40c9-bc04-11096fc684b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807154851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3807154851
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.4274854001
Short name T686
Test name
Test status
Simulation time 3716522904 ps
CPU time 17.64 seconds
Started May 07 12:46:37 PM PDT 24
Finished May 07 12:46:56 PM PDT 24
Peak memory 203584 kb
Host smart-f48a3b48-75e7-464b-8fbd-a6600060be7e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4274854001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.4274854001
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2261993809
Short name T349
Test name
Test status
Simulation time 63462965 ps
CPU time 6.08 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:46:41 PM PDT 24
Peak memory 211664 kb
Host smart-a2b3a4e2-f528-4d6b-b8d1-7fab0fe8743f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261993809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2261993809
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.2151320206
Short name T512
Test name
Test status
Simulation time 68189369 ps
CPU time 4.77 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:37 PM PDT 24
Peak memory 203504 kb
Host smart-273cb181-6aaf-420a-8541-c2feaef8d2e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2151320206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2151320206
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.225175942
Short name T420
Test name
Test status
Simulation time 32282091 ps
CPU time 2.11 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:36 PM PDT 24
Peak memory 203084 kb
Host smart-d1d031b6-be9e-4695-816e-fc1f5521c718
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=225175942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.225175942
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2543873683
Short name T599
Test name
Test status
Simulation time 9404080467 ps
CPU time 33.02 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:47:07 PM PDT 24
Peak memory 203548 kb
Host smart-a628aa30-4e27-4a56-8a28-7c95748ffc9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543873683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2543873683
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1443760011
Short name T424
Test name
Test status
Simulation time 4064635520 ps
CPU time 27.39 seconds
Started May 07 12:46:23 PM PDT 24
Finished May 07 12:46:52 PM PDT 24
Peak memory 203572 kb
Host smart-444011c0-2493-4f79-9504-61b0542c6321
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1443760011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1443760011
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3677958672
Short name T305
Test name
Test status
Simulation time 47022385 ps
CPU time 2.46 seconds
Started May 07 12:46:30 PM PDT 24
Finished May 07 12:46:33 PM PDT 24
Peak memory 203472 kb
Host smart-ce5825f3-a22f-45c0-8af1-f29d3b58d22f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677958672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3677958672
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.2144754676
Short name T147
Test name
Test status
Simulation time 8572753711 ps
CPU time 135.49 seconds
Started May 07 12:46:35 PM PDT 24
Finished May 07 12:48:52 PM PDT 24
Peak memory 211744 kb
Host smart-67bd8f51-6f5d-41ad-8206-841220b1c30d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2144754676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2144754676
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2675966386
Short name T666
Test name
Test status
Simulation time 358561428 ps
CPU time 7.77 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:46:43 PM PDT 24
Peak memory 203440 kb
Host smart-bb961d68-8ad4-4692-9211-f22626d50341
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2675966386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2675966386
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3934495259
Short name T195
Test name
Test status
Simulation time 1265572938 ps
CPU time 251.24 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:50:47 PM PDT 24
Peak memory 208752 kb
Host smart-6d8157ea-6766-41d8-a052-df660421e906
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934495259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.3934495259
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3388341021
Short name T423
Test name
Test status
Simulation time 551289052 ps
CPU time 14.98 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:46:51 PM PDT 24
Peak memory 205156 kb
Host smart-84fb80dc-b5d9-4b52-9bd4-2b81648e1bf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3388341021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3388341021
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1439281773
Short name T468
Test name
Test status
Simulation time 861778338 ps
CPU time 21.19 seconds
Started May 07 12:46:35 PM PDT 24
Finished May 07 12:46:58 PM PDT 24
Peak memory 211732 kb
Host smart-c9f576f8-688d-42a5-a458-c08b8234f747
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1439281773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1439281773
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1136981773
Short name T118
Test name
Test status
Simulation time 20182218573 ps
CPU time 101.61 seconds
Started May 07 12:46:34 PM PDT 24
Finished May 07 12:48:18 PM PDT 24
Peak memory 211756 kb
Host smart-6768719d-0c2a-4d1f-802c-096c777cb6c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1136981773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.1136981773
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1466436070
Short name T12
Test name
Test status
Simulation time 196625569 ps
CPU time 7.44 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:42 PM PDT 24
Peak memory 203756 kb
Host smart-044714d7-a19d-47be-95b9-c5f6ee132060
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1466436070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1466436070
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.1411679166
Short name T345
Test name
Test status
Simulation time 236944905 ps
CPU time 21.55 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:55 PM PDT 24
Peak memory 203400 kb
Host smart-da38242b-fc73-4225-a3a1-3a0502bbf413
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1411679166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1411679166
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.2690413323
Short name T201
Test name
Test status
Simulation time 159152744 ps
CPU time 13.23 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:48 PM PDT 24
Peak memory 204984 kb
Host smart-be145a55-3d5f-4868-8022-3386187d8d56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2690413323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2690413323
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3951979847
Short name T613
Test name
Test status
Simulation time 24271656116 ps
CPU time 113.4 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:48:29 PM PDT 24
Peak memory 205004 kb
Host smart-dbf66fa4-57e6-4866-aca0-695e19090f0d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951979847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3951979847
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3051274997
Short name T473
Test name
Test status
Simulation time 14314735862 ps
CPU time 74.24 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:47:50 PM PDT 24
Peak memory 204736 kb
Host smart-30269397-e991-43e7-95b6-0ddcf13ddbd4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3051274997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3051274997
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1871370744
Short name T571
Test name
Test status
Simulation time 155779665 ps
CPU time 13.31 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:46:49 PM PDT 24
Peak memory 204624 kb
Host smart-4d4d0c5b-6827-48ac-b424-129a537c12ec
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871370744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1871370744
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.3904375850
Short name T652
Test name
Test status
Simulation time 464570117 ps
CPU time 18.23 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:46:53 PM PDT 24
Peak memory 211592 kb
Host smart-9924ce2e-7f74-487b-ab2b-2840b25aa626
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3904375850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3904375850
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.656817739
Short name T486
Test name
Test status
Simulation time 414623510 ps
CPU time 2.74 seconds
Started May 07 12:46:34 PM PDT 24
Finished May 07 12:46:39 PM PDT 24
Peak memory 203472 kb
Host smart-2e2ef958-ebcb-4f75-86cc-020f71d48a97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=656817739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.656817739
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.20909095
Short name T765
Test name
Test status
Simulation time 11056036228 ps
CPU time 37.11 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:47:11 PM PDT 24
Peak memory 203560 kb
Host smart-4a86c77f-faea-4a02-aec1-2b8e4afabb72
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=20909095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.20909095
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3599234695
Short name T515
Test name
Test status
Simulation time 10032763779 ps
CPU time 27.56 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:47:06 PM PDT 24
Peak memory 203572 kb
Host smart-59fcda53-b54c-4fc0-8898-22c10b4fbda3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3599234695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3599234695
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2282114558
Short name T644
Test name
Test status
Simulation time 57463990 ps
CPU time 2.61 seconds
Started May 07 12:46:34 PM PDT 24
Finished May 07 12:46:39 PM PDT 24
Peak memory 203496 kb
Host smart-fc520171-a11b-4164-a217-dcf1c94c03f9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282114558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2282114558
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3359001772
Short name T768
Test name
Test status
Simulation time 2735003261 ps
CPU time 64.27 seconds
Started May 07 12:46:34 PM PDT 24
Finished May 07 12:47:40 PM PDT 24
Peak memory 206852 kb
Host smart-eb5a8fd0-1fbf-44dc-925a-8ed397bcc464
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3359001772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3359001772
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.342236323
Short name T463
Test name
Test status
Simulation time 4262575311 ps
CPU time 129.44 seconds
Started May 07 12:46:34 PM PDT 24
Finished May 07 12:48:46 PM PDT 24
Peak memory 207496 kb
Host smart-42c48528-1d5b-4cc5-8a73-d0c3fad12ba8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=342236323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.342236323
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.146138559
Short name T40
Test name
Test status
Simulation time 13426905484 ps
CPU time 465.57 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:54:19 PM PDT 24
Peak memory 210204 kb
Host smart-d0cc43a6-7906-44b0-a760-0911cce2b412
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=146138559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand
_reset.146138559
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2323161712
Short name T458
Test name
Test status
Simulation time 162589566 ps
CPU time 29.97 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:47:06 PM PDT 24
Peak memory 206196 kb
Host smart-4fd6b65a-bb38-418e-a623-c2455703203b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2323161712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.2323161712
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2842492700
Short name T464
Test name
Test status
Simulation time 102114875 ps
CPU time 9.85 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:46:45 PM PDT 24
Peak memory 204820 kb
Host smart-8bc82a0a-0a3e-4119-8cb9-9809bee7cacd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2842492700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2842492700
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2285647222
Short name T224
Test name
Test status
Simulation time 3377833651 ps
CPU time 66.46 seconds
Started May 07 12:46:40 PM PDT 24
Finished May 07 12:47:48 PM PDT 24
Peak memory 206852 kb
Host smart-440e6824-2206-4323-b3cf-287df09e3b46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2285647222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2285647222
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1496876590
Short name T111
Test name
Test status
Simulation time 27731519199 ps
CPU time 242 seconds
Started May 07 12:46:40 PM PDT 24
Finished May 07 12:50:44 PM PDT 24
Peak memory 211764 kb
Host smart-b78575bf-0eed-494f-8d13-9631b481fe12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1496876590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.1496876590
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3800862142
Short name T414
Test name
Test status
Simulation time 146650423 ps
CPU time 16.17 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:46:56 PM PDT 24
Peak memory 204064 kb
Host smart-1a3318be-f991-4527-aeea-02f135ca6185
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3800862142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3800862142
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.1397805290
Short name T676
Test name
Test status
Simulation time 1598550302 ps
CPU time 29.79 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:47:09 PM PDT 24
Peak memory 203456 kb
Host smart-a0e88e41-9adf-45c0-9e86-483a768b1aec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1397805290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1397805290
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.1364168917
Short name T647
Test name
Test status
Simulation time 710748163 ps
CPU time 31.52 seconds
Started May 07 12:46:45 PM PDT 24
Finished May 07 12:47:18 PM PDT 24
Peak memory 204536 kb
Host smart-b4384afd-e7d0-4be7-bf1a-d0d022c3b7cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1364168917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1364168917
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.799674719
Short name T623
Test name
Test status
Simulation time 35680777518 ps
CPU time 84.4 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:48:05 PM PDT 24
Peak memory 204928 kb
Host smart-7795b19e-eea0-4b81-9195-25268195b699
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=799674719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.799674719
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3598598825
Short name T791
Test name
Test status
Simulation time 20828515997 ps
CPU time 166.05 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:49:27 PM PDT 24
Peak memory 205136 kb
Host smart-3af77625-d9fc-4091-82c0-766e7eec758f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3598598825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3598598825
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2372892439
Short name T589
Test name
Test status
Simulation time 17837613 ps
CPU time 1.88 seconds
Started May 07 12:46:37 PM PDT 24
Finished May 07 12:46:40 PM PDT 24
Peak memory 203592 kb
Host smart-a3c9ef4c-5da2-4fd5-9536-6024c29b248f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372892439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2372892439
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.3201528157
Short name T574
Test name
Test status
Simulation time 1504997560 ps
CPU time 7.39 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:46:48 PM PDT 24
Peak memory 203800 kb
Host smart-2cdcb607-faab-4b5a-8964-a22867b72277
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3201528157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3201528157
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.1697670949
Short name T619
Test name
Test status
Simulation time 165774355 ps
CPU time 3.25 seconds
Started May 07 12:46:31 PM PDT 24
Finished May 07 12:46:35 PM PDT 24
Peak memory 203500 kb
Host smart-33607c71-488a-4314-8d1a-d2516076baa0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1697670949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1697670949
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3857535435
Short name T762
Test name
Test status
Simulation time 8186240954 ps
CPU time 40 seconds
Started May 07 12:46:33 PM PDT 24
Finished May 07 12:47:15 PM PDT 24
Peak memory 203556 kb
Host smart-8f2111e6-efa0-4260-86e3-a804f69a7645
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857535435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3857535435
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1438344533
Short name T179
Test name
Test status
Simulation time 7440049166 ps
CPU time 23.96 seconds
Started May 07 12:46:32 PM PDT 24
Finished May 07 12:46:58 PM PDT 24
Peak memory 203556 kb
Host smart-4e1f2736-16be-4161-80d0-2e6083efa394
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1438344533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1438344533
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2776276383
Short name T823
Test name
Test status
Simulation time 40063478 ps
CPU time 2.59 seconds
Started May 07 12:46:34 PM PDT 24
Finished May 07 12:46:39 PM PDT 24
Peak memory 203676 kb
Host smart-42ddf1ca-71c4-4fa8-af25-01acf92f6c4a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776276383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2776276383
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1672642848
Short name T535
Test name
Test status
Simulation time 1299593282 ps
CPU time 128.62 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:48:48 PM PDT 24
Peak memory 207228 kb
Host smart-b6f5888d-6851-4739-b3d9-0b6951ea5b0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1672642848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1672642848
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1355717365
Short name T729
Test name
Test status
Simulation time 12693448932 ps
CPU time 64.99 seconds
Started May 07 12:46:37 PM PDT 24
Finished May 07 12:47:43 PM PDT 24
Peak memory 205948 kb
Host smart-4d9af7d2-69c5-4125-a5ef-8df4969d72ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1355717365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1355717365
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.913910089
Short name T128
Test name
Test status
Simulation time 15993296148 ps
CPU time 551.19 seconds
Started May 07 12:46:37 PM PDT 24
Finished May 07 12:55:49 PM PDT 24
Peak memory 219948 kb
Host smart-dd16fde4-e3fd-4336-a0d3-00c1b2cbbf17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=913910089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand
_reset.913910089
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3746248609
Short name T811
Test name
Test status
Simulation time 203948446 ps
CPU time 17.71 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:46:58 PM PDT 24
Peak memory 204860 kb
Host smart-376fd1fc-f4bb-4c2c-a30a-31cadfa6e4e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3746248609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3746248609
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3485204039
Short name T679
Test name
Test status
Simulation time 7242828705 ps
CPU time 52.64 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:47:32 PM PDT 24
Peak memory 205416 kb
Host smart-333ea5ef-0d2f-4b76-86ec-3e2f65a4a519
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3485204039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3485204039
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2206752079
Short name T478
Test name
Test status
Simulation time 93100703531 ps
CPU time 600.38 seconds
Started May 07 12:46:37 PM PDT 24
Finished May 07 12:56:39 PM PDT 24
Peak memory 206200 kb
Host smart-587566ed-f7aa-4015-ad54-caa9b19718e4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2206752079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2206752079
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.708801303
Short name T2
Test name
Test status
Simulation time 955323492 ps
CPU time 17.63 seconds
Started May 07 12:46:42 PM PDT 24
Finished May 07 12:47:01 PM PDT 24
Peak memory 204076 kb
Host smart-981f0aa9-0247-411a-a886-e063ffd657af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=708801303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.708801303
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.4005340713
Short name T373
Test name
Test status
Simulation time 71866111 ps
CPU time 3.24 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:46:44 PM PDT 24
Peak memory 203488 kb
Host smart-eb478a5a-308b-4499-a60c-2a2ce3bf2fc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4005340713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4005340713
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.3102619041
Short name T816
Test name
Test status
Simulation time 412808895 ps
CPU time 12.32 seconds
Started May 07 12:46:42 PM PDT 24
Finished May 07 12:46:56 PM PDT 24
Peak memory 211672 kb
Host smart-ace14c96-d0af-4367-85af-abca1bd3ae1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3102619041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3102619041
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1171281658
Short name T873
Test name
Test status
Simulation time 33634065811 ps
CPU time 159.58 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:49:19 PM PDT 24
Peak memory 204940 kb
Host smart-39457843-099e-4375-85ae-b4800d02cbd8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171281658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1171281658
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2650869427
Short name T99
Test name
Test status
Simulation time 19206859003 ps
CPU time 171.08 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:49:32 PM PDT 24
Peak memory 204784 kb
Host smart-ccef0962-3db0-4ac0-8af5-7e119d01c9d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2650869427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2650869427
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2670290860
Short name T310
Test name
Test status
Simulation time 86877713 ps
CPU time 12.81 seconds
Started May 07 12:46:40 PM PDT 24
Finished May 07 12:46:55 PM PDT 24
Peak memory 211644 kb
Host smart-72a9d43f-9f13-475e-b536-59485eef9db2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670290860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2670290860
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.2359698266
Short name T885
Test name
Test status
Simulation time 264569825 ps
CPU time 17.95 seconds
Started May 07 12:46:40 PM PDT 24
Finished May 07 12:47:00 PM PDT 24
Peak memory 204148 kb
Host smart-0c7512e6-5cc9-4f39-8baf-13812af4a443
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2359698266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2359698266
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.3805592788
Short name T528
Test name
Test status
Simulation time 231664925 ps
CPU time 3.92 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:46:45 PM PDT 24
Peak memory 203468 kb
Host smart-e7c711b4-bbf1-4c66-8fc8-569514c57453
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3805592788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3805592788
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.194427977
Short name T609
Test name
Test status
Simulation time 4703188170 ps
CPU time 29.07 seconds
Started May 07 12:46:44 PM PDT 24
Finished May 07 12:47:14 PM PDT 24
Peak memory 203588 kb
Host smart-ad6cbbf3-861b-422d-8add-d265527682bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=194427977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.194427977
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1534373081
Short name T620
Test name
Test status
Simulation time 11868464883 ps
CPU time 44.58 seconds
Started May 07 12:46:45 PM PDT 24
Finished May 07 12:47:31 PM PDT 24
Peak memory 203556 kb
Host smart-7361478f-5aa1-4f29-84db-0a9c534252b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1534373081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1534373081
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2614771354
Short name T298
Test name
Test status
Simulation time 35576186 ps
CPU time 1.99 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:46:43 PM PDT 24
Peak memory 203500 kb
Host smart-73d1a47f-2108-4f28-81aa-a1c7159b1e24
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614771354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2614771354
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2894945001
Short name T856
Test name
Test status
Simulation time 6737833322 ps
CPU time 218.67 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:50:19 PM PDT 24
Peak memory 209172 kb
Host smart-e9dde52d-fbbb-4bb2-9608-11bb2fd994e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2894945001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2894945001
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3281459413
Short name T539
Test name
Test status
Simulation time 8523677721 ps
CPU time 154.99 seconds
Started May 07 12:46:45 PM PDT 24
Finished May 07 12:49:21 PM PDT 24
Peak memory 207844 kb
Host smart-ce5b0bac-06f0-4725-ad95-127088d3c9ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281459413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3281459413
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2759879222
Short name T164
Test name
Test status
Simulation time 423380464 ps
CPU time 161.63 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:49:22 PM PDT 24
Peak memory 208444 kb
Host smart-0dd97ed3-b9c2-4ad8-843b-4a1cdfbd5be6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2759879222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.2759879222
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2418527121
Short name T287
Test name
Test status
Simulation time 2173741233 ps
CPU time 358.24 seconds
Started May 07 12:46:44 PM PDT 24
Finished May 07 12:52:43 PM PDT 24
Peak memory 220064 kb
Host smart-a85dd6d8-236a-4292-86c5-b98ed6c82b07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2418527121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.2418527121
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3824174665
Short name T781
Test name
Test status
Simulation time 123239709 ps
CPU time 9.85 seconds
Started May 07 12:46:40 PM PDT 24
Finished May 07 12:46:51 PM PDT 24
Peak memory 205060 kb
Host smart-1cb3bbf2-cbda-4f98-8a10-bc55e8e0f23c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3824174665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3824174665
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.472497851
Short name T324
Test name
Test status
Simulation time 399685407 ps
CPU time 41.45 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:47:23 PM PDT 24
Peak memory 211672 kb
Host smart-39eed493-3d61-428f-a0da-e6ee32f8b278
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=472497851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.472497851
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3380663265
Short name T849
Test name
Test status
Simulation time 24925666365 ps
CPU time 128.37 seconds
Started May 07 12:46:42 PM PDT 24
Finished May 07 12:48:52 PM PDT 24
Peak memory 206100 kb
Host smart-d5c1e49d-5a59-40c2-a3b1-3f7a8d988ea7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3380663265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.3380663265
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.851858724
Short name T375
Test name
Test status
Simulation time 499786742 ps
CPU time 18.54 seconds
Started May 07 12:46:47 PM PDT 24
Finished May 07 12:47:07 PM PDT 24
Peak memory 203944 kb
Host smart-d6e0050c-6006-43ce-bf66-e27b7971377b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=851858724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.851858724
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.2041581967
Short name T348
Test name
Test status
Simulation time 45493025 ps
CPU time 5.24 seconds
Started May 07 12:46:42 PM PDT 24
Finished May 07 12:46:48 PM PDT 24
Peak memory 203416 kb
Host smart-79a08dbe-0b9c-47e4-9d06-5f6c7cead7dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2041581967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2041581967
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.2161386305
Short name T594
Test name
Test status
Simulation time 725770868 ps
CPU time 12.3 seconds
Started May 07 12:46:42 PM PDT 24
Finished May 07 12:46:56 PM PDT 24
Peak memory 204692 kb
Host smart-97126f39-d3c8-4373-accd-2f705281130e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2161386305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2161386305
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1963708795
Short name T85
Test name
Test status
Simulation time 41093198949 ps
CPU time 147.31 seconds
Started May 07 12:46:40 PM PDT 24
Finished May 07 12:49:09 PM PDT 24
Peak memory 211748 kb
Host smart-7dc887f7-b637-43aa-9be4-0cba24d2d66f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963708795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1963708795
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3896249942
Short name T859
Test name
Test status
Simulation time 27921610519 ps
CPU time 203.75 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:50:05 PM PDT 24
Peak memory 205248 kb
Host smart-633edd8f-eefb-4510-b9a8-cf9695ce599e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3896249942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3896249942
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.4206263027
Short name T406
Test name
Test status
Simulation time 26453197 ps
CPU time 3.35 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:46:44 PM PDT 24
Peak memory 203504 kb
Host smart-21bfc0fa-d38d-46c5-acba-40cece962e67
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206263027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.4206263027
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.3097495446
Short name T64
Test name
Test status
Simulation time 2659035999 ps
CPU time 28.42 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:47:08 PM PDT 24
Peak memory 204072 kb
Host smart-334cd613-9a2a-4b82-94af-2c54480e6c70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3097495446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3097495446
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.258546145
Short name T343
Test name
Test status
Simulation time 184286880 ps
CPU time 3.59 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:46:44 PM PDT 24
Peak memory 203468 kb
Host smart-40fe87a0-f39e-4ddc-bc74-17683595b5e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=258546145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.258546145
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3237073821
Short name T371
Test name
Test status
Simulation time 9816391101 ps
CPU time 33.88 seconds
Started May 07 12:46:38 PM PDT 24
Finished May 07 12:47:13 PM PDT 24
Peak memory 203560 kb
Host smart-70c84845-3102-4837-8fb8-80bdac81dc38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237073821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3237073821
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.724266797
Short name T263
Test name
Test status
Simulation time 7632152557 ps
CPU time 30.47 seconds
Started May 07 12:46:39 PM PDT 24
Finished May 07 12:47:11 PM PDT 24
Peak memory 203556 kb
Host smart-5aa14828-c8d4-410b-8996-60554d934df1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=724266797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.724266797
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1055434923
Short name T554
Test name
Test status
Simulation time 28291409 ps
CPU time 2.1 seconds
Started May 07 12:46:42 PM PDT 24
Finished May 07 12:46:45 PM PDT 24
Peak memory 203464 kb
Host smart-256e09a1-ee17-4f54-8f19-7b395bba91cd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055434923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1055434923
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2310091945
Short name T116
Test name
Test status
Simulation time 7216637621 ps
CPU time 144.02 seconds
Started May 07 12:46:44 PM PDT 24
Finished May 07 12:49:09 PM PDT 24
Peak memory 211752 kb
Host smart-d838de5e-4b9c-40f3-bb3f-c63807f10dcb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2310091945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2310091945
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3804255731
Short name T418
Test name
Test status
Simulation time 3508980055 ps
CPU time 131.29 seconds
Started May 07 12:46:49 PM PDT 24
Finished May 07 12:49:01 PM PDT 24
Peak memory 208212 kb
Host smart-4b8f5aa1-f0e7-459e-bda4-bcfd7f9288b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3804255731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3804255731
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.511259273
Short name T213
Test name
Test status
Simulation time 1316701812 ps
CPU time 61.82 seconds
Started May 07 12:46:46 PM PDT 24
Finished May 07 12:47:49 PM PDT 24
Peak memory 208328 kb
Host smart-3d8f54ef-7197-4993-9f7a-f78872f7cf07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=511259273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand
_reset.511259273
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.731901747
Short name T281
Test name
Test status
Simulation time 467708154 ps
CPU time 90.02 seconds
Started May 07 12:46:47 PM PDT 24
Finished May 07 12:48:18 PM PDT 24
Peak memory 209444 kb
Host smart-1187c1da-8c3d-4d69-bc5e-6890dff1dedc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=731901747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res
et_error.731901747
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2995505105
Short name T316
Test name
Test status
Simulation time 26460308 ps
CPU time 3.1 seconds
Started May 07 12:46:42 PM PDT 24
Finished May 07 12:46:46 PM PDT 24
Peak memory 204520 kb
Host smart-79a08e16-b619-40da-b6ea-6d3d5cd4a5c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2995505105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2995505105
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3314105959
Short name T97
Test name
Test status
Simulation time 1440463980 ps
CPU time 51.33 seconds
Started May 07 12:44:52 PM PDT 24
Finished May 07 12:45:44 PM PDT 24
Peak memory 211580 kb
Host smart-99649d53-3678-4cb0-9294-685d19667f2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3314105959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3314105959
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.4292387796
Short name T632
Test name
Test status
Simulation time 103383546960 ps
CPU time 563.43 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:54:18 PM PDT 24
Peak memory 211752 kb
Host smart-5b1b8fd4-bf58-492a-a250-eccf2db7d506
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4292387796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.4292387796
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.533367169
Short name T121
Test name
Test status
Simulation time 137727748 ps
CPU time 9.89 seconds
Started May 07 12:44:55 PM PDT 24
Finished May 07 12:45:06 PM PDT 24
Peak memory 203796 kb
Host smart-9b05945f-4319-4b18-aed6-a247ec6d0a76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=533367169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.533367169
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.3551836313
Short name T474
Test name
Test status
Simulation time 695225743 ps
CPU time 22.9 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:45:12 PM PDT 24
Peak memory 203508 kb
Host smart-3b81dd59-bbe8-4242-8c66-6991232cd775
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3551836313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3551836313
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.4000157045
Short name T92
Test name
Test status
Simulation time 3023853476 ps
CPU time 29.83 seconds
Started May 07 12:44:43 PM PDT 24
Finished May 07 12:45:14 PM PDT 24
Peak memory 204748 kb
Host smart-e29d9b3c-229c-4ada-a387-6432dc85af84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4000157045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.4000157045
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1056883673
Short name T401
Test name
Test status
Simulation time 4183484066 ps
CPU time 12.53 seconds
Started May 07 12:45:02 PM PDT 24
Finished May 07 12:45:15 PM PDT 24
Peak memory 203564 kb
Host smart-ddacf8e3-2b5d-4898-b158-fcd3511332f5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056883673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1056883673
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.377290633
Short name T792
Test name
Test status
Simulation time 18939923747 ps
CPU time 153.19 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:47:09 PM PDT 24
Peak memory 204636 kb
Host smart-e80d103c-f109-4185-bcd8-688ba01bd8a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=377290633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.377290633
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.629330856
Short name T191
Test name
Test status
Simulation time 205946725 ps
CPU time 21.92 seconds
Started May 07 12:44:55 PM PDT 24
Finished May 07 12:45:18 PM PDT 24
Peak memory 204624 kb
Host smart-3edc9178-179c-4c5c-957c-c7adfcd02746
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629330856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.629330856
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.3662078850
Short name T754
Test name
Test status
Simulation time 218760294 ps
CPU time 11.75 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:23 PM PDT 24
Peak memory 203532 kb
Host smart-544e2823-8a9c-45b9-8332-e9008f9e6dcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3662078850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3662078850
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.1257012935
Short name T358
Test name
Test status
Simulation time 170597430 ps
CPU time 3.24 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 203476 kb
Host smart-3e52e6e9-0e6d-4050-ad05-a998033e56f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1257012935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1257012935
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.724490632
Short name T342
Test name
Test status
Simulation time 5442564859 ps
CPU time 31.19 seconds
Started May 07 12:44:43 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 203504 kb
Host smart-15812c3c-bfbc-4b76-9ad5-8e8e8d814b5a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=724490632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.724490632
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1025735750
Short name T485
Test name
Test status
Simulation time 3475022738 ps
CPU time 26.59 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:45:18 PM PDT 24
Peak memory 203568 kb
Host smart-bfb01263-68ef-482b-8409-cf00e92aeb68
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1025735750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1025735750
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.219009225
Short name T215
Test name
Test status
Simulation time 161492607 ps
CPU time 2.4 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:09 PM PDT 24
Peak memory 203448 kb
Host smart-45bbea52-57fd-40a6-88f0-af09d0509828
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219009225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.219009225
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1994181644
Short name T775
Test name
Test status
Simulation time 2318816170 ps
CPU time 82.1 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:46:05 PM PDT 24
Peak memory 211816 kb
Host smart-b0508b51-3778-4158-ac3f-374da8e4d356
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1994181644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1994181644
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.57067792
Short name T448
Test name
Test status
Simulation time 3774491792 ps
CPU time 105.31 seconds
Started May 07 12:44:47 PM PDT 24
Finished May 07 12:46:33 PM PDT 24
Peak memory 205932 kb
Host smart-c5f71672-ec15-49f8-9833-fd5d9972fa37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57067792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.57067792
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.189159266
Short name T727
Test name
Test status
Simulation time 289398448 ps
CPU time 110.76 seconds
Started May 07 12:44:58 PM PDT 24
Finished May 07 12:46:50 PM PDT 24
Peak memory 208352 kb
Host smart-04a8cd66-e2df-4e8d-b330-96a4bd77a87f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=189159266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_
reset.189159266
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2771198260
Short name T566
Test name
Test status
Simulation time 7773194 ps
CPU time 2.18 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:44:41 PM PDT 24
Peak memory 203424 kb
Host smart-6a942f6a-2a07-4593-92d3-d95ce12acd4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2771198260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.2771198260
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1782196361
Short name T869
Test name
Test status
Simulation time 1127839496 ps
CPU time 14.69 seconds
Started May 07 12:44:55 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 204980 kb
Host smart-7d300b89-fc45-4a5f-953e-3ea80a1c81f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1782196361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1782196361
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1332115136
Short name T194
Test name
Test status
Simulation time 524103767 ps
CPU time 36.56 seconds
Started May 07 12:44:46 PM PDT 24
Finished May 07 12:45:24 PM PDT 24
Peak memory 206280 kb
Host smart-98bd428d-8ae3-4cdf-8dad-ff841811d851
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1332115136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1332115136
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2933422708
Short name T189
Test name
Test status
Simulation time 50594739012 ps
CPU time 362.13 seconds
Started May 07 12:45:00 PM PDT 24
Finished May 07 12:51:03 PM PDT 24
Peak memory 211776 kb
Host smart-1bb90251-ddf2-4b19-bd4f-e87e7c4028e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2933422708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.2933422708
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1137544665
Short name T899
Test name
Test status
Simulation time 230673567 ps
CPU time 3.4 seconds
Started May 07 12:44:44 PM PDT 24
Finished May 07 12:44:48 PM PDT 24
Peak memory 203508 kb
Host smart-8f4f2243-bdd2-48bb-a382-b298efd42819
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1137544665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1137544665
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.952926389
Short name T810
Test name
Test status
Simulation time 993450360 ps
CPU time 20.42 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:45:33 PM PDT 24
Peak memory 203472 kb
Host smart-533cd1fb-8eb7-432c-9510-388d25c96057
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=952926389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.952926389
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.509687502
Short name T744
Test name
Test status
Simulation time 170052363 ps
CPU time 19.08 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:35 PM PDT 24
Peak memory 204660 kb
Host smart-ce42ee5c-ce1f-4b19-b51b-b6819495b21e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=509687502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.509687502
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2807719326
Short name T782
Test name
Test status
Simulation time 43393605201 ps
CPU time 76.58 seconds
Started May 07 12:44:56 PM PDT 24
Finished May 07 12:46:13 PM PDT 24
Peak memory 211748 kb
Host smart-6ce6321a-ce28-4eeb-8c65-ffb9d8376ae3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807719326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2807719326
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2314214924
Short name T671
Test name
Test status
Simulation time 219644505645 ps
CPU time 437.62 seconds
Started May 07 12:44:44 PM PDT 24
Finished May 07 12:52:03 PM PDT 24
Peak memory 204756 kb
Host smart-b6d6fa84-bef4-41b2-82e0-37bb022c57e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2314214924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2314214924
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3635821992
Short name T534
Test name
Test status
Simulation time 65716778 ps
CPU time 6.42 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:44:49 PM PDT 24
Peak memory 204524 kb
Host smart-e1e29847-3db9-4fe3-9ec5-e49b97dc6466
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635821992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3635821992
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.712812111
Short name T44
Test name
Test status
Simulation time 513055973 ps
CPU time 14.74 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:45:28 PM PDT 24
Peak memory 204084 kb
Host smart-d7fdb95c-af08-41dd-9c30-cc9277201985
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=712812111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.712812111
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.3936602154
Short name T180
Test name
Test status
Simulation time 40257941 ps
CPU time 2.49 seconds
Started May 07 12:45:10 PM PDT 24
Finished May 07 12:45:15 PM PDT 24
Peak memory 203500 kb
Host smart-585df903-255f-46f2-8d05-e696e447d064
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3936602154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3936602154
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.451827986
Short name T290
Test name
Test status
Simulation time 9850239870 ps
CPU time 37.83 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:46 PM PDT 24
Peak memory 203556 kb
Host smart-705db5ff-b15c-4e0f-8493-ee09769bc616
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=451827986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.451827986
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.624769548
Short name T98
Test name
Test status
Simulation time 3295935771 ps
CPU time 25.48 seconds
Started May 07 12:44:53 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203544 kb
Host smart-ea88ed7d-0bfd-4446-85dd-81cb9372c39e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=624769548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.624769548
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.765004234
Short name T769
Test name
Test status
Simulation time 92514328 ps
CPU time 2.73 seconds
Started May 07 12:44:58 PM PDT 24
Finished May 07 12:45:01 PM PDT 24
Peak memory 203504 kb
Host smart-e3036017-7adc-4e3f-bf13-5cade68b081c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765004234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.765004234
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1339843212
Short name T136
Test name
Test status
Simulation time 9096011327 ps
CPU time 287.22 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:49:45 PM PDT 24
Peak memory 210304 kb
Host smart-b15bf66b-24e4-43d2-93b7-4b33f6852e6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1339843212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1339843212
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3489605351
Short name T719
Test name
Test status
Simulation time 2730319399 ps
CPU time 133.12 seconds
Started May 07 12:44:37 PM PDT 24
Finished May 07 12:46:52 PM PDT 24
Peak memory 206756 kb
Host smart-e8174569-5ab1-414e-8a91-4387e449790a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3489605351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3489605351
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1759031271
Short name T130
Test name
Test status
Simulation time 2898062081 ps
CPU time 157.97 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:47:44 PM PDT 24
Peak memory 207164 kb
Host smart-65481eef-1ffa-4673-8609-b0f65592fac4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1759031271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.1759031271
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.124749293
Short name T785
Test name
Test status
Simulation time 5837607709 ps
CPU time 337.75 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:50:45 PM PDT 24
Peak memory 219876 kb
Host smart-11d30176-c4b3-4a33-940f-f4f274b4ab18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=124749293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese
t_error.124749293
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2691114393
Short name T848
Test name
Test status
Simulation time 1903738753 ps
CPU time 24.1 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:45:16 PM PDT 24
Peak memory 205020 kb
Host smart-fb4df7ff-0e9f-4ee1-99e1-8cd5bff5ca74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2691114393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2691114393
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.4242742406
Short name T598
Test name
Test status
Simulation time 239549499 ps
CPU time 23.13 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 205512 kb
Host smart-a8847840-dc29-47ea-b204-0fa857f612f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4242742406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.4242742406
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3231678367
Short name T148
Test name
Test status
Simulation time 98038134949 ps
CPU time 611.53 seconds
Started May 07 12:44:54 PM PDT 24
Finished May 07 12:55:07 PM PDT 24
Peak memory 211760 kb
Host smart-9d7bdc71-3296-4cb0-95af-e2f16ff59b3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3231678367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.3231678367
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3977747086
Short name T304
Test name
Test status
Simulation time 116255508 ps
CPU time 13.28 seconds
Started May 07 12:45:04 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203800 kb
Host smart-972ee4eb-cb5c-46ed-9579-b6e2e24bd69f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3977747086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3977747086
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.2825231502
Short name T578
Test name
Test status
Simulation time 590670987 ps
CPU time 19.47 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:45:12 PM PDT 24
Peak memory 203492 kb
Host smart-f4563750-4d79-4410-bd30-7d2776c803e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2825231502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2825231502
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.216184903
Short name T94
Test name
Test status
Simulation time 973794894 ps
CPU time 23.42 seconds
Started May 07 12:45:27 PM PDT 24
Finished May 07 12:45:55 PM PDT 24
Peak memory 204512 kb
Host smart-1ef8df8b-1e20-4b1a-bb49-2f76acbfbe51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=216184903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.216184903
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3464909840
Short name T391
Test name
Test status
Simulation time 36167935005 ps
CPU time 200.91 seconds
Started May 07 12:44:44 PM PDT 24
Finished May 07 12:48:05 PM PDT 24
Peak memory 205452 kb
Host smart-99b82277-25ad-40ea-9347-d88cdfc3cce6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464909840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3464909840
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2548832322
Short name T161
Test name
Test status
Simulation time 39130396207 ps
CPU time 107.29 seconds
Started May 07 12:44:52 PM PDT 24
Finished May 07 12:46:40 PM PDT 24
Peak memory 204900 kb
Host smart-4c9776da-8c9e-4a82-a0a3-f1f6465beba7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2548832322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2548832322
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1074912002
Short name T467
Test name
Test status
Simulation time 74190221 ps
CPU time 6.04 seconds
Started May 07 12:44:55 PM PDT 24
Finished May 07 12:45:02 PM PDT 24
Peak memory 204736 kb
Host smart-035b2f87-69f8-49f6-b073-f1f8722cfefb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074912002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1074912002
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.647852521
Short name T651
Test name
Test status
Simulation time 590735387 ps
CPU time 15.14 seconds
Started May 07 12:45:02 PM PDT 24
Finished May 07 12:45:18 PM PDT 24
Peak memory 204224 kb
Host smart-13f49532-4719-444e-bdff-646bbf673b54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=647852521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.647852521
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.3477859331
Short name T551
Test name
Test status
Simulation time 29963559 ps
CPU time 2.37 seconds
Started May 07 12:44:59 PM PDT 24
Finished May 07 12:45:02 PM PDT 24
Peak memory 203500 kb
Host smart-a04d65f6-6714-4dcf-a8db-809deae70b9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3477859331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3477859331
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2451385417
Short name T553
Test name
Test status
Simulation time 13302692215 ps
CPU time 36.84 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:45:29 PM PDT 24
Peak memory 203540 kb
Host smart-7603c1a6-b7ae-4abb-83ba-058d5751123b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451385417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2451385417
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2489722412
Short name T61
Test name
Test status
Simulation time 2383558978 ps
CPU time 19.95 seconds
Started May 07 12:45:02 PM PDT 24
Finished May 07 12:45:23 PM PDT 24
Peak memory 203568 kb
Host smart-5dc02468-6781-4e21-b09d-04caa84a3209
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2489722412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2489722412
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3755836976
Short name T595
Test name
Test status
Simulation time 39425597 ps
CPU time 2.38 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:45:00 PM PDT 24
Peak memory 203480 kb
Host smart-a9330689-4be0-4d5d-bd13-1476338f1d5d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755836976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3755836976
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.4021611531
Short name T763
Test name
Test status
Simulation time 4818530392 ps
CPU time 124.09 seconds
Started May 07 12:44:52 PM PDT 24
Finished May 07 12:46:57 PM PDT 24
Peak memory 207616 kb
Host smart-6714026b-6d64-47d4-bfd6-9be17f076d9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4021611531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4021611531
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1686960247
Short name T413
Test name
Test status
Simulation time 6936214868 ps
CPU time 69.08 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:45:58 PM PDT 24
Peak memory 206124 kb
Host smart-eea6d005-1b98-4c95-9435-e6517a58f8e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1686960247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1686960247
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3986494549
Short name T389
Test name
Test status
Simulation time 148144413 ps
CPU time 45.19 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:45:43 PM PDT 24
Peak memory 207964 kb
Host smart-323efaff-3e85-4747-b739-962e8600c212
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3986494549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.3986494549
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2209632416
Short name T288
Test name
Test status
Simulation time 415187877 ps
CPU time 128.57 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:47:16 PM PDT 24
Peak memory 210908 kb
Host smart-16a52eec-ab3c-4438-8b9e-6d8e472961d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2209632416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.2209632416
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.907290631
Short name T658
Test name
Test status
Simulation time 3437277033 ps
CPU time 28.92 seconds
Started May 07 12:44:53 PM PDT 24
Finished May 07 12:45:23 PM PDT 24
Peak memory 211732 kb
Host smart-238adfb4-28b4-4ba2-8300-e2d7ab53149d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=907290631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.907290631
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1735881475
Short name T472
Test name
Test status
Simulation time 3045671994 ps
CPU time 59.83 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:45:52 PM PDT 24
Peak memory 206340 kb
Host smart-6d8a4216-70ac-4e65-b582-f8d4a4de9008
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1735881475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1735881475
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3291337399
Short name T243
Test name
Test status
Simulation time 24098010307 ps
CPU time 138.01 seconds
Started May 07 12:45:02 PM PDT 24
Finished May 07 12:47:21 PM PDT 24
Peak memory 205924 kb
Host smart-ecdad616-bbb8-4845-84b2-ee1c396854cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3291337399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.3291337399
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.32310535
Short name T736
Test name
Test status
Simulation time 59248909 ps
CPU time 6.17 seconds
Started May 07 12:45:00 PM PDT 24
Finished May 07 12:45:07 PM PDT 24
Peak memory 203812 kb
Host smart-f7723823-6e21-4852-afeb-7afbe373331b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32310535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.32310535
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.2743734957
Short name T778
Test name
Test status
Simulation time 133688228 ps
CPU time 10.2 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:22 PM PDT 24
Peak memory 203492 kb
Host smart-fb86cd6a-3d5c-4bf1-bbda-934f625a050f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2743734957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2743734957
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.64952795
Short name T88
Test name
Test status
Simulation time 584960574 ps
CPU time 21.2 seconds
Started May 07 12:45:04 PM PDT 24
Finished May 07 12:45:26 PM PDT 24
Peak memory 204516 kb
Host smart-b14947a0-49cd-4d6d-80ec-607542dc851a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64952795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.64952795
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3737335413
Short name T202
Test name
Test status
Simulation time 32612075840 ps
CPU time 131.27 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:47:26 PM PDT 24
Peak memory 205160 kb
Host smart-79bd8fdc-49e3-4b76-a383-e1ff02bb1469
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737335413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3737335413
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1323391076
Short name T506
Test name
Test status
Simulation time 30940305754 ps
CPU time 121.59 seconds
Started May 07 12:45:02 PM PDT 24
Finished May 07 12:47:05 PM PDT 24
Peak memory 204776 kb
Host smart-f32036af-998f-41c5-a2f6-49f5b791b486
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1323391076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1323391076
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2181497300
Short name T207
Test name
Test status
Simulation time 96072637 ps
CPU time 11.59 seconds
Started May 07 12:44:59 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 204700 kb
Host smart-904e2208-0911-4108-9499-43becc376326
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181497300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2181497300
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.1713861368
Short name T461
Test name
Test status
Simulation time 3397746409 ps
CPU time 33.8 seconds
Started May 07 12:44:49 PM PDT 24
Finished May 07 12:45:23 PM PDT 24
Peak memory 204188 kb
Host smart-1a9c1182-2660-4cc1-9b17-7fe48daf19d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1713861368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1713861368
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.1305379879
Short name T449
Test name
Test status
Simulation time 55557599 ps
CPU time 2.32 seconds
Started May 07 12:45:01 PM PDT 24
Finished May 07 12:45:04 PM PDT 24
Peak memory 203488 kb
Host smart-1856a5f8-2423-4ca8-85e2-e97393df58ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1305379879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1305379879
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.805466245
Short name T399
Test name
Test status
Simulation time 5142718025 ps
CPU time 26.55 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:34 PM PDT 24
Peak memory 203580 kb
Host smart-0c838950-062a-4f13-aca0-f4c80869c8ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=805466245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.805466245
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3504439640
Short name T131
Test name
Test status
Simulation time 3147540321 ps
CPU time 24.35 seconds
Started May 07 12:44:43 PM PDT 24
Finished May 07 12:45:08 PM PDT 24
Peak memory 203452 kb
Host smart-47cc65b0-aa88-4e97-99fe-70904cb2eaf4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3504439640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3504439640
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.182164561
Short name T47
Test name
Test status
Simulation time 65719630 ps
CPU time 2.38 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:09 PM PDT 24
Peak memory 203476 kb
Host smart-c94a5081-65c1-4746-b502-0dcb9a30e2ad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182164561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.182164561
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.2259056845
Short name T198
Test name
Test status
Simulation time 1135146607 ps
CPU time 154.7 seconds
Started May 07 12:45:00 PM PDT 24
Finished May 07 12:47:36 PM PDT 24
Peak memory 211664 kb
Host smart-9669e771-d69b-456b-95f9-363e2e44fc87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2259056845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2259056845
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.566745421
Short name T802
Test name
Test status
Simulation time 961066565 ps
CPU time 11.28 seconds
Started May 07 12:45:02 PM PDT 24
Finished May 07 12:45:14 PM PDT 24
Peak memory 203992 kb
Host smart-e9c6be30-644c-4d08-9ac5-f3c06ba7d8e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=566745421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.566745421
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2832628967
Short name T507
Test name
Test status
Simulation time 501147222 ps
CPU time 187.99 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:47:57 PM PDT 24
Peak memory 209412 kb
Host smart-a2a0cc63-d564-40dc-a46b-2cd8b48ff7a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2832628967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.2832628967
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3823683618
Short name T892
Test name
Test status
Simulation time 201110793 ps
CPU time 41.49 seconds
Started May 07 12:45:14 PM PDT 24
Finished May 07 12:45:58 PM PDT 24
Peak memory 206568 kb
Host smart-01ae7ab1-ca62-4a11-8a3e-198bc0caebbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3823683618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.3823683618
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2498503373
Short name T289
Test name
Test status
Simulation time 180814324 ps
CPU time 21.26 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:35 PM PDT 24
Peak memory 205144 kb
Host smart-73470cb2-a4f3-4c6a-bb85-0d29bbc77b62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2498503373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2498503373
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2965755081
Short name T209
Test name
Test status
Simulation time 195725206 ps
CPU time 16.5 seconds
Started May 07 12:45:03 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 204596 kb
Host smart-b40c69f5-660e-455c-98d7-aef5a21452f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2965755081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2965755081
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2682654254
Short name T86
Test name
Test status
Simulation time 67044012148 ps
CPU time 272.36 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:49:50 PM PDT 24
Peak memory 206012 kb
Host smart-7a734abe-0198-4cfd-8eaa-caa5421fb041
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2682654254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.2682654254
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2711703366
Short name T514
Test name
Test status
Simulation time 683365030 ps
CPU time 21.11 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:45:38 PM PDT 24
Peak memory 203512 kb
Host smart-98daea54-9580-4caf-a56b-0fb9d8704635
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2711703366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2711703366
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.3008526750
Short name T460
Test name
Test status
Simulation time 1474167478 ps
CPU time 35.59 seconds
Started May 07 12:45:00 PM PDT 24
Finished May 07 12:45:37 PM PDT 24
Peak memory 203504 kb
Host smart-14849a39-4a30-462f-92b3-520db96e9e76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3008526750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3008526750
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.1203094409
Short name T231
Test name
Test status
Simulation time 929856394 ps
CPU time 32.98 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:39 PM PDT 24
Peak memory 204840 kb
Host smart-1f47d723-471a-40ca-8963-78490cbf62c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1203094409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1203094409
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3424733113
Short name T319
Test name
Test status
Simulation time 26463916665 ps
CPU time 102.81 seconds
Started May 07 12:45:13 PM PDT 24
Finished May 07 12:46:59 PM PDT 24
Peak memory 205144 kb
Host smart-e59bf894-9c86-4801-8a9b-d63e56b7761a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424733113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3424733113
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.550154902
Short name T162
Test name
Test status
Simulation time 50744221991 ps
CPU time 280.07 seconds
Started May 07 12:45:12 PM PDT 24
Finished May 07 12:49:54 PM PDT 24
Peak memory 205392 kb
Host smart-a46fc39a-6016-4f41-9839-c51691176a85
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=550154902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.550154902
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2348435180
Short name T174
Test name
Test status
Simulation time 524304786 ps
CPU time 23.23 seconds
Started May 07 12:45:14 PM PDT 24
Finished May 07 12:45:40 PM PDT 24
Peak memory 204624 kb
Host smart-b338c4a7-aec5-4ad5-9f78-50b6e65993b7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348435180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2348435180
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.686414537
Short name T387
Test name
Test status
Simulation time 226696248 ps
CPU time 16.65 seconds
Started May 07 12:45:15 PM PDT 24
Finished May 07 12:45:35 PM PDT 24
Peak memory 203904 kb
Host smart-ca43813a-1bc7-4995-822c-0829984ff618
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=686414537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.686414537
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.3001215421
Short name T374
Test name
Test status
Simulation time 125986867 ps
CPU time 3.58 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:44:53 PM PDT 24
Peak memory 203660 kb
Host smart-9c76d003-0d3f-4d1c-b8ac-53c7d391c911
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3001215421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3001215421
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1455409699
Short name T803
Test name
Test status
Simulation time 11294862876 ps
CPU time 35.2 seconds
Started May 07 12:45:23 PM PDT 24
Finished May 07 12:46:00 PM PDT 24
Peak memory 203508 kb
Host smart-e21b4af3-8c37-4cf5-94dc-504270e4b125
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455409699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1455409699
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.270926822
Short name T426
Test name
Test status
Simulation time 5170716509 ps
CPU time 27.37 seconds
Started May 07 12:44:52 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 203564 kb
Host smart-b3355bab-4fa6-4f84-9d26-9570a4a6afbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=270926822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.270926822
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4167182223
Short name T516
Test name
Test status
Simulation time 40977420 ps
CPU time 2.61 seconds
Started May 07 12:45:07 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 203488 kb
Host smart-c2108a25-dcbe-4d31-8b67-45d3586b28e6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167182223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4167182223
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3059846688
Short name T678
Test name
Test status
Simulation time 5659196463 ps
CPU time 76.63 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:46:28 PM PDT 24
Peak memory 205576 kb
Host smart-f22e9db9-6f40-4298-bc26-7bc273bdca9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3059846688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3059846688
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2281991250
Short name T286
Test name
Test status
Simulation time 321421894 ps
CPU time 90.03 seconds
Started May 07 12:44:55 PM PDT 24
Finished May 07 12:46:26 PM PDT 24
Peak memory 209796 kb
Host smart-7cb31b53-c65e-455b-a293-76235466ad6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281991250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2281991250
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3981422541
Short name T197
Test name
Test status
Simulation time 854070281 ps
CPU time 22.74 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:45:14 PM PDT 24
Peak memory 204984 kb
Host smart-cb9c29d8-9e82-477f-9183-4bdaa48ec465
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3981422541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3981422541
Directory /workspace/9.xbar_unmapped_addr/latest
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