Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1868	1			T8	21		T14	22		T19	16
all_values[1]	1810	1			T8	16		T14	22		T19	19
all_values[2]	1794	1			T8	23		T14	24		T19	29
all_values[3]	1766	1			T8	18		T14	13		T19	19
all_values[4]	1837	1			T8	11		T14	24		T19	23
all_values[5]	1782	1			T8	11		T14	23		T19	18
all_values[6]	1885	1			T8	20		T14	21		T19	31
all_values[7]	1813	1			T8	22		T14	26		T19	16
all_values[8]	1744	1			T8	15		T14	20		T19	23
all_values[9]	1807	1			T8	19		T14	27		T19	23
all_values[10]	1865	1			T8	19		T14	21		T19	18
all_values[11]	1853	1			T8	22		T14	14		T19	20
all_values[12]	1883	1			T8	16		T14	24		T19	25
all_values[13]	1838	1			T8	22		T14	24		T19	18
all_values[14]	1728	1			T8	18		T14	16		T19	17
all_values[15]	1789	1			T8	23		T14	21		T19	22
all_values[16]	1821	1			T8	20		T14	23		T19	15
all_values[17]	1766	1			T8	21		T14	24		T19	14
all_values[18]	1843	1			T8	22		T14	24		T19	15
all_values[19]	1793	1			T8	21		T14	22		T19	24
all_values[20]	1864	1			T8	28		T14	31		T19	32
all_values[21]	1778	1			T8	25		T14	15		T19	28
all_values[22]	1767	1			T8	16		T14	10		T19	25
all_values[23]	1779	1			T8	25		T14	24		T19	21
all_values[24]	1783	1			T8	20		T14	18		T19	13
all_values[25]	1775	1			T8	16		T14	24		T19	32
all_values[26]	1755	1			T8	25		T14	20		T19	24
all_values[27]	1903	1			T8	18		T14	17		T19	26
all_values[28]	1851	1			T8	18		T14	29		T19	23
all_values[29]	1873	1			T8	20		T14	18		T19	21
all_values[30]	1804	1			T8	19		T14	23		T19	22
all_values[31]	1848	1			T8	26		T14	13		T19	24
all_values[32]	1795	1			T8	15		T14	13		T19	23
all_values[33]	1879	1			T8	17		T14	26		T19	20
all_values[34]	1782	1			T8	25		T14	20		T19	19
all_values[35]	1796	1			T8	21		T14	23		T19	19
all_values[36]	1826	1			T8	23		T14	26		T19	18
all_values[37]	1827	1			T8	21		T14	26		T19	20
all_values[38]	1856	1			T8	19		T14	26		T19	13
all_values[39]	1783	1			T8	28		T14	18		T19	16
all_values[40]	1765	1			T8	14		T14	22		T19	16
all_values[41]	1864	1			T8	17		T14	28		T19	16
all_values[42]	1801	1			T8	20		T14	22		T19	19
all_values[43]	1853	1			T8	21		T14	28		T19	26
all_values[44]	1854	1			T8	25		T14	27		T19	27
all_values[45]	1865	1			T8	19		T14	25		T19	25
all_values[46]	1814	1			T8	25		T14	31		T19	20
all_values[47]	1778	1			T8	20		T14	25		T19	15
all_values[48]	1869	1			T8	24		T14	20		T19	15
all_values[49]	1837	1			T8	16		T14	17		T19	23
all_values[50]	1773	1			T8	23		T14	25		T19	12
all_values[51]	1803	1			T8	21		T14	20		T19	18
all_values[52]	1855	1			T8	27		T14	19		T19	28
all_values[53]	1811	1			T8	21		T14	21		T19	16
all_values[54]	1772	1			T8	16		T14	22		T19	23
all_values[55]	1840	1			T8	21		T14	30		T19	20
all_values[56]	1787	1			T8	21		T14	19		T19	11
all_values[57]	1799	1			T8	27		T14	18		T19	18
all_values[58]	1818	1			T8	13		T14	22		T19	19
all_values[59]	1817	1			T8	16		T14	21		T19	22
all_values[60]	1833	1			T8	24		T14	24		T19	22
all_values[61]	1828	1			T8	21		T14	19		T19	22
all_values[62]	1829	1			T8	11		T14	19		T19	25
all_values[63]	1800	1			T8	14		T14	33		T19	24