Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 441 1 T10 7 T11 2 T17 2
all_values[1] 498 1 T10 7 T4 1 T12 3
all_values[2] 506 1 T10 6 T11 1 T12 1
all_values[3] 504 1 T10 6 T11 1 T4 2
all_values[4] 484 1 T10 6 T11 1 T4 1
all_values[5] 480 1 T3 1 T10 7 T4 2
all_values[6] 453 1 T10 7 T11 2 T4 1
all_values[7] 427 1 T10 6 T4 1 T12 3
all_values[8] 445 1 T10 2 T4 1 T17 1
all_values[9] 417 1 T10 6 T4 1 T12 2
all_values[10] 467 1 T10 5 T17 2 T106 6
all_values[11] 449 1 T10 5 T11 2 T12 2
all_values[12] 463 1 T10 4 T11 2 T12 1
all_values[13] 445 1 T10 8 T11 1 T12 1
all_values[14] 478 1 T10 6 T11 1 T17 3
all_values[15] 442 1 T10 5 T11 2 T4 1
all_values[16] 460 1 T10 2 T17 3 T20 3
all_values[17] 464 1 T10 3 T11 4 T4 1
all_values[18] 460 1 T10 5 T11 1 T4 1
all_values[19] 410 1 T10 4 T11 2 T4 1
all_values[20] 461 1 T10 10 T17 2 T20 1
all_values[21] 439 1 T10 1 T12 1 T17 1
all_values[22] 435 1 T10 6 T4 1 T17 2
all_values[23] 423 1 T10 9 T11 1 T4 1

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