Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1581	1			T10	25		T11	1		T12	6
all_values[1]	1567	1			T10	18		T12	7		T17	2
all_values[2]	1697	1			T10	15		T12	1		T17	1
all_values[3]	1644	1			T10	24		T12	5		T17	2
all_values[4]	1543	1			T10	28		T12	4		T17	2
all_values[5]	1655	1			T10	32		T11	2		T12	4
all_values[6]	1613	1			T10	23		T11	3		T12	7
all_values[7]	1644	1			T10	27		T12	3		T17	1
all_values[8]	1684	1			T10	22		T12	2		T17	1
all_values[9]	1626	1			T10	30		T12	4		T18	2
all_values[10]	1613	1			T10	28		T12	6		T18	3
all_values[11]	1654	1			T10	24		T12	5		T17	3
all_values[12]	1558	1			T10	30		T11	1		T12	6
all_values[13]	1669	1			T10	30		T12	3		T17	2
all_values[14]	1687	1			T10	34		T12	8		T18	5
all_values[15]	1623	1			T10	23		T11	1		T12	4
all_values[16]	1718	1			T10	26		T12	2		T17	2
all_values[17]	1579	1			T10	28		T12	3		T17	1
all_values[18]	1651	1			T10	17		T12	4		T17	1
all_values[19]	1666	1			T10	22		T12	3		T17	2
all_values[20]	1621	1			T10	23		T12	10		T17	1
all_values[21]	1596	1			T10	25		T12	3		T17	1
all_values[22]	1628	1			T10	24		T18	10		T21	1
all_values[23]	1648	1			T10	25		T17	1		T18	12
all_values[24]	1592	1			T10	23		T11	2		T12	6
all_values[25]	1601	1			T10	21		T12	7		T17	1
all_values[26]	1611	1			T10	29		T12	3		T18	6
all_values[27]	1664	1			T10	22		T12	3		T17	1
all_values[28]	1599	1			T10	23		T12	4		T17	1
all_values[29]	1605	1			T10	29		T12	10		T17	2
all_values[30]	1529	1			T10	15		T12	4		T17	1
all_values[31]	1615	1			T10	25		T12	5		T17	1
all_values[32]	1653	1			T10	30		T12	4		T18	2
all_values[33]	1681	1			T10	27		T12	5		T17	1
all_values[34]	1688	1			T10	29		T12	3		T17	1
all_values[35]	1705	1			T10	19		T11	1		T12	6
all_values[36]	1678	1			T10	25		T11	1		T12	4
all_values[37]	1604	1			T10	20		T11	1		T12	3
all_values[38]	1590	1			T10	24		T12	5		T18	2
all_values[39]	1650	1			T10	26		T12	5		T17	2
all_values[40]	1609	1			T10	19		T12	5		T17	3
all_values[41]	1610	1			T10	25		T12	1		T18	7
all_values[42]	1651	1			T10	24		T11	1		T12	3
all_values[43]	1612	1			T10	24		T12	4		T18	3
all_values[44]	1594	1			T10	24		T12	3		T17	2
all_values[45]	1602	1			T10	30		T12	1		T17	1
all_values[46]	1582	1			T10	22		T12	5		T17	3
all_values[47]	1616	1			T10	19		T11	1		T12	5
all_values[48]	1624	1			T10	21		T12	3		T17	2
all_values[49]	1655	1			T10	25		T12	4		T18	8
all_values[50]	1611	1			T10	22		T12	3		T17	1
all_values[51]	1668	1			T10	18		T12	6		T17	1
all_values[52]	1694	1			T10	24		T12	3		T17	2
all_values[53]	1585	1			T10	24		T11	1		T12	6
all_values[54]	1657	1			T10	23		T11	1		T12	3
all_values[55]	1695	1			T10	33		T12	2		T17	1
all_values[56]	1649	1			T10	24		T12	6		T17	1
all_values[57]	1713	1			T10	26		T12	5		T17	3
all_values[58]	1599	1			T10	20		T12	3		T18	2
all_values[59]	1667	1			T10	27		T12	3		T17	1
all_values[60]	1619	1			T10	30		T12	3		T17	3
all_values[61]	1633	1			T10	18		T12	7		T17	1
all_values[62]	1688	1			T10	22		T12	8		T17	2
all_values[63]	1694	1			T10	23		T12	3		T17	1