Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 537 1 T12 8 T13 5 T16 2
all_values[1] 520 1 T2 1 T12 3 T13 1
all_values[2] 471 1 T2 1 T12 8 T13 5
all_values[3] 528 1 T2 1 T12 5 T13 1
all_values[4] 487 1 T2 1 T12 9 T13 2
all_values[5] 464 1 T12 12 T13 1 T16 1
all_values[6] 519 1 T2 3 T12 2 T13 4
all_values[7] 550 1 T12 7 T13 3 T16 1
all_values[8] 522 1 T12 5 T13 2 T19 1
all_values[9] 479 1 T2 1 T9 2 T12 3
all_values[10] 480 1 T2 3 T12 7 T13 4
all_values[11] 500 1 T2 3 T12 6 T13 2
all_values[12] 539 1 T2 1 T12 6 T13 2
all_values[13] 515 1 T2 1 T12 5 T13 7
all_values[14] 529 1 T2 1 T12 9 T13 3
all_values[15] 505 1 T12 8 T13 1 T17 1
all_values[16] 512 1 T12 7 T13 4 T65 1
all_values[17] 563 1 T12 11 T13 6 T19 1
all_values[18] 529 1 T12 4 T13 1 T16 1
all_values[19] 496 1 T12 12 T13 2 T19 1
all_values[20] 475 1 T2 2 T12 8 T13 2
all_values[21] 483 1 T2 1 T12 6 T13 2
all_values[22] 524 1 T9 1 T12 7 T17 1
all_values[23] 504 1 T9 2 T12 8 T13 5

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