Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1657	1			T2	7		T9	11		T10	2
all_values[1]	1720	1			T2	6		T9	7		T12	16
all_values[2]	1778	1			T2	3		T9	4		T12	16
all_values[3]	1792	1			T2	6		T9	8		T12	9
all_values[4]	1709	1			T2	10		T9	4		T12	12
all_values[5]	1822	1			T2	11		T9	4		T12	23
all_values[6]	1744	1			T2	7		T9	3		T12	21
all_values[7]	1677	1			T2	6		T9	2		T12	12
all_values[8]	1763	1			T2	3		T9	3		T12	18
all_values[9]	1761	1			T2	3		T9	2		T12	19
all_values[10]	1739	1			T2	5		T9	5		T12	18
all_values[11]	1748	1			T2	5		T9	4		T12	15
all_values[12]	1766	1			T2	3		T12	22		T13	11
all_values[13]	1757	1			T2	5		T9	9		T12	24
all_values[14]	1658	1			T2	7		T9	2		T10	1
all_values[15]	1718	1			T2	3		T9	1		T10	1
all_values[16]	1729	1			T2	2		T9	4		T10	1
all_values[17]	1776	1			T2	6		T9	4		T12	19
all_values[18]	1698	1			T2	3		T9	4		T12	19
all_values[19]	1648	1			T2	3		T9	3		T12	10
all_values[20]	1732	1			T2	4		T9	7		T12	18
all_values[21]	1686	1			T2	3		T12	17		T13	12
all_values[22]	1726	1			T2	8		T9	1		T10	1
all_values[23]	1779	1			T2	4		T9	8		T10	1
all_values[24]	1719	1			T2	4		T10	2		T12	19
all_values[25]	1701	1			T2	7		T9	7		T12	13
all_values[26]	1663	1			T2	3		T9	5		T10	1
all_values[27]	1744	1			T2	12		T9	3		T12	13
all_values[28]	1787	1			T2	4		T9	6		T12	14
all_values[29]	1766	1			T2	8		T9	5		T12	9
all_values[30]	1742	1			T2	8		T9	4		T12	16
all_values[31]	1751	1			T2	5		T9	4		T10	1
all_values[32]	1774	1			T2	10		T9	2		T10	1
all_values[33]	1780	1			T2	5		T9	1		T12	15
all_values[34]	1692	1			T2	6		T9	5		T12	21
all_values[35]	1737	1			T2	6		T9	2		T12	15
all_values[36]	1737	1			T2	4		T9	5		T10	1
all_values[37]	1773	1			T2	5		T9	5		T10	1
all_values[38]	1710	1			T2	2		T9	8		T12	8
all_values[39]	1704	1			T2	4		T9	1		T10	1
all_values[40]	1812	1			T2	3		T9	4		T12	19
all_values[41]	1777	1			T2	5		T9	8		T12	19
all_values[42]	1819	1			T2	8		T9	4		T10	1
all_values[43]	1787	1			T2	5		T9	3		T10	1
all_values[44]	1677	1			T2	7		T9	3		T12	21
all_values[45]	1843	1			T2	1		T9	4		T12	16
all_values[46]	1742	1			T2	1		T9	2		T12	12
all_values[47]	1709	1			T2	7		T12	19		T13	5
all_values[48]	1788	1			T2	4		T9	3		T12	14
all_values[49]	1771	1			T2	4		T9	5		T10	1
all_values[50]	1728	1			T2	5		T9	8		T12	14
all_values[51]	1703	1			T2	4		T9	3		T12	23
all_values[52]	1762	1			T2	4		T9	7		T12	10
all_values[53]	1731	1			T2	3		T9	4		T10	1
all_values[54]	1736	1			T2	10		T9	3		T12	13
all_values[55]	1767	1			T2	1		T9	4		T12	17
all_values[56]	1743	1			T2	7		T10	1		T12	19
all_values[57]	1731	1			T2	9		T9	4		T12	11
all_values[58]	1704	1			T2	8		T9	2		T10	1
all_values[59]	1776	1			T2	5		T9	7		T10	1
all_values[60]	1803	1			T2	3		T9	2		T12	13
all_values[61]	1681	1			T2	5		T9	6		T12	13
all_values[62]	1670	1			T2	3		T9	4		T10	1
all_values[63]	1799	1			T2	4		T9	3		T12	12