Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1767	1			T8	7		T24	2		T14	7
all_values[1]	1696	1			T8	8		T24	3		T14	10
all_values[2]	1756	1			T8	8		T24	1		T14	5
all_values[3]	1733	1			T8	9		T24	2		T14	21
all_values[4]	1768	1			T8	8		T24	4		T14	12
all_values[5]	1696	1			T8	7		T24	3		T14	9
all_values[6]	1772	1			T8	6		T24	1		T14	6
all_values[7]	1780	1			T8	5		T24	4		T14	10
all_values[8]	1767	1			T8	4		T24	5		T14	10
all_values[9]	1793	1			T8	10		T24	4		T14	7
all_values[10]	1737	1			T8	6		T24	2		T14	7
all_values[11]	1735	1			T8	9		T24	4		T14	8
all_values[12]	1684	1			T8	6		T24	3		T14	9
all_values[13]	1761	1			T8	8		T24	3		T14	11
all_values[14]	1759	1			T8	3		T24	5		T14	8
all_values[15]	1720	1			T8	7		T24	1		T14	15
all_values[16]	1687	1			T8	5		T24	4		T14	10
all_values[17]	1741	1			T8	4		T24	3		T14	7
all_values[18]	1745	1			T8	7		T24	7		T14	10
all_values[19]	1769	1			T8	10		T24	1		T14	11
all_values[20]	1711	1			T8	12		T24	4		T14	11
all_values[21]	1726	1			T8	3		T24	5		T14	14
all_values[22]	1727	1			T8	9		T24	1		T14	7
all_values[23]	1738	1			T8	7		T24	4		T14	13
all_values[24]	1719	1			T8	10		T24	2		T14	16
all_values[25]	1718	1			T8	14		T24	5		T14	11
all_values[26]	1728	1			T8	4		T24	2		T14	7
all_values[27]	1722	1			T8	11		T24	5		T14	6
all_values[28]	1729	1			T8	7		T24	1		T14	6
all_values[29]	1711	1			T8	7		T24	1		T14	16
all_values[30]	1731	1			T8	11		T24	2		T14	8
all_values[31]	1786	1			T8	10		T24	3		T14	15
all_values[32]	1843	1			T8	15		T24	1		T14	12
all_values[33]	1746	1			T8	13		T24	7		T14	10
all_values[34]	1735	1			T8	17		T24	3		T14	14
all_values[35]	1763	1			T8	6		T24	3		T14	12
all_values[36]	1683	1			T8	13		T24	4		T14	10
all_values[37]	1717	1			T8	4		T24	5		T14	10
all_values[38]	1744	1			T8	8		T24	4		T14	14
all_values[39]	1705	1			T8	5		T24	3		T14	8
all_values[40]	1701	1			T8	8		T24	5		T14	14
all_values[41]	1722	1			T8	6		T24	1		T14	9
all_values[42]	1756	1			T8	10		T24	5		T14	10
all_values[43]	1752	1			T8	8		T24	3		T14	15
all_values[44]	1746	1			T8	14		T24	2		T14	11
all_values[45]	1721	1			T8	9		T24	2		T14	8
all_values[46]	1785	1			T8	11		T24	2		T14	14
all_values[47]	1674	1			T8	8		T24	2		T14	9
all_values[48]	1724	1			T8	4		T24	2		T14	12
all_values[49]	1722	1			T8	7		T24	3		T14	23
all_values[50]	1833	1			T8	10		T24	4		T14	11
all_values[51]	1802	1			T8	7		T24	1		T14	13
all_values[52]	1807	1			T8	13		T24	3		T14	8
all_values[53]	1794	1			T8	4		T24	1		T14	11
all_values[54]	1679	1			T8	10		T24	2		T14	10
all_values[55]	1779	1			T8	8		T24	2		T14	13
all_values[56]	1753	1			T8	1		T24	2		T14	13
all_values[57]	1823	1			T8	7		T24	5		T14	9
all_values[58]	1740	1			T8	7		T24	1		T14	9
all_values[59]	1819	1			T8	8		T24	1		T14	8
all_values[60]	1782	1			T8	8		T24	3		T14	12
all_values[61]	1767	1			T8	6		T24	2		T14	5
all_values[62]	1810	1			T8	7		T24	1		T14	13
all_values[63]	1829	1			T8	11		T24	3		T14	3