| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.02 | 99.26 | 88.94 | 98.80 | 95.88 | 99.26 | 100.00 |
| T771 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.702605717 | May 16 01:56:59 PM PDT 24 | May 16 02:01:14 PM PDT 24 | 35417877002 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1682843334 | May 16 02:00:55 PM PDT 24 | May 16 02:00:58 PM PDT 24 | 62300520 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3654712225 | May 16 01:51:57 PM PDT 24 | May 16 01:57:01 PM PDT 24 | 7028079001 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/8.xbar_same_source.1053075957 | May 16 01:53:03 PM PDT 24 | May 16 01:53:18 PM PDT 24 | 2359220186 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3068564045 | May 16 01:56:54 PM PDT 24 | May 16 01:57:27 PM PDT 24 | 1346225402 ps | ||
| T61 | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1941277463 | May 16 01:58:40 PM PDT 24 | May 16 01:59:44 PM PDT 24 | 2430146443 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/34.xbar_error_random.2299311428 | May 16 01:58:14 PM PDT 24 | May 16 01:58:48 PM PDT 24 | 4900110962 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.801516216 | May 16 01:58:13 PM PDT 24 | May 16 01:58:17 PM PDT 24 | 56398160 ps | ||
| T141 | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2680232605 | May 16 01:54:41 PM PDT 24 | May 16 01:54:56 PM PDT 24 | 1248630358 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1524376441 | May 16 02:01:10 PM PDT 24 | May 16 02:01:18 PM PDT 24 | 235375422 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1960846926 | May 16 01:58:14 PM PDT 24 | May 16 01:58:46 PM PDT 24 | 3481489798 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/20.xbar_error_random.857352993 | May 16 01:55:41 PM PDT 24 | May 16 01:55:54 PM PDT 24 | 111375324 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/13.xbar_same_source.863237374 | May 16 01:53:55 PM PDT 24 | May 16 01:54:04 PM PDT 24 | 313365531 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/28.xbar_random.1820286376 | May 16 01:56:57 PM PDT 24 | May 16 01:57:08 PM PDT 24 | 230224920 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2843654489 | May 16 01:58:13 PM PDT 24 | May 16 01:58:35 PM PDT 24 | 808898335 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2209037051 | May 16 01:51:47 PM PDT 24 | May 16 01:51:51 PM PDT 24 | 39621984 ps | ||
| T139 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1235192446 | May 16 01:56:49 PM PDT 24 | May 16 01:57:30 PM PDT 24 | 1042400425 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1698235617 | May 16 01:58:02 PM PDT 24 | May 16 01:58:32 PM PDT 24 | 3077834943 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3918596380 | May 16 01:51:49 PM PDT 24 | May 16 01:53:15 PM PDT 24 | 25867703913 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3381704458 | May 16 01:56:51 PM PDT 24 | May 16 01:59:27 PM PDT 24 | 1538877844 ps | ||
| T159 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2050478732 | May 16 01:59:49 PM PDT 24 | May 16 02:00:37 PM PDT 24 | 7691956854 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4064136363 | May 16 01:59:39 PM PDT 24 | May 16 01:59:44 PM PDT 24 | 52516469 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3389160851 | May 16 01:54:17 PM PDT 24 | May 16 02:00:08 PM PDT 24 | 43997570895 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/38.xbar_smoke.3302545397 | May 16 01:58:51 PM PDT 24 | May 16 01:58:57 PM PDT 24 | 166168205 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.58740143 | May 16 01:58:51 PM PDT 24 | May 16 01:58:55 PM PDT 24 | 100942881 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2030109274 | May 16 01:55:51 PM PDT 24 | May 16 01:56:29 PM PDT 24 | 890185792 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/45.xbar_random.1488864250 | May 16 02:00:36 PM PDT 24 | May 16 02:00:45 PM PDT 24 | 188656657 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1656334271 | May 16 01:56:50 PM PDT 24 | May 16 01:57:05 PM PDT 24 | 1157043714 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3360073537 | May 16 01:58:32 PM PDT 24 | May 16 02:00:21 PM PDT 24 | 1385639637 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3722953526 | May 16 01:59:36 PM PDT 24 | May 16 02:00:16 PM PDT 24 | 1580523919 ps | ||
| T62 | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1628726872 | May 16 01:58:31 PM PDT 24 | May 16 01:59:01 PM PDT 24 | 5156291698 ps | ||
| T63 | /workspace/coverage/xbar_build_mode/43.xbar_random.36541751 | May 16 02:00:16 PM PDT 24 | May 16 02:00:33 PM PDT 24 | 199779786 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.4010113263 | May 16 01:54:40 PM PDT 24 | May 16 01:55:10 PM PDT 24 | 4577221095 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3231439032 | May 16 01:52:16 PM PDT 24 | May 16 01:52:32 PM PDT 24 | 2664502145 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3241159621 | May 16 01:58:42 PM PDT 24 | May 16 01:58:53 PM PDT 24 | 7760964 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3497967259 | May 16 02:00:17 PM PDT 24 | May 16 02:02:25 PM PDT 24 | 35163433497 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3373708599 | May 16 02:00:59 PM PDT 24 | May 16 02:01:32 PM PDT 24 | 10224563733 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2386314487 | May 16 01:51:49 PM PDT 24 | May 16 01:52:25 PM PDT 24 | 12182502840 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.4069251383 | May 16 01:59:37 PM PDT 24 | May 16 02:00:10 PM PDT 24 | 7650123012 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2981193343 | May 16 01:54:38 PM PDT 24 | May 16 01:55:06 PM PDT 24 | 1603225549 ps | ||
| T256 | /workspace/coverage/xbar_build_mode/19.xbar_same_source.369853480 | May 16 01:55:23 PM PDT 24 | May 16 01:55:45 PM PDT 24 | 791226111 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3176111109 | May 16 02:01:11 PM PDT 24 | May 16 02:01:45 PM PDT 24 | 1167676675 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2067265729 | May 16 01:56:40 PM PDT 24 | May 16 01:57:17 PM PDT 24 | 10059766006 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3054216755 | May 16 01:54:50 PM PDT 24 | May 16 01:55:07 PM PDT 24 | 103805636 ps | ||
| T64 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3952056157 | May 16 01:57:13 PM PDT 24 | May 16 01:57:46 PM PDT 24 | 6864801879 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3280163103 | May 16 02:00:43 PM PDT 24 | May 16 02:01:31 PM PDT 24 | 33552817557 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2190352254 | May 16 02:01:06 PM PDT 24 | May 16 02:02:39 PM PDT 24 | 9292980619 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3035548420 | May 16 01:52:28 PM PDT 24 | May 16 01:53:09 PM PDT 24 | 6847793488 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1615594851 | May 16 01:53:45 PM PDT 24 | May 16 01:53:56 PM PDT 24 | 52685262 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1018294227 | May 16 01:59:03 PM PDT 24 | May 16 01:59:34 PM PDT 24 | 1877358878 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.88403820 | May 16 01:52:53 PM PDT 24 | May 16 02:01:49 PM PDT 24 | 148711166219 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3721802564 | May 16 01:54:26 PM PDT 24 | May 16 01:55:10 PM PDT 24 | 1444205378 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3495324942 | May 16 01:57:20 PM PDT 24 | May 16 01:57:26 PM PDT 24 | 426792127 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2582502689 | May 16 02:00:57 PM PDT 24 | May 16 02:05:48 PM PDT 24 | 4443630542 ps | ||
| T255 | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.125381040 | May 16 01:51:57 PM PDT 24 | May 16 01:52:29 PM PDT 24 | 837580398 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.131872998 | May 16 01:53:29 PM PDT 24 | May 16 01:53:32 PM PDT 24 | 25747639 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1295085231 | May 16 01:56:39 PM PDT 24 | May 16 01:56:50 PM PDT 24 | 305752452 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2442112311 | May 16 01:58:51 PM PDT 24 | May 16 01:59:15 PM PDT 24 | 1083360591 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.4201843302 | May 16 02:00:57 PM PDT 24 | May 16 02:01:36 PM PDT 24 | 937307217 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2985329331 | May 16 01:57:54 PM PDT 24 | May 16 02:04:49 PM PDT 24 | 55037144211 ps | ||
| T142 | /workspace/coverage/xbar_build_mode/8.xbar_smoke.3992478904 | May 16 01:53:04 PM PDT 24 | May 16 01:53:09 PM PDT 24 | 293307092 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.846474904 | May 16 01:55:11 PM PDT 24 | May 16 01:55:44 PM PDT 24 | 5787936940 ps | ||
| T197 | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3797428128 | May 16 01:55:51 PM PDT 24 | May 16 01:56:08 PM PDT 24 | 79143837 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2603169146 | May 16 01:57:53 PM PDT 24 | May 16 01:58:09 PM PDT 24 | 138441347 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/30.xbar_random.3231015369 | May 16 01:57:29 PM PDT 24 | May 16 01:57:42 PM PDT 24 | 354049538 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.742026326 | May 16 01:52:08 PM PDT 24 | May 16 01:56:07 PM PDT 24 | 37518715986 ps | ||
| T35 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1344777972 | May 16 01:53:37 PM PDT 24 | May 16 01:59:26 PM PDT 24 | 885800883 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.58597927 | May 16 01:52:19 PM PDT 24 | May 16 01:53:26 PM PDT 24 | 565331919 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4190773951 | May 16 01:51:48 PM PDT 24 | May 16 01:51:52 PM PDT 24 | 79595922 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.632085318 | May 16 01:56:49 PM PDT 24 | May 16 01:57:01 PM PDT 24 | 139990700 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.506292555 | May 16 01:57:20 PM PDT 24 | May 16 01:57:30 PM PDT 24 | 82509581 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/10.xbar_same_source.2832642931 | May 16 01:53:31 PM PDT 24 | May 16 01:54:11 PM PDT 24 | 7769923163 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2493048931 | May 16 01:59:02 PM PDT 24 | May 16 01:59:26 PM PDT 24 | 88186130 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2649257950 | May 16 01:53:03 PM PDT 24 | May 16 01:53:09 PM PDT 24 | 41255287 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.776583942 | May 16 01:57:19 PM PDT 24 | May 16 01:57:23 PM PDT 24 | 15761399 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.175327321 | May 16 01:54:38 PM PDT 24 | May 16 01:55:09 PM PDT 24 | 1296418109 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/5.xbar_same_source.225047343 | May 16 01:52:25 PM PDT 24 | May 16 01:52:34 PM PDT 24 | 109125475 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/40.xbar_smoke.2069058739 | May 16 01:59:11 PM PDT 24 | May 16 01:59:17 PM PDT 24 | 240227877 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2744616401 | May 16 01:57:10 PM PDT 24 | May 16 01:57:14 PM PDT 24 | 34014165 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1473751971 | May 16 01:52:26 PM PDT 24 | May 16 01:57:24 PM PDT 24 | 57194130659 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2100228310 | May 16 01:55:24 PM PDT 24 | May 16 01:55:28 PM PDT 24 | 32858709 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.962845158 | May 16 02:00:31 PM PDT 24 | May 16 02:00:54 PM PDT 24 | 313847447 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3322288463 | May 16 01:56:20 PM PDT 24 | May 16 01:56:25 PM PDT 24 | 22012205 ps | ||
| T182 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1082853863 | May 16 01:58:03 PM PDT 24 | May 16 01:58:48 PM PDT 24 | 20419827591 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/22.xbar_random.800629428 | May 16 01:55:51 PM PDT 24 | May 16 01:56:21 PM PDT 24 | 284801320 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3621365813 | May 16 01:57:54 PM PDT 24 | May 16 01:59:03 PM PDT 24 | 1543015019 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3813424139 | May 16 01:52:20 PM PDT 24 | May 16 01:55:20 PM PDT 24 | 31937409863 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.24365446 | May 16 01:59:23 PM PDT 24 | May 16 01:59:28 PM PDT 24 | 31052429 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1062071036 | May 16 01:57:29 PM PDT 24 | May 16 01:57:35 PM PDT 24 | 42831606 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.283965482 | May 16 01:56:00 PM PDT 24 | May 16 01:56:12 PM PDT 24 | 56689111 ps | ||
| T143 | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3858625508 | May 16 02:00:17 PM PDT 24 | May 16 02:03:13 PM PDT 24 | 28447939510 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/45.xbar_smoke.3040483588 | May 16 02:00:30 PM PDT 24 | May 16 02:00:35 PM PDT 24 | 34002524 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.172013187 | May 16 02:00:31 PM PDT 24 | May 16 02:01:34 PM PDT 24 | 869552193 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.269164091 | May 16 01:53:48 PM PDT 24 | May 16 01:54:19 PM PDT 24 | 13429199912 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3068002873 | May 16 01:52:28 PM PDT 24 | May 16 01:52:53 PM PDT 24 | 5646387150 ps | ||
| T125 | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2631986625 | May 16 02:00:44 PM PDT 24 | May 16 02:01:38 PM PDT 24 | 1134418270 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2104434128 | May 16 01:53:28 PM PDT 24 | May 16 01:56:52 PM PDT 24 | 24442332841 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.4243989028 | May 16 01:55:41 PM PDT 24 | May 16 01:59:17 PM PDT 24 | 3888352477 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1702390045 | May 16 01:59:50 PM PDT 24 | May 16 01:59:54 PM PDT 24 | 33568984 ps | ||
| T144 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.566663328 | May 16 01:54:06 PM PDT 24 | May 16 01:54:09 PM PDT 24 | 62491830 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1959805258 | May 16 01:52:19 PM PDT 24 | May 16 01:52:53 PM PDT 24 | 74581215 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2224929456 | May 16 01:52:26 PM PDT 24 | May 16 01:56:42 PM PDT 24 | 1056999078 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2540019735 | May 16 02:00:28 PM PDT 24 | May 16 02:00:48 PM PDT 24 | 973799515 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.481846452 | May 16 02:01:05 PM PDT 24 | May 16 02:01:34 PM PDT 24 | 3253233200 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/12.xbar_smoke.364361012 | May 16 01:53:45 PM PDT 24 | May 16 01:53:51 PM PDT 24 | 272114015 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2136099976 | May 16 01:55:51 PM PDT 24 | May 16 01:56:01 PM PDT 24 | 589609560 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1563752169 | May 16 01:58:03 PM PDT 24 | May 16 02:00:27 PM PDT 24 | 348591966 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1871119186 | May 16 01:58:21 PM PDT 24 | May 16 01:58:56 PM PDT 24 | 5268602121 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1518772289 | May 16 01:58:13 PM PDT 24 | May 16 02:02:05 PM PDT 24 | 9597169964 ps | ||
| T213 | /workspace/coverage/xbar_build_mode/49.xbar_random.1980999820 | May 16 02:01:11 PM PDT 24 | May 16 02:01:48 PM PDT 24 | 1473884489 ps | ||
| T126 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3906543025 | May 16 01:52:17 PM PDT 24 | May 16 01:55:03 PM PDT 24 | 10038024499 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2156575390 | May 16 02:00:57 PM PDT 24 | May 16 02:01:09 PM PDT 24 | 180474360 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2329807688 | May 16 02:00:30 PM PDT 24 | May 16 02:04:27 PM PDT 24 | 15870460404 ps | ||
| T211 | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.4176272208 | May 16 02:00:29 PM PDT 24 | May 16 02:04:18 PM PDT 24 | 45645897779 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3798064080 | May 16 01:52:20 PM PDT 24 | May 16 01:52:57 PM PDT 24 | 25930846570 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2292698542 | May 16 02:00:16 PM PDT 24 | May 16 02:00:59 PM PDT 24 | 2060905479 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3770369397 | May 16 01:59:03 PM PDT 24 | May 16 02:05:29 PM PDT 24 | 16694291586 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/42.xbar_error_random.2470349999 | May 16 02:00:03 PM PDT 24 | May 16 02:00:29 PM PDT 24 | 304880949 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3245012244 | May 16 01:58:04 PM PDT 24 | May 16 01:58:09 PM PDT 24 | 27813962 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.928736887 | May 16 02:00:29 PM PDT 24 | May 16 02:00:47 PM PDT 24 | 464013045 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1207301650 | May 16 01:53:13 PM PDT 24 | May 16 01:53:22 PM PDT 24 | 206035533 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/9.xbar_random.1507738173 | May 16 01:53:13 PM PDT 24 | May 16 01:53:29 PM PDT 24 | 94793535 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.4291120345 | May 16 01:59:36 PM PDT 24 | May 16 02:00:01 PM PDT 24 | 450316285 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.279367485 | May 16 01:57:29 PM PDT 24 | May 16 01:58:04 PM PDT 24 | 583909698 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3622086410 | May 16 01:55:41 PM PDT 24 | May 16 01:56:09 PM PDT 24 | 2598310923 ps | ||
| T127 | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1922501740 | May 16 01:55:12 PM PDT 24 | May 16 02:02:52 PM PDT 24 | 46833797815 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3900754102 | May 16 01:51:49 PM PDT 24 | May 16 02:04:30 PM PDT 24 | 15708678750 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.4243178281 | May 16 02:00:58 PM PDT 24 | May 16 02:01:02 PM PDT 24 | 339514440 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3555964586 | May 16 01:59:52 PM PDT 24 | May 16 02:00:48 PM PDT 24 | 9307508437 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.4130228 | May 16 01:53:14 PM PDT 24 | May 16 01:53:37 PM PDT 24 | 1379667008 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1778276637 | May 16 01:53:46 PM PDT 24 | May 16 01:54:50 PM PDT 24 | 2723569011 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3259370953 | May 16 01:58:03 PM PDT 24 | May 16 01:59:05 PM PDT 24 | 3221282664 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2313015005 | May 16 01:52:26 PM PDT 24 | May 16 01:54:54 PM PDT 24 | 3333900386 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2226819830 | May 16 01:56:15 PM PDT 24 | May 16 01:57:26 PM PDT 24 | 1809031755 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2478644058 | May 16 01:52:09 PM PDT 24 | May 16 01:55:59 PM PDT 24 | 8374111968 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/47.xbar_smoke.3593390443 | May 16 02:00:42 PM PDT 24 | May 16 02:00:48 PM PDT 24 | 616231795 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2457941250 | May 16 01:53:43 PM PDT 24 | May 16 01:56:07 PM PDT 24 | 44166607418 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3866917981 | May 16 01:52:07 PM PDT 24 | May 16 01:52:16 PM PDT 24 | 198002341 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3118616968 | May 16 01:51:50 PM PDT 24 | May 16 01:51:54 PM PDT 24 | 38727094 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2552070367 | May 16 01:51:57 PM PDT 24 | May 16 01:52:23 PM PDT 24 | 1440831659 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1719434247 | May 16 01:53:02 PM PDT 24 | May 16 01:53:34 PM PDT 24 | 1855177402 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2547838710 | May 16 01:55:41 PM PDT 24 | May 16 01:56:22 PM PDT 24 | 17253868469 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3234815122 | May 16 02:01:04 PM PDT 24 | May 16 02:02:17 PM PDT 24 | 239427461 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/38.xbar_random.3127115924 | May 16 01:59:01 PM PDT 24 | May 16 01:59:40 PM PDT 24 | 883313491 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.4173710536 | May 16 02:01:09 PM PDT 24 | May 16 02:02:45 PM PDT 24 | 19315924520 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4077941914 | May 16 01:58:04 PM PDT 24 | May 16 02:02:15 PM PDT 24 | 7758652373 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2064716781 | May 16 01:58:30 PM PDT 24 | May 16 02:00:16 PM PDT 24 | 24037341369 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1859236146 | May 16 02:00:30 PM PDT 24 | May 16 02:04:34 PM PDT 24 | 25851232565 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2293363178 | May 16 01:57:31 PM PDT 24 | May 16 01:58:00 PM PDT 24 | 7906408667 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.4265396320 | May 16 01:56:02 PM PDT 24 | May 16 01:56:39 PM PDT 24 | 706019350 ps |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.2038473805 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 913484592 ps |
| CPU time | 35.13 seconds |
| Started | May 16 01:57:44 PM PDT 24 |
| Finished | May 16 01:58:21 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-e7f9e634-582f-406d-ac7a-cc23abdabbb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2038473805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2038473805 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3236437239 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 89475792826 ps |
| CPU time | 799.73 seconds |
| Started | May 16 01:54:27 PM PDT 24 |
| Finished | May 16 02:07:49 PM PDT 24 |
| Peak memory | 207516 kb |
| Host | smart-964f1a7f-2a67-448f-8f19-adb6bed9cc2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3236437239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.3236437239 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1011795385 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 48202323942 ps |
| CPU time | 264.36 seconds |
| Started | May 16 01:57:42 PM PDT 24 |
| Finished | May 16 02:02:08 PM PDT 24 |
| Peak memory | 206648 kb |
| Host | smart-531299e0-5ebf-4b6c-88f6-aef75714a632 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1011795385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.1011795385 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.400145422 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 51618292060 ps |
| CPU time | 401.78 seconds |
| Started | May 16 01:56:00 PM PDT 24 |
| Finished | May 16 02:02:44 PM PDT 24 |
| Peak memory | 207204 kb |
| Host | smart-6c6213b8-c0eb-448c-b335-1ca1942c6042 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=400145422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slo w_rsp.400145422 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1342371031 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 278719493 ps |
| CPU time | 67.41 seconds |
| Started | May 16 01:53:13 PM PDT 24 |
| Finished | May 16 01:54:21 PM PDT 24 |
| Peak memory | 207008 kb |
| Host | smart-94fd1dd6-683e-4d88-8abe-1b2047e7ac71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1342371031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1342371031 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.401535007 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 142407921 ps |
| CPU time | 56.33 seconds |
| Started | May 16 01:59:38 PM PDT 24 |
| Finished | May 16 02:00:38 PM PDT 24 |
| Peak memory | 208084 kb |
| Host | smart-7e6cc086-5d2c-4d17-a97b-2ce9242d4e6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=401535007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.401535007 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2630843966 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 138691351955 ps |
| CPU time | 256.51 seconds |
| Started | May 16 01:58:24 PM PDT 24 |
| Finished | May 16 02:02:42 PM PDT 24 |
| Peak memory | 204808 kb |
| Host | smart-9ebc8ccc-b43c-44e7-9f72-8bd173c0f666 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630843966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2630843966 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.259724306 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6323353345 ps |
| CPU time | 274.34 seconds |
| Started | May 16 01:53:36 PM PDT 24 |
| Finished | May 16 01:58:12 PM PDT 24 |
| Peak memory | 209708 kb |
| Host | smart-f0d5225b-b7d8-428d-975e-9d035639ccf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=259724306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.259724306 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3938960757 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 419119989 ps |
| CPU time | 118.98 seconds |
| Started | May 16 01:54:05 PM PDT 24 |
| Finished | May 16 01:56:05 PM PDT 24 |
| Peak memory | 208352 kb |
| Host | smart-325e5cb3-ced0-4cb5-aae7-05f067af4db9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3938960757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.3938960757 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2840608650 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 61210824517 ps |
| CPU time | 489.85 seconds |
| Started | May 16 02:00:58 PM PDT 24 |
| Finished | May 16 02:09:10 PM PDT 24 |
| Peak memory | 207136 kb |
| Host | smart-ccc6d042-89e4-40ff-9b61-a870becf5205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2840608650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.2840608650 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1653960251 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 9032130459 ps |
| CPU time | 358.81 seconds |
| Started | May 16 01:51:48 PM PDT 24 |
| Finished | May 16 01:57:48 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-35169b93-e4f0-43c9-8094-fbc9f21d9857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1653960251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1653960251 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3952103770 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 694264389 ps |
| CPU time | 322.62 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 02:01:19 PM PDT 24 |
| Peak memory | 220832 kb |
| Host | smart-85db7878-83ff-460b-8dbe-12faa16ecd29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3952103770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.3952103770 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3940827795 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1680217082 ps |
| CPU time | 364.65 seconds |
| Started | May 16 01:55:10 PM PDT 24 |
| Finished | May 16 02:01:16 PM PDT 24 |
| Peak memory | 209596 kb |
| Host | smart-53fac185-2c0a-496e-8044-ea1836fe0252 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3940827795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3940827795 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1027097297 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1557800970 ps |
| CPU time | 63.81 seconds |
| Started | May 16 01:57:43 PM PDT 24 |
| Finished | May 16 01:58:49 PM PDT 24 |
| Peak memory | 205480 kb |
| Host | smart-8a47eb0f-db82-4abd-a5c3-a81a6c4e548d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1027097297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1027097297 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1028560364 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 7512675772 ps |
| CPU time | 369.67 seconds |
| Started | May 16 01:54:27 PM PDT 24 |
| Finished | May 16 02:00:38 PM PDT 24 |
| Peak memory | 219896 kb |
| Host | smart-f771edd2-638a-41a0-9d1d-528bb589d903 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028560364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.1028560364 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1926350956 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 459380212 ps |
| CPU time | 142.9 seconds |
| Started | May 16 01:53:48 PM PDT 24 |
| Finished | May 16 01:56:12 PM PDT 24 |
| Peak memory | 209828 kb |
| Host | smart-0d797df5-4831-4147-9759-427093118f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1926350956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.1926350956 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.667488526 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 30115255714 ps |
| CPU time | 230.83 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 02:01:57 PM PDT 24 |
| Peak memory | 204900 kb |
| Host | smart-4dc1205f-beb3-4629-8920-76a15f50433a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=667488526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.667488526 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4152310882 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2509065975 ps |
| CPU time | 226.2 seconds |
| Started | May 16 01:58:15 PM PDT 24 |
| Finished | May 16 02:02:03 PM PDT 24 |
| Peak memory | 211704 kb |
| Host | smart-e78f5e5f-b086-4b6e-83b4-008ed6f14d78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4152310882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.4152310882 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2871216754 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 6275818681 ps |
| CPU time | 205.92 seconds |
| Started | May 16 01:55:00 PM PDT 24 |
| Finished | May 16 01:58:28 PM PDT 24 |
| Peak memory | 208844 kb |
| Host | smart-53a0d316-ca8e-42cc-a849-30d1060c5368 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2871216754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2871216754 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1112047226 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 11718385356 ps |
| CPU time | 61.5 seconds |
| Started | May 16 01:53:54 PM PDT 24 |
| Finished | May 16 01:54:58 PM PDT 24 |
| Peak memory | 204728 kb |
| Host | smart-2d268093-707b-4f95-b086-f4a4281d8a0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112047226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1112047226 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2500150145 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3109255348 ps |
| CPU time | 56.96 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:48 PM PDT 24 |
| Peak memory | 206188 kb |
| Host | smart-ea618fea-c61b-4d3b-bd05-ac2279efbf01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2500150145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2500150145 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.982116232 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 110829317216 ps |
| CPU time | 858.46 seconds |
| Started | May 16 01:51:50 PM PDT 24 |
| Finished | May 16 02:06:10 PM PDT 24 |
| Peak memory | 206108 kb |
| Host | smart-12c5a4dd-7a55-4af3-830c-867a7d7a20a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=982116232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.982116232 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3900902563 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 843097651 ps |
| CPU time | 25.02 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:16 PM PDT 24 |
| Peak memory | 203896 kb |
| Host | smart-58f3e909-0eb4-4b12-b21b-71269c4a540d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3900902563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3900902563 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.3786132556 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1779951178 ps |
| CPU time | 38.42 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:29 PM PDT 24 |
| Peak memory | 203800 kb |
| Host | smart-eaf6261f-fc5a-4f16-9736-5acdc616d558 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3786132556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3786132556 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.4168604239 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3835464496 ps |
| CPU time | 40.68 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:32 PM PDT 24 |
| Peak memory | 204712 kb |
| Host | smart-c2c8bd40-b1bb-4c8b-a888-5517c88be6aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4168604239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4168604239 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3918596380 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 25867703913 ps |
| CPU time | 83.48 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:53:15 PM PDT 24 |
| Peak memory | 204700 kb |
| Host | smart-04fd7789-ab76-416c-a6ad-5ef3c36d4e6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918596380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3918596380 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3683008725 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 25724832495 ps |
| CPU time | 192.89 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:55:03 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-4e0fe1ed-e9e9-40f5-8503-e89456d065fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3683008725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3683008725 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3118616968 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 38727094 ps |
| CPU time | 2.34 seconds |
| Started | May 16 01:51:50 PM PDT 24 |
| Finished | May 16 01:51:54 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-de1bb504-dff7-4f05-89b5-a8df0b74e73e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118616968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3118616968 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.1256104531 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 267470942 ps |
| CPU time | 20.57 seconds |
| Started | May 16 01:51:50 PM PDT 24 |
| Finished | May 16 01:52:12 PM PDT 24 |
| Peak memory | 204016 kb |
| Host | smart-96af9403-ca4a-4dd6-b73a-1547737e4f7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1256104531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1256104531 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.3669563156 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 33763477 ps |
| CPU time | 2.17 seconds |
| Started | May 16 01:51:48 PM PDT 24 |
| Finished | May 16 01:51:52 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-d376346a-4fe9-48d6-903c-8d3866c3b460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3669563156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3669563156 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1366918860 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4177848468 ps |
| CPU time | 21.86 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:13 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-61b53e64-16de-44e3-9999-8f1a772e4fe6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366918860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1366918860 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3648696782 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 11811688898 ps |
| CPU time | 35.16 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:27 PM PDT 24 |
| Peak memory | 203364 kb |
| Host | smart-e883ef69-0b9c-4d3a-ab8b-0e97ffba00a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3648696782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3648696782 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2209037051 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 39621984 ps |
| CPU time | 2.56 seconds |
| Started | May 16 01:51:47 PM PDT 24 |
| Finished | May 16 01:51:51 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-a4a8ce9a-cb51-4a9e-9c81-74e6d39f351a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209037051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2209037051 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.327418433 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 15883958410 ps |
| CPU time | 209.15 seconds |
| Started | May 16 01:51:50 PM PDT 24 |
| Finished | May 16 01:55:21 PM PDT 24 |
| Peak memory | 207180 kb |
| Host | smart-86684a4e-0f57-416c-a89d-fbfe8d33d7b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=327418433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.327418433 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1318530564 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 7344393203 ps |
| CPU time | 295.13 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:56:47 PM PDT 24 |
| Peak memory | 211544 kb |
| Host | smart-38c4370a-8505-4a63-a0ae-dd66e04e37be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1318530564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1318530564 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3900754102 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 15708678750 ps |
| CPU time | 759.38 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 02:04:30 PM PDT 24 |
| Peak memory | 228064 kb |
| Host | smart-1bbeb42a-f0be-4ab6-ad3f-8d1830b85273 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3900754102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3900754102 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.874115714 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 195247202 ps |
| CPU time | 7.01 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:51:58 PM PDT 24 |
| Peak memory | 205012 kb |
| Host | smart-b6b1ae2d-bc8d-4156-955c-ee1cf52047f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874115714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.874115714 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3651608512 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 894921857 ps |
| CPU time | 20.52 seconds |
| Started | May 16 01:51:47 PM PDT 24 |
| Finished | May 16 01:52:09 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-41e81a1b-97ec-4d3c-b7cc-006ddb54bdff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3651608512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3651608512 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3313938641 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 34444838673 ps |
| CPU time | 87.94 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:53:19 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-927182ec-d4db-47a0-8d15-41c8b2c76e29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3313938641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.3313938641 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.4252669649 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 108499099 ps |
| CPU time | 9.62 seconds |
| Started | May 16 01:51:57 PM PDT 24 |
| Finished | May 16 01:52:08 PM PDT 24 |
| Peak memory | 203380 kb |
| Host | smart-5b497345-b9cc-4bf5-8819-dafcdf0749d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4252669649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.4252669649 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.585526847 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1400487583 ps |
| CPU time | 41.42 seconds |
| Started | May 16 01:51:57 PM PDT 24 |
| Finished | May 16 01:52:40 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-9ab1d94f-cd59-40e9-bc9c-f463c2476ee6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=585526847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.585526847 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.3425758137 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 622858575 ps |
| CPU time | 24.69 seconds |
| Started | May 16 01:51:48 PM PDT 24 |
| Finished | May 16 01:52:13 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-8533adbe-f1e0-440b-b22e-5e0df752abab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3425758137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3425758137 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2942998766 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 27265525024 ps |
| CPU time | 169.92 seconds |
| Started | May 16 01:51:48 PM PDT 24 |
| Finished | May 16 01:54:39 PM PDT 24 |
| Peak memory | 205156 kb |
| Host | smart-b6eeb5a3-b540-4e1f-8cda-175c2e62d60f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942998766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2942998766 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2930741583 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1753695315 ps |
| CPU time | 12.46 seconds |
| Started | May 16 01:51:47 PM PDT 24 |
| Finished | May 16 01:52:01 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-02c38889-74d3-4c25-ab2a-fb2b1a905b2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2930741583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2930741583 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1152257271 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 228131508 ps |
| CPU time | 26.55 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:18 PM PDT 24 |
| Peak memory | 204744 kb |
| Host | smart-55368eef-9521-498b-bc9e-4743f9acbc60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152257271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1152257271 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2552070367 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1440831659 ps |
| CPU time | 24.61 seconds |
| Started | May 16 01:51:57 PM PDT 24 |
| Finished | May 16 01:52:23 PM PDT 24 |
| Peak memory | 204044 kb |
| Host | smart-d1716f41-185e-40f1-9dcc-305dcf29b21d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2552070367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2552070367 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.582781808 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 312681611 ps |
| CPU time | 3.44 seconds |
| Started | May 16 01:51:52 PM PDT 24 |
| Finished | May 16 01:51:56 PM PDT 24 |
| Peak memory | 203388 kb |
| Host | smart-de600f66-5c74-4308-8319-9f1822105068 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=582781808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.582781808 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1893669062 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 8202602275 ps |
| CPU time | 31.51 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:23 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-17330860-080c-43b6-b775-3cd4f8b3c948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893669062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1893669062 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2386314487 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 12182502840 ps |
| CPU time | 33.7 seconds |
| Started | May 16 01:51:49 PM PDT 24 |
| Finished | May 16 01:52:25 PM PDT 24 |
| Peak memory | 203460 kb |
| Host | smart-e26096c4-9acd-499a-aea4-2eb66cabd9c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2386314487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2386314487 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4190773951 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 79595922 ps |
| CPU time | 2.77 seconds |
| Started | May 16 01:51:48 PM PDT 24 |
| Finished | May 16 01:51:52 PM PDT 24 |
| Peak memory | 203420 kb |
| Host | smart-9f1da866-9a05-461e-860c-77b14c53fbef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190773951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4190773951 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1219549587 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2504875705 ps |
| CPU time | 200.46 seconds |
| Started | May 16 01:51:59 PM PDT 24 |
| Finished | May 16 01:55:21 PM PDT 24 |
| Peak memory | 211716 kb |
| Host | smart-7cc41253-3713-4b4a-96f7-a0d9009df34f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1219549587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1219549587 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2478644058 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 8374111968 ps |
| CPU time | 228.28 seconds |
| Started | May 16 01:52:09 PM PDT 24 |
| Finished | May 16 01:55:59 PM PDT 24 |
| Peak memory | 206888 kb |
| Host | smart-7752bc37-2a3a-494d-be6e-9e881b879855 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2478644058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2478644058 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3654712225 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 7028079001 ps |
| CPU time | 302.63 seconds |
| Started | May 16 01:51:57 PM PDT 24 |
| Finished | May 16 01:57:01 PM PDT 24 |
| Peak memory | 210868 kb |
| Host | smart-d2ddf35f-1676-4fb7-a9a0-7a09ff1bd098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3654712225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.3654712225 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.4129516781 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1634170576 ps |
| CPU time | 127.62 seconds |
| Started | May 16 01:52:09 PM PDT 24 |
| Finished | May 16 01:54:18 PM PDT 24 |
| Peak memory | 209256 kb |
| Host | smart-069f1514-11c9-4655-a923-1c31c8952c89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4129516781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.4129516781 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.125381040 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 837580398 ps |
| CPU time | 30.42 seconds |
| Started | May 16 01:51:57 PM PDT 24 |
| Finished | May 16 01:52:29 PM PDT 24 |
| Peak memory | 205116 kb |
| Host | smart-c0132cae-f9b5-4881-8e28-00ee43e6df2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=125381040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.125381040 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.4265538891 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1223451819 ps |
| CPU time | 29.94 seconds |
| Started | May 16 01:53:27 PM PDT 24 |
| Finished | May 16 01:53:58 PM PDT 24 |
| Peak memory | 204744 kb |
| Host | smart-894c6dd9-da81-4b68-9279-a70e8e229517 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4265538891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.4265538891 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2104434128 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 24442332841 ps |
| CPU time | 202.9 seconds |
| Started | May 16 01:53:28 PM PDT 24 |
| Finished | May 16 01:56:52 PM PDT 24 |
| Peak memory | 206340 kb |
| Host | smart-fcb82785-065f-4c9c-ad87-5b588c623cb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2104434128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2104434128 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3443762595 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 239252696 ps |
| CPU time | 9.88 seconds |
| Started | May 16 01:53:44 PM PDT 24 |
| Finished | May 16 01:53:56 PM PDT 24 |
| Peak memory | 203456 kb |
| Host | smart-4e5129b3-a8b2-4c6f-9a54-fbd7448cfddf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3443762595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3443762595 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.137213812 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 951050936 ps |
| CPU time | 30.66 seconds |
| Started | May 16 01:53:36 PM PDT 24 |
| Finished | May 16 01:54:07 PM PDT 24 |
| Peak memory | 203668 kb |
| Host | smart-40013ae1-e4c7-441c-8f45-6987f46fa533 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=137213812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.137213812 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.3557112446 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1483154538 ps |
| CPU time | 18.48 seconds |
| Started | May 16 01:53:26 PM PDT 24 |
| Finished | May 16 01:53:45 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-8eaf6134-a904-4b11-ac83-83ef5994b9f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3557112446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3557112446 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1430769308 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 30014269624 ps |
| CPU time | 130.01 seconds |
| Started | May 16 01:53:27 PM PDT 24 |
| Finished | May 16 01:55:38 PM PDT 24 |
| Peak memory | 204864 kb |
| Host | smart-038e23d3-0b88-4f0b-b083-26e08af494ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430769308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1430769308 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1977696319 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 170892023331 ps |
| CPU time | 384.83 seconds |
| Started | May 16 01:53:28 PM PDT 24 |
| Finished | May 16 01:59:53 PM PDT 24 |
| Peak memory | 211664 kb |
| Host | smart-9ae01ef4-ec1d-4e09-bf75-4c60bf82a2b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1977696319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1977696319 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1092185571 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 176941594 ps |
| CPU time | 22.02 seconds |
| Started | May 16 01:53:27 PM PDT 24 |
| Finished | May 16 01:53:50 PM PDT 24 |
| Peak memory | 204764 kb |
| Host | smart-2740cae8-76ad-436e-85ee-ac8560a912c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092185571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1092185571 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.2832642931 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 7769923163 ps |
| CPU time | 39.47 seconds |
| Started | May 16 01:53:31 PM PDT 24 |
| Finished | May 16 01:54:11 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-b6f43416-5b5b-4988-950f-94e7c851d0c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2832642931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2832642931 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.1497983657 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 163267959 ps |
| CPU time | 4.32 seconds |
| Started | May 16 01:53:26 PM PDT 24 |
| Finished | May 16 01:53:31 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-b9fbcc20-8230-44e7-910f-7bd2aaeee327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1497983657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1497983657 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3950471852 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 13489178337 ps |
| CPU time | 30.74 seconds |
| Started | May 16 01:53:26 PM PDT 24 |
| Finished | May 16 01:53:58 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-38469d85-f8a8-4f6b-a73b-aa6f7894c069 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950471852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3950471852 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.4062900427 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 9456846916 ps |
| CPU time | 40.87 seconds |
| Started | May 16 01:53:29 PM PDT 24 |
| Finished | May 16 01:54:11 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-cec69c19-32df-4072-8af8-9bdb51605f33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4062900427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.4062900427 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.131872998 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 25747639 ps |
| CPU time | 2.21 seconds |
| Started | May 16 01:53:29 PM PDT 24 |
| Finished | May 16 01:53:32 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-1289aa7f-1b73-44df-9e5c-0c0440903bac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131872998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.131872998 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3819762309 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3300547380 ps |
| CPU time | 69.23 seconds |
| Started | May 16 01:53:38 PM PDT 24 |
| Finished | May 16 01:54:49 PM PDT 24 |
| Peak memory | 205132 kb |
| Host | smart-e337a726-514a-4549-9051-3244f1d04d93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3819762309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3819762309 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1344777972 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 885800883 ps |
| CPU time | 346.6 seconds |
| Started | May 16 01:53:37 PM PDT 24 |
| Finished | May 16 01:59:26 PM PDT 24 |
| Peak memory | 209900 kb |
| Host | smart-0e32f065-59a5-4405-a583-ee82e774f1b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1344777972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.1344777972 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2500477813 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 199401683 ps |
| CPU time | 37.03 seconds |
| Started | May 16 01:53:37 PM PDT 24 |
| Finished | May 16 01:54:16 PM PDT 24 |
| Peak memory | 206580 kb |
| Host | smart-4a264d40-bed7-482f-bcc4-16e2acc51abf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2500477813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2500477813 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1615594851 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 52685262 ps |
| CPU time | 8.46 seconds |
| Started | May 16 01:53:45 PM PDT 24 |
| Finished | May 16 01:53:56 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-edafdae5-c6d9-439b-8816-fd6f0ca0ed63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1615594851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1615594851 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2707894069 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 482531068 ps |
| CPU time | 16.83 seconds |
| Started | May 16 01:53:46 PM PDT 24 |
| Finished | May 16 01:54:05 PM PDT 24 |
| Peak memory | 211596 kb |
| Host | smart-d047d190-e7a8-48d0-8ecc-04ccf3a536d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2707894069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2707894069 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1379395244 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 83502694407 ps |
| CPU time | 270.78 seconds |
| Started | May 16 01:53:45 PM PDT 24 |
| Finished | May 16 01:58:18 PM PDT 24 |
| Peak memory | 211624 kb |
| Host | smart-bb22c638-b3c9-40c8-b37a-6c980904aced |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1379395244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1379395244 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3079701475 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 538312686 ps |
| CPU time | 26.89 seconds |
| Started | May 16 01:53:43 PM PDT 24 |
| Finished | May 16 01:54:12 PM PDT 24 |
| Peak memory | 204016 kb |
| Host | smart-5938f092-27b8-43d1-9a40-0d20ac571734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3079701475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3079701475 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1170401362 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 81259549 ps |
| CPU time | 7.66 seconds |
| Started | May 16 01:53:44 PM PDT 24 |
| Finished | May 16 01:53:53 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-328b39b0-c040-44c8-b7e2-be65fb351b1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1170401362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1170401362 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1155970247 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 109955490 ps |
| CPU time | 4.39 seconds |
| Started | May 16 01:53:37 PM PDT 24 |
| Finished | May 16 01:53:44 PM PDT 24 |
| Peak memory | 203968 kb |
| Host | smart-9277df75-0451-44e3-a337-571617b3fb03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1155970247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1155970247 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2457941250 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 44166607418 ps |
| CPU time | 141.73 seconds |
| Started | May 16 01:53:43 PM PDT 24 |
| Finished | May 16 01:56:07 PM PDT 24 |
| Peak memory | 205044 kb |
| Host | smart-40ed8ca5-17b1-4a3f-b96c-2fddf9959190 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457941250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2457941250 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.660162295 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 24758813253 ps |
| CPU time | 186.13 seconds |
| Started | May 16 01:53:44 PM PDT 24 |
| Finished | May 16 01:56:52 PM PDT 24 |
| Peak memory | 205268 kb |
| Host | smart-529164db-d086-4e02-8edd-8b0bc557be36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=660162295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.660162295 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1288365666 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 196319070 ps |
| CPU time | 21.04 seconds |
| Started | May 16 01:53:36 PM PDT 24 |
| Finished | May 16 01:53:59 PM PDT 24 |
| Peak memory | 205128 kb |
| Host | smart-24186409-c52f-420a-9ca1-5515067a9047 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288365666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1288365666 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2634792639 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1216387662 ps |
| CPU time | 10.89 seconds |
| Started | May 16 01:53:46 PM PDT 24 |
| Finished | May 16 01:53:59 PM PDT 24 |
| Peak memory | 204040 kb |
| Host | smart-2d401cf2-2f0f-42fb-9a1a-140af15675f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2634792639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2634792639 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.1737349256 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 27895264 ps |
| CPU time | 2.18 seconds |
| Started | May 16 01:53:46 PM PDT 24 |
| Finished | May 16 01:53:50 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-68390aea-1b69-45b6-90ff-350669049d8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1737349256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1737349256 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3085738077 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 8553517152 ps |
| CPU time | 31.91 seconds |
| Started | May 16 01:53:45 PM PDT 24 |
| Finished | May 16 01:54:19 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-98b7dc63-7d32-4e84-9044-610a541fb840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085738077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3085738077 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3396959978 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3543792815 ps |
| CPU time | 25.3 seconds |
| Started | May 16 01:53:37 PM PDT 24 |
| Finished | May 16 01:54:04 PM PDT 24 |
| Peak memory | 203484 kb |
| Host | smart-50461e0e-3ac7-419c-b913-d4d9cb5de3ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3396959978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3396959978 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3401168473 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 27390713 ps |
| CPU time | 2.28 seconds |
| Started | May 16 01:53:39 PM PDT 24 |
| Finished | May 16 01:53:43 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-d08a4735-0cce-4a57-95d3-2a88b469cfb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401168473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3401168473 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1778276637 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2723569011 ps |
| CPU time | 61.52 seconds |
| Started | May 16 01:53:46 PM PDT 24 |
| Finished | May 16 01:54:50 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-ec8c5da2-ced1-4f9e-b304-448aeef88f6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1778276637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1778276637 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1527936881 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 874145809 ps |
| CPU time | 28.21 seconds |
| Started | May 16 01:53:39 PM PDT 24 |
| Finished | May 16 01:54:08 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-d75500a6-f4ed-49c5-ad4d-114365def01e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1527936881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1527936881 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1856541657 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1703214310 ps |
| CPU time | 187.55 seconds |
| Started | May 16 01:53:44 PM PDT 24 |
| Finished | May 16 01:56:53 PM PDT 24 |
| Peak memory | 208560 kb |
| Host | smart-2b2d9253-865e-4218-971a-8b8bc77e4231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1856541657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.1856541657 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3012822903 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 141080116 ps |
| CPU time | 24.8 seconds |
| Started | May 16 01:53:37 PM PDT 24 |
| Finished | May 16 01:54:04 PM PDT 24 |
| Peak memory | 206088 kb |
| Host | smart-962e220c-a03e-40bb-b64e-4a237eb2ef2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3012822903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.3012822903 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.300955923 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 231500704 ps |
| CPU time | 4.21 seconds |
| Started | May 16 01:53:37 PM PDT 24 |
| Finished | May 16 01:53:43 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-247ec40a-4f9e-4613-a656-c5595985ef33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=300955923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.300955923 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2343937267 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 5122744959 ps |
| CPU time | 73.7 seconds |
| Started | May 16 01:53:48 PM PDT 24 |
| Finished | May 16 01:55:03 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-e0b5be76-a1b4-452c-8567-6272884162a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2343937267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2343937267 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2460249682 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 14804411124 ps |
| CPU time | 81.14 seconds |
| Started | May 16 01:53:48 PM PDT 24 |
| Finished | May 16 01:55:11 PM PDT 24 |
| Peak memory | 211704 kb |
| Host | smart-23df0268-be1d-4394-9c6b-3d1743ca8944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2460249682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2460249682 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.41295426 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 38140225 ps |
| CPU time | 2.01 seconds |
| Started | May 16 01:53:54 PM PDT 24 |
| Finished | May 16 01:53:58 PM PDT 24 |
| Peak memory | 203340 kb |
| Host | smart-59ee0e59-f5b5-4567-b667-001033621565 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41295426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.41295426 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.607370819 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 275044249 ps |
| CPU time | 12.6 seconds |
| Started | May 16 01:53:54 PM PDT 24 |
| Finished | May 16 01:54:09 PM PDT 24 |
| Peak memory | 203352 kb |
| Host | smart-6e6dd908-0b4d-454d-9d7a-b54b5511d61d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=607370819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.607370819 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.1381409983 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 587393576 ps |
| CPU time | 9.66 seconds |
| Started | May 16 01:53:44 PM PDT 24 |
| Finished | May 16 01:53:56 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-de577163-ee96-422e-9205-d6183ebc932a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1381409983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1381409983 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.4274020587 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 5207484715 ps |
| CPU time | 48.38 seconds |
| Started | May 16 01:53:50 PM PDT 24 |
| Finished | May 16 01:54:39 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-ecbba875-6ab7-4235-b10f-6d81fe5f7e75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4274020587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4274020587 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3914966495 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 263430091 ps |
| CPU time | 7.42 seconds |
| Started | May 16 01:53:47 PM PDT 24 |
| Finished | May 16 01:53:56 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-da9a1027-522b-45ef-9b81-cddb5cd541d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914966495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3914966495 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.1272075848 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1249222797 ps |
| CPU time | 23.54 seconds |
| Started | May 16 01:53:54 PM PDT 24 |
| Finished | May 16 01:54:20 PM PDT 24 |
| Peak memory | 203904 kb |
| Host | smart-d4787f08-0491-4312-89fb-c5487d9d5a60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1272075848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1272075848 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.364361012 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 272114015 ps |
| CPU time | 3.39 seconds |
| Started | May 16 01:53:45 PM PDT 24 |
| Finished | May 16 01:53:51 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-1d8454ea-f602-42ed-a191-82bab45ac29b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=364361012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.364361012 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2088155823 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 4499991298 ps |
| CPU time | 27.91 seconds |
| Started | May 16 01:53:38 PM PDT 24 |
| Finished | May 16 01:54:08 PM PDT 24 |
| Peak memory | 203484 kb |
| Host | smart-118d4b06-d352-4937-9b81-682dc9ff673a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088155823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2088155823 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1105131177 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4700061683 ps |
| CPU time | 38.53 seconds |
| Started | May 16 01:53:44 PM PDT 24 |
| Finished | May 16 01:54:24 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-efb3e688-8469-49a3-b673-f6a4add4a844 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1105131177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1105131177 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.937312385 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 56461684 ps |
| CPU time | 2.37 seconds |
| Started | May 16 01:53:36 PM PDT 24 |
| Finished | May 16 01:53:40 PM PDT 24 |
| Peak memory | 203420 kb |
| Host | smart-af0e69f7-dd5f-41c3-afd7-65783f917f05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937312385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.937312385 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.885419674 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3226503272 ps |
| CPU time | 99.96 seconds |
| Started | May 16 01:53:54 PM PDT 24 |
| Finished | May 16 01:55:36 PM PDT 24 |
| Peak memory | 205336 kb |
| Host | smart-e8ec93d7-5f87-4980-8328-8aec452e707d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=885419674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.885419674 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3031719544 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5964634215 ps |
| CPU time | 221.97 seconds |
| Started | May 16 01:53:47 PM PDT 24 |
| Finished | May 16 01:57:31 PM PDT 24 |
| Peak memory | 207868 kb |
| Host | smart-b28a1e34-ed97-478a-81e3-f26647a5437c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3031719544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3031719544 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1785893231 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 7243376774 ps |
| CPU time | 99.62 seconds |
| Started | May 16 01:53:50 PM PDT 24 |
| Finished | May 16 01:55:30 PM PDT 24 |
| Peak memory | 208348 kb |
| Host | smart-c6c8b2f3-1dd5-42fc-a69b-a1dc6d27024b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1785893231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1785893231 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2326755572 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 166504952 ps |
| CPU time | 7.22 seconds |
| Started | May 16 01:53:48 PM PDT 24 |
| Finished | May 16 01:53:57 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-2ca80c04-2d26-4635-9c9d-66227ad51949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2326755572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2326755572 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1151857477 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 918615590 ps |
| CPU time | 41.89 seconds |
| Started | May 16 01:53:56 PM PDT 24 |
| Finished | May 16 01:54:40 PM PDT 24 |
| Peak memory | 205544 kb |
| Host | smart-761b0611-43ce-4c3b-ad7c-e060ad887617 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1151857477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1151857477 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2875378588 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 106258372604 ps |
| CPU time | 606.96 seconds |
| Started | May 16 01:53:56 PM PDT 24 |
| Finished | May 16 02:04:05 PM PDT 24 |
| Peak memory | 207704 kb |
| Host | smart-d8063bef-7cc1-42d1-827d-6a25ea513dac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2875378588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2875378588 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.4114480666 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 51512544 ps |
| CPU time | 4.61 seconds |
| Started | May 16 01:53:57 PM PDT 24 |
| Finished | May 16 01:54:03 PM PDT 24 |
| Peak memory | 203512 kb |
| Host | smart-50f62e1a-a4b5-4bb7-aa98-3b839ba29dac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4114480666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.4114480666 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.3772456030 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 252374091 ps |
| CPU time | 24.52 seconds |
| Started | May 16 01:53:57 PM PDT 24 |
| Finished | May 16 01:54:22 PM PDT 24 |
| Peak memory | 203420 kb |
| Host | smart-424ed3b1-d99a-4385-b8c9-4e40545fca47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3772456030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3772456030 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.1660496857 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 269815454 ps |
| CPU time | 9.37 seconds |
| Started | May 16 01:53:56 PM PDT 24 |
| Finished | May 16 01:54:07 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-cc5ef27d-80b5-46e1-ad09-7ecc5eb14acb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1660496857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1660496857 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3677572216 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 37548845797 ps |
| CPU time | 196.97 seconds |
| Started | May 16 01:53:57 PM PDT 24 |
| Finished | May 16 01:57:15 PM PDT 24 |
| Peak memory | 204984 kb |
| Host | smart-11e45989-f63b-4a4e-916b-16e9f82df165 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677572216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3677572216 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2627960305 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 25505696518 ps |
| CPU time | 173.43 seconds |
| Started | May 16 01:53:54 PM PDT 24 |
| Finished | May 16 01:56:50 PM PDT 24 |
| Peak memory | 205272 kb |
| Host | smart-d2753f5e-a1e1-4e28-a250-3bae0ed0f3d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2627960305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2627960305 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3945401167 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 121648154 ps |
| CPU time | 18.43 seconds |
| Started | May 16 01:53:54 PM PDT 24 |
| Finished | May 16 01:54:14 PM PDT 24 |
| Peak memory | 211536 kb |
| Host | smart-12985c03-15b6-4bff-8ba0-4781ba4a9688 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945401167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3945401167 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.863237374 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 313365531 ps |
| CPU time | 7.12 seconds |
| Started | May 16 01:53:55 PM PDT 24 |
| Finished | May 16 01:54:04 PM PDT 24 |
| Peak memory | 203568 kb |
| Host | smart-35a68014-d7fe-4453-9045-f4dbce4f445c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863237374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.863237374 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.4257932150 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 228498207 ps |
| CPU time | 3.82 seconds |
| Started | May 16 01:53:47 PM PDT 24 |
| Finished | May 16 01:53:52 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-aa644cb6-a361-4623-aa1f-8dd2f5390027 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257932150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4257932150 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.269164091 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 13429199912 ps |
| CPU time | 29.88 seconds |
| Started | May 16 01:53:48 PM PDT 24 |
| Finished | May 16 01:54:19 PM PDT 24 |
| Peak memory | 203492 kb |
| Host | smart-5b37d50c-c05f-4561-ae1b-1e0399f6a062 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=269164091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.269164091 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1873867549 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3463688758 ps |
| CPU time | 20.7 seconds |
| Started | May 16 01:53:45 PM PDT 24 |
| Finished | May 16 01:54:08 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-d73e5601-2d49-4ad8-bbd3-8a9a5ff4079c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1873867549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1873867549 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.766848232 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 36182156 ps |
| CPU time | 2.16 seconds |
| Started | May 16 01:53:48 PM PDT 24 |
| Finished | May 16 01:53:52 PM PDT 24 |
| Peak memory | 203320 kb |
| Host | smart-b152da76-94cd-42b0-805b-b14e9676aac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766848232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.766848232 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2248999706 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 227974764 ps |
| CPU time | 18.83 seconds |
| Started | May 16 01:54:07 PM PDT 24 |
| Finished | May 16 01:54:27 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-61fecaea-b745-481b-9429-3c1ae6d5a537 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2248999706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2248999706 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.386330845 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 6659156113 ps |
| CPU time | 114.26 seconds |
| Started | May 16 01:54:05 PM PDT 24 |
| Finished | May 16 01:56:00 PM PDT 24 |
| Peak memory | 211604 kb |
| Host | smart-50735afc-4529-4230-9ea5-8c5e19a9d495 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=386330845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.386330845 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1274474634 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 705061075 ps |
| CPU time | 211.25 seconds |
| Started | May 16 01:54:08 PM PDT 24 |
| Finished | May 16 01:57:40 PM PDT 24 |
| Peak memory | 211576 kb |
| Host | smart-102e40e9-fa0a-43a2-a460-2959769bff57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1274474634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1274474634 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3314313242 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 345417065 ps |
| CPU time | 13.83 seconds |
| Started | May 16 01:53:55 PM PDT 24 |
| Finished | May 16 01:54:11 PM PDT 24 |
| Peak memory | 204784 kb |
| Host | smart-2c621b36-9231-4372-97e8-6d1595a90ea9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3314313242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3314313242 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.742876877 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 81535786 ps |
| CPU time | 7.38 seconds |
| Started | May 16 01:54:16 PM PDT 24 |
| Finished | May 16 01:54:24 PM PDT 24 |
| Peak memory | 204160 kb |
| Host | smart-04bcde92-06ba-4d05-8355-524ddcb32e13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742876877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.742876877 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3389160851 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 43997570895 ps |
| CPU time | 350.46 seconds |
| Started | May 16 01:54:17 PM PDT 24 |
| Finished | May 16 02:00:08 PM PDT 24 |
| Peak memory | 205912 kb |
| Host | smart-945c9f12-324d-4fda-9842-937f7be32a43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3389160851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3389160851 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1336660659 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 532805903 ps |
| CPU time | 13.1 seconds |
| Started | May 16 01:54:16 PM PDT 24 |
| Finished | May 16 01:54:30 PM PDT 24 |
| Peak memory | 203936 kb |
| Host | smart-f708f695-5570-49ec-8102-9a6228ed8a18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1336660659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1336660659 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.3115511987 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 585086913 ps |
| CPU time | 19.61 seconds |
| Started | May 16 01:54:16 PM PDT 24 |
| Finished | May 16 01:54:36 PM PDT 24 |
| Peak memory | 203476 kb |
| Host | smart-fa95e5e8-a728-4d59-8ea7-2ee7dac4ed17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3115511987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3115511987 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.811461559 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1036634285 ps |
| CPU time | 35.8 seconds |
| Started | May 16 01:54:16 PM PDT 24 |
| Finished | May 16 01:54:53 PM PDT 24 |
| Peak memory | 204836 kb |
| Host | smart-37986fa9-8a69-48fd-b540-8dc733660f41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=811461559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.811461559 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1537927126 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 50572021032 ps |
| CPU time | 181.98 seconds |
| Started | May 16 01:54:17 PM PDT 24 |
| Finished | May 16 01:57:20 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-c654c3ae-daa5-4991-b88b-95abc33e8b99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537927126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1537927126 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3942939304 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 25484736072 ps |
| CPU time | 114.25 seconds |
| Started | May 16 01:54:15 PM PDT 24 |
| Finished | May 16 01:56:10 PM PDT 24 |
| Peak memory | 205028 kb |
| Host | smart-8da781bb-54fe-4c88-9e37-8260b9d3f2b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3942939304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3942939304 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2784276446 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 96582994 ps |
| CPU time | 10.33 seconds |
| Started | May 16 01:54:18 PM PDT 24 |
| Finished | May 16 01:54:29 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-07320b46-751b-4704-b391-36172faf8db1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784276446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2784276446 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.3456054333 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 599927216 ps |
| CPU time | 8.96 seconds |
| Started | May 16 01:54:16 PM PDT 24 |
| Finished | May 16 01:54:26 PM PDT 24 |
| Peak memory | 204044 kb |
| Host | smart-9f45f7cd-49c2-49ac-b6a7-801e16800a5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3456054333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3456054333 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.48554415 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 124304640 ps |
| CPU time | 3.03 seconds |
| Started | May 16 01:54:06 PM PDT 24 |
| Finished | May 16 01:54:10 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-d051c4bf-47d8-4c7b-ad78-e13603fb7a53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=48554415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.48554415 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.279582324 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 11707760156 ps |
| CPU time | 29.97 seconds |
| Started | May 16 01:54:07 PM PDT 24 |
| Finished | May 16 01:54:38 PM PDT 24 |
| Peak memory | 203492 kb |
| Host | smart-f925f819-d376-4af6-b02c-dc518583ca63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=279582324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.279582324 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2678906909 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 8338175138 ps |
| CPU time | 31.71 seconds |
| Started | May 16 01:54:07 PM PDT 24 |
| Finished | May 16 01:54:40 PM PDT 24 |
| Peak memory | 203456 kb |
| Host | smart-0b8360bd-3c95-45ae-b552-7befd8584a90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2678906909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2678906909 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.566663328 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 62491830 ps |
| CPU time | 2.29 seconds |
| Started | May 16 01:54:06 PM PDT 24 |
| Finished | May 16 01:54:09 PM PDT 24 |
| Peak memory | 203400 kb |
| Host | smart-903542b8-14fc-40b3-b04a-e43da4770a61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566663328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.566663328 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3391698540 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 603195740 ps |
| CPU time | 77.17 seconds |
| Started | May 16 01:54:16 PM PDT 24 |
| Finished | May 16 01:55:34 PM PDT 24 |
| Peak memory | 205520 kb |
| Host | smart-9bb73f82-e91f-4b09-8bd3-89beffd8eed9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3391698540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3391698540 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2123288125 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 45486060495 ps |
| CPU time | 400.18 seconds |
| Started | May 16 01:54:29 PM PDT 24 |
| Finished | May 16 02:01:10 PM PDT 24 |
| Peak memory | 207672 kb |
| Host | smart-0e4e218b-4810-4f4a-ace3-86b38541f1ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123288125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2123288125 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.24274839 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 88339983 ps |
| CPU time | 12.32 seconds |
| Started | May 16 01:54:18 PM PDT 24 |
| Finished | May 16 01:54:31 PM PDT 24 |
| Peak memory | 205288 kb |
| Host | smart-75694fdf-e2d1-4944-bd96-b0df34324914 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24274839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_ reset.24274839 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1150008912 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 278751122 ps |
| CPU time | 9.63 seconds |
| Started | May 16 01:54:16 PM PDT 24 |
| Finished | May 16 01:54:26 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-ef0563ff-f7b8-44e4-a5bd-4be75928c4d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1150008912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1150008912 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3721802564 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1444205378 ps |
| CPU time | 43.23 seconds |
| Started | May 16 01:54:26 PM PDT 24 |
| Finished | May 16 01:55:10 PM PDT 24 |
| Peak memory | 205924 kb |
| Host | smart-d9c572cb-2cda-44ff-8b6f-c29098f95f37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3721802564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3721802564 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.4096516961 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 117520987 ps |
| CPU time | 3.42 seconds |
| Started | May 16 01:54:38 PM PDT 24 |
| Finished | May 16 01:54:43 PM PDT 24 |
| Peak memory | 203396 kb |
| Host | smart-9fb44d6c-068a-4b69-bc99-613cc1cdce1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096516961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4096516961 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.278699850 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 262401383 ps |
| CPU time | 8.05 seconds |
| Started | May 16 01:54:39 PM PDT 24 |
| Finished | May 16 01:54:50 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-1bf3c9df-bb54-4bff-b6b4-77687489b013 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=278699850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.278699850 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.68538454 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 432896273 ps |
| CPU time | 29.03 seconds |
| Started | May 16 01:54:28 PM PDT 24 |
| Finished | May 16 01:54:59 PM PDT 24 |
| Peak memory | 205080 kb |
| Host | smart-a8241232-b9e8-4ee2-aa0b-97d355bc0b26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=68538454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.68538454 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1171648751 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 5860227554 ps |
| CPU time | 33.22 seconds |
| Started | May 16 01:54:28 PM PDT 24 |
| Finished | May 16 01:55:03 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-6f865a70-d198-4897-98f0-e4b0a6e8fc45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171648751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1171648751 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1772709741 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 19292865771 ps |
| CPU time | 184.32 seconds |
| Started | May 16 01:54:29 PM PDT 24 |
| Finished | May 16 01:57:35 PM PDT 24 |
| Peak memory | 204676 kb |
| Host | smart-48df8405-277b-4435-89b2-0b67ec16949d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1772709741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1772709741 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1903379259 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 416669326 ps |
| CPU time | 9.9 seconds |
| Started | May 16 01:54:28 PM PDT 24 |
| Finished | May 16 01:54:40 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-ee178b82-2447-4613-a282-37b8133eb143 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903379259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1903379259 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.1762355720 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1121196836 ps |
| CPU time | 18.62 seconds |
| Started | May 16 01:54:27 PM PDT 24 |
| Finished | May 16 01:54:46 PM PDT 24 |
| Peak memory | 204200 kb |
| Host | smart-86f5bef9-4d5f-4309-9ecd-217a98fe8c62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1762355720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1762355720 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.3851542973 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 142905912 ps |
| CPU time | 2.52 seconds |
| Started | May 16 01:54:28 PM PDT 24 |
| Finished | May 16 01:54:32 PM PDT 24 |
| Peak memory | 203328 kb |
| Host | smart-38379bfa-9e48-4f85-bb58-fddba94e39db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3851542973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3851542973 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2078521954 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 12117468896 ps |
| CPU time | 34.04 seconds |
| Started | May 16 01:54:27 PM PDT 24 |
| Finished | May 16 01:55:02 PM PDT 24 |
| Peak memory | 203476 kb |
| Host | smart-ee66ef1c-26a4-4937-95ae-f5a9e2768754 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078521954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2078521954 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3294926744 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 5629682510 ps |
| CPU time | 27.88 seconds |
| Started | May 16 01:54:28 PM PDT 24 |
| Finished | May 16 01:54:58 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-ceb0a85b-bca7-483f-82db-282532400200 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3294926744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3294926744 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2269131884 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 46594470 ps |
| CPU time | 2.46 seconds |
| Started | May 16 01:54:27 PM PDT 24 |
| Finished | May 16 01:54:31 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-4669b8ed-7cc9-49a7-a9a3-dd156d71a4d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269131884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2269131884 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1872344129 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3295586006 ps |
| CPU time | 114.38 seconds |
| Started | May 16 01:54:41 PM PDT 24 |
| Finished | May 16 01:56:38 PM PDT 24 |
| Peak memory | 208188 kb |
| Host | smart-d63acc25-1dd7-4f5f-a6d9-d1d2be98195c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1872344129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1872344129 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1301867484 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3192529588 ps |
| CPU time | 124.41 seconds |
| Started | May 16 01:54:38 PM PDT 24 |
| Finished | May 16 01:56:43 PM PDT 24 |
| Peak memory | 207760 kb |
| Host | smart-7cadfde3-7bb2-4a67-b64e-6afe716c6211 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301867484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1301867484 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1028473279 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7131893060 ps |
| CPU time | 459.31 seconds |
| Started | May 16 01:54:39 PM PDT 24 |
| Finished | May 16 02:02:19 PM PDT 24 |
| Peak memory | 209776 kb |
| Host | smart-a4c106f3-10e9-47f5-81f1-e56e80a8ca5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028473279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.1028473279 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.350951353 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 108521480 ps |
| CPU time | 21.62 seconds |
| Started | May 16 01:54:40 PM PDT 24 |
| Finished | May 16 01:55:05 PM PDT 24 |
| Peak memory | 205900 kb |
| Host | smart-f37870c8-e2e6-4e6c-afc0-5821c0f8da98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=350951353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res et_error.350951353 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.175327321 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1296418109 ps |
| CPU time | 29.52 seconds |
| Started | May 16 01:54:38 PM PDT 24 |
| Finished | May 16 01:55:09 PM PDT 24 |
| Peak memory | 211616 kb |
| Host | smart-7e0aed7a-da7a-4afe-af81-225103358960 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=175327321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.175327321 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3473246261 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 457702526 ps |
| CPU time | 23.07 seconds |
| Started | May 16 01:54:40 PM PDT 24 |
| Finished | May 16 01:55:05 PM PDT 24 |
| Peak memory | 211612 kb |
| Host | smart-cd72c902-215a-43a6-a114-88933924304e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3473246261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3473246261 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2138429464 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3401561405 ps |
| CPU time | 28.5 seconds |
| Started | May 16 01:54:41 PM PDT 24 |
| Finished | May 16 01:55:12 PM PDT 24 |
| Peak memory | 211652 kb |
| Host | smart-50d33f04-615a-4fc2-b633-1047f6f96d60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2138429464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2138429464 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2239169513 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 723389591 ps |
| CPU time | 26.65 seconds |
| Started | May 16 01:54:56 PM PDT 24 |
| Finished | May 16 01:55:24 PM PDT 24 |
| Peak memory | 203932 kb |
| Host | smart-e456c921-e2fa-4ec6-aaa2-d17def55e99f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2239169513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2239169513 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.3405981497 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1775340951 ps |
| CPU time | 36.45 seconds |
| Started | May 16 01:54:40 PM PDT 24 |
| Finished | May 16 01:55:20 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-56885982-c2e4-47b5-b562-c1333b6dba73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3405981497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3405981497 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1944350371 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 207165253 ps |
| CPU time | 27.89 seconds |
| Started | May 16 01:54:41 PM PDT 24 |
| Finished | May 16 01:55:11 PM PDT 24 |
| Peak memory | 204956 kb |
| Host | smart-7220ee1b-6fed-47c0-9548-c6c5030eed95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1944350371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1944350371 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.4045803124 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 227070934632 ps |
| CPU time | 324.53 seconds |
| Started | May 16 01:54:39 PM PDT 24 |
| Finished | May 16 02:00:06 PM PDT 24 |
| Peak memory | 205020 kb |
| Host | smart-99dfb663-149b-4d92-a137-5c8caf596802 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045803124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.4045803124 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.231512082 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 17215537233 ps |
| CPU time | 159.87 seconds |
| Started | May 16 01:54:40 PM PDT 24 |
| Finished | May 16 01:57:22 PM PDT 24 |
| Peak memory | 205292 kb |
| Host | smart-59e9cb9a-d34d-4553-927f-99ea0488bb75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=231512082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.231512082 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.1483123676 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 204376016 ps |
| CPU time | 28.2 seconds |
| Started | May 16 01:54:40 PM PDT 24 |
| Finished | May 16 01:55:11 PM PDT 24 |
| Peak memory | 204916 kb |
| Host | smart-e30fd4fa-b7e7-408b-a4d4-8c8df9c957cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483123676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1483123676 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2981193343 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 1603225549 ps |
| CPU time | 26.89 seconds |
| Started | May 16 01:54:38 PM PDT 24 |
| Finished | May 16 01:55:06 PM PDT 24 |
| Peak memory | 203956 kb |
| Host | smart-b2cc5225-4ad7-4617-afea-1c8bd1537588 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2981193343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2981193343 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.214693481 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 56254464 ps |
| CPU time | 2.49 seconds |
| Started | May 16 01:54:38 PM PDT 24 |
| Finished | May 16 01:54:42 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-fc48ed8f-ce3d-472b-a24b-5f2204e5eafa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=214693481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.214693481 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.4010113263 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4577221095 ps |
| CPU time | 27.15 seconds |
| Started | May 16 01:54:40 PM PDT 24 |
| Finished | May 16 01:55:10 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-921653a9-22e5-45d6-91c0-dfe9e93a9f31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010113263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.4010113263 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.4005339152 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4987791813 ps |
| CPU time | 24.71 seconds |
| Started | May 16 01:54:39 PM PDT 24 |
| Finished | May 16 01:55:06 PM PDT 24 |
| Peak memory | 203460 kb |
| Host | smart-7d154ac6-54fe-44fd-a181-54016f4d763c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4005339152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4005339152 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1375554692 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 40501416 ps |
| CPU time | 2.35 seconds |
| Started | May 16 01:54:40 PM PDT 24 |
| Finished | May 16 01:54:45 PM PDT 24 |
| Peak memory | 203372 kb |
| Host | smart-9aabd117-5373-429b-bb76-44a17bcf1295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375554692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1375554692 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.131033634 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 949727902 ps |
| CPU time | 69.21 seconds |
| Started | May 16 01:54:53 PM PDT 24 |
| Finished | May 16 01:56:05 PM PDT 24 |
| Peak memory | 205860 kb |
| Host | smart-2a264b51-a2dd-401d-b4de-b9c5cde90a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=131033634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.131033634 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1561603331 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1711644315 ps |
| CPU time | 37.35 seconds |
| Started | May 16 01:54:52 PM PDT 24 |
| Finished | May 16 01:55:31 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-4d351daf-a5d4-478e-b119-bdf3b11458b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1561603331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1561603331 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.240699769 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 219373167 ps |
| CPU time | 59.78 seconds |
| Started | May 16 01:54:55 PM PDT 24 |
| Finished | May 16 01:55:57 PM PDT 24 |
| Peak memory | 207816 kb |
| Host | smart-4127d782-a9ce-4ff4-9cdf-652ca6264dcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=240699769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.240699769 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2909535259 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 725649034 ps |
| CPU time | 111.78 seconds |
| Started | May 16 01:54:54 PM PDT 24 |
| Finished | May 16 01:56:48 PM PDT 24 |
| Peak memory | 209580 kb |
| Host | smart-76028340-04d4-483e-8638-77c60159e95f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2909535259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.2909535259 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2680232605 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1248630358 ps |
| CPU time | 11.93 seconds |
| Started | May 16 01:54:41 PM PDT 24 |
| Finished | May 16 01:54:56 PM PDT 24 |
| Peak memory | 204756 kb |
| Host | smart-d78b7094-7840-4c0e-9b5b-22907609a8b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2680232605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2680232605 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3978848216 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 813345134 ps |
| CPU time | 12.3 seconds |
| Started | May 16 01:54:51 PM PDT 24 |
| Finished | May 16 01:55:04 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-a03d8740-bcaa-4894-87c9-a8723d73639e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3978848216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3978848216 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3878042379 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 225327083667 ps |
| CPU time | 551.33 seconds |
| Started | May 16 01:54:52 PM PDT 24 |
| Finished | May 16 02:04:05 PM PDT 24 |
| Peak memory | 207272 kb |
| Host | smart-1b5a2718-de2d-4a81-b747-7d264995eec9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3878042379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3878042379 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1229308332 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 553407975 ps |
| CPU time | 20.14 seconds |
| Started | May 16 01:54:56 PM PDT 24 |
| Finished | May 16 01:55:18 PM PDT 24 |
| Peak memory | 203700 kb |
| Host | smart-b3e24781-8958-437c-ae29-ae09e1d7aace |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1229308332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1229308332 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.2799418410 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 650503718 ps |
| CPU time | 15.63 seconds |
| Started | May 16 01:54:54 PM PDT 24 |
| Finished | May 16 01:55:12 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-4d2f7ff0-c096-4ae4-990e-402ec473f964 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2799418410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2799418410 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.3395152826 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 277692980 ps |
| CPU time | 11.99 seconds |
| Started | May 16 01:54:52 PM PDT 24 |
| Finished | May 16 01:55:06 PM PDT 24 |
| Peak memory | 204612 kb |
| Host | smart-8b9a1039-a452-4e1c-acf7-10cad907a5c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3395152826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3395152826 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.4066533094 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 26194309509 ps |
| CPU time | 67.94 seconds |
| Started | May 16 01:54:57 PM PDT 24 |
| Finished | May 16 01:56:07 PM PDT 24 |
| Peak memory | 211668 kb |
| Host | smart-0144287e-2a56-474a-8cab-db367e1a6161 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066533094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4066533094 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4278618273 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 13201093773 ps |
| CPU time | 114.94 seconds |
| Started | May 16 01:54:52 PM PDT 24 |
| Finished | May 16 01:56:49 PM PDT 24 |
| Peak memory | 205188 kb |
| Host | smart-853319dc-043f-4ca1-a94a-1400d1779dea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4278618273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4278618273 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.655095370 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 497461542 ps |
| CPU time | 13.06 seconds |
| Started | May 16 01:54:52 PM PDT 24 |
| Finished | May 16 01:55:07 PM PDT 24 |
| Peak memory | 211540 kb |
| Host | smart-865f1c62-6ac2-4b62-99c8-4235213f97d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655095370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.655095370 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.2517630576 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 787203311 ps |
| CPU time | 15.88 seconds |
| Started | May 16 01:54:54 PM PDT 24 |
| Finished | May 16 01:55:12 PM PDT 24 |
| Peak memory | 203968 kb |
| Host | smart-5c2240ef-f315-4508-8d79-b7c46d5add22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2517630576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2517630576 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.647349430 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 370610025 ps |
| CPU time | 3.9 seconds |
| Started | May 16 01:54:52 PM PDT 24 |
| Finished | May 16 01:54:58 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-495abae9-3c9e-4e81-8ea5-81f2c229d83a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647349430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.647349430 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2336780149 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 27565880848 ps |
| CPU time | 38.32 seconds |
| Started | May 16 01:54:53 PM PDT 24 |
| Finished | May 16 01:55:34 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-43feb4fe-094b-4702-869e-1f82ddbe9824 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336780149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2336780149 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.4238572340 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4104323681 ps |
| CPU time | 31.17 seconds |
| Started | May 16 01:54:57 PM PDT 24 |
| Finished | May 16 01:55:30 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-99dc8867-c08c-430e-9fe8-5e1adec89562 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4238572340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.4238572340 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2865756195 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 64586485 ps |
| CPU time | 2.46 seconds |
| Started | May 16 01:54:53 PM PDT 24 |
| Finished | May 16 01:54:58 PM PDT 24 |
| Peak memory | 203416 kb |
| Host | smart-5b8bc106-e47d-4c1a-a592-80d482885476 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865756195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2865756195 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2166802695 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2162997372 ps |
| CPU time | 128.33 seconds |
| Started | May 16 01:55:04 PM PDT 24 |
| Finished | May 16 01:57:13 PM PDT 24 |
| Peak memory | 209156 kb |
| Host | smart-cfec3b01-39b1-435e-b8e5-d024700a0381 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2166802695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2166802695 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2247228613 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1296186812 ps |
| CPU time | 276.58 seconds |
| Started | May 16 01:55:04 PM PDT 24 |
| Finished | May 16 01:59:41 PM PDT 24 |
| Peak memory | 211080 kb |
| Host | smart-6035088d-8af8-4de2-b907-846f126c300d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2247228613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.2247228613 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.286704390 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5354951069 ps |
| CPU time | 188.96 seconds |
| Started | May 16 01:55:04 PM PDT 24 |
| Finished | May 16 01:58:14 PM PDT 24 |
| Peak memory | 209524 kb |
| Host | smart-c3539712-e628-4c53-b502-d03a3d60f249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=286704390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.286704390 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3054216755 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 103805636 ps |
| CPU time | 15.5 seconds |
| Started | May 16 01:54:50 PM PDT 24 |
| Finished | May 16 01:55:07 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-bb59b2a5-2abf-48ea-a464-92bbe8906b34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3054216755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3054216755 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1738716731 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 666771753 ps |
| CPU time | 22.64 seconds |
| Started | May 16 01:55:11 PM PDT 24 |
| Finished | May 16 01:55:36 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-8555633b-bb2b-4b1f-b3a0-6a79ef4cff5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1738716731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1738716731 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1922501740 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 46833797815 ps |
| CPU time | 457.55 seconds |
| Started | May 16 01:55:12 PM PDT 24 |
| Finished | May 16 02:02:52 PM PDT 24 |
| Peak memory | 211648 kb |
| Host | smart-95e4111f-1841-488f-a43d-809cda5bb568 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1922501740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1922501740 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.44911769 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 67398694 ps |
| CPU time | 3.87 seconds |
| Started | May 16 01:55:10 PM PDT 24 |
| Finished | May 16 01:55:16 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-55a2c6bb-a7d3-4d95-8168-b897e0546c79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=44911769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.44911769 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1875455379 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 2674167312 ps |
| CPU time | 28.2 seconds |
| Started | May 16 01:55:11 PM PDT 24 |
| Finished | May 16 01:55:42 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-7736b81b-deba-45dc-95ac-4ba3afb11c54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1875455379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1875455379 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.1580020630 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 84853009 ps |
| CPU time | 2.87 seconds |
| Started | May 16 01:55:01 PM PDT 24 |
| Finished | May 16 01:55:06 PM PDT 24 |
| Peak memory | 203356 kb |
| Host | smart-deeef1c0-ea3a-4d56-a363-759761fdf555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1580020630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1580020630 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2999832761 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 116391442694 ps |
| CPU time | 267.19 seconds |
| Started | May 16 01:55:00 PM PDT 24 |
| Finished | May 16 01:59:29 PM PDT 24 |
| Peak memory | 204832 kb |
| Host | smart-dfeda2a0-3098-4b48-9fd3-3107fc085664 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999832761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2999832761 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2521274104 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 101497624971 ps |
| CPU time | 272.64 seconds |
| Started | May 16 01:55:00 PM PDT 24 |
| Finished | May 16 01:59:34 PM PDT 24 |
| Peak memory | 205684 kb |
| Host | smart-ae77bf74-839f-4df6-a797-71d133e529d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2521274104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2521274104 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1078988959 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 51980302 ps |
| CPU time | 5.96 seconds |
| Started | May 16 01:55:01 PM PDT 24 |
| Finished | May 16 01:55:09 PM PDT 24 |
| Peak memory | 204540 kb |
| Host | smart-920de045-2e8d-41a7-82f6-1d0a64e2cc7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078988959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1078988959 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.3694667595 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 293184666 ps |
| CPU time | 15.27 seconds |
| Started | May 16 01:55:12 PM PDT 24 |
| Finished | May 16 01:55:30 PM PDT 24 |
| Peak memory | 211628 kb |
| Host | smart-a4ad2f48-bf57-4d49-b593-c1b45cdec10e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3694667595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3694667595 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.3463965028 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 226980374 ps |
| CPU time | 3.64 seconds |
| Started | May 16 01:55:01 PM PDT 24 |
| Finished | May 16 01:55:06 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-0b5dd233-abfb-4ec1-91aa-20b0cfcaeaef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463965028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3463965028 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3707949667 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5476714213 ps |
| CPU time | 29.5 seconds |
| Started | May 16 01:54:59 PM PDT 24 |
| Finished | May 16 01:55:30 PM PDT 24 |
| Peak memory | 203360 kb |
| Host | smart-b17f0f49-0be4-4213-9e40-6b66a3c99563 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707949667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3707949667 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1531963948 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 8727407399 ps |
| CPU time | 29.8 seconds |
| Started | May 16 01:55:01 PM PDT 24 |
| Finished | May 16 01:55:32 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-89f89b7e-2734-4fd1-886f-fc0ab0aea9d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1531963948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1531963948 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.782533321 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 120284941 ps |
| CPU time | 2.24 seconds |
| Started | May 16 01:55:01 PM PDT 24 |
| Finished | May 16 01:55:05 PM PDT 24 |
| Peak memory | 203380 kb |
| Host | smart-39392761-407e-484b-8415-f955c09cff69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782533321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.782533321 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2386377444 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1591922339 ps |
| CPU time | 65.33 seconds |
| Started | May 16 01:55:13 PM PDT 24 |
| Finished | May 16 01:56:21 PM PDT 24 |
| Peak memory | 206032 kb |
| Host | smart-c4e1ade6-b174-4e28-ba57-f21f77d58277 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2386377444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2386377444 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.852047590 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 448532800 ps |
| CPU time | 26.86 seconds |
| Started | May 16 01:55:14 PM PDT 24 |
| Finished | May 16 01:55:43 PM PDT 24 |
| Peak memory | 204152 kb |
| Host | smart-be13fd49-0687-40d7-9470-312275aac6e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=852047590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.852047590 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.4106430985 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4808540025 ps |
| CPU time | 214.23 seconds |
| Started | May 16 01:55:11 PM PDT 24 |
| Finished | May 16 01:58:47 PM PDT 24 |
| Peak memory | 211752 kb |
| Host | smart-2a7cab54-e3ed-4b27-b5cc-444b811ba980 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4106430985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.4106430985 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3826890678 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 164502136 ps |
| CPU time | 11.93 seconds |
| Started | May 16 01:55:11 PM PDT 24 |
| Finished | May 16 01:55:26 PM PDT 24 |
| Peak memory | 204676 kb |
| Host | smart-4f9b670a-fa1c-4c09-ba4b-74e89489fb8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3826890678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3826890678 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.4109037524 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1064096739 ps |
| CPU time | 24.34 seconds |
| Started | May 16 01:55:24 PM PDT 24 |
| Finished | May 16 01:55:50 PM PDT 24 |
| Peak memory | 204688 kb |
| Host | smart-ba7d7c3a-02f6-4cd1-a27e-644155c49ca5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4109037524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.4109037524 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2030220459 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 36227193142 ps |
| CPU time | 351.77 seconds |
| Started | May 16 01:55:26 PM PDT 24 |
| Finished | May 16 02:01:19 PM PDT 24 |
| Peak memory | 206884 kb |
| Host | smart-eb2b2d0d-2656-4938-a350-00bb858476c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2030220459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.2030220459 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3261130582 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 483651963 ps |
| CPU time | 16.25 seconds |
| Started | May 16 01:55:24 PM PDT 24 |
| Finished | May 16 01:55:42 PM PDT 24 |
| Peak memory | 203676 kb |
| Host | smart-fba1acf3-0668-43f1-bb17-df18ee12f5c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261130582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3261130582 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.796651797 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1175615621 ps |
| CPU time | 18.54 seconds |
| Started | May 16 01:55:23 PM PDT 24 |
| Finished | May 16 01:55:42 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-19b05717-2f13-426f-9d41-fa7cacb0e5cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796651797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.796651797 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.2019425611 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 75887015 ps |
| CPU time | 2.94 seconds |
| Started | May 16 01:55:25 PM PDT 24 |
| Finished | May 16 01:55:29 PM PDT 24 |
| Peak memory | 203372 kb |
| Host | smart-9cd5f5c2-fa96-4bd6-ab55-8ecec50f209f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2019425611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2019425611 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.323641105 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 67447770000 ps |
| CPU time | 233.12 seconds |
| Started | May 16 01:55:25 PM PDT 24 |
| Finished | May 16 01:59:19 PM PDT 24 |
| Peak memory | 205340 kb |
| Host | smart-212caac8-42dc-44e3-a201-45cd00a92cba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=323641105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.323641105 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3326495519 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 121478211987 ps |
| CPU time | 255.91 seconds |
| Started | May 16 01:55:23 PM PDT 24 |
| Finished | May 16 01:59:40 PM PDT 24 |
| Peak memory | 204844 kb |
| Host | smart-324446e2-39ed-4cc5-be2a-4597fb0db4d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3326495519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3326495519 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2570726052 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 54389217 ps |
| CPU time | 5.36 seconds |
| Started | May 16 01:55:23 PM PDT 24 |
| Finished | May 16 01:55:30 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-2532d98f-29f5-4dc7-b671-0f6a6c03e048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570726052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2570726052 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.369853480 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 791226111 ps |
| CPU time | 20.62 seconds |
| Started | May 16 01:55:23 PM PDT 24 |
| Finished | May 16 01:55:45 PM PDT 24 |
| Peak memory | 204024 kb |
| Host | smart-79825e0b-7ada-4dbb-9921-7be1a26c448d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=369853480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.369853480 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.1765589285 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 277302049 ps |
| CPU time | 3.68 seconds |
| Started | May 16 01:55:12 PM PDT 24 |
| Finished | May 16 01:55:18 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-defbb02a-7aa9-49c3-b997-91f5a4e9eb6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1765589285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1765589285 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1644732610 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 12936366111 ps |
| CPU time | 31.06 seconds |
| Started | May 16 01:55:11 PM PDT 24 |
| Finished | May 16 01:55:44 PM PDT 24 |
| Peak memory | 203540 kb |
| Host | smart-11491cce-2c2c-4742-b5d2-ece9a1a4f090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644732610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1644732610 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.846474904 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5787936940 ps |
| CPU time | 31.32 seconds |
| Started | May 16 01:55:11 PM PDT 24 |
| Finished | May 16 01:55:44 PM PDT 24 |
| Peak memory | 203464 kb |
| Host | smart-9233d359-0f85-4cc4-bf0e-c19727a6dfa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=846474904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.846474904 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2523010130 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 147336125 ps |
| CPU time | 2.59 seconds |
| Started | May 16 01:55:11 PM PDT 24 |
| Finished | May 16 01:55:16 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-21fc313c-ee66-4bfd-830a-b3378fdd6c46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523010130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2523010130 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3059719397 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1178417134 ps |
| CPU time | 125.37 seconds |
| Started | May 16 01:55:27 PM PDT 24 |
| Finished | May 16 01:57:34 PM PDT 24 |
| Peak memory | 206052 kb |
| Host | smart-0fba0de9-d635-4546-8eb9-ef90a54c92a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3059719397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3059719397 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.633009679 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 519913436 ps |
| CPU time | 62.49 seconds |
| Started | May 16 01:55:25 PM PDT 24 |
| Finished | May 16 01:56:29 PM PDT 24 |
| Peak memory | 205800 kb |
| Host | smart-c22205c4-b93a-4bef-9692-f2ee3cfe9ea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=633009679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.633009679 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1040905675 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 55342076 ps |
| CPU time | 44.67 seconds |
| Started | May 16 01:55:23 PM PDT 24 |
| Finished | May 16 01:56:09 PM PDT 24 |
| Peak memory | 208068 kb |
| Host | smart-3f089893-3ec7-43d3-a819-15129c1f3e46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1040905675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.1040905675 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3593658582 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5761962779 ps |
| CPU time | 219.19 seconds |
| Started | May 16 01:55:24 PM PDT 24 |
| Finished | May 16 01:59:05 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-ccf80f94-e409-4742-81b8-a443f2a93579 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3593658582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3593658582 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2084571023 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 118174084 ps |
| CPU time | 19.81 seconds |
| Started | May 16 01:55:23 PM PDT 24 |
| Finished | May 16 01:55:45 PM PDT 24 |
| Peak memory | 204912 kb |
| Host | smart-04d2a505-772c-4dda-a473-63b355ffe723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2084571023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2084571023 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2658440025 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 35903090 ps |
| CPU time | 3.09 seconds |
| Started | May 16 01:52:07 PM PDT 24 |
| Finished | May 16 01:52:12 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-b17e8fd7-860c-426d-900b-37b452ba8271 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2658440025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2658440025 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3379861047 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 65558017606 ps |
| CPU time | 567.82 seconds |
| Started | May 16 01:52:07 PM PDT 24 |
| Finished | May 16 02:01:37 PM PDT 24 |
| Peak memory | 207492 kb |
| Host | smart-9d39a58d-be4c-4072-a3b5-c594aa77525a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3379861047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3379861047 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.704230023 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 287745313 ps |
| CPU time | 7.83 seconds |
| Started | May 16 01:52:07 PM PDT 24 |
| Finished | May 16 01:52:17 PM PDT 24 |
| Peak memory | 203552 kb |
| Host | smart-37a58935-3011-4073-abf7-9660acc91163 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=704230023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.704230023 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2807186429 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 546353711 ps |
| CPU time | 7.25 seconds |
| Started | May 16 01:52:07 PM PDT 24 |
| Finished | May 16 01:52:16 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-5677414e-fac2-4393-9e51-f59d4457d19f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2807186429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2807186429 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.1416223261 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1235683554 ps |
| CPU time | 38.52 seconds |
| Started | May 16 01:52:06 PM PDT 24 |
| Finished | May 16 01:52:46 PM PDT 24 |
| Peak memory | 204996 kb |
| Host | smart-02540c4d-1f5c-429f-8e92-97157b9b0387 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1416223261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1416223261 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3836893585 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 7996745944 ps |
| CPU time | 47.97 seconds |
| Started | May 16 01:52:05 PM PDT 24 |
| Finished | May 16 01:52:54 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-69cbf71d-f645-4722-9b3f-3ee5ab3416d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836893585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3836893585 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.742026326 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 37518715986 ps |
| CPU time | 237.26 seconds |
| Started | May 16 01:52:08 PM PDT 24 |
| Finished | May 16 01:56:07 PM PDT 24 |
| Peak memory | 204980 kb |
| Host | smart-0f051c98-0d34-42fd-b13a-3cfbc8df6473 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=742026326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.742026326 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3866917981 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 198002341 ps |
| CPU time | 7.96 seconds |
| Started | May 16 01:52:07 PM PDT 24 |
| Finished | May 16 01:52:16 PM PDT 24 |
| Peak memory | 204516 kb |
| Host | smart-83becb0b-710c-4ede-8f00-d43d13325ecb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866917981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3866917981 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.2896753592 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2858552117 ps |
| CPU time | 26.11 seconds |
| Started | May 16 01:52:06 PM PDT 24 |
| Finished | May 16 01:52:33 PM PDT 24 |
| Peak memory | 203456 kb |
| Host | smart-c80076f0-89b2-4f99-a9af-f8920286edae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2896753592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2896753592 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2141584460 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 67193412 ps |
| CPU time | 2.32 seconds |
| Started | May 16 01:52:07 PM PDT 24 |
| Finished | May 16 01:52:11 PM PDT 24 |
| Peak memory | 203372 kb |
| Host | smart-621af94f-71ba-4177-a209-19f6124c9cea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2141584460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2141584460 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3069787083 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 5898216767 ps |
| CPU time | 28.46 seconds |
| Started | May 16 01:52:06 PM PDT 24 |
| Finished | May 16 01:52:36 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-a8d73df2-1993-45fa-a37b-445eedf78895 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069787083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3069787083 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2693475886 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 13616473118 ps |
| CPU time | 35.53 seconds |
| Started | May 16 01:52:06 PM PDT 24 |
| Finished | May 16 01:52:43 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-642ed9c3-e7ee-47cc-ac80-60302b0fafe1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2693475886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2693475886 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3541593086 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 58585220 ps |
| CPU time | 2.34 seconds |
| Started | May 16 01:52:06 PM PDT 24 |
| Finished | May 16 01:52:10 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-a54078f2-bbed-4b4d-862a-fe5f00395b9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541593086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3541593086 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1633596804 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3565367968 ps |
| CPU time | 106.94 seconds |
| Started | May 16 01:52:06 PM PDT 24 |
| Finished | May 16 01:53:55 PM PDT 24 |
| Peak memory | 211744 kb |
| Host | smart-f9de3b27-aa1c-433e-a4ba-295e04c371c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1633596804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1633596804 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.638191789 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 372009169 ps |
| CPU time | 10.49 seconds |
| Started | May 16 01:52:08 PM PDT 24 |
| Finished | May 16 01:52:20 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-ad88e8e0-7ba6-423f-97ed-6c8ed9bd8d60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=638191789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.638191789 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1400581852 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 983488422 ps |
| CPU time | 121.09 seconds |
| Started | May 16 01:52:07 PM PDT 24 |
| Finished | May 16 01:54:10 PM PDT 24 |
| Peak memory | 208684 kb |
| Host | smart-a3acbc3f-8652-4f43-9d90-bcd38ad65080 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1400581852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.1400581852 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.402428378 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3197038541 ps |
| CPU time | 168.67 seconds |
| Started | May 16 01:52:08 PM PDT 24 |
| Finished | May 16 01:54:58 PM PDT 24 |
| Peak memory | 211636 kb |
| Host | smart-80e98816-142b-4856-916a-7576e0659fed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=402428378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.402428378 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1654629454 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 289668759 ps |
| CPU time | 8.64 seconds |
| Started | May 16 01:52:08 PM PDT 24 |
| Finished | May 16 01:52:18 PM PDT 24 |
| Peak memory | 211604 kb |
| Host | smart-7a9f1096-5269-4011-9fc9-a5141101eca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1654629454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1654629454 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2325870107 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 389643320 ps |
| CPU time | 31 seconds |
| Started | May 16 01:55:40 PM PDT 24 |
| Finished | May 16 01:56:16 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-dbe4f1fd-9926-49ba-8851-303c8cd0d647 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2325870107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2325870107 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.545203979 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 48049946236 ps |
| CPU time | 205.59 seconds |
| Started | May 16 01:55:41 PM PDT 24 |
| Finished | May 16 01:59:11 PM PDT 24 |
| Peak memory | 206244 kb |
| Host | smart-6355e58d-f9da-464c-a948-8809c7aa7fcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=545203979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.545203979 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3622086410 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2598310923 ps |
| CPU time | 22.53 seconds |
| Started | May 16 01:55:41 PM PDT 24 |
| Finished | May 16 01:56:09 PM PDT 24 |
| Peak memory | 203680 kb |
| Host | smart-53700da0-0100-414e-af29-3636541ddfa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3622086410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3622086410 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.857352993 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 111375324 ps |
| CPU time | 7.3 seconds |
| Started | May 16 01:55:41 PM PDT 24 |
| Finished | May 16 01:55:54 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-01bf5147-3194-46fb-b4f0-f791ca027f5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=857352993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.857352993 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.2914970380 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 300325815 ps |
| CPU time | 10.56 seconds |
| Started | May 16 01:55:41 PM PDT 24 |
| Finished | May 16 01:55:56 PM PDT 24 |
| Peak memory | 211600 kb |
| Host | smart-029eb928-9c8a-403d-b707-6d2d27f3c813 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2914970380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2914970380 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2321022103 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 22189952949 ps |
| CPU time | 78.38 seconds |
| Started | May 16 01:55:41 PM PDT 24 |
| Finished | May 16 01:57:04 PM PDT 24 |
| Peak memory | 204772 kb |
| Host | smart-b814ae68-5267-4483-827e-6ceee9550ede |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321022103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2321022103 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3328022283 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 32707444292 ps |
| CPU time | 136.39 seconds |
| Started | May 16 01:55:43 PM PDT 24 |
| Finished | May 16 01:58:04 PM PDT 24 |
| Peak memory | 205276 kb |
| Host | smart-380fef93-979f-4689-a76a-46d398c17567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3328022283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3328022283 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2370203900 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 135796923 ps |
| CPU time | 16.26 seconds |
| Started | May 16 01:55:43 PM PDT 24 |
| Finished | May 16 01:56:04 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-dc7e9da1-4b46-473b-a415-4c0d9dc334f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370203900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2370203900 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.3823291088 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 227282645 ps |
| CPU time | 6.06 seconds |
| Started | May 16 01:55:43 PM PDT 24 |
| Finished | May 16 01:55:54 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-d4c8b646-b081-4edb-9e93-c4b442628a4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3823291088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3823291088 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2397275213 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 266995268 ps |
| CPU time | 4.14 seconds |
| Started | May 16 01:55:24 PM PDT 24 |
| Finished | May 16 01:55:30 PM PDT 24 |
| Peak memory | 203388 kb |
| Host | smart-6d029014-0f62-44e6-9223-d5b3b7467db9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2397275213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2397275213 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2547838710 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 17253868469 ps |
| CPU time | 35.77 seconds |
| Started | May 16 01:55:41 PM PDT 24 |
| Finished | May 16 01:56:22 PM PDT 24 |
| Peak memory | 203476 kb |
| Host | smart-406e4999-a1c5-4e56-a430-88f8d4d234cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547838710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2547838710 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.636738365 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3759749428 ps |
| CPU time | 33.52 seconds |
| Started | May 16 01:55:42 PM PDT 24 |
| Finished | May 16 01:56:21 PM PDT 24 |
| Peak memory | 203476 kb |
| Host | smart-6723ae64-ae52-4220-8a0a-55b56c889a6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=636738365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.636738365 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2100228310 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 32858709 ps |
| CPU time | 2.38 seconds |
| Started | May 16 01:55:24 PM PDT 24 |
| Finished | May 16 01:55:28 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-02530462-70e2-4188-8af4-a293778600ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100228310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2100228310 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3796170622 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4263364451 ps |
| CPU time | 143.3 seconds |
| Started | May 16 01:55:42 PM PDT 24 |
| Finished | May 16 01:58:10 PM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-85253afe-2b78-420a-8ae5-78a31b2d9c24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3796170622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3796170622 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3417140826 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1370427269 ps |
| CPU time | 16.8 seconds |
| Started | May 16 01:55:52 PM PDT 24 |
| Finished | May 16 01:56:14 PM PDT 24 |
| Peak memory | 203652 kb |
| Host | smart-b19e0b64-95e7-40b1-9fc2-6e11e2be2d5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417140826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3417140826 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.4243989028 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 3888352477 ps |
| CPU time | 210.86 seconds |
| Started | May 16 01:55:41 PM PDT 24 |
| Finished | May 16 01:59:17 PM PDT 24 |
| Peak memory | 208428 kb |
| Host | smart-0d16ad19-d189-4ad9-9647-c990c6de7889 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4243989028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.4243989028 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1784477411 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 32967086 ps |
| CPU time | 4.34 seconds |
| Started | May 16 01:55:43 PM PDT 24 |
| Finished | May 16 01:55:53 PM PDT 24 |
| Peak memory | 204904 kb |
| Host | smart-d3541d90-88d5-4d3b-9fba-e83146ace010 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784477411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1784477411 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.283965482 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 56689111 ps |
| CPU time | 9.8 seconds |
| Started | May 16 01:56:00 PM PDT 24 |
| Finished | May 16 01:56:12 PM PDT 24 |
| Peak memory | 204168 kb |
| Host | smart-c04f2d08-7ddd-494e-ab77-9eb4cc1eb016 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=283965482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.283965482 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3490954256 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 25238459314 ps |
| CPU time | 223.54 seconds |
| Started | May 16 01:55:53 PM PDT 24 |
| Finished | May 16 01:59:41 PM PDT 24 |
| Peak memory | 206704 kb |
| Host | smart-a75af10b-ab9b-4005-8095-b344e2e41af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3490954256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3490954256 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2030109274 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 890185792 ps |
| CPU time | 32.96 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:56:29 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-6c34516a-6cf5-49d0-bfc5-a37c28869ad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2030109274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2030109274 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.3797288132 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 329225189 ps |
| CPU time | 10.81 seconds |
| Started | May 16 01:55:55 PM PDT 24 |
| Finished | May 16 01:56:09 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-0a413787-8619-4173-b863-6c18ef46f9ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3797288132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3797288132 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.4089568009 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 4620839450 ps |
| CPU time | 31.9 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:56:30 PM PDT 24 |
| Peak memory | 205272 kb |
| Host | smart-8daee598-2a9b-42b1-8b98-16f74a192b33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4089568009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.4089568009 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3351649143 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 34267039883 ps |
| CPU time | 97.07 seconds |
| Started | May 16 01:55:50 PM PDT 24 |
| Finished | May 16 01:57:33 PM PDT 24 |
| Peak memory | 204708 kb |
| Host | smart-c26471a2-cf68-43be-b55e-439a40e7ac45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351649143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3351649143 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.921320383 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 20634314522 ps |
| CPU time | 169.18 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:58:46 PM PDT 24 |
| Peak memory | 204732 kb |
| Host | smart-1526cc0b-5cfa-45d4-9d27-1d626dee8d93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=921320383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.921320383 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3797428128 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 79143837 ps |
| CPU time | 11.38 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:56:08 PM PDT 24 |
| Peak memory | 204720 kb |
| Host | smart-a3818273-5a00-476e-b573-759192e08562 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797428128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3797428128 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.608284174 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 776576331 ps |
| CPU time | 14.52 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:56:12 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-c161ce32-3bcc-44fd-b7e5-31a9641a99d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=608284174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.608284174 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.3623364101 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 60899330 ps |
| CPU time | 3.04 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:55:59 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-a7bf3fe0-f5a8-44ed-9a3d-00d0b08af5f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3623364101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3623364101 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1764947448 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5598780138 ps |
| CPU time | 31.9 seconds |
| Started | May 16 01:55:52 PM PDT 24 |
| Finished | May 16 01:56:29 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-7cb9ed6d-50ed-43a5-b289-0e9158df16d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764947448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1764947448 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2728672808 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4018855977 ps |
| CPU time | 27.37 seconds |
| Started | May 16 01:55:50 PM PDT 24 |
| Finished | May 16 01:56:23 PM PDT 24 |
| Peak memory | 203504 kb |
| Host | smart-89ecc085-7f74-4a73-8cc5-d251416fbe92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2728672808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2728672808 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.954455249 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 61366366 ps |
| CPU time | 2.25 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:56:00 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-93aee12f-fdd0-4760-b6c6-4b0db1390e24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954455249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.954455249 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1414360514 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4539349929 ps |
| CPU time | 62.83 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:57:00 PM PDT 24 |
| Peak memory | 206232 kb |
| Host | smart-5139f7a2-0e06-4aeb-acee-67eef699bfdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1414360514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1414360514 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3430497224 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2659605984 ps |
| CPU time | 163.92 seconds |
| Started | May 16 01:55:50 PM PDT 24 |
| Finished | May 16 01:58:39 PM PDT 24 |
| Peak memory | 209648 kb |
| Host | smart-a21e2a87-c4ed-4ab9-9fd5-ac579bf27014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3430497224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3430497224 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2326700822 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 18219171 ps |
| CPU time | 22.24 seconds |
| Started | May 16 01:55:53 PM PDT 24 |
| Finished | May 16 01:56:20 PM PDT 24 |
| Peak memory | 206436 kb |
| Host | smart-3ae3a3cd-9a81-4511-a1f1-fcac23381d6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2326700822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2326700822 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2381073926 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1517310118 ps |
| CPU time | 190.21 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:59:08 PM PDT 24 |
| Peak memory | 210616 kb |
| Host | smart-ffba7fa9-fc42-4593-b6b3-d706bf54885f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2381073926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.2381073926 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3687581868 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2203499089 ps |
| CPU time | 19.74 seconds |
| Started | May 16 01:55:50 PM PDT 24 |
| Finished | May 16 01:56:14 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-89a78fdb-b0c8-4cc8-bdc6-0c332bf4d414 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3687581868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3687581868 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3793729999 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 225825545 ps |
| CPU time | 16.22 seconds |
| Started | May 16 01:55:59 PM PDT 24 |
| Finished | May 16 01:56:17 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-f7bde0c6-b860-4a9c-9515-92dd40bd3e5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3793729999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3793729999 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4018437183 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 39669314 ps |
| CPU time | 5.21 seconds |
| Started | May 16 01:55:52 PM PDT 24 |
| Finished | May 16 01:56:02 PM PDT 24 |
| Peak memory | 203532 kb |
| Host | smart-20d3131b-f72e-49f6-8df9-01234fc0473d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018437183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4018437183 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.3986570764 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 487358363 ps |
| CPU time | 28.44 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:56:27 PM PDT 24 |
| Peak memory | 203844 kb |
| Host | smart-b988dd50-4c76-485f-96ce-1d104c98cf63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3986570764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3986570764 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.800629428 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 284801320 ps |
| CPU time | 24.26 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:56:21 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-67c58517-84cf-4c04-9450-30c5409d7324 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=800629428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.800629428 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.4052478719 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 6334731994 ps |
| CPU time | 18.75 seconds |
| Started | May 16 01:55:52 PM PDT 24 |
| Finished | May 16 01:56:16 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-7b3c0293-be32-4ae7-82cf-262f36b497c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052478719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.4052478719 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1632220992 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 89700547899 ps |
| CPU time | 189.32 seconds |
| Started | May 16 01:55:52 PM PDT 24 |
| Finished | May 16 01:59:07 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-8d7cf58c-85f0-46d6-92ea-fa53b13524d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1632220992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1632220992 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3272723320 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 199420362 ps |
| CPU time | 12.71 seconds |
| Started | May 16 01:56:00 PM PDT 24 |
| Finished | May 16 01:56:15 PM PDT 24 |
| Peak memory | 211616 kb |
| Host | smart-5b098bc7-cd90-4204-9dd2-6e6c2bf9cc8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272723320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3272723320 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.938424528 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1094426029 ps |
| CPU time | 24.04 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:56:21 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-b6edd6c2-6598-4df5-8d6f-826faa3992aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=938424528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.938424528 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2136099976 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 589609560 ps |
| CPU time | 3.98 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:56:01 PM PDT 24 |
| Peak memory | 203416 kb |
| Host | smart-d0352f2d-2f23-4930-a370-0a17b734097b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2136099976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2136099976 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1150726355 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 8760783006 ps |
| CPU time | 33.56 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:56:32 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-f39a167a-1a8d-4746-8cee-c9440c1390a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150726355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1150726355 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.657444164 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 4994275995 ps |
| CPU time | 26.79 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:56:25 PM PDT 24 |
| Peak memory | 203464 kb |
| Host | smart-c704fa3c-1767-43f4-b902-2ff049a60a83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=657444164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.657444164 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3493501744 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 33984318 ps |
| CPU time | 2.84 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:56:01 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-e8a6ac1a-7443-46cc-8a66-410e8d8b0633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493501744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3493501744 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1614518647 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 868910820 ps |
| CPU time | 95.74 seconds |
| Started | May 16 01:55:54 PM PDT 24 |
| Finished | May 16 01:57:34 PM PDT 24 |
| Peak memory | 211628 kb |
| Host | smart-1c610361-e4b3-408e-8a51-f8c560e88d43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1614518647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1614518647 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1606621971 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1179377684 ps |
| CPU time | 34.15 seconds |
| Started | May 16 01:56:00 PM PDT 24 |
| Finished | May 16 01:56:36 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-ea72b5a3-3e9a-42af-909b-7ac47cabd1d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1606621971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1606621971 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3582281175 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 8487418462 ps |
| CPU time | 126.11 seconds |
| Started | May 16 01:55:52 PM PDT 24 |
| Finished | May 16 01:58:03 PM PDT 24 |
| Peak memory | 208904 kb |
| Host | smart-c6e43408-2e51-4538-b1f1-841c36efc5a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582281175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3582281175 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.980876892 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 269810272 ps |
| CPU time | 61.74 seconds |
| Started | May 16 01:56:03 PM PDT 24 |
| Finished | May 16 01:57:06 PM PDT 24 |
| Peak memory | 208392 kb |
| Host | smart-1985e5a2-3862-470c-a8a8-a138a2e82f6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=980876892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res et_error.980876892 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3838969260 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 557772984 ps |
| CPU time | 13.75 seconds |
| Started | May 16 01:55:51 PM PDT 24 |
| Finished | May 16 01:56:11 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-58b16006-c23f-49d6-8f79-319cba5a7259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3838969260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3838969260 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.4265396320 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 706019350 ps |
| CPU time | 34.43 seconds |
| Started | May 16 01:56:02 PM PDT 24 |
| Finished | May 16 01:56:39 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-0f17c26b-01d0-4920-8020-b9c8762bb2ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4265396320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4265396320 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.730034938 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 148605733821 ps |
| CPU time | 638.84 seconds |
| Started | May 16 01:56:03 PM PDT 24 |
| Finished | May 16 02:06:43 PM PDT 24 |
| Peak memory | 211700 kb |
| Host | smart-c856b688-8adc-408a-bd34-fb6e1dc293a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=730034938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo w_rsp.730034938 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2133345121 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 50273850 ps |
| CPU time | 6.32 seconds |
| Started | May 16 01:56:13 PM PDT 24 |
| Finished | May 16 01:56:21 PM PDT 24 |
| Peak memory | 203752 kb |
| Host | smart-7d3439c6-f50a-4243-b084-ac3d981e6a95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2133345121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2133345121 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.3231150234 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 29213583 ps |
| CPU time | 2.05 seconds |
| Started | May 16 01:56:05 PM PDT 24 |
| Finished | May 16 01:56:09 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-235c4151-c430-4f4e-8924-17d1bb6ca8fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3231150234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3231150234 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.2046057465 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 92772315 ps |
| CPU time | 9.78 seconds |
| Started | May 16 01:56:02 PM PDT 24 |
| Finished | May 16 01:56:14 PM PDT 24 |
| Peak memory | 211532 kb |
| Host | smart-0e1a1b20-479c-460d-990e-3c9a467347b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2046057465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2046057465 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.818317500 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 13092718522 ps |
| CPU time | 81.08 seconds |
| Started | May 16 01:56:03 PM PDT 24 |
| Finished | May 16 01:57:26 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-dc324d1b-38a3-4466-8f25-17be2f7eafe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=818317500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.818317500 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2065877002 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 62199079501 ps |
| CPU time | 290.67 seconds |
| Started | May 16 01:56:05 PM PDT 24 |
| Finished | May 16 02:00:58 PM PDT 24 |
| Peak memory | 205560 kb |
| Host | smart-31c37b03-10f2-469b-8f01-bf24c42996eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2065877002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2065877002 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2471388752 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 177803232 ps |
| CPU time | 21.18 seconds |
| Started | May 16 01:56:02 PM PDT 24 |
| Finished | May 16 01:56:26 PM PDT 24 |
| Peak memory | 211612 kb |
| Host | smart-105df768-113e-46fe-ba7c-2778cb9fc934 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471388752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2471388752 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3492927105 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 437449698 ps |
| CPU time | 16.58 seconds |
| Started | May 16 01:56:06 PM PDT 24 |
| Finished | May 16 01:56:24 PM PDT 24 |
| Peak memory | 211600 kb |
| Host | smart-062b87fe-25b0-4d5e-819a-f6047f5a2252 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3492927105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3492927105 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.4029727915 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 153042751 ps |
| CPU time | 3.45 seconds |
| Started | May 16 01:56:02 PM PDT 24 |
| Finished | May 16 01:56:08 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-19b62a21-c288-463b-953f-393405f8f118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4029727915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4029727915 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4163844411 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 8826391085 ps |
| CPU time | 27.75 seconds |
| Started | May 16 01:56:04 PM PDT 24 |
| Finished | May 16 01:56:34 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-6d64224c-346c-4330-8958-2c89f51439f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163844411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4163844411 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4155980627 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3682455160 ps |
| CPU time | 30.81 seconds |
| Started | May 16 01:56:03 PM PDT 24 |
| Finished | May 16 01:56:36 PM PDT 24 |
| Peak memory | 203476 kb |
| Host | smart-ba7aaca6-eb58-4ee1-8485-a7f2d946c779 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4155980627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4155980627 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2416506998 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 33715968 ps |
| CPU time | 2.44 seconds |
| Started | May 16 01:56:01 PM PDT 24 |
| Finished | May 16 01:56:06 PM PDT 24 |
| Peak memory | 203416 kb |
| Host | smart-72b29c39-9309-41da-8d4f-e4a8a73c33da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416506998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2416506998 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1055854174 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 25202634687 ps |
| CPU time | 221.35 seconds |
| Started | May 16 01:56:16 PM PDT 24 |
| Finished | May 16 01:59:59 PM PDT 24 |
| Peak memory | 207452 kb |
| Host | smart-6643e6ba-eeef-474f-afbb-bdf9df62c3e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055854174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1055854174 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3678942448 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 482129725 ps |
| CPU time | 52.14 seconds |
| Started | May 16 01:56:12 PM PDT 24 |
| Finished | May 16 01:57:07 PM PDT 24 |
| Peak memory | 206464 kb |
| Host | smart-29c4150a-778f-49ee-a8c4-1570f0d8dc30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3678942448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3678942448 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.530980830 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1200550207 ps |
| CPU time | 287.75 seconds |
| Started | May 16 01:56:12 PM PDT 24 |
| Finished | May 16 02:01:02 PM PDT 24 |
| Peak memory | 208404 kb |
| Host | smart-c74db6f1-4e17-4aa4-afb3-b7c6d143d3b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=530980830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.530980830 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.493118505 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 596109365 ps |
| CPU time | 187.92 seconds |
| Started | May 16 01:56:11 PM PDT 24 |
| Finished | May 16 01:59:22 PM PDT 24 |
| Peak memory | 211548 kb |
| Host | smart-0a0a030c-6a0a-4603-b17f-0c5454509d4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=493118505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.493118505 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1130724731 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 143091650 ps |
| CPU time | 12.2 seconds |
| Started | May 16 01:56:12 PM PDT 24 |
| Finished | May 16 01:56:26 PM PDT 24 |
| Peak memory | 204896 kb |
| Host | smart-1971c25c-08b8-44fd-a942-add3e7822c11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1130724731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1130724731 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2226819830 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 1809031755 ps |
| CPU time | 69.75 seconds |
| Started | May 16 01:56:15 PM PDT 24 |
| Finished | May 16 01:57:26 PM PDT 24 |
| Peak memory | 205500 kb |
| Host | smart-ac2c0d24-06ac-4f40-8f59-65dd0f6e6441 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2226819830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2226819830 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2611466089 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3719213548 ps |
| CPU time | 30.71 seconds |
| Started | May 16 01:56:11 PM PDT 24 |
| Finished | May 16 01:56:43 PM PDT 24 |
| Peak memory | 203512 kb |
| Host | smart-fdb8ab63-7189-42e9-abfa-44cd92f12aa8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2611466089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.2611466089 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2005156992 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 496320457 ps |
| CPU time | 14.66 seconds |
| Started | May 16 01:56:19 PM PDT 24 |
| Finished | May 16 01:56:36 PM PDT 24 |
| Peak memory | 203968 kb |
| Host | smart-b3edcd08-cefb-48e1-ae21-8fcfb7dd56e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2005156992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2005156992 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2965863659 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1419303925 ps |
| CPU time | 33.92 seconds |
| Started | May 16 01:56:20 PM PDT 24 |
| Finished | May 16 01:56:56 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-e2d5c9af-32d2-4275-9f42-feab6021a917 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2965863659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2965863659 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.2156405402 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 172090947 ps |
| CPU time | 18.63 seconds |
| Started | May 16 01:56:14 PM PDT 24 |
| Finished | May 16 01:56:35 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-47f90968-4c93-4279-af13-efa1ae081c63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2156405402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2156405402 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1405215662 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 15730888179 ps |
| CPU time | 96.18 seconds |
| Started | May 16 01:56:14 PM PDT 24 |
| Finished | May 16 01:57:52 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-9d40af77-ef39-49d2-b8c9-f41472bea359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405215662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1405215662 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1364258437 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28477313156 ps |
| CPU time | 205.14 seconds |
| Started | May 16 01:56:12 PM PDT 24 |
| Finished | May 16 01:59:40 PM PDT 24 |
| Peak memory | 205500 kb |
| Host | smart-f6a77842-3aed-4652-8fdf-365972a90e65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1364258437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1364258437 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.4005224183 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 179705319 ps |
| CPU time | 20.14 seconds |
| Started | May 16 01:56:14 PM PDT 24 |
| Finished | May 16 01:56:36 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-da3368c9-1834-40c2-aeae-096988f1b1fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005224183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.4005224183 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.22424711 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 45335217 ps |
| CPU time | 3.21 seconds |
| Started | May 16 01:56:23 PM PDT 24 |
| Finished | May 16 01:56:28 PM PDT 24 |
| Peak memory | 203460 kb |
| Host | smart-0c1ae9f0-1fae-4845-bdb4-a8648b0defc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=22424711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.22424711 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.36913393 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 77886964 ps |
| CPU time | 2.46 seconds |
| Started | May 16 01:56:12 PM PDT 24 |
| Finished | May 16 01:56:17 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-78ea7305-bdd0-469a-9156-243f813fa8b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=36913393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.36913393 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1214932243 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 8703326668 ps |
| CPU time | 32.55 seconds |
| Started | May 16 01:56:13 PM PDT 24 |
| Finished | May 16 01:56:48 PM PDT 24 |
| Peak memory | 203356 kb |
| Host | smart-d16df6fc-481b-4db5-8aa4-38c65b4b96db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214932243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1214932243 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2180150909 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3041690210 ps |
| CPU time | 25.3 seconds |
| Started | May 16 01:56:11 PM PDT 24 |
| Finished | May 16 01:56:39 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-a9cb5dc8-06e9-43a2-a53a-a381278eaa73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2180150909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2180150909 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3444626890 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 109475871 ps |
| CPU time | 2.23 seconds |
| Started | May 16 01:56:11 PM PDT 24 |
| Finished | May 16 01:56:15 PM PDT 24 |
| Peak memory | 203276 kb |
| Host | smart-50b487cc-efda-4cf9-ad3b-f7053994ecd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444626890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3444626890 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1788364112 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1906769868 ps |
| CPU time | 192.35 seconds |
| Started | May 16 01:56:22 PM PDT 24 |
| Finished | May 16 01:59:36 PM PDT 24 |
| Peak memory | 206060 kb |
| Host | smart-0f81a609-c7ff-4d35-8686-05076d6bd72c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1788364112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1788364112 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1125319235 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5885497102 ps |
| CPU time | 184 seconds |
| Started | May 16 01:56:21 PM PDT 24 |
| Finished | May 16 01:59:28 PM PDT 24 |
| Peak memory | 208344 kb |
| Host | smart-2eafb541-6542-4f77-8ba2-6617f190683b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1125319235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1125319235 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1030732567 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 135009897 ps |
| CPU time | 77.66 seconds |
| Started | May 16 01:56:20 PM PDT 24 |
| Finished | May 16 01:57:41 PM PDT 24 |
| Peak memory | 208300 kb |
| Host | smart-6a2ccf86-10ab-4f7c-9682-965627f27078 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1030732567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.1030732567 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.406556026 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 476753769 ps |
| CPU time | 127.13 seconds |
| Started | May 16 01:56:20 PM PDT 24 |
| Finished | May 16 01:58:30 PM PDT 24 |
| Peak memory | 209840 kb |
| Host | smart-ee3d6d1b-95b2-4f83-bace-aeb1f7236d7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=406556026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.406556026 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.323552810 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 73289860 ps |
| CPU time | 6.47 seconds |
| Started | May 16 01:56:20 PM PDT 24 |
| Finished | May 16 01:56:29 PM PDT 24 |
| Peak memory | 204772 kb |
| Host | smart-e0c8e099-2b02-40b3-92b9-75340286dc46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=323552810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.323552810 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1178193721 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 30045723 ps |
| CPU time | 5.38 seconds |
| Started | May 16 01:56:32 PM PDT 24 |
| Finished | May 16 01:56:38 PM PDT 24 |
| Peak memory | 203520 kb |
| Host | smart-535e8710-8556-4bf3-b104-64ba38485105 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1178193721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1178193721 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.211209476 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 55193077211 ps |
| CPU time | 179.69 seconds |
| Started | May 16 01:56:31 PM PDT 24 |
| Finished | May 16 01:59:32 PM PDT 24 |
| Peak memory | 205276 kb |
| Host | smart-f00aa9ff-8712-447d-b0bb-9241ca4850fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=211209476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.211209476 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1295085231 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 305752452 ps |
| CPU time | 9.21 seconds |
| Started | May 16 01:56:39 PM PDT 24 |
| Finished | May 16 01:56:50 PM PDT 24 |
| Peak memory | 203620 kb |
| Host | smart-3420c51b-795f-42c7-b6c5-d5312aa721da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1295085231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1295085231 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.4098180084 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 403285831 ps |
| CPU time | 21.73 seconds |
| Started | May 16 01:56:30 PM PDT 24 |
| Finished | May 16 01:56:53 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-1b559cc0-8db0-47d5-b468-c84bac73fda9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4098180084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.4098180084 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.1400168018 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 743603769 ps |
| CPU time | 17.15 seconds |
| Started | May 16 01:56:21 PM PDT 24 |
| Finished | May 16 01:56:41 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-51a43869-f382-499b-b3f9-fbf2f83b1f7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1400168018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1400168018 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1164618125 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 34982888710 ps |
| CPU time | 199.19 seconds |
| Started | May 16 01:56:30 PM PDT 24 |
| Finished | May 16 01:59:50 PM PDT 24 |
| Peak memory | 205136 kb |
| Host | smart-251699e2-5ba0-4619-be56-4409516a353c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164618125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1164618125 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4219822714 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 36355206205 ps |
| CPU time | 246.36 seconds |
| Started | May 16 01:56:34 PM PDT 24 |
| Finished | May 16 02:00:41 PM PDT 24 |
| Peak memory | 205152 kb |
| Host | smart-2f565c64-5571-48b8-b37b-ff74c3bcc1be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4219822714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4219822714 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1153714614 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 51302289 ps |
| CPU time | 3.64 seconds |
| Started | May 16 01:56:20 PM PDT 24 |
| Finished | May 16 01:56:26 PM PDT 24 |
| Peak memory | 203704 kb |
| Host | smart-5afbed6c-8a92-4d5c-8bab-6b391e411115 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153714614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1153714614 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.993146526 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 995228431 ps |
| CPU time | 14.53 seconds |
| Started | May 16 01:56:33 PM PDT 24 |
| Finished | May 16 01:56:49 PM PDT 24 |
| Peak memory | 203888 kb |
| Host | smart-bf13354f-b9f7-4f32-835c-279ab9ff0691 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=993146526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.993146526 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.1444789968 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 272282150 ps |
| CPU time | 4.15 seconds |
| Started | May 16 01:56:21 PM PDT 24 |
| Finished | May 16 01:56:28 PM PDT 24 |
| Peak memory | 203352 kb |
| Host | smart-bef23061-5c42-49c2-b9d7-7df1841263ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1444789968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1444789968 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3500143496 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 11421385182 ps |
| CPU time | 30.44 seconds |
| Started | May 16 01:56:20 PM PDT 24 |
| Finished | May 16 01:56:54 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-ae2b4890-1e3c-4ceb-839c-119ded47a3c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500143496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3500143496 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2398794220 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3462757328 ps |
| CPU time | 27.44 seconds |
| Started | May 16 01:56:21 PM PDT 24 |
| Finished | May 16 01:56:51 PM PDT 24 |
| Peak memory | 203508 kb |
| Host | smart-46ce0b5c-51d7-4d7a-8d83-afd949367fe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2398794220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2398794220 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3322288463 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 22012205 ps |
| CPU time | 2.05 seconds |
| Started | May 16 01:56:20 PM PDT 24 |
| Finished | May 16 01:56:25 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-a2ea6346-b1e4-4b6e-85c9-9b261d37a6e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322288463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3322288463 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.2295192824 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 728586868 ps |
| CPU time | 65.07 seconds |
| Started | May 16 01:56:41 PM PDT 24 |
| Finished | May 16 01:57:48 PM PDT 24 |
| Peak memory | 206956 kb |
| Host | smart-50df8f73-8210-49e8-84f0-4ae78861dcbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2295192824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2295192824 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2667486857 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1796464517 ps |
| CPU time | 30.91 seconds |
| Started | May 16 01:56:47 PM PDT 24 |
| Finished | May 16 01:57:18 PM PDT 24 |
| Peak memory | 203540 kb |
| Host | smart-aeb5c112-38db-4af3-b924-579934f25522 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2667486857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2667486857 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1817328909 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1996208427 ps |
| CPU time | 194.66 seconds |
| Started | May 16 01:56:40 PM PDT 24 |
| Finished | May 16 01:59:57 PM PDT 24 |
| Peak memory | 207952 kb |
| Host | smart-557c899f-9892-499b-923d-e8e4745b8633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1817328909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1817328909 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1799822904 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 734668910 ps |
| CPU time | 107.17 seconds |
| Started | May 16 01:56:39 PM PDT 24 |
| Finished | May 16 01:58:29 PM PDT 24 |
| Peak memory | 209672 kb |
| Host | smart-2072f99a-4be2-4f5d-af22-aa362dbf8855 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1799822904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1799822904 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.20942387 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 445060248 ps |
| CPU time | 16.26 seconds |
| Started | May 16 01:56:41 PM PDT 24 |
| Finished | May 16 01:56:59 PM PDT 24 |
| Peak memory | 204916 kb |
| Host | smart-195fdc87-7ec8-4e7b-9e7d-cd33aac3798b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=20942387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.20942387 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1656334271 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1157043714 ps |
| CPU time | 13.97 seconds |
| Started | May 16 01:56:50 PM PDT 24 |
| Finished | May 16 01:57:05 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-ae642913-42b1-40b4-9518-31dcdb0d7f35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1656334271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1656334271 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2832084763 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 75951847697 ps |
| CPU time | 347.22 seconds |
| Started | May 16 01:56:48 PM PDT 24 |
| Finished | May 16 02:02:37 PM PDT 24 |
| Peak memory | 206056 kb |
| Host | smart-75e80284-88b9-440c-af35-a9d54d60404b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2832084763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.2832084763 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1528434145 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 419388697 ps |
| CPU time | 5.37 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:56:56 PM PDT 24 |
| Peak memory | 203532 kb |
| Host | smart-0bc6ef1f-a0c1-42a0-8d82-c1137cc4623a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1528434145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1528434145 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.158439990 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 224596912 ps |
| CPU time | 19.18 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:57:10 PM PDT 24 |
| Peak memory | 203536 kb |
| Host | smart-2f3700ad-3cc0-423d-a3cb-3c70b4b636cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=158439990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.158439990 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.1456551404 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 46150682 ps |
| CPU time | 4.92 seconds |
| Started | May 16 01:56:40 PM PDT 24 |
| Finished | May 16 01:56:47 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-d3a72dad-730f-4078-85af-757777ca8af3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456551404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1456551404 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4221155373 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 152296453403 ps |
| CPU time | 169.55 seconds |
| Started | May 16 01:56:39 PM PDT 24 |
| Finished | May 16 01:59:31 PM PDT 24 |
| Peak memory | 204888 kb |
| Host | smart-14be307d-b0fd-463f-84f3-69b3d053c903 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221155373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4221155373 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.650282306 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 42680122351 ps |
| CPU time | 179 seconds |
| Started | May 16 01:56:40 PM PDT 24 |
| Finished | May 16 01:59:41 PM PDT 24 |
| Peak memory | 205304 kb |
| Host | smart-a7c9dab7-9032-438d-b943-8fda86a25e7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=650282306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.650282306 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2530950402 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1163843098 ps |
| CPU time | 27.26 seconds |
| Started | May 16 01:56:40 PM PDT 24 |
| Finished | May 16 01:57:10 PM PDT 24 |
| Peak memory | 204920 kb |
| Host | smart-50d863ca-3323-480d-bf03-7b0890f121fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530950402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2530950402 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3068564045 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1346225402 ps |
| CPU time | 32.07 seconds |
| Started | May 16 01:56:54 PM PDT 24 |
| Finished | May 16 01:57:27 PM PDT 24 |
| Peak memory | 204160 kb |
| Host | smart-393fc985-5418-4900-89d3-3db31ea2b3ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3068564045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3068564045 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.2204739523 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 101384456 ps |
| CPU time | 2.71 seconds |
| Started | May 16 01:56:41 PM PDT 24 |
| Finished | May 16 01:56:46 PM PDT 24 |
| Peak memory | 203416 kb |
| Host | smart-30e027c5-6335-48b2-9bf0-773ac31ffce2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2204739523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2204739523 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2067265729 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 10059766006 ps |
| CPU time | 34.63 seconds |
| Started | May 16 01:56:40 PM PDT 24 |
| Finished | May 16 01:57:17 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-26cc93ad-279b-4f6a-b53d-1a6d8280c307 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067265729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2067265729 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1527027336 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4151946129 ps |
| CPU time | 27.77 seconds |
| Started | May 16 01:56:39 PM PDT 24 |
| Finished | May 16 01:57:09 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-877aa1db-3bb7-4311-8d43-1a164086859e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1527027336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1527027336 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3407441076 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 37795954 ps |
| CPU time | 2.6 seconds |
| Started | May 16 01:56:40 PM PDT 24 |
| Finished | May 16 01:56:45 PM PDT 24 |
| Peak memory | 203336 kb |
| Host | smart-b8a58178-b586-43f7-983b-cb2e4892e994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407441076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3407441076 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3381704458 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1538877844 ps |
| CPU time | 154.52 seconds |
| Started | May 16 01:56:51 PM PDT 24 |
| Finished | May 16 01:59:27 PM PDT 24 |
| Peak memory | 209856 kb |
| Host | smart-89d2aa06-7bbd-4d9a-b691-80a0911fa647 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381704458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3381704458 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.632085318 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 139990700 ps |
| CPU time | 10.83 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:57:01 PM PDT 24 |
| Peak memory | 203524 kb |
| Host | smart-d80ee00d-8932-4d5b-8daa-dbfc022d43b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=632085318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.632085318 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3545959606 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 10082685727 ps |
| CPU time | 511 seconds |
| Started | May 16 01:56:51 PM PDT 24 |
| Finished | May 16 02:05:24 PM PDT 24 |
| Peak memory | 219900 kb |
| Host | smart-3e78f9a9-3c31-46ab-beee-cd216f72d94c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3545959606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.3545959606 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2176276798 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 14224407697 ps |
| CPU time | 240.31 seconds |
| Started | May 16 01:56:51 PM PDT 24 |
| Finished | May 16 02:00:53 PM PDT 24 |
| Peak memory | 211688 kb |
| Host | smart-0c5dade1-abc0-4469-a167-f24cd4955516 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2176276798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.2176276798 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3814583556 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 72994137 ps |
| CPU time | 12.85 seconds |
| Started | May 16 01:56:48 PM PDT 24 |
| Finished | May 16 01:57:02 PM PDT 24 |
| Peak memory | 204852 kb |
| Host | smart-71f6a701-d402-4377-8b4e-fa68b3fa2f93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3814583556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3814583556 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1235192446 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1042400425 ps |
| CPU time | 39.16 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:57:30 PM PDT 24 |
| Peak memory | 204884 kb |
| Host | smart-180ef97a-9891-4e25-8eda-e2f060ecacdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1235192446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1235192446 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.702605717 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 35417877002 ps |
| CPU time | 252.41 seconds |
| Started | May 16 01:56:59 PM PDT 24 |
| Finished | May 16 02:01:14 PM PDT 24 |
| Peak memory | 206032 kb |
| Host | smart-13833396-170f-4e97-8d9f-ba92581d4274 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=702605717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.702605717 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.374250772 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 311615857 ps |
| CPU time | 5.2 seconds |
| Started | May 16 01:56:57 PM PDT 24 |
| Finished | May 16 01:57:03 PM PDT 24 |
| Peak memory | 203604 kb |
| Host | smart-e3a67937-8c96-4d8f-b238-d13e22e81c4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=374250772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.374250772 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.1761355881 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 125842654 ps |
| CPU time | 4.92 seconds |
| Started | May 16 01:56:59 PM PDT 24 |
| Finished | May 16 01:57:06 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-9a733d8a-03f5-4b51-9512-8de564f31f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1761355881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1761355881 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.4209484668 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1209964359 ps |
| CPU time | 36.34 seconds |
| Started | May 16 01:56:51 PM PDT 24 |
| Finished | May 16 01:57:28 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-36e420d5-0418-4b37-b8c4-8b48337f12c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4209484668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.4209484668 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.957970268 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 14991375332 ps |
| CPU time | 57.08 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:57:48 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-5fc85bc4-50ce-4279-8ec0-dd69e83279bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=957970268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.957970268 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2449863972 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 12742737497 ps |
| CPU time | 59.11 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:57:50 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-3644a178-3efe-4ddb-8f72-acd559201bfd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2449863972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2449863972 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2264329727 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 15531905 ps |
| CPU time | 2.43 seconds |
| Started | May 16 01:56:51 PM PDT 24 |
| Finished | May 16 01:56:55 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-4001b224-416a-410d-8807-71bc6f5c52ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264329727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2264329727 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.1824432087 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1848689738 ps |
| CPU time | 27.51 seconds |
| Started | May 16 01:56:57 PM PDT 24 |
| Finished | May 16 01:57:25 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-798a9591-f0ca-4b26-ade7-bc4e2f2e8d82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1824432087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1824432087 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.2816438509 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 50809218 ps |
| CPU time | 2.31 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:56:52 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-5a11e7d4-7ea2-4140-a7d2-808c1dffb11b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2816438509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2816438509 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4157816540 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4722295777 ps |
| CPU time | 25.49 seconds |
| Started | May 16 01:56:51 PM PDT 24 |
| Finished | May 16 01:57:18 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-2c024be4-97e7-4697-8942-fcd29f2a9f66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157816540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4157816540 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.616198336 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5555321526 ps |
| CPU time | 35.76 seconds |
| Started | May 16 01:56:49 PM PDT 24 |
| Finished | May 16 01:57:26 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-e6c3241d-6838-4320-9cab-f99183281554 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=616198336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.616198336 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2761850525 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 72768761 ps |
| CPU time | 2.21 seconds |
| Started | May 16 01:56:52 PM PDT 24 |
| Finished | May 16 01:56:55 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-dd4a24c2-a2d9-4fd8-af7d-b46e38c9c127 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761850525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2761850525 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.4090164973 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 11148831226 ps |
| CPU time | 179.57 seconds |
| Started | May 16 01:56:58 PM PDT 24 |
| Finished | May 16 01:59:59 PM PDT 24 |
| Peak memory | 209288 kb |
| Host | smart-ef6c80d8-9d37-4507-9330-b2a642c6ab12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090164973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4090164973 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2778360019 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1934542049 ps |
| CPU time | 29.65 seconds |
| Started | May 16 01:57:00 PM PDT 24 |
| Finished | May 16 01:57:32 PM PDT 24 |
| Peak memory | 203492 kb |
| Host | smart-cfa312fd-e75c-4355-82c3-2bc04ae8da58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2778360019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2778360019 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.436623402 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2602296190 ps |
| CPU time | 513.45 seconds |
| Started | May 16 01:56:57 PM PDT 24 |
| Finished | May 16 02:05:32 PM PDT 24 |
| Peak memory | 223788 kb |
| Host | smart-1b62dbbd-0fd7-4f1c-a553-f23c483b55e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=436623402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.436623402 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1378566009 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1955011442 ps |
| CPU time | 177.56 seconds |
| Started | May 16 01:56:58 PM PDT 24 |
| Finished | May 16 01:59:58 PM PDT 24 |
| Peak memory | 210884 kb |
| Host | smart-c7d5e607-6e23-4613-95ae-a55ef5e31898 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1378566009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.1378566009 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1153150483 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 141376195 ps |
| CPU time | 17.09 seconds |
| Started | May 16 01:56:59 PM PDT 24 |
| Finished | May 16 01:57:18 PM PDT 24 |
| Peak memory | 204940 kb |
| Host | smart-352283ea-8253-488a-bfa2-d458e9249e86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1153150483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1153150483 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3887575665 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 756778669 ps |
| CPU time | 17.07 seconds |
| Started | May 16 01:57:09 PM PDT 24 |
| Finished | May 16 01:57:27 PM PDT 24 |
| Peak memory | 204424 kb |
| Host | smart-0b07990d-6054-44f0-a70d-ede9dfef0a24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3887575665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3887575665 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1057929683 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 10836844385 ps |
| CPU time | 91.04 seconds |
| Started | May 16 01:57:08 PM PDT 24 |
| Finished | May 16 01:58:40 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-af2f3dda-bf5b-4310-8af9-1123b6a93e21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1057929683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.1057929683 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2634025817 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 176994517 ps |
| CPU time | 16.7 seconds |
| Started | May 16 01:57:11 PM PDT 24 |
| Finished | May 16 01:57:29 PM PDT 24 |
| Peak memory | 203464 kb |
| Host | smart-9808fafd-8442-4eae-a9f8-5182bfd557d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2634025817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2634025817 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.3133996076 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 180550480 ps |
| CPU time | 11.99 seconds |
| Started | May 16 01:57:09 PM PDT 24 |
| Finished | May 16 01:57:23 PM PDT 24 |
| Peak memory | 203380 kb |
| Host | smart-4036bee9-06b5-4ddf-be5b-6a45a73d0d04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3133996076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3133996076 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.1820286376 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 230224920 ps |
| CPU time | 8.81 seconds |
| Started | May 16 01:56:57 PM PDT 24 |
| Finished | May 16 01:57:08 PM PDT 24 |
| Peak memory | 204488 kb |
| Host | smart-ff621803-c43e-477c-959a-e09a42f7cb0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1820286376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1820286376 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2578360544 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 46787892122 ps |
| CPU time | 161.77 seconds |
| Started | May 16 01:56:59 PM PDT 24 |
| Finished | May 16 01:59:43 PM PDT 24 |
| Peak memory | 205060 kb |
| Host | smart-a42e48c5-2546-4f2b-8554-43e4e89851aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578360544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2578360544 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3299037300 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 5234292881 ps |
| CPU time | 29.29 seconds |
| Started | May 16 01:57:11 PM PDT 24 |
| Finished | May 16 01:57:42 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-b16cfa8c-6166-4e86-b439-85d8e716f3cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3299037300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3299037300 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.4066020708 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 364312771 ps |
| CPU time | 32.95 seconds |
| Started | May 16 01:56:59 PM PDT 24 |
| Finished | May 16 01:57:34 PM PDT 24 |
| Peak memory | 204540 kb |
| Host | smart-f371b6a7-0d53-47c0-a065-d90ce6e3efb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066020708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.4066020708 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.307572807 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1523513701 ps |
| CPU time | 27.45 seconds |
| Started | May 16 01:57:09 PM PDT 24 |
| Finished | May 16 01:57:39 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-8b154e91-b050-44ea-a2e8-ea0584759d17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=307572807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.307572807 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.1013425573 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 97835391 ps |
| CPU time | 2.95 seconds |
| Started | May 16 01:56:58 PM PDT 24 |
| Finished | May 16 01:57:03 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-f9908913-29ab-488d-a683-e9361b951fbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1013425573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1013425573 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2670960304 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 11855432362 ps |
| CPU time | 32.35 seconds |
| Started | May 16 01:56:57 PM PDT 24 |
| Finished | May 16 01:57:31 PM PDT 24 |
| Peak memory | 203332 kb |
| Host | smart-e12fbc29-a910-4294-a24a-a1b9d37723e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670960304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2670960304 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3883936339 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2846668060 ps |
| CPU time | 24.71 seconds |
| Started | May 16 01:56:58 PM PDT 24 |
| Finished | May 16 01:57:24 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-f8fdc1bd-785f-4145-8907-c1ada004b953 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3883936339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3883936339 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.4057229880 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 48260096 ps |
| CPU time | 2.42 seconds |
| Started | May 16 01:57:04 PM PDT 24 |
| Finished | May 16 01:57:08 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-bd257404-a703-4e8e-9dd7-72c16678fa8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057229880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.4057229880 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1718339736 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2745770805 ps |
| CPU time | 95.93 seconds |
| Started | May 16 01:57:10 PM PDT 24 |
| Finished | May 16 01:58:47 PM PDT 24 |
| Peak memory | 207960 kb |
| Host | smart-af552c5c-bc38-4b1d-adaa-ff5f03cad886 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1718339736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1718339736 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.665615582 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 457140737 ps |
| CPU time | 66.65 seconds |
| Started | May 16 01:57:13 PM PDT 24 |
| Finished | May 16 01:58:21 PM PDT 24 |
| Peak memory | 204776 kb |
| Host | smart-d61eab32-0138-4c54-8c3b-0448522fa527 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=665615582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.665615582 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3667740563 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 252076865 ps |
| CPU time | 62.79 seconds |
| Started | May 16 01:57:13 PM PDT 24 |
| Finished | May 16 01:58:17 PM PDT 24 |
| Peak memory | 208200 kb |
| Host | smart-2033979e-60a7-47f3-ad15-e1c7887269d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3667740563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.3667740563 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4168344863 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5820806307 ps |
| CPU time | 222.73 seconds |
| Started | May 16 01:57:10 PM PDT 24 |
| Finished | May 16 02:00:54 PM PDT 24 |
| Peak memory | 210428 kb |
| Host | smart-9afa86c2-73f1-4e86-9ac6-c981f2e1c566 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4168344863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.4168344863 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1275990624 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 39732897 ps |
| CPU time | 3.34 seconds |
| Started | May 16 01:57:11 PM PDT 24 |
| Finished | May 16 01:57:16 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-73e83a10-5935-48c5-aef8-008560fc5e32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1275990624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1275990624 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.635836539 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 319008784 ps |
| CPU time | 17.82 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 01:57:41 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-7f39a74a-6b26-4413-abc5-d9de66e8c7c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=635836539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.635836539 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2752796343 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 117269960747 ps |
| CPU time | 588.84 seconds |
| Started | May 16 01:57:21 PM PDT 24 |
| Finished | May 16 02:07:12 PM PDT 24 |
| Peak memory | 207388 kb |
| Host | smart-728fb5ae-e522-49df-81d9-8d2d141d5410 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2752796343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2752796343 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2350738900 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 219891563 ps |
| CPU time | 7.23 seconds |
| Started | May 16 01:57:22 PM PDT 24 |
| Finished | May 16 01:57:31 PM PDT 24 |
| Peak memory | 203532 kb |
| Host | smart-9af09b41-c123-468c-8a3d-b81db1cbbe30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2350738900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2350738900 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.2759665859 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 190368788 ps |
| CPU time | 2.7 seconds |
| Started | May 16 01:57:19 PM PDT 24 |
| Finished | May 16 01:57:23 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-fb32395c-e24d-41bf-a5a9-fa71e68dff1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2759665859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2759665859 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2874665931 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1324052473 ps |
| CPU time | 33.38 seconds |
| Started | May 16 01:57:10 PM PDT 24 |
| Finished | May 16 01:57:45 PM PDT 24 |
| Peak memory | 204752 kb |
| Host | smart-eda09d71-16bd-4422-8112-17ee04f8e388 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2874665931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2874665931 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1878158075 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 38592093461 ps |
| CPU time | 239.64 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 02:01:22 PM PDT 24 |
| Peak memory | 211684 kb |
| Host | smart-d13d36fd-8574-4ad4-855a-f0d954a84333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878158075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1878158075 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2300177634 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 38908799362 ps |
| CPU time | 245.41 seconds |
| Started | May 16 01:57:21 PM PDT 24 |
| Finished | May 16 02:01:29 PM PDT 24 |
| Peak memory | 204780 kb |
| Host | smart-1866124b-ff99-400a-b8ba-2f7552d01c72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2300177634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2300177634 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.506292555 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 82509581 ps |
| CPU time | 8.36 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 01:57:30 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-8a3cca80-2cef-472e-8095-00eafc03e9d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506292555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.506292555 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.610176979 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 88834162 ps |
| CPU time | 7.47 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 01:57:30 PM PDT 24 |
| Peak memory | 203980 kb |
| Host | smart-4bac2117-c643-4b47-9b07-e0be3f84139d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=610176979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.610176979 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.739019928 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 134157501 ps |
| CPU time | 4.06 seconds |
| Started | May 16 01:57:08 PM PDT 24 |
| Finished | May 16 01:57:14 PM PDT 24 |
| Peak memory | 203388 kb |
| Host | smart-cc55acc0-c16d-4984-a931-e86758876ba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=739019928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.739019928 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3952056157 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 6864801879 ps |
| CPU time | 31.29 seconds |
| Started | May 16 01:57:13 PM PDT 24 |
| Finished | May 16 01:57:46 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-c1fe0a36-9d56-4413-9b05-54df3b40d4e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952056157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3952056157 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2033863335 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 6302518886 ps |
| CPU time | 25.7 seconds |
| Started | May 16 01:57:09 PM PDT 24 |
| Finished | May 16 01:57:37 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-3ea1c748-883e-44a9-a955-d2505ff7e305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2033863335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2033863335 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2744616401 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 34014165 ps |
| CPU time | 2.29 seconds |
| Started | May 16 01:57:10 PM PDT 24 |
| Finished | May 16 01:57:14 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-cf4ebe7a-f048-4353-aeda-4fd9ac6ef21b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744616401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2744616401 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.403841440 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 297871818 ps |
| CPU time | 34.81 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 01:57:57 PM PDT 24 |
| Peak memory | 205472 kb |
| Host | smart-380734bf-cbf8-4bb6-a2a8-13c907d50f4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=403841440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.403841440 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2937503864 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 394910370 ps |
| CPU time | 49.91 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 01:58:13 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-eca4474d-8f82-439c-9737-9c3ee091b788 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2937503864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2937503864 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.204820427 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 546624624 ps |
| CPU time | 226.11 seconds |
| Started | May 16 01:57:22 PM PDT 24 |
| Finished | May 16 02:01:11 PM PDT 24 |
| Peak memory | 208884 kb |
| Host | smart-d5a81b2b-1a44-4e38-ae76-f901c6fd0240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=204820427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.204820427 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2240770363 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 8933203655 ps |
| CPU time | 357.4 seconds |
| Started | May 16 01:57:22 PM PDT 24 |
| Finished | May 16 02:03:22 PM PDT 24 |
| Peak memory | 219892 kb |
| Host | smart-1697b7bb-2b8e-43f0-b0bd-843db5239f65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2240770363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2240770363 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.776583942 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 15761399 ps |
| CPU time | 2.06 seconds |
| Started | May 16 01:57:19 PM PDT 24 |
| Finished | May 16 01:57:23 PM PDT 24 |
| Peak memory | 203396 kb |
| Host | smart-9c1f3c03-6081-46ff-95aa-e3fe1ce48e7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=776583942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.776583942 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1083636444 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 243172919 ps |
| CPU time | 35.74 seconds |
| Started | May 16 01:52:15 PM PDT 24 |
| Finished | May 16 01:52:51 PM PDT 24 |
| Peak memory | 206516 kb |
| Host | smart-e425dece-ea68-46fa-bc34-4d3b40b8d079 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1083636444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1083636444 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1612326269 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 15918811570 ps |
| CPU time | 103.06 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:54:04 PM PDT 24 |
| Peak memory | 206100 kb |
| Host | smart-d1a14d52-bfeb-4f2e-ab26-299fb4d788ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1612326269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1612326269 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2178256588 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 890673006 ps |
| CPU time | 29.74 seconds |
| Started | May 16 01:52:20 PM PDT 24 |
| Finished | May 16 01:52:52 PM PDT 24 |
| Peak memory | 203484 kb |
| Host | smart-3fe37ee2-75e0-47fb-afa3-3d6cf26bbd12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2178256588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2178256588 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2200014411 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 974413920 ps |
| CPU time | 22.87 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:40 PM PDT 24 |
| Peak memory | 203420 kb |
| Host | smart-a82ad2d7-b0aa-4229-970e-61bc07fda05f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200014411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2200014411 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3751717368 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 971361140 ps |
| CPU time | 27.96 seconds |
| Started | May 16 01:52:21 PM PDT 24 |
| Finished | May 16 01:52:50 PM PDT 24 |
| Peak memory | 204880 kb |
| Host | smart-2b4deb1c-d0e9-486c-9363-9e224d52d974 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3751717368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3751717368 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1619020030 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 14936739205 ps |
| CPU time | 75.08 seconds |
| Started | May 16 01:52:17 PM PDT 24 |
| Finished | May 16 01:53:35 PM PDT 24 |
| Peak memory | 204716 kb |
| Host | smart-f48cefdc-49a6-4570-b6fc-ed44fdacc235 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619020030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1619020030 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3813424139 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 31937409863 ps |
| CPU time | 177.58 seconds |
| Started | May 16 01:52:20 PM PDT 24 |
| Finished | May 16 01:55:20 PM PDT 24 |
| Peak memory | 205116 kb |
| Host | smart-d9556ddd-771b-4095-ab2d-45f948fc6cd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3813424139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3813424139 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2434163595 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 165410904 ps |
| CPU time | 21.58 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:39 PM PDT 24 |
| Peak memory | 211648 kb |
| Host | smart-1868527e-3815-46b3-a569-743e4f56ecef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434163595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2434163595 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3231439032 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2664502145 ps |
| CPU time | 14.76 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:32 PM PDT 24 |
| Peak memory | 204056 kb |
| Host | smart-87e6725f-9286-4cd8-8faf-b72f0fefea38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3231439032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3231439032 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2887838227 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 132335693 ps |
| CPU time | 3.77 seconds |
| Started | May 16 01:52:06 PM PDT 24 |
| Finished | May 16 01:52:11 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-0821f30b-2fc1-4e51-bd20-c5d089ec0833 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2887838227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2887838227 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.853542770 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 16103925523 ps |
| CPU time | 34.55 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:52 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-05bf0ed4-c210-4028-8667-74b5bfdba222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=853542770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.853542770 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2786034465 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 6465726744 ps |
| CPU time | 34.64 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:52 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-ca39ad41-886a-4eeb-984c-133358e02ac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2786034465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2786034465 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3208865499 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 123322110 ps |
| CPU time | 2.56 seconds |
| Started | May 16 01:52:21 PM PDT 24 |
| Finished | May 16 01:52:25 PM PDT 24 |
| Peak memory | 203384 kb |
| Host | smart-15b35662-8619-4d46-933e-0a86097d79e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208865499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3208865499 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3906543025 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 10038024499 ps |
| CPU time | 164.48 seconds |
| Started | May 16 01:52:17 PM PDT 24 |
| Finished | May 16 01:55:03 PM PDT 24 |
| Peak memory | 210044 kb |
| Host | smart-55d55edc-f305-4ee1-902c-e922cf340e8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906543025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3906543025 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.911084827 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 4235181439 ps |
| CPU time | 145.7 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:54:47 PM PDT 24 |
| Peak memory | 208644 kb |
| Host | smart-fc46c832-e00f-461f-969c-f910fd69eda4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=911084827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.911084827 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3384286305 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2559328663 ps |
| CPU time | 341.66 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:57:59 PM PDT 24 |
| Peak memory | 209512 kb |
| Host | smart-68544324-8148-4235-936b-7339c810e5d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3384286305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3384286305 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1034973981 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 470223618 ps |
| CPU time | 121.94 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:54:20 PM PDT 24 |
| Peak memory | 209444 kb |
| Host | smart-023c8bc0-c16e-4640-ae63-2a001892e4a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1034973981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1034973981 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2022494184 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 415940033 ps |
| CPU time | 19.3 seconds |
| Started | May 16 01:52:17 PM PDT 24 |
| Finished | May 16 01:52:39 PM PDT 24 |
| Peak memory | 205104 kb |
| Host | smart-fa45ed89-feb3-4a1c-8042-1dad80270742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2022494184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2022494184 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.279367485 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 583909698 ps |
| CPU time | 30.27 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:58:04 PM PDT 24 |
| Peak memory | 204768 kb |
| Host | smart-c26d296b-cc28-4d28-8880-03e9039a8406 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=279367485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.279367485 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1097156848 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 134117301346 ps |
| CPU time | 602.78 seconds |
| Started | May 16 01:57:30 PM PDT 24 |
| Finished | May 16 02:07:38 PM PDT 24 |
| Peak memory | 207144 kb |
| Host | smart-7ed32ca7-0044-414e-8ad0-a81352294e23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1097156848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.1097156848 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3880940882 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1206117040 ps |
| CPU time | 23 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:57:56 PM PDT 24 |
| Peak memory | 203580 kb |
| Host | smart-35f93e1b-652b-4392-bbec-d3a90592e8a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3880940882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3880940882 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.2176558255 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 670565312 ps |
| CPU time | 22.61 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:57:56 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-b51d088b-100d-47e5-8c8d-9c20fb83ab08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2176558255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2176558255 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.3231015369 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 354049538 ps |
| CPU time | 8.91 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:57:42 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-1e6d0f7f-a99a-4d35-ad46-847f73883afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3231015369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3231015369 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2826841576 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 41314620289 ps |
| CPU time | 168.17 seconds |
| Started | May 16 01:57:32 PM PDT 24 |
| Finished | May 16 02:00:24 PM PDT 24 |
| Peak memory | 204940 kb |
| Host | smart-374d8401-f087-47db-8f37-45b3b007d8ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826841576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2826841576 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1697201789 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 15133428731 ps |
| CPU time | 140.19 seconds |
| Started | May 16 01:57:30 PM PDT 24 |
| Finished | May 16 01:59:55 PM PDT 24 |
| Peak memory | 205000 kb |
| Host | smart-09481a8b-8041-45a2-a6af-1d88cd2fefc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1697201789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1697201789 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.4022701083 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 70702179 ps |
| CPU time | 6.78 seconds |
| Started | May 16 01:57:30 PM PDT 24 |
| Finished | May 16 01:57:41 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-b3b9e447-615c-4ebc-ab5a-364fb45ea503 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022701083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.4022701083 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3529220429 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 48059478 ps |
| CPU time | 3.77 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:57:37 PM PDT 24 |
| Peak memory | 203456 kb |
| Host | smart-48b80f89-f927-47ba-9187-617859d08220 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3529220429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3529220429 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3495324942 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 426792127 ps |
| CPU time | 3.38 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 01:57:26 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-1e6150d2-f65d-4030-a651-fd3e22c31bfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3495324942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3495324942 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1109288967 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 6428743178 ps |
| CPU time | 38.76 seconds |
| Started | May 16 01:57:20 PM PDT 24 |
| Finished | May 16 01:58:01 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-d41d0030-b85d-44e9-8a06-52db68e19b7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109288967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1109288967 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3725752749 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3696373500 ps |
| CPU time | 30.49 seconds |
| Started | May 16 01:57:30 PM PDT 24 |
| Finished | May 16 01:58:05 PM PDT 24 |
| Peak memory | 203504 kb |
| Host | smart-ac970136-584e-45da-be86-033e8d7e12cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3725752749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3725752749 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2194947885 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 35878859 ps |
| CPU time | 2.38 seconds |
| Started | May 16 01:57:21 PM PDT 24 |
| Finished | May 16 01:57:26 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-57bc4196-2fbf-4fee-824c-8d31a7145e59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194947885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2194947885 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2527237395 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 226281060 ps |
| CPU time | 21.3 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:57:55 PM PDT 24 |
| Peak memory | 205164 kb |
| Host | smart-8e9da54b-2891-41b0-a545-5c7baeab4fe8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2527237395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2527237395 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.103482435 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1481209618 ps |
| CPU time | 123.73 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:59:36 PM PDT 24 |
| Peak memory | 208184 kb |
| Host | smart-78dd61f5-f144-4f9c-99aa-443da4860184 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=103482435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.103482435 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2872905230 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 662137063 ps |
| CPU time | 219.55 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 02:01:12 PM PDT 24 |
| Peak memory | 208916 kb |
| Host | smart-c4af34ed-198f-459d-910f-9b0daeab0243 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2872905230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2872905230 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1962770167 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 11561996175 ps |
| CPU time | 491.89 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 02:05:46 PM PDT 24 |
| Peak memory | 227436 kb |
| Host | smart-0961cd5c-5089-4c62-b323-6435891d5da6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1962770167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1962770167 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.3506445990 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 98188567 ps |
| CPU time | 12.64 seconds |
| Started | May 16 01:57:28 PM PDT 24 |
| Finished | May 16 01:57:42 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-e8b88dad-f910-43c7-9006-1f0565ec2572 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3506445990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3506445990 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3597005722 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 96961983 ps |
| CPU time | 12.13 seconds |
| Started | May 16 01:57:45 PM PDT 24 |
| Finished | May 16 01:57:59 PM PDT 24 |
| Peak memory | 203864 kb |
| Host | smart-24d83618-7eac-4792-ba38-f03e7489d57b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3597005722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3597005722 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.2202521566 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 347124141 ps |
| CPU time | 6.71 seconds |
| Started | May 16 01:57:27 PM PDT 24 |
| Finished | May 16 01:57:36 PM PDT 24 |
| Peak memory | 204132 kb |
| Host | smart-c5b64821-88ea-47f3-aee5-6701385236a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2202521566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2202521566 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3335508551 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 165510880380 ps |
| CPU time | 242.3 seconds |
| Started | May 16 01:57:42 PM PDT 24 |
| Finished | May 16 02:01:47 PM PDT 24 |
| Peak memory | 205176 kb |
| Host | smart-708830e5-9705-4afa-8b01-6e81110d1108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335508551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3335508551 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1265193275 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 13685650300 ps |
| CPU time | 108.05 seconds |
| Started | May 16 01:57:43 PM PDT 24 |
| Finished | May 16 01:59:33 PM PDT 24 |
| Peak memory | 211660 kb |
| Host | smart-77e9ff65-e91c-43b8-91fe-353e7b74838e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1265193275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1265193275 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.2746275689 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 23000854 ps |
| CPU time | 2.28 seconds |
| Started | May 16 01:57:45 PM PDT 24 |
| Finished | May 16 01:57:49 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-d98832a7-136a-488f-837a-a43654ad2c06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746275689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2746275689 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1740841180 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1571886729 ps |
| CPU time | 18.11 seconds |
| Started | May 16 01:57:45 PM PDT 24 |
| Finished | May 16 01:58:05 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-39678dd2-c98a-42e5-8ca6-8059b0d706d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1740841180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1740841180 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.3394990382 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 373019772 ps |
| CPU time | 3.61 seconds |
| Started | May 16 01:57:30 PM PDT 24 |
| Finished | May 16 01:57:38 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-b7d52ecd-9854-41b4-b79a-6324ebca6629 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394990382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3394990382 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2198816858 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4379501868 ps |
| CPU time | 26.59 seconds |
| Started | May 16 01:57:27 PM PDT 24 |
| Finished | May 16 01:57:56 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-4832451b-f783-4ecd-869b-00a87ed212fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198816858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2198816858 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2293363178 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 7906408667 ps |
| CPU time | 24.18 seconds |
| Started | May 16 01:57:31 PM PDT 24 |
| Finished | May 16 01:58:00 PM PDT 24 |
| Peak memory | 203484 kb |
| Host | smart-1a86a374-a395-438b-9443-707c8e8d8be6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2293363178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2293363178 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1062071036 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 42831606 ps |
| CPU time | 2.29 seconds |
| Started | May 16 01:57:29 PM PDT 24 |
| Finished | May 16 01:57:35 PM PDT 24 |
| Peak memory | 203416 kb |
| Host | smart-ed20aa0f-c15b-426b-b4ac-cb8cdd832b90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062071036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1062071036 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2317623560 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 17852006350 ps |
| CPU time | 262.92 seconds |
| Started | May 16 01:57:45 PM PDT 24 |
| Finished | May 16 02:02:10 PM PDT 24 |
| Peak memory | 209708 kb |
| Host | smart-8b878976-8c7e-4ee8-9ecf-1ab02798a3b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2317623560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2317623560 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3621365813 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1543015019 ps |
| CPU time | 67.01 seconds |
| Started | May 16 01:57:54 PM PDT 24 |
| Finished | May 16 01:59:03 PM PDT 24 |
| Peak memory | 207248 kb |
| Host | smart-ef5b1c0a-18eb-4b28-bd68-48f69f7f08d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3621365813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3621365813 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3436098061 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1596060885 ps |
| CPU time | 64.24 seconds |
| Started | May 16 01:57:52 PM PDT 24 |
| Finished | May 16 01:58:59 PM PDT 24 |
| Peak memory | 208280 kb |
| Host | smart-145bc9b2-e98b-4334-a625-2b5de696e52a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3436098061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3436098061 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1573891533 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2850637210 ps |
| CPU time | 97.07 seconds |
| Started | May 16 01:57:54 PM PDT 24 |
| Finished | May 16 01:59:33 PM PDT 24 |
| Peak memory | 209124 kb |
| Host | smart-7eef9e29-683f-4b02-a99e-98a79394a4a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1573891533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1573891533 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.505445487 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 624320509 ps |
| CPU time | 18.5 seconds |
| Started | May 16 01:57:45 PM PDT 24 |
| Finished | May 16 01:58:05 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-cc982f89-a453-4e3f-98fb-2929ce9cb41f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=505445487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.505445487 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1451328633 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 750198059 ps |
| CPU time | 33.47 seconds |
| Started | May 16 01:57:56 PM PDT 24 |
| Finished | May 16 01:58:31 PM PDT 24 |
| Peak memory | 205564 kb |
| Host | smart-9da0ebb3-6e64-4568-a2de-6f66041b860c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451328633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1451328633 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2985329331 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 55037144211 ps |
| CPU time | 412.82 seconds |
| Started | May 16 01:57:54 PM PDT 24 |
| Finished | May 16 02:04:49 PM PDT 24 |
| Peak memory | 205988 kb |
| Host | smart-8eb69576-5d6e-4a3e-b7d6-a8ec2cf93e6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2985329331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2985329331 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2603169146 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 138441347 ps |
| CPU time | 13.06 seconds |
| Started | May 16 01:57:53 PM PDT 24 |
| Finished | May 16 01:58:09 PM PDT 24 |
| Peak memory | 203632 kb |
| Host | smart-7e1173ff-5532-4e68-90b7-d1b5b2653326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2603169146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2603169146 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.3440047003 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 930267518 ps |
| CPU time | 28.69 seconds |
| Started | May 16 01:57:52 PM PDT 24 |
| Finished | May 16 01:58:24 PM PDT 24 |
| Peak memory | 203456 kb |
| Host | smart-517f70cc-d785-4c38-b72d-fbf6aaf56b1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440047003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3440047003 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.2221214478 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1413181383 ps |
| CPU time | 29.38 seconds |
| Started | May 16 01:57:53 PM PDT 24 |
| Finished | May 16 01:58:25 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-a11d65ee-13d9-4c03-be55-923d96742882 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221214478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2221214478 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3402933625 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 67841626278 ps |
| CPU time | 142.99 seconds |
| Started | May 16 01:57:52 PM PDT 24 |
| Finished | May 16 02:00:17 PM PDT 24 |
| Peak memory | 211528 kb |
| Host | smart-fef4eb9b-48ee-4fd0-9a8b-68bb51c69e81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402933625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3402933625 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2216820061 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 29308387090 ps |
| CPU time | 91.72 seconds |
| Started | May 16 01:57:51 PM PDT 24 |
| Finished | May 16 01:59:25 PM PDT 24 |
| Peak memory | 204764 kb |
| Host | smart-6d5df627-91f2-4554-b33a-ea90d7c1220e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2216820061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2216820061 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.4125856646 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 132870759 ps |
| CPU time | 16.77 seconds |
| Started | May 16 01:57:52 PM PDT 24 |
| Finished | May 16 01:58:11 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-eeb45b6d-dcd9-48fb-a2e1-12db9f3f8b45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125856646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4125856646 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.699558775 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 529338033 ps |
| CPU time | 15.97 seconds |
| Started | May 16 01:57:53 PM PDT 24 |
| Finished | May 16 01:58:12 PM PDT 24 |
| Peak memory | 203948 kb |
| Host | smart-24f88093-3c4d-49cd-9ce3-567b2e295eac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=699558775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.699558775 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3339755741 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 34410727 ps |
| CPU time | 2.37 seconds |
| Started | May 16 01:57:52 PM PDT 24 |
| Finished | May 16 01:57:57 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-9de536cc-7017-426e-8067-bf943d862e43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3339755741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3339755741 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3903875853 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 9630787808 ps |
| CPU time | 32.57 seconds |
| Started | May 16 01:57:53 PM PDT 24 |
| Finished | May 16 01:58:28 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-67b0fda0-be6d-4c0e-9581-dc76df606c74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903875853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3903875853 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3004713139 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 11498500862 ps |
| CPU time | 35.44 seconds |
| Started | May 16 01:57:51 PM PDT 24 |
| Finished | May 16 01:58:29 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-5a878c1e-3dcc-4437-9fdc-6db30d29734a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3004713139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3004713139 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.185374775 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 33266047 ps |
| CPU time | 2.71 seconds |
| Started | May 16 01:57:52 PM PDT 24 |
| Finished | May 16 01:57:57 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-0f582a28-452c-4f32-97b3-e5120c8de68c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185374775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.185374775 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2238367130 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 5693542012 ps |
| CPU time | 160.91 seconds |
| Started | May 16 01:57:53 PM PDT 24 |
| Finished | May 16 02:00:36 PM PDT 24 |
| Peak memory | 211676 kb |
| Host | smart-76db0ae5-9cff-4fc0-a100-4a0d86f3bfde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2238367130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2238367130 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4077941914 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 7758652373 ps |
| CPU time | 247.98 seconds |
| Started | May 16 01:58:04 PM PDT 24 |
| Finished | May 16 02:02:15 PM PDT 24 |
| Peak memory | 210252 kb |
| Host | smart-fc2883e4-7377-463d-83e6-abfdd07d9c3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4077941914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4077941914 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4228275085 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5123474006 ps |
| CPU time | 324.85 seconds |
| Started | May 16 01:57:57 PM PDT 24 |
| Finished | May 16 02:03:24 PM PDT 24 |
| Peak memory | 208748 kb |
| Host | smart-cef7b8d1-a864-4761-9d12-b5a88f5149e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4228275085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.4228275085 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1563752169 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 348591966 ps |
| CPU time | 141.03 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 02:00:27 PM PDT 24 |
| Peak memory | 210248 kb |
| Host | smart-6015e86c-889b-473d-97cf-9ac17a88fc4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563752169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1563752169 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1303124625 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 38532479 ps |
| CPU time | 4.31 seconds |
| Started | May 16 01:57:53 PM PDT 24 |
| Finished | May 16 01:58:00 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-764ad027-fb2c-4159-a971-803b4cc0f114 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1303124625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1303124625 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3259370953 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 3221282664 ps |
| CPU time | 59.08 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 01:59:05 PM PDT 24 |
| Peak memory | 205616 kb |
| Host | smart-d21ce90b-97e5-4aef-afc0-6ee0874b405c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3259370953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3259370953 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1219415642 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 87991146644 ps |
| CPU time | 274.57 seconds |
| Started | May 16 01:58:02 PM PDT 24 |
| Finished | May 16 02:02:41 PM PDT 24 |
| Peak memory | 206500 kb |
| Host | smart-2c57e0f2-76d0-4bcb-a759-7a4c7785f132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1219415642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1219415642 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.411135530 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1268741899 ps |
| CPU time | 24.35 seconds |
| Started | May 16 01:58:02 PM PDT 24 |
| Finished | May 16 01:58:30 PM PDT 24 |
| Peak memory | 203584 kb |
| Host | smart-94e5c804-dec6-4404-b59f-03ccd5bb1482 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=411135530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.411135530 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2484136275 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 857658224 ps |
| CPU time | 33.55 seconds |
| Started | May 16 01:58:04 PM PDT 24 |
| Finished | May 16 01:58:40 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-bd1f7b8f-bbd7-4351-9677-6f2c63ad6792 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2484136275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2484136275 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2271077943 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1179000860 ps |
| CPU time | 14.15 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 01:58:20 PM PDT 24 |
| Peak memory | 211592 kb |
| Host | smart-ae4ec424-ca82-428b-b5a4-a66351959d61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2271077943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2271077943 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.1552612384 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 30381406531 ps |
| CPU time | 163.7 seconds |
| Started | May 16 01:58:05 PM PDT 24 |
| Finished | May 16 02:00:51 PM PDT 24 |
| Peak memory | 211552 kb |
| Host | smart-8312ecb9-b1d1-4931-8419-fbb42b3a30bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552612384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1552612384 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3851168199 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 231867676 ps |
| CPU time | 14.61 seconds |
| Started | May 16 01:58:06 PM PDT 24 |
| Finished | May 16 01:58:22 PM PDT 24 |
| Peak memory | 204728 kb |
| Host | smart-4aed23d0-f974-4fc3-92ca-b4bc86ba6811 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851168199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3851168199 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2313404515 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 596562656 ps |
| CPU time | 11.91 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 01:58:19 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-be561206-ba42-406f-aeae-6235656af710 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2313404515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2313404515 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.3702775899 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 479187448 ps |
| CPU time | 3.45 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 01:58:10 PM PDT 24 |
| Peak memory | 203388 kb |
| Host | smart-b7b61485-fabd-4f21-9bba-c5f16f73a879 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3702775899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3702775899 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1082853863 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 20419827591 ps |
| CPU time | 41.74 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 01:58:48 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-a0cd1641-75c4-4891-b17b-264c366bed48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082853863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1082853863 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1698235617 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3077834943 ps |
| CPU time | 26 seconds |
| Started | May 16 01:58:02 PM PDT 24 |
| Finished | May 16 01:58:32 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-74c5516c-109a-4c48-be7d-25a1be2911c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1698235617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1698235617 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3245012244 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 27813962 ps |
| CPU time | 1.99 seconds |
| Started | May 16 01:58:04 PM PDT 24 |
| Finished | May 16 01:58:09 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-7c8d94bd-d372-4e1e-8709-c2e7e19b7b8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245012244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3245012244 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3184498784 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3889551348 ps |
| CPU time | 74.25 seconds |
| Started | May 16 01:58:03 PM PDT 24 |
| Finished | May 16 01:59:21 PM PDT 24 |
| Peak memory | 207900 kb |
| Host | smart-ee668245-9325-4142-a123-5ab03e6a345b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3184498784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3184498784 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3233711116 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2971629145 ps |
| CPU time | 97.59 seconds |
| Started | May 16 01:58:04 PM PDT 24 |
| Finished | May 16 01:59:44 PM PDT 24 |
| Peak memory | 206208 kb |
| Host | smart-bd57f840-cc15-4c3d-9b25-6c886d18ecfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3233711116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3233711116 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1369762692 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 129449349 ps |
| CPU time | 89.22 seconds |
| Started | May 16 01:58:02 PM PDT 24 |
| Finished | May 16 01:59:35 PM PDT 24 |
| Peak memory | 208564 kb |
| Host | smart-aca6b53e-5bf8-4ea1-a1f1-a66c4623a0eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1369762692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.1369762692 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.257591867 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 23851978 ps |
| CPU time | 3.14 seconds |
| Started | May 16 01:58:06 PM PDT 24 |
| Finished | May 16 01:58:10 PM PDT 24 |
| Peak memory | 211576 kb |
| Host | smart-b1e1fdab-52b4-4bfc-9098-26b510ed2753 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=257591867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.257591867 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1357695054 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3542044766 ps |
| CPU time | 55.91 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:59:11 PM PDT 24 |
| Peak memory | 206412 kb |
| Host | smart-7f7aa14e-42a5-4d2b-953c-86f654c9281c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1357695054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1357695054 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.32192623 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 23401104801 ps |
| CPU time | 221.65 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 02:01:58 PM PDT 24 |
| Peak memory | 206024 kb |
| Host | smart-a855d725-0a2b-4e2c-aca5-692a3f77ffff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=32192623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow _rsp.32192623 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2843654489 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 808898335 ps |
| CPU time | 20.6 seconds |
| Started | May 16 01:58:13 PM PDT 24 |
| Finished | May 16 01:58:35 PM PDT 24 |
| Peak memory | 203992 kb |
| Host | smart-4242b450-c091-4013-9a41-29fcc8006c2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2843654489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2843654489 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.2299311428 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4900110962 ps |
| CPU time | 31.59 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:58:48 PM PDT 24 |
| Peak memory | 203920 kb |
| Host | smart-89f81756-51d9-44f0-ba2b-23598b607d6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2299311428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2299311428 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.2809566029 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 217996263 ps |
| CPU time | 12.16 seconds |
| Started | May 16 01:58:13 PM PDT 24 |
| Finished | May 16 01:58:27 PM PDT 24 |
| Peak memory | 204488 kb |
| Host | smart-1e629950-9440-4abf-b8c8-7bb9aec27718 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2809566029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2809566029 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1097361803 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 48775502490 ps |
| CPU time | 255.12 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 02:02:31 PM PDT 24 |
| Peak memory | 204708 kb |
| Host | smart-010381c8-8803-4638-88d2-038e7bd027a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097361803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1097361803 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2091255233 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 67636821258 ps |
| CPU time | 146.16 seconds |
| Started | May 16 01:58:15 PM PDT 24 |
| Finished | May 16 02:00:43 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-5548f671-3bfd-4e95-b9f5-e6148953dac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2091255233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2091255233 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3518711321 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 249497906 ps |
| CPU time | 15.38 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:58:31 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-b5413d43-96bb-4904-9dcb-16ea2b98916b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518711321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3518711321 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.717045100 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 82415880 ps |
| CPU time | 6.36 seconds |
| Started | May 16 01:58:15 PM PDT 24 |
| Finished | May 16 01:58:23 PM PDT 24 |
| Peak memory | 204036 kb |
| Host | smart-e2cd4abf-53b4-4f7d-ba9f-a086cce2d892 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=717045100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.717045100 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1569938541 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 508162910 ps |
| CPU time | 3.76 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:58:19 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-f3ae2d4b-41a3-4576-9c54-17d8f8ad9179 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1569938541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1569938541 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2711237539 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 20947702905 ps |
| CPU time | 46.03 seconds |
| Started | May 16 01:58:15 PM PDT 24 |
| Finished | May 16 01:59:03 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-3169e645-e56a-486d-bd30-d812684751c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711237539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2711237539 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1960846926 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3481489798 ps |
| CPU time | 29.43 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:58:46 PM PDT 24 |
| Peak memory | 203504 kb |
| Host | smart-223ce52f-28e4-45ff-805a-3822b7a1eb95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1960846926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1960846926 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.801516216 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 56398160 ps |
| CPU time | 2.03 seconds |
| Started | May 16 01:58:13 PM PDT 24 |
| Finished | May 16 01:58:17 PM PDT 24 |
| Peak memory | 203380 kb |
| Host | smart-1b09998d-5835-4c91-8725-20042cf3cdc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801516216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.801516216 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.339693504 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2053736805 ps |
| CPU time | 87.41 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:59:44 PM PDT 24 |
| Peak memory | 206792 kb |
| Host | smart-e4becc21-3294-4aae-80f7-b96a51b1f47f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=339693504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.339693504 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2841754008 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 403202879 ps |
| CPU time | 54.6 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:59:11 PM PDT 24 |
| Peak memory | 205764 kb |
| Host | smart-c80b1dc9-67c9-456e-8c50-9df1a0d634a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2841754008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2841754008 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3956329062 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 4390432907 ps |
| CPU time | 584.36 seconds |
| Started | May 16 01:58:15 PM PDT 24 |
| Finished | May 16 02:08:01 PM PDT 24 |
| Peak memory | 209736 kb |
| Host | smart-667f64a3-778d-430f-8eec-8c52078282ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3956329062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3956329062 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1518772289 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 9597169964 ps |
| CPU time | 230.32 seconds |
| Started | May 16 01:58:13 PM PDT 24 |
| Finished | May 16 02:02:05 PM PDT 24 |
| Peak memory | 219896 kb |
| Host | smart-3077d2dd-8b37-478a-821e-fedbe6b5d772 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1518772289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.1518772289 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.822635820 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 555587258 ps |
| CPU time | 9.73 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:58:26 PM PDT 24 |
| Peak memory | 211544 kb |
| Host | smart-0f2f5fcf-07ee-4c44-b972-d10178ff662c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=822635820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.822635820 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1570890618 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3844643847 ps |
| CPU time | 69.04 seconds |
| Started | May 16 01:58:22 PM PDT 24 |
| Finished | May 16 01:59:33 PM PDT 24 |
| Peak memory | 206796 kb |
| Host | smart-c71ce380-be4f-40e8-abef-c0aa95bc74e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1570890618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1570890618 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3371968467 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 145701438663 ps |
| CPU time | 894.59 seconds |
| Started | May 16 01:58:23 PM PDT 24 |
| Finished | May 16 02:13:20 PM PDT 24 |
| Peak memory | 211700 kb |
| Host | smart-3923b305-761c-4544-8c40-a05b185a9d75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3371968467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.3371968467 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1996408387 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 340780181 ps |
| CPU time | 9.17 seconds |
| Started | May 16 01:58:22 PM PDT 24 |
| Finished | May 16 01:58:34 PM PDT 24 |
| Peak memory | 203680 kb |
| Host | smart-c3af4a1e-ed1e-4930-ad32-0d1a150061a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996408387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1996408387 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.2861061861 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 230862578 ps |
| CPU time | 20.55 seconds |
| Started | May 16 01:58:26 PM PDT 24 |
| Finished | May 16 01:58:48 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-d61aed7b-f642-4c63-aba5-c66755f8dd9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2861061861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2861061861 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.3549180308 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 228909715 ps |
| CPU time | 26.84 seconds |
| Started | May 16 01:58:22 PM PDT 24 |
| Finished | May 16 01:58:51 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-e6afd0c3-7910-48c3-84cc-fbdf677531e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3549180308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3549180308 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.300124479 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 11535205065 ps |
| CPU time | 56.73 seconds |
| Started | May 16 01:58:23 PM PDT 24 |
| Finished | May 16 01:59:22 PM PDT 24 |
| Peak memory | 204680 kb |
| Host | smart-98c7c460-0c27-4fa4-bd04-c0e9fdcbea75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=300124479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.300124479 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3502860515 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 59021059 ps |
| CPU time | 3.99 seconds |
| Started | May 16 01:58:23 PM PDT 24 |
| Finished | May 16 01:58:29 PM PDT 24 |
| Peak memory | 203892 kb |
| Host | smart-ac90d18f-07bd-4aad-8c57-a4d80837c914 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502860515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3502860515 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.2645960490 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 344900756 ps |
| CPU time | 19.04 seconds |
| Started | May 16 01:58:23 PM PDT 24 |
| Finished | May 16 01:58:44 PM PDT 24 |
| Peak memory | 204040 kb |
| Host | smart-bc65262e-3768-41d2-8d46-2b7dfaefb4b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2645960490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2645960490 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.2186580867 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 60976523 ps |
| CPU time | 2.32 seconds |
| Started | May 16 01:58:14 PM PDT 24 |
| Finished | May 16 01:58:18 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-320af6c6-a361-4bf0-9bd2-1cfa02b0c922 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186580867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2186580867 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.4249929250 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 9378673590 ps |
| CPU time | 28.11 seconds |
| Started | May 16 01:58:26 PM PDT 24 |
| Finished | May 16 01:58:56 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-065b5d71-ea63-402d-9907-de8e3fed0f22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249929250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.4249929250 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1871119186 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 5268602121 ps |
| CPU time | 33.63 seconds |
| Started | May 16 01:58:21 PM PDT 24 |
| Finished | May 16 01:58:56 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-0f86b004-14e2-4c2a-9a3f-d30eb1c63b5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1871119186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1871119186 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3851662278 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29694179 ps |
| CPU time | 2.32 seconds |
| Started | May 16 01:58:23 PM PDT 24 |
| Finished | May 16 01:58:28 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-4a82fcb4-4895-4d66-a72f-b708b41467f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851662278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3851662278 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1633577657 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 600200805 ps |
| CPU time | 35.98 seconds |
| Started | May 16 01:58:23 PM PDT 24 |
| Finished | May 16 01:59:01 PM PDT 24 |
| Peak memory | 211544 kb |
| Host | smart-c2f8af95-ad58-42ca-8fa2-b88ee5750d2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1633577657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1633577657 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3360073537 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1385639637 ps |
| CPU time | 107.6 seconds |
| Started | May 16 01:58:32 PM PDT 24 |
| Finished | May 16 02:00:21 PM PDT 24 |
| Peak memory | 207624 kb |
| Host | smart-0b5e147c-4492-41f9-8801-8e6f9335b32f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3360073537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3360073537 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.138211261 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 479096374 ps |
| CPU time | 101.89 seconds |
| Started | May 16 01:58:23 PM PDT 24 |
| Finished | May 16 02:00:07 PM PDT 24 |
| Peak memory | 207260 kb |
| Host | smart-9f406bdb-7aba-4cfd-9b4c-6a197ad4a1a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=138211261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.138211261 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.528000808 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 7115299556 ps |
| CPU time | 174.15 seconds |
| Started | May 16 01:58:31 PM PDT 24 |
| Finished | May 16 02:01:27 PM PDT 24 |
| Peak memory | 210472 kb |
| Host | smart-3fcc9cf4-65c2-4540-9d3e-47fb7edf4c32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=528000808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res et_error.528000808 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1435158495 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 53666903 ps |
| CPU time | 5.22 seconds |
| Started | May 16 01:58:26 PM PDT 24 |
| Finished | May 16 01:58:33 PM PDT 24 |
| Peak memory | 211580 kb |
| Host | smart-e8a6a025-aff1-4c28-ac1f-81f2e726bd9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1435158495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1435158495 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1941277463 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2430146443 ps |
| CPU time | 61.73 seconds |
| Started | May 16 01:58:40 PM PDT 24 |
| Finished | May 16 01:59:44 PM PDT 24 |
| Peak memory | 205608 kb |
| Host | smart-12baf11e-bb6c-4b69-b353-8a6f17389fc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941277463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1941277463 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2965528295 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 131969688875 ps |
| CPU time | 486 seconds |
| Started | May 16 01:58:41 PM PDT 24 |
| Finished | May 16 02:06:49 PM PDT 24 |
| Peak memory | 211536 kb |
| Host | smart-e74e921a-7bcc-4069-85e3-3462fb983a8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2965528295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.2965528295 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2791729173 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 93228837 ps |
| CPU time | 9.88 seconds |
| Started | May 16 01:58:41 PM PDT 24 |
| Finished | May 16 01:58:53 PM PDT 24 |
| Peak memory | 203724 kb |
| Host | smart-c8ba94fa-b8a4-4a94-8341-91262f34c27c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2791729173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2791729173 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.2323503061 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 346122693 ps |
| CPU time | 14.05 seconds |
| Started | May 16 01:58:41 PM PDT 24 |
| Finished | May 16 01:58:57 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-77e31f5d-19ba-475c-8c4f-8c9c1a866087 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2323503061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2323503061 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.3865782151 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 107568716 ps |
| CPU time | 4.14 seconds |
| Started | May 16 01:58:32 PM PDT 24 |
| Finished | May 16 01:58:38 PM PDT 24 |
| Peak memory | 204008 kb |
| Host | smart-6d0ff948-b41b-43ec-9f07-cb4b4ab1ccdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3865782151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3865782151 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2064716781 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 24037341369 ps |
| CPU time | 104.37 seconds |
| Started | May 16 01:58:30 PM PDT 24 |
| Finished | May 16 02:00:16 PM PDT 24 |
| Peak memory | 204752 kb |
| Host | smart-c9c0c608-8589-4bcf-b056-1e86c50a2c0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064716781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2064716781 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1810956559 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 9422221050 ps |
| CPU time | 65.96 seconds |
| Started | May 16 01:58:41 PM PDT 24 |
| Finished | May 16 01:59:48 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-aae2a7ee-7e87-41af-8951-6de1aadfbe2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1810956559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1810956559 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.710257387 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 158398974 ps |
| CPU time | 8.6 seconds |
| Started | May 16 01:58:32 PM PDT 24 |
| Finished | May 16 01:58:42 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-4e468e79-4812-4e8e-a0cc-fb01935cc00f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710257387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.710257387 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2428906423 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1060746797 ps |
| CPU time | 25.67 seconds |
| Started | May 16 01:58:43 PM PDT 24 |
| Finished | May 16 01:59:11 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-c31a7e01-d394-425d-b2a0-bb87fc29977a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2428906423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2428906423 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.2429618745 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 48758694 ps |
| CPU time | 2.31 seconds |
| Started | May 16 01:58:32 PM PDT 24 |
| Finished | May 16 01:58:36 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-deaea476-2c0e-4fc9-94f1-2973e9eee5ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2429618745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2429618745 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1628726872 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5156291698 ps |
| CPU time | 27.76 seconds |
| Started | May 16 01:58:31 PM PDT 24 |
| Finished | May 16 01:59:01 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-6aaf1571-ad77-424f-a5b5-bebbcb47e27c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628726872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1628726872 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2423508346 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 5651863979 ps |
| CPU time | 35.32 seconds |
| Started | May 16 01:58:30 PM PDT 24 |
| Finished | May 16 01:59:07 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-df788503-f94b-4471-8ede-4a39459bfb49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2423508346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2423508346 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.4087966878 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 27142122 ps |
| CPU time | 2.5 seconds |
| Started | May 16 01:58:32 PM PDT 24 |
| Finished | May 16 01:58:36 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-ad47128b-a6c7-4763-bff2-9f55a2f589bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087966878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.4087966878 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.513985851 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1232908903 ps |
| CPU time | 19.22 seconds |
| Started | May 16 01:58:43 PM PDT 24 |
| Finished | May 16 01:59:04 PM PDT 24 |
| Peak memory | 205220 kb |
| Host | smart-7c710e46-4d09-4169-90e8-5bd85a15812c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=513985851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.513985851 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.231316303 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1513517268 ps |
| CPU time | 132.04 seconds |
| Started | May 16 01:58:44 PM PDT 24 |
| Finished | May 16 02:00:57 PM PDT 24 |
| Peak memory | 207080 kb |
| Host | smart-7b07e1df-effa-4614-b225-e35a0e8c4421 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=231316303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.231316303 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3241159621 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7760964 ps |
| CPU time | 9.45 seconds |
| Started | May 16 01:58:42 PM PDT 24 |
| Finished | May 16 01:58:53 PM PDT 24 |
| Peak memory | 203920 kb |
| Host | smart-f486480f-6d5e-499a-8fac-478950d06d96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3241159621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3241159621 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1680190162 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 178590896 ps |
| CPU time | 81.6 seconds |
| Started | May 16 01:58:42 PM PDT 24 |
| Finished | May 16 02:00:06 PM PDT 24 |
| Peak memory | 208648 kb |
| Host | smart-6b6226e4-0b86-4138-88bf-63bf2869bc2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680190162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.1680190162 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3763627113 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 298089148 ps |
| CPU time | 22.11 seconds |
| Started | May 16 01:58:40 PM PDT 24 |
| Finished | May 16 01:59:04 PM PDT 24 |
| Peak memory | 211596 kb |
| Host | smart-9e9c3960-4d2e-496f-aa87-1b775bd01c7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3763627113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3763627113 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1189500516 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2019038867 ps |
| CPU time | 71.35 seconds |
| Started | May 16 01:58:55 PM PDT 24 |
| Finished | May 16 02:00:09 PM PDT 24 |
| Peak memory | 211600 kb |
| Host | smart-e371eb52-544e-4e98-972d-54612c5da12c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1189500516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1189500516 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.183757155 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 228965353003 ps |
| CPU time | 704.58 seconds |
| Started | May 16 01:58:52 PM PDT 24 |
| Finished | May 16 02:10:38 PM PDT 24 |
| Peak memory | 207556 kb |
| Host | smart-50ed9d93-b4ca-4764-adf9-5f8b9752a725 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=183757155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo w_rsp.183757155 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.4244078331 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 325433861 ps |
| CPU time | 10.08 seconds |
| Started | May 16 01:58:55 PM PDT 24 |
| Finished | May 16 01:59:07 PM PDT 24 |
| Peak memory | 203732 kb |
| Host | smart-f05a5a6c-6e29-414b-8c2f-66370f95632a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4244078331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.4244078331 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1496508623 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 935340333 ps |
| CPU time | 21.3 seconds |
| Started | May 16 01:58:54 PM PDT 24 |
| Finished | May 16 01:59:17 PM PDT 24 |
| Peak memory | 203380 kb |
| Host | smart-4417d6e9-8d99-41be-aefe-1c1ea2af37e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1496508623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1496508623 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2306542596 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1068014364 ps |
| CPU time | 36.87 seconds |
| Started | May 16 01:58:53 PM PDT 24 |
| Finished | May 16 01:59:31 PM PDT 24 |
| Peak memory | 204724 kb |
| Host | smart-76f2ccee-2564-446e-8480-8540a315e794 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2306542596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2306542596 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1363283045 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 22787045307 ps |
| CPU time | 72.89 seconds |
| Started | May 16 01:58:52 PM PDT 24 |
| Finished | May 16 02:00:07 PM PDT 24 |
| Peak memory | 211688 kb |
| Host | smart-17d69d9c-5daa-4dad-be38-a1593f1b1b0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363283045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1363283045 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1271203451 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 10086779170 ps |
| CPU time | 52.73 seconds |
| Started | May 16 01:58:52 PM PDT 24 |
| Finished | May 16 01:59:47 PM PDT 24 |
| Peak memory | 211684 kb |
| Host | smart-9407d1a4-581f-4dbc-8b25-ffafa4805268 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1271203451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1271203451 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3191803645 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 248339882 ps |
| CPU time | 19.27 seconds |
| Started | May 16 01:58:53 PM PDT 24 |
| Finished | May 16 01:59:14 PM PDT 24 |
| Peak memory | 211624 kb |
| Host | smart-c2b10bf0-860f-40e3-8c11-60879f8f2c50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191803645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3191803645 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2442112311 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1083360591 ps |
| CPU time | 22.54 seconds |
| Started | May 16 01:58:51 PM PDT 24 |
| Finished | May 16 01:59:15 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-2e95511f-4005-4dd6-ba45-a71276e9b951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2442112311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2442112311 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.1570530940 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 127799141 ps |
| CPU time | 3.49 seconds |
| Started | May 16 01:58:41 PM PDT 24 |
| Finished | May 16 01:58:47 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-d4b41369-7230-44b6-8081-319cc1548094 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1570530940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1570530940 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1700251751 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 49642592677 ps |
| CPU time | 52.73 seconds |
| Started | May 16 01:58:55 PM PDT 24 |
| Finished | May 16 01:59:49 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-7705b940-62f6-4bb4-b477-5dd2b356bbe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700251751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1700251751 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.795692574 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5980006775 ps |
| CPU time | 34.01 seconds |
| Started | May 16 01:58:53 PM PDT 24 |
| Finished | May 16 01:59:28 PM PDT 24 |
| Peak memory | 203396 kb |
| Host | smart-f443121e-bf2b-41fd-b84e-9725a9375ef9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=795692574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.795692574 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3111416457 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 30049133 ps |
| CPU time | 2.31 seconds |
| Started | May 16 01:58:43 PM PDT 24 |
| Finished | May 16 01:58:47 PM PDT 24 |
| Peak memory | 203416 kb |
| Host | smart-1cc65f2f-d0a3-419b-b81c-ef529fae6b2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111416457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3111416457 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3942189552 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4866183482 ps |
| CPU time | 112.3 seconds |
| Started | May 16 01:58:53 PM PDT 24 |
| Finished | May 16 02:00:47 PM PDT 24 |
| Peak memory | 207096 kb |
| Host | smart-24a8f5c0-6247-4475-865b-d7e7c3352a2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3942189552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3942189552 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.387225047 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 6052215147 ps |
| CPU time | 148.94 seconds |
| Started | May 16 01:58:53 PM PDT 24 |
| Finished | May 16 02:01:23 PM PDT 24 |
| Peak memory | 211660 kb |
| Host | smart-b7a5ae5a-c261-4cff-95db-8a22b3e6d603 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=387225047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.387225047 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.4049660720 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 896904415 ps |
| CPU time | 263.81 seconds |
| Started | May 16 01:58:55 PM PDT 24 |
| Finished | May 16 02:03:21 PM PDT 24 |
| Peak memory | 210048 kb |
| Host | smart-58cdfddd-b265-438c-817a-6864af4418bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049660720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.4049660720 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3925263451 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 525620594 ps |
| CPU time | 93.9 seconds |
| Started | May 16 01:58:53 PM PDT 24 |
| Finished | May 16 02:00:29 PM PDT 24 |
| Peak memory | 209504 kb |
| Host | smart-bd90da3d-1e75-4c2d-93e6-e7c786e0d1de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3925263451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3925263451 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2551792158 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 263666698 ps |
| CPU time | 9.72 seconds |
| Started | May 16 01:58:52 PM PDT 24 |
| Finished | May 16 01:59:03 PM PDT 24 |
| Peak memory | 211564 kb |
| Host | smart-2e44e1fe-e29c-49df-985a-5ffd61e93909 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2551792158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2551792158 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1367970092 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5542825010 ps |
| CPU time | 65.45 seconds |
| Started | May 16 01:59:03 PM PDT 24 |
| Finished | May 16 02:00:10 PM PDT 24 |
| Peak memory | 211676 kb |
| Host | smart-0d489ea7-0967-43a2-b486-752dd35e81f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1367970092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1367970092 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1952392450 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 60359535537 ps |
| CPU time | 411.01 seconds |
| Started | May 16 01:59:01 PM PDT 24 |
| Finished | May 16 02:05:53 PM PDT 24 |
| Peak memory | 206996 kb |
| Host | smart-908e77df-c7fd-45eb-b3a4-2c4165d1f4da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1952392450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1952392450 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.63644290 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 102687280 ps |
| CPU time | 14.93 seconds |
| Started | May 16 01:59:02 PM PDT 24 |
| Finished | May 16 01:59:19 PM PDT 24 |
| Peak memory | 203736 kb |
| Host | smart-9d31eba5-72ea-411f-a684-6e20b744fed2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=63644290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.63644290 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.122070317 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 786221760 ps |
| CPU time | 19.79 seconds |
| Started | May 16 01:59:02 PM PDT 24 |
| Finished | May 16 01:59:24 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-8014d1aa-f6db-402e-a1cc-20af03a1ceb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=122070317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.122070317 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.3127115924 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 883313491 ps |
| CPU time | 36.9 seconds |
| Started | May 16 01:59:01 PM PDT 24 |
| Finished | May 16 01:59:40 PM PDT 24 |
| Peak memory | 204756 kb |
| Host | smart-03f7d6ec-69d9-456b-8589-fbc752bd2210 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127115924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3127115924 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2036150051 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 148496971889 ps |
| CPU time | 173.12 seconds |
| Started | May 16 01:59:02 PM PDT 24 |
| Finished | May 16 02:01:57 PM PDT 24 |
| Peak memory | 204664 kb |
| Host | smart-64ac7f74-1b20-4f77-8a26-86f5d07d30ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036150051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2036150051 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3358178275 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 134984237856 ps |
| CPU time | 320.68 seconds |
| Started | May 16 01:59:00 PM PDT 24 |
| Finished | May 16 02:04:23 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-1b4712a0-d9a8-42ec-b197-2d13a674d1ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3358178275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3358178275 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2322007029 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 368972246 ps |
| CPU time | 27.7 seconds |
| Started | May 16 01:59:02 PM PDT 24 |
| Finished | May 16 01:59:31 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-1b0fef1b-cfad-4692-a3ee-a058154ed9d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322007029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2322007029 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.4181833296 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 175388593 ps |
| CPU time | 2.97 seconds |
| Started | May 16 01:59:01 PM PDT 24 |
| Finished | May 16 01:59:06 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-745fad3f-639a-4001-8758-420ebea239f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4181833296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4181833296 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.3302545397 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 166168205 ps |
| CPU time | 4.17 seconds |
| Started | May 16 01:58:51 PM PDT 24 |
| Finished | May 16 01:58:57 PM PDT 24 |
| Peak memory | 203388 kb |
| Host | smart-54236ad2-d3b7-43d5-b434-8ad0da0ce696 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3302545397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3302545397 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1894747889 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 7771105580 ps |
| CPU time | 39.92 seconds |
| Started | May 16 01:59:03 PM PDT 24 |
| Finished | May 16 01:59:45 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-4c13fe0c-4987-492f-acd9-b29ab05742f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894747889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1894747889 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2695782730 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 16887185057 ps |
| CPU time | 37.67 seconds |
| Started | May 16 01:59:02 PM PDT 24 |
| Finished | May 16 01:59:42 PM PDT 24 |
| Peak memory | 203504 kb |
| Host | smart-577aee23-b0e6-4db2-a179-b4b64ea24fb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2695782730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2695782730 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.58740143 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 100942881 ps |
| CPU time | 2.48 seconds |
| Started | May 16 01:58:51 PM PDT 24 |
| Finished | May 16 01:58:55 PM PDT 24 |
| Peak memory | 203284 kb |
| Host | smart-7c4e42e5-f551-4f84-b3a8-ce4f0122793d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58740143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.58740143 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3497126618 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 7240438611 ps |
| CPU time | 178.23 seconds |
| Started | May 16 01:59:01 PM PDT 24 |
| Finished | May 16 02:02:02 PM PDT 24 |
| Peak memory | 208464 kb |
| Host | smart-ed56e576-6a0f-44dc-9b8b-b2a6c4f8d867 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3497126618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3497126618 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2633531826 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 30539427339 ps |
| CPU time | 176.4 seconds |
| Started | May 16 01:59:00 PM PDT 24 |
| Finished | May 16 02:01:58 PM PDT 24 |
| Peak memory | 208496 kb |
| Host | smart-e5e949e9-ab49-48e7-847a-a0b47c356f2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2633531826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2633531826 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2493048931 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 88186130 ps |
| CPU time | 21.96 seconds |
| Started | May 16 01:59:02 PM PDT 24 |
| Finished | May 16 01:59:26 PM PDT 24 |
| Peak memory | 206184 kb |
| Host | smart-ce3b1ff9-4e6c-4539-a5a0-b36a6c89cc9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2493048931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2493048931 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3770369397 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 16694291586 ps |
| CPU time | 384.14 seconds |
| Started | May 16 01:59:03 PM PDT 24 |
| Finished | May 16 02:05:29 PM PDT 24 |
| Peak memory | 219884 kb |
| Host | smart-c9307ad9-3fec-439e-8409-23c81d108da7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3770369397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.3770369397 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1018294227 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1877358878 ps |
| CPU time | 29.7 seconds |
| Started | May 16 01:59:03 PM PDT 24 |
| Finished | May 16 01:59:34 PM PDT 24 |
| Peak memory | 205028 kb |
| Host | smart-af5f0480-1f91-4dfa-8812-8024089af1a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1018294227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1018294227 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2378684669 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1444688872 ps |
| CPU time | 67.17 seconds |
| Started | May 16 01:59:12 PM PDT 24 |
| Finished | May 16 02:00:22 PM PDT 24 |
| Peak memory | 205836 kb |
| Host | smart-859c764d-6aa2-4d32-aa89-c32906bd4ad9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2378684669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2378684669 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1403927635 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 22328352665 ps |
| CPU time | 162.59 seconds |
| Started | May 16 01:59:10 PM PDT 24 |
| Finished | May 16 02:01:54 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-6d52c30a-ddea-49a1-90d7-5797deb1cf1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1403927635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.1403927635 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1323775319 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 30748347 ps |
| CPU time | 2.45 seconds |
| Started | May 16 01:59:12 PM PDT 24 |
| Finished | May 16 01:59:17 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-e1171be1-9ccc-4fa4-b913-44d8c75374df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1323775319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1323775319 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3021737327 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1335719365 ps |
| CPU time | 30.69 seconds |
| Started | May 16 01:59:10 PM PDT 24 |
| Finished | May 16 01:59:43 PM PDT 24 |
| Peak memory | 203524 kb |
| Host | smart-a8e770d0-5506-498c-8d92-3e96f665d0dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3021737327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3021737327 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.1352166596 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1150430291 ps |
| CPU time | 25.16 seconds |
| Started | May 16 01:59:11 PM PDT 24 |
| Finished | May 16 01:59:39 PM PDT 24 |
| Peak memory | 211612 kb |
| Host | smart-416504f7-e875-4b3c-b1e8-91ee8a52989e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1352166596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1352166596 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.774272582 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 118485572021 ps |
| CPU time | 292.23 seconds |
| Started | May 16 01:59:13 PM PDT 24 |
| Finished | May 16 02:04:07 PM PDT 24 |
| Peak memory | 205712 kb |
| Host | smart-533e39b3-647f-4d8c-b1a7-32e450841bdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=774272582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.774272582 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1718407313 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10088846941 ps |
| CPU time | 58.85 seconds |
| Started | May 16 01:59:10 PM PDT 24 |
| Finished | May 16 02:00:11 PM PDT 24 |
| Peak memory | 211684 kb |
| Host | smart-ff855835-f334-4231-ac1f-c2bf1fc078d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1718407313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1718407313 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3086789164 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 362077570 ps |
| CPU time | 27.32 seconds |
| Started | May 16 01:59:12 PM PDT 24 |
| Finished | May 16 01:59:41 PM PDT 24 |
| Peak memory | 211608 kb |
| Host | smart-93ee6230-e17c-4724-9aed-8a3647fb93c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086789164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3086789164 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.3542858305 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1320388019 ps |
| CPU time | 35.14 seconds |
| Started | May 16 01:59:12 PM PDT 24 |
| Finished | May 16 01:59:50 PM PDT 24 |
| Peak memory | 203920 kb |
| Host | smart-a2fa8e73-befd-46ec-82e4-0a41fc5e94ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3542858305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3542858305 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.4227279099 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 138253459 ps |
| CPU time | 3.9 seconds |
| Started | May 16 01:59:01 PM PDT 24 |
| Finished | May 16 01:59:07 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-f857580a-c310-4b43-9e5d-a2fb1a5dde06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4227279099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.4227279099 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2836147411 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4981711326 ps |
| CPU time | 26.86 seconds |
| Started | May 16 01:59:11 PM PDT 24 |
| Finished | May 16 01:59:39 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-63e5f732-a945-481c-88ec-ac17eb203513 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836147411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2836147411 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2932507163 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4745563973 ps |
| CPU time | 26.79 seconds |
| Started | May 16 01:59:11 PM PDT 24 |
| Finished | May 16 01:59:40 PM PDT 24 |
| Peak memory | 203464 kb |
| Host | smart-6735f9dd-e6f6-4b5a-b5ed-10c3ef16caf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2932507163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2932507163 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.4078946822 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 44411093 ps |
| CPU time | 2.15 seconds |
| Started | May 16 01:59:12 PM PDT 24 |
| Finished | May 16 01:59:17 PM PDT 24 |
| Peak memory | 203364 kb |
| Host | smart-7cf89622-7220-42b5-89e8-4b9083e46cf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078946822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.4078946822 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.4264191696 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 8782711617 ps |
| CPU time | 299.29 seconds |
| Started | May 16 01:59:12 PM PDT 24 |
| Finished | May 16 02:04:13 PM PDT 24 |
| Peak memory | 207356 kb |
| Host | smart-8ac5b3f5-eeda-4e61-9d29-04e2eb56dcdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4264191696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4264191696 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3224510468 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2314280463 ps |
| CPU time | 70.34 seconds |
| Started | May 16 01:59:10 PM PDT 24 |
| Finished | May 16 02:00:21 PM PDT 24 |
| Peak memory | 205456 kb |
| Host | smart-20f43e13-974f-4e12-887f-b5d8047bf114 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3224510468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3224510468 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.271789719 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2310512732 ps |
| CPU time | 444.62 seconds |
| Started | May 16 01:59:13 PM PDT 24 |
| Finished | May 16 02:06:40 PM PDT 24 |
| Peak memory | 223588 kb |
| Host | smart-b441a23b-4c11-4ddd-a8f8-b15786688f42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=271789719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand _reset.271789719 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3662811831 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3234992605 ps |
| CPU time | 186.24 seconds |
| Started | May 16 01:59:10 PM PDT 24 |
| Finished | May 16 02:02:18 PM PDT 24 |
| Peak memory | 211664 kb |
| Host | smart-e0e926d4-6371-4e4a-8fc1-e26cbd3090ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3662811831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.3662811831 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1508826688 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1585836755 ps |
| CPU time | 20.55 seconds |
| Started | May 16 01:59:13 PM PDT 24 |
| Finished | May 16 01:59:36 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-755ca204-250c-4ea2-b5a9-0a4cb04b4469 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508826688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1508826688 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1158144805 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1489600049 ps |
| CPU time | 31.51 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:50 PM PDT 24 |
| Peak memory | 205552 kb |
| Host | smart-9be15b4f-5d22-4065-8151-ac08081a8061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1158144805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1158144805 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1811277850 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 31640883026 ps |
| CPU time | 183.37 seconds |
| Started | May 16 01:52:17 PM PDT 24 |
| Finished | May 16 01:55:22 PM PDT 24 |
| Peak memory | 205900 kb |
| Host | smart-e7e8f542-536e-4a66-828b-542784f2d5a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1811277850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.1811277850 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1408242013 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 278622813 ps |
| CPU time | 11.3 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:52:32 PM PDT 24 |
| Peak memory | 203604 kb |
| Host | smart-256b6f89-507d-493b-a996-09682d62ea98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1408242013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1408242013 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.1518538815 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 782703604 ps |
| CPU time | 29.12 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:52:50 PM PDT 24 |
| Peak memory | 203456 kb |
| Host | smart-b0d84df8-efd9-4b45-bb9d-8de7c5abf6a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1518538815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1518538815 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.3316058711 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 591375510 ps |
| CPU time | 19.27 seconds |
| Started | May 16 01:52:19 PM PDT 24 |
| Finished | May 16 01:52:40 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-c30b6a39-5c2f-4d75-a84c-a6a2f94b6366 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316058711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3316058711 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1288871921 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5467459459 ps |
| CPU time | 26.55 seconds |
| Started | May 16 01:52:19 PM PDT 24 |
| Finished | May 16 01:52:48 PM PDT 24 |
| Peak memory | 211688 kb |
| Host | smart-b87faeab-dc6d-4dce-a780-3c77b9ecfbe5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288871921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1288871921 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.194988887 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 21709629478 ps |
| CPU time | 225.04 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:56:03 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-a64a3770-5dc6-4cd7-abfc-0a93ebb7daad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=194988887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.194988887 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3143180701 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 132818332 ps |
| CPU time | 21.2 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:52:42 PM PDT 24 |
| Peak memory | 204756 kb |
| Host | smart-c249f58e-cad5-428a-8d59-5e549dc9c6fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143180701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3143180701 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.1962309198 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 507171399 ps |
| CPU time | 7.27 seconds |
| Started | May 16 01:52:17 PM PDT 24 |
| Finished | May 16 01:52:27 PM PDT 24 |
| Peak memory | 203836 kb |
| Host | smart-67f613c2-fb70-42aa-b7d0-b453a37238f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1962309198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1962309198 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2423051403 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 29010411 ps |
| CPU time | 2.3 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:20 PM PDT 24 |
| Peak memory | 203376 kb |
| Host | smart-e46e6d18-3103-4880-bb32-b69cca8c59c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2423051403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2423051403 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3798064080 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 25930846570 ps |
| CPU time | 34.8 seconds |
| Started | May 16 01:52:20 PM PDT 24 |
| Finished | May 16 01:52:57 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-2b15ec5f-bd80-4f2f-9df3-fd95e307f9d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798064080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3798064080 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3762556650 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 10100878033 ps |
| CPU time | 36.19 seconds |
| Started | May 16 01:52:19 PM PDT 24 |
| Finished | May 16 01:52:58 PM PDT 24 |
| Peak memory | 203480 kb |
| Host | smart-e81b45c3-24d8-498d-a0f4-4debb5bc06d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3762556650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3762556650 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2185488627 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 97039755 ps |
| CPU time | 2.57 seconds |
| Started | May 16 01:52:17 PM PDT 24 |
| Finished | May 16 01:52:22 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-d8023656-3a7d-429b-85f3-26b86dc9842e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185488627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2185488627 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1699412214 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 4385677572 ps |
| CPU time | 182.51 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:55:23 PM PDT 24 |
| Peak memory | 207156 kb |
| Host | smart-bce72cf9-e0e5-41ce-8094-4a2f4972da31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699412214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1699412214 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.58597927 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 565331919 ps |
| CPU time | 64.4 seconds |
| Started | May 16 01:52:19 PM PDT 24 |
| Finished | May 16 01:53:26 PM PDT 24 |
| Peak memory | 205992 kb |
| Host | smart-bd549fa9-8f1c-4bef-a173-0f77c68c1cf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=58597927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.58597927 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1959805258 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 74581215 ps |
| CPU time | 32.07 seconds |
| Started | May 16 01:52:19 PM PDT 24 |
| Finished | May 16 01:52:53 PM PDT 24 |
| Peak memory | 206984 kb |
| Host | smart-af7cb2f1-5dc6-4de1-a211-2fcaada85f9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1959805258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.1959805258 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.858075431 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1557939617 ps |
| CPU time | 113.91 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:54:12 PM PDT 24 |
| Peak memory | 209228 kb |
| Host | smart-12272417-6d73-4c91-b89c-a75e83e72bbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858075431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.858075431 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1735227183 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 134262558 ps |
| CPU time | 18.97 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:52:39 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-00f5e5b3-a749-4f63-9a8c-bf17f40562a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1735227183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1735227183 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.2993452623 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2126492523 ps |
| CPU time | 66.95 seconds |
| Started | May 16 01:59:23 PM PDT 24 |
| Finished | May 16 02:00:32 PM PDT 24 |
| Peak memory | 205532 kb |
| Host | smart-c04fd459-68a9-47cd-a33a-b6a0f35a22d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2993452623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.2993452623 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1444772696 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 63847721303 ps |
| CPU time | 588.32 seconds |
| Started | May 16 01:59:22 PM PDT 24 |
| Finished | May 16 02:09:13 PM PDT 24 |
| Peak memory | 207360 kb |
| Host | smart-4d2896ef-3d06-4535-bd33-927a521c591a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1444772696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.1444772696 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.885580666 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 795472926 ps |
| CPU time | 12.69 seconds |
| Started | May 16 01:59:38 PM PDT 24 |
| Finished | May 16 01:59:54 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-4046637f-4133-46e4-9ec1-6c156bc17ff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=885580666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.885580666 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3329548623 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1027178540 ps |
| CPU time | 36.6 seconds |
| Started | May 16 01:59:35 PM PDT 24 |
| Finished | May 16 02:00:13 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-5c98365f-1d96-454e-8739-d5a1243efeca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3329548623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3329548623 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.3605448148 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 127802489 ps |
| CPU time | 20.58 seconds |
| Started | May 16 01:59:23 PM PDT 24 |
| Finished | May 16 01:59:45 PM PDT 24 |
| Peak memory | 211536 kb |
| Host | smart-d27f7a4d-3e56-4a09-a0bd-556fa362f7ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605448148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3605448148 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.4123194161 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 13300530169 ps |
| CPU time | 79.32 seconds |
| Started | May 16 01:59:24 PM PDT 24 |
| Finished | May 16 02:00:46 PM PDT 24 |
| Peak memory | 211684 kb |
| Host | smart-7ea1d572-f53b-4206-8ae5-3a3441e1a662 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123194161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4123194161 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2998330094 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 18051340983 ps |
| CPU time | 113.37 seconds |
| Started | May 16 01:59:24 PM PDT 24 |
| Finished | May 16 02:01:19 PM PDT 24 |
| Peak memory | 204784 kb |
| Host | smart-7929846a-7a5e-43a9-81ba-196449787302 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2998330094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2998330094 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3406774634 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 145673364 ps |
| CPU time | 8.9 seconds |
| Started | May 16 01:59:22 PM PDT 24 |
| Finished | May 16 01:59:33 PM PDT 24 |
| Peak memory | 204668 kb |
| Host | smart-28be1423-211c-450a-a39f-a17607c8ada9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406774634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3406774634 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2567172860 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 466868918 ps |
| CPU time | 11.25 seconds |
| Started | May 16 01:59:24 PM PDT 24 |
| Finished | May 16 01:59:37 PM PDT 24 |
| Peak memory | 203996 kb |
| Host | smart-eca88cf1-1022-4ef1-956d-c7e689b0128f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2567172860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2567172860 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.2069058739 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 240227877 ps |
| CPU time | 3.85 seconds |
| Started | May 16 01:59:11 PM PDT 24 |
| Finished | May 16 01:59:17 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-43b6ca12-a840-4431-8fb0-59b619e01c1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2069058739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2069058739 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.4223745522 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 32241590418 ps |
| CPU time | 47.85 seconds |
| Started | May 16 01:59:23 PM PDT 24 |
| Finished | May 16 02:00:13 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-ae11614f-fa1d-4618-a9eb-ef9a5f746738 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223745522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.4223745522 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1892896856 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 7132109682 ps |
| CPU time | 32.19 seconds |
| Started | May 16 01:59:23 PM PDT 24 |
| Finished | May 16 01:59:57 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-d0a4a7cc-ccb4-4974-b9f7-be4d60eafdf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1892896856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1892896856 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.24365446 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 31052429 ps |
| CPU time | 2.21 seconds |
| Started | May 16 01:59:23 PM PDT 24 |
| Finished | May 16 01:59:28 PM PDT 24 |
| Peak memory | 203352 kb |
| Host | smart-6f444b92-76a8-4c64-a123-621ffe995022 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24365446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.24365446 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3277047253 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 84746513 ps |
| CPU time | 4.99 seconds |
| Started | May 16 01:59:36 PM PDT 24 |
| Finished | May 16 01:59:44 PM PDT 24 |
| Peak memory | 211624 kb |
| Host | smart-5902a64d-64d9-4c67-8867-1f110b90673b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3277047253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3277047253 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3722953526 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1580523919 ps |
| CPU time | 37.92 seconds |
| Started | May 16 01:59:36 PM PDT 24 |
| Finished | May 16 02:00:16 PM PDT 24 |
| Peak memory | 205156 kb |
| Host | smart-0b6a5a04-8060-4dc1-9bee-11c61edc35d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3722953526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3722953526 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3549634589 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 1155868175 ps |
| CPU time | 327.25 seconds |
| Started | May 16 01:59:38 PM PDT 24 |
| Finished | May 16 02:05:08 PM PDT 24 |
| Peak memory | 211640 kb |
| Host | smart-ecd48801-10b3-4d98-b873-603192faab6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3549634589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.3549634589 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.4291120345 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 450316285 ps |
| CPU time | 23.53 seconds |
| Started | May 16 01:59:36 PM PDT 24 |
| Finished | May 16 02:00:01 PM PDT 24 |
| Peak memory | 211580 kb |
| Host | smart-a8d96541-1bf5-4a00-9639-e02382bfaff5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4291120345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.4291120345 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2190769662 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 480130142 ps |
| CPU time | 11.3 seconds |
| Started | May 16 01:59:52 PM PDT 24 |
| Finished | May 16 02:00:05 PM PDT 24 |
| Peak memory | 211568 kb |
| Host | smart-833e7bb3-7b55-4ba6-9422-bf3fe3dd76c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2190769662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2190769662 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.883683556 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4901456841 ps |
| CPU time | 43.07 seconds |
| Started | May 16 01:59:46 PM PDT 24 |
| Finished | May 16 02:00:32 PM PDT 24 |
| Peak memory | 205040 kb |
| Host | smart-96d3e988-fdee-4208-a4d3-e2128f26ec21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=883683556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo w_rsp.883683556 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4238205505 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 139864696 ps |
| CPU time | 17.3 seconds |
| Started | May 16 01:59:47 PM PDT 24 |
| Finished | May 16 02:00:08 PM PDT 24 |
| Peak memory | 203380 kb |
| Host | smart-ff964daf-bfdf-4f3e-941c-a02cab7924a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4238205505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4238205505 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.1775047909 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 41839213 ps |
| CPU time | 5.99 seconds |
| Started | May 16 01:59:52 PM PDT 24 |
| Finished | May 16 02:00:00 PM PDT 24 |
| Peak memory | 203000 kb |
| Host | smart-d84e445a-8ae0-4336-ab7a-efc48f0933c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1775047909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1775047909 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.464255270 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 558503784 ps |
| CPU time | 19.54 seconds |
| Started | May 16 01:59:37 PM PDT 24 |
| Finished | May 16 01:59:58 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-f5bf2526-cb00-4f7e-91e6-fa62e9d349a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464255270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.464255270 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2197673195 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 44602589394 ps |
| CPU time | 122.88 seconds |
| Started | May 16 01:59:37 PM PDT 24 |
| Finished | May 16 02:01:42 PM PDT 24 |
| Peak memory | 204884 kb |
| Host | smart-58582222-f5ce-48f9-9506-79fc0994420f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197673195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2197673195 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3843396751 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12959584140 ps |
| CPU time | 70.88 seconds |
| Started | May 16 01:59:36 PM PDT 24 |
| Finished | May 16 02:00:49 PM PDT 24 |
| Peak memory | 204752 kb |
| Host | smart-4d58987d-adce-4bbf-83fe-c7dc95b053e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3843396751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3843396751 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2889874191 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 94500636 ps |
| CPU time | 15.11 seconds |
| Started | May 16 01:59:36 PM PDT 24 |
| Finished | May 16 01:59:53 PM PDT 24 |
| Peak memory | 211600 kb |
| Host | smart-c3a8fbe8-060f-4055-9cf2-f1594b65e19f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889874191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2889874191 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.1087368065 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 347886393 ps |
| CPU time | 16.35 seconds |
| Started | May 16 01:59:48 PM PDT 24 |
| Finished | May 16 02:00:08 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-df58addd-4bd4-43e9-b0ca-779d6dff6bb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1087368065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1087368065 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3447679296 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 370061677 ps |
| CPU time | 2.99 seconds |
| Started | May 16 01:59:35 PM PDT 24 |
| Finished | May 16 01:59:38 PM PDT 24 |
| Peak memory | 203288 kb |
| Host | smart-8651940a-8d6d-4e4c-a0f3-6f802da38c00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3447679296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3447679296 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.4069251383 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 7650123012 ps |
| CPU time | 30.89 seconds |
| Started | May 16 01:59:37 PM PDT 24 |
| Finished | May 16 02:00:10 PM PDT 24 |
| Peak memory | 203504 kb |
| Host | smart-474591b8-89d4-4ba3-9a51-9e413e62233d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069251383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.4069251383 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3682665579 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 19664629655 ps |
| CPU time | 44.81 seconds |
| Started | May 16 01:59:37 PM PDT 24 |
| Finished | May 16 02:00:23 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-4137964a-ab52-4818-aac1-813e4dafb847 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3682665579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3682665579 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4064136363 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 52516469 ps |
| CPU time | 2.42 seconds |
| Started | May 16 01:59:39 PM PDT 24 |
| Finished | May 16 01:59:44 PM PDT 24 |
| Peak memory | 203420 kb |
| Host | smart-11df72cb-671a-49ea-97ad-42a0ce77533b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064136363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.4064136363 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.3858770571 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1035638224 ps |
| CPU time | 53.69 seconds |
| Started | May 16 01:59:52 PM PDT 24 |
| Finished | May 16 02:00:47 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-1beb5d97-f828-4b0b-9593-d22e5afb0b28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3858770571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3858770571 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1204553331 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1155066599 ps |
| CPU time | 68.29 seconds |
| Started | May 16 01:59:46 PM PDT 24 |
| Finished | May 16 02:00:58 PM PDT 24 |
| Peak memory | 205748 kb |
| Host | smart-33f8aed6-8f69-4f04-a21c-d90ea2a0086f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1204553331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1204553331 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1394952899 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 169440799 ps |
| CPU time | 98.82 seconds |
| Started | May 16 01:59:48 PM PDT 24 |
| Finished | May 16 02:01:30 PM PDT 24 |
| Peak memory | 207372 kb |
| Host | smart-3ce70d0e-5e6c-4d5b-abd9-5a4fb5d9878d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1394952899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1394952899 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.371364399 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 12186309517 ps |
| CPU time | 370.04 seconds |
| Started | May 16 01:59:45 PM PDT 24 |
| Finished | May 16 02:05:58 PM PDT 24 |
| Peak memory | 219892 kb |
| Host | smart-07b0fd11-7918-4350-b071-c0a645823fd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371364399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.371364399 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3361298743 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 231036348 ps |
| CPU time | 2.53 seconds |
| Started | May 16 01:59:53 PM PDT 24 |
| Finished | May 16 01:59:57 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-a2c35451-fbb1-4ef2-9676-8059f6ac1dc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3361298743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3361298743 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2050478732 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 7691956854 ps |
| CPU time | 46.13 seconds |
| Started | May 16 01:59:49 PM PDT 24 |
| Finished | May 16 02:00:37 PM PDT 24 |
| Peak memory | 211676 kb |
| Host | smart-cd3dc483-9219-4359-8313-adbc33ab2c74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2050478732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2050478732 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2431650675 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 16251134732 ps |
| CPU time | 116.15 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:01:59 PM PDT 24 |
| Peak memory | 204792 kb |
| Host | smart-0c5012cc-c60b-4df9-8d17-fb97b8bdbb06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2431650675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2431650675 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.883127950 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 159065599 ps |
| CPU time | 11.91 seconds |
| Started | May 16 02:00:00 PM PDT 24 |
| Finished | May 16 02:00:12 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-a43a5d52-35be-456e-bd57-fd5f4d5bd769 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883127950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.883127950 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.2470349999 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 304880949 ps |
| CPU time | 25.56 seconds |
| Started | May 16 02:00:03 PM PDT 24 |
| Finished | May 16 02:00:29 PM PDT 24 |
| Peak memory | 203740 kb |
| Host | smart-a2c8957b-4b2f-4702-b0d5-9ad4a6725cba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2470349999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2470349999 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.4185282260 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 854882106 ps |
| CPU time | 38.19 seconds |
| Started | May 16 01:59:51 PM PDT 24 |
| Finished | May 16 02:00:31 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-93c1acc7-84c7-4388-8589-4f5372d2d88f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4185282260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.4185282260 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1153279706 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 191019647835 ps |
| CPU time | 288.05 seconds |
| Started | May 16 01:59:47 PM PDT 24 |
| Finished | May 16 02:04:38 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-0a41bd31-139e-416b-bac7-f79285c2f90e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153279706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1153279706 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3555964586 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 9307508437 ps |
| CPU time | 53.38 seconds |
| Started | May 16 01:59:52 PM PDT 24 |
| Finished | May 16 02:00:48 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-a79b29ab-a6d3-4a44-ac2c-0c21f3043204 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3555964586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3555964586 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2374507007 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 153958737 ps |
| CPU time | 17.46 seconds |
| Started | May 16 01:59:45 PM PDT 24 |
| Finished | May 16 02:00:05 PM PDT 24 |
| Peak memory | 204488 kb |
| Host | smart-e06d5d05-d112-428b-ab83-a195385e13c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374507007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2374507007 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.447460652 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 279987150 ps |
| CPU time | 18.76 seconds |
| Started | May 16 02:00:00 PM PDT 24 |
| Finished | May 16 02:00:19 PM PDT 24 |
| Peak memory | 211624 kb |
| Host | smart-460b1a78-bfbf-4cf8-93a5-fae5df89c4a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=447460652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.447460652 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2063305376 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 163715016 ps |
| CPU time | 4.26 seconds |
| Started | May 16 01:59:47 PM PDT 24 |
| Finished | May 16 01:59:55 PM PDT 24 |
| Peak memory | 203336 kb |
| Host | smart-fafd2c26-29a4-4be4-b4ab-ef346327e672 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2063305376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2063305376 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1691904023 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6914206368 ps |
| CPU time | 28.63 seconds |
| Started | May 16 01:59:51 PM PDT 24 |
| Finished | May 16 02:00:21 PM PDT 24 |
| Peak memory | 203492 kb |
| Host | smart-cce16934-fc1e-4c16-b5b7-002e85fd8e15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691904023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1691904023 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3868242891 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2654660752 ps |
| CPU time | 23.12 seconds |
| Started | May 16 01:59:46 PM PDT 24 |
| Finished | May 16 02:00:12 PM PDT 24 |
| Peak memory | 203472 kb |
| Host | smart-bcacd53c-cada-4e53-9a0b-2cc9f85abc5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3868242891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3868242891 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1702390045 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 33568984 ps |
| CPU time | 2.24 seconds |
| Started | May 16 01:59:50 PM PDT 24 |
| Finished | May 16 01:59:54 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-a3ba5b94-26fa-4ec8-bbe9-5a1707ffda2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702390045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1702390045 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1674618762 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2233221428 ps |
| CPU time | 49.42 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:00:51 PM PDT 24 |
| Peak memory | 205772 kb |
| Host | smart-ade4e333-d9ef-4132-a771-ec0c1ebe4227 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1674618762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1674618762 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3430755938 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 54064163 ps |
| CPU time | 7.83 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:00:10 PM PDT 24 |
| Peak memory | 204124 kb |
| Host | smart-d3943dbb-bd9a-44fe-b029-ca9a95a921c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3430755938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3430755938 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2828168438 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3650728277 ps |
| CPU time | 380.89 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:06:24 PM PDT 24 |
| Peak memory | 209716 kb |
| Host | smart-3d8dc63c-f987-4c24-bf4d-d86664e6e7d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828168438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.2828168438 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2200750052 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 72279786 ps |
| CPU time | 2.54 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:00:05 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-d507439c-daae-4052-a76d-0b05bda0a593 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200750052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.2200750052 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.690154905 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 70118828 ps |
| CPU time | 2.37 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:00:05 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-0f1c54c8-4bc0-4258-9a13-a64ba3767b02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=690154905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.690154905 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1334836668 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 234301533 ps |
| CPU time | 7.08 seconds |
| Started | May 16 02:00:15 PM PDT 24 |
| Finished | May 16 02:00:24 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-73c67120-bc6a-428d-aff3-c427c73e6238 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1334836668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1334836668 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1817376664 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 105334388377 ps |
| CPU time | 518.46 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:08:57 PM PDT 24 |
| Peak memory | 207352 kb |
| Host | smart-7f41ae1b-1c0f-4d60-a8b3-37c409e4ddfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1817376664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1817376664 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2203308772 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 108135951 ps |
| CPU time | 14.18 seconds |
| Started | May 16 02:00:16 PM PDT 24 |
| Finished | May 16 02:00:32 PM PDT 24 |
| Peak memory | 203876 kb |
| Host | smart-ce1905ef-3162-4fb9-8d93-49b65541e8ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2203308772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2203308772 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3616946870 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2622696190 ps |
| CPU time | 26.31 seconds |
| Started | May 16 02:00:16 PM PDT 24 |
| Finished | May 16 02:00:43 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-1f068715-d15c-450f-b19e-e5a0d2d7486c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3616946870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3616946870 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.36541751 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 199779786 ps |
| CPU time | 15.32 seconds |
| Started | May 16 02:00:16 PM PDT 24 |
| Finished | May 16 02:00:33 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-179c4696-a30f-43ad-ba99-dc7d32b28a48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=36541751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.36541751 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3497967259 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 35163433497 ps |
| CPU time | 125.24 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:02:25 PM PDT 24 |
| Peak memory | 205200 kb |
| Host | smart-daa62051-f7d7-4eaf-975a-8b3c023b2836 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497967259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3497967259 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.135416344 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6161882274 ps |
| CPU time | 30.6 seconds |
| Started | May 16 02:00:16 PM PDT 24 |
| Finished | May 16 02:00:49 PM PDT 24 |
| Peak memory | 211624 kb |
| Host | smart-e38b5dd7-8a9f-4e1d-800d-e1d7b0c1547d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=135416344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.135416344 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3755037164 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 282160117 ps |
| CPU time | 24.06 seconds |
| Started | May 16 02:00:15 PM PDT 24 |
| Finished | May 16 02:00:40 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-4d7d1463-2def-4cfc-9132-b6c514e8773e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755037164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3755037164 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.1644332633 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2295914917 ps |
| CPU time | 28.32 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:00:48 PM PDT 24 |
| Peak memory | 204092 kb |
| Host | smart-57a67fe0-b06a-4495-9264-bb6f353a7fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1644332633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1644332633 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.944597554 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 101056556 ps |
| CPU time | 2.3 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:00:04 PM PDT 24 |
| Peak memory | 203400 kb |
| Host | smart-2f8d80ae-3fa3-4fd7-a0c4-cc7626e4bf4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=944597554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.944597554 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2180553675 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 7795902179 ps |
| CPU time | 37.26 seconds |
| Started | May 16 02:00:03 PM PDT 24 |
| Finished | May 16 02:00:41 PM PDT 24 |
| Peak memory | 203492 kb |
| Host | smart-b09189dd-8d1c-4b9d-a505-496d2ce5cfdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180553675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2180553675 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.447663945 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 16381545017 ps |
| CPU time | 44.34 seconds |
| Started | May 16 02:00:02 PM PDT 24 |
| Finished | May 16 02:00:48 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-5226390c-4719-47d3-9e92-4e1097a4445c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=447663945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.447663945 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.335442317 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 152279519 ps |
| CPU time | 2.73 seconds |
| Started | May 16 02:00:01 PM PDT 24 |
| Finished | May 16 02:00:06 PM PDT 24 |
| Peak memory | 203332 kb |
| Host | smart-0814e6ea-76cf-4c73-a64c-46af964937c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335442317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.335442317 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.4160332536 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3944428808 ps |
| CPU time | 130.21 seconds |
| Started | May 16 02:00:15 PM PDT 24 |
| Finished | May 16 02:02:26 PM PDT 24 |
| Peak memory | 211684 kb |
| Host | smart-71477fdf-d5d3-4af6-955f-b23ac1f1689b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4160332536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4160332536 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3047585071 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5647864943 ps |
| CPU time | 144.71 seconds |
| Started | May 16 02:00:15 PM PDT 24 |
| Finished | May 16 02:02:40 PM PDT 24 |
| Peak memory | 207916 kb |
| Host | smart-e8982cf2-8984-4667-acc2-ff112d0c793e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3047585071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3047585071 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3261668826 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 100030010 ps |
| CPU time | 39.12 seconds |
| Started | May 16 02:00:15 PM PDT 24 |
| Finished | May 16 02:00:55 PM PDT 24 |
| Peak memory | 206840 kb |
| Host | smart-50e69ca9-8568-4ed1-a112-c2e7a76a6a65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261668826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.3261668826 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1014161094 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 222439874 ps |
| CPU time | 51.86 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:01:11 PM PDT 24 |
| Peak memory | 207600 kb |
| Host | smart-e3adbeda-c524-4689-901d-cd024932155b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1014161094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.1014161094 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.4232898134 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 516324775 ps |
| CPU time | 23.67 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:00:43 PM PDT 24 |
| Peak memory | 211604 kb |
| Host | smart-a7b38420-7943-4bc3-b963-6410e8c7c876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4232898134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4232898134 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2292698542 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2060905479 ps |
| CPU time | 40.81 seconds |
| Started | May 16 02:00:16 PM PDT 24 |
| Finished | May 16 02:00:59 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-f4091378-6007-4aeb-9002-c32572fc5986 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2292698542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2292698542 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2757307788 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 107334355309 ps |
| CPU time | 604.8 seconds |
| Started | May 16 02:00:19 PM PDT 24 |
| Finished | May 16 02:10:25 PM PDT 24 |
| Peak memory | 207440 kb |
| Host | smart-2d7a466e-782c-4350-b3e6-225c227240ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2757307788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2757307788 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.928736887 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 464013045 ps |
| CPU time | 17.02 seconds |
| Started | May 16 02:00:29 PM PDT 24 |
| Finished | May 16 02:00:47 PM PDT 24 |
| Peak memory | 203360 kb |
| Host | smart-ebb2bce4-3dba-46fe-bac4-41c467ab1a18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=928736887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.928736887 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.1563863556 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 365964053 ps |
| CPU time | 26.92 seconds |
| Started | May 16 02:00:15 PM PDT 24 |
| Finished | May 16 02:00:43 PM PDT 24 |
| Peak memory | 203680 kb |
| Host | smart-733f0e37-174e-4753-9ff7-c7e8a819dfb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563863556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1563863556 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.2993863720 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 135272429 ps |
| CPU time | 7.74 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:00:26 PM PDT 24 |
| Peak memory | 204616 kb |
| Host | smart-bb24bbee-e475-46ae-8337-24a02cc96512 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2993863720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2993863720 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1889198708 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 44724929127 ps |
| CPU time | 147.87 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:02:47 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-d1a1814e-7c9e-42cf-a19d-04338f5f7083 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889198708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1889198708 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3858625508 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 28447939510 ps |
| CPU time | 174.6 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:03:13 PM PDT 24 |
| Peak memory | 205108 kb |
| Host | smart-37416e39-1d80-45c0-abaa-dcb3ffa5658d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3858625508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3858625508 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.695292730 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 218451943 ps |
| CPU time | 29 seconds |
| Started | May 16 02:00:16 PM PDT 24 |
| Finished | May 16 02:00:47 PM PDT 24 |
| Peak memory | 211612 kb |
| Host | smart-05ce4088-5eeb-4f74-90f2-05a77b59131b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695292730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.695292730 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.2599083315 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1360754251 ps |
| CPU time | 17.39 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:00:37 PM PDT 24 |
| Peak memory | 203392 kb |
| Host | smart-8b4570d8-eda4-4781-8dd7-76a75e086f57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2599083315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2599083315 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.2455956450 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 812782276 ps |
| CPU time | 4.01 seconds |
| Started | May 16 02:00:16 PM PDT 24 |
| Finished | May 16 02:00:22 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-7a39b3ca-4f0e-48f1-a90c-0779c8ddba0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455956450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2455956450 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3562831922 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 6061490902 ps |
| CPU time | 29.81 seconds |
| Started | May 16 02:00:19 PM PDT 24 |
| Finished | May 16 02:00:50 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-12b6039f-712a-4234-b893-3372009c246d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562831922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3562831922 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2091432069 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 8593705123 ps |
| CPU time | 36.75 seconds |
| Started | May 16 02:00:19 PM PDT 24 |
| Finished | May 16 02:00:57 PM PDT 24 |
| Peak memory | 203464 kb |
| Host | smart-42f672c7-09e4-4046-949b-a314a34383e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2091432069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2091432069 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.815664469 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 33120595 ps |
| CPU time | 2.48 seconds |
| Started | May 16 02:00:17 PM PDT 24 |
| Finished | May 16 02:00:21 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-e511568d-2dbd-47e0-bcff-b51c30cbbab3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815664469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.815664469 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1050486519 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 329934332 ps |
| CPU time | 41.09 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:01:13 PM PDT 24 |
| Peak memory | 205340 kb |
| Host | smart-ebe762e7-470a-47c0-ac9f-be778b29c37c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1050486519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1050486519 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2329807688 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 15870460404 ps |
| CPU time | 234.04 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:04:27 PM PDT 24 |
| Peak memory | 209744 kb |
| Host | smart-6e7aaa5a-8f81-4d9b-9678-c3e2ce1a8b77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2329807688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2329807688 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3576326306 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 51805946 ps |
| CPU time | 17.78 seconds |
| Started | May 16 02:00:29 PM PDT 24 |
| Finished | May 16 02:00:49 PM PDT 24 |
| Peak memory | 206612 kb |
| Host | smart-0fe26e5c-65aa-45dd-b4cb-b20e90edfe73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3576326306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3576326306 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2668481233 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 2233514157 ps |
| CPU time | 203.61 seconds |
| Started | May 16 02:00:28 PM PDT 24 |
| Finished | May 16 02:03:53 PM PDT 24 |
| Peak memory | 210864 kb |
| Host | smart-cb061f64-de10-44a2-ac6d-09851c7e6cff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2668481233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2668481233 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.4291684831 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 146512224 ps |
| CPU time | 10.91 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:00:43 PM PDT 24 |
| Peak memory | 204920 kb |
| Host | smart-86c11d5c-0a51-4bfd-96dc-b90ec6faad8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4291684831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.4291684831 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2017944744 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 818287482 ps |
| CPU time | 21.48 seconds |
| Started | May 16 02:00:33 PM PDT 24 |
| Finished | May 16 02:00:56 PM PDT 24 |
| Peak memory | 205552 kb |
| Host | smart-136f9be5-f2db-4a01-9e00-9cc30e0bf56c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2017944744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2017944744 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2067108743 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 114039467795 ps |
| CPU time | 349.58 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:06:22 PM PDT 24 |
| Peak memory | 206120 kb |
| Host | smart-56b73115-74c4-4c6b-9974-04b11b9331f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2067108743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2067108743 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2594219905 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 881370901 ps |
| CPU time | 15.68 seconds |
| Started | May 16 02:00:28 PM PDT 24 |
| Finished | May 16 02:00:45 PM PDT 24 |
| Peak memory | 203684 kb |
| Host | smart-215e6931-5deb-48cc-a657-456ccf71a721 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2594219905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2594219905 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.442751099 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5851255082 ps |
| CPU time | 45.29 seconds |
| Started | May 16 02:00:29 PM PDT 24 |
| Finished | May 16 02:01:16 PM PDT 24 |
| Peak memory | 203972 kb |
| Host | smart-e23b73dc-4556-4154-a08c-29a0e5d94c62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=442751099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.442751099 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.1488864250 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 188656657 ps |
| CPU time | 8.31 seconds |
| Started | May 16 02:00:36 PM PDT 24 |
| Finished | May 16 02:00:45 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-7c55ffa1-7093-4007-836a-fc081f993fb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1488864250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1488864250 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.4078426301 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 46204689219 ps |
| CPU time | 102.7 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:02:14 PM PDT 24 |
| Peak memory | 211692 kb |
| Host | smart-d96414d0-7c90-4a69-8bc6-4fa3f9331008 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078426301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4078426301 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3820176405 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 55148426022 ps |
| CPU time | 205.36 seconds |
| Started | May 16 02:00:28 PM PDT 24 |
| Finished | May 16 02:03:55 PM PDT 24 |
| Peak memory | 205536 kb |
| Host | smart-a67cd341-ec51-4e6a-9b32-3994b48d1a02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3820176405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3820176405 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.962845158 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 313847447 ps |
| CPU time | 20.72 seconds |
| Started | May 16 02:00:31 PM PDT 24 |
| Finished | May 16 02:00:54 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-1a8328e6-7443-4944-885b-83318f2b76c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962845158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.962845158 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1624445548 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1499741074 ps |
| CPU time | 32.88 seconds |
| Started | May 16 02:00:31 PM PDT 24 |
| Finished | May 16 02:01:06 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-f4e6c086-d33a-4636-a727-6a477152971c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1624445548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1624445548 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.3040483588 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 34002524 ps |
| CPU time | 2.82 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:00:35 PM PDT 24 |
| Peak memory | 203396 kb |
| Host | smart-6d296bdd-4d2f-4113-b3ec-d664b0d1ac5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3040483588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3040483588 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.511642063 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 7323332917 ps |
| CPU time | 33.55 seconds |
| Started | May 16 02:00:28 PM PDT 24 |
| Finished | May 16 02:01:03 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-595bdb9b-437b-469c-ad00-0a1e33b1f46e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=511642063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.511642063 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1152634435 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 5787291609 ps |
| CPU time | 30.14 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:01:03 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-beb9f400-edfd-49d9-b946-3c430eea865f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1152634435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1152634435 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2662485902 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 48838440 ps |
| CPU time | 2.44 seconds |
| Started | May 16 02:00:31 PM PDT 24 |
| Finished | May 16 02:00:36 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-e9e911ca-d973-4a66-abc7-bd036bc203ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662485902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2662485902 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.172013187 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 869552193 ps |
| CPU time | 60.75 seconds |
| Started | May 16 02:00:31 PM PDT 24 |
| Finished | May 16 02:01:34 PM PDT 24 |
| Peak memory | 205388 kb |
| Host | smart-88874279-bf75-40d8-a383-6b74c4a4b3ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=172013187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.172013187 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.553610656 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1532410827 ps |
| CPU time | 67.77 seconds |
| Started | May 16 02:00:28 PM PDT 24 |
| Finished | May 16 02:01:37 PM PDT 24 |
| Peak memory | 205108 kb |
| Host | smart-e10777b9-3578-4b3d-8621-340eea22e9c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=553610656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.553610656 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.486361025 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 86565478 ps |
| CPU time | 22.31 seconds |
| Started | May 16 02:00:31 PM PDT 24 |
| Finished | May 16 02:00:56 PM PDT 24 |
| Peak memory | 206436 kb |
| Host | smart-c9804295-2da7-4cf4-8305-637f3aa38c9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=486361025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand _reset.486361025 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2891905532 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 493469344 ps |
| CPU time | 120.26 seconds |
| Started | May 16 02:00:32 PM PDT 24 |
| Finished | May 16 02:02:34 PM PDT 24 |
| Peak memory | 209764 kb |
| Host | smart-c2cf7847-79a7-46a0-84dd-fca4baa5db58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2891905532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2891905532 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1782546567 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 104063981 ps |
| CPU time | 13.74 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:00:47 PM PDT 24 |
| Peak memory | 204948 kb |
| Host | smart-3c6ef1f1-d78b-46b4-adfb-3993ad2b30f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1782546567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1782546567 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2540019735 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 973799515 ps |
| CPU time | 19.27 seconds |
| Started | May 16 02:00:28 PM PDT 24 |
| Finished | May 16 02:00:48 PM PDT 24 |
| Peak memory | 204332 kb |
| Host | smart-3a85d5f9-5a53-40e0-8fb0-ecf18b2fe281 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2540019735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2540019735 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2276367371 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 10110320949 ps |
| CPU time | 85.61 seconds |
| Started | May 16 02:00:42 PM PDT 24 |
| Finished | May 16 02:02:10 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-b88836ec-abfd-4dc9-ba24-770968d98001 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2276367371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2276367371 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.899632834 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 699030631 ps |
| CPU time | 21.04 seconds |
| Started | May 16 02:00:42 PM PDT 24 |
| Finished | May 16 02:01:05 PM PDT 24 |
| Peak memory | 203684 kb |
| Host | smart-69b937cd-8c4c-464d-8beb-66089f0f5cc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=899632834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.899632834 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.3881662691 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 260870172 ps |
| CPU time | 15.47 seconds |
| Started | May 16 02:00:41 PM PDT 24 |
| Finished | May 16 02:00:58 PM PDT 24 |
| Peak memory | 203384 kb |
| Host | smart-42decdaf-e417-4822-9a53-6f9a2c85096a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3881662691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3881662691 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.3680111701 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1080016820 ps |
| CPU time | 26.13 seconds |
| Started | May 16 02:00:32 PM PDT 24 |
| Finished | May 16 02:01:00 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-b87073df-67c4-4c77-834e-cd0f57fb8f8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3680111701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3680111701 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.4176272208 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 45645897779 ps |
| CPU time | 228.33 seconds |
| Started | May 16 02:00:29 PM PDT 24 |
| Finished | May 16 02:04:18 PM PDT 24 |
| Peak memory | 205444 kb |
| Host | smart-ade5e7a6-64d8-4241-8e48-c18de3e4b5c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176272208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.4176272208 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1859236146 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 25851232565 ps |
| CPU time | 242.7 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:04:34 PM PDT 24 |
| Peak memory | 204808 kb |
| Host | smart-4bf33238-b31f-4c32-b9b0-64c732fb287d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1859236146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1859236146 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1154458742 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 435234525 ps |
| CPU time | 31.78 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:01:05 PM PDT 24 |
| Peak memory | 204540 kb |
| Host | smart-565da246-e7d1-4816-b480-2ad1cc09d44d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154458742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1154458742 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1185861835 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1557993892 ps |
| CPU time | 32.11 seconds |
| Started | May 16 02:00:44 PM PDT 24 |
| Finished | May 16 02:01:17 PM PDT 24 |
| Peak memory | 211612 kb |
| Host | smart-6220e680-9951-4bf4-9fc3-a52ed3673b4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1185861835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1185861835 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.2725685557 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 53896943 ps |
| CPU time | 2.43 seconds |
| Started | May 16 02:00:30 PM PDT 24 |
| Finished | May 16 02:00:34 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-6536f931-1e3a-4749-a349-db6b5f72adda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2725685557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2725685557 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.741011529 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 7470580223 ps |
| CPU time | 28.76 seconds |
| Started | May 16 02:00:29 PM PDT 24 |
| Finished | May 16 02:01:00 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-689cfd1d-8b3a-4bff-bb91-23d4d1fc9738 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=741011529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.741011529 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2989674444 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3685302974 ps |
| CPU time | 25.31 seconds |
| Started | May 16 02:00:33 PM PDT 24 |
| Finished | May 16 02:01:00 PM PDT 24 |
| Peak memory | 203396 kb |
| Host | smart-a3ba297a-09f0-4129-9986-e461d96cd830 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2989674444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2989674444 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.337543849 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 39773469 ps |
| CPU time | 2.51 seconds |
| Started | May 16 02:00:31 PM PDT 24 |
| Finished | May 16 02:00:36 PM PDT 24 |
| Peak memory | 203408 kb |
| Host | smart-45691a06-cc31-4efd-8177-82270170f272 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337543849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.337543849 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2810713994 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2325770188 ps |
| CPU time | 62.22 seconds |
| Started | May 16 02:00:43 PM PDT 24 |
| Finished | May 16 02:01:47 PM PDT 24 |
| Peak memory | 207596 kb |
| Host | smart-3276e6f1-e6a1-4524-b745-d01ce172de04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2810713994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2810713994 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1669101405 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1464852109 ps |
| CPU time | 32.64 seconds |
| Started | May 16 02:00:44 PM PDT 24 |
| Finished | May 16 02:01:18 PM PDT 24 |
| Peak memory | 206156 kb |
| Host | smart-77b97305-60de-4944-abee-f76c929e86c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1669101405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1669101405 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3085527683 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1466031689 ps |
| CPU time | 278.08 seconds |
| Started | May 16 02:00:42 PM PDT 24 |
| Finished | May 16 02:05:22 PM PDT 24 |
| Peak memory | 210936 kb |
| Host | smart-f5b04d1d-5e5a-4829-ab74-c50beb83ecee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085527683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.3085527683 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.428201369 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 16647804640 ps |
| CPU time | 458.41 seconds |
| Started | May 16 02:00:45 PM PDT 24 |
| Finished | May 16 02:08:25 PM PDT 24 |
| Peak memory | 219900 kb |
| Host | smart-7fb00c01-44ec-4918-befa-492e9d83ccee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=428201369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.428201369 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1709181972 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 287079280 ps |
| CPU time | 12.46 seconds |
| Started | May 16 02:00:41 PM PDT 24 |
| Finished | May 16 02:00:55 PM PDT 24 |
| Peak memory | 211584 kb |
| Host | smart-921018ad-da08-487a-9b81-f259be778d94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1709181972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1709181972 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2631986625 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1134418270 ps |
| CPU time | 52.88 seconds |
| Started | May 16 02:00:44 PM PDT 24 |
| Finished | May 16 02:01:38 PM PDT 24 |
| Peak memory | 205076 kb |
| Host | smart-e61f1b3e-c064-406e-890e-3178928dfe0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631986625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2631986625 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3395692092 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 124813315535 ps |
| CPU time | 466.73 seconds |
| Started | May 16 02:00:43 PM PDT 24 |
| Finished | May 16 02:08:31 PM PDT 24 |
| Peak memory | 211676 kb |
| Host | smart-85f5774a-b969-4d7c-b017-2aeaf267252b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3395692092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3395692092 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1204963069 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 612959515 ps |
| CPU time | 12.3 seconds |
| Started | May 16 02:00:57 PM PDT 24 |
| Finished | May 16 02:01:11 PM PDT 24 |
| Peak memory | 203860 kb |
| Host | smart-d5212c03-f089-4521-8c88-7f6e68cf2f4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1204963069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1204963069 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.1271211316 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 72692680 ps |
| CPU time | 6.18 seconds |
| Started | May 16 02:00:46 PM PDT 24 |
| Finished | May 16 02:00:54 PM PDT 24 |
| Peak memory | 203436 kb |
| Host | smart-e935a36a-a89f-41cd-a48b-a3e52193f38c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1271211316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1271211316 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.1126864880 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 30197191 ps |
| CPU time | 3.44 seconds |
| Started | May 16 02:00:49 PM PDT 24 |
| Finished | May 16 02:00:54 PM PDT 24 |
| Peak memory | 203988 kb |
| Host | smart-cee80c87-8314-4dc0-9d23-0383ba5b27dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1126864880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1126864880 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1614557659 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 39300497146 ps |
| CPU time | 227.89 seconds |
| Started | May 16 02:00:44 PM PDT 24 |
| Finished | May 16 02:04:33 PM PDT 24 |
| Peak memory | 204724 kb |
| Host | smart-db67e627-1418-4452-be23-26659f6c9a6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614557659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1614557659 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3218330914 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 11004624810 ps |
| CPU time | 68.12 seconds |
| Started | May 16 02:00:44 PM PDT 24 |
| Finished | May 16 02:01:54 PM PDT 24 |
| Peak memory | 211676 kb |
| Host | smart-38cab3d3-2472-4340-a0e8-44dc1fb3be75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3218330914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3218330914 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2614489441 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 465541406 ps |
| CPU time | 22.36 seconds |
| Started | May 16 02:00:43 PM PDT 24 |
| Finished | May 16 02:01:07 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-e8eae7f4-8cb8-44ed-b741-df508939b5f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614489441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2614489441 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2976312468 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 334336875 ps |
| CPU time | 16.75 seconds |
| Started | May 16 02:00:44 PM PDT 24 |
| Finished | May 16 02:01:02 PM PDT 24 |
| Peak memory | 203400 kb |
| Host | smart-5a0a1fc4-32ed-4262-ac79-c22ac8374fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2976312468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2976312468 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.3593390443 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 616231795 ps |
| CPU time | 4.44 seconds |
| Started | May 16 02:00:42 PM PDT 24 |
| Finished | May 16 02:00:48 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-1d2c364d-ddd3-4f75-a0ef-01bd07d0162c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3593390443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3593390443 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3280163103 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 33552817557 ps |
| CPU time | 46.35 seconds |
| Started | May 16 02:00:43 PM PDT 24 |
| Finished | May 16 02:01:31 PM PDT 24 |
| Peak memory | 203492 kb |
| Host | smart-d31b94e5-83be-4b12-99d9-77e5cadbd4ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280163103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3280163103 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.143644072 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 9980855153 ps |
| CPU time | 31.38 seconds |
| Started | May 16 02:00:43 PM PDT 24 |
| Finished | May 16 02:01:16 PM PDT 24 |
| Peak memory | 203504 kb |
| Host | smart-3b2bd297-ff80-4655-abcc-a09fba063be6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=143644072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.143644072 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1918394727 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 35574993 ps |
| CPU time | 2.27 seconds |
| Started | May 16 02:00:42 PM PDT 24 |
| Finished | May 16 02:00:46 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-db48a05c-ae3e-4882-9e9a-9d71cd1aa7c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918394727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1918394727 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.282677366 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4480159175 ps |
| CPU time | 216.6 seconds |
| Started | May 16 02:00:57 PM PDT 24 |
| Finished | May 16 02:04:35 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-9abec2af-9f74-4d1a-86fa-df36fa1f1b78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=282677366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.282677366 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.540771790 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 6207259723 ps |
| CPU time | 139.23 seconds |
| Started | May 16 02:00:56 PM PDT 24 |
| Finished | May 16 02:03:16 PM PDT 24 |
| Peak memory | 208744 kb |
| Host | smart-3be6ae41-518a-49b8-bf40-e253cdc7ae13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=540771790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.540771790 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2991074719 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 4471927388 ps |
| CPU time | 502.03 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:09:18 PM PDT 24 |
| Peak memory | 219896 kb |
| Host | smart-61c553d0-a8b6-4998-b769-0a1a2765462e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991074719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2991074719 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2582502689 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4443630542 ps |
| CPU time | 289.69 seconds |
| Started | May 16 02:00:57 PM PDT 24 |
| Finished | May 16 02:05:48 PM PDT 24 |
| Peak memory | 219840 kb |
| Host | smart-797adf5b-9240-4e42-9ef9-9795d76bd594 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2582502689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2582502689 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3745116326 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 77055285 ps |
| CPU time | 2.83 seconds |
| Started | May 16 02:00:43 PM PDT 24 |
| Finished | May 16 02:00:48 PM PDT 24 |
| Peak memory | 204044 kb |
| Host | smart-fd748e68-25b3-48f0-a540-2b4340703525 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745116326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3745116326 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2156575390 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 180474360 ps |
| CPU time | 10.93 seconds |
| Started | May 16 02:00:57 PM PDT 24 |
| Finished | May 16 02:01:09 PM PDT 24 |
| Peak memory | 204084 kb |
| Host | smart-3e0f66bc-e4e8-4961-bec9-797ea7ff648b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2156575390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2156575390 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2871523862 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1192921281 ps |
| CPU time | 25.82 seconds |
| Started | May 16 02:00:57 PM PDT 24 |
| Finished | May 16 02:01:24 PM PDT 24 |
| Peak memory | 203572 kb |
| Host | smart-c6907496-1361-4ea8-a00e-550726619ad0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2871523862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2871523862 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.4199094124 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 635919620 ps |
| CPU time | 15.6 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:01:12 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-0ef803ce-c922-4de0-a1ce-810adcb5af55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4199094124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4199094124 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.630717566 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 987846942 ps |
| CPU time | 23.7 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:01:20 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-deed00ec-c5a1-417d-84e9-49a7eaa86bd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=630717566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.630717566 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.619303648 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 21470690427 ps |
| CPU time | 129.08 seconds |
| Started | May 16 02:00:59 PM PDT 24 |
| Finished | May 16 02:03:09 PM PDT 24 |
| Peak memory | 211700 kb |
| Host | smart-4156429d-b9e0-4219-bffa-9a1781a45450 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=619303648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.619303648 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.446220333 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 6247260922 ps |
| CPU time | 25.48 seconds |
| Started | May 16 02:00:56 PM PDT 24 |
| Finished | May 16 02:01:23 PM PDT 24 |
| Peak memory | 204008 kb |
| Host | smart-6a6270d1-1a32-449b-839c-d4fa404b1a70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=446220333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.446220333 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.484138972 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 205722714 ps |
| CPU time | 17.75 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:01:14 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-3e906b85-c379-4c42-b771-4341fe24dfca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484138972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.484138972 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1456415223 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1746345361 ps |
| CPU time | 33.36 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:01:30 PM PDT 24 |
| Peak memory | 203304 kb |
| Host | smart-8bc2589b-aa8a-499a-9eee-ae044d2ca26b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456415223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1456415223 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.4243178281 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 339514440 ps |
| CPU time | 3.05 seconds |
| Started | May 16 02:00:58 PM PDT 24 |
| Finished | May 16 02:01:02 PM PDT 24 |
| Peak memory | 203356 kb |
| Host | smart-53b0d724-0eda-4ff2-862b-a01aed7f83db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4243178281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.4243178281 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3373708599 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 10224563733 ps |
| CPU time | 31.83 seconds |
| Started | May 16 02:00:59 PM PDT 24 |
| Finished | May 16 02:01:32 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-171b45f4-8ccb-4bf5-9874-13d7d595bbde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373708599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3373708599 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.638291549 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6458731243 ps |
| CPU time | 37.03 seconds |
| Started | May 16 02:00:54 PM PDT 24 |
| Finished | May 16 02:01:33 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-f4b01016-f043-4680-9349-5c89f224e180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=638291549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.638291549 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.200303577 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 61670823 ps |
| CPU time | 2.41 seconds |
| Started | May 16 02:00:56 PM PDT 24 |
| Finished | May 16 02:01:00 PM PDT 24 |
| Peak memory | 203372 kb |
| Host | smart-c57e9073-5825-4a9d-9c88-0d0d3098139c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200303577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.200303577 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.3196500319 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3343048993 ps |
| CPU time | 90.53 seconds |
| Started | May 16 02:00:56 PM PDT 24 |
| Finished | May 16 02:02:28 PM PDT 24 |
| Peak memory | 205612 kb |
| Host | smart-ad6e4cad-08f6-4445-be3d-7138e1d3645f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3196500319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3196500319 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3430848959 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 601107300 ps |
| CPU time | 11.73 seconds |
| Started | May 16 02:00:58 PM PDT 24 |
| Finished | May 16 02:01:11 PM PDT 24 |
| Peak memory | 203384 kb |
| Host | smart-c9280bab-c210-4cf0-a650-e07bb690e0af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3430848959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3430848959 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.63874789 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3623225552 ps |
| CPU time | 275.5 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:05:32 PM PDT 24 |
| Peak memory | 208272 kb |
| Host | smart-5900aacb-e091-403d-9b4f-cdaa02c5b470 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=63874789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_ reset.63874789 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4153195538 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 373829811 ps |
| CPU time | 171.09 seconds |
| Started | May 16 02:00:56 PM PDT 24 |
| Finished | May 16 02:03:48 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-e0b52ae1-30b0-45f0-a6f0-e6b2cbc3fa74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4153195538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.4153195538 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.4201843302 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 937307217 ps |
| CPU time | 37.18 seconds |
| Started | May 16 02:00:57 PM PDT 24 |
| Finished | May 16 02:01:36 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-ea929129-123a-4bd3-8d2f-960e08b7c7a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4201843302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4201843302 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1666065072 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1336056044 ps |
| CPU time | 60.21 seconds |
| Started | May 16 02:01:10 PM PDT 24 |
| Finished | May 16 02:02:11 PM PDT 24 |
| Peak memory | 206028 kb |
| Host | smart-9fadb26d-b1a3-46fa-bb11-6fe0acac34a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1666065072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1666065072 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2190352254 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 9292980619 ps |
| CPU time | 91.26 seconds |
| Started | May 16 02:01:06 PM PDT 24 |
| Finished | May 16 02:02:39 PM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-1f3e25fb-4e67-425a-a111-4a97eda5e227 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2190352254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2190352254 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1524376441 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 235375422 ps |
| CPU time | 6.26 seconds |
| Started | May 16 02:01:10 PM PDT 24 |
| Finished | May 16 02:01:18 PM PDT 24 |
| Peak memory | 203464 kb |
| Host | smart-d0452603-19fa-41dc-b05d-54eeca9e6115 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1524376441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1524376441 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.619082696 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 29677512 ps |
| CPU time | 4.38 seconds |
| Started | May 16 02:01:12 PM PDT 24 |
| Finished | May 16 02:01:17 PM PDT 24 |
| Peak memory | 203376 kb |
| Host | smart-9bda156c-8f38-41dd-b9aa-83a13f07154f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=619082696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.619082696 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.1980999820 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1473884489 ps |
| CPU time | 35.94 seconds |
| Started | May 16 02:01:11 PM PDT 24 |
| Finished | May 16 02:01:48 PM PDT 24 |
| Peak memory | 211540 kb |
| Host | smart-eb64b892-6afa-4d1c-a480-242860279dc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1980999820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1980999820 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.4173710536 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 19315924520 ps |
| CPU time | 93.64 seconds |
| Started | May 16 02:01:09 PM PDT 24 |
| Finished | May 16 02:02:45 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-467e2b00-32dc-4efe-b1aa-3de46a964ac8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173710536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4173710536 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1654366373 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 18540356364 ps |
| CPU time | 129.03 seconds |
| Started | May 16 02:01:03 PM PDT 24 |
| Finished | May 16 02:03:13 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-c4cde5c2-87fd-4c0c-b4fe-c19194049b55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1654366373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1654366373 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3667814641 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 148423301 ps |
| CPU time | 22.86 seconds |
| Started | May 16 02:01:05 PM PDT 24 |
| Finished | May 16 02:01:29 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-b26f3dba-17fd-4f7a-a05c-23e2638d4ade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667814641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3667814641 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1390124149 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1035291768 ps |
| CPU time | 16.68 seconds |
| Started | May 16 02:01:06 PM PDT 24 |
| Finished | May 16 02:01:24 PM PDT 24 |
| Peak memory | 203464 kb |
| Host | smart-f76c0bf1-216b-40bc-8c8b-132d0a321a95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1390124149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1390124149 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.2853756366 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 142008681 ps |
| CPU time | 3.89 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:01:00 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-7199589d-01d8-4e2d-b8cd-205855921f39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2853756366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2853756366 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3746517330 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 5202095885 ps |
| CPU time | 29.52 seconds |
| Started | May 16 02:00:59 PM PDT 24 |
| Finished | May 16 02:01:30 PM PDT 24 |
| Peak memory | 203500 kb |
| Host | smart-6e758651-6724-4b8c-944d-f96f377d352f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746517330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3746517330 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.481846452 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3253233200 ps |
| CPU time | 27.67 seconds |
| Started | May 16 02:01:05 PM PDT 24 |
| Finished | May 16 02:01:34 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-0f0bf91f-4f09-446b-ad5c-ff6da1e1b9c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=481846452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.481846452 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1682843334 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 62300520 ps |
| CPU time | 2.08 seconds |
| Started | May 16 02:00:55 PM PDT 24 |
| Finished | May 16 02:00:58 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-03614e36-9b08-4b60-b150-4382b84664ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682843334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1682843334 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3034601987 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1617610693 ps |
| CPU time | 86.7 seconds |
| Started | May 16 02:01:09 PM PDT 24 |
| Finished | May 16 02:02:38 PM PDT 24 |
| Peak memory | 206996 kb |
| Host | smart-c9b46993-3d51-4a4e-b5e5-db33d7d0d700 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034601987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3034601987 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2670030382 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2098697465 ps |
| CPU time | 58.57 seconds |
| Started | May 16 02:01:12 PM PDT 24 |
| Finished | May 16 02:02:12 PM PDT 24 |
| Peak memory | 205044 kb |
| Host | smart-17698b19-0394-4036-944a-4c961c2e6b17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2670030382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2670030382 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3234815122 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 239427461 ps |
| CPU time | 71.25 seconds |
| Started | May 16 02:01:04 PM PDT 24 |
| Finished | May 16 02:02:17 PM PDT 24 |
| Peak memory | 207184 kb |
| Host | smart-76b276be-2a42-4548-ae99-36ebe4ac13bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3234815122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.3234815122 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1262144328 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 275419964 ps |
| CPU time | 60.03 seconds |
| Started | May 16 02:01:03 PM PDT 24 |
| Finished | May 16 02:02:04 PM PDT 24 |
| Peak memory | 208036 kb |
| Host | smart-55234a05-a40f-42db-9fcd-9335c81d71bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1262144328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.1262144328 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3176111109 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1167676675 ps |
| CPU time | 33.43 seconds |
| Started | May 16 02:01:11 PM PDT 24 |
| Finished | May 16 02:01:45 PM PDT 24 |
| Peak memory | 211536 kb |
| Host | smart-27b3f8d5-1b15-4070-8575-022fecdd7b8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3176111109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3176111109 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2027579052 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2821473996 ps |
| CPU time | 36.22 seconds |
| Started | May 16 01:52:29 PM PDT 24 |
| Finished | May 16 01:53:06 PM PDT 24 |
| Peak memory | 205432 kb |
| Host | smart-0dd423f0-51ec-4830-8a7d-a724d2af7480 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2027579052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2027579052 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1473751971 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 57194130659 ps |
| CPU time | 296.83 seconds |
| Started | May 16 01:52:26 PM PDT 24 |
| Finished | May 16 01:57:24 PM PDT 24 |
| Peak memory | 211744 kb |
| Host | smart-ada0bd90-621a-4c3f-9b7b-8344037c92c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1473751971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.1473751971 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4060441426 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 71247920 ps |
| CPU time | 2.15 seconds |
| Started | May 16 01:52:25 PM PDT 24 |
| Finished | May 16 01:52:29 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-5ada0dcd-5574-48fa-82c2-f0606a79c8fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4060441426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4060441426 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.3218448432 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 72191860 ps |
| CPU time | 1.79 seconds |
| Started | May 16 01:52:26 PM PDT 24 |
| Finished | May 16 01:52:29 PM PDT 24 |
| Peak memory | 203400 kb |
| Host | smart-d5bdc3ff-dba5-4b50-a09d-127b3b7365f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3218448432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3218448432 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.1754575633 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3762152597 ps |
| CPU time | 41.93 seconds |
| Started | May 16 01:52:20 PM PDT 24 |
| Finished | May 16 01:53:04 PM PDT 24 |
| Peak memory | 205064 kb |
| Host | smart-bb6eaf39-e54a-4c1b-9d9e-b73f0d7f3c9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1754575633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1754575633 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3141167763 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 19908640467 ps |
| CPU time | 130.74 seconds |
| Started | May 16 01:52:25 PM PDT 24 |
| Finished | May 16 01:54:37 PM PDT 24 |
| Peak memory | 204920 kb |
| Host | smart-a7dda00f-9b65-491a-92b3-a361102a7394 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141167763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3141167763 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1341751468 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 16655938716 ps |
| CPU time | 42.88 seconds |
| Started | May 16 01:52:27 PM PDT 24 |
| Finished | May 16 01:53:11 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-e32c4f81-de1c-46d8-98a7-9c6f4efd5b71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1341751468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1341751468 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1082868153 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 113253078 ps |
| CPU time | 6.65 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:25 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-cad09f20-ccb0-4100-8933-1b5d01775a93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082868153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1082868153 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.225047343 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 109125475 ps |
| CPU time | 7.37 seconds |
| Started | May 16 01:52:25 PM PDT 24 |
| Finished | May 16 01:52:34 PM PDT 24 |
| Peak memory | 204208 kb |
| Host | smart-d2bc7650-b384-4858-8322-e4a8c7ac8915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=225047343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.225047343 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.3655290372 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 246133771 ps |
| CPU time | 3.63 seconds |
| Started | May 16 01:52:16 PM PDT 24 |
| Finished | May 16 01:52:21 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-ed41172f-723c-4eb7-b9f3-b7b395473a11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3655290372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3655290372 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.602773413 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 16744496722 ps |
| CPU time | 31.51 seconds |
| Started | May 16 01:52:18 PM PDT 24 |
| Finished | May 16 01:52:52 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-42d4370b-9c5f-4740-b173-31683e6b235a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=602773413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.602773413 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2875725779 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4122782080 ps |
| CPU time | 27.82 seconds |
| Started | May 16 01:52:21 PM PDT 24 |
| Finished | May 16 01:52:50 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-d51499d8-24e0-4f7a-b7c8-a5ae73e7c26e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2875725779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2875725779 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.914484483 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 38445433 ps |
| CPU time | 2.13 seconds |
| Started | May 16 01:52:19 PM PDT 24 |
| Finished | May 16 01:52:23 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-725254b2-d41a-491d-a63f-7d1a5c014a72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914484483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.914484483 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2313015005 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3333900386 ps |
| CPU time | 146.6 seconds |
| Started | May 16 01:52:26 PM PDT 24 |
| Finished | May 16 01:54:54 PM PDT 24 |
| Peak memory | 207304 kb |
| Host | smart-3250a211-c4a4-4725-86d4-0ae26f79f832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2313015005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2313015005 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1807430376 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 11874275216 ps |
| CPU time | 249.68 seconds |
| Started | May 16 01:52:26 PM PDT 24 |
| Finished | May 16 01:56:37 PM PDT 24 |
| Peak memory | 207012 kb |
| Host | smart-848f1020-1e4a-4f8a-b195-54dae4987ee6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1807430376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1807430376 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.723199473 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1199541136 ps |
| CPU time | 196.32 seconds |
| Started | May 16 01:52:25 PM PDT 24 |
| Finished | May 16 01:55:43 PM PDT 24 |
| Peak memory | 208992 kb |
| Host | smart-8b4b5ff0-71ef-4e63-a722-7d200ea50da2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=723199473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_ reset.723199473 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2224929456 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1056999078 ps |
| CPU time | 254.32 seconds |
| Started | May 16 01:52:26 PM PDT 24 |
| Finished | May 16 01:56:42 PM PDT 24 |
| Peak memory | 219964 kb |
| Host | smart-904aefe9-82c8-41fe-80d7-537af0bc2376 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2224929456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.2224929456 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2528427865 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 167064641 ps |
| CPU time | 6.02 seconds |
| Started | May 16 01:52:28 PM PDT 24 |
| Finished | May 16 01:52:36 PM PDT 24 |
| Peak memory | 205048 kb |
| Host | smart-bbf7cbd0-3a2b-4aa6-8fcd-b6c24bd6a110 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2528427865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2528427865 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2149213705 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1493620474 ps |
| CPU time | 43.69 seconds |
| Started | May 16 01:52:35 PM PDT 24 |
| Finished | May 16 01:53:20 PM PDT 24 |
| Peak memory | 206052 kb |
| Host | smart-3a9a9278-dbf8-4f42-aa5e-e6e6bc363508 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149213705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2149213705 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3560518482 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 187072546777 ps |
| CPU time | 576.15 seconds |
| Started | May 16 01:52:38 PM PDT 24 |
| Finished | May 16 02:02:16 PM PDT 24 |
| Peak memory | 207392 kb |
| Host | smart-0f4c2b94-45a4-473e-a275-339e2ea99c45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3560518482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.3560518482 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.341925834 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 62776718 ps |
| CPU time | 4.47 seconds |
| Started | May 16 01:52:39 PM PDT 24 |
| Finished | May 16 01:52:45 PM PDT 24 |
| Peak memory | 203560 kb |
| Host | smart-6cc6b735-2607-4666-af3b-71d030c919d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=341925834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.341925834 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.1593190277 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 140192746 ps |
| CPU time | 9.87 seconds |
| Started | May 16 01:52:37 PM PDT 24 |
| Finished | May 16 01:52:49 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-aead88aa-3ccd-4095-bc1d-e707d38f5121 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1593190277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1593190277 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.551625569 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1892056485 ps |
| CPU time | 23.73 seconds |
| Started | May 16 01:52:27 PM PDT 24 |
| Finished | May 16 01:52:52 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-a0ecce37-18b4-4c5a-8fa1-dc84a832e74e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=551625569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.551625569 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.857096355 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 37610426323 ps |
| CPU time | 162.57 seconds |
| Started | May 16 01:52:28 PM PDT 24 |
| Finished | May 16 01:55:12 PM PDT 24 |
| Peak memory | 205084 kb |
| Host | smart-142cc8e7-92cd-4ab7-924f-dcec22a04f1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=857096355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.857096355 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.316348072 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 50430524125 ps |
| CPU time | 185.36 seconds |
| Started | May 16 01:52:39 PM PDT 24 |
| Finished | May 16 01:55:46 PM PDT 24 |
| Peak memory | 211652 kb |
| Host | smart-62c9921c-0edd-4132-ada0-636417e92949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=316348072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.316348072 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3218520958 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 46413338 ps |
| CPU time | 6.71 seconds |
| Started | May 16 01:52:28 PM PDT 24 |
| Finished | May 16 01:52:36 PM PDT 24 |
| Peak memory | 211624 kb |
| Host | smart-637af447-6fd0-4980-a251-2d13485474cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218520958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3218520958 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.1849164232 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1658324690 ps |
| CPU time | 21.59 seconds |
| Started | May 16 01:52:39 PM PDT 24 |
| Finished | May 16 01:53:02 PM PDT 24 |
| Peak memory | 211564 kb |
| Host | smart-5d063075-e8ff-4eb5-867d-fa243ef34e40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1849164232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1849164232 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.2052377969 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 150093639 ps |
| CPU time | 4.5 seconds |
| Started | May 16 01:52:28 PM PDT 24 |
| Finished | May 16 01:52:34 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-f0fd1099-7c33-4eaf-82b1-ba814c95bcc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2052377969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2052377969 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3035548420 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 6847793488 ps |
| CPU time | 39.63 seconds |
| Started | May 16 01:52:28 PM PDT 24 |
| Finished | May 16 01:53:09 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-d7651af3-23d7-4968-97ed-d1fb6f028c1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035548420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3035548420 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3068002873 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 5646387150 ps |
| CPU time | 24.48 seconds |
| Started | May 16 01:52:28 PM PDT 24 |
| Finished | May 16 01:52:53 PM PDT 24 |
| Peak memory | 203492 kb |
| Host | smart-7a6a7c91-23cf-418d-827f-d66d53d84d9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3068002873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3068002873 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2623717983 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 36333431 ps |
| CPU time | 2.46 seconds |
| Started | May 16 01:52:28 PM PDT 24 |
| Finished | May 16 01:52:32 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-cc3882a9-8cfe-420b-a570-1ffe87251e5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623717983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2623717983 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2140101530 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5640419663 ps |
| CPU time | 129.15 seconds |
| Started | May 16 01:52:33 PM PDT 24 |
| Finished | May 16 01:54:43 PM PDT 24 |
| Peak memory | 211648 kb |
| Host | smart-28d7551f-1c93-4bad-88e8-96756e3de158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2140101530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2140101530 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1071166001 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4232481195 ps |
| CPU time | 109.2 seconds |
| Started | May 16 01:52:35 PM PDT 24 |
| Finished | May 16 01:54:25 PM PDT 24 |
| Peak memory | 206400 kb |
| Host | smart-8175f74b-314a-40c1-b071-819d2399dfe4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1071166001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1071166001 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1185462728 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2214918875 ps |
| CPU time | 236.03 seconds |
| Started | May 16 01:52:39 PM PDT 24 |
| Finished | May 16 01:56:36 PM PDT 24 |
| Peak memory | 211656 kb |
| Host | smart-cefe51e7-0740-42d0-84fc-a9b933395421 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1185462728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1185462728 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3628643811 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 13143426260 ps |
| CPU time | 565.88 seconds |
| Started | May 16 01:52:42 PM PDT 24 |
| Finished | May 16 02:02:10 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-76ba7fe4-d96f-4e9d-8f23-61923046404e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3628643811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.3628643811 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2590373460 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 47814778 ps |
| CPU time | 2.63 seconds |
| Started | May 16 01:52:34 PM PDT 24 |
| Finished | May 16 01:52:38 PM PDT 24 |
| Peak memory | 203424 kb |
| Host | smart-90477cb3-115f-4baa-b4f8-8a416c4b9c55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590373460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2590373460 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.107912470 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 351967689 ps |
| CPU time | 22.91 seconds |
| Started | May 16 01:52:53 PM PDT 24 |
| Finished | May 16 01:53:18 PM PDT 24 |
| Peak memory | 204424 kb |
| Host | smart-c2a152ca-2b71-423f-a454-2b1372066a0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=107912470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.107912470 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.88403820 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 148711166219 ps |
| CPU time | 533.39 seconds |
| Started | May 16 01:52:53 PM PDT 24 |
| Finished | May 16 02:01:49 PM PDT 24 |
| Peak memory | 211628 kb |
| Host | smart-5aa41b3f-3d49-4e89-a8d5-07fa8b9e5668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=88403820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.88403820 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3243318382 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 163418195 ps |
| CPU time | 15.48 seconds |
| Started | May 16 01:52:52 PM PDT 24 |
| Finished | May 16 01:53:11 PM PDT 24 |
| Peak memory | 203960 kb |
| Host | smart-51622852-1f46-4900-b954-096305c22727 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3243318382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3243318382 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2617015702 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 74396936 ps |
| CPU time | 7.07 seconds |
| Started | May 16 01:52:54 PM PDT 24 |
| Finished | May 16 01:53:03 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-d4702c39-946c-48a0-9568-9e606067e3a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2617015702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2617015702 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.2719357798 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 230502108 ps |
| CPU time | 7.52 seconds |
| Started | May 16 01:52:52 PM PDT 24 |
| Finished | May 16 01:53:03 PM PDT 24 |
| Peak memory | 204416 kb |
| Host | smart-14cbef5d-f578-4d84-886c-6838ccc6a7d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2719357798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2719357798 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2009613502 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 19134044289 ps |
| CPU time | 89.46 seconds |
| Started | May 16 01:52:54 PM PDT 24 |
| Finished | May 16 01:54:26 PM PDT 24 |
| Peak memory | 205016 kb |
| Host | smart-4ff6b507-3b7c-41c1-90f5-e6b25b48b7b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009613502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2009613502 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.813994374 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4167019998 ps |
| CPU time | 26.09 seconds |
| Started | May 16 01:52:52 PM PDT 24 |
| Finished | May 16 01:53:21 PM PDT 24 |
| Peak memory | 204080 kb |
| Host | smart-a113241e-c307-4064-9c43-e8a387086e19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=813994374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.813994374 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3846870111 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 22835043 ps |
| CPU time | 2.09 seconds |
| Started | May 16 01:52:54 PM PDT 24 |
| Finished | May 16 01:52:58 PM PDT 24 |
| Peak memory | 203420 kb |
| Host | smart-be5ba067-ddb6-4a6c-a49f-7dd710090334 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846870111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3846870111 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.3717818396 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2380899363 ps |
| CPU time | 37.54 seconds |
| Started | May 16 01:52:53 PM PDT 24 |
| Finished | May 16 01:53:33 PM PDT 24 |
| Peak memory | 211636 kb |
| Host | smart-06bd1c7d-536d-4e55-aaaa-9543bd0ebad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3717818396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3717818396 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.3206362381 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 65485274 ps |
| CPU time | 2.58 seconds |
| Started | May 16 01:52:44 PM PDT 24 |
| Finished | May 16 01:52:49 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-2fd3f502-aa92-40f4-a332-da27335f144f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3206362381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3206362381 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2648871749 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 5795320905 ps |
| CPU time | 34.94 seconds |
| Started | May 16 01:52:42 PM PDT 24 |
| Finished | May 16 01:53:19 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-8459840c-df40-49b6-b6b1-10074822628d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648871749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2648871749 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3330916841 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2643531556 ps |
| CPU time | 23.61 seconds |
| Started | May 16 01:52:42 PM PDT 24 |
| Finished | May 16 01:53:08 PM PDT 24 |
| Peak memory | 203352 kb |
| Host | smart-d1f7070c-cfae-416b-9fd3-e02c3979cf22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3330916841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3330916841 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3169476126 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 113282825 ps |
| CPU time | 2.62 seconds |
| Started | May 16 01:52:43 PM PDT 24 |
| Finished | May 16 01:52:48 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-464e77b5-097a-4d6b-ac56-4dce77bb2487 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169476126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3169476126 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2726428459 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5156961539 ps |
| CPU time | 166.83 seconds |
| Started | May 16 01:52:54 PM PDT 24 |
| Finished | May 16 01:55:43 PM PDT 24 |
| Peak memory | 208920 kb |
| Host | smart-e3d67ead-672d-4c0f-a3e2-2178ee0147ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2726428459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2726428459 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2298975714 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1266382737 ps |
| CPU time | 125.29 seconds |
| Started | May 16 01:52:54 PM PDT 24 |
| Finished | May 16 01:55:01 PM PDT 24 |
| Peak memory | 207580 kb |
| Host | smart-c164ed69-b57e-4cb0-9d97-89afb65299f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2298975714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2298975714 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3237261067 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 112946379 ps |
| CPU time | 44.26 seconds |
| Started | May 16 01:52:54 PM PDT 24 |
| Finished | May 16 01:53:40 PM PDT 24 |
| Peak memory | 206744 kb |
| Host | smart-a498a2c6-9832-4fde-a8b0-2b6b144e1d0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3237261067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.3237261067 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2161933261 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1760366716 ps |
| CPU time | 124.06 seconds |
| Started | May 16 01:52:54 PM PDT 24 |
| Finished | May 16 01:55:00 PM PDT 24 |
| Peak memory | 209732 kb |
| Host | smart-202c529c-ae4b-4895-b0e5-9abf5b4d7346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2161933261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2161933261 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3161631096 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 123774566 ps |
| CPU time | 20.7 seconds |
| Started | May 16 01:52:53 PM PDT 24 |
| Finished | May 16 01:53:16 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-26845a42-88ed-40a3-b0e0-c00a371ae0d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3161631096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3161631096 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1593703574 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 136895425 ps |
| CPU time | 4.42 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:53:09 PM PDT 24 |
| Peak memory | 203388 kb |
| Host | smart-68e46177-d503-43d8-afcd-f02382f18ba3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1593703574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1593703574 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3594148974 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 32211941845 ps |
| CPU time | 298.98 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:58:04 PM PDT 24 |
| Peak memory | 206772 kb |
| Host | smart-063f4acc-e8ab-4660-a3de-03e05c6d03b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3594148974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3594148974 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2649257950 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 41255287 ps |
| CPU time | 4.14 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:53:09 PM PDT 24 |
| Peak memory | 203396 kb |
| Host | smart-3da98729-76ea-4c0e-882a-f85051dbc029 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2649257950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2649257950 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.95319945 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1163671897 ps |
| CPU time | 35.86 seconds |
| Started | May 16 01:53:05 PM PDT 24 |
| Finished | May 16 01:53:42 PM PDT 24 |
| Peak memory | 203432 kb |
| Host | smart-e08e9ca1-0ce3-4fd4-8942-cd757a18735f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=95319945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.95319945 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.1592830642 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 25364276 ps |
| CPU time | 3.27 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:53:08 PM PDT 24 |
| Peak memory | 203932 kb |
| Host | smart-0ddcf815-f5b5-4de0-a3b5-e6736ce4381a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1592830642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1592830642 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1152499236 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 168818618852 ps |
| CPU time | 315.34 seconds |
| Started | May 16 01:53:06 PM PDT 24 |
| Finished | May 16 01:58:22 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-552ea270-0b85-41c8-9f00-efa38ed934bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152499236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1152499236 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.251824391 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 17245607676 ps |
| CPU time | 160.59 seconds |
| Started | May 16 01:53:02 PM PDT 24 |
| Finished | May 16 01:55:44 PM PDT 24 |
| Peak memory | 205112 kb |
| Host | smart-5bf6af0d-6592-4151-9213-d4e749b6d52c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=251824391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.251824391 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3212983193 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 46785751 ps |
| CPU time | 3.39 seconds |
| Started | May 16 01:53:02 PM PDT 24 |
| Finished | May 16 01:53:07 PM PDT 24 |
| Peak memory | 203916 kb |
| Host | smart-e20e1a9b-0d3a-474f-a17d-e3dec819e98c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212983193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3212983193 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.1053075957 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 2359220186 ps |
| CPU time | 13.53 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:53:18 PM PDT 24 |
| Peak memory | 203532 kb |
| Host | smart-7ffb3ccb-a37b-4af4-9ba7-093d19f2a441 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1053075957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1053075957 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.3992478904 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 293307092 ps |
| CPU time | 3.62 seconds |
| Started | May 16 01:53:04 PM PDT 24 |
| Finished | May 16 01:53:09 PM PDT 24 |
| Peak memory | 203416 kb |
| Host | smart-728232c2-f55d-499e-95d4-5d92366e0afb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3992478904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3992478904 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1861852889 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 12164234554 ps |
| CPU time | 31.04 seconds |
| Started | May 16 01:53:05 PM PDT 24 |
| Finished | May 16 01:53:37 PM PDT 24 |
| Peak memory | 203488 kb |
| Host | smart-d3419a41-3cf7-4ffc-90de-703353069df8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861852889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1861852889 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2244288799 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4813078572 ps |
| CPU time | 37.02 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:53:41 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-4e45bdb2-2b3b-4d2c-8d40-f6376b1c000b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2244288799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2244288799 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.698446394 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 31383314 ps |
| CPU time | 2.53 seconds |
| Started | May 16 01:53:06 PM PDT 24 |
| Finished | May 16 01:53:09 PM PDT 24 |
| Peak memory | 203324 kb |
| Host | smart-bf313109-fd96-4171-ab47-afe1fdd3b6a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698446394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.698446394 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1719434247 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1855177402 ps |
| CPU time | 29.99 seconds |
| Started | May 16 01:53:02 PM PDT 24 |
| Finished | May 16 01:53:34 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-bc812de9-ff51-4031-b26f-5ba278c18014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1719434247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1719434247 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2045612884 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 15401430964 ps |
| CPU time | 275.8 seconds |
| Started | May 16 01:53:02 PM PDT 24 |
| Finished | May 16 01:57:39 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-170bb371-7e28-4916-b122-0383a684c960 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2045612884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2045612884 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.320930659 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1577891054 ps |
| CPU time | 178.31 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:56:03 PM PDT 24 |
| Peak memory | 208448 kb |
| Host | smart-686fa041-4cc5-4e49-a603-74fadc0658ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=320930659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_ reset.320930659 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.4286120196 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 261736989 ps |
| CPU time | 91.44 seconds |
| Started | May 16 01:53:03 PM PDT 24 |
| Finished | May 16 01:54:36 PM PDT 24 |
| Peak memory | 208764 kb |
| Host | smart-85c00b85-b2f1-473b-bb3d-17e600520307 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4286120196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.4286120196 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1748173093 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 128710368 ps |
| CPU time | 25.13 seconds |
| Started | May 16 01:53:02 PM PDT 24 |
| Finished | May 16 01:53:29 PM PDT 24 |
| Peak memory | 204924 kb |
| Host | smart-99c70a65-1f76-4c66-92fa-8dbc1625a212 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1748173093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1748173093 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1437551691 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1170416954 ps |
| CPU time | 40.52 seconds |
| Started | May 16 01:53:13 PM PDT 24 |
| Finished | May 16 01:53:54 PM PDT 24 |
| Peak memory | 205860 kb |
| Host | smart-0d2cfffe-0fcb-4b85-b54e-c7564b9e0a05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1437551691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1437551691 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.181790454 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 55157960842 ps |
| CPU time | 312.77 seconds |
| Started | May 16 01:53:14 PM PDT 24 |
| Finished | May 16 01:58:28 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-05878932-f73a-4671-a76c-b21a08149210 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=181790454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow _rsp.181790454 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.4130228 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1379667008 ps |
| CPU time | 21.75 seconds |
| Started | May 16 01:53:14 PM PDT 24 |
| Finished | May 16 01:53:37 PM PDT 24 |
| Peak memory | 203812 kb |
| Host | smart-ed23ae78-bb62-4bd7-ac64-21771d907ef9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4130228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.4130228 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.797388713 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 715418152 ps |
| CPU time | 9.96 seconds |
| Started | May 16 01:53:14 PM PDT 24 |
| Finished | May 16 01:53:25 PM PDT 24 |
| Peak memory | 203448 kb |
| Host | smart-ea010c80-988e-4606-aefd-d81a5657dfce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=797388713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.797388713 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.1507738173 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 94793535 ps |
| CPU time | 13.57 seconds |
| Started | May 16 01:53:13 PM PDT 24 |
| Finished | May 16 01:53:29 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-2100360a-6990-4c34-93e5-a3d631dc7297 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1507738173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1507738173 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3628209778 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 41654005228 ps |
| CPU time | 214.71 seconds |
| Started | May 16 01:53:15 PM PDT 24 |
| Finished | May 16 01:56:51 PM PDT 24 |
| Peak memory | 211564 kb |
| Host | smart-9415f576-48b5-427d-862a-905e30ba636c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628209778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3628209778 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2474230452 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 12680567395 ps |
| CPU time | 87.62 seconds |
| Started | May 16 01:53:14 PM PDT 24 |
| Finished | May 16 01:54:43 PM PDT 24 |
| Peak memory | 211664 kb |
| Host | smart-63f7a518-9c4f-49f7-807f-62479bf73734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2474230452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2474230452 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1207301650 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 206035533 ps |
| CPU time | 7.16 seconds |
| Started | May 16 01:53:13 PM PDT 24 |
| Finished | May 16 01:53:22 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-996997e7-f549-456e-8478-10cf3fcd1054 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207301650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1207301650 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.2806077620 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1246454336 ps |
| CPU time | 29.98 seconds |
| Started | May 16 01:53:13 PM PDT 24 |
| Finished | May 16 01:53:45 PM PDT 24 |
| Peak memory | 204096 kb |
| Host | smart-45a337b1-f7cb-4d08-9f87-2bfc543e651a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2806077620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2806077620 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3885453082 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 169388887 ps |
| CPU time | 4.17 seconds |
| Started | May 16 01:53:04 PM PDT 24 |
| Finished | May 16 01:53:09 PM PDT 24 |
| Peak memory | 203352 kb |
| Host | smart-c70179c2-2a52-440b-a38f-ce53d1ed8594 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3885453082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3885453082 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3613822984 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 5582920006 ps |
| CPU time | 26.52 seconds |
| Started | May 16 01:53:14 PM PDT 24 |
| Finished | May 16 01:53:42 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-e9bf5743-1869-49d4-b86e-78e47d2e08ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613822984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3613822984 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1851029601 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4188693775 ps |
| CPU time | 31.26 seconds |
| Started | May 16 01:53:14 PM PDT 24 |
| Finished | May 16 01:53:46 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-e868e636-4816-4d33-bf40-2536f318a4c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1851029601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1851029601 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1704539471 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 28258186 ps |
| CPU time | 2.3 seconds |
| Started | May 16 01:53:15 PM PDT 24 |
| Finished | May 16 01:53:19 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-a3495080-aeed-4d7e-93a6-3b524c3bd304 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704539471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1704539471 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3715331448 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4442653682 ps |
| CPU time | 144.83 seconds |
| Started | May 16 01:53:14 PM PDT 24 |
| Finished | May 16 01:55:40 PM PDT 24 |
| Peak memory | 211676 kb |
| Host | smart-a062c382-6a1f-40be-a3e6-ffd918874f9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3715331448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3715331448 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3357506909 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 961051107 ps |
| CPU time | 32.22 seconds |
| Started | May 16 01:53:15 PM PDT 24 |
| Finished | May 16 01:53:48 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-43130570-d334-4f5a-94d2-b7abf77dbc06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3357506909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3357506909 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2437183672 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1256601903 ps |
| CPU time | 80.51 seconds |
| Started | May 16 01:53:16 PM PDT 24 |
| Finished | May 16 01:54:38 PM PDT 24 |
| Peak memory | 206044 kb |
| Host | smart-df4785fb-8fd5-4940-9eb3-6ca617d4bea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2437183672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2437183672 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.802318819 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 256318579 ps |
| CPU time | 18.65 seconds |
| Started | May 16 01:53:13 PM PDT 24 |
| Finished | May 16 01:53:33 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-efe982cf-b825-40e1-9cb7-9d8b5aadb27c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=802318819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.802318819 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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