Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 525 1 T2 2 T9 3 T10 5
all_values[1] 515 1 T2 2 T9 3 T10 1
all_values[2] 516 1 T2 2 T9 4 T12 2
all_values[3] 492 1 T2 3 T9 3 T10 1
all_values[4] 490 1 T9 3 T10 2 T12 1
all_values[5] 500 1 T2 1 T9 3 T10 3
all_values[6] 498 1 T10 3 T16 1 T187 1
all_values[7] 533 1 T2 2 T9 4 T12 1
all_values[8] 509 1 T2 5 T9 4 T10 3
all_values[9] 478 1 T2 1 T9 1 T15 1
all_values[10] 515 1 T2 1 T9 4 T12 2
all_values[11] 523 1 T2 2 T9 3 T10 3
all_values[12] 506 1 T2 1 T9 2 T10 1
all_values[13] 535 1 T2 1 T9 3 T10 1
all_values[14] 490 1 T2 2 T9 3 T10 1
all_values[15] 466 1 T2 2 T9 2 T17 1
all_values[16] 518 1 T2 2 T9 4 T12 2
all_values[17] 480 1 T2 1 T9 1 T15 1
all_values[18] 485 1 T2 2 T9 3 T10 2
all_values[19] 491 1 T2 1 T9 2 T10 3
all_values[20] 516 1 T2 3 T9 5 T10 1
all_values[21] 466 1 T2 3 T9 2 T17 2
all_values[22] 474 1 T2 1 T9 2 T10 2
all_values[23] 514 1 T2 1 T9 2 T10 1

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