Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1892	1			T2	26		T9	15		T4	3
all_values[1]	1901	1			T1	1		T2	21		T9	17
all_values[2]	1925	1			T1	3		T2	27		T9	15
all_values[3]	1854	1			T1	1		T2	17		T9	12
all_values[4]	1824	1			T2	13		T9	11		T4	1
all_values[5]	1810	1			T2	16		T9	15		T4	3
all_values[6]	1828	1			T1	1		T2	32		T9	10
all_values[7]	1885	1			T2	17		T9	16		T4	2
all_values[8]	1884	1			T2	24		T9	18		T4	2
all_values[9]	1878	1			T2	22		T9	10		T15	1
all_values[10]	1881	1			T1	1		T2	20		T9	17
all_values[11]	1874	1			T2	16		T9	24		T4	1
all_values[12]	1921	1			T1	2		T2	20		T9	12
all_values[13]	1832	1			T1	2		T2	20		T9	9
all_values[14]	1915	1			T2	14		T9	9		T4	2
all_values[15]	1922	1			T1	2		T2	18		T9	14
all_values[16]	1864	1			T1	3		T2	21		T9	18
all_values[17]	1867	1			T2	21		T9	14		T15	1
all_values[18]	1981	1			T2	20		T9	22		T15	4
all_values[19]	1849	1			T2	17		T9	10		T4	1
all_values[20]	1798	1			T2	21		T9	14		T4	1
all_values[21]	1884	1			T1	1		T2	24		T9	20
all_values[22]	1923	1			T1	1		T2	23		T9	11
all_values[23]	1789	1			T1	2		T2	19		T9	8
all_values[24]	1929	1			T1	1		T2	23		T9	7
all_values[25]	1890	1			T1	2		T2	26		T9	16
all_values[26]	1882	1			T1	1		T2	13		T9	12
all_values[27]	1886	1			T1	2		T2	20		T9	11
all_values[28]	1886	1			T1	1		T2	20		T9	17
all_values[29]	1931	1			T1	3		T2	23		T9	15
all_values[30]	1890	1			T2	26		T9	10		T4	3
all_values[31]	1859	1			T2	26		T9	10		T15	4
all_values[32]	1843	1			T1	2		T2	19		T9	17
all_values[33]	1862	1			T2	18		T9	12		T4	2
all_values[34]	1877	1			T1	1		T2	17		T9	14
all_values[35]	1892	1			T1	2		T2	10		T9	13
all_values[36]	1873	1			T1	3		T2	28		T9	10
all_values[37]	1950	1			T1	2		T2	21		T9	10
all_values[38]	1843	1			T1	1		T2	17		T9	16
all_values[39]	1856	1			T2	15		T9	8		T4	2
all_values[40]	1913	1			T1	2		T2	20		T9	10
all_values[41]	1832	1			T1	1		T2	19		T9	14
all_values[42]	1896	1			T1	2		T2	19		T9	14
all_values[43]	1800	1			T1	2		T2	23		T9	15
all_values[44]	1863	1			T1	1		T2	20		T9	9
all_values[45]	1928	1			T1	1		T2	17		T9	15
all_values[46]	1871	1			T1	1		T2	20		T9	6
all_values[47]	1895	1			T1	2		T2	18		T9	18
all_values[48]	1844	1			T1	2		T2	9		T9	12
all_values[49]	1875	1			T2	22		T9	19		T4	1
all_values[50]	1899	1			T1	1		T2	22		T9	13
all_values[51]	1806	1			T1	1		T2	24		T9	13
all_values[52]	1853	1			T1	1		T2	21		T9	13
all_values[53]	1866	1			T1	1		T2	26		T9	14
all_values[54]	1830	1			T1	1		T2	16		T9	9
all_values[55]	1902	1			T1	1		T2	18		T9	21
all_values[56]	1897	1			T2	25		T9	14		T15	2
all_values[57]	1913	1			T2	22		T9	10		T4	2
all_values[58]	1950	1			T1	3		T2	14		T9	16
all_values[59]	1894	1			T2	22		T9	10		T4	2
all_values[60]	1914	1			T1	2		T2	17		T9	15
all_values[61]	1848	1			T2	14		T9	12		T15	3
all_values[62]	1786	1			T1	1		T2	18		T9	6
all_values[63]	1906	1			T1	4		T2	18		T9	8