Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1748	1			T2	3		T3	1		T9	5
all_values[1]	1798	1			T2	5		T3	3		T9	12
all_values[2]	1762	1			T2	1		T3	3		T9	18
all_values[3]	1851	1			T2	3		T3	3		T9	12
all_values[4]	1845	1			T2	4		T3	1		T9	5
all_values[5]	1828	1			T2	4		T3	2		T9	10
all_values[6]	1856	1			T2	5		T9	15		T8	3
all_values[7]	1841	1			T2	7		T3	1		T9	13
all_values[8]	1807	1			T2	4		T3	2		T9	15
all_values[9]	1812	1			T2	7		T3	1		T9	18
all_values[10]	1763	1			T2	8		T3	3		T9	15
all_values[11]	1881	1			T2	5		T3	1		T9	13
all_values[12]	1861	1			T2	1		T3	1		T9	12
all_values[13]	1745	1			T2	1		T3	2		T9	16
all_values[14]	1854	1			T2	7		T3	2		T9	14
all_values[15]	1814	1			T2	9		T9	13		T8	3
all_values[16]	1781	1			T2	9		T3	4		T9	13
all_values[17]	1850	1			T2	6		T3	4		T9	16
all_values[18]	1824	1			T2	7		T3	1		T9	18
all_values[19]	1820	1			T2	7		T3	5		T9	16
all_values[20]	1864	1			T2	1		T3	1		T9	15
all_values[21]	1911	1			T2	9		T3	3		T9	11
all_values[22]	1881	1			T2	3		T3	2		T9	10
all_values[23]	1811	1			T2	3		T9	16		T8	3
all_values[24]	1797	1			T2	6		T3	4		T9	13
all_values[25]	1821	1			T2	6		T3	3		T9	11
all_values[26]	1856	1			T2	2		T3	1		T9	15
all_values[27]	1887	1			T2	4		T3	3		T9	18
all_values[28]	1789	1			T2	2		T3	3		T9	11
all_values[29]	1915	1			T2	5		T3	3		T9	16
all_values[30]	1843	1			T2	5		T3	4		T9	10
all_values[31]	1881	1			T2	6		T3	5		T9	13
all_values[32]	1841	1			T2	3		T3	1		T9	19
all_values[33]	1853	1			T2	6		T3	3		T9	16
all_values[34]	1837	1			T2	5		T3	3		T9	11
all_values[35]	1827	1			T2	5		T3	1		T9	13
all_values[36]	1831	1			T2	2		T3	3		T9	11
all_values[37]	1735	1			T2	3		T3	3		T9	10
all_values[38]	1853	1			T2	6		T3	3		T9	16
all_values[39]	1934	1			T2	2		T3	2		T9	10
all_values[40]	1836	1			T2	4		T9	13		T8	2
all_values[41]	1744	1			T2	7		T3	4		T9	15
all_values[42]	1779	1			T2	4		T3	2		T9	17
all_values[43]	1789	1			T2	3		T3	2		T9	15
all_values[44]	1896	1			T2	7		T3	1		T9	17
all_values[45]	1831	1			T2	4		T3	1		T9	10
all_values[46]	1876	1			T2	7		T9	6		T8	9
all_values[47]	1799	1			T2	2		T3	3		T9	12
all_values[48]	1837	1			T2	7		T3	2		T9	16
all_values[49]	1822	1			T2	5		T3	2		T9	11
all_values[50]	1875	1			T2	3		T3	5		T9	15
all_values[51]	1883	1			T2	7		T3	7		T9	11
all_values[52]	1821	1			T2	6		T9	14		T8	3
all_values[53]	1774	1			T2	6		T3	5		T9	15
all_values[54]	1897	1			T2	4		T3	1		T9	26
all_values[55]	1845	1			T2	3		T3	8		T9	15
all_values[56]	1877	1			T2	7		T3	3		T9	19
all_values[57]	1803	1			T2	9		T3	1		T9	8
all_values[58]	1797	1			T2	9		T3	3		T9	16
all_values[59]	1758	1			T2	3		T3	1		T9	16
all_values[60]	1922	1			T2	3		T3	1		T9	22
all_values[61]	1876	1			T2	1		T9	21		T8	5
all_values[62]	1811	1			T2	9		T3	4		T9	13
all_values[63]	1864	1			T2	5		T3	3		T9	13