Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.03	99.26	88.97	98.80		95.88	99.26	100.00

Total test records in report: 900

T763	/workspace/coverage/xbar_build_mode/4.xbar_smoke.2740985617	May 21 12:43:31 PM PDT 24	May 21 12:43:37 PM PDT 24	50218394 ps
T764	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3831943564	May 21 12:44:13 PM PDT 24	May 21 12:44:25 PM PDT 24	153818677 ps
T765	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1014071180	May 21 12:45:04 PM PDT 24	May 21 12:45:18 PM PDT 24	114419222 ps
T766	/workspace/coverage/xbar_build_mode/27.xbar_smoke.712250270	May 21 12:45:14 PM PDT 24	May 21 12:45:29 PM PDT 24	176582148 ps
T767	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1880417435	May 21 12:46:00 PM PDT 24	May 21 12:46:15 PM PDT 24	211642828 ps
T768	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3886593743	May 21 12:46:45 PM PDT 24	May 21 12:47:14 PM PDT 24	6504292128 ps
T769	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3617049657	May 21 12:44:35 PM PDT 24	May 21 12:46:53 PM PDT 24	468073179 ps
T22	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.620492342	May 21 12:45:46 PM PDT 24	May 21 12:51:15 PM PDT 24	8874540336 ps
T770	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.2643360429	May 21 12:44:43 PM PDT 24	May 21 12:46:19 PM PDT 24	736216155 ps
T771	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1728775527	May 21 12:44:21 PM PDT 24	May 21 12:47:10 PM PDT 24	18901574444 ps
T772	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.4267438999	May 21 12:46:00 PM PDT 24	May 21 12:47:34 PM PDT 24	17692891686 ps
T773	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1379527599	May 21 12:43:24 PM PDT 24	May 21 12:43:38 PM PDT 24	1398565775 ps
T774	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1881228435	May 21 12:44:59 PM PDT 24	May 21 12:47:53 PM PDT 24	40145856362 ps
T775	/workspace/coverage/xbar_build_mode/21.xbar_error_random.1983521546	May 21 12:45:01 PM PDT 24	May 21 12:45:15 PM PDT 24	258152827 ps
T122	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3970060432	May 21 12:44:34 PM PDT 24	May 21 12:54:35 PM PDT 24	98287218768 ps
T33	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3302366274	May 21 12:46:02 PM PDT 24	May 21 12:50:24 PM PDT 24	2121621921 ps
T776	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2458585128	May 21 12:44:58 PM PDT 24	May 21 12:45:11 PM PDT 24	1116010965 ps
T777	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.537390347	May 21 12:43:44 PM PDT 24	May 21 12:44:26 PM PDT 24	2372702378 ps
T778	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.379110806	May 21 12:45:56 PM PDT 24	May 21 12:46:13 PM PDT 24	87611921 ps
T279	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1556356642	May 21 12:45:26 PM PDT 24	May 21 12:46:17 PM PDT 24	10908095360 ps
T779	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1754509125	May 21 12:44:07 PM PDT 24	May 21 12:44:35 PM PDT 24	1336713782 ps
T780	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3539508857	May 21 12:44:22 PM PDT 24	May 21 12:52:13 PM PDT 24	92501756304 ps
T781	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2117876105	May 21 12:43:25 PM PDT 24	May 21 12:46:46 PM PDT 24	821790385 ps
T234	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2422308041	May 21 12:45:33 PM PDT 24	May 21 12:45:59 PM PDT 24	243762664 ps
T782	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3321730246	May 21 12:46:33 PM PDT 24	May 21 12:46:38 PM PDT 24	100697423 ps
T783	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.987025083	May 21 12:43:24 PM PDT 24	May 21 12:44:02 PM PDT 24	7611789121 ps
T784	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2317647768	May 21 12:43:42 PM PDT 24	May 21 12:44:47 PM PDT 24	9813849842 ps
T785	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3146002939	May 21 12:46:50 PM PDT 24	May 21 12:48:17 PM PDT 24	10923044521 ps
T786	/workspace/coverage/xbar_build_mode/15.xbar_error_random.324770989	May 21 12:44:27 PM PDT 24	May 21 12:44:36 PM PDT 24	501020918 ps
T787	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.4215808104	May 21 12:44:48 PM PDT 24	May 21 12:47:47 PM PDT 24	984924692 ps
T31	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3835184944	May 21 12:44:36 PM PDT 24	May 21 12:51:17 PM PDT 24	2595022080 ps
T788	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1818161682	May 21 12:43:59 PM PDT 24	May 21 12:44:05 PM PDT 24	108222353 ps
T789	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2077048116	May 21 12:44:22 PM PDT 24	May 21 12:44:29 PM PDT 24	176448174 ps
T790	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.4106492858	May 21 12:43:18 PM PDT 24	May 21 12:46:56 PM PDT 24	25196407345 ps
T791	/workspace/coverage/xbar_build_mode/38.xbar_random.1765473162	May 21 12:46:12 PM PDT 24	May 21 12:46:43 PM PDT 24	1096636882 ps
T792	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3409454752	May 21 12:43:56 PM PDT 24	May 21 12:44:28 PM PDT 24	22201503150 ps
T793	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1225777789	May 21 12:44:29 PM PDT 24	May 21 12:44:34 PM PDT 24	66579174 ps
T794	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.4200976871	May 21 12:46:09 PM PDT 24	May 21 12:46:23 PM PDT 24	144459570 ps
T795	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.2170623454	May 21 12:43:31 PM PDT 24	May 21 12:46:00 PM PDT 24	4722648451 ps
T796	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.1924426829	May 21 12:45:43 PM PDT 24	May 21 12:47:54 PM PDT 24	1142300700 ps
T797	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2922995405	May 21 12:44:13 PM PDT 24	May 21 12:44:30 PM PDT 24	89045344 ps
T798	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1862198586	May 21 12:45:40 PM PDT 24	May 21 12:52:44 PM PDT 24	7929606391 ps
T799	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2506471345	May 21 12:44:35 PM PDT 24	May 21 12:44:42 PM PDT 24	53820836 ps
T800	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3118299898	May 21 12:45:31 PM PDT 24	May 21 12:49:19 PM PDT 24	12703928337 ps
T801	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2712032128	May 21 12:43:37 PM PDT 24	May 21 12:44:19 PM PDT 24	570580155 ps
T802	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2804972959	May 21 12:46:39 PM PDT 24	May 21 12:47:21 PM PDT 24	18435746493 ps
T803	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.798005684	May 21 12:45:39 PM PDT 24	May 21 12:45:54 PM PDT 24	566588913 ps
T804	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3877876118	May 21 12:45:00 PM PDT 24	May 21 12:45:23 PM PDT 24	1865977279 ps
T805	/workspace/coverage/xbar_build_mode/5.xbar_error_random.2573757847	May 21 12:43:46 PM PDT 24	May 21 12:44:17 PM PDT 24	3267219818 ps
T806	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.969894167	May 21 12:46:22 PM PDT 24	May 21 12:50:29 PM PDT 24	54565817561 ps
T807	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3914033773	May 21 12:43:58 PM PDT 24	May 21 12:44:22 PM PDT 24	2359854506 ps
T808	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.3857985899	May 21 12:43:43 PM PDT 24	May 21 12:45:46 PM PDT 24	22660493495 ps
T809	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.569856183	May 21 12:46:32 PM PDT 24	May 21 12:46:40 PM PDT 24	74221479 ps
T810	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3884479643	May 21 12:45:32 PM PDT 24	May 21 12:46:04 PM PDT 24	5985036882 ps
T235	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1802270046	May 21 12:46:53 PM PDT 24	May 21 12:47:15 PM PDT 24	208407314 ps
T811	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3151617681	May 21 12:45:24 PM PDT 24	May 21 12:50:47 PM PDT 24	35548053922 ps
T812	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3607746055	May 21 12:46:34 PM PDT 24	May 21 12:47:23 PM PDT 24	634463060 ps
T813	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2345924878	May 21 12:46:37 PM PDT 24	May 21 12:48:27 PM PDT 24	395330292 ps
T241	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2859893835	May 21 12:44:30 PM PDT 24	May 21 12:44:55 PM PDT 24	2869209401 ps
T814	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2124977300	May 21 12:43:48 PM PDT 24	May 21 12:44:15 PM PDT 24	1206204568 ps
T815	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2105149675	May 21 12:43:18 PM PDT 24	May 21 12:43:23 PM PDT 24	35445715 ps
T816	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3936174223	May 21 12:46:01 PM PDT 24	May 21 12:46:26 PM PDT 24	4407374592 ps
T817	/workspace/coverage/xbar_build_mode/7.xbar_error_random.4050634568	May 21 12:43:55 PM PDT 24	May 21 12:44:06 PM PDT 24	111054434 ps
T818	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.934257585	May 21 12:45:13 PM PDT 24	May 21 12:45:54 PM PDT 24	1825466962 ps
T819	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3384375718	May 21 12:44:43 PM PDT 24	May 21 12:45:00 PM PDT 24	188461011 ps
T820	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3114280515	May 21 12:43:58 PM PDT 24	May 21 12:47:48 PM PDT 24	3322347665 ps
T821	/workspace/coverage/xbar_build_mode/31.xbar_random.3848644925	May 21 12:45:35 PM PDT 24	May 21 12:46:02 PM PDT 24	166605062 ps
T822	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1066504286	May 21 12:45:25 PM PDT 24	May 21 12:46:02 PM PDT 24	6120195779 ps
T823	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1797655262	May 21 12:46:08 PM PDT 24	May 21 12:47:00 PM PDT 24	6671723445 ps
T144	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.135797553	May 21 12:45:20 PM PDT 24	May 21 12:45:53 PM PDT 24	1326480175 ps
T824	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2944934674	May 21 12:46:12 PM PDT 24	May 21 12:46:26 PM PDT 24	87383589 ps
T825	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.493709990	May 21 12:45:41 PM PDT 24	May 21 12:46:11 PM PDT 24	6205663888 ps
T826	/workspace/coverage/xbar_build_mode/47.xbar_smoke.3574583119	May 21 12:46:48 PM PDT 24	May 21 12:46:52 PM PDT 24	30594816 ps
T827	/workspace/coverage/xbar_build_mode/27.xbar_random.1565713581	May 21 12:45:18 PM PDT 24	May 21 12:45:35 PM PDT 24	55364172 ps
T828	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.741781618	May 21 12:46:57 PM PDT 24	May 21 12:47:13 PM PDT 24	2287601425 ps
T829	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2082067566	May 21 12:43:43 PM PDT 24	May 21 12:45:03 PM PDT 24	9524736403 ps
T830	/workspace/coverage/xbar_build_mode/23.xbar_same_source.4202130882	May 21 12:45:03 PM PDT 24	May 21 12:45:16 PM PDT 24	851180298 ps
T831	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1809530365	May 21 12:43:44 PM PDT 24	May 21 12:44:00 PM PDT 24	273231845 ps
T832	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3839047477	May 21 12:43:29 PM PDT 24	May 21 12:44:11 PM PDT 24	190815228 ps
T833	/workspace/coverage/xbar_build_mode/18.xbar_same_source.844964239	May 21 12:44:44 PM PDT 24	May 21 12:44:58 PM PDT 24	892520136 ps
T834	/workspace/coverage/xbar_build_mode/17.xbar_error_random.2711067308	May 21 12:44:35 PM PDT 24	May 21 12:44:40 PM PDT 24	60288407 ps
T835	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2788709803	May 21 12:46:00 PM PDT 24	May 21 12:46:32 PM PDT 24	1423948165 ps
T836	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3014570315	May 21 12:45:06 PM PDT 24	May 21 12:45:39 PM PDT 24	4037242041 ps
T837	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1276093408	May 21 12:43:25 PM PDT 24	May 21 12:43:41 PM PDT 24	101720656 ps
T838	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.202613010	May 21 12:45:46 PM PDT 24	May 21 12:47:26 PM PDT 24	2360362006 ps
T839	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.750901538	May 21 12:46:38 PM PDT 24	May 21 12:47:22 PM PDT 24	13302325321 ps
T840	/workspace/coverage/xbar_build_mode/0.xbar_same_source.529806671	May 21 12:43:17 PM PDT 24	May 21 12:43:38 PM PDT 24	2547203607 ps
T841	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3289635370	May 21 12:43:36 PM PDT 24	May 21 12:46:37 PM PDT 24	27911482255 ps
T842	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2880542050	May 21 12:45:25 PM PDT 24	May 21 12:46:10 PM PDT 24	6273378929 ps
T843	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1078128336	May 21 12:44:08 PM PDT 24	May 21 12:44:16 PM PDT 24	64521990 ps
T844	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1409518577	May 21 12:46:11 PM PDT 24	May 21 12:49:05 PM PDT 24	12934587806 ps
T845	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.925870286	May 21 12:44:30 PM PDT 24	May 21 12:53:09 PM PDT 24	70073602857 ps
T846	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2734327203	May 21 12:44:19 PM PDT 24	May 21 12:47:15 PM PDT 24	503394825 ps
T847	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3310743005	May 21 12:45:00 PM PDT 24	May 21 12:46:13 PM PDT 24	33114162279 ps
T848	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2724502911	May 21 12:46:30 PM PDT 24	May 21 12:47:37 PM PDT 24	2983842532 ps
T849	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2537433012	May 21 12:45:55 PM PDT 24	May 21 12:47:31 PM PDT 24	327473859 ps
T850	/workspace/coverage/xbar_build_mode/39.xbar_same_source.3322804729	May 21 12:46:13 PM PDT 24	May 21 12:46:25 PM PDT 24	497439997 ps
T851	/workspace/coverage/xbar_build_mode/36.xbar_random.2849258668	May 21 12:46:00 PM PDT 24	May 21 12:46:13 PM PDT 24	150882669 ps
T852	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.300006754	May 21 12:44:36 PM PDT 24	May 21 12:44:44 PM PDT 24	35611398 ps
T853	/workspace/coverage/xbar_build_mode/45.xbar_random.3616783150	May 21 12:46:33 PM PDT 24	May 21 12:47:11 PM PDT 24	1707901311 ps
T854	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2633573452	May 21 12:46:13 PM PDT 24	May 21 12:46:44 PM PDT 24	3173134606 ps
T855	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.351702084	May 21 12:45:57 PM PDT 24	May 21 12:46:59 PM PDT 24	10754342443 ps
T856	/workspace/coverage/xbar_build_mode/37.xbar_same_source.2077539	May 21 12:46:06 PM PDT 24	May 21 12:46:47 PM PDT 24	1822697427 ps
T857	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.849910714	May 21 12:43:45 PM PDT 24	May 21 12:48:13 PM PDT 24	584442100 ps
T858	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3687712063	May 21 12:45:20 PM PDT 24	May 21 12:45:33 PM PDT 24	24343691 ps
T859	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.2241558919	May 21 12:44:59 PM PDT 24	May 21 12:46:44 PM PDT 24	15864005680 ps
T860	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2995476196	May 21 12:44:36 PM PDT 24	May 21 12:44:59 PM PDT 24	1796614912 ps
T861	/workspace/coverage/xbar_build_mode/10.xbar_error_random.2590734986	May 21 12:44:08 PM PDT 24	May 21 12:44:35 PM PDT 24	2675213736 ps
T862	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.3320356835	May 21 12:46:39 PM PDT 24	May 21 12:50:11 PM PDT 24	23128271008 ps
T863	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1897395713	May 21 12:46:12 PM PDT 24	May 21 12:48:38 PM PDT 24	19208018365 ps
T864	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.323290526	May 21 12:45:04 PM PDT 24	May 21 12:47:19 PM PDT 24	81007574882 ps
T865	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3440168608	May 21 12:43:52 PM PDT 24	May 21 12:44:13 PM PDT 24	148528228 ps
T866	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2134861868	May 21 12:45:00 PM PDT 24	May 21 12:45:31 PM PDT 24	2883387433 ps
T867	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1971785483	May 21 12:44:33 PM PDT 24	May 21 12:45:40 PM PDT 24	13250376278 ps
T868	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3718916900	May 21 12:45:11 PM PDT 24	May 21 12:45:48 PM PDT 24	7880488385 ps
T869	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.363801408	May 21 12:46:46 PM PDT 24	May 21 12:50:08 PM PDT 24	2309182556 ps
T870	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.291562758	May 21 12:43:54 PM PDT 24	May 21 12:44:07 PM PDT 24	90688610 ps
T871	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.46808978	May 21 12:45:43 PM PDT 24	May 21 12:45:49 PM PDT 24	114166039 ps
T872	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3326672451	May 21 12:43:53 PM PDT 24	May 21 12:45:21 PM PDT 24	3719693863 ps
T873	/workspace/coverage/xbar_build_mode/19.xbar_random.3070600993	May 21 12:44:41 PM PDT 24	May 21 12:44:49 PM PDT 24	26626104 ps
T874	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.756436577	May 21 12:46:20 PM PDT 24	May 21 12:48:41 PM PDT 24	310815888 ps
T875	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1595748710	May 21 12:46:00 PM PDT 24	May 21 12:46:19 PM PDT 24	143358163 ps
T133	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1678730361	May 21 12:43:46 PM PDT 24	May 21 12:52:30 PM PDT 24	57183536432 ps
T876	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.1238649944	May 21 12:46:13 PM PDT 24	May 21 12:47:01 PM PDT 24	1241959647 ps
T877	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2399845791	May 21 12:43:32 PM PDT 24	May 21 12:49:10 PM PDT 24	16442003883 ps
T878	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.4273461129	May 21 12:44:43 PM PDT 24	May 21 12:45:14 PM PDT 24	3815610201 ps
T879	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4292574801	May 21 12:45:32 PM PDT 24	May 21 12:47:44 PM PDT 24	269169599 ps
T880	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.4230510067	May 21 12:46:28 PM PDT 24	May 21 12:47:27 PM PDT 24	10198465798 ps
T881	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3503705542	May 21 12:44:36 PM PDT 24	May 21 12:48:25 PM PDT 24	61010057561 ps
T882	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.424086307	May 21 12:46:53 PM PDT 24	May 21 12:47:08 PM PDT 24	373410298 ps
T883	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3547080877	May 21 12:46:30 PM PDT 24	May 21 12:52:09 PM PDT 24	81712423035 ps
T884	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2359723716	May 21 12:44:33 PM PDT 24	May 21 12:44:39 PM PDT 24	375189051 ps
T885	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2661684361	May 21 12:46:41 PM PDT 24	May 21 12:46:56 PM PDT 24	527524096 ps
T134	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3733082355	May 21 12:46:34 PM PDT 24	May 21 12:51:23 PM PDT 24	35191721925 ps
T886	/workspace/coverage/xbar_build_mode/13.xbar_smoke.3398879047	May 21 12:44:13 PM PDT 24	May 21 12:44:22 PM PDT 24	273791149 ps
T887	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1120615198	May 21 12:46:28 PM PDT 24	May 21 12:51:17 PM PDT 24	3243063368 ps
T888	/workspace/coverage/xbar_build_mode/6.xbar_error_random.722518678	May 21 12:43:46 PM PDT 24	May 21 12:43:53 PM PDT 24	65050007 ps
T889	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1795479754	May 21 12:45:43 PM PDT 24	May 21 12:46:18 PM PDT 24	7376853741 ps
T890	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.4059210289	May 21 12:43:25 PM PDT 24	May 21 12:44:00 PM PDT 24	1164055333 ps
T891	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2861104923	May 21 12:43:53 PM PDT 24	May 21 12:46:15 PM PDT 24	30821088015 ps
T892	/workspace/coverage/xbar_build_mode/31.xbar_same_source.1647713136	May 21 12:45:32 PM PDT 24	May 21 12:45:51 PM PDT 24	880708227 ps
T893	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1615596772	May 21 12:43:48 PM PDT 24	May 21 12:44:14 PM PDT 24	157869367 ps
T894	/workspace/coverage/xbar_build_mode/3.xbar_smoke.3784670246	May 21 12:43:32 PM PDT 24	May 21 12:43:38 PM PDT 24	265662295 ps
T895	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.921810766	May 21 12:44:34 PM PDT 24	May 21 12:47:07 PM PDT 24	78651276554 ps
T896	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.13063544	May 21 12:46:45 PM PDT 24	May 21 12:46:57 PM PDT 24	342954217 ps
T897	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2417526412	May 21 12:46:34 PM PDT 24	May 21 12:47:21 PM PDT 24	7609937410 ps
T898	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.225028416	May 21 12:44:21 PM PDT 24	May 21 12:44:57 PM PDT 24	8801411829 ps
T135	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3098694478	May 21 12:44:13 PM PDT 24	May 21 12:48:19 PM PDT 24	73864175211 ps
T899	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.93150387	May 21 12:46:32 PM PDT 24	May 21 12:46:35 PM PDT 24	30448900 ps
T900	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1550414784	May 21 12:45:01 PM PDT 24	May 21 12:45:14 PM PDT 24	229350809 ps

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.571908684
Short name	T8
Test name
Test status
Simulation time	7100451920 ps
CPU time	164.8 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:48:06 PM PDT 24
Peak memory	208764 kb
Host	smart-612e3af5-53e8-4ed7-ae08-001d74fa85bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=571908684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.571908684
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1590410015
Short name	T42
Test name
Test status
Simulation time	102044823975 ps
CPU time	819.71 seconds
Started	May 21 12:45:15 PM PDT 24
Finished	May 21 12:59:05 PM PDT 24
Peak memory	207560 kb
Host	smart-850d1d07-5683-41c2-9f0c-f9d2f265f23f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1590410015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.1590410015
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.536112646
Short name	T100
Test name
Test status
Simulation time	123226636887 ps
CPU time	655.52 seconds
Started	May 21 12:45:13 PM PDT 24
Finished	May 21 12:56:20 PM PDT 24
Peak memory	211580 kb
Host	smart-aa0a990b-3e79-4c68-b366-1b88c4cf4f37
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=536112646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.536112646
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.369600003
Short name	T71
Test name
Test status
Simulation time	118073082690 ps
CPU time	643.47 seconds
Started	May 21 12:45:05 PM PDT 24
Finished	May 21 12:55:51 PM PDT 24
Peak memory	207640 kb
Host	smart-94c9ff35-4ac5-480c-8288-10fd816cf470
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=369600003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo w_rsp.369600003
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2287480973
Short name	T4
Test name
Test status
Simulation time	4940747921 ps
CPU time	30.61 seconds
Started	May 21 12:43:16 PM PDT 24
Finished	May 21 12:43:49 PM PDT 24
Peak memory	203380 kb
Host	smart-1ccd423b-6388-4189-b243-2e4235a1ff29
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287480973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2287480973
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1682165670
Short name	T9
Test name
Test status
Simulation time	1005456090 ps
CPU time	188.62 seconds
Started	May 21 12:44:50 PM PDT 24
Finished	May 21 12:48:03 PM PDT 24
Peak memory	209208 kb
Host	smart-1b9d88f8-918e-46f4-9fb0-07d7c98fbf5e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1682165670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1682165670
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.144503869
Short name	T96
Test name
Test status
Simulation time	129138439558 ps
CPU time	548.74 seconds
Started	May 21 12:44:05 PM PDT 24
Finished	May 21 12:53:16 PM PDT 24
Peak memory	211920 kb
Host	smart-1a0dd2a9-8034-40a4-9e5b-905397ebfdec
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=144503869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slo w_rsp.144503869
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.4142052412
Short name	T17
Test name
Test status
Simulation time	15288206927 ps
CPU time	322.08 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:50:53 PM PDT 24
Peak memory	211652 kb
Host	smart-5c3f70ff-7e1f-4826-8049-7af44fd0cc42
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4142052412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4142052412
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.437353401
Short name	T32
Test name
Test status
Simulation time	7114109619 ps
CPU time	188.13 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:47:53 PM PDT 24
Peak memory	211692 kb
Host	smart-4070e909-5564-49e3-bd34-a9c05363af85
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=437353401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.437353401
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.354613752
Short name	T34
Test name
Test status
Simulation time	2855930787 ps
CPU time	425.04 seconds
Started	May 21 12:46:40 PM PDT 24
Finished	May 21 12:53:47 PM PDT 24
Peak memory	209752 kb
Host	smart-69f77c42-c1dd-48fa-b656-7a6d7049eba7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=354613752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand _reset.354613752
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3983888488
Short name	T148
Test name
Test status
Simulation time	321455733 ps
CPU time	99.47 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:47:09 PM PDT 24
Peak memory	208080 kb
Host	smart-d58d64e1-079f-4ba2-9fd9-357abeb8fe04
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3983888488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3983888488
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.912948490
Short name	T24
Test name
Test status
Simulation time	3465439154 ps
CPU time	187.44 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:49:30 PM PDT 24
Peak memory	208892 kb
Host	smart-77ff3e66-ad38-46b7-bd32-0806e1c2d2f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=912948490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.912948490
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.4010163271
Short name	T118
Test name
Test status
Simulation time	1586477703 ps
CPU time	61.54 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:45:02 PM PDT 24
Peak memory	211628 kb
Host	smart-0e430bc2-8fb1-4b13-a2d8-40d20503eeae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4010163271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.4010163271
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2753015806
Short name	T97
Test name
Test status
Simulation time	6386815546 ps
CPU time	312.72 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:48:40 PM PDT 24
Peak memory	208916 kb
Host	smart-a258b41f-b53f-486f-835b-f0d0ed76f469
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2753015806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.2753015806
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1864947627
Short name	T68
Test name
Test status
Simulation time	5951301075 ps
CPU time	152.26 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:46:00 PM PDT 24
Peak memory	208548 kb
Host	smart-1d109de9-1113-45e3-b41b-0f0354249832
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1864947627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1864947627
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1956253837
Short name	T207
Test name
Test status
Simulation time	45126430390 ps
CPU time	309.08 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:49:29 PM PDT 24
Peak memory	206868 kb
Host	smart-eb3fcd9a-650c-4c61-a140-ab24d029741d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1956253837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.1956253837
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1643446660
Short name	T21
Test name
Test status
Simulation time	2395045778 ps
CPU time	371.72 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:50:30 PM PDT 24
Peak memory	226436 kb
Host	smart-f17dad4d-f33e-4cc6-9f0c-52e2879b9126
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1643446660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.1643446660
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3835184944
Short name	T31
Test name
Test status
Simulation time	2595022080 ps
CPU time	397 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:51:17 PM PDT 24
Peak memory	210108 kb
Host	smart-39b8dfc3-134e-4392-ab31-02bac09f5a10
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3835184944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3835184944
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3843358917
Short name	T29
Test name
Test status
Simulation time	393919920 ps
CPU time	125.9 seconds
Started	May 21 12:45:42 PM PDT 24
Finished	May 21 12:47:51 PM PDT 24
Peak memory	209692 kb
Host	smart-a9bfc4c2-5f64-4cb5-a99d-4e1ff93387d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843358917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.3843358917
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3302366274
Short name	T33
Test name
Test status
Simulation time	2121621921 ps
CPU time	256.78 seconds
Started	May 21 12:46:02 PM PDT 24
Finished	May 21 12:50:24 PM PDT 24
Peak memory	208372 kb
Host	smart-59c23f9d-278f-4997-bfc1-170722566a3b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3302366274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.3302366274
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.465058534
Short name	T434
Test name
Test status
Simulation time	1323952107 ps
CPU time	26.45 seconds
Started	May 21 12:43:15 PM PDT 24
Finished	May 21 12:43:45 PM PDT 24
Peak memory	204536 kb
Host	smart-df90d52c-5079-45d0-8e9d-bb515d783e62
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465058534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.465058534
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2426408383
Short name	T283
Test name
Test status
Simulation time	25726443401 ps
CPU time	211.04 seconds
Started	May 21 12:43:17 PM PDT 24
Finished	May 21 12:46:50 PM PDT 24
Peak memory	206960 kb
Host	smart-ddc912b7-11eb-451b-a053-b9dd81649453
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2426408383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2426408383
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3265388150
Short name	T404
Test name
Test status
Simulation time	530331814 ps
CPU time	6.9 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:34 PM PDT 24
Peak memory	203324 kb
Host	smart-6eb17ca2-53dd-4d26-b413-1fbb025e7d60
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3265388150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3265388150
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.1694464443
Short name	T617
Test name
Test status
Simulation time	924914673 ps
CPU time	24.14 seconds
Started	May 21 12:43:18 PM PDT 24
Finished	May 21 12:43:45 PM PDT 24
Peak memory	203552 kb
Host	smart-89fd23ec-9078-48e3-aa0a-d720ac593c37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1694464443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1694464443
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.3441700949
Short name	T502
Test name
Test status
Simulation time	3099015414 ps
CPU time	34.58 seconds
Started	May 21 12:43:16 PM PDT 24
Finished	May 21 12:43:54 PM PDT 24
Peak memory	204600 kb
Host	smart-214e894d-b4a3-4ed4-ab6e-4312924eba33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3441700949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3441700949
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1981146063
Short name	T720
Test name
Test status
Simulation time	8656944851 ps
CPU time	45.28 seconds
Started	May 21 12:43:17 PM PDT 24
Finished	May 21 12:44:06 PM PDT 24
Peak memory	204752 kb
Host	smart-b6d8f804-a0a3-4ec1-9526-002470f2be06
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981146063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1981146063
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.4106492858
Short name	T790
Test name
Test status
Simulation time	25196407345 ps
CPU time	215.39 seconds
Started	May 21 12:43:18 PM PDT 24
Finished	May 21 12:46:56 PM PDT 24
Peak memory	205180 kb
Host	smart-80084d71-52de-4fb8-bd9c-247eb6dccadd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4106492858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4106492858
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.4120508567
Short name	T400
Test name
Test status
Simulation time	191142543 ps
CPU time	23.25 seconds
Started	May 21 12:43:15 PM PDT 24
Finished	May 21 12:43:41 PM PDT 24
Peak memory	204580 kb
Host	smart-34124aee-2a98-4570-9784-01a3cf26944b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120508567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.4120508567
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.529806671
Short name	T840
Test name
Test status
Simulation time	2547203607 ps
CPU time	17.5 seconds
Started	May 21 12:43:17 PM PDT 24
Finished	May 21 12:43:38 PM PDT 24
Peak memory	203532 kb
Host	smart-a49b3ee8-07f4-4fa0-87fa-da477e63db87
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=529806671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.529806671
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.267136133
Short name	T754
Test name
Test status
Simulation time	151527454 ps
CPU time	3.61 seconds
Started	May 21 12:43:17 PM PDT 24
Finished	May 21 12:43:23 PM PDT 24
Peak memory	203368 kb
Host	smart-e575ba57-161e-4f79-b843-f23331193d1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=267136133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.267136133
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1642139953
Short name	T364
Test name
Test status
Simulation time	4485701064 ps
CPU time	29.23 seconds
Started	May 21 12:43:15 PM PDT 24
Finished	May 21 12:43:47 PM PDT 24
Peak memory	203508 kb
Host	smart-a1846d1c-ff9e-4e91-9321-3b2edd08fb51
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1642139953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1642139953
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2105149675
Short name	T815
Test name
Test status
Simulation time	35445715 ps
CPU time	2.04 seconds
Started	May 21 12:43:18 PM PDT 24
Finished	May 21 12:43:23 PM PDT 24
Peak memory	203400 kb
Host	smart-be2bd092-eb34-4ee0-914b-dd73400ccacb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105149675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2105149675
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.1840995624
Short name	T264
Test name
Test status
Simulation time	2824900946 ps
CPU time	79.31 seconds
Started	May 21 12:43:22 PM PDT 24
Finished	May 21 12:44:42 PM PDT 24
Peak memory	206008 kb
Host	smart-67712478-3157-432f-863d-988b5badac53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840995624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1840995624
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3461418250
Short name	T12
Test name
Test status
Simulation time	8533326561 ps
CPU time	213.41 seconds
Started	May 21 12:43:23 PM PDT 24
Finished	May 21 12:46:59 PM PDT 24
Peak memory	207852 kb
Host	smart-10d96426-c624-4986-9124-b28a58389ea6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3461418250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3461418250
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3487085367
Short name	T230
Test name
Test status
Simulation time	855788117 ps
CPU time	258.08 seconds
Started	May 21 12:43:21 PM PDT 24
Finished	May 21 12:47:41 PM PDT 24
Peak memory	208140 kb
Host	smart-58c70282-d101-43a3-ba3b-f06a2ba463aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3487085367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3487085367
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2117876105
Short name	T781
Test name
Test status
Simulation time	821790385 ps
CPU time	196.77 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:46:46 PM PDT 24
Peak memory	211364 kb
Host	smart-984dfb20-7442-4911-b4c5-396d1e2d0195
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2117876105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2117876105
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3501172086
Short name	T601
Test name
Test status
Simulation time	548394323 ps
CPU time	19.62 seconds
Started	May 21 12:43:17 PM PDT 24
Finished	May 21 12:43:39 PM PDT 24
Peak memory	204980 kb
Host	smart-0724ad4c-f6a2-4d01-80a3-a3e2120d1695
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3501172086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3501172086
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1722690855
Short name	T166
Test name
Test status
Simulation time	949461267 ps
CPU time	27.16 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:55 PM PDT 24
Peak memory	211612 kb
Host	smart-9b275695-3c5a-45a4-a98f-8c85f75b595d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1722690855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1722690855
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2963605920
Short name	T47
Test name
Test status
Simulation time	60463417222 ps
CPU time	330.36 seconds
Started	May 21 12:43:23 PM PDT 24
Finished	May 21 12:48:55 PM PDT 24
Peak memory	206804 kb
Host	smart-a44ce356-3a03-4d89-8a32-576c075add1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2963605920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2963605920
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2032091295
Short name	T454
Test name
Test status
Simulation time	367366768 ps
CPU time	13.21 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:41 PM PDT 24
Peak memory	203604 kb
Host	smart-80d2dc30-789d-48c9-94d9-948515eefcc1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2032091295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2032091295
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.601959313
Short name	T486
Test name
Test status
Simulation time	1132546661 ps
CPU time	26.13 seconds
Started	May 21 12:43:26 PM PDT 24
Finished	May 21 12:43:56 PM PDT 24
Peak memory	203664 kb
Host	smart-219ba170-f5b5-4a11-91e5-0bfc950dacbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=601959313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.601959313
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.1484030521
Short name	T257
Test name
Test status
Simulation time	1369526155 ps
CPU time	39.91 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:44:08 PM PDT 24
Peak memory	211624 kb
Host	smart-ab2a9fdc-dd63-4806-8b25-075ca0a4cd23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1484030521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1484030521
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2246089673
Short name	T709
Test name
Test status
Simulation time	17518256317 ps
CPU time	87.19 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:44:55 PM PDT 24
Peak memory	204652 kb
Host	smart-f3f66f41-e6fd-4dda-b0ff-e55d401e6716
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246089673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2246089673
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3614273828
Short name	T507
Test name
Test status
Simulation time	28866601027 ps
CPU time	198.82 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:46:48 PM PDT 24
Peak memory	204984 kb
Host	smart-4e014d67-58a0-48a5-bae2-117f8eaccba0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3614273828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3614273828
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1276093408
Short name	T837
Test name
Test status
Simulation time	101720656 ps
CPU time	11.77 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:43:41 PM PDT 24
Peak memory	204488 kb
Host	smart-0b97682a-21f4-46b1-96d5-5d862e4b71e2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276093408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1276093408
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.2259713388
Short name	T648
Test name
Test status
Simulation time	102393434 ps
CPU time	8.47 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:36 PM PDT 24
Peak memory	203932 kb
Host	smart-22a4abeb-81ee-4a08-bc16-e922fa773e68
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2259713388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2259713388
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.4117936670
Short name	T369
Test name
Test status
Simulation time	44906415 ps
CPU time	2.36 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:30 PM PDT 24
Peak memory	203348 kb
Host	smart-b4e464d8-0abe-4773-a964-ffa8f1cf7a5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4117936670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4117936670
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.987025083
Short name	T783
Test name
Test status
Simulation time	7611789121 ps
CPU time	36.01 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:44:02 PM PDT 24
Peak memory	203496 kb
Host	smart-3fc99f90-9fd0-4df0-b50c-29a31cca1a36
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=987025083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.987025083
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2267960854
Short name	T70
Test name
Test status
Simulation time	20597092748 ps
CPU time	42.03 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:44:09 PM PDT 24
Peak memory	203492 kb
Host	smart-f84ca4e3-da82-4b7e-84c8-ab44ace3d969
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2267960854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2267960854
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.352045553
Short name	T468
Test name
Test status
Simulation time	45602953 ps
CPU time	2.45 seconds
Started	May 21 12:43:23 PM PDT 24
Finished	May 21 12:43:28 PM PDT 24
Peak memory	203416 kb
Host	smart-4d604669-53fa-47f7-bc22-edad41020c92
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352045553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.352045553
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.3248646042
Short name	T153
Test name
Test status
Simulation time	4215629811 ps
CPU time	105.39 seconds
Started	May 21 12:43:23 PM PDT 24
Finished	May 21 12:45:11 PM PDT 24
Peak memory	205284 kb
Host	smart-8e9727d1-6032-4756-8f73-755d26ab7153
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3248646042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3248646042
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.202752925
Short name	T443
Test name
Test status
Simulation time	5135301736 ps
CPU time	109 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:45:18 PM PDT 24
Peak memory	206404 kb
Host	smart-d60a9aef-81ef-4c3f-a7ee-ffe647112573
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=202752925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.202752925
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.4145055849
Short name	T458
Test name
Test status
Simulation time	811657656 ps
CPU time	15.64 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:43:44 PM PDT 24
Peak memory	204900 kb
Host	smart-e62b40a0-bae1-4b37-aa12-1fbfaf609485
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145055849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.4145055849
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.930933237
Short name	T340
Test name
Test status
Simulation time	166002353 ps
CPU time	13.2 seconds
Started	May 21 12:44:06 PM PDT 24
Finished	May 21 12:44:20 PM PDT 24
Peak memory	211588 kb
Host	smart-b7eaaba8-39f9-43e5-97bd-60b8ca45dc65
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930933237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.930933237
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1754509125
Short name	T779
Test name
Test status
Simulation time	1336713782 ps
CPU time	26.7 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:44:35 PM PDT 24
Peak memory	203832 kb
Host	smart-8aa7bc19-c8cb-478b-818f-a2d5da7b3ba6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1754509125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1754509125
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.2590734986
Short name	T861
Test name
Test status
Simulation time	2675213736 ps
CPU time	24.73 seconds
Started	May 21 12:44:08 PM PDT 24
Finished	May 21 12:44:35 PM PDT 24
Peak memory	203480 kb
Host	smart-55740c60-e453-4a2c-828c-4680274cfc47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590734986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2590734986
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.2851745184
Short name	T41
Test name
Test status
Simulation time	101857215 ps
CPU time	4.35 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:44:14 PM PDT 24
Peak memory	203428 kb
Host	smart-8ce34a4b-9dc4-4b0d-a4e7-7d024885469c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2851745184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2851745184
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1352693542
Short name	T411
Test name
Test status
Simulation time	60351264395 ps
CPU time	101.26 seconds
Started	May 21 12:44:08 PM PDT 24
Finished	May 21 12:45:52 PM PDT 24
Peak memory	204880 kb
Host	smart-3cd2b3b2-0c95-4a46-bf68-fd28cbfc5a93
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352693542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1352693542
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.353789300
Short name	T696
Test name
Test status
Simulation time	29781151165 ps
CPU time	159.27 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:46:48 PM PDT 24
Peak memory	205044 kb
Host	smart-56cc072d-076a-4cc8-8e57-1e4abcc44107
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=353789300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.353789300
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2945451209
Short name	T627
Test name
Test status
Simulation time	65354475 ps
CPU time	8.56 seconds
Started	May 21 12:44:09 PM PDT 24
Finished	May 21 12:44:20 PM PDT 24
Peak memory	204480 kb
Host	smart-373c8ade-c62f-4d36-a936-91ca353a9a4b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945451209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2945451209
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.3812280266
Short name	T533
Test name
Test status
Simulation time	1590494171 ps
CPU time	19.68 seconds
Started	May 21 12:44:05 PM PDT 24
Finished	May 21 12:44:26 PM PDT 24
Peak memory	203440 kb
Host	smart-6829b90a-8f1d-4973-ac94-c79e3333990c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3812280266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3812280266
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.4054030205
Short name	T757
Test name
Test status
Simulation time	40495387 ps
CPU time	1.93 seconds
Started	May 21 12:44:08 PM PDT 24
Finished	May 21 12:44:12 PM PDT 24
Peak memory	203300 kb
Host	smart-646f2f3d-e123-4928-be0b-81f0498aa362
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4054030205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4054030205
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.256936912
Short name	T19
Test name
Test status
Simulation time	9783370677 ps
CPU time	29.41 seconds
Started	May 21 12:44:11 PM PDT 24
Finished	May 21 12:44:44 PM PDT 24
Peak memory	203472 kb
Host	smart-1ad6059a-0dd4-459c-a69a-7045482e40d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=256936912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.256936912
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.772625260
Short name	T463
Test name
Test status
Simulation time	8070228225 ps
CPU time	31.89 seconds
Started	May 21 12:44:06 PM PDT 24
Finished	May 21 12:44:40 PM PDT 24
Peak memory	203408 kb
Host	smart-6e0182d8-3504-481e-9891-edfb3b938710
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=772625260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.772625260
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.702251349
Short name	T591
Test name
Test status
Simulation time	34181777 ps
CPU time	2.38 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:44:11 PM PDT 24
Peak memory	203356 kb
Host	smart-12769d73-6dbb-4104-a3ba-a1e6b1545d5a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702251349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.702251349
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.4057198937
Short name	T577
Test name
Test status
Simulation time	1425180609 ps
CPU time	147.45 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:46:44 PM PDT 24
Peak memory	211604 kb
Host	smart-95434c9f-bff3-421a-b643-3d4c76bd06d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4057198937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4057198937
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2133008385
Short name	T365
Test name
Test status
Simulation time	941426944 ps
CPU time	107.23 seconds
Started	May 21 12:44:09 PM PDT 24
Finished	May 21 12:45:59 PM PDT 24
Peak memory	206388 kb
Host	smart-595e259b-8d8a-4fae-b410-00594e986845
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2133008385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2133008385
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2663588352
Short name	T436
Test name
Test status
Simulation time	680964302 ps
CPU time	274.32 seconds
Started	May 21 12:44:06 PM PDT 24
Finished	May 21 12:48:42 PM PDT 24
Peak memory	208364 kb
Host	smart-e9b46849-a51b-4302-8db4-7a5e7af69818
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2663588352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2663588352
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1559510295
Short name	T698
Test name
Test status
Simulation time	86044583 ps
CPU time	17.01 seconds
Started	May 21 12:44:06 PM PDT 24
Finished	May 21 12:44:25 PM PDT 24
Peak memory	205480 kb
Host	smart-384c8424-8f1d-4e8a-99d1-69fae0ac8251
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1559510295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1559510295
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1466250018
Short name	T394
Test name
Test status
Simulation time	2812927086 ps
CPU time	19.11 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:44:29 PM PDT 24
Peak memory	211684 kb
Host	smart-386f8d4b-49f5-475c-9b9c-3c3ab4c63d1f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1466250018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1466250018
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1064426606
Short name	T142
Test name
Test status
Simulation time	5590170514 ps
CPU time	52.34 seconds
Started	May 21 12:44:15 PM PDT 24
Finished	May 21 12:45:12 PM PDT 24
Peak memory	205308 kb
Host	smart-f86059bc-3d2b-401e-adc7-e069607d07d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1064426606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1064426606
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1822847465
Short name	T117
Test name
Test status
Simulation time	361884010504 ps
CPU time	868.21 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:58:47 PM PDT 24
Peak memory	207412 kb
Host	smart-24298d1f-b737-4a68-ad1d-d9f86cae6e42
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1822847465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1822847465
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4041604824
Short name	T503
Test name
Test status
Simulation time	955353432 ps
CPU time	10.59 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:44:28 PM PDT 24
Peak memory	203356 kb
Host	smart-849fbd47-d492-4857-ae8a-b2a213b01746
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4041604824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4041604824
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.2203976167
Short name	T225
Test name
Test status
Simulation time	40533811 ps
CPU time	3.35 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:44:23 PM PDT 24
Peak memory	203384 kb
Host	smart-761862da-ff02-40ce-89e8-e88a8b8539e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2203976167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2203976167
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.1278940796
Short name	T43
Test name
Test status
Simulation time	945357629 ps
CPU time	28.94 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:44:49 PM PDT 24
Peak memory	204556 kb
Host	smart-c1c629fc-f678-4c8f-8768-78c94aa1993a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1278940796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1278940796
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.349634598
Short name	T439
Test name
Test status
Simulation time	39854096959 ps
CPU time	67.22 seconds
Started	May 21 12:44:11 PM PDT 24
Finished	May 21 12:45:23 PM PDT 24
Peak memory	204752 kb
Host	smart-5d765966-79d5-4f7a-a331-51788a09b614
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=349634598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.349634598
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2749073986
Short name	T188
Test name
Test status
Simulation time	31405786688 ps
CPU time	149.16 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:46:48 PM PDT 24
Peak memory	211676 kb
Host	smart-f1fa7a2d-58a4-47bc-806a-ccade21e2192
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2749073986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2749073986
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2922995405
Short name	T797
Test name
Test status
Simulation time	89045344 ps
CPU time	12.24 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:30 PM PDT 24
Peak memory	204784 kb
Host	smart-1e67021c-240c-458e-b5e3-4cfcb997f843
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922995405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2922995405
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.1029475692
Short name	T466
Test name
Test status
Simulation time	287446323 ps
CPU time	13.52 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:44:33 PM PDT 24
Peak memory	203516 kb
Host	smart-8008746f-3696-4bf3-b046-0290b865cc34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1029475692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1029475692
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.1426252801
Short name	T383
Test name
Test status
Simulation time	198473811 ps
CPU time	3.17 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:44:19 PM PDT 24
Peak memory	203408 kb
Host	smart-dbd924f8-1fdb-40f8-96cf-5276de8d3327
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1426252801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1426252801
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1161705233
Short name	T147
Test name
Test status
Simulation time	17745120950 ps
CPU time	41.34 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:44:50 PM PDT 24
Peak memory	203368 kb
Host	smart-ad992f1f-e4bf-47ef-a417-238ae7f1836a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161705233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1161705233
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1588911504
Short name	T61
Test name
Test status
Simulation time	3071824338 ps
CPU time	22.51 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:44:39 PM PDT 24
Peak memory	203448 kb
Host	smart-7f7a6b2d-592f-4777-bdcb-134688f60a92
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1588911504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1588911504
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1607478923
Short name	T315
Test name
Test status
Simulation time	41626731 ps
CPU time	2.17 seconds
Started	May 21 12:44:09 PM PDT 24
Finished	May 21 12:44:13 PM PDT 24
Peak memory	203456 kb
Host	smart-2f709858-7715-4709-969b-ec5e8a6a6886
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607478923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1607478923
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.2048339003
Short name	T607
Test name
Test status
Simulation time	18112539620 ps
CPU time	123.93 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:46:22 PM PDT 24
Peak memory	206844 kb
Host	smart-97d49a06-8976-413e-b75e-cd852fccf3e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048339003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2048339003
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.880181400
Short name	T3
Test name
Test status
Simulation time	3029434924 ps
CPU time	80.26 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:45:40 PM PDT 24
Peak memory	207064 kb
Host	smart-d29641b3-0c0f-4e08-b6ae-6abff1f7a3d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=880181400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.880181400
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.949473343
Short name	T719
Test name
Test status
Simulation time	555878450 ps
CPU time	84.77 seconds
Started	May 21 12:44:15 PM PDT 24
Finished	May 21 12:45:45 PM PDT 24
Peak memory	207476 kb
Host	smart-2662aa2a-80b8-4c05-906d-c8c535eea8cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=949473343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.949473343
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3884059398
Short name	T285
Test name
Test status
Simulation time	5023294368 ps
CPU time	158.16 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:46:57 PM PDT 24
Peak memory	210608 kb
Host	smart-8f69a152-1b87-4be6-a171-6e611f42fedf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3884059398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.3884059398
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3831943564
Short name	T764
Test name
Test status
Simulation time	153818677 ps
CPU time	6.87 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:25 PM PDT 24
Peak memory	204764 kb
Host	smart-943a6762-2e1f-42f8-b2cd-26b373bf793d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3831943564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3831943564
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3197891351
Short name	T749
Test name
Test status
Simulation time	583915003 ps
CPU time	24.94 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:44:42 PM PDT 24
Peak memory	205552 kb
Host	smart-d0aea529-cb9e-48ce-969a-ef4033ddd84d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3197891351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3197891351
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1085202438
Short name	T573
Test name
Test status
Simulation time	758934465 ps
CPU time	16.43 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:35 PM PDT 24
Peak memory	203632 kb
Host	smart-54aba26c-a097-4af6-b7a5-6daf69126e05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1085202438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1085202438
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.1608699904
Short name	T492
Test name
Test status
Simulation time	58515594 ps
CPU time	4.24 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:22 PM PDT 24
Peak memory	203448 kb
Host	smart-88440869-d8dc-4f21-97e8-e5f4437f5668
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1608699904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1608699904
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.1884028634
Short name	T243
Test name
Test status
Simulation time	174274552 ps
CPU time	22.95 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:41 PM PDT 24
Peak memory	204704 kb
Host	smart-96670060-6c6b-4f7b-81cf-da0d99c6f6f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1884028634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1884028634
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3098694478
Short name	T135
Test name
Test status
Simulation time	73864175211 ps
CPU time	240.41 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:48:19 PM PDT 24
Peak memory	205172 kb
Host	smart-604bf2cc-416b-4f81-bddd-d4a6ae7bc48f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098694478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3098694478
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2753161520
Short name	T687
Test name
Test status
Simulation time	38731374405 ps
CPU time	145.59 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:46:45 PM PDT 24
Peak memory	205040 kb
Host	smart-f20e1e12-76f8-4978-9de9-2be16a8a5655
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2753161520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2753161520
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3659471551
Short name	T688
Test name
Test status
Simulation time	56892866 ps
CPU time	2.88 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:44:21 PM PDT 24
Peak memory	203436 kb
Host	smart-a54f2297-a2a9-46b7-afc1-ad91de502f72
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659471551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3659471551
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.3459150395
Short name	T83
Test name
Test status
Simulation time	418935794 ps
CPU time	18.93 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:37 PM PDT 24
Peak memory	203476 kb
Host	smart-35a47119-5d7e-418c-a6ef-db1afe1c1d41
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3459150395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3459150395
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.2609026450
Short name	T678
Test name
Test status
Simulation time	243989713 ps
CPU time	3.6 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:21 PM PDT 24
Peak memory	203316 kb
Host	smart-b7706918-9290-4494-b477-045263bd6627
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2609026450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2609026450
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1185739419
Short name	T18
Test name
Test status
Simulation time	12431370046 ps
CPU time	33.08 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:44:50 PM PDT 24
Peak memory	203508 kb
Host	smart-40644ae5-6b62-4415-bda9-0322ca480228
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185739419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1185739419
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3325278415
Short name	T355
Test name
Test status
Simulation time	4881224389 ps
CPU time	23.19 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:41 PM PDT 24
Peak memory	203496 kb
Host	smart-6cee8faf-48e4-4022-bf3b-ad713c19627f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3325278415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3325278415
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.569665030
Short name	T298
Test name
Test status
Simulation time	39269548 ps
CPU time	2.39 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:20 PM PDT 24
Peak memory	203464 kb
Host	smart-f7ce46ed-5a4d-4beb-b583-f3ac51606509
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569665030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.569665030
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.3348552012
Short name	T638
Test name
Test status
Simulation time	2509379131 ps
CPU time	73.12 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:45:31 PM PDT 24
Peak memory	206668 kb
Host	smart-23f0ad7e-ddd2-4431-8892-8bd2d4405ede
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3348552012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3348552012
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.4056522537
Short name	T549
Test name
Test status
Simulation time	714489790 ps
CPU time	72.87 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:45:33 PM PDT 24
Peak memory	211660 kb
Host	smart-641ce65c-35c9-4d89-bfef-afa1a3a45864
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4056522537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4056522537
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2897471960
Short name	T204
Test name
Test status
Simulation time	9612815975 ps
CPU time	486.51 seconds
Started	May 21 12:44:12 PM PDT 24
Finished	May 21 12:52:23 PM PDT 24
Peak memory	208972 kb
Host	smart-031500ac-00be-4a27-ab6a-23b12beb2c9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2897471960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.2897471960
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.656795483
Short name	T151
Test name
Test status
Simulation time	543066279 ps
CPU time	15.68 seconds
Started	May 21 12:44:14 PM PDT 24
Finished	May 21 12:44:36 PM PDT 24
Peak memory	211652 kb
Host	smart-c85be4e0-488f-4830-a289-2f3c3c5c8d76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=656795483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.656795483
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3380442379
Short name	T433
Test name
Test status
Simulation time	219959687 ps
CPU time	24.31 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:44:49 PM PDT 24
Peak memory	204440 kb
Host	smart-97ce44ba-f31e-4ccb-86cf-ce9cb6bedfa9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3380442379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3380442379
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3539508857
Short name	T780
Test name
Test status
Simulation time	92501756304 ps
CPU time	466.3 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:52:13 PM PDT 24
Peak memory	205980 kb
Host	smart-ee755ffb-b332-4f59-affe-c4b74dd1e134
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3539508857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3539508857
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1800434322
Short name	T130
Test name
Test status
Simulation time	638192708 ps
CPU time	16.46 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:44:43 PM PDT 24
Peak memory	203832 kb
Host	smart-a3446fe7-ba68-4c5c-a0d3-d6f94156adc7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1800434322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1800434322
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.3525717922
Short name	T633
Test name
Test status
Simulation time	1899688590 ps
CPU time	31.54 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:44:56 PM PDT 24
Peak memory	203440 kb
Host	smart-c9a396bc-2baf-4720-9ddd-4e1dea601422
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3525717922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3525717922
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.2964659247
Short name	T214
Test name
Test status
Simulation time	46900880 ps
CPU time	6.63 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:44:32 PM PDT 24
Peak memory	211568 kb
Host	smart-67bfb7d5-93ce-4852-9d87-7c8ce8257258
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964659247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2964659247
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2464204549
Short name	T588
Test name
Test status
Simulation time	5737371974 ps
CPU time	35.75 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:45:02 PM PDT 24
Peak memory	204616 kb
Host	smart-4d882d44-cbb7-4449-a546-a734bf893607
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464204549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2464204549
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2205855404
Short name	T48
Test name
Test status
Simulation time	33546513550 ps
CPU time	248.96 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:48:33 PM PDT 24
Peak memory	205096 kb
Host	smart-f5bafee9-9d51-4421-aca5-2fabf7d5a426
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2205855404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2205855404
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1109026591
Short name	T516
Test name
Test status
Simulation time	93067991 ps
CPU time	12.4 seconds
Started	May 21 12:44:23 PM PDT 24
Finished	May 21 12:44:40 PM PDT 24
Peak memory	204564 kb
Host	smart-fe3997ee-fcb8-4343-899e-ae2cc00da157
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109026591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1109026591
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.3653697364
Short name	T27
Test name
Test status
Simulation time	2548172179 ps
CPU time	29.36 seconds
Started	May 21 12:44:19 PM PDT 24
Finished	May 21 12:44:54 PM PDT 24
Peak memory	204336 kb
Host	smart-dd02bcf0-be6d-4731-b022-d46d470f4d69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653697364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3653697364
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.3398879047
Short name	T886
Test name
Test status
Simulation time	273791149 ps
CPU time	3.59 seconds
Started	May 21 12:44:13 PM PDT 24
Finished	May 21 12:44:22 PM PDT 24
Peak memory	203424 kb
Host	smart-c4e8b2f9-1e07-4c26-a037-4c4ecdabab06
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3398879047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3398879047
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2197548048
Short name	T658
Test name
Test status
Simulation time	5525359893 ps
CPU time	26.92 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:44:53 PM PDT 24
Peak memory	203348 kb
Host	smart-ec5d33ca-b937-4059-b9a0-105bec4856de
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197548048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2197548048
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.225028416
Short name	T898
Test name
Test status
Simulation time	8801411829 ps
CPU time	31.06 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:44:57 PM PDT 24
Peak memory	203472 kb
Host	smart-0b7634c0-e405-4e61-a3ba-9ed5d878e33d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=225028416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.225028416
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2821045034
Short name	T338
Test name
Test status
Simulation time	32791843 ps
CPU time	2.25 seconds
Started	May 21 12:44:11 PM PDT 24
Finished	May 21 12:44:16 PM PDT 24
Peak memory	203384 kb
Host	smart-2057ec52-d5de-4e11-9e6d-f9222ff6f65d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821045034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2821045034
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.2530024726
Short name	T290
Test name
Test status
Simulation time	3101718096 ps
CPU time	120.39 seconds
Started	May 21 12:44:23 PM PDT 24
Finished	May 21 12:46:28 PM PDT 24
Peak memory	208708 kb
Host	smart-da90a6bf-64b1-4f2b-a269-db666bdb09b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2530024726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2530024726
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3940195164
Short name	T575
Test name
Test status
Simulation time	4846480631 ps
CPU time	165.42 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:47:12 PM PDT 24
Peak memory	209544 kb
Host	smart-41ecb893-6f6b-4870-99d8-d6e54cb98921
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3940195164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3940195164
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2734327203
Short name	T846
Test name
Test status
Simulation time	503394825 ps
CPU time	171.49 seconds
Started	May 21 12:44:19 PM PDT 24
Finished	May 21 12:47:15 PM PDT 24
Peak memory	210300 kb
Host	smart-6c569b6b-4052-4673-9434-a9553cbe47c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2734327203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.2734327203
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3788336750
Short name	T437
Test name
Test status
Simulation time	201260582 ps
CPU time	59.75 seconds
Started	May 21 12:44:24 PM PDT 24
Finished	May 21 12:45:28 PM PDT 24
Peak memory	208220 kb
Host	smart-7563a31b-181c-4530-a6a8-e3a0b2bfff96
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788336750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.3788336750
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2184412146
Short name	T553
Test name
Test status
Simulation time	78793155 ps
CPU time	10.15 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:44:35 PM PDT 24
Peak memory	211604 kb
Host	smart-04e6b1b2-d2e3-49b9-bbe4-9c547bb6500b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2184412146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2184412146
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.59098006
Short name	T598
Test name
Test status
Simulation time	1401195389 ps
CPU time	38.96 seconds
Started	May 21 12:44:19 PM PDT 24
Finished	May 21 12:45:02 PM PDT 24
Peak memory	205540 kb
Host	smart-41f93e57-4a32-4dde-803c-d83a3f7fc70f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=59098006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.59098006
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2101323607
Short name	T116
Test name
Test status
Simulation time	41245777343 ps
CPU time	298.61 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:49:25 PM PDT 24
Peak memory	205976 kb
Host	smart-3dadfd98-d9c2-4093-aa23-64ca05a4d66f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2101323607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.2101323607
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3250600300
Short name	T110
Test name
Test status
Simulation time	224660089 ps
CPU time	9.35 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:44:34 PM PDT 24
Peak memory	203752 kb
Host	smart-f1bcfa4f-55b2-4618-920c-7d45dfcab3f8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3250600300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3250600300
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.3030895708
Short name	T342
Test name
Test status
Simulation time	36665914 ps
CPU time	5.05 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:44:31 PM PDT 24
Peak memory	203352 kb
Host	smart-f387132e-2dc8-43d7-94f1-83160ca9a1cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3030895708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3030895708
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.2255436260
Short name	T38
Test name
Test status
Simulation time	1740773186 ps
CPU time	29.93 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:44:55 PM PDT 24
Peak memory	211604 kb
Host	smart-fcc3ca25-100a-47ef-b2d4-f087463133d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2255436260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2255436260
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3988635529
Short name	T46
Test name
Test status
Simulation time	34350782277 ps
CPU time	146.14 seconds
Started	May 21 12:44:24 PM PDT 24
Finished	May 21 12:46:54 PM PDT 24
Peak memory	205080 kb
Host	smart-31d11805-03a8-4d23-b7ff-39f287f334b0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988635529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3988635529
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1728775527
Short name	T771
Test name
Test status
Simulation time	18901574444 ps
CPU time	163.39 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:47:10 PM PDT 24
Peak memory	205128 kb
Host	smart-cfe994ff-4270-48dd-b854-458e3f36f261
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1728775527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1728775527
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.274042654
Short name	T155
Test name
Test status
Simulation time	42504072 ps
CPU time	4.3 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:44:29 PM PDT 24
Peak memory	204088 kb
Host	smart-0520a67e-6e07-4f8d-886e-aceacb849f77
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274042654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.274042654
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.2275014822
Short name	T368
Test name
Test status
Simulation time	212037295 ps
CPU time	8.51 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:44:34 PM PDT 24
Peak memory	203468 kb
Host	smart-f532ec7f-0cbd-45c3-b2a4-fb625e0d8feb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2275014822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2275014822
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.1599587809
Short name	T708
Test name
Test status
Simulation time	54814248 ps
CPU time	2.32 seconds
Started	May 21 12:44:23 PM PDT 24
Finished	May 21 12:44:29 PM PDT 24
Peak memory	203428 kb
Host	smart-985b6539-8e7a-43b9-b74b-1b46031cf050
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1599587809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1599587809
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3893797599
Short name	T85
Test name
Test status
Simulation time	16541946362 ps
CPU time	39.76 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:45:04 PM PDT 24
Peak memory	203492 kb
Host	smart-bb859fc2-09b8-4a6a-ba90-c2d0bf7d4ead
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893797599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3893797599
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2968665122
Short name	T432
Test name
Test status
Simulation time	8681833478 ps
CPU time	32.74 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:44:59 PM PDT 24
Peak memory	203412 kb
Host	smart-63ec4827-0b94-47fd-857c-32b7be876f9f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2968665122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2968665122
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2077048116
Short name	T789
Test name
Test status
Simulation time	176448174 ps
CPU time	2.43 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:44:29 PM PDT 24
Peak memory	203336 kb
Host	smart-a1b847b6-49c6-43c9-9f83-c4b9376183e8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077048116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2077048116
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.2188318799
Short name	T259
Test name
Test status
Simulation time	3916141409 ps
CPU time	115.43 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:46:22 PM PDT 24
Peak memory	205940 kb
Host	smart-42a141da-3ae1-48a0-b2b5-b8bd5655b9cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2188318799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2188318799
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2419261409
Short name	T161
Test name
Test status
Simulation time	6915687064 ps
CPU time	119.8 seconds
Started	May 21 12:44:25 PM PDT 24
Finished	May 21 12:46:28 PM PDT 24
Peak memory	205220 kb
Host	smart-d1a3aa89-31e4-44a1-8cbc-78691a707139
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419261409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2419261409
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1633147713
Short name	T208
Test name
Test status
Simulation time	4880106679 ps
CPU time	299.4 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:49:26 PM PDT 24
Peak memory	209636 kb
Host	smart-2ac5a526-f53b-4eda-8049-b7aebeabade6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1633147713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1633147713
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.940405168
Short name	T14
Test name
Test status
Simulation time	6387426684 ps
CPU time	299.28 seconds
Started	May 21 12:44:21 PM PDT 24
Finished	May 21 12:49:25 PM PDT 24
Peak memory	211688 kb
Host	smart-3259a8b6-3716-4bce-944d-339461036237
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=940405168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.940405168
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3446739295
Short name	T660
Test name
Test status
Simulation time	1410917851 ps
CPU time	31.52 seconds
Started	May 21 12:44:22 PM PDT 24
Finished	May 21 12:44:58 PM PDT 24
Peak memory	205236 kb
Host	smart-05cf8715-9b81-4779-86b5-8725656da6be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446739295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3446739295
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.634565561
Short name	T683
Test name
Test status
Simulation time	1085306052 ps
CPU time	38.66 seconds
Started	May 21 12:44:30 PM PDT 24
Finished	May 21 12:45:11 PM PDT 24
Peak memory	205520 kb
Host	smart-51f5b6b5-2931-4360-9a68-640cc8df7440
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=634565561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.634565561
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.925870286
Short name	T845
Test name
Test status
Simulation time	70073602857 ps
CPU time	516.54 seconds
Started	May 21 12:44:30 PM PDT 24
Finished	May 21 12:53:09 PM PDT 24
Peak memory	207300 kb
Host	smart-82eb1bb7-d204-4864-a3cc-7b6f0d83c5c4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=925870286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slo w_rsp.925870286
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2995476196
Short name	T860
Test name
Test status
Simulation time	1796614912 ps
CPU time	18.66 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:59 PM PDT 24
Peak memory	203900 kb
Host	smart-22d5b5b6-a6fe-4593-9fe7-7c5f4f46baee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2995476196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2995476196
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.324770989
Short name	T786
Test name
Test status
Simulation time	501020918 ps
CPU time	5.72 seconds
Started	May 21 12:44:27 PM PDT 24
Finished	May 21 12:44:36 PM PDT 24
Peak memory	203476 kb
Host	smart-b55104e2-fe86-4e2a-9fe0-d5a54fcb0e46
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=324770989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.324770989
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.2763911655
Short name	T669
Test name
Test status
Simulation time	175804390 ps
CPU time	19.2 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:44:49 PM PDT 24
Peak memory	204920 kb
Host	smart-a36f71a2-7462-482b-ae37-652a25d0cb5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2763911655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2763911655
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2302052947
Short name	T164
Test name
Test status
Simulation time	47366051139 ps
CPU time	250.39 seconds
Started	May 21 12:44:29 PM PDT 24
Finished	May 21 12:48:42 PM PDT 24
Peak memory	204876 kb
Host	smart-b4e66f79-aba4-4fd4-a374-12945cfaba35
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302052947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2302052947
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.4280813658
Short name	T347
Test name
Test status
Simulation time	23341593527 ps
CPU time	226.47 seconds
Started	May 21 12:44:28 PM PDT 24
Finished	May 21 12:48:17 PM PDT 24
Peak memory	205248 kb
Host	smart-68e2f2e3-c4c1-4916-ae35-cd34872a783e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4280813658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4280813658
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2832317106
Short name	T198
Test name
Test status
Simulation time	73788812 ps
CPU time	4.52 seconds
Started	May 21 12:44:28 PM PDT 24
Finished	May 21 12:44:36 PM PDT 24
Peak memory	204144 kb
Host	smart-e8c5d748-b0af-448b-90ad-9618991345f3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832317106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2832317106
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.2437041637
Short name	T746
Test name
Test status
Simulation time	844127657 ps
CPU time	16.3 seconds
Started	May 21 12:44:27 PM PDT 24
Finished	May 21 12:44:47 PM PDT 24
Peak memory	203672 kb
Host	smart-29932bc9-7bd1-4892-a64f-ebaa51850a5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2437041637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2437041637
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.1924360337
Short name	T495
Test name
Test status
Simulation time	35460130 ps
CPU time	2.52 seconds
Started	May 21 12:44:20 PM PDT 24
Finished	May 21 12:44:28 PM PDT 24
Peak memory	203284 kb
Host	smart-12b178af-fe26-4a6a-92fe-563b19fa80b7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1924360337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1924360337
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1818517825
Short name	T395
Test name
Test status
Simulation time	21406802411 ps
CPU time	41.13 seconds
Started	May 21 12:44:28 PM PDT 24
Finished	May 21 12:45:12 PM PDT 24
Peak memory	203492 kb
Host	smart-02eca25b-992d-4f02-a9a5-08e7c7b04ba4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818517825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1818517825
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1509159803
Short name	T701
Test name
Test status
Simulation time	8651304498 ps
CPU time	37.17 seconds
Started	May 21 12:44:28 PM PDT 24
Finished	May 21 12:45:08 PM PDT 24
Peak memory	203352 kb
Host	smart-9000743a-b6a1-45d5-8b2f-ce315edf1419
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1509159803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1509159803
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3349984975
Short name	T680
Test name
Test status
Simulation time	55853666 ps
CPU time	2.46 seconds
Started	May 21 12:44:19 PM PDT 24
Finished	May 21 12:44:27 PM PDT 24
Peak memory	203424 kb
Host	smart-40096408-ba33-48f1-bfa2-13eb2bd2f121
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349984975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3349984975
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.1632137965
Short name	T252
Test name
Test status
Simulation time	1631486400 ps
CPU time	72.45 seconds
Started	May 21 12:44:27 PM PDT 24
Finished	May 21 12:45:43 PM PDT 24
Peak memory	206292 kb
Host	smart-ea29accb-7b88-4edc-a938-8c3c0c6edd8d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1632137965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1632137965
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1542957406
Short name	T284
Test name
Test status
Simulation time	10016950611 ps
CPU time	182.51 seconds
Started	May 21 12:44:30 PM PDT 24
Finished	May 21 12:47:35 PM PDT 24
Peak memory	211668 kb
Host	smart-3cde10a8-5501-4edb-bf13-93674c065e37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1542957406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1542957406
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3462961949
Short name	T450
Test name
Test status
Simulation time	243602548 ps
CPU time	41.93 seconds
Started	May 21 12:44:29 PM PDT 24
Finished	May 21 12:45:13 PM PDT 24
Peak memory	207768 kb
Host	smart-8ef27635-a408-4f48-9543-e9f916958d38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462961949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3462961949
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1425814501
Short name	T310
Test name
Test status
Simulation time	363305246 ps
CPU time	11.95 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:44:41 PM PDT 24
Peak memory	204952 kb
Host	smart-8a461531-c48b-4944-9e26-147a22bc04ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1425814501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1425814501
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2859893835
Short name	T241
Test name
Test status
Simulation time	2869209401 ps
CPU time	22.91 seconds
Started	May 21 12:44:30 PM PDT 24
Finished	May 21 12:44:55 PM PDT 24
Peak memory	211712 kb
Host	smart-98275565-f071-4d40-bd31-556d53f0bec6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2859893835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2859893835
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.237877099
Short name	T94
Test name
Test status
Simulation time	24474616486 ps
CPU time	148.54 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:46:58 PM PDT 24
Peak memory	204924 kb
Host	smart-899a8198-94ab-437c-b08e-1d425874859a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=237877099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.237877099
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.370802546
Short name	T644
Test name
Test status
Simulation time	460577024 ps
CPU time	3.92 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:44:34 PM PDT 24
Peak memory	203424 kb
Host	smart-db650c97-a75a-48bb-ac55-2040f7524054
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=370802546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.370802546
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.1757785660
Short name	T304
Test name
Test status
Simulation time	1132294966 ps
CPU time	14.63 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:44:44 PM PDT 24
Peak memory	203432 kb
Host	smart-c700fb8e-bc2d-4f75-b128-06577b1346c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1757785660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1757785660
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.2894395886
Short name	T505
Test name
Test status
Simulation time	217708419 ps
CPU time	19.64 seconds
Started	May 21 12:44:27 PM PDT 24
Finished	May 21 12:44:50 PM PDT 24
Peak memory	211548 kb
Host	smart-7ee62878-11e4-4732-81dd-149bc7ff5466
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2894395886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2894395886
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3503705542
Short name	T881
Test name
Test status
Simulation time	61010057561 ps
CPU time	224.72 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:48:25 PM PDT 24
Peak memory	205692 kb
Host	smart-c3fe72df-fc5c-4540-be0d-bac87340f8b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503705542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3503705542
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1276317862
Short name	T584
Test name
Test status
Simulation time	18488726230 ps
CPU time	33.35 seconds
Started	May 21 12:44:27 PM PDT 24
Finished	May 21 12:45:04 PM PDT 24
Peak memory	203564 kb
Host	smart-586b0199-c3ea-469a-b204-d2b5fe58b075
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1276317862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1276317862
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4138406029
Short name	T233
Test name
Test status
Simulation time	147109314 ps
CPU time	14.66 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:44:44 PM PDT 24
Peak memory	204564 kb
Host	smart-05b94067-ac52-40cb-8895-6f1715c8833e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138406029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4138406029
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.153810508
Short name	T88
Test name
Test status
Simulation time	181212324 ps
CPU time	10.47 seconds
Started	May 21 12:44:29 PM PDT 24
Finished	May 21 12:44:42 PM PDT 24
Peak memory	203480 kb
Host	smart-81cdf19f-5b06-489b-89b2-7513b6d91c58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=153810508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.153810508
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.1292771351
Short name	T509
Test name
Test status
Simulation time	141528720 ps
CPU time	3.04 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:44:32 PM PDT 24
Peak memory	203316 kb
Host	smart-b2de7a53-cf63-4cc4-870d-fbf4780a5c6e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1292771351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1292771351
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1422809423
Short name	T408
Test name
Test status
Simulation time	18663806742 ps
CPU time	38.08 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:45:18 PM PDT 24
Peak memory	203444 kb
Host	smart-93a5d2f2-620c-439e-b1a1-0dadcb36a94e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422809423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1422809423
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3247889221
Short name	T676
Test name
Test status
Simulation time	5045392449 ps
CPU time	25.83 seconds
Started	May 21 12:44:29 PM PDT 24
Finished	May 21 12:44:58 PM PDT 24
Peak memory	203496 kb
Host	smart-29dd1bba-6fea-446a-b91d-442fe3535758
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3247889221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3247889221
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1225777789
Short name	T793
Test name
Test status
Simulation time	66579174 ps
CPU time	2.16 seconds
Started	May 21 12:44:29 PM PDT 24
Finished	May 21 12:44:34 PM PDT 24
Peak memory	203320 kb
Host	smart-2453a428-bd84-4e77-a38b-5ac078f223d5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225777789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1225777789
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.708462025
Short name	T78
Test name
Test status
Simulation time	2563583401 ps
CPU time	53.79 seconds
Started	May 21 12:44:27 PM PDT 24
Finished	May 21 12:45:24 PM PDT 24
Peak memory	206344 kb
Host	smart-3fa4e81a-ca42-409b-aaa1-5fda18eb380f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708462025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.708462025
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.95494767
Short name	T162
Test name
Test status
Simulation time	1678439631 ps
CPU time	65.18 seconds
Started	May 21 12:44:25 PM PDT 24
Finished	May 21 12:45:34 PM PDT 24
Peak memory	205924 kb
Host	smart-a9dba103-e13e-45f7-bc9c-a17fcb4d8231
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=95494767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.95494767
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3509111430
Short name	T115
Test name
Test status
Simulation time	10721608931 ps
CPU time	174.93 seconds
Started	May 21 12:44:26 PM PDT 24
Finished	May 21 12:47:25 PM PDT 24
Peak memory	209692 kb
Host	smart-67f63b43-4872-4e64-9c4c-8eba4576e5c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3509111430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3509111430
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3519358876
Short name	T26
Test name
Test status
Simulation time	1071941405 ps
CPU time	151.51 seconds
Started	May 21 12:44:27 PM PDT 24
Finished	May 21 12:47:02 PM PDT 24
Peak memory	209612 kb
Host	smart-9e27990b-e9c5-4360-9954-71b9032ea005
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3519358876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3519358876
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2061994803
Short name	T459
Test name
Test status
Simulation time	978324443 ps
CPU time	16.17 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:56 PM PDT 24
Peak memory	205084 kb
Host	smart-e31136ea-efb6-4e51-bd09-d16625039c27
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2061994803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2061994803
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.555120348
Short name	T726
Test name
Test status
Simulation time	2552596534 ps
CPU time	45.26 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:45:23 PM PDT 24
Peak memory	211568 kb
Host	smart-62bc34c4-45e9-44e6-8db7-7a7af7fc6453
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=555120348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.555120348
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3970060432
Short name	T122
Test name
Test status
Simulation time	98287218768 ps
CPU time	599.04 seconds
Started	May 21 12:44:34 PM PDT 24
Finished	May 21 12:54:35 PM PDT 24
Peak memory	207332 kb
Host	smart-2f8b22dc-7ee4-478f-95a7-fdfa0ff6557a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3970060432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3970060432
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2359723716
Short name	T884
Test name
Test status
Simulation time	375189051 ps
CPU time	4.14 seconds
Started	May 21 12:44:33 PM PDT 24
Finished	May 21 12:44:39 PM PDT 24
Peak memory	203416 kb
Host	smart-c915e1cd-7c05-4ab9-b759-c47cd4815b52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2359723716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2359723716
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.2711067308
Short name	T834
Test name
Test status
Simulation time	60288407 ps
CPU time	2.54 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:44:40 PM PDT 24
Peak memory	203324 kb
Host	smart-58f3515c-6ebd-4ad8-bd85-11547c973203
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2711067308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2711067308
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.3450582302
Short name	T39
Test name
Test status
Simulation time	871069957 ps
CPU time	17.96 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:58 PM PDT 24
Peak memory	211604 kb
Host	smart-70100218-0df0-4643-b666-3ac4d5aa4eb3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3450582302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3450582302
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1971785483
Short name	T867
Test name
Test status
Simulation time	13250376278 ps
CPU time	65.21 seconds
Started	May 21 12:44:33 PM PDT 24
Finished	May 21 12:45:40 PM PDT 24
Peak memory	204732 kb
Host	smart-7b8a7550-3124-44c8-8e65-e6ac875046b6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971785483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1971785483
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.579436564
Short name	T672
Test name
Test status
Simulation time	45396113150 ps
CPU time	189.85 seconds
Started	May 21 12:44:32 PM PDT 24
Finished	May 21 12:47:43 PM PDT 24
Peak memory	204968 kb
Host	smart-6d8476f7-e929-4dad-94d1-b934921959c6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=579436564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.579436564
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.300006754
Short name	T852
Test name
Test status
Simulation time	35611398 ps
CPU time	4.67 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:44 PM PDT 24
Peak memory	204544 kb
Host	smart-3947c4ae-0386-4340-83ef-74a4e2ed9942
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300006754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.300006754
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.3775744038
Short name	T106
Test name
Test status
Simulation time	178042200 ps
CPU time	4.77 seconds
Started	May 21 12:44:34 PM PDT 24
Finished	May 21 12:44:40 PM PDT 24
Peak memory	203628 kb
Host	smart-7c759afe-eb73-491a-b033-808c32264c87
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775744038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3775744038
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.1871823003
Short name	T682
Test name
Test status
Simulation time	48822795 ps
CPU time	2.44 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:41 PM PDT 24
Peak memory	203412 kb
Host	smart-3f3c5dfd-b00d-43c0-8cd3-e1d143db6900
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871823003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1871823003
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2905314293
Short name	T63
Test name
Test status
Simulation time	5120806278 ps
CPU time	22.97 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:45:02 PM PDT 24
Peak memory	203492 kb
Host	smart-b965e8ec-90f7-4ddf-b0f3-c8af005d1233
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905314293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2905314293
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.630963316
Short name	T140
Test name
Test status
Simulation time	8269651064 ps
CPU time	27.18 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:45:06 PM PDT 24
Peak memory	203720 kb
Host	smart-c3c3971a-49d2-4563-be09-12c813fb2a8d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=630963316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.630963316
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.705460779
Short name	T536
Test name
Test status
Simulation time	42980798 ps
CPU time	2.35 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:43 PM PDT 24
Peak memory	203420 kb
Host	smart-71950196-a0ce-4a29-bc2b-5651799cc0b4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705460779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.705460779
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.2530349821
Short name	T569
Test name
Test status
Simulation time	1858087183 ps
CPU time	34.26 seconds
Started	May 21 12:44:37 PM PDT 24
Finished	May 21 12:45:15 PM PDT 24
Peak memory	205596 kb
Host	smart-317c35c4-7c7d-4c17-a611-3823779cb18b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2530349821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2530349821
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.228683211
Short name	T260
Test name
Test status
Simulation time	5637696896 ps
CPU time	134.01 seconds
Started	May 21 12:44:34 PM PDT 24
Finished	May 21 12:46:50 PM PDT 24
Peak memory	206504 kb
Host	smart-8db094e7-4c23-4def-8d0e-706f4fadf70f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=228683211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.228683211
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3365140884
Short name	T277
Test name
Test status
Simulation time	4108536943 ps
CPU time	236.96 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:48:35 PM PDT 24
Peak memory	209424 kb
Host	smart-95aa0ddb-8086-4b47-9dd7-42edf1556dd5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3365140884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3365140884
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3617049657
Short name	T769
Test name
Test status
Simulation time	468073179 ps
CPU time	134.56 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:46:53 PM PDT 24
Peak memory	210500 kb
Host	smart-a0e27ffc-48a3-4f0e-a200-17303b43ad5e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3617049657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3617049657
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2091596094
Short name	T467
Test name
Test status
Simulation time	199020104 ps
CPU time	8.48 seconds
Started	May 21 12:44:34 PM PDT 24
Finished	May 21 12:44:43 PM PDT 24
Peak memory	204968 kb
Host	smart-d949cd09-f548-4ce6-9056-15d0c8f4be9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2091596094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2091596094
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1454966670
Short name	T75
Test name
Test status
Simulation time	1820196463 ps
CPU time	32.61 seconds
Started	May 21 12:44:44 PM PDT 24
Finished	May 21 12:45:20 PM PDT 24
Peak memory	204512 kb
Host	smart-cd2f9c67-38d9-4490-92d3-3565f345fc77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1454966670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1454966670
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2370883419
Short name	T200
Test name
Test status
Simulation time	136510288753 ps
CPU time	358.25 seconds
Started	May 21 12:44:44 PM PDT 24
Finished	May 21 12:50:46 PM PDT 24
Peak memory	206072 kb
Host	smart-fd5cdbee-6cd9-4579-b446-d3d6936cf266
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2370883419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.2370883419
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3203257845
Short name	T421
Test name
Test status
Simulation time	21376123 ps
CPU time	1.77 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:44:47 PM PDT 24
Peak memory	203388 kb
Host	smart-57d21a1c-7326-4b66-968d-26e341e53c51
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3203257845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3203257845
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.1760387223
Short name	T318
Test name
Test status
Simulation time	288726688 ps
CPU time	17.09 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:45:03 PM PDT 24
Peak memory	203444 kb
Host	smart-ed96bb8f-f377-4fde-8ad7-2afe82ec765f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1760387223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1760387223
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.2703984803
Short name	T366
Test name
Test status
Simulation time	97409761 ps
CPU time	7.91 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:44:46 PM PDT 24
Peak memory	204580 kb
Host	smart-6af86d09-6f51-445b-ae4a-73fafea852b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2703984803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2703984803
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.921810766
Short name	T895
Test name
Test status
Simulation time	78651276554 ps
CPU time	151.3 seconds
Started	May 21 12:44:34 PM PDT 24
Finished	May 21 12:47:07 PM PDT 24
Peak memory	204792 kb
Host	smart-ddaf301d-3dad-4322-844f-e7499dea6afe
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=921810766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.921810766
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3700206310
Short name	T632
Test name
Test status
Simulation time	31982748067 ps
CPU time	200.39 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:47:59 PM PDT 24
Peak memory	211564 kb
Host	smart-3c719d39-26b3-4c33-ab59-9e4e933a3d5c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3700206310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3700206310
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2506471345
Short name	T799
Test name
Test status
Simulation time	53820836 ps
CPU time	5.12 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:44:42 PM PDT 24
Peak memory	211628 kb
Host	smart-77f247f7-70aa-4b5c-a185-559fca069885
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506471345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2506471345
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.844964239
Short name	T833
Test name
Test status
Simulation time	892520136 ps
CPU time	10.51 seconds
Started	May 21 12:44:44 PM PDT 24
Finished	May 21 12:44:58 PM PDT 24
Peak memory	204072 kb
Host	smart-290185f7-5e32-4ecc-99e6-e1c16e4dc707
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=844964239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.844964239
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.1061557427
Short name	T602
Test name
Test status
Simulation time	96916994 ps
CPU time	2.37 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:43 PM PDT 24
Peak memory	203320 kb
Host	smart-d9a5252d-921b-42dc-8a53-732b16e5612c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1061557427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1061557427
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3300817405
Short name	T475
Test name
Test status
Simulation time	6287925628 ps
CPU time	27.67 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:45:06 PM PDT 24
Peak memory	203376 kb
Host	smart-4f477d74-dcbd-49d5-97da-8c66bc1c4df7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300817405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3300817405
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2350907281
Short name	T391
Test name
Test status
Simulation time	4964375413 ps
CPU time	26.98 seconds
Started	May 21 12:44:35 PM PDT 24
Finished	May 21 12:45:03 PM PDT 24
Peak memory	203480 kb
Host	smart-b70bf966-44eb-4584-8264-4085cb2a8f58
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2350907281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2350907281
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.386785581
Short name	T354
Test name
Test status
Simulation time	57995018 ps
CPU time	2.42 seconds
Started	May 21 12:44:36 PM PDT 24
Finished	May 21 12:44:41 PM PDT 24
Peak memory	203356 kb
Host	smart-61a505f6-5167-4b6f-833a-30f5743c7839
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386785581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.386785581
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.2643360429
Short name	T770
Test name
Test status
Simulation time	736216155 ps
CPU time	92.73 seconds
Started	May 21 12:44:43 PM PDT 24
Finished	May 21 12:46:19 PM PDT 24
Peak memory	205404 kb
Host	smart-136f6930-c57d-44a2-829d-fcdc25935803
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2643360429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2643360429
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1774339844
Short name	T738
Test name
Test status
Simulation time	2034768620 ps
CPU time	89.93 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:46:16 PM PDT 24
Peak memory	204964 kb
Host	smart-e201315c-b3ba-42a1-b232-015637a9380b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1774339844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1774339844
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2577981819
Short name	T36
Test name
Test status
Simulation time	90650337 ps
CPU time	17.08 seconds
Started	May 21 12:44:44 PM PDT 24
Finished	May 21 12:45:05 PM PDT 24
Peak memory	205776 kb
Host	smart-ce7e27b4-ebb5-4a69-b6b5-9841f03a7221
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2577981819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.2577981819
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1396235437
Short name	T594
Test name
Test status
Simulation time	6338985559 ps
CPU time	362.03 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:50:47 PM PDT 24
Peak memory	219920 kb
Host	smart-5ab88e1e-6f76-4af2-9891-474b394e63f8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1396235437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.1396235437
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3384375718
Short name	T819
Test name
Test status
Simulation time	188461011 ps
CPU time	13.47 seconds
Started	May 21 12:44:43 PM PDT 24
Finished	May 21 12:45:00 PM PDT 24
Peak memory	204836 kb
Host	smart-ed99d9a2-f141-43ff-98fc-502308babe6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3384375718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3384375718
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2187545154
Short name	T179
Test name
Test status
Simulation time	827556948 ps
CPU time	36.12 seconds
Started	May 21 12:44:45 PM PDT 24
Finished	May 21 12:45:25 PM PDT 24
Peak memory	211588 kb
Host	smart-2484267c-4c56-438f-b115-81e4997c855e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187545154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2187545154
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1382799647
Short name	T98
Test name
Test status
Simulation time	90921842868 ps
CPU time	496.83 seconds
Started	May 21 12:44:45 PM PDT 24
Finished	May 21 12:53:06 PM PDT 24
Peak memory	207068 kb
Host	smart-a60bce80-1a89-498a-b9e8-75661ac899ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1382799647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1382799647
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4126543505
Short name	T297
Test name
Test status
Simulation time	616235103 ps
CPU time	21.26 seconds
Started	May 21 12:44:41 PM PDT 24
Finished	May 21 12:45:07 PM PDT 24
Peak memory	204052 kb
Host	smart-85de3046-6d0c-4eea-b365-66abc4ec3340
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4126543505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4126543505
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.2515937786
Short name	T405
Test name
Test status
Simulation time	1228779840 ps
CPU time	33.23 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:45:18 PM PDT 24
Peak memory	203448 kb
Host	smart-a7d0cb12-a207-4755-a1a3-73f56907fa5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2515937786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2515937786
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.3070600993
Short name	T873
Test name
Test status
Simulation time	26626104 ps
CPU time	3.15 seconds
Started	May 21 12:44:41 PM PDT 24
Finished	May 21 12:44:49 PM PDT 24
Peak memory	203656 kb
Host	smart-661e29e8-8090-4201-a0cf-f7d7f6370d82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070600993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3070600993
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1283527526
Short name	T755
Test name
Test status
Simulation time	26489349838 ps
CPU time	104.57 seconds
Started	May 21 12:44:41 PM PDT 24
Finished	May 21 12:46:29 PM PDT 24
Peak memory	204704 kb
Host	smart-e076a879-8c66-4e28-9817-52b4c917da2d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283527526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1283527526
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2405055869
Short name	T334
Test name
Test status
Simulation time	15963931926 ps
CPU time	142.61 seconds
Started	May 21 12:44:39 PM PDT 24
Finished	May 21 12:47:04 PM PDT 24
Peak memory	204972 kb
Host	smart-53876142-c80e-4733-b02a-ef70f511a745
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2405055869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2405055869
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1112654865
Short name	T324
Test name
Test status
Simulation time	223346844 ps
CPU time	22.73 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:45:09 PM PDT 24
Peak memory	211648 kb
Host	smart-10fa1788-7ab6-4e26-984d-e4d659505409
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112654865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1112654865
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.2378454786
Short name	T470
Test name
Test status
Simulation time	1559478801 ps
CPU time	30.56 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:45:16 PM PDT 24
Peak memory	211648 kb
Host	smart-e8b53460-6a3f-4d32-8c59-a1352f7474d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2378454786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2378454786
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.3062970400
Short name	T251
Test name
Test status
Simulation time	172471333 ps
CPU time	3.17 seconds
Started	May 21 12:44:44 PM PDT 24
Finished	May 21 12:44:51 PM PDT 24
Peak memory	203424 kb
Host	smart-6dfbc744-f6c0-4055-a86b-485b99e12eac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3062970400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3062970400
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2021750051
Short name	T716
Test name
Test status
Simulation time	5759484447 ps
CPU time	30.02 seconds
Started	May 21 12:44:42 PM PDT 24
Finished	May 21 12:45:16 PM PDT 24
Peak memory	203376 kb
Host	smart-7e51a336-0383-49b4-af7e-08d2b970f5ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021750051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2021750051
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.4273461129
Short name	T878
Test name
Test status
Simulation time	3815610201 ps
CPU time	27.51 seconds
Started	May 21 12:44:43 PM PDT 24
Finished	May 21 12:45:14 PM PDT 24
Peak memory	203496 kb
Host	smart-f2c80335-04e2-4fbe-9c9d-84056f9fee3c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4273461129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.4273461129
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.4034785159
Short name	T352
Test name
Test status
Simulation time	55202056 ps
CPU time	2.49 seconds
Started	May 21 12:44:43 PM PDT 24
Finished	May 21 12:44:49 PM PDT 24
Peak memory	203412 kb
Host	smart-c86f9b1e-f397-4bd7-b370-ee67c452584e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034785159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.4034785159
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1187153550
Short name	T543
Test name
Test status
Simulation time	2492356940 ps
CPU time	125.46 seconds
Started	May 21 12:44:55 PM PDT 24
Finished	May 21 12:47:02 PM PDT 24
Peak memory	205588 kb
Host	smart-25d03740-4e41-4b5b-bc36-4c8227261a38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1187153550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1187153550
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3598328446
Short name	T190
Test name
Test status
Simulation time	671530333 ps
CPU time	173.66 seconds
Started	May 21 12:44:44 PM PDT 24
Finished	May 21 12:47:42 PM PDT 24
Peak memory	208552 kb
Host	smart-ffccc93a-202b-408e-8eda-6a07bc935239
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3598328446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.3598328446
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.4215808104
Short name	T787
Test name
Test status
Simulation time	984924692 ps
CPU time	174.88 seconds
Started	May 21 12:44:48 PM PDT 24
Finished	May 21 12:47:47 PM PDT 24
Peak memory	211216 kb
Host	smart-5a1437bb-d73b-4c07-be55-b90b592c971b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4215808104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.4215808104
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.686321518
Short name	T73
Test name
Test status
Simulation time	595835363 ps
CPU time	15.1 seconds
Started	May 21 12:44:43 PM PDT 24
Finished	May 21 12:45:02 PM PDT 24
Peak memory	205052 kb
Host	smart-6b30a668-0d49-41fe-aee1-a722789d0016
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686321518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.686321518
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.4290664200
Short name	T497
Test name
Test status
Simulation time	444162672 ps
CPU time	14.71 seconds
Started	May 21 12:43:27 PM PDT 24
Finished	May 21 12:43:44 PM PDT 24
Peak memory	204480 kb
Host	smart-18c15d73-a9ac-469c-b143-9fa898f5e944
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4290664200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.4290664200
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3907191627
Short name	T554
Test name
Test status
Simulation time	277923716381 ps
CPU time	805.52 seconds
Started	May 21 12:43:22 PM PDT 24
Finished	May 21 12:56:49 PM PDT 24
Peak memory	207672 kb
Host	smart-e10b0a53-ee76-45d6-b0a8-43489ec862ee
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3907191627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3907191627
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2120053787
Short name	T441
Test name
Test status
Simulation time	463632073 ps
CPU time	13.27 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:41 PM PDT 24
Peak memory	203584 kb
Host	smart-d64c1559-2236-4da0-8800-84def173de80
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2120053787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2120053787
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.969723618
Short name	T530
Test name
Test status
Simulation time	2235252701 ps
CPU time	20.01 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:47 PM PDT 24
Peak memory	203512 kb
Host	smart-ec43769e-594c-4448-ad36-41866a5ce753
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=969723618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.969723618
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.3034304997
Short name	T715
Test name
Test status
Simulation time	81572658 ps
CPU time	8.09 seconds
Started	May 21 12:43:22 PM PDT 24
Finished	May 21 12:43:32 PM PDT 24
Peak memory	204568 kb
Host	smart-75ac5ce3-a593-4f53-90d3-1f262c859d53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034304997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3034304997
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1033078225
Short name	T714
Test name
Test status
Simulation time	3783797211 ps
CPU time	15.78 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:43:44 PM PDT 24
Peak memory	203508 kb
Host	smart-90f2a3fd-7571-4d26-a690-45ef50e6bf46
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033078225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1033078225
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1379527599
Short name	T773
Test name
Test status
Simulation time	1398565775 ps
CPU time	11.07 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:38 PM PDT 24
Peak memory	203468 kb
Host	smart-fcf972f5-225b-4a86-8991-3fd344b96c54
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1379527599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1379527599
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3066726995
Short name	T496
Test name
Test status
Simulation time	14838924 ps
CPU time	1.97 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:43:31 PM PDT 24
Peak memory	203472 kb
Host	smart-3d51fab4-8302-4727-8e62-b2c0fe1ae79c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066726995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3066726995
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.1447684743
Short name	T138
Test name
Test status
Simulation time	1459419979 ps
CPU time	7.66 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:43:36 PM PDT 24
Peak memory	203448 kb
Host	smart-0e6c5e38-48ad-49a9-8b32-0f8720fdb4c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1447684743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1447684743
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.716377487
Short name	T163
Test name
Test status
Simulation time	90959596 ps
CPU time	2.07 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:30 PM PDT 24
Peak memory	203664 kb
Host	smart-556578fd-d104-45e3-80bc-39b70c0d7a55
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=716377487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.716377487
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3491564049
Short name	T326
Test name
Test status
Simulation time	6221240067 ps
CPU time	25.6 seconds
Started	May 21 12:43:24 PM PDT 24
Finished	May 21 12:43:53 PM PDT 24
Peak memory	203488 kb
Host	smart-721c9815-6654-4026-949b-9e84c76bf1a9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491564049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3491564049
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2805596564
Short name	T487
Test name
Test status
Simulation time	14886590786 ps
CPU time	34.46 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:44:03 PM PDT 24
Peak memory	203488 kb
Host	smart-809fda5a-b501-45cf-8ec5-c4bac71269a8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2805596564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2805596564
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.971615242
Short name	T582
Test name
Test status
Simulation time	69442640 ps
CPU time	2.66 seconds
Started	May 21 12:43:26 PM PDT 24
Finished	May 21 12:43:32 PM PDT 24
Peak memory	203412 kb
Host	smart-3ed493a5-5b75-422b-bae5-f48111fcb3b6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971615242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.971615242
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.4061675548
Short name	T346
Test name
Test status
Simulation time	229737280 ps
CPU time	28.18 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:44:02 PM PDT 24
Peak memory	211516 kb
Host	smart-da779a2f-ee76-4216-90ad-bfb642de26b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4061675548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4061675548
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3334195582
Short name	T396
Test name
Test status
Simulation time	17447849474 ps
CPU time	143.41 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:45:58 PM PDT 24
Peak memory	211968 kb
Host	smart-988c1085-ba63-479f-a053-0184b0d9e35d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3334195582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3334195582
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1668669663
Short name	T343
Test name
Test status
Simulation time	43753057 ps
CPU time	16.91 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:43:51 PM PDT 24
Peak memory	205892 kb
Host	smart-ad5254e1-5816-4b66-8c38-a51793eb95e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1668669663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.1668669663
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1536797865
Short name	T349
Test name
Test status
Simulation time	375874908 ps
CPU time	129.71 seconds
Started	May 21 12:43:30 PM PDT 24
Finished	May 21 12:45:43 PM PDT 24
Peak memory	210552 kb
Host	smart-c7b9ad2d-58f7-4e76-8324-a64277bbc843
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1536797865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.1536797865
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.4059210289
Short name	T890
Test name
Test status
Simulation time	1164055333 ps
CPU time	31.87 seconds
Started	May 21 12:43:25 PM PDT 24
Finished	May 21 12:44:00 PM PDT 24
Peak memory	211588 kb
Host	smart-62db2e50-4176-4de7-9534-d13a3744d236
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4059210289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4059210289
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.51708549
Short name	T525
Test name
Test status
Simulation time	2333592008 ps
CPU time	22.72 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:45:15 PM PDT 24
Peak memory	204540 kb
Host	smart-20c424e1-8325-4290-b61f-da7bbe504b7a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=51708549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.51708549
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2139796042
Short name	T550
Test name
Test status
Simulation time	41781387435 ps
CPU time	397.91 seconds
Started	May 21 12:44:48 PM PDT 24
Finished	May 21 12:51:30 PM PDT 24
Peak memory	211704 kb
Host	smart-808a5a4c-4865-4a31-a622-6486080a1a68
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2139796042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2139796042
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3106326215
Short name	T480
Test name
Test status
Simulation time	351305095 ps
CPU time	16.8 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:45:09 PM PDT 24
Peak memory	203972 kb
Host	smart-7e0fa9cf-27b8-4c40-af1a-6fba25bea178
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3106326215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3106326215
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.293019107
Short name	T654
Test name
Test status
Simulation time	2392927664 ps
CPU time	34.83 seconds
Started	May 21 12:44:52 PM PDT 24
Finished	May 21 12:45:30 PM PDT 24
Peak memory	203492 kb
Host	smart-211d894b-11eb-49aa-91ef-158c42883829
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=293019107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.293019107
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.1415405328
Short name	T416
Test name
Test status
Simulation time	104810132 ps
CPU time	5.93 seconds
Started	May 21 12:44:51 PM PDT 24
Finished	May 21 12:45:00 PM PDT 24
Peak memory	211612 kb
Host	smart-5f7fe4c7-52bf-4262-bba8-48c2489fda23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1415405328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1415405328
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2940635781
Short name	T113
Test name
Test status
Simulation time	11351278966 ps
CPU time	56.76 seconds
Started	May 21 12:44:51 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	211696 kb
Host	smart-995ca5ca-8645-41a9-90ea-6e17c3a4660e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940635781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2940635781
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1541645179
Short name	T413
Test name
Test status
Simulation time	31202858133 ps
CPU time	142.49 seconds
Started	May 21 12:44:48 PM PDT 24
Finished	May 21 12:47:15 PM PDT 24
Peak memory	204744 kb
Host	smart-47546916-d089-4475-9635-722d991633b5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1541645179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1541645179
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.930960894
Short name	T679
Test name
Test status
Simulation time	219446093 ps
CPU time	17.68 seconds
Started	May 21 12:44:48 PM PDT 24
Finished	May 21 12:45:10 PM PDT 24
Peak memory	211600 kb
Host	smart-5c4a54dd-ff42-4920-88fe-b9b89a811d1f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930960894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.930960894
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.3141945829
Short name	T759
Test name
Test status
Simulation time	25136227 ps
CPU time	2.02 seconds
Started	May 21 12:44:53 PM PDT 24
Finished	May 21 12:44:57 PM PDT 24
Peak memory	203428 kb
Host	smart-f023048d-3d53-4d0d-a6e9-b2e14d88756b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3141945829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3141945829
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.1006474868
Short name	T244
Test name
Test status
Simulation time	198274972 ps
CPU time	3.68 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:44:57 PM PDT 24
Peak memory	203428 kb
Host	smart-55530762-e402-42c0-9871-a95b0e288ee0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1006474868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1006474868
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.625668449
Short name	T521
Test name
Test status
Simulation time	5769081267 ps
CPU time	28.99 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:45:22 PM PDT 24
Peak memory	203456 kb
Host	smart-4b04a844-00e4-4031-abf6-f164fde6ccde
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=625668449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.625668449
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.4064194826
Short name	T540
Test name
Test status
Simulation time	7991557060 ps
CPU time	24.4 seconds
Started	May 21 12:44:48 PM PDT 24
Finished	May 21 12:45:17 PM PDT 24
Peak memory	203392 kb
Host	smart-6f2e400d-c107-4cee-9f36-232848febe1a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4064194826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.4064194826
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.968009643
Short name	T359
Test name
Test status
Simulation time	43637457 ps
CPU time	2.23 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:44:55 PM PDT 24
Peak memory	203440 kb
Host	smart-eac2c967-99a2-4901-865e-7ce9a1d9bab8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968009643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.968009643
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.2356597334
Short name	T120
Test name
Test status
Simulation time	3008114200 ps
CPU time	113.55 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:46:47 PM PDT 24
Peak memory	208388 kb
Host	smart-bdbdcf5b-fced-4890-82b5-7c5c18dadc50
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2356597334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2356597334
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.269710254
Short name	T375
Test name
Test status
Simulation time	1273278521 ps
CPU time	105.19 seconds
Started	May 21 12:44:48 PM PDT 24
Finished	May 21 12:46:37 PM PDT 24
Peak memory	207620 kb
Host	smart-b3f86fb2-de4d-46b2-9103-ed61e8e76c6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=269710254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.269710254
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2953958000
Short name	T137
Test name
Test status
Simulation time	5626637869 ps
CPU time	250.56 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:49:04 PM PDT 24
Peak memory	219892 kb
Host	smart-4e5a8a2b-088b-4f60-bd5f-4d20c29d3263
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2953958000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2953958000
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1966008474
Short name	T247
Test name
Test status
Simulation time	29153168 ps
CPU time	1.96 seconds
Started	May 21 12:44:50 PM PDT 24
Finished	May 21 12:44:55 PM PDT 24
Peak memory	203456 kb
Host	smart-f0ce02ef-c7e0-44e9-a9b1-798e4175f83e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1966008474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1966008474
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.371197472
Short name	T62
Test name
Test status
Simulation time	1067910219 ps
CPU time	17.47 seconds
Started	May 21 12:44:50 PM PDT 24
Finished	May 21 12:45:11 PM PDT 24
Peak memory	204724 kb
Host	smart-8bfb5915-b0be-4606-a6af-c698a69f08c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371197472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.371197472
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2510954747
Short name	T114
Test name
Test status
Simulation time	24935095960 ps
CPU time	226.77 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:48:50 PM PDT 24
Peak memory	205996 kb
Host	smart-478a1d91-5202-4979-a5e9-4b6a3b57d056
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2510954747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.2510954747
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2458585128
Short name	T776
Test name
Test status
Simulation time	1116010965 ps
CPU time	11.89 seconds
Started	May 21 12:44:58 PM PDT 24
Finished	May 21 12:45:11 PM PDT 24
Peak memory	203520 kb
Host	smart-8a26f9cd-2392-4c3f-a9a0-05d5f86fbc5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2458585128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2458585128
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.1983521546
Short name	T775
Test name
Test status
Simulation time	258152827 ps
CPU time	11.03 seconds
Started	May 21 12:45:01 PM PDT 24
Finished	May 21 12:45:15 PM PDT 24
Peak memory	203420 kb
Host	smart-b79425ef-3035-46c2-9d95-425d1a29a1cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1983521546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1983521546
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.685058464
Short name	T165
Test name
Test status
Simulation time	895206956 ps
CPU time	23.44 seconds
Started	May 21 12:44:51 PM PDT 24
Finished	May 21 12:45:18 PM PDT 24
Peak memory	204612 kb
Host	smart-38a5b2cd-2550-4062-b0ad-be351976c31a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=685058464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.685058464
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2193966887
Short name	T609
Test name
Test status
Simulation time	77672575280 ps
CPU time	140.61 seconds
Started	May 21 12:44:52 PM PDT 24
Finished	May 21 12:47:15 PM PDT 24
Peak memory	204620 kb
Host	smart-f3810d3a-a529-4691-8c60-90c1ba890050
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193966887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2193966887
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3686492019
Short name	T446
Test name
Test status
Simulation time	14713622166 ps
CPU time	118.85 seconds
Started	May 21 12:44:51 PM PDT 24
Finished	May 21 12:46:53 PM PDT 24
Peak memory	204776 kb
Host	smart-c489838c-3034-4955-8603-183948bc70f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3686492019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3686492019
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.814909194
Short name	T557
Test name
Test status
Simulation time	120953537 ps
CPU time	13.41 seconds
Started	May 21 12:44:53 PM PDT 24
Finished	May 21 12:45:09 PM PDT 24
Peak memory	211532 kb
Host	smart-7cb417dc-cb5a-40a5-b6e3-f2fe3a664496
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814909194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.814909194
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.3579548421
Short name	T194
Test name
Test status
Simulation time	1322905432 ps
CPU time	14.27 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:45:18 PM PDT 24
Peak memory	204064 kb
Host	smart-5bb5f2ba-9599-4975-b28f-2f013af160fe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3579548421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3579548421
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.204506219
Short name	T642
Test name
Test status
Simulation time	165653080 ps
CPU time	4.15 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:44:57 PM PDT 24
Peak memory	203340 kb
Host	smart-89cc75e2-c071-4a31-a4b1-13b32b107d07
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=204506219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.204506219
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3808961171
Short name	T172
Test name
Test status
Simulation time	5879905186 ps
CPU time	33.24 seconds
Started	May 21 12:44:51 PM PDT 24
Finished	May 21 12:45:27 PM PDT 24
Peak memory	203496 kb
Host	smart-7ecd8a98-0319-44ba-9753-e10a937083dd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808961171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3808961171
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.464261530
Short name	T139
Test name
Test status
Simulation time	4291499262 ps
CPU time	30.47 seconds
Started	May 21 12:44:49 PM PDT 24
Finished	May 21 12:45:24 PM PDT 24
Peak memory	203472 kb
Host	smart-7a97b74f-8cd2-4e3e-b78e-428286bbcda2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=464261530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.464261530
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2091049463
Short name	T656
Test name
Test status
Simulation time	49046663 ps
CPU time	2.32 seconds
Started	May 21 12:44:48 PM PDT 24
Finished	May 21 12:44:55 PM PDT 24
Peak memory	203424 kb
Host	smart-d5327d01-7868-4fa7-869f-c7b9b7cf7cd1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091049463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2091049463
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.666892777
Short name	T201
Test name
Test status
Simulation time	6395039553 ps
CPU time	136.7 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:47:20 PM PDT 24
Peak memory	207672 kb
Host	smart-c1a30e36-1cbe-4916-b172-4bbd993ca38c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=666892777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.666892777
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1999174029
Short name	T381
Test name
Test status
Simulation time	8582616078 ps
CPU time	250.2 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:49:13 PM PDT 24
Peak memory	207368 kb
Host	smart-2a16a788-a9f7-40f1-9fb0-228f67ffc110
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1999174029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1999174029
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.4210589704
Short name	T435
Test name
Test status
Simulation time	280400155 ps
CPU time	59.38 seconds
Started	May 21 12:44:57 PM PDT 24
Finished	May 21 12:45:57 PM PDT 24
Peak memory	208020 kb
Host	smart-deb0abac-c91f-4ebd-91e1-8c854b442028
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4210589704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.4210589704
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2961093467
Short name	T424
Test name
Test status
Simulation time	5131803780 ps
CPU time	642.03 seconds
Started	May 21 12:45:02 PM PDT 24
Finished	May 21 12:55:47 PM PDT 24
Peak memory	226532 kb
Host	smart-0fc1252f-a9de-4d49-aea2-688bc2616f9d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2961093467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.2961093467
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2149311504
Short name	T13
Test name
Test status
Simulation time	180893113 ps
CPU time	11.46 seconds
Started	May 21 12:45:04 PM PDT 24
Finished	May 21 12:45:18 PM PDT 24
Peak memory	205020 kb
Host	smart-377899b3-dbf6-470b-bb6b-b82675735deb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149311504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2149311504
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3551132387
Short name	T111
Test name
Test status
Simulation time	3949216627 ps
CPU time	51.64 seconds
Started	May 21 12:44:59 PM PDT 24
Finished	May 21 12:45:53 PM PDT 24
Peak memory	204576 kb
Host	smart-2a78e79d-5e96-4df6-9afa-f08fca0fbf41
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3551132387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3551132387
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3649230670
Short name	T677
Test name
Test status
Simulation time	64145527051 ps
CPU time	392.92 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:51:36 PM PDT 24
Peak memory	211572 kb
Host	smart-6254bfe9-185c-4be8-9220-bf3d01a42e87
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3649230670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.3649230670
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3877876118
Short name	T804
Test name
Test status
Simulation time	1865977279 ps
CPU time	20.39 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:45:23 PM PDT 24
Peak memory	204088 kb
Host	smart-7d79a787-aa83-4209-9a8a-1e7ba4c2129e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3877876118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3877876118
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.3694955615
Short name	T668
Test name
Test status
Simulation time	125734523 ps
CPU time	2.51 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:45:06 PM PDT 24
Peak memory	203472 kb
Host	smart-5ceedd84-84bc-433b-94be-214bb3e714a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3694955615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3694955615
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.4011723492
Short name	T527
Test name
Test status
Simulation time	1070386048 ps
CPU time	24.25 seconds
Started	May 21 12:45:01 PM PDT 24
Finished	May 21 12:45:28 PM PDT 24
Peak memory	204580 kb
Host	smart-b34e68be-7377-454e-9c4f-9e7d567b76ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4011723492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.4011723492
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1881228435
Short name	T774
Test name
Test status
Simulation time	40145856362 ps
CPU time	170.94 seconds
Started	May 21 12:44:59 PM PDT 24
Finished	May 21 12:47:53 PM PDT 24
Peak memory	205272 kb
Host	smart-ec1c94b0-878c-4c61-99a3-3866b8909f73
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881228435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1881228435
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3310743005
Short name	T847
Test name
Test status
Simulation time	33114162279 ps
CPU time	70.94 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:46:13 PM PDT 24
Peak memory	204652 kb
Host	smart-967db42d-f8a4-46f9-adfb-3ff30f153800
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3310743005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3310743005
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.581745621
Short name	T666
Test name
Test status
Simulation time	75344771 ps
CPU time	10.27 seconds
Started	May 21 12:45:01 PM PDT 24
Finished	May 21 12:45:14 PM PDT 24
Peak memory	204560 kb
Host	smart-482a9f7c-b30a-4039-a09f-3cc0c8a3ab5d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581745621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.581745621
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.1254188073
Short name	T258
Test name
Test status
Simulation time	637727159 ps
CPU time	15.12 seconds
Started	May 21 12:44:58 PM PDT 24
Finished	May 21 12:45:14 PM PDT 24
Peak memory	203952 kb
Host	smart-831a4988-6a16-447d-a9ae-d98e67f7d7e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1254188073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1254188073
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.2124277308
Short name	T180
Test name
Test status
Simulation time	116047187 ps
CPU time	3.05 seconds
Started	May 21 12:44:57 PM PDT 24
Finished	May 21 12:45:01 PM PDT 24
Peak memory	203424 kb
Host	smart-f9a3b964-c26e-4d71-b37c-940e5721c13b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2124277308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2124277308
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2997609676
Short name	T316
Test name
Test status
Simulation time	5489818194 ps
CPU time	30.23 seconds
Started	May 21 12:44:58 PM PDT 24
Finished	May 21 12:45:29 PM PDT 24
Peak memory	203476 kb
Host	smart-b9c97b44-f3fd-4129-9fb7-8eeb2df861b4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997609676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2997609676
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3523868724
Short name	T752
Test name
Test status
Simulation time	3747974423 ps
CPU time	32.83 seconds
Started	May 21 12:44:59 PM PDT 24
Finished	May 21 12:45:34 PM PDT 24
Peak memory	203520 kb
Host	smart-d94e516c-9d68-4559-9337-981a3adfe73d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3523868724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3523868724
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1160700988
Short name	T218
Test name
Test status
Simulation time	29718163 ps
CPU time	2.09 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:45:06 PM PDT 24
Peak memory	203296 kb
Host	smart-84819e68-be2a-48cc-a02a-c84b836d466b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160700988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1160700988
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.2241558919
Short name	T859
Test name
Test status
Simulation time	15864005680 ps
CPU time	103.47 seconds
Started	May 21 12:44:59 PM PDT 24
Finished	May 21 12:46:44 PM PDT 24
Peak memory	211712 kb
Host	smart-84d082df-0799-48ef-8630-adaf55a27c4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2241558919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2241558919
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3167786521
Short name	T537
Test name
Test status
Simulation time	14870831352 ps
CPU time	191.73 seconds
Started	May 21 12:44:59 PM PDT 24
Finished	May 21 12:48:11 PM PDT 24
Peak memory	210120 kb
Host	smart-13e798d0-affc-42b6-b78f-5b37099a9c24
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3167786521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3167786521
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3355953384
Short name	T266
Test name
Test status
Simulation time	3064564326 ps
CPU time	171.96 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:47:55 PM PDT 24
Peak memory	209540 kb
Host	smart-b12182d7-05e2-48a1-a056-a666866ac7d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3355953384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3355953384
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.312031469
Short name	T721
Test name
Test status
Simulation time	2360189021 ps
CPU time	329.32 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:50:33 PM PDT 24
Peak memory	211724 kb
Host	smart-fd15e5d7-bedb-48c4-b5bf-e2a6f92105ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=312031469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res et_error.312031469
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.337298048
Short name	T239
Test name
Test status
Simulation time	170284483 ps
CPU time	14.99 seconds
Started	May 21 12:45:01 PM PDT 24
Finished	May 21 12:45:19 PM PDT 24
Peak memory	205136 kb
Host	smart-c0147bbf-30c5-4393-9aee-ff2ba2e00197
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=337298048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.337298048
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2749388521
Short name	T123
Test name
Test status
Simulation time	215913777 ps
CPU time	30.69 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:45:46 PM PDT 24
Peak memory	211600 kb
Host	smart-7ad289d8-d66a-4c55-9c27-d17de971b626
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2749388521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2749388521
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1014071180
Short name	T765
Test name
Test status
Simulation time	114419222 ps
CPU time	11 seconds
Started	May 21 12:45:04 PM PDT 24
Finished	May 21 12:45:18 PM PDT 24
Peak memory	203448 kb
Host	smart-8f8b1f80-113d-49f9-93e9-4ae822ebd3de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1014071180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1014071180
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.4005834161
Short name	T333
Test name
Test status
Simulation time	1022453882 ps
CPU time	29.57 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:45:42 PM PDT 24
Peak memory	203452 kb
Host	smart-a520292c-63f7-4f49-a207-001062a7dbdd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4005834161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.4005834161
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.475854716
Short name	T51
Test name
Test status
Simulation time	399160272 ps
CPU time	19.14 seconds
Started	May 21 12:45:01 PM PDT 24
Finished	May 21 12:45:23 PM PDT 24
Peak memory	211580 kb
Host	smart-31f74679-fe91-4399-b671-64c069d4a7a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=475854716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.475854716
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.323290526
Short name	T864
Test name
Test status
Simulation time	81007574882 ps
CPU time	132.41 seconds
Started	May 21 12:45:04 PM PDT 24
Finished	May 21 12:47:19 PM PDT 24
Peak memory	204788 kb
Host	smart-8e132971-ff6d-4957-928b-d7dbbc4c7c43
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=323290526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.323290526
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2594339842
Short name	T753
Test name
Test status
Simulation time	12168775380 ps
CPU time	123.49 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:47:18 PM PDT 24
Peak memory	205024 kb
Host	smart-5b9b8d48-ad1e-4e71-aab5-1cd1e5ef9c9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2594339842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2594339842
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1550414784
Short name	T900
Test name
Test status
Simulation time	229350809 ps
CPU time	10.04 seconds
Started	May 21 12:45:01 PM PDT 24
Finished	May 21 12:45:14 PM PDT 24
Peak memory	211608 kb
Host	smart-e0f9e66a-ac63-4f1b-b80a-5943ee33e1f6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550414784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1550414784
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.4202130882
Short name	T830
Test name
Test status
Simulation time	851180298 ps
CPU time	10.41 seconds
Started	May 21 12:45:03 PM PDT 24
Finished	May 21 12:45:16 PM PDT 24
Peak memory	204008 kb
Host	smart-884e7e37-1bf3-4344-a71a-ec625030e610
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4202130882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4202130882
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.495588333
Short name	T483
Test name
Test status
Simulation time	349645457 ps
CPU time	3.52 seconds
Started	May 21 12:44:57 PM PDT 24
Finished	May 21 12:45:01 PM PDT 24
Peak memory	203400 kb
Host	smart-db20a7b4-865a-4446-acd5-36cda5e7e112
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=495588333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.495588333
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1476954990
Short name	T599
Test name
Test status
Simulation time	10726925767 ps
CPU time	30.16 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:45:33 PM PDT 24
Peak memory	203476 kb
Host	smart-e642349b-27cf-4c1d-bcd7-528e1f532eeb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476954990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1476954990
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2134861868
Short name	T866
Test name
Test status
Simulation time	2883387433 ps
CPU time	28.11 seconds
Started	May 21 12:45:00 PM PDT 24
Finished	May 21 12:45:31 PM PDT 24
Peak memory	203488 kb
Host	smart-df02788d-b105-4550-a0a2-ba1a0dee8eba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2134861868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2134861868
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3199271955
Short name	T499
Test name
Test status
Simulation time	24291851 ps
CPU time	2.01 seconds
Started	May 21 12:44:59 PM PDT 24
Finished	May 21 12:45:02 PM PDT 24
Peak memory	203436 kb
Host	smart-fc34d26f-9255-4f07-863f-2c264cce86c0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199271955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3199271955
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.354192128
Short name	T76
Test name
Test status
Simulation time	4299718621 ps
CPU time	146.89 seconds
Started	May 21 12:45:08 PM PDT 24
Finished	May 21 12:47:43 PM PDT 24
Peak memory	209468 kb
Host	smart-48293bc9-8e16-48e1-8db6-90b607776527
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=354192128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.354192128
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2283608673
Short name	T561
Test name
Test status
Simulation time	3242629759 ps
CPU time	85.01 seconds
Started	May 21 12:45:08 PM PDT 24
Finished	May 21 12:46:43 PM PDT 24
Peak memory	207136 kb
Host	smart-bbdc5a7d-21fa-41de-957c-c98d40addffa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2283608673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2283608673
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3702226062
Short name	T228
Test name
Test status
Simulation time	2165289532 ps
CPU time	224.43 seconds
Started	May 21 12:45:09 PM PDT 24
Finished	May 21 12:49:04 PM PDT 24
Peak memory	208820 kb
Host	smart-b72abb2b-373e-415b-a13e-a8fb5a939b81
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3702226062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3702226062
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.500872358
Short name	T269
Test name
Test status
Simulation time	614627801 ps
CPU time	166.65 seconds
Started	May 21 12:45:06 PM PDT 24
Finished	May 21 12:47:58 PM PDT 24
Peak memory	211656 kb
Host	smart-41f6dac2-f746-46c4-bd2d-18e94d01f425
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=500872358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.500872358
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2528200582
Short name	T462
Test name
Test status
Simulation time	1015049666 ps
CPU time	29.55 seconds
Started	May 21 12:45:05 PM PDT 24
Finished	May 21 12:45:37 PM PDT 24
Peak memory	204840 kb
Host	smart-43f569c9-244a-4119-bacd-00bb49ba9848
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2528200582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2528200582
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3405511384
Short name	T336
Test name
Test status
Simulation time	642833845 ps
CPU time	35.72 seconds
Started	May 21 12:45:09 PM PDT 24
Finished	May 21 12:45:55 PM PDT 24
Peak memory	211600 kb
Host	smart-e5a40587-bc81-4aa5-88c5-aaa4bf21d912
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3405511384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3405511384
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.663645349
Short name	T547
Test name
Test status
Simulation time	24542877529 ps
CPU time	141.93 seconds
Started	May 21 12:45:08 PM PDT 24
Finished	May 21 12:47:38 PM PDT 24
Peak memory	205236 kb
Host	smart-20a0ea73-2edb-4d9b-b396-3982494274ad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=663645349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.663645349
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.612600029
Short name	T645
Test name
Test status
Simulation time	105883005 ps
CPU time	7.93 seconds
Started	May 21 12:45:09 PM PDT 24
Finished	May 21 12:45:27 PM PDT 24
Peak memory	203732 kb
Host	smart-a46a5fd5-4aed-4815-93ba-10e4403b33a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=612600029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.612600029
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.405734239
Short name	T294
Test name
Test status
Simulation time	89329624 ps
CPU time	10.53 seconds
Started	May 21 12:45:08 PM PDT 24
Finished	May 21 12:45:26 PM PDT 24
Peak memory	203432 kb
Host	smart-820b65fd-3ab1-4055-bf60-f2c807e1f236
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=405734239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.405734239
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.1854610498
Short name	T610
Test name
Test status
Simulation time	262336093 ps
CPU time	20.79 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:45:43 PM PDT 24
Peak memory	204576 kb
Host	smart-35788199-0220-42e2-820e-314bc7b37d56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854610498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1854610498
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3724402169
Short name	T426
Test name
Test status
Simulation time	20704128973 ps
CPU time	71.94 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:46:26 PM PDT 24
Peak memory	204948 kb
Host	smart-11ad4ddc-1016-4b3a-996a-dd1a0f7ceb4b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724402169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3724402169
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1867443460
Short name	T255
Test name
Test status
Simulation time	2860545568 ps
CPU time	17.65 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:45:31 PM PDT 24
Peak memory	203512 kb
Host	smart-7933c2da-3dba-43b9-be7b-5b20edbf82b6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1867443460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1867443460
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2601317536
Short name	T410
Test name
Test status
Simulation time	607936056 ps
CPU time	23.87 seconds
Started	May 21 12:45:09 PM PDT 24
Finished	May 21 12:45:43 PM PDT 24
Peak memory	211432 kb
Host	smart-4060269e-7305-4e42-a193-b7b137a2d99a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601317536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2601317536
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.2100721859
Short name	T727
Test name
Test status
Simulation time	751056802 ps
CPU time	11.7 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:45:27 PM PDT 24
Peak memory	203936 kb
Host	smart-54a3de75-92f3-4643-a80f-6099f1d60470
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100721859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2100721859
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.554904372
Short name	T618
Test name
Test status
Simulation time	437983543 ps
CPU time	3.85 seconds
Started	May 21 12:45:09 PM PDT 24
Finished	May 21 12:45:23 PM PDT 24
Peak memory	203412 kb
Host	smart-903f1c1d-9653-435e-a358-021ba26cf7bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=554904372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.554904372
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3065221012
Short name	T339
Test name
Test status
Simulation time	12312294819 ps
CPU time	29.88 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:45:52 PM PDT 24
Peak memory	203356 kb
Host	smart-cb5e822e-e4c5-44a3-b30d-24da61fb270e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065221012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3065221012
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3014570315
Short name	T836
Test name
Test status
Simulation time	4037242041 ps
CPU time	28.6 seconds
Started	May 21 12:45:06 PM PDT 24
Finished	May 21 12:45:39 PM PDT 24
Peak memory	203496 kb
Host	smart-60ca06a2-5989-47e5-9741-dbb1b267f9aa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3014570315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3014570315
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2502270616
Short name	T197
Test name
Test status
Simulation time	37306389 ps
CPU time	2.3 seconds
Started	May 21 12:45:08 PM PDT 24
Finished	May 21 12:45:21 PM PDT 24
Peak memory	203336 kb
Host	smart-1f199e18-d78c-4191-bf97-2cf27c0479f2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502270616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2502270616
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.2834808260
Short name	T374
Test name
Test status
Simulation time	19645757625 ps
CPU time	198.98 seconds
Started	May 21 12:45:09 PM PDT 24
Finished	May 21 12:48:38 PM PDT 24
Peak memory	206908 kb
Host	smart-775870ac-1cac-459d-85fd-0a5cbfb884fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834808260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2834808260
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.81990882
Short name	T220
Test name
Test status
Simulation time	3327893741 ps
CPU time	55.22 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:46:07 PM PDT 24
Peak memory	205000 kb
Host	smart-535b42d7-bb4b-4ae0-9ff2-abcb80834c7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81990882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.81990882
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2703685128
Short name	T28
Test name
Test status
Simulation time	434351020 ps
CPU time	156.75 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:47:52 PM PDT 24
Peak memory	208804 kb
Host	smart-1814da5a-9793-4b56-b5e7-1988d92d568b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2703685128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.2703685128
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1412041732
Short name	T482
Test name
Test status
Simulation time	3068911187 ps
CPU time	44.88 seconds
Started	May 21 12:45:09 PM PDT 24
Finished	May 21 12:46:04 PM PDT 24
Peak memory	205992 kb
Host	smart-84ea7bb4-5ff5-4a7c-9a1c-0090aa2e270b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1412041732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.1412041732
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2540551342
Short name	T128
Test name
Test status
Simulation time	837387443 ps
CPU time	9.16 seconds
Started	May 21 12:45:06 PM PDT 24
Finished	May 21 12:45:20 PM PDT 24
Peak memory	204948 kb
Host	smart-354ed9f6-aa7b-41ad-b50c-5944a1572644
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2540551342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2540551342
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3844973733
Short name	T72
Test name
Test status
Simulation time	1346813904 ps
CPU time	50.36 seconds
Started	May 21 12:45:15 PM PDT 24
Finished	May 21 12:46:16 PM PDT 24
Peak memory	206480 kb
Host	smart-010260ec-1966-4a99-89b4-48d78360cd65
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3844973733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3844973733
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3534277373
Short name	T488
Test name
Test status
Simulation time	15078997 ps
CPU time	1.86 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:45:24 PM PDT 24
Peak memory	203452 kb
Host	smart-962b1094-7e9e-4fc7-ba58-aff709efa6b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3534277373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3534277373
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.1591105076
Short name	T159
Test name
Test status
Simulation time	2014577359 ps
CPU time	23.21 seconds
Started	May 21 12:45:13 PM PDT 24
Finished	May 21 12:45:47 PM PDT 24
Peak memory	203472 kb
Host	smart-c4e37665-7575-4fa4-af74-849cbbf42712
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1591105076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1591105076
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.3251790366
Short name	T673
Test name
Test status
Simulation time	212827043 ps
CPU time	24.82 seconds
Started	May 21 12:45:04 PM PDT 24
Finished	May 21 12:45:31 PM PDT 24
Peak memory	204928 kb
Host	smart-ac148a7e-90ab-40d2-b2ab-c52282f62bb8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3251790366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3251790366
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2117075089
Short name	T745
Test name
Test status
Simulation time	30679533252 ps
CPU time	119.98 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:47:22 PM PDT 24
Peak memory	211532 kb
Host	smart-20755fde-b5fd-4e82-b1b0-a37358a225ef
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117075089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2117075089
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.234704806
Short name	T54
Test name
Test status
Simulation time	26463607005 ps
CPU time	117.66 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:47:19 PM PDT 24
Peak memory	204940 kb
Host	smart-4041bcca-752c-433f-9189-698489c1d932
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=234704806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.234704806
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3901469158
Short name	T464
Test name
Test status
Simulation time	88817683 ps
CPU time	13.61 seconds
Started	May 21 12:45:06 PM PDT 24
Finished	May 21 12:45:24 PM PDT 24
Peak memory	211632 kb
Host	smart-8b9af88c-5976-4a52-84fc-186303b4e5a8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901469158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3901469158
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.726285364
Short name	T760
Test name
Test status
Simulation time	1433105182 ps
CPU time	28.66 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	204176 kb
Host	smart-31dbb453-cdad-40d4-bdc7-9f60a2292793
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726285364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.726285364
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.3575023836
Short name	T125
Test name
Test status
Simulation time	30946826 ps
CPU time	2.4 seconds
Started	May 21 12:45:06 PM PDT 24
Finished	May 21 12:45:13 PM PDT 24
Peak memory	203312 kb
Host	smart-3d65584d-4b6e-4408-b6b6-a56cb6d28498
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3575023836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3575023836
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2302583383
Short name	T713
Test name
Test status
Simulation time	5500546894 ps
CPU time	32.58 seconds
Started	May 21 12:45:08 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	203428 kb
Host	smart-8202e2a9-7521-465b-a6bc-782ad0359919
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302583383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2302583383
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2260744399
Short name	T728
Test name
Test status
Simulation time	5178407976 ps
CPU time	35.09 seconds
Started	May 21 12:45:07 PM PDT 24
Finished	May 21 12:45:49 PM PDT 24
Peak memory	203356 kb
Host	smart-989916a7-b1ef-4bb8-878b-fc7b0af30ce6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2260744399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2260744399
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2475667536
Short name	T344
Test name
Test status
Simulation time	33877528 ps
CPU time	2.56 seconds
Started	May 21 12:45:08 PM PDT 24
Finished	May 21 12:45:20 PM PDT 24
Peak memory	203420 kb
Host	smart-cb8c38bf-e1cf-410a-a0ba-3a2a9efe5ece
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475667536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2475667536
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.1237156795
Short name	T112
Test name
Test status
Simulation time	32264087873 ps
CPU time	175.68 seconds
Started	May 21 12:45:15 PM PDT 24
Finished	May 21 12:48:21 PM PDT 24
Peak memory	209616 kb
Host	smart-d1275a0f-3417-4842-84c7-951f9a1b8578
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1237156795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1237156795
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3072550530
Short name	T589
Test name
Test status
Simulation time	11893452448 ps
CPU time	142.21 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:47:45 PM PDT 24
Peak memory	208532 kb
Host	smart-43e76785-9299-46f0-a614-48f6473d2201
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3072550530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3072550530
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1659736170
Short name	T170
Test name
Test status
Simulation time	505439577 ps
CPU time	83.87 seconds
Started	May 21 12:45:13 PM PDT 24
Finished	May 21 12:46:48 PM PDT 24
Peak memory	207432 kb
Host	smart-ea6e4db4-6212-4d78-a0c4-610868d9bc45
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1659736170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1659736170
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.311152116
Short name	T403
Test name
Test status
Simulation time	5164964815 ps
CPU time	120.83 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:47:25 PM PDT 24
Peak memory	209092 kb
Host	smart-5970a0a2-aea8-48bd-810d-1be14eb17919
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=311152116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.311152116
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.934257585
Short name	T818
Test name
Test status
Simulation time	1825466962 ps
CPU time	29.75 seconds
Started	May 21 12:45:13 PM PDT 24
Finished	May 21 12:45:54 PM PDT 24
Peak memory	211892 kb
Host	smart-0936d0c0-e905-4502-aa6a-4d7530395d6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=934257585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.934257585
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1485076896
Short name	T149
Test name
Test status
Simulation time	3199870987 ps
CPU time	66.45 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:46:30 PM PDT 24
Peak memory	206760 kb
Host	smart-a5e9311e-cfd8-4243-9093-f5e198db6d88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1485076896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1485076896
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3984626385
Short name	T659
Test name
Test status
Simulation time	859379573 ps
CPU time	25.95 seconds
Started	May 21 12:45:14 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	203628 kb
Host	smart-e5e4af29-be60-4fa5-aa0e-9e44c6c8e1b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3984626385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3984626385
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.4080283078
Short name	T652
Test name
Test status
Simulation time	137719274 ps
CPU time	15.68 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:45:39 PM PDT 24
Peak memory	203436 kb
Host	smart-b5a80db6-9b15-4adf-b85c-01b72a292c9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4080283078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.4080283078
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.1890502063
Short name	T40
Test name
Test status
Simulation time	3060054834 ps
CPU time	32.04 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:45:54 PM PDT 24
Peak memory	204528 kb
Host	smart-2475d93a-c0ca-4fc4-81f9-b42d9994a493
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1890502063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1890502063
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.38348694
Short name	T693
Test name
Test status
Simulation time	13325705754 ps
CPU time	69.98 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:46:32 PM PDT 24
Peak memory	204808 kb
Host	smart-6f239660-b458-4058-bf57-6942078a3339
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=38348694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.38348694
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2904106418
Short name	T570
Test name
Test status
Simulation time	20515532268 ps
CPU time	194.44 seconds
Started	May 21 12:45:14 PM PDT 24
Finished	May 21 12:48:40 PM PDT 24
Peak memory	205268 kb
Host	smart-1735c022-f017-4c97-adde-efbdebee618f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2904106418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2904106418
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.878093221
Short name	T246
Test name
Test status
Simulation time	24381412 ps
CPU time	3.16 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:45:27 PM PDT 24
Peak memory	203476 kb
Host	smart-d00f3ed9-123f-47a3-9ae5-7072cd59c6f0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878093221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.878093221
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.588999563
Short name	T6
Test name
Test status
Simulation time	885755342 ps
CPU time	23.16 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:45:46 PM PDT 24
Peak memory	203504 kb
Host	smart-c05a4ebd-1e02-4881-aa28-4c609378203d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588999563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.588999563
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.2236368896
Short name	T586
Test name
Test status
Simulation time	188768190 ps
CPU time	3.43 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:45:26 PM PDT 24
Peak memory	203412 kb
Host	smart-f37d31b8-ef9d-4060-844d-1503e2682b20
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2236368896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2236368896
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3718916900
Short name	T868
Test name
Test status
Simulation time	7880488385 ps
CPU time	26.26 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:45:48 PM PDT 24
Peak memory	203504 kb
Host	smart-4b1eb09e-a0fd-493a-8f74-ed2ee00ee7d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718916900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3718916900
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.88737573
Short name	T295
Test name
Test status
Simulation time	4462380302 ps
CPU time	30.12 seconds
Started	May 21 12:45:11 PM PDT 24
Finished	May 21 12:45:52 PM PDT 24
Peak memory	203496 kb
Host	smart-9a4190cc-1e30-4d11-a027-4cd66075076c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=88737573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.88737573
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2301901580
Short name	T372
Test name
Test status
Simulation time	34114968 ps
CPU time	2.29 seconds
Started	May 21 12:45:15 PM PDT 24
Finished	May 21 12:45:28 PM PDT 24
Peak memory	203432 kb
Host	smart-a19543cb-e0b0-4d0b-88e7-cd7d039b57a1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301901580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2301901580
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.2885531517
Short name	T373
Test name
Test status
Simulation time	562984721 ps
CPU time	8.71 seconds
Started	May 21 12:45:15 PM PDT 24
Finished	May 21 12:45:34 PM PDT 24
Peak memory	205128 kb
Host	smart-64868ca4-3dc9-4a65-841a-9d42edf25399
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2885531517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2885531517
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1067608938
Short name	T636
Test name
Test status
Simulation time	8654046362 ps
CPU time	191.48 seconds
Started	May 21 12:45:13 PM PDT 24
Finished	May 21 12:48:36 PM PDT 24
Peak memory	210224 kb
Host	smart-6fef84de-aed3-4c78-9825-b2d23c208f3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1067608938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1067608938
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.168140828
Short name	T730
Test name
Test status
Simulation time	5471124827 ps
CPU time	402.35 seconds
Started	May 21 12:45:12 PM PDT 24
Finished	May 21 12:52:06 PM PDT 24
Peak memory	220028 kb
Host	smart-16907368-9099-41d4-bd42-2b124eb6975a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=168140828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.168140828
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1476189086
Short name	T216
Test name
Test status
Simulation time	106361091 ps
CPU time	13.09 seconds
Started	May 21 12:45:13 PM PDT 24
Finished	May 21 12:45:38 PM PDT 24
Peak memory	204796 kb
Host	smart-9fbb5ce2-7218-4556-b112-e118affde596
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1476189086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1476189086
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.135797553
Short name	T144
Test name
Test status
Simulation time	1326480175 ps
CPU time	22.03 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:45:53 PM PDT 24
Peak memory	204512 kb
Host	smart-f95c97cf-e5f2-434f-8b3a-1649f28fe5a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=135797553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.135797553
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1399429126
Short name	T389
Test name
Test status
Simulation time	272596091855 ps
CPU time	504.5 seconds
Started	May 21 12:45:22 PM PDT 24
Finished	May 21 12:53:56 PM PDT 24
Peak memory	205968 kb
Host	smart-797b7cb1-4a59-496a-81d3-d0af177f88ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1399429126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.1399429126
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2166921550
Short name	T193
Test name
Test status
Simulation time	739740080 ps
CPU time	18.72 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:45:47 PM PDT 24
Peak memory	203452 kb
Host	smart-257d6955-6ae3-4c8d-a51e-696496d00806
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2166921550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2166921550
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.2316981457
Short name	T332
Test name
Test status
Simulation time	2851808517 ps
CPU time	20.81 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:45:48 PM PDT 24
Peak memory	203480 kb
Host	smart-348899c7-5620-4b08-9377-909da376feb4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2316981457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2316981457
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.1565713581
Short name	T827
Test name
Test status
Simulation time	55364172 ps
CPU time	7.44 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:45:35 PM PDT 24
Peak memory	211588 kb
Host	smart-518b7642-0899-4aa9-bb0d-6d83b8ad81de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1565713581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1565713581
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2247451287
Short name	T119
Test name
Test status
Simulation time	63783348860 ps
CPU time	78.13 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:46:46 PM PDT 24
Peak memory	211648 kb
Host	smart-478818ab-bcb1-453c-8f45-ca361025d426
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247451287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2247451287
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1929559773
Short name	T606
Test name
Test status
Simulation time	166805682206 ps
CPU time	433.99 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:52:43 PM PDT 24
Peak memory	211688 kb
Host	smart-5f443337-11e1-466d-8e3e-db1134dd0146
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1929559773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1929559773
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1490715969
Short name	T647
Test name
Test status
Simulation time	88844890 ps
CPU time	9.66 seconds
Started	May 21 12:45:22 PM PDT 24
Finished	May 21 12:45:41 PM PDT 24
Peak memory	204652 kb
Host	smart-98fcb593-be8f-44aa-95e2-2c65b13b0c3f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490715969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1490715969
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.2223598579
Short name	T469
Test name
Test status
Simulation time	1171334765 ps
CPU time	23.01 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	203512 kb
Host	smart-13ac4633-8992-4409-bb18-9fc2c26193b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2223598579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2223598579
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.712250270
Short name	T766
Test name
Test status
Simulation time	176582148 ps
CPU time	3.62 seconds
Started	May 21 12:45:14 PM PDT 24
Finished	May 21 12:45:29 PM PDT 24
Peak memory	203452 kb
Host	smart-95dd2edd-5388-429b-853e-aa7a2cc2e6f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=712250270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.712250270
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2821102476
Short name	T351
Test name
Test status
Simulation time	5157110970 ps
CPU time	24.82 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:45:54 PM PDT 24
Peak memory	203480 kb
Host	smart-5530bd83-1440-4f26-9b8b-2eef22691b58
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821102476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2821102476
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3885424746
Short name	T363
Test name
Test status
Simulation time	3114704968 ps
CPU time	22.28 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:45:52 PM PDT 24
Peak memory	203392 kb
Host	smart-416d52f6-29c9-4f29-80a0-7e8f976d10c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3885424746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3885424746
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3426213132
Short name	T249
Test name
Test status
Simulation time	33790352 ps
CPU time	2.27 seconds
Started	May 21 12:45:13 PM PDT 24
Finished	May 21 12:45:27 PM PDT 24
Peak memory	203428 kb
Host	smart-4cf80fa1-cdd4-4ede-8bc4-7304fcad9b56
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426213132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3426213132
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.103917038
Short name	T229
Test name
Test status
Simulation time	1130737482 ps
CPU time	93.79 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:47:02 PM PDT 24
Peak memory	207668 kb
Host	smart-a9d2a314-4b8d-4875-8d2e-85a4be44418e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=103917038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.103917038
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3894130863
Short name	T353
Test name
Test status
Simulation time	1502666044 ps
CPU time	141.65 seconds
Started	May 21 12:45:21 PM PDT 24
Finished	May 21 12:47:53 PM PDT 24
Peak memory	211548 kb
Host	smart-22c5f17a-704a-4bed-b88b-508f7d1e3460
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3894130863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3894130863
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.234791405
Short name	T345
Test name
Test status
Simulation time	6417017916 ps
CPU time	198.97 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:48:49 PM PDT 24
Peak memory	208584 kb
Host	smart-e7fc6743-ab1e-43fd-a55b-0b387ab7b103
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=234791405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.234791405
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3316822077
Short name	T11
Test name
Test status
Simulation time	73640459 ps
CPU time	9.68 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:45:39 PM PDT 24
Peak memory	204784 kb
Host	smart-92c130d1-48fa-4b30-b887-e04fe166b2bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316822077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3316822077
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2880542050
Short name	T842
Test name
Test status
Simulation time	6273378929 ps
CPU time	37.1 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:46:10 PM PDT 24
Peak memory	206508 kb
Host	smart-c28f66d6-f02c-4d28-b481-79289556ecc3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2880542050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2880542050
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3151617681
Short name	T811
Test name
Test status
Simulation time	35548053922 ps
CPU time	314.78 seconds
Started	May 21 12:45:24 PM PDT 24
Finished	May 21 12:50:47 PM PDT 24
Peak memory	206112 kb
Host	smart-e3a5d880-627c-473c-aede-a63e1f6c1750
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3151617681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.3151617681
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2595276574
Short name	T305
Test name
Test status
Simulation time	1977725618 ps
CPU time	25.73 seconds
Started	May 21 12:45:24 PM PDT 24
Finished	May 21 12:45:58 PM PDT 24
Peak memory	203692 kb
Host	smart-a7440009-3c9f-4c6b-a06d-017a988e519b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2595276574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2595276574
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.1587644216
Short name	T595
Test name
Test status
Simulation time	381214181 ps
CPU time	15.46 seconds
Started	May 21 12:45:24 PM PDT 24
Finished	May 21 12:45:48 PM PDT 24
Peak memory	203400 kb
Host	smart-6a481bec-3e99-4405-bf19-2fe046f6a9bd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1587644216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1587644216
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.2783434740
Short name	T675
Test name
Test status
Simulation time	114306412 ps
CPU time	3.16 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:45:31 PM PDT 24
Peak memory	203864 kb
Host	smart-987288bd-dc55-4edb-91d9-e10938965d37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2783434740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2783434740
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2806713076
Short name	T723
Test name
Test status
Simulation time	36409662272 ps
CPU time	196.16 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:48:44 PM PDT 24
Peak memory	204804 kb
Host	smart-dd7b94f9-3d49-4cb5-99d1-20c29dee3321
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806713076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2806713076
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3281904685
Short name	T508
Test name
Test status
Simulation time	9670380620 ps
CPU time	48.35 seconds
Started	May 21 12:45:18 PM PDT 24
Finished	May 21 12:46:16 PM PDT 24
Peak memory	211560 kb
Host	smart-1da77aa7-1a6a-4e4c-8091-26b3c0d34219
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3281904685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3281904685
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2929650556
Short name	T634
Test name
Test status
Simulation time	209364418 ps
CPU time	27.57 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:45:56 PM PDT 24
Peak memory	205048 kb
Host	smart-78a23882-8540-4107-8a65-5b2925939300
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929650556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2929650556
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.265735671
Short name	T30
Test name
Test status
Simulation time	657833355 ps
CPU time	14.96 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:45:46 PM PDT 24
Peak memory	203488 kb
Host	smart-5ad8854a-4f71-4bdf-8597-5eda8a64ad9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=265735671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.265735671
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.830749446
Short name	T471
Test name
Test status
Simulation time	755682142 ps
CPU time	3.84 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:45:37 PM PDT 24
Peak memory	203436 kb
Host	smart-b958b65b-071b-4980-a77e-39312ad7cf01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830749446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.830749446
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.65953744
Short name	T37
Test name
Test status
Simulation time	11180197439 ps
CPU time	29.81 seconds
Started	May 21 12:45:23 PM PDT 24
Finished	May 21 12:46:02 PM PDT 24
Peak memory	203496 kb
Host	smart-c92be5f7-1b91-432c-8667-ba96f9385e64
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=65953744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.65953744
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1838335618
Short name	T524
Test name
Test status
Simulation time	2915200283 ps
CPU time	20.14 seconds
Started	May 21 12:45:21 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	203520 kb
Host	smart-294f75aa-699f-45a4-a835-82d1fd488344
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1838335618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1838335618
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3687712063
Short name	T858
Test name
Test status
Simulation time	24343691 ps
CPU time	2.24 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:45:33 PM PDT 24
Peak memory	203412 kb
Host	smart-38ee2f3b-5731-4a3c-96b5-55fad96bf4bd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687712063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3687712063
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.789035343
Short name	T541
Test name
Test status
Simulation time	6499328319 ps
CPU time	188.89 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:48:38 PM PDT 24
Peak memory	207188 kb
Host	smart-b7ddd00f-d02c-4012-9650-67378edb55b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=789035343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.789035343
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.15254305
Short name	T237
Test name
Test status
Simulation time	230024646 ps
CPU time	54.83 seconds
Started	May 21 12:45:24 PM PDT 24
Finished	May 21 12:46:27 PM PDT 24
Peak memory	208072 kb
Host	smart-c15b07c3-6410-42b8-9371-196a9a97b444
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=15254305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_ reset.15254305
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3459988429
Short name	T690
Test name
Test status
Simulation time	1303008322 ps
CPU time	247.96 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:49:36 PM PDT 24
Peak memory	219784 kb
Host	smart-132f8e5a-82f5-4b6f-a191-b62cf821c5da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3459988429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3459988429
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3601614298
Short name	T731
Test name
Test status
Simulation time	81433415 ps
CPU time	9.95 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:45:38 PM PDT 24
Peak memory	211580 kb
Host	smart-ef81ca43-0bc3-4fa8-97a9-4915ba062ed8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3601614298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3601614298
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.237417708
Short name	T303
Test name
Test status
Simulation time	64070516 ps
CPU time	10.39 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:45:44 PM PDT 24
Peak memory	204180 kb
Host	smart-df13a027-cdd9-4aa3-87b1-0b70e4c37aa4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=237417708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.237417708
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3704879904
Short name	T356
Test name
Test status
Simulation time	3436438377 ps
CPU time	27.19 seconds
Started	May 21 12:45:26 PM PDT 24
Finished	May 21 12:46:02 PM PDT 24
Peak memory	203744 kb
Host	smart-938231bd-3e9d-4a34-adb8-d61a01f2ff8b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3704879904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3704879904
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.647495604
Short name	T445
Test name
Test status
Simulation time	798820567 ps
CPU time	28.87 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:46:02 PM PDT 24
Peak memory	203472 kb
Host	smart-922bd05d-1b07-4bf2-8efb-5c496f5315b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647495604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.647495604
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.2664356314
Short name	T376
Test name
Test status
Simulation time	401788901 ps
CPU time	10.11 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:45:44 PM PDT 24
Peak memory	203476 kb
Host	smart-d9c22afa-05af-4244-92cd-ea938a855f70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664356314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2664356314
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.3162130556
Short name	T744
Test name
Test status
Simulation time	42248501 ps
CPU time	5.09 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:45:39 PM PDT 24
Peak memory	211588 kb
Host	smart-f43b84e6-a0fb-4ca6-bc22-33380f01cb2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3162130556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3162130556
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.989039788
Short name	T65
Test name
Test status
Simulation time	67063509617 ps
CPU time	252.23 seconds
Started	May 21 12:45:27 PM PDT 24
Finished	May 21 12:49:47 PM PDT 24
Peak memory	204996 kb
Host	smart-43516fda-f30d-4f46-8721-378bd7184eac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=989039788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.989039788
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1556356642
Short name	T279
Test name
Test status
Simulation time	10908095360 ps
CPU time	42.7 seconds
Started	May 21 12:45:26 PM PDT 24
Finished	May 21 12:46:17 PM PDT 24
Peak memory	211708 kb
Host	smart-b7c0f73a-4806-499f-ba1c-8822f953dbb3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1556356642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1556356642
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3744829909
Short name	T685
Test name
Test status
Simulation time	127226129 ps
CPU time	7.7 seconds
Started	May 21 12:45:26 PM PDT 24
Finished	May 21 12:45:42 PM PDT 24
Peak memory	204576 kb
Host	smart-324f51b9-e8c4-498d-82d3-367f985928d9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744829909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3744829909
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.2951476039
Short name	T169
Test name
Test status
Simulation time	652698504 ps
CPU time	11.52 seconds
Started	May 21 12:45:27 PM PDT 24
Finished	May 21 12:45:46 PM PDT 24
Peak memory	203956 kb
Host	smart-ddf3a364-8161-4652-a105-b08bce53de8d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2951476039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2951476039
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.3455398571
Short name	T674
Test name
Test status
Simulation time	128372054 ps
CPU time	3.17 seconds
Started	May 21 12:45:19 PM PDT 24
Finished	May 21 12:45:32 PM PDT 24
Peak memory	203384 kb
Host	smart-c1b8d186-d3a8-4207-8292-ec6ea011e947
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3455398571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3455398571
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3836499476
Short name	T689
Test name
Test status
Simulation time	8504225750 ps
CPU time	34.35 seconds
Started	May 21 12:45:24 PM PDT 24
Finished	May 21 12:46:07 PM PDT 24
Peak memory	203400 kb
Host	smart-14adf323-f0eb-40a5-a4e2-2f0bcfde6ac4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836499476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3836499476
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2139683392
Short name	T69
Test name
Test status
Simulation time	5803175579 ps
CPU time	29.25 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:46:03 PM PDT 24
Peak memory	203504 kb
Host	smart-8fb907aa-ce2c-415d-970b-1ba669cc0bcd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2139683392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2139683392
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3286124257
Short name	T534
Test name
Test status
Simulation time	28114514 ps
CPU time	2.27 seconds
Started	May 21 12:45:20 PM PDT 24
Finished	May 21 12:45:33 PM PDT 24
Peak memory	203344 kb
Host	smart-fec73387-1451-424c-ba62-0aeb2079f540
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286124257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3286124257
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.2552048007
Short name	T579
Test name
Test status
Simulation time	262601331 ps
CPU time	32.45 seconds
Started	May 21 12:45:26 PM PDT 24
Finished	May 21 12:46:07 PM PDT 24
Peak memory	205748 kb
Host	smart-3f311d33-9887-4616-926b-114092c630cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2552048007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2552048007
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2680927521
Short name	T205
Test name
Test status
Simulation time	29091768420 ps
CPU time	182.32 seconds
Started	May 21 12:45:28 PM PDT 24
Finished	May 21 12:48:38 PM PDT 24
Peak memory	209744 kb
Host	smart-4ff3ea7e-2289-4e9b-a0f7-2f6045e62481
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2680927521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2680927521
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4249904566
Short name	T74
Test name
Test status
Simulation time	12618574842 ps
CPU time	419.32 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:52:33 PM PDT 24
Peak memory	219756 kb
Host	smart-2584e924-2352-4cb3-b6d8-ae9f5e0d0a8c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4249904566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.4249904566
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2252889405
Short name	T358
Test name
Test status
Simulation time	5020938990 ps
CPU time	173.97 seconds
Started	May 21 12:45:27 PM PDT 24
Finished	May 21 12:48:29 PM PDT 24
Peak memory	211416 kb
Host	smart-30c69f88-0cde-4aa3-8b83-236c3bf40e16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2252889405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2252889405
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2690226053
Short name	T45
Test name
Test status
Simulation time	459016256 ps
CPU time	17.67 seconds
Started	May 21 12:45:26 PM PDT 24
Finished	May 21 12:45:52 PM PDT 24
Peak memory	205160 kb
Host	smart-b36281b7-a61c-46e5-a414-9efd2807fa13
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2690226053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2690226053
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3315159660
Short name	T181
Test name
Test status
Simulation time	1508887324 ps
CPU time	62.17 seconds
Started	May 21 12:43:29 PM PDT 24
Finished	May 21 12:44:34 PM PDT 24
Peak memory	206348 kb
Host	smart-d3639afb-5390-4c7b-bbee-57835bcc706c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3315159660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3315159660
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3387638836
Short name	T282
Test name
Test status
Simulation time	17935978634 ps
CPU time	118.34 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:45:32 PM PDT 24
Peak memory	205028 kb
Host	smart-5adf77b3-22e4-40c7-8df7-4177862ea195
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3387638836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.3387638836
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1052782351
Short name	T307
Test name
Test status
Simulation time	151085364 ps
CPU time	18.32 seconds
Started	May 21 12:43:29 PM PDT 24
Finished	May 21 12:43:50 PM PDT 24
Peak memory	203848 kb
Host	smart-55d5ae2b-daec-43ab-8e01-c9ce41b34e76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1052782351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1052782351
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.1099683359
Short name	T393
Test name
Test status
Simulation time	37421462 ps
CPU time	4.25 seconds
Started	May 21 12:43:30 PM PDT 24
Finished	May 21 12:43:37 PM PDT 24
Peak memory	203444 kb
Host	smart-296d7680-aa56-41df-b483-2e4c439d5399
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1099683359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1099683359
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.1523970741
Short name	T532
Test name
Test status
Simulation time	618108629 ps
CPU time	25.3 seconds
Started	May 21 12:43:32 PM PDT 24
Finished	May 21 12:44:00 PM PDT 24
Peak memory	204520 kb
Host	smart-cd2755d3-f709-4ceb-bc5c-950d3923f29a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1523970741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1523970741
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3960125108
Short name	T574
Test name
Test status
Simulation time	14271511540 ps
CPU time	60.38 seconds
Started	May 21 12:43:29 PM PDT 24
Finished	May 21 12:44:32 PM PDT 24
Peak memory	204800 kb
Host	smart-4fc48164-00fe-42e3-b468-077db66de3a3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960125108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3960125108
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.968367129
Short name	T265
Test name
Test status
Simulation time	13155991223 ps
CPU time	104.02 seconds
Started	May 21 12:43:30 PM PDT 24
Finished	May 21 12:45:16 PM PDT 24
Peak memory	204660 kb
Host	smart-43229786-5a31-4cb7-a8c6-8e385af1cbb4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=968367129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.968367129
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3349458571
Short name	T86
Test name
Test status
Simulation time	16568432 ps
CPU time	2.39 seconds
Started	May 21 12:43:29 PM PDT 24
Finished	May 21 12:43:34 PM PDT 24
Peak memory	203308 kb
Host	smart-eec85363-b855-4360-a1ce-4da016ebcef2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349458571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3349458571
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.1474366720
Short name	T350
Test name
Test status
Simulation time	214257618 ps
CPU time	10.01 seconds
Started	May 21 12:43:33 PM PDT 24
Finished	May 21 12:43:45 PM PDT 24
Peak memory	203480 kb
Host	smart-611d3184-7b6c-4bc2-a6ea-6f3519cbef2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1474366720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1474366720
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.3784670246
Short name	T894
Test name
Test status
Simulation time	265662295 ps
CPU time	3.07 seconds
Started	May 21 12:43:32 PM PDT 24
Finished	May 21 12:43:38 PM PDT 24
Peak memory	203424 kb
Host	smart-fd3f88ca-a854-4dae-a538-a055b29c2847
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3784670246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3784670246
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4047703278
Short name	T313
Test name
Test status
Simulation time	38101722106 ps
CPU time	45.11 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:44:19 PM PDT 24
Peak memory	203464 kb
Host	smart-def1254f-45f7-439b-8c94-f2bc1cf9cbe5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047703278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4047703278
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3015733766
Short name	T64
Test name
Test status
Simulation time	7927451545 ps
CPU time	27.31 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:44:01 PM PDT 24
Peak memory	203468 kb
Host	smart-2e251322-6bd3-410c-a064-72edad4f4e7c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3015733766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3015733766
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.760646322
Short name	T330
Test name
Test status
Simulation time	36927415 ps
CPU time	1.96 seconds
Started	May 21 12:43:29 PM PDT 24
Finished	May 21 12:43:34 PM PDT 24
Peak memory	203408 kb
Host	smart-6a3df95f-45c7-4832-b6d2-7392fa1c992b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760646322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.760646322
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.2170623454
Short name	T795
Test name
Test status
Simulation time	4722648451 ps
CPU time	146.06 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:46:00 PM PDT 24
Peak memory	209864 kb
Host	smart-78eb1aca-8f25-40f7-96e5-06afb54352d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2170623454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2170623454
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2319866695
Short name	T558
Test name
Test status
Simulation time	16693827244 ps
CPU time	296.53 seconds
Started	May 21 12:43:30 PM PDT 24
Finished	May 21 12:48:29 PM PDT 24
Peak memory	211720 kb
Host	smart-1e0ed56b-23fe-46b6-9f8f-4e6cf50e31bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2319866695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2319866695
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3839047477
Short name	T832
Test name
Test status
Simulation time	190815228 ps
CPU time	39.97 seconds
Started	May 21 12:43:29 PM PDT 24
Finished	May 21 12:44:11 PM PDT 24
Peak memory	206656 kb
Host	smart-ddeb698d-537b-496a-89fc-0e49a9b69f1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3839047477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3839047477
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2399845791
Short name	T877
Test name
Test status
Simulation time	16442003883 ps
CPU time	335.03 seconds
Started	May 21 12:43:32 PM PDT 24
Finished	May 21 12:49:10 PM PDT 24
Peak memory	223300 kb
Host	smart-d133562c-167d-410a-9986-6d064710ddc9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2399845791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.2399845791
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.100996687
Short name	T423
Test name
Test status
Simulation time	55480780 ps
CPU time	9.74 seconds
Started	May 21 12:43:30 PM PDT 24
Finished	May 21 12:43:42 PM PDT 24
Peak memory	205108 kb
Host	smart-38af2d87-9c2d-4fa5-a4ae-43e4be981d7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=100996687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.100996687
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1642926258
Short name	T44
Test name
Test status
Simulation time	401604884 ps
CPU time	42.35 seconds
Started	May 21 12:45:34 PM PDT 24
Finished	May 21 12:46:21 PM PDT 24
Peak memory	205304 kb
Host	smart-3e66754f-28a0-41ea-8e22-20ed65ba23be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642926258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1642926258
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1290468028
Short name	T418
Test name
Test status
Simulation time	30657812175 ps
CPU time	274.9 seconds
Started	May 21 12:45:33 PM PDT 24
Finished	May 21 12:50:13 PM PDT 24
Peak memory	211684 kb
Host	smart-757833e0-6850-413b-8fbd-cfd0b1150e33
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1290468028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.1290468028
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3786709231
Short name	T124
Test name
Test status
Simulation time	4036646999 ps
CPU time	25.61 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:46:03 PM PDT 24
Peak memory	203388 kb
Host	smart-432cf183-2480-459e-8d03-1e42087d770d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3786709231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3786709231
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.4272113201
Short name	T581
Test name
Test status
Simulation time	336526635 ps
CPU time	14.62 seconds
Started	May 21 12:45:34 PM PDT 24
Finished	May 21 12:45:53 PM PDT 24
Peak memory	203436 kb
Host	smart-215a69ed-9dc1-4505-a416-7cea27346426
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4272113201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.4272113201
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.2320928212
Short name	T275
Test name
Test status
Simulation time	1752567338 ps
CPU time	24.08 seconds
Started	May 21 12:45:31 PM PDT 24
Finished	May 21 12:46:01 PM PDT 24
Peak memory	204512 kb
Host	smart-2ca9e92b-dfaa-428a-9c50-3444aa1573dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2320928212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2320928212
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3654243706
Short name	T477
Test name
Test status
Simulation time	3048949171 ps
CPU time	18.15 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:45:56 PM PDT 24
Peak memory	203364 kb
Host	smart-c38f5b31-07f7-4c79-8731-2cbf06d33bef
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654243706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3654243706
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1436857701
Short name	T176
Test name
Test status
Simulation time	18312027051 ps
CPU time	83.9 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:47:02 PM PDT 24
Peak memory	204904 kb
Host	smart-9d20be0b-aedb-455c-bbc1-293c0c2056a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1436857701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1436857701
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.901425981
Short name	T175
Test name
Test status
Simulation time	152404388 ps
CPU time	12.3 seconds
Started	May 21 12:45:34 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	204480 kb
Host	smart-3df82cee-e5cb-420f-8584-e81c1f4c1048
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901425981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.901425981
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.2199346956
Short name	T224
Test name
Test status
Simulation time	490493534 ps
CPU time	2.7 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:45:41 PM PDT 24
Peak memory	203404 kb
Host	smart-db5a7de9-0f79-452a-a0ee-9898be74d9c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2199346956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2199346956
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.2834123639
Short name	T427
Test name
Test status
Simulation time	177295166 ps
CPU time	4.27 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:45:38 PM PDT 24
Peak memory	203448 kb
Host	smart-8d059157-5081-4967-bf0c-d80a8722eaea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834123639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2834123639
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2946189217
Short name	T671
Test name
Test status
Simulation time	15779892290 ps
CPU time	41.2 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:46:15 PM PDT 24
Peak memory	203428 kb
Host	smart-66a1a8b0-574d-470e-8890-ea44845e5014
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946189217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2946189217
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1066504286
Short name	T822
Test name
Test status
Simulation time	6120195779 ps
CPU time	28.42 seconds
Started	May 21 12:45:25 PM PDT 24
Finished	May 21 12:46:02 PM PDT 24
Peak memory	203440 kb
Host	smart-64a0f3c9-826c-468a-9a8c-325b5da9cbc5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1066504286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1066504286
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2424838214
Short name	T221
Test name
Test status
Simulation time	31892990 ps
CPU time	2.34 seconds
Started	May 21 12:45:26 PM PDT 24
Finished	May 21 12:45:37 PM PDT 24
Peak memory	203412 kb
Host	smart-1658d3be-6e65-4aa5-99de-f6f3b3401764
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424838214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2424838214
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.1395609143
Short name	T624
Test name
Test status
Simulation time	1491627528 ps
CPU time	12.01 seconds
Started	May 21 12:45:33 PM PDT 24
Finished	May 21 12:45:50 PM PDT 24
Peak memory	204808 kb
Host	smart-1a874404-e4f0-4678-a853-3afb7a8158d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1395609143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1395609143
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2719958239
Short name	T620
Test name
Test status
Simulation time	611540442 ps
CPU time	64.82 seconds
Started	May 21 12:45:31 PM PDT 24
Finished	May 21 12:46:41 PM PDT 24
Peak memory	205840 kb
Host	smart-ed627034-0024-4aec-b289-1596da5c61c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2719958239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2719958239
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4292574801
Short name	T879
Test name
Test status
Simulation time	269169599 ps
CPU time	126.76 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:47:44 PM PDT 24
Peak memory	208196 kb
Host	smart-3da3a5e9-9549-4b8f-9863-8a0d0e0041c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4292574801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.4292574801
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3118299898
Short name	T800
Test name
Test status
Simulation time	12703928337 ps
CPU time	222.83 seconds
Started	May 21 12:45:31 PM PDT 24
Finished	May 21 12:49:19 PM PDT 24
Peak memory	219912 kb
Host	smart-df0d7470-a261-4f0e-9b1d-027ed9aee005
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118299898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.3118299898
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.4212827926
Short name	T390
Test name
Test status
Simulation time	170845610 ps
CPU time	8.05 seconds
Started	May 21 12:45:31 PM PDT 24
Finished	May 21 12:45:45 PM PDT 24
Peak memory	204900 kb
Host	smart-5bbb87fe-36fe-4d68-b781-714c12054250
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4212827926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4212827926
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2422308041
Short name	T234
Test name
Test status
Simulation time	243762664 ps
CPU time	21.2 seconds
Started	May 21 12:45:33 PM PDT 24
Finished	May 21 12:45:59 PM PDT 24
Peak memory	204668 kb
Host	smart-3d52f534-497b-4fb6-9978-e9d0205c5628
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2422308041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2422308041
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2537707731
Short name	T212
Test name
Test status
Simulation time	3993062026 ps
CPU time	29.05 seconds
Started	May 21 12:45:36 PM PDT 24
Finished	May 21 12:46:08 PM PDT 24
Peak memory	203520 kb
Host	smart-fa4cf784-aa6e-4d0e-90e6-80cfdb955363
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2537707731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2537707731
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.925807569
Short name	T717
Test name
Test status
Simulation time	1332293380 ps
CPU time	15.72 seconds
Started	May 21 12:45:45 PM PDT 24
Finished	May 21 12:46:03 PM PDT 24
Peak memory	203720 kb
Host	smart-cbe83753-a12c-4634-8303-4771cbb0c3a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=925807569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.925807569
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.3535756024
Short name	T191
Test name
Test status
Simulation time	89510953 ps
CPU time	6.55 seconds
Started	May 21 12:45:40 PM PDT 24
Finished	May 21 12:45:49 PM PDT 24
Peak memory	203476 kb
Host	smart-d184b2f8-6e9d-409a-a17e-9e4fc7a6ba7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3535756024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3535756024
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.3848644925
Short name	T821
Test name
Test status
Simulation time	166605062 ps
CPU time	23.57 seconds
Started	May 21 12:45:35 PM PDT 24
Finished	May 21 12:46:02 PM PDT 24
Peak memory	204868 kb
Host	smart-4272fcba-ddba-41ea-9e78-f4f955468634
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3848644925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3848644925
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3824975700
Short name	T576
Test name
Test status
Simulation time	43635462879 ps
CPU time	168.3 seconds
Started	May 21 12:45:35 PM PDT 24
Finished	May 21 12:48:27 PM PDT 24
Peak memory	205496 kb
Host	smart-fe7ddf9a-f9b5-47e3-8b8b-29cde69761ee
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824975700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3824975700
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2487271230
Short name	T429
Test name
Test status
Simulation time	23959652959 ps
CPU time	214.59 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:49:13 PM PDT 24
Peak memory	204684 kb
Host	smart-fa59a8b3-980a-4641-ba4e-273c380fbb6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2487271230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2487271230
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.967190052
Short name	T270
Test name
Test status
Simulation time	529359938 ps
CPU time	12.35 seconds
Started	May 21 12:45:33 PM PDT 24
Finished	May 21 12:45:50 PM PDT 24
Peak memory	204716 kb
Host	smart-ec8cb1f1-4e44-4b52-8724-61512599caab
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967190052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.967190052
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.1647713136
Short name	T892
Test name
Test status
Simulation time	880708227 ps
CPU time	13.05 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	203952 kb
Host	smart-2ea6d95a-d701-41af-af2e-892b812e2701
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1647713136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1647713136
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.2789874130
Short name	T476
Test name
Test status
Simulation time	170190793 ps
CPU time	3.32 seconds
Started	May 21 12:45:36 PM PDT 24
Finished	May 21 12:45:43 PM PDT 24
Peak memory	203376 kb
Host	smart-fa6eae94-991f-4ac1-8bb9-bc57806ab2af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2789874130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2789874130
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3884479643
Short name	T810
Test name
Test status
Simulation time	5985036882 ps
CPU time	26.51 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:46:04 PM PDT 24
Peak memory	203480 kb
Host	smart-c2efa29c-bb87-40ca-bf9e-8b9eefb07891
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884479643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3884479643
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2304174458
Short name	T695
Test name
Test status
Simulation time	5545860971 ps
CPU time	27.59 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:46:06 PM PDT 24
Peak memory	203484 kb
Host	smart-46ddf9e0-668c-40a1-8539-d6774d995631
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2304174458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2304174458
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3577326072
Short name	T414
Test name
Test status
Simulation time	46244196 ps
CPU time	2.78 seconds
Started	May 21 12:45:32 PM PDT 24
Finished	May 21 12:45:40 PM PDT 24
Peak memory	203708 kb
Host	smart-69b5429a-a92d-4458-b25c-c5be8ebef946
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577326072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3577326072
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.798005684
Short name	T803
Test name
Test status
Simulation time	566588913 ps
CPU time	12.78 seconds
Started	May 21 12:45:39 PM PDT 24
Finished	May 21 12:45:54 PM PDT 24
Peak memory	204916 kb
Host	smart-cf699f8b-f1cb-46f2-ab4e-70e904b96060
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=798005684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.798005684
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1077649655
Short name	T87
Test name
Test status
Simulation time	7331185664 ps
CPU time	41.27 seconds
Started	May 21 12:45:40 PM PDT 24
Finished	May 21 12:46:24 PM PDT 24
Peak memory	204464 kb
Host	smart-3ffde39a-58cb-4576-bf1d-17e248eb9c7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077649655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1077649655
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.993141317
Short name	T79
Test name
Test status
Simulation time	5634945949 ps
CPU time	415.32 seconds
Started	May 21 12:45:40 PM PDT 24
Finished	May 21 12:52:39 PM PDT 24
Peak memory	211716 kb
Host	smart-89738bc5-f51d-4eb2-8ef9-55b17ca964f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=993141317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand _reset.993141317
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1862198586
Short name	T798
Test name
Test status
Simulation time	7929606391 ps
CPU time	421.76 seconds
Started	May 21 12:45:40 PM PDT 24
Finished	May 21 12:52:44 PM PDT 24
Peak memory	219988 kb
Host	smart-4785ce19-9c61-4d54-81c4-6ec8add630da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1862198586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1862198586
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.431472943
Short name	T518
Test name
Test status
Simulation time	249266858 ps
CPU time	13.55 seconds
Started	May 21 12:45:39 PM PDT 24
Finished	May 21 12:45:56 PM PDT 24
Peak memory	204992 kb
Host	smart-9ac75084-71d9-4122-9510-9d71469c1a24
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=431472943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.431472943
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2225065077
Short name	T415
Test name
Test status
Simulation time	1472680977 ps
CPU time	40.97 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:46:27 PM PDT 24
Peak memory	211612 kb
Host	smart-1dffb8e1-0861-4d45-ac64-4bc746908f1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2225065077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2225065077
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1951192686
Short name	T528
Test name
Test status
Simulation time	41544216940 ps
CPU time	247.24 seconds
Started	May 21 12:45:39 PM PDT 24
Finished	May 21 12:49:50 PM PDT 24
Peak memory	206428 kb
Host	smart-abcedbf8-9c07-4172-b283-b3cb0a7190df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1951192686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1951192686
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.46808978
Short name	T871
Test name
Test status
Simulation time	114166039 ps
CPU time	3.82 seconds
Started	May 21 12:45:43 PM PDT 24
Finished	May 21 12:45:49 PM PDT 24
Peak memory	203428 kb
Host	smart-8f9d338d-c25a-4de8-8363-f05394c0a928
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=46808978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.46808978
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.2660544647
Short name	T670
Test name
Test status
Simulation time	717091358 ps
CPU time	12.44 seconds
Started	May 21 12:45:42 PM PDT 24
Finished	May 21 12:45:57 PM PDT 24
Peak memory	203404 kb
Host	smart-d67ac432-0d09-4cc7-a8a1-15fe950695fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2660544647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2660544647
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.1904994417
Short name	T628
Test name
Test status
Simulation time	1537839164 ps
CPU time	24.17 seconds
Started	May 21 12:45:41 PM PDT 24
Finished	May 21 12:46:08 PM PDT 24
Peak memory	204556 kb
Host	smart-c4bcc4d3-bace-4dc6-b619-c0e11af7933a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1904994417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1904994417
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3302226423
Short name	T256
Test name
Test status
Simulation time	35287187574 ps
CPU time	81.91 seconds
Started	May 21 12:45:37 PM PDT 24
Finished	May 21 12:47:02 PM PDT 24
Peak memory	204920 kb
Host	smart-fd20f5aa-a277-41c4-8218-43511c3359fb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302226423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3302226423
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2968115416
Short name	T538
Test name
Test status
Simulation time	12718807805 ps
CPU time	134.36 seconds
Started	May 21 12:45:42 PM PDT 24
Finished	May 21 12:47:59 PM PDT 24
Peak memory	205304 kb
Host	smart-61b6be84-4793-4dba-81bb-acffd1ed85b3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2968115416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2968115416
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3164955313
Short name	T568
Test name
Test status
Simulation time	283083182 ps
CPU time	25.19 seconds
Started	May 21 12:45:42 PM PDT 24
Finished	May 21 12:46:10 PM PDT 24
Peak memory	211620 kb
Host	smart-05fc2cf1-ce28-456b-900a-2a992c79b38f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164955313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3164955313
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.905017049
Short name	T152
Test name
Test status
Simulation time	2021223395 ps
CPU time	34.9 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:46:22 PM PDT 24
Peak memory	211600 kb
Host	smart-eaa53c6f-2a98-4b1a-96ea-af2bfe70e157
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=905017049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.905017049
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.4158601192
Short name	T555
Test name
Test status
Simulation time	300448737 ps
CPU time	3.2 seconds
Started	May 21 12:45:43 PM PDT 24
Finished	May 21 12:45:48 PM PDT 24
Peak memory	203400 kb
Host	smart-6a84245d-dbb0-4951-ab4e-63e41f9714b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4158601192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4158601192
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1795479754
Short name	T889
Test name
Test status
Simulation time	7376853741 ps
CPU time	32.2 seconds
Started	May 21 12:45:43 PM PDT 24
Finished	May 21 12:46:18 PM PDT 24
Peak memory	203492 kb
Host	smart-1a7ef9fc-2858-41ad-8ccf-0b6abd8a1c2a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795479754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1795479754
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3762956102
Short name	T461
Test name
Test status
Simulation time	4322614591 ps
CPU time	23.69 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:46:10 PM PDT 24
Peak memory	203472 kb
Host	smart-efb8dd7d-8dda-4932-97fd-970b2745b3c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3762956102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3762956102
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2440999396
Short name	T81
Test name
Test status
Simulation time	29146655 ps
CPU time	2.01 seconds
Started	May 21 12:45:43 PM PDT 24
Finished	May 21 12:45:48 PM PDT 24
Peak memory	203452 kb
Host	smart-03cef6e9-c052-45a7-ac97-80031e240e67
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440999396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2440999396
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.1924426829
Short name	T796
Test name
Test status
Simulation time	1142300700 ps
CPU time	127.61 seconds
Started	May 21 12:45:43 PM PDT 24
Finished	May 21 12:47:54 PM PDT 24
Peak memory	207172 kb
Host	smart-94ad73ac-d592-413d-b892-d3b95d1919f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1924426829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1924426829
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4134060477
Short name	T35
Test name
Test status
Simulation time	16070337942 ps
CPU time	179.04 seconds
Started	May 21 12:45:40 PM PDT 24
Finished	May 21 12:48:42 PM PDT 24
Peak memory	208992 kb
Host	smart-1786d339-f8a3-49db-a4c1-46634a544d7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134060477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4134060477
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3216027760
Short name	T272
Test name
Test status
Simulation time	184406103 ps
CPU time	48.87 seconds
Started	May 21 12:45:41 PM PDT 24
Finished	May 21 12:46:33 PM PDT 24
Peak memory	206740 kb
Host	smart-cc490d62-efb6-431e-82d1-950903253be4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3216027760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3216027760
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1332237998
Short name	T232
Test name
Test status
Simulation time	1850055520 ps
CPU time	31.14 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:46:17 PM PDT 24
Peak memory	205268 kb
Host	smart-ef739b3d-0e73-4260-9db3-38f52e16f3f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1332237998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1332237998
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3617205406
Short name	T697
Test name
Test status
Simulation time	216368046 ps
CPU time	15.4 seconds
Started	May 21 12:45:46 PM PDT 24
Finished	May 21 12:46:04 PM PDT 24
Peak memory	204492 kb
Host	smart-4031782a-fb59-4560-b251-ec7e93b53bf7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3617205406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3617205406
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3758019544
Short name	T702
Test name
Test status
Simulation time	185759986482 ps
CPU time	632.92 seconds
Started	May 21 12:45:45 PM PDT 24
Finished	May 21 12:56:20 PM PDT 24
Peak memory	206096 kb
Host	smart-a8127fb3-5762-4b06-81ea-8ca234d8b4f9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3758019544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.3758019544
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1698381713
Short name	T361
Test name
Test status
Simulation time	262327310 ps
CPU time	7.45 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:45:54 PM PDT 24
Peak memory	203404 kb
Host	smart-999fc60f-46ee-4bd7-9acc-f239facb1fe8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1698381713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1698381713
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.3109207451
Short name	T7
Test name
Test status
Simulation time	1892336275 ps
CPU time	21.72 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:46:08 PM PDT 24
Peak memory	203340 kb
Host	smart-4b436ad5-f7b5-49a7-9e17-430c1ad3a0d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109207451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3109207451
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.285529451
Short name	T80
Test name
Test status
Simulation time	1122963170 ps
CPU time	39.74 seconds
Started	May 21 12:45:45 PM PDT 24
Finished	May 21 12:46:27 PM PDT 24
Peak memory	205092 kb
Host	smart-9f79e7e6-6208-40eb-98b8-38a44d97319f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285529451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.285529451
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3104709700
Short name	T664
Test name
Test status
Simulation time	31774222008 ps
CPU time	122.1 seconds
Started	May 21 12:45:45 PM PDT 24
Finished	May 21 12:47:49 PM PDT 24
Peak memory	211672 kb
Host	smart-ee546311-d89f-48f3-b09e-2342bf838c00
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104709700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3104709700
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.675874870
Short name	T312
Test name
Test status
Simulation time	65057220389 ps
CPU time	147.35 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:48:14 PM PDT 24
Peak memory	211692 kb
Host	smart-820837ce-9135-48b7-8bd3-77c187b44c19
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=675874870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.675874870
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.26878234
Short name	T612
Test name
Test status
Simulation time	171125749 ps
CPU time	9.74 seconds
Started	May 21 12:45:47 PM PDT 24
Finished	May 21 12:45:59 PM PDT 24
Peak memory	204732 kb
Host	smart-18359d0c-e607-4f3c-a77e-89241c7e8730
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26878234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.26878234
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.2470757260
Short name	T273
Test name
Test status
Simulation time	541649766 ps
CPU time	7.77 seconds
Started	May 21 12:45:46 PM PDT 24
Finished	May 21 12:45:56 PM PDT 24
Peak memory	203756 kb
Host	smart-03de5590-cbd0-45f6-b0bc-17e399dd5d92
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2470757260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2470757260
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.2079806278
Short name	T560
Test name
Test status
Simulation time	46238736 ps
CPU time	2.11 seconds
Started	May 21 12:45:45 PM PDT 24
Finished	May 21 12:45:50 PM PDT 24
Peak memory	203404 kb
Host	smart-7b043cc8-ffec-435f-8023-2eb18bb2ba7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2079806278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2079806278
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2855413022
Short name	T419
Test name
Test status
Simulation time	12835094646 ps
CPU time	30.5 seconds
Started	May 21 12:45:40 PM PDT 24
Finished	May 21 12:46:13 PM PDT 24
Peak memory	203492 kb
Host	smart-f161fe6f-2f3e-4ab2-8913-359efecb8cb6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855413022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2855413022
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.493709990
Short name	T825
Test name
Test status
Simulation time	6205663888 ps
CPU time	27.34 seconds
Started	May 21 12:45:41 PM PDT 24
Finished	May 21 12:46:11 PM PDT 24
Peak memory	203504 kb
Host	smart-c36f60dc-5c03-4ca1-9c06-a775621f8b40
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=493709990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.493709990
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.843338686
Short name	T430
Test name
Test status
Simulation time	42179594 ps
CPU time	2.36 seconds
Started	May 21 12:45:41 PM PDT 24
Finished	May 21 12:45:47 PM PDT 24
Peak memory	203424 kb
Host	smart-c529dcd4-888c-4119-a043-278789dcf4ef
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843338686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.843338686
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.827337121
Short name	T95
Test name
Test status
Simulation time	10723967432 ps
CPU time	182.63 seconds
Started	May 21 12:45:47 PM PDT 24
Finished	May 21 12:48:53 PM PDT 24
Peak memory	208968 kb
Host	smart-5401d2b9-1d42-41f4-ad3d-cefaa3684549
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827337121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.827337121
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1294380368
Short name	T317
Test name
Test status
Simulation time	13741808881 ps
CPU time	286.55 seconds
Started	May 21 12:45:48 PM PDT 24
Finished	May 21 12:50:38 PM PDT 24
Peak memory	211628 kb
Host	smart-0b130713-e0e2-405a-b546-6d0e4311b8a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1294380368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1294380368
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.202613010
Short name	T838
Test name
Test status
Simulation time	2360362006 ps
CPU time	97.03 seconds
Started	May 21 12:45:46 PM PDT 24
Finished	May 21 12:47:26 PM PDT 24
Peak memory	207952 kb
Host	smart-9fe15f5a-c44d-4483-a3fb-afe250a2124b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=202613010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand _reset.202613010
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.620492342
Short name	T22
Test name
Test status
Simulation time	8874540336 ps
CPU time	326.53 seconds
Started	May 21 12:45:46 PM PDT 24
Finished	May 21 12:51:15 PM PDT 24
Peak memory	219884 kb
Host	smart-badb8304-8424-4a95-b052-b9f20d2fc481
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=620492342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res et_error.620492342
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1336809620
Short name	T222
Test name
Test status
Simulation time	257090201 ps
CPU time	10.57 seconds
Started	May 21 12:45:48 PM PDT 24
Finished	May 21 12:46:02 PM PDT 24
Peak memory	211564 kb
Host	smart-01a1666b-8348-49d2-b5c1-83604fe0b3a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1336809620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1336809620
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3911392504
Short name	T600
Test name
Test status
Simulation time	1317826284 ps
CPU time	34.23 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:40 PM PDT 24
Peak memory	204604 kb
Host	smart-cfdd7dc9-cc13-4b42-b424-b8fd3a92ecff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3911392504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3911392504
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1489464603
Short name	T219
Test name
Test status
Simulation time	43107865830 ps
CPU time	424.57 seconds
Started	May 21 12:46:02 PM PDT 24
Finished	May 21 12:53:12 PM PDT 24
Peak memory	206300 kb
Host	smart-ace4c3a8-bf78-4fe6-bbcf-ac2bb6fdb7e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1489464603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1489464603
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3055819604
Short name	T544
Test name
Test status
Simulation time	2450088075 ps
CPU time	17.76 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:46:21 PM PDT 24
Peak memory	203876 kb
Host	smart-91351377-353e-4c3c-8c3d-76860514cd03
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3055819604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3055819604
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.3242430623
Short name	T412
Test name
Test status
Simulation time	2031392463 ps
CPU time	27.79 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:46:33 PM PDT 24
Peak memory	203408 kb
Host	smart-590c2c65-52ae-4f67-a5f0-532aa4669831
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3242430623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3242430623
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.2589723014
Short name	T185
Test name
Test status
Simulation time	128138260 ps
CPU time	3 seconds
Started	May 21 12:45:46 PM PDT 24
Finished	May 21 12:45:52 PM PDT 24
Peak memory	204052 kb
Host	smart-785ed72f-5191-4765-a203-3fff47a05799
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2589723014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2589723014
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1653519968
Short name	T399
Test name
Test status
Simulation time	135438919485 ps
CPU time	271.48 seconds
Started	May 21 12:45:56 PM PDT 24
Finished	May 21 12:50:31 PM PDT 24
Peak memory	204828 kb
Host	smart-2491cc34-ac13-49a3-b7b2-e671b1dbab55
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653519968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1653519968
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3903993900
Short name	T692
Test name
Test status
Simulation time	15209780169 ps
CPU time	107.84 seconds
Started	May 21 12:45:56 PM PDT 24
Finished	May 21 12:47:47 PM PDT 24
Peak memory	204992 kb
Host	smart-fbefdff5-0827-464a-a698-fd3d69db2480
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3903993900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3903993900
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3015527226
Short name	T493
Test name
Test status
Simulation time	217303842 ps
CPU time	15.25 seconds
Started	May 21 12:45:44 PM PDT 24
Finished	May 21 12:46:02 PM PDT 24
Peak memory	211520 kb
Host	smart-e7e61446-e843-4aac-af62-49db24b44016
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015527226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3015527226
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.66615831
Short name	T710
Test name
Test status
Simulation time	1560731482 ps
CPU time	23.71 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:46:28 PM PDT 24
Peak memory	203400 kb
Host	smart-b00152d7-a1bf-4251-8a18-c2e48709ca26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=66615831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.66615831
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.81422340
Short name	T1
Test name
Test status
Simulation time	542311032 ps
CPU time	3.25 seconds
Started	May 21 12:45:45 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	203420 kb
Host	smart-fa519912-6525-41ad-a16b-6319dfe10e58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81422340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.81422340
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2492521609
Short name	T66
Test name
Test status
Simulation time	7484946490 ps
CPU time	24.86 seconds
Started	May 21 12:45:45 PM PDT 24
Finished	May 21 12:46:12 PM PDT 24
Peak memory	203376 kb
Host	smart-479b8881-c74f-489a-bcf1-8c568e0a272d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492521609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2492521609
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2107386448
Short name	T422
Test name
Test status
Simulation time	2587046531 ps
CPU time	23.37 seconds
Started	May 21 12:45:47 PM PDT 24
Finished	May 21 12:46:14 PM PDT 24
Peak memory	203464 kb
Host	smart-d2bb5bc7-ff8e-4820-a6fe-b211b5dfa0ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2107386448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2107386448
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2928963471
Short name	T523
Test name
Test status
Simulation time	27094570 ps
CPU time	2.38 seconds
Started	May 21 12:45:46 PM PDT 24
Finished	May 21 12:45:51 PM PDT 24
Peak memory	203336 kb
Host	smart-203e8c1d-43e6-4d44-bf2c-afd882b03b28
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928963471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2928963471
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.3742351053
Short name	T641
Test name
Test status
Simulation time	2721745065 ps
CPU time	67.18 seconds
Started	May 21 12:45:56 PM PDT 24
Finished	May 21 12:47:06 PM PDT 24
Peak memory	206328 kb
Host	smart-eb2f12bb-fabe-46a0-8203-885e85b58944
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3742351053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3742351053
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2115971014
Short name	T614
Test name
Test status
Simulation time	6131957263 ps
CPU time	135.81 seconds
Started	May 21 12:45:58 PM PDT 24
Finished	May 21 12:48:19 PM PDT 24
Peak memory	207660 kb
Host	smart-4968f646-6c3b-4cd8-8008-2db9d8f84be8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2115971014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2115971014
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3184734160
Short name	T132
Test name
Test status
Simulation time	7195155845 ps
CPU time	319.14 seconds
Started	May 21 12:45:58 PM PDT 24
Finished	May 21 12:51:22 PM PDT 24
Peak memory	209752 kb
Host	smart-ea94ab9f-794a-4c07-a75f-6307c7afb0b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3184734160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3184734160
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2537433012
Short name	T849
Test name
Test status
Simulation time	327473859 ps
CPU time	92.93 seconds
Started	May 21 12:45:55 PM PDT 24
Finished	May 21 12:47:31 PM PDT 24
Peak memory	209640 kb
Host	smart-6013ba8e-d1e3-42a4-8a91-f3c0e7ce80f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2537433012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.2537433012
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1880417435
Short name	T767
Test name
Test status
Simulation time	211642828 ps
CPU time	9.15 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:15 PM PDT 24
Peak memory	211596 kb
Host	smart-335f976a-fab9-4118-97b8-ee1b337bd4f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1880417435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1880417435
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.351702084
Short name	T855
Test name
Test status
Simulation time	10754342443 ps
CPU time	57.48 seconds
Started	May 21 12:45:57 PM PDT 24
Finished	May 21 12:46:59 PM PDT 24
Peak memory	205820 kb
Host	smart-77ea4ef9-149e-45fa-ac4e-5cbafc09b252
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=351702084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.351702084
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2614771318
Short name	T263
Test name
Test status
Simulation time	69142939797 ps
CPU time	526.12 seconds
Started	May 21 12:45:56 PM PDT 24
Finished	May 21 12:54:46 PM PDT 24
Peak memory	207272 kb
Host	smart-38685427-35d3-4019-af78-95b10cd458a3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2614771318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2614771318
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4007213001
Short name	T474
Test name
Test status
Simulation time	1378168016 ps
CPU time	21.1 seconds
Started	May 21 12:46:01 PM PDT 24
Finished	May 21 12:46:28 PM PDT 24
Peak memory	204060 kb
Host	smart-c090ef3b-e222-4081-847c-e7ae99776f55
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4007213001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4007213001
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.2889813761
Short name	T631
Test name
Test status
Simulation time	196280121 ps
CPU time	13.12 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:46:17 PM PDT 24
Peak memory	203368 kb
Host	smart-34c4932d-4894-4fab-a871-953e6295fd63
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2889813761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2889813761
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.2916784450
Short name	T455
Test name
Test status
Simulation time	697508456 ps
CPU time	29.92 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:35 PM PDT 24
Peak memory	204624 kb
Host	smart-65586330-d69c-4949-9488-81b1d9fd704a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2916784450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2916784450
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2526709222
Short name	T103
Test name
Test status
Simulation time	27219203525 ps
CPU time	106.62 seconds
Started	May 21 12:45:57 PM PDT 24
Finished	May 21 12:47:48 PM PDT 24
Peak memory	205076 kb
Host	smart-7a63e58a-7eae-466f-b646-aab6e6a90c11
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526709222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2526709222
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3448351744
Short name	T92
Test name
Test status
Simulation time	8552750602 ps
CPU time	26.14 seconds
Started	May 21 12:45:57 PM PDT 24
Finished	May 21 12:46:26 PM PDT 24
Peak memory	211580 kb
Host	smart-88fec21b-d652-4558-a11d-8d8a154dba1a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3448351744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3448351744
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1735789241
Short name	T571
Test name
Test status
Simulation time	34920361 ps
CPU time	3.95 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:46:09 PM PDT 24
Peak memory	203976 kb
Host	smart-969e18d1-0be7-4dcc-9986-1c3fbd5e3200
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735789241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1735789241
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.3693689470
Short name	T5
Test name
Test status
Simulation time	858584206 ps
CPU time	19.31 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:25 PM PDT 24
Peak memory	204000 kb
Host	smart-babcf9a3-6039-45c7-b0ab-ddf37204e286
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3693689470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3693689470
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.1187025071
Short name	T506
Test name
Test status
Simulation time	239123944 ps
CPU time	3.72 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:09 PM PDT 24
Peak memory	203448 kb
Host	smart-b39d4216-2557-4e14-8d7f-8643dfff2e59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1187025071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1187025071
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3145939745
Short name	T55
Test name
Test status
Simulation time	34664682439 ps
CPU time	48.33 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:54 PM PDT 24
Peak memory	203492 kb
Host	smart-e14f0d86-c87a-4d07-bd90-8d48c34ebe7d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145939745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3145939745
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3535963797
Short name	T473
Test name
Test status
Simulation time	2623427247 ps
CPU time	23.72 seconds
Started	May 21 12:45:58 PM PDT 24
Finished	May 21 12:46:25 PM PDT 24
Peak memory	203520 kb
Host	smart-f22008bd-c717-4581-95d1-68b2c19c10f4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3535963797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3535963797
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2643125975
Short name	T622
Test name
Test status
Simulation time	60374822 ps
CPU time	2.08 seconds
Started	May 21 12:45:56 PM PDT 24
Finished	May 21 12:46:01 PM PDT 24
Peak memory	203320 kb
Host	smart-008929ca-20c3-4fb1-9b26-003afa7e2fd4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643125975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2643125975
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.254035587
Short name	T613
Test name
Test status
Simulation time	13570757662 ps
CPU time	218.82 seconds
Started	May 21 12:46:44 PM PDT 24
Finished	May 21 12:50:24 PM PDT 24
Peak memory	210032 kb
Host	smart-c21f310f-2c62-481e-b417-ea45680cc2f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=254035587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.254035587
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2895565450
Short name	T531
Test name
Test status
Simulation time	1906181386 ps
CPU time	111.34 seconds
Started	May 21 12:45:58 PM PDT 24
Finished	May 21 12:47:54 PM PDT 24
Peak memory	208412 kb
Host	smart-06f1054d-e7d8-4448-81ec-16e9305a6c1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2895565450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2895565450
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3716386508
Short name	T25
Test name
Test status
Simulation time	2176013673 ps
CPU time	103.63 seconds
Started	May 21 12:46:02 PM PDT 24
Finished	May 21 12:47:51 PM PDT 24
Peak memory	208664 kb
Host	smart-0b590324-73d5-4e3e-b05f-f71350f92f79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3716386508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3716386508
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.379110806
Short name	T778
Test name
Test status
Simulation time	87611921 ps
CPU time	13.98 seconds
Started	May 21 12:45:56 PM PDT 24
Finished	May 21 12:46:13 PM PDT 24
Peak memory	205192 kb
Host	smart-fa4af7fd-5c33-46e9-a912-b12c4771fe6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=379110806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.379110806
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3345551699
Short name	T449
Test name
Test status
Simulation time	300388258 ps
CPU time	11.17 seconds
Started	May 21 12:46:05 PM PDT 24
Finished	May 21 12:46:21 PM PDT 24
Peak memory	204140 kb
Host	smart-befdc939-119e-46c4-983e-a9350d518c68
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345551699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3345551699
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1365363575
Short name	T559
Test name
Test status
Simulation time	138959248913 ps
CPU time	627.04 seconds
Started	May 21 12:46:02 PM PDT 24
Finished	May 21 12:56:34 PM PDT 24
Peak memory	205704 kb
Host	smart-4968b890-daf1-4642-a8a2-261e00e4736a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1365363575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.1365363575
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.397974349
Short name	T712
Test name
Test status
Simulation time	154420951 ps
CPU time	12.42 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:46:17 PM PDT 24
Peak memory	203792 kb
Host	smart-ba7b3e7d-5dad-4474-8e36-45594cf82b97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=397974349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.397974349
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.307081045
Short name	T301
Test name
Test status
Simulation time	3287995881 ps
CPU time	34.47 seconds
Started	May 21 12:46:03 PM PDT 24
Finished	May 21 12:46:43 PM PDT 24
Peak memory	202928 kb
Host	smart-4a2714a2-2e13-4157-987a-74f33a292ea8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=307081045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.307081045
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.2849258668
Short name	T851
Test name
Test status
Simulation time	150882669 ps
CPU time	7.87 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:13 PM PDT 24
Peak memory	204712 kb
Host	smart-17cf63b9-43b1-46ce-8bd9-118c2cbbde48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2849258668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2849258668
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1695541732
Short name	T585
Test name
Test status
Simulation time	44832915407 ps
CPU time	243.78 seconds
Started	May 21 12:46:01 PM PDT 24
Finished	May 21 12:50:10 PM PDT 24
Peak memory	204964 kb
Host	smart-cc68ac29-293f-4af2-b4bb-e83de56e7674
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695541732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1695541732
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.822654073
Short name	T651
Test name
Test status
Simulation time	13199815348 ps
CPU time	105.81 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:47:52 PM PDT 24
Peak memory	204832 kb
Host	smart-6204486c-ba2e-4bc7-a935-e8e905da7aaa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=822654073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.822654073
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.4040294771
Short name	T293
Test name
Test status
Simulation time	363621998 ps
CPU time	21.38 seconds
Started	May 21 12:46:05 PM PDT 24
Finished	May 21 12:46:31 PM PDT 24
Peak memory	204608 kb
Host	smart-f0437817-c6a6-410b-8b41-09da8cf70ce5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040294771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4040294771
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2788709803
Short name	T835
Test name
Test status
Simulation time	1423948165 ps
CPU time	26.6 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:32 PM PDT 24
Peak memory	204008 kb
Host	smart-6e6f3403-aa1a-48e9-8f50-1320a3d814f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2788709803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2788709803
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.3030262501
Short name	T322
Test name
Test status
Simulation time	32910171 ps
CPU time	2.27 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:08 PM PDT 24
Peak memory	203436 kb
Host	smart-65de708f-2ab4-4799-93a3-0983a5a93603
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3030262501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3030262501
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3936174223
Short name	T816
Test name
Test status
Simulation time	4407374592 ps
CPU time	20.29 seconds
Started	May 21 12:46:01 PM PDT 24
Finished	May 21 12:46:26 PM PDT 24
Peak memory	203384 kb
Host	smart-2ce4d2b2-15a7-4c1b-ae6b-c1c82452c4dd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936174223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3936174223
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1477202580
Short name	T556
Test name
Test status
Simulation time	2859394989 ps
CPU time	24.7 seconds
Started	May 21 12:46:02 PM PDT 24
Finished	May 21 12:46:32 PM PDT 24
Peak memory	203496 kb
Host	smart-4593db4e-07b1-4a33-a3b6-713b0b877256
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1477202580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1477202580
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1705178757
Short name	T733
Test name
Test status
Simulation time	109595847 ps
CPU time	2.69 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:09 PM PDT 24
Peak memory	203440 kb
Host	smart-1926637b-ea5a-4ada-be4d-67525a916dfd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705178757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1705178757
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.3704601393
Short name	T210
Test name
Test status
Simulation time	1200643564 ps
CPU time	120.56 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:48:05 PM PDT 24
Peak memory	210060 kb
Host	smart-ef31fc41-4ae4-4784-b7b2-ab3c8dae2ac8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3704601393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3704601393
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.288838563
Short name	T183
Test name
Test status
Simulation time	17238494999 ps
CPU time	162.76 seconds
Started	May 21 12:46:01 PM PDT 24
Finished	May 21 12:48:50 PM PDT 24
Peak memory	206780 kb
Host	smart-1cb92fdf-5efe-4d67-ac6f-1e005c4f2ad3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=288838563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.288838563
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1312465991
Short name	T203
Test name
Test status
Simulation time	793067836 ps
CPU time	222.52 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:49:49 PM PDT 24
Peak memory	209876 kb
Host	smart-6c935017-6eb3-4be0-98e5-b03c3f73f251
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1312465991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1312465991
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.406993274
Short name	T302
Test name
Test status
Simulation time	260539185 ps
CPU time	87.28 seconds
Started	May 21 12:46:04 PM PDT 24
Finished	May 21 12:47:36 PM PDT 24
Peak memory	209188 kb
Host	smart-f5b5aeea-3ee8-4c9e-a863-d0edb0673499
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=406993274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res et_error.406993274
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1595748710
Short name	T875
Test name
Test status
Simulation time	143358163 ps
CPU time	13.19 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:19 PM PDT 24
Peak memory	204796 kb
Host	smart-dc6d6d4c-7382-453d-a22b-33151263f4e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1595748710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1595748710
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2444368411
Short name	T192
Test name
Test status
Simulation time	1668862409 ps
CPU time	46.68 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:53 PM PDT 24
Peak memory	205388 kb
Host	smart-1af54074-dba5-42f9-adc4-6a7cd14100e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2444368411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2444368411
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1720388215
Short name	T380
Test name
Test status
Simulation time	13090120303 ps
CPU time	89.74 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:47:36 PM PDT 24
Peak memory	205076 kb
Host	smart-b4d894f7-ea3d-4d4c-9dd6-369ec060ec13
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1720388215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1720388215
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1603661199
Short name	T562
Test name
Test status
Simulation time	261688035 ps
CPU time	20.44 seconds
Started	May 21 12:46:08 PM PDT 24
Finished	May 21 12:46:33 PM PDT 24
Peak memory	203536 kb
Host	smart-f80a7a03-183b-4167-ab36-6616dbaef790
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1603661199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1603661199
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.1635876133
Short name	T732
Test name
Test status
Simulation time	99360331 ps
CPU time	7.96 seconds
Started	May 21 12:46:08 PM PDT 24
Finished	May 21 12:46:20 PM PDT 24
Peak memory	203452 kb
Host	smart-a9591271-ed01-42da-acc3-590afa9b5007
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1635876133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1635876133
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.222912967
Short name	T724
Test name
Test status
Simulation time	234359648 ps
CPU time	15 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:21 PM PDT 24
Peak memory	211600 kb
Host	smart-2385652a-6709-4e31-b8d4-f2edf9a25aa5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=222912967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.222912967
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.4267438999
Short name	T772
Test name
Test status
Simulation time	17692891686 ps
CPU time	88.32 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:47:34 PM PDT 24
Peak memory	204924 kb
Host	smart-3dbfc756-cf32-4814-a172-51dc31547563
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267438999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.4267438999
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.695514687
Short name	T278
Test name
Test status
Simulation time	8532161092 ps
CPU time	36.79 seconds
Started	May 21 12:46:04 PM PDT 24
Finished	May 21 12:46:45 PM PDT 24
Peak memory	204024 kb
Host	smart-99035810-ce37-4341-a037-6e745d10013d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=695514687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.695514687
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1449445808
Short name	T451
Test name
Test status
Simulation time	171139493 ps
CPU time	14.88 seconds
Started	May 21 12:46:04 PM PDT 24
Finished	May 21 12:46:24 PM PDT 24
Peak memory	204892 kb
Host	smart-db9c579f-abb4-4ab4-a780-75e102def3b8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449445808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1449445808
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.2077539
Short name	T856
Test name
Test status
Simulation time	1822697427 ps
CPU time	36.13 seconds
Started	May 21 12:46:06 PM PDT 24
Finished	May 21 12:46:47 PM PDT 24
Peak memory	203428 kb
Host	smart-1b8c3c04-087c-4c8c-844d-58b5849dbdf1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2077539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2077539
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.2979016430
Short name	T56
Test name
Test status
Simulation time	458744515 ps
CPU time	3.63 seconds
Started	May 21 12:46:02 PM PDT 24
Finished	May 21 12:46:11 PM PDT 24
Peak memory	203344 kb
Host	smart-a0366d7c-d8f7-4307-854e-02f9500f08db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979016430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2979016430
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2628935507
Short name	T325
Test name
Test status
Simulation time	3953045878 ps
CPU time	22.25 seconds
Started	May 21 12:46:02 PM PDT 24
Finished	May 21 12:46:29 PM PDT 24
Peak memory	203492 kb
Host	smart-e482bff9-928e-4f65-bf9c-a62fb9f5d74f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628935507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2628935507
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1363088632
Short name	T299
Test name
Test status
Simulation time	4067610204 ps
CPU time	23.9 seconds
Started	May 21 12:46:00 PM PDT 24
Finished	May 21 12:46:30 PM PDT 24
Peak memory	203464 kb
Host	smart-ecf05eeb-1a64-4d57-bfba-a4bb5b66f679
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1363088632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1363088632
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1394785834
Short name	T605
Test name
Test status
Simulation time	70851108 ps
CPU time	2.56 seconds
Started	May 21 12:45:59 PM PDT 24
Finished	May 21 12:46:07 PM PDT 24
Peak memory	203424 kb
Host	smart-629f5990-d3d3-4c08-a3a7-7b4314a37815
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394785834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1394785834
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.1353949716
Short name	T578
Test name
Test status
Simulation time	1459486030 ps
CPU time	157.46 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:48:53 PM PDT 24
Peak memory	205976 kb
Host	smart-fde530b4-76fb-4cfd-9f84-afbafe35dc96
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1353949716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1353949716
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1358648839
Short name	T545
Test name
Test status
Simulation time	1104057271 ps
CPU time	79.31 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:47:31 PM PDT 24
Peak memory	211520 kb
Host	smart-80b97877-83e6-4be0-95fd-70d37e92f628
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1358648839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1358648839
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.101248307
Short name	T217
Test name
Test status
Simulation time	7903054562 ps
CPU time	375.89 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:52:27 PM PDT 24
Peak memory	211584 kb
Host	smart-5b45660f-6a2b-4275-9472-79a9fd05650f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=101248307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.101248307
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3405152385
Short name	T253
Test name
Test status
Simulation time	476173851 ps
CPU time	127.69 seconds
Started	May 21 12:46:08 PM PDT 24
Finished	May 21 12:48:20 PM PDT 24
Peak memory	210292 kb
Host	smart-82104a45-4e59-4010-bb58-71094b5c7bbb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3405152385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3405152385
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.102512674
Short name	T615
Test name
Test status
Simulation time	44681163 ps
CPU time	5.27 seconds
Started	May 21 12:46:09 PM PDT 24
Finished	May 21 12:46:18 PM PDT 24
Peak memory	204800 kb
Host	smart-4ed21ae1-7902-4aa4-a481-0ae7a45d9a04
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=102512674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.102512674
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3457033929
Short name	T57
Test name
Test status
Simulation time	388389550 ps
CPU time	11.3 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:46:27 PM PDT 24
Peak memory	204500 kb
Host	smart-c0afc547-3fdd-4baf-b02a-17f25018af52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3457033929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3457033929
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3761488275
Short name	T748
Test name
Test status
Simulation time	273395072196 ps
CPU time	810.06 seconds
Started	May 21 12:46:10 PM PDT 24
Finished	May 21 12:59:44 PM PDT 24
Peak memory	207568 kb
Host	smart-265f6d6b-913e-4369-a6eb-15c60d9c4c54
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3761488275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3761488275
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3853668198
Short name	T637
Test name
Test status
Simulation time	894615594 ps
CPU time	6.25 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:46:18 PM PDT 24
Peak memory	203652 kb
Host	smart-035e73c1-1911-4190-a716-7c7716bf7cb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3853668198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3853668198
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.4189347005
Short name	T341
Test name
Test status
Simulation time	2515178581 ps
CPU time	34.86 seconds
Started	May 21 12:46:08 PM PDT 24
Finished	May 21 12:46:47 PM PDT 24
Peak memory	203504 kb
Host	smart-d4e65c1f-304a-4e92-a133-f2e9e22167f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4189347005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4189347005
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.1765473162
Short name	T791
Test name
Test status
Simulation time	1096636882 ps
CPU time	27.79 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:46:43 PM PDT 24
Peak memory	204444 kb
Host	smart-184897bd-003a-4bf0-8cd8-5922b68838ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1765473162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1765473162
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.473045806
Short name	T707
Test name
Test status
Simulation time	95435023923 ps
CPU time	256.67 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:50:29 PM PDT 24
Peak memory	205752 kb
Host	smart-5929ab19-3d17-4599-a11b-e86cd4349f0d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=473045806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.473045806
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1797655262
Short name	T823
Test name
Test status
Simulation time	6671723445 ps
CPU time	47.14 seconds
Started	May 21 12:46:08 PM PDT 24
Finished	May 21 12:47:00 PM PDT 24
Peak memory	204524 kb
Host	smart-a9584c08-e5ee-4914-8bd1-3214622d3ab5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1797655262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1797655262
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1034401135
Short name	T67
Test name
Test status
Simulation time	276867970 ps
CPU time	26.83 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:46:38 PM PDT 24
Peak memory	211540 kb
Host	smart-13afe460-30f0-493c-9afa-c0d7c5e23893
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034401135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1034401135
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.928934698
Short name	T706
Test name
Test status
Simulation time	147288820 ps
CPU time	12.11 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:46:24 PM PDT 24
Peak memory	203468 kb
Host	smart-f3976f3e-2bce-4522-9a31-1160b421c04e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=928934698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.928934698
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.2205341324
Short name	T756
Test name
Test status
Simulation time	560878844 ps
CPU time	4.14 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:46:17 PM PDT 24
Peak memory	203452 kb
Host	smart-c1a937be-04d3-4d46-a1fd-ce3517de388d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2205341324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2205341324
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3790179547
Short name	T276
Test name
Test status
Simulation time	3964977854 ps
CPU time	23.89 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:46:36 PM PDT 24
Peak memory	203492 kb
Host	smart-c56cdba7-de4c-4369-a710-dcde4a7276e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790179547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3790179547
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3162313461
Short name	T280
Test name
Test status
Simulation time	5122491476 ps
CPU time	40.4 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:46:52 PM PDT 24
Peak memory	203356 kb
Host	smart-67370527-7b3e-4ba7-b376-52bcc38c57fa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3162313461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3162313461
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2862323409
Short name	T384
Test name
Test status
Simulation time	47835550 ps
CPU time	2.3 seconds
Started	May 21 12:46:08 PM PDT 24
Finished	May 21 12:46:15 PM PDT 24
Peak memory	203456 kb
Host	smart-e2257e05-de75-4562-a58a-5048fd4ea0dd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862323409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2862323409
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.2286461875
Short name	T121
Test name
Test status
Simulation time	21464843039 ps
CPU time	212.38 seconds
Started	May 21 12:46:06 PM PDT 24
Finished	May 21 12:49:43 PM PDT 24
Peak memory	207852 kb
Host	smart-df1aef74-5eae-4647-9d41-4668addfdf41
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2286461875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2286461875
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1409518577
Short name	T844
Test name
Test status
Simulation time	12934587806 ps
CPU time	170.45 seconds
Started	May 21 12:46:11 PM PDT 24
Finished	May 21 12:49:05 PM PDT 24
Peak memory	211676 kb
Host	smart-c8c31a56-28b0-4c9e-910d-afa2036b0352
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1409518577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1409518577
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.327435676
Short name	T699
Test name
Test status
Simulation time	676193641 ps
CPU time	119.27 seconds
Started	May 21 12:46:07 PM PDT 24
Finished	May 21 12:48:11 PM PDT 24
Peak memory	208200 kb
Host	smart-6097db5f-8465-42eb-a9f7-723684cc3d48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=327435676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand _reset.327435676
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.245342257
Short name	T490
Test name
Test status
Simulation time	222136069 ps
CPU time	47.19 seconds
Started	May 21 12:46:09 PM PDT 24
Finished	May 21 12:47:01 PM PDT 24
Peak memory	207692 kb
Host	smart-e955358b-5483-4c38-b288-54a4c1cc04a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=245342257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res et_error.245342257
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.4200976871
Short name	T794
Test name
Test status
Simulation time	144459570 ps
CPU time	10.39 seconds
Started	May 21 12:46:09 PM PDT 24
Finished	May 21 12:46:23 PM PDT 24
Peak memory	204984 kb
Host	smart-c2766188-3e48-4e49-bdb9-09defdff6478
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4200976871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4200976871
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.746921360
Short name	T99
Test name
Test status
Simulation time	1500225062 ps
CPU time	14.62 seconds
Started	May 21 12:46:13 PM PDT 24
Finished	May 21 12:46:31 PM PDT 24
Peak memory	204544 kb
Host	smart-972c9c74-ce11-4dd9-9661-63c6c65f304c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=746921360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.746921360
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1897395713
Short name	T863
Test name
Test status
Simulation time	19208018365 ps
CPU time	142.83 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:48:38 PM PDT 24
Peak memory	206204 kb
Host	smart-58b319f6-ba78-4dd7-8e8a-a66009597182
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1897395713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.1897395713
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2944934674
Short name	T824
Test name
Test status
Simulation time	87383589 ps
CPU time	10.47 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:46:26 PM PDT 24
Peak memory	203676 kb
Host	smart-6ae0d240-1539-4106-961e-dcd4a8acaeab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2944934674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2944934674
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.1005019510
Short name	T643
Test name
Test status
Simulation time	255855957 ps
CPU time	9.35 seconds
Started	May 21 12:46:13 PM PDT 24
Finished	May 21 12:46:26 PM PDT 24
Peak memory	203332 kb
Host	smart-bfb9d5ac-6ad9-4b82-8def-19f710fe1647
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1005019510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1005019510
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.3655407603
Short name	T129
Test name
Test status
Simulation time	140773357 ps
CPU time	13.84 seconds
Started	May 21 12:46:15 PM PDT 24
Finished	May 21 12:46:32 PM PDT 24
Peak memory	204624 kb
Host	smart-f3002330-b75d-4f68-9fd1-1d5aef3d52b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3655407603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3655407603
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2210938265
Short name	T565
Test name
Test status
Simulation time	36183381090 ps
CPU time	224.58 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:50:00 PM PDT 24
Peak memory	211712 kb
Host	smart-91f3a90b-e745-4c1e-b557-5e5ef0cc44a7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210938265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2210938265
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2984545970
Short name	T227
Test name
Test status
Simulation time	60189227492 ps
CPU time	147.12 seconds
Started	May 21 12:46:15 PM PDT 24
Finished	May 21 12:48:45 PM PDT 24
Peak memory	204632 kb
Host	smart-944150c4-dcca-404f-89e7-00fd897b0f3b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2984545970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2984545970
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1187428351
Short name	T402
Test name
Test status
Simulation time	451316962 ps
CPU time	24.83 seconds
Started	May 21 12:46:14 PM PDT 24
Finished	May 21 12:46:42 PM PDT 24
Peak memory	204872 kb
Host	smart-8fb68ddf-5fd9-4fea-9f9d-3ed456bc6233
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187428351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1187428351
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.3322804729
Short name	T850
Test name
Test status
Simulation time	497439997 ps
CPU time	8.42 seconds
Started	May 21 12:46:13 PM PDT 24
Finished	May 21 12:46:25 PM PDT 24
Peak memory	203452 kb
Host	smart-0fce40cc-9d94-4694-9c89-55b197c1e540
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3322804729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3322804729
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.1539346665
Short name	T182
Test name
Test status
Simulation time	464124776 ps
CPU time	4.38 seconds
Started	May 21 12:46:13 PM PDT 24
Finished	May 21 12:46:20 PM PDT 24
Peak memory	203420 kb
Host	smart-28311c2c-383a-4726-ae07-1fdfe07c8f6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1539346665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1539346665
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.4036509784
Short name	T736
Test name
Test status
Simulation time	5182439867 ps
CPU time	26.53 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:46:42 PM PDT 24
Peak memory	203452 kb
Host	smart-2018567c-113e-4374-a939-33580890f29e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036509784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.4036509784
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3341773123
Short name	T211
Test name
Test status
Simulation time	15506365481 ps
CPU time	43.1 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:46:59 PM PDT 24
Peak memory	203476 kb
Host	smart-c2f956e4-01cf-4c62-a68a-958c0f014999
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3341773123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3341773123
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.372397334
Short name	T511
Test name
Test status
Simulation time	45670341 ps
CPU time	2.2 seconds
Started	May 21 12:46:14 PM PDT 24
Finished	May 21 12:46:19 PM PDT 24
Peak memory	203424 kb
Host	smart-fc9d363f-761d-475d-bae3-7f4923b6e337
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372397334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.372397334
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.1238649944
Short name	T876
Test name
Test status
Simulation time	1241959647 ps
CPU time	44.58 seconds
Started	May 21 12:46:13 PM PDT 24
Finished	May 21 12:47:01 PM PDT 24
Peak memory	205308 kb
Host	smart-a8201818-1e86-4d93-bf69-cc5327ee41f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238649944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1238649944
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3251518913
Short name	T319
Test name
Test status
Simulation time	544694863 ps
CPU time	15.86 seconds
Started	May 21 12:46:14 PM PDT 24
Finished	May 21 12:46:33 PM PDT 24
Peak memory	203568 kb
Host	smart-ffa989e3-0bcc-48dc-87c0-97f6b18b3698
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3251518913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3251518913
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.756436577
Short name	T874
Test name
Test status
Simulation time	310815888 ps
CPU time	139.59 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:48:41 PM PDT 24
Peak memory	208160 kb
Host	smart-c3537e89-b7d2-4f8b-97ef-678972597602
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=756436577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand _reset.756436577
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.44081211
Short name	T195
Test name
Test status
Simulation time	6792206113 ps
CPU time	140.81 seconds
Started	May 21 12:46:15 PM PDT 24
Finished	May 21 12:48:39 PM PDT 24
Peak memory	210068 kb
Host	smart-eb0b1a8c-991b-4575-8658-2b32c0436797
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=44081211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rese t_error.44081211
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2077793298
Short name	T382
Test name
Test status
Simulation time	153195425 ps
CPU time	19.11 seconds
Started	May 21 12:46:14 PM PDT 24
Finished	May 21 12:46:36 PM PDT 24
Peak memory	204828 kb
Host	smart-322825b9-4623-43bb-9f83-6bd9d4a00d52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2077793298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2077793298
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.117960815
Short name	T240
Test name
Test status
Simulation time	267873511 ps
CPU time	36.81 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:44:17 PM PDT 24
Peak memory	204564 kb
Host	smart-f1204270-58c0-4c98-8b27-c9270f4f27e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117960815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.117960815
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.959101979
Short name	T223
Test name
Test status
Simulation time	19180069709 ps
CPU time	162.36 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:46:24 PM PDT 24
Peak memory	211708 kb
Host	smart-4e51febe-a2d1-45b6-91f2-76a8db6515ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=959101979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.959101979
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3690409931
Short name	T684
Test name
Test status
Simulation time	22898318 ps
CPU time	2.46 seconds
Started	May 21 12:43:37 PM PDT 24
Finished	May 21 12:43:42 PM PDT 24
Peak memory	203460 kb
Host	smart-942db209-ecb2-4f82-8c89-4d8b8590cfb4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3690409931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3690409931
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.3694636583
Short name	T168
Test name
Test status
Simulation time	2189620759 ps
CPU time	23.93 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:44:13 PM PDT 24
Peak memory	203408 kb
Host	smart-7b084cfc-eec9-4b69-b740-04f7fd995b11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3694636583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3694636583
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.544214514
Short name	T420
Test name
Test status
Simulation time	412642947 ps
CPU time	23.27 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:43:57 PM PDT 24
Peak memory	204936 kb
Host	smart-45c5feec-a0bf-4185-af48-dd920a41853f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=544214514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.544214514
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2317647768
Short name	T784
Test name
Test status
Simulation time	9813849842 ps
CPU time	61.82 seconds
Started	May 21 12:43:42 PM PDT 24
Finished	May 21 12:44:47 PM PDT 24
Peak memory	211596 kb
Host	smart-cabd6336-589c-4238-9704-517dc20c9dea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317647768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2317647768
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2723422363
Short name	T626
Test name
Test status
Simulation time	30057172446 ps
CPU time	193.31 seconds
Started	May 21 12:43:40 PM PDT 24
Finished	May 21 12:46:58 PM PDT 24
Peak memory	205144 kb
Host	smart-7f54a858-a6da-405e-a63e-afdab746b552
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2723422363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2723422363
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.556797264
Short name	T386
Test name
Test status
Simulation time	281909728 ps
CPU time	24.01 seconds
Started	May 21 12:43:37 PM PDT 24
Finished	May 21 12:44:03 PM PDT 24
Peak memory	211656 kb
Host	smart-1b00a46f-ab9f-4b00-8e3f-9ba78e34a5f8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556797264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.556797264
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.1896500912
Short name	T729
Test name
Test status
Simulation time	277296100 ps
CPU time	5.06 seconds
Started	May 21 12:43:39 PM PDT 24
Finished	May 21 12:43:48 PM PDT 24
Peak memory	203568 kb
Host	smart-8e332a78-f5a4-4bc8-8394-4664ce9eb32c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1896500912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1896500912
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.2740985617
Short name	T763
Test name
Test status
Simulation time	50218394 ps
CPU time	2.48 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:43:37 PM PDT 24
Peak memory	203400 kb
Host	smart-fdf9a493-d44a-4c20-bc31-3cc08960dc59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2740985617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2740985617
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2425002488
Short name	T456
Test name
Test status
Simulation time	23886962645 ps
CPU time	40.13 seconds
Started	May 21 12:43:33 PM PDT 24
Finished	May 21 12:44:15 PM PDT 24
Peak memory	203464 kb
Host	smart-245d097a-85c4-4a06-9e7e-b4570db1c7dd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425002488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2425002488
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1758720813
Short name	T580
Test name
Test status
Simulation time	14048001675 ps
CPU time	38.68 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:44:13 PM PDT 24
Peak memory	203464 kb
Host	smart-10ca1938-4175-4a25-af60-bbf7ce94c4ee
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1758720813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1758720813
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2037286880
Short name	T126
Test name
Test status
Simulation time	64681223 ps
CPU time	2.35 seconds
Started	May 21 12:43:31 PM PDT 24
Finished	May 21 12:43:36 PM PDT 24
Peak memory	203424 kb
Host	smart-9722de81-06de-487e-88c9-75a3da0953c8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037286880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2037286880
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.3155586638
Short name	T49
Test name
Test status
Simulation time	6010162776 ps
CPU time	54.39 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:44:35 PM PDT 24
Peak memory	206356 kb
Host	smart-43dd5e46-e273-4ea1-8a4b-a8eb2fdeae4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3155586638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3155586638
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2712032128
Short name	T801
Test name
Test status
Simulation time	570580155 ps
CPU time	39.89 seconds
Started	May 21 12:43:37 PM PDT 24
Finished	May 21 12:44:19 PM PDT 24
Peak memory	205500 kb
Host	smart-8a2d69c1-4404-44f1-b1e0-3c3202774e52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2712032128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2712032128
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4131039816
Short name	T401
Test name
Test status
Simulation time	447958451 ps
CPU time	117.62 seconds
Started	May 21 12:43:40 PM PDT 24
Finished	May 21 12:45:41 PM PDT 24
Peak memory	208528 kb
Host	smart-a08c7abd-1fd2-4438-b42f-fe8f95afd0f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4131039816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.4131039816
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1511130494
Short name	T546
Test name
Test status
Simulation time	6267223695 ps
CPU time	336.47 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:49:17 PM PDT 24
Peak memory	219888 kb
Host	smart-fa3bbcc4-3c9f-4bf1-8dd9-2121cebc2e74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1511130494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1511130494
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.4101314548
Short name	T323
Test name
Test status
Simulation time	401793586 ps
CPU time	12.01 seconds
Started	May 21 12:43:36 PM PDT 24
Finished	May 21 12:43:51 PM PDT 24
Peak memory	211616 kb
Host	smart-9c15c178-a178-438a-9dc4-2530303af999
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4101314548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.4101314548
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1481089801
Short name	T238
Test name
Test status
Simulation time	129564899 ps
CPU time	6.05 seconds
Started	May 21 12:46:17 PM PDT 24
Finished	May 21 12:46:25 PM PDT 24
Peak memory	203476 kb
Host	smart-bedff05c-5d81-4f09-89c0-f49c01ce2c44
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1481089801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1481089801
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.213394470
Short name	T184
Test name
Test status
Simulation time	66657345408 ps
CPU time	404.64 seconds
Started	May 21 12:46:18 PM PDT 24
Finished	May 21 12:53:05 PM PDT 24
Peak memory	206000 kb
Host	smart-0f11debf-3ff7-4589-baa0-1c7278d8d3a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=213394470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo w_rsp.213394470
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4040131030
Short name	T331
Test name
Test status
Simulation time	193854982 ps
CPU time	5.55 seconds
Started	May 21 12:46:25 PM PDT 24
Finished	May 21 12:46:32 PM PDT 24
Peak memory	203384 kb
Host	smart-dcbd0846-7fc5-4b0c-a8cb-0b4e8997fe65
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040131030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4040131030
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.1897414892
Short name	T409
Test name
Test status
Simulation time	205217807 ps
CPU time	8.9 seconds
Started	May 21 12:46:21 PM PDT 24
Finished	May 21 12:46:32 PM PDT 24
Peak memory	203416 kb
Host	smart-66a94744-8709-48eb-925d-217e3cd6bc33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1897414892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1897414892
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.3068001265
Short name	T650
Test name
Test status
Simulation time	341107785 ps
CPU time	23.36 seconds
Started	May 21 12:46:13 PM PDT 24
Finished	May 21 12:46:39 PM PDT 24
Peak memory	204772 kb
Host	smart-b774a45a-fc05-4b90-aefb-dc909dc2b36d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3068001265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3068001265
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.592907419
Short name	T750
Test name
Test status
Simulation time	130946044431 ps
CPU time	133.01 seconds
Started	May 21 12:46:15 PM PDT 24
Finished	May 21 12:48:31 PM PDT 24
Peak memory	204844 kb
Host	smart-6551731d-4d01-4414-aff6-a9d8da7acb39
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=592907419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.592907419
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1191852532
Short name	T447
Test name
Test status
Simulation time	10367835647 ps
CPU time	53.04 seconds
Started	May 21 12:46:22 PM PDT 24
Finished	May 21 12:47:17 PM PDT 24
Peak memory	204708 kb
Host	smart-bb626b09-9fbb-44cc-b750-ec73d5210bcf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1191852532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1191852532
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1773237618
Short name	T308
Test name
Test status
Simulation time	369762247 ps
CPU time	18.08 seconds
Started	May 21 12:46:14 PM PDT 24
Finished	May 21 12:46:35 PM PDT 24
Peak memory	204664 kb
Host	smart-22f61e9d-c435-4cbc-8dab-daccd28974ff
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773237618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1773237618
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.3191830007
Short name	T387
Test name
Test status
Simulation time	122681741 ps
CPU time	9.1 seconds
Started	May 21 12:46:19 PM PDT 24
Finished	May 21 12:46:30 PM PDT 24
Peak memory	203984 kb
Host	smart-6c922164-24eb-4386-a55a-ba83181a5ac3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3191830007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3191830007
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.804141630
Short name	T517
Test name
Test status
Simulation time	154532703 ps
CPU time	2.43 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:46:25 PM PDT 24
Peak memory	203288 kb
Host	smart-6be25729-4cc0-4558-bbb8-15ae293db480
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=804141630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.804141630
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2439948808
Short name	T608
Test name
Test status
Simulation time	9838836784 ps
CPU time	33.36 seconds
Started	May 21 12:46:12 PM PDT 24
Finished	May 21 12:46:49 PM PDT 24
Peak memory	203444 kb
Host	smart-411b5307-0afd-4e5d-b261-092d5b5d10d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439948808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2439948808
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2633573452
Short name	T854
Test name
Test status
Simulation time	3173134606 ps
CPU time	27.8 seconds
Started	May 21 12:46:13 PM PDT 24
Finished	May 21 12:46:44 PM PDT 24
Peak memory	203472 kb
Host	smart-f8ab0269-9003-4a62-b33a-0b3f182a004f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2633573452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2633573452
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.4055290056
Short name	T127
Test name
Test status
Simulation time	96455043 ps
CPU time	2.44 seconds
Started	May 21 12:46:15 PM PDT 24
Finished	May 21 12:46:20 PM PDT 24
Peak memory	203292 kb
Host	smart-a385bbb9-a4b6-4327-9ff9-9fec6133dee8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055290056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.4055290056
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.844745861
Short name	T145
Test name
Test status
Simulation time	5195138366 ps
CPU time	78.92 seconds
Started	May 21 12:46:19 PM PDT 24
Finished	May 21 12:47:40 PM PDT 24
Peak memory	206804 kb
Host	smart-37be9461-9fe1-4824-8cc3-bd3e5ef428bd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=844745861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.844745861
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3794243593
Short name	T663
Test name
Test status
Simulation time	11979139508 ps
CPU time	170.68 seconds
Started	May 21 12:46:22 PM PDT 24
Finished	May 21 12:49:14 PM PDT 24
Peak memory	206768 kb
Host	smart-f776dac6-2815-4072-b92f-9879be2c05cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3794243593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3794243593
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1399138823
Short name	T15
Test name
Test status
Simulation time	2661626139 ps
CPU time	363.65 seconds
Started	May 21 12:46:22 PM PDT 24
Finished	May 21 12:52:27 PM PDT 24
Peak memory	219852 kb
Host	smart-40d559ad-e4f9-4be3-86d1-5d361b7118e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399138823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.1399138823
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1205320563
Short name	T593
Test name
Test status
Simulation time	790590204 ps
CPU time	23.61 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:46:45 PM PDT 24
Peak memory	211648 kb
Host	smart-4b2b6f5b-a9cc-4042-a6ad-4b38c50e717b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1205320563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1205320563
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.4220099044
Short name	T178
Test name
Test status
Simulation time	4454402238 ps
CPU time	49.24 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:47:12 PM PDT 24
Peak memory	211652 kb
Host	smart-36d24b5b-44ba-4fa9-8bfe-d6d2fbf873fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4220099044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.4220099044
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1464704465
Short name	T93
Test name
Test status
Simulation time	21353445461 ps
CPU time	113.34 seconds
Started	May 21 12:46:22 PM PDT 24
Finished	May 21 12:48:17 PM PDT 24
Peak memory	206280 kb
Host	smart-b3c9fda9-c540-4053-bfd1-08ceeadb69bf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1464704465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1464704465
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3532736646
Short name	T510
Test name
Test status
Simulation time	117895356 ps
CPU time	11.86 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:46:34 PM PDT 24
Peak memory	203720 kb
Host	smart-70561872-ceca-47ac-a8a6-2b3229fe5ece
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3532736646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3532736646
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.232223245
Short name	T520
Test name
Test status
Simulation time	480553886 ps
CPU time	17.09 seconds
Started	May 21 12:46:19 PM PDT 24
Finished	May 21 12:46:38 PM PDT 24
Peak memory	203608 kb
Host	smart-e190c443-29e6-4c9f-ba0b-bea6c01e3a32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=232223245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.232223245
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.2738776308
Short name	T392
Test name
Test status
Simulation time	273446222 ps
CPU time	18.53 seconds
Started	May 21 12:46:18 PM PDT 24
Finished	May 21 12:46:38 PM PDT 24
Peak memory	204748 kb
Host	smart-a8a46a4f-86fc-4805-90e2-ece71c2a1cef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738776308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2738776308
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3335456034
Short name	T328
Test name
Test status
Simulation time	9094924951 ps
CPU time	14.41 seconds
Started	May 21 12:46:18 PM PDT 24
Finished	May 21 12:46:33 PM PDT 24
Peak memory	203524 kb
Host	smart-e934ebaa-b338-4c87-a457-c8b967e07fbf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335456034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3335456034
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.969894167
Short name	T806
Test name
Test status
Simulation time	54565817561 ps
CPU time	245.5 seconds
Started	May 21 12:46:22 PM PDT 24
Finished	May 21 12:50:29 PM PDT 24
Peak memory	204516 kb
Host	smart-78519de9-cc83-43fc-8a0a-6d3ba14082d6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=969894167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.969894167
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2572332255
Short name	T737
Test name
Test status
Simulation time	50589075 ps
CPU time	9.15 seconds
Started	May 21 12:46:19 PM PDT 24
Finished	May 21 12:46:30 PM PDT 24
Peak memory	204556 kb
Host	smart-7b19d1e2-8feb-4d5b-999a-02dd6cec058c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572332255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2572332255
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.2898053790
Short name	T329
Test name
Test status
Simulation time	131199860 ps
CPU time	6.59 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:46:29 PM PDT 24
Peak memory	203880 kb
Host	smart-9b8eb04f-400c-4569-bd09-7d7aa77f96a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2898053790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2898053790
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.4089192054
Short name	T526
Test name
Test status
Simulation time	48995345 ps
CPU time	2.32 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:46:25 PM PDT 24
Peak memory	203300 kb
Host	smart-4fbfe7d8-91be-4a98-9c3f-6f45dd2d7dfc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4089192054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.4089192054
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3789241234
Short name	T321
Test name
Test status
Simulation time	19655336862 ps
CPU time	34.33 seconds
Started	May 21 12:46:21 PM PDT 24
Finished	May 21 12:46:57 PM PDT 24
Peak memory	203452 kb
Host	smart-f2e5fc64-620f-4ee3-a969-af2f95527f0d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789241234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3789241234
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4025994933
Short name	T150
Test name
Test status
Simulation time	14602592914 ps
CPU time	36.83 seconds
Started	May 21 12:46:19 PM PDT 24
Finished	May 21 12:46:58 PM PDT 24
Peak memory	203496 kb
Host	smart-dc9dbd1a-fcde-412b-aade-188a4f805310
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4025994933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4025994933
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3105552286
Short name	T590
Test name
Test status
Simulation time	38802229 ps
CPU time	2.33 seconds
Started	May 21 12:46:25 PM PDT 24
Finished	May 21 12:46:28 PM PDT 24
Peak memory	203288 kb
Host	smart-f4f7cb0c-da32-4cc4-b926-4214b6cea66f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105552286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3105552286
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.1990614600
Short name	T703
Test name
Test status
Simulation time	5162444579 ps
CPU time	138.88 seconds
Started	May 21 12:46:20 PM PDT 24
Finished	May 21 12:48:41 PM PDT 24
Peak memory	208484 kb
Host	smart-214886d4-374d-4e88-b98f-a8a98945aded
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990614600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1990614600
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2724502911
Short name	T848
Test name
Test status
Simulation time	2983842532 ps
CPU time	66.11 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:47:37 PM PDT 24
Peak memory	205676 kb
Host	smart-2fc4ea0a-3c35-4ac5-865e-47502d23f886
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2724502911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2724502911
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1582083407
Short name	T740
Test name
Test status
Simulation time	532489818 ps
CPU time	260.51 seconds
Started	May 21 12:46:29 PM PDT 24
Finished	May 21 12:50:52 PM PDT 24
Peak memory	209348 kb
Host	smart-67b7458e-fe6d-431d-a251-ab763a9b1789
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1582083407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1582083407
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2246213757
Short name	T104
Test name
Test status
Simulation time	6732569237 ps
CPU time	234.42 seconds
Started	May 21 12:46:29 PM PDT 24
Finished	May 21 12:50:25 PM PDT 24
Peak memory	210244 kb
Host	smart-931ad1c0-62fa-4d14-8fc5-5e822850bf5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2246213757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2246213757
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.224009967
Short name	T16
Test name
Test status
Simulation time	253910063 ps
CPU time	10.23 seconds
Started	May 21 12:46:19 PM PDT 24
Finished	May 21 12:46:31 PM PDT 24
Peak memory	211644 kb
Host	smart-f1e14b70-0687-4a51-a866-6f7ce9fe4d66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=224009967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.224009967
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3222112355
Short name	T741
Test name
Test status
Simulation time	637274874 ps
CPU time	4.23 seconds
Started	May 21 12:46:27 PM PDT 24
Finished	May 21 12:46:32 PM PDT 24
Peak memory	203464 kb
Host	smart-5102cfcd-5897-4738-afea-f85a24018f23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3222112355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3222112355
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3547080877
Short name	T883
Test name
Test status
Simulation time	81712423035 ps
CPU time	337.21 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:52:09 PM PDT 24
Peak memory	206012 kb
Host	smart-6a618137-0508-4e1e-b9e0-d29b28d52081
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3547080877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.3547080877
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.752229071
Short name	T705
Test name
Test status
Simulation time	179727851 ps
CPU time	3.42 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:46:35 PM PDT 24
Peak memory	203472 kb
Host	smart-52dfd076-b25e-467b-9f09-78a95af17fa7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=752229071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.752229071
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.3194748666
Short name	T82
Test name
Test status
Simulation time	43478083 ps
CPU time	4.34 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:46:36 PM PDT 24
Peak memory	203476 kb
Host	smart-52fbfb2c-a57f-47d4-9724-4ad9f15d11b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3194748666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3194748666
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.1824709894
Short name	T156
Test name
Test status
Simulation time	288090720 ps
CPU time	24.6 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:46:54 PM PDT 24
Peak memory	211444 kb
Host	smart-d06fdf49-5a9b-44ee-b086-a376c196f27d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1824709894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1824709894
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.4230510067
Short name	T880
Test name
Test status
Simulation time	10198465798 ps
CPU time	57.43 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:47:27 PM PDT 24
Peak memory	211912 kb
Host	smart-f9d444ea-1bd7-493b-b8b7-38d9308fc377
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230510067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.4230510067
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.986300499
Short name	T335
Test name
Test status
Simulation time	1201898827 ps
CPU time	11.7 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:46:43 PM PDT 24
Peak memory	203420 kb
Host	smart-e46c129b-85ca-4581-aedc-d14af636f6c8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=986300499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.986300499
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1448795212
Short name	T154
Test name
Test status
Simulation time	80679502 ps
CPU time	6.24 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:46:36 PM PDT 24
Peak memory	211616 kb
Host	smart-5a55e765-c83a-40dd-8bb7-c4936cd80709
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448795212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1448795212
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.3900253306
Short name	T751
Test name
Test status
Simulation time	4528049445 ps
CPU time	35.66 seconds
Started	May 21 12:46:31 PM PDT 24
Finished	May 21 12:47:07 PM PDT 24
Peak memory	211648 kb
Host	smart-b9d85d8a-ff55-4fda-b92e-12eb038739f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3900253306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3900253306
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.1426151561
Short name	T362
Test name
Test status
Simulation time	311668051 ps
CPU time	3.85 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:46:37 PM PDT 24
Peak memory	203404 kb
Host	smart-ce4605a4-bf0e-4393-a193-f3a922ea0a2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1426151561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1426151561
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2505231390
Short name	T215
Test name
Test status
Simulation time	19797891359 ps
CPU time	36.99 seconds
Started	May 21 12:46:26 PM PDT 24
Finished	May 21 12:47:04 PM PDT 24
Peak memory	203492 kb
Host	smart-a3562ffa-d99f-4949-922f-f49f80dfa925
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505231390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2505231390
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2995192240
Short name	T377
Test name
Test status
Simulation time	3137343448 ps
CPU time	28.53 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:47:00 PM PDT 24
Peak memory	203480 kb
Host	smart-e71599e5-f3d2-49f6-a862-61442333d667
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2995192240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2995192240
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2447846958
Short name	T604
Test name
Test status
Simulation time	55220944 ps
CPU time	2.25 seconds
Started	May 21 12:46:27 PM PDT 24
Finished	May 21 12:46:31 PM PDT 24
Peak memory	203436 kb
Host	smart-9ccefb47-c2a5-445c-8abd-e2dc7ce10fe9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447846958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2447846958
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.481427796
Short name	T452
Test name
Test status
Simulation time	20431432953 ps
CPU time	207.69 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:49:57 PM PDT 24
Peak memory	209088 kb
Host	smart-e36c9e8d-bc64-4da8-bc8c-9c4403d3b8ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=481427796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.481427796
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.496021705
Short name	T630
Test name
Test status
Simulation time	1773022792 ps
CPU time	13.31 seconds
Started	May 21 12:46:29 PM PDT 24
Finished	May 21 12:46:44 PM PDT 24
Peak memory	203440 kb
Host	smart-85b21c94-3102-49ae-a299-f57e8ef0b15e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=496021705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.496021705
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1120615198
Short name	T887
Test name
Test status
Simulation time	3243063368 ps
CPU time	287.28 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:51:17 PM PDT 24
Peak memory	208668 kb
Host	smart-6034dc21-222c-4f48-866a-72bec54a87d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1120615198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1120615198
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3358671206
Short name	T491
Test name
Test status
Simulation time	2059932147 ps
CPU time	179.12 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:49:32 PM PDT 24
Peak memory	211604 kb
Host	smart-e57ad0d7-2ede-4647-b7df-4367107ad758
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3358671206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3358671206
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.471494146
Short name	T739
Test name
Test status
Simulation time	354063292 ps
CPU time	15.81 seconds
Started	May 21 12:46:29 PM PDT 24
Finished	May 21 12:46:46 PM PDT 24
Peak memory	204872 kb
Host	smart-61c6b28f-0331-43e6-a3ca-0fcab34e91db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=471494146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.471494146
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3882652386
Short name	T619
Test name
Test status
Simulation time	263388525 ps
CPU time	37.91 seconds
Started	May 21 12:46:29 PM PDT 24
Finished	May 21 12:47:09 PM PDT 24
Peak memory	205172 kb
Host	smart-c4bfa5ef-8e86-4981-b0c1-bbc1568921e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3882652386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3882652386
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3522470310
Short name	T77
Test name
Test status
Simulation time	113770974321 ps
CPU time	645.89 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:57:17 PM PDT 24
Peak memory	206008 kb
Host	smart-dbb0ee6e-bc3d-4e79-9094-1f79d00b58f9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3522470310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3522470310
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1393473719
Short name	T84
Test name
Test status
Simulation time	45646656 ps
CPU time	5.92 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:46:42 PM PDT 24
Peak memory	203680 kb
Host	smart-edadd159-9132-4234-9f2d-a6d962e7ac6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1393473719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1393473719
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.1769729195
Short name	T250
Test name
Test status
Simulation time	192838207 ps
CPU time	4.17 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:46:34 PM PDT 24
Peak memory	203368 kb
Host	smart-efef951f-d33f-4929-b83a-d7b37b972a93
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1769729195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1769729195
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.4221515050
Short name	T735
Test name
Test status
Simulation time	244700663 ps
CPU time	17.75 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:46:47 PM PDT 24
Peak memory	204500 kb
Host	smart-31e2f6a0-fffb-4a79-80d9-3e7aae439f61
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221515050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.4221515050
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.964715289
Short name	T438
Test name
Test status
Simulation time	71771453554 ps
CPU time	273.48 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:51:03 PM PDT 24
Peak memory	211676 kb
Host	smart-56d15248-2cfa-4038-b608-ea935e3edad5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=964715289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.964715289
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1420016681
Short name	T583
Test name
Test status
Simulation time	19924687741 ps
CPU time	181.13 seconds
Started	May 21 12:46:30 PM PDT 24
Finished	May 21 12:49:33 PM PDT 24
Peak memory	211660 kb
Host	smart-f7b98425-9194-4d5a-8e22-461a3343515c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1420016681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1420016681
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.4265054775
Short name	T105
Test name
Test status
Simulation time	187034496 ps
CPU time	15.76 seconds
Started	May 21 12:46:26 PM PDT 24
Finished	May 21 12:46:43 PM PDT 24
Peak memory	204692 kb
Host	smart-27ca2125-6253-4fb2-ab3a-77ec6b57b037
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265054775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.4265054775
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.3481275117
Short name	T539
Test name
Test status
Simulation time	448345698 ps
CPU time	9.12 seconds
Started	May 21 12:46:29 PM PDT 24
Finished	May 21 12:46:39 PM PDT 24
Peak memory	203448 kb
Host	smart-97a092e3-ff76-45df-9df6-d29e6750d1d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3481275117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3481275117
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.2098273917
Short name	T160
Test name
Test status
Simulation time	186101513 ps
CPU time	3.6 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:46:33 PM PDT 24
Peak memory	203392 kb
Host	smart-eaa66db6-c23d-4086-b0ed-e5904b4d20ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2098273917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2098273917
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1302159889
Short name	T457
Test name
Test status
Simulation time	7346151441 ps
CPU time	25.08 seconds
Started	May 21 12:46:26 PM PDT 24
Finished	May 21 12:46:52 PM PDT 24
Peak memory	203392 kb
Host	smart-09f9217c-ac61-4f45-ad8e-ac77cecc6e20
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302159889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1302159889
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1380452516
Short name	T397
Test name
Test status
Simulation time	3146557571 ps
CPU time	28.23 seconds
Started	May 21 12:46:31 PM PDT 24
Finished	May 21 12:47:00 PM PDT 24
Peak memory	203464 kb
Host	smart-fd03b976-4b4a-43c4-b7e3-b9552480bd87
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1380452516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1380452516
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.61590043
Short name	T379
Test name
Test status
Simulation time	127492972 ps
CPU time	2.32 seconds
Started	May 21 12:46:28 PM PDT 24
Finished	May 21 12:46:31 PM PDT 24
Peak memory	203448 kb
Host	smart-392bf3d7-45e0-4750-ae9d-217ba2f988b4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61590043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.61590043
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.1315809089
Short name	T661
Test name
Test status
Simulation time	2545351649 ps
CPU time	131.32 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:48:47 PM PDT 24
Peak memory	209740 kb
Host	smart-43f4205e-8224-4b7a-8839-f0cec4ab34fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1315809089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1315809089
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.51253144
Short name	T2
Test name
Test status
Simulation time	1066579161 ps
CPU time	89.11 seconds
Started	May 21 12:46:40 PM PDT 24
Finished	May 21 12:48:12 PM PDT 24
Peak memory	204740 kb
Host	smart-b77153bd-97f3-4b60-b374-a112fa653d2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=51253144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.51253144
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3010390239
Short name	T209
Test name
Test status
Simulation time	3827854687 ps
CPU time	375.98 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:52:50 PM PDT 24
Peak memory	222952 kb
Host	smart-77e5db58-ce16-4ccf-aa1a-98cf86c07de9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3010390239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.3010390239
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2843203476
Short name	T101
Test name
Test status
Simulation time	164721796 ps
CPU time	24.77 seconds
Started	May 21 12:46:37 PM PDT 24
Finished	May 21 12:47:04 PM PDT 24
Peak memory	205948 kb
Host	smart-6e02790c-7b89-4b17-927a-b260e16c9783
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2843203476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.2843203476
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.100043429
Short name	T58
Test name
Test status
Simulation time	1332348789 ps
CPU time	29.3 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:47:05 PM PDT 24
Peak memory	204968 kb
Host	smart-e0556c4c-1732-4c74-89d7-a49d411da59b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=100043429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.100043429
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2905850639
Short name	T157
Test name
Test status
Simulation time	1591815611 ps
CPU time	63.88 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:47:40 PM PDT 24
Peak memory	205536 kb
Host	smart-d2be7aa9-58ad-49ab-9de0-d29122bd74f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2905850639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2905850639
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3733082355
Short name	T134
Test name
Test status
Simulation time	35191721925 ps
CPU time	286.26 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:51:23 PM PDT 24
Peak memory	206080 kb
Host	smart-ef6fe2af-f4b2-4397-82b9-fac6e6424cd1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3733082355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.3733082355
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2626825240
Short name	T306
Test name
Test status
Simulation time	180028975 ps
CPU time	3.53 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:46:38 PM PDT 24
Peak memory	203340 kb
Host	smart-9368bf3e-168f-42aa-ba78-279c0d8fb807
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2626825240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2626825240
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.2369170078
Short name	T291
Test name
Test status
Simulation time	131547336 ps
CPU time	15.37 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:46:48 PM PDT 24
Peak memory	203404 kb
Host	smart-c1c6fd62-bf52-49b6-bdcf-071df24e2896
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2369170078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2369170078
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.2440808678
Short name	T50
Test name
Test status
Simulation time	2305160760 ps
CPU time	25.37 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:47:01 PM PDT 24
Peak memory	211668 kb
Host	smart-5e830d8b-1e6e-41b4-be93-cf196030c1de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2440808678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2440808678
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2254407323
Short name	T289
Test name
Test status
Simulation time	20691897615 ps
CPU time	61.78 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:47:35 PM PDT 24
Peak memory	205000 kb
Host	smart-1e2e99fe-348e-4c88-9fad-21d604398dbf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254407323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2254407323
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4187993869
Short name	T639
Test name
Test status
Simulation time	89302642007 ps
CPU time	301.86 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:51:39 PM PDT 24
Peak memory	205336 kb
Host	smart-693bd871-4399-4f46-bd1e-9e209315f717
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4187993869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4187993869
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3912381570
Short name	T348
Test name
Test status
Simulation time	17617346 ps
CPU time	2.35 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:46:39 PM PDT 24
Peak memory	203420 kb
Host	smart-2273dddd-96eb-4ad2-b23f-bb74a5d27813
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912381570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3912381570
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.4061101167
Short name	T327
Test name
Test status
Simulation time	1526809478 ps
CPU time	34.02 seconds
Started	May 21 12:46:37 PM PDT 24
Finished	May 21 12:47:12 PM PDT 24
Peak memory	203812 kb
Host	smart-37981ecf-5f4f-4b62-85a4-af851113f28b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4061101167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4061101167
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.3754665997
Short name	T448
Test name
Test status
Simulation time	196135890 ps
CPU time	3.87 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:46:39 PM PDT 24
Peak memory	203416 kb
Host	smart-ae1b95f0-fc5f-47ed-961a-f11ffd5a6e94
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3754665997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3754665997
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1182048638
Short name	T174
Test name
Test status
Simulation time	6345239382 ps
CPU time	30.91 seconds
Started	May 21 12:46:40 PM PDT 24
Finished	May 21 12:47:13 PM PDT 24
Peak memory	203344 kb
Host	smart-661c8192-a73b-4779-9f92-f29f5035c22a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182048638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1182048638
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2999309703
Short name	T367
Test name
Test status
Simulation time	3714026256 ps
CPU time	30.74 seconds
Started	May 21 12:46:37 PM PDT 24
Finished	May 21 12:47:09 PM PDT 24
Peak memory	202964 kb
Host	smart-d5882a26-8e97-4058-a604-3db2d95feaf8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2999309703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2999309703
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3321730246
Short name	T782
Test name
Test status
Simulation time	100697423 ps
CPU time	2.18 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:46:38 PM PDT 24
Peak memory	203428 kb
Host	smart-91f69bdb-d124-494a-a9f1-00a298f0b032
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321730246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3321730246
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.3472792415
Short name	T425
Test name
Test status
Simulation time	3545090792 ps
CPU time	95.77 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:48:12 PM PDT 24
Peak memory	207304 kb
Host	smart-07460c10-8392-4c01-a393-ed895ebddfdc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3472792415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3472792415
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3607746055
Short name	T812
Test name
Test status
Simulation time	634463060 ps
CPU time	46.81 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:47:23 PM PDT 24
Peak memory	206420 kb
Host	smart-97157784-b9a3-4d60-a628-003e93d928eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3607746055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3607746055
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4112615413
Short name	T187
Test name
Test status
Simulation time	1631384926 ps
CPU time	228.14 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:50:25 PM PDT 24
Peak memory	209060 kb
Host	smart-595663a8-2c95-4991-8a55-2cac59deb1e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4112615413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.4112615413
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2345924878
Short name	T813
Test name
Test status
Simulation time	395330292 ps
CPU time	107.5 seconds
Started	May 21 12:46:37 PM PDT 24
Finished	May 21 12:48:27 PM PDT 24
Peak memory	209816 kb
Host	smart-0abdfdf6-f740-47f4-9578-e6f78e3ba25a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2345924878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2345924878
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.569856183
Short name	T809
Test name
Test status
Simulation time	74221479 ps
CPU time	6.33 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:46:40 PM PDT 24
Peak memory	204848 kb
Host	smart-d3964495-ca43-4178-b9e1-e84f2306bd6e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=569856183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.569856183
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.828353019
Short name	T378
Test name
Test status
Simulation time	305818119 ps
CPU time	19.13 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:46:54 PM PDT 24
Peak memory	205208 kb
Host	smart-04751444-59da-458b-b5e4-90b2e3479fbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=828353019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.828353019
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.343816354
Short name	T131
Test name
Test status
Simulation time	109669276179 ps
CPU time	354.69 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:52:28 PM PDT 24
Peak memory	206000 kb
Host	smart-29efa0d5-2617-400a-9cbb-a9d6e284ae27
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=343816354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.343816354
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2577607870
Short name	T563
Test name
Test status
Simulation time	44455697 ps
CPU time	4.52 seconds
Started	May 21 12:46:39 PM PDT 24
Finished	May 21 12:46:45 PM PDT 24
Peak memory	203452 kb
Host	smart-5f85aecc-78b2-4d2a-b3c0-452903f3374f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2577607870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2577607870
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.1310911923
Short name	T300
Test name
Test status
Simulation time	733701864 ps
CPU time	31.05 seconds
Started	May 21 12:46:41 PM PDT 24
Finished	May 21 12:47:14 PM PDT 24
Peak memory	203696 kb
Host	smart-4f6ddb72-e09e-4f8a-89f2-a1dcd8cdbbe6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1310911923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1310911923
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.3616783150
Short name	T853
Test name
Test status
Simulation time	1707901311 ps
CPU time	36.49 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:47:11 PM PDT 24
Peak memory	204604 kb
Host	smart-c1e9238a-6fe0-4106-bf97-35ba64af9725
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3616783150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3616783150
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3072553345
Short name	T444
Test name
Test status
Simulation time	19269575639 ps
CPU time	109.68 seconds
Started	May 21 12:46:37 PM PDT 24
Finished	May 21 12:48:29 PM PDT 24
Peak memory	211688 kb
Host	smart-a7fa7e3a-cb62-4ec4-927a-e74ff56b3dda
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072553345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3072553345
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2417526412
Short name	T897
Test name
Test status
Simulation time	7609937410 ps
CPU time	44.51 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:47:21 PM PDT 24
Peak memory	204692 kb
Host	smart-648b7a05-db83-43c5-a334-ba6925825c46
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2417526412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2417526412
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2448212142
Short name	T635
Test name
Test status
Simulation time	158259691 ps
CPU time	5.9 seconds
Started	May 21 12:46:33 PM PDT 24
Finished	May 21 12:46:41 PM PDT 24
Peak memory	204544 kb
Host	smart-6da49793-4d71-4939-942a-d7de8a8f784f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448212142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2448212142
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.2452606740
Short name	T734
Test name
Test status
Simulation time	112850848 ps
CPU time	8.9 seconds
Started	May 21 12:46:34 PM PDT 24
Finished	May 21 12:46:45 PM PDT 24
Peak memory	203916 kb
Host	smart-6b18d2c2-53e1-4c7b-821f-4e2b65ae3b40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2452606740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2452606740
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.1063178857
Short name	T552
Test name
Test status
Simulation time	160277387 ps
CPU time	3.81 seconds
Started	May 21 12:46:37 PM PDT 24
Finished	May 21 12:46:42 PM PDT 24
Peak memory	202848 kb
Host	smart-f34f3bc3-4a76-46d0-8a15-8b13287dba32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1063178857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1063178857
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.455336107
Short name	T52
Test name
Test status
Simulation time	11356310661 ps
CPU time	31.43 seconds
Started	May 21 12:46:38 PM PDT 24
Finished	May 21 12:47:11 PM PDT 24
Peak memory	203344 kb
Host	smart-73189839-538a-4eda-b80e-dad0d5de1f9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=455336107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.455336107
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3523086364
Short name	T514
Test name
Test status
Simulation time	6062983258 ps
CPU time	32.65 seconds
Started	May 21 12:46:37 PM PDT 24
Finished	May 21 12:47:12 PM PDT 24
Peak memory	203496 kb
Host	smart-b3b4ffd4-e822-4e5d-b9aa-57a9c80f2713
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3523086364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3523086364
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.93150387
Short name	T899
Test name
Test status
Simulation time	30448900 ps
CPU time	2.37 seconds
Started	May 21 12:46:32 PM PDT 24
Finished	May 21 12:46:35 PM PDT 24
Peak memory	203424 kb
Host	smart-0807cbdc-d06f-4230-a8ed-57341b38a57e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93150387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.93150387
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.3320356835
Short name	T862
Test name
Test status
Simulation time	23128271008 ps
CPU time	210.19 seconds
Started	May 21 12:46:39 PM PDT 24
Finished	May 21 12:50:11 PM PDT 24
Peak memory	209132 kb
Host	smart-db308132-251c-42eb-bc76-eb584e141e95
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320356835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3320356835
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.4122306847
Short name	T657
Test name
Test status
Simulation time	5221870263 ps
CPU time	136.7 seconds
Started	May 21 12:46:38 PM PDT 24
Finished	May 21 12:48:57 PM PDT 24
Peak memory	206540 kb
Host	smart-1bff7d53-a605-4cc8-bb3e-ef88c3e603a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4122306847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4122306847
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.4033484126
Short name	T494
Test name
Test status
Simulation time	3463904455 ps
CPU time	246.26 seconds
Started	May 21 12:46:41 PM PDT 24
Finished	May 21 12:50:50 PM PDT 24
Peak memory	211336 kb
Host	smart-20cbe37a-c49d-4e04-9fab-488a01443c6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4033484126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.4033484126
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.4166191031
Short name	T529
Test name
Test status
Simulation time	171895115 ps
CPU time	6.21 seconds
Started	May 21 12:46:41 PM PDT 24
Finished	May 21 12:46:49 PM PDT 24
Peak memory	204804 kb
Host	smart-f0d048c1-88e3-41e0-81b8-92fce82cc70c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4166191031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4166191031
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2661684361
Short name	T885
Test name
Test status
Simulation time	527524096 ps
CPU time	13.38 seconds
Started	May 21 12:46:41 PM PDT 24
Finished	May 21 12:46:56 PM PDT 24
Peak memory	204372 kb
Host	smart-d0cea563-880a-41ff-a1c9-217aa42c0070
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2661684361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2661684361
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3059024231
Short name	T143
Test name
Test status
Simulation time	196999799780 ps
CPU time	790.37 seconds
Started	May 21 12:46:41 PM PDT 24
Finished	May 21 12:59:53 PM PDT 24
Peak memory	206096 kb
Host	smart-32fd2884-28a6-42d6-8466-acb793fe9aae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3059024231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.3059024231
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2807718538
Short name	T288
Test name
Test status
Simulation time	951393875 ps
CPU time	21.28 seconds
Started	May 21 12:46:47 PM PDT 24
Finished	May 21 12:47:11 PM PDT 24
Peak memory	204116 kb
Host	smart-8abbebeb-4a4c-4b6b-8a3d-acf4c29f5937
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2807718538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2807718538
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.3723180970
Short name	T248
Test name
Test status
Simulation time	158866384 ps
CPU time	14.04 seconds
Started	May 21 12:46:39 PM PDT 24
Finished	May 21 12:46:54 PM PDT 24
Peak memory	203420 kb
Host	smart-4a5db087-42b5-4aee-892e-fa59905174f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3723180970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3723180970
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.3528186017
Short name	T231
Test name
Test status
Simulation time	262035309 ps
CPU time	20.57 seconds
Started	May 21 12:46:44 PM PDT 24
Finished	May 21 12:47:06 PM PDT 24
Peak memory	204836 kb
Host	smart-5fbd96cd-837b-41f0-8d8b-d9c87c6280b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3528186017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3528186017
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3883709064
Short name	T548
Test name
Test status
Simulation time	5668278163 ps
CPU time	38.34 seconds
Started	May 21 12:46:38 PM PDT 24
Finished	May 21 12:47:18 PM PDT 24
Peak memory	205036 kb
Host	smart-64201326-cd08-41e0-a9a3-edc5267d2cce
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883709064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3883709064
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1047161617
Short name	T91
Test name
Test status
Simulation time	113627658032 ps
CPU time	278.68 seconds
Started	May 21 12:46:43 PM PDT 24
Finished	May 21 12:51:23 PM PDT 24
Peak memory	211676 kb
Host	smart-0e1050d2-7b4a-402c-8b6b-37d8dd1b52d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1047161617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1047161617
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.216123414
Short name	T649
Test name
Test status
Simulation time	72425951 ps
CPU time	5.82 seconds
Started	May 21 12:46:40 PM PDT 24
Finished	May 21 12:46:48 PM PDT 24
Peak memory	211480 kb
Host	smart-ed091ae5-1419-4aa2-969b-d0d06268b437
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216123414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.216123414
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.1968658142
Short name	T189
Test name
Test status
Simulation time	332305606 ps
CPU time	6.01 seconds
Started	May 21 12:46:43 PM PDT 24
Finished	May 21 12:46:51 PM PDT 24
Peak memory	203652 kb
Host	smart-175349d6-c8d9-47ad-a37f-7ec9f5ad6dce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1968658142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1968658142
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.3979197727
Short name	T398
Test name
Test status
Simulation time	100867877 ps
CPU time	2.78 seconds
Started	May 21 12:46:43 PM PDT 24
Finished	May 21 12:46:47 PM PDT 24
Peak memory	203412 kb
Host	smart-d37fbd90-9408-43ab-906d-5ffed232464c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3979197727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3979197727
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2804972959
Short name	T802
Test name
Test status
Simulation time	18435746493 ps
CPU time	40.46 seconds
Started	May 21 12:46:39 PM PDT 24
Finished	May 21 12:47:21 PM PDT 24
Peak memory	203492 kb
Host	smart-97932547-2f94-4287-8e97-72f8c8266526
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804972959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2804972959
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.750901538
Short name	T839
Test name
Test status
Simulation time	13302325321 ps
CPU time	41.91 seconds
Started	May 21 12:46:38 PM PDT 24
Finished	May 21 12:47:22 PM PDT 24
Peak memory	203496 kb
Host	smart-ebb4cb32-c453-4f74-bcd8-e6441d424646
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=750901538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.750901538
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.197626848
Short name	T10
Test name
Test status
Simulation time	113714300 ps
CPU time	2.57 seconds
Started	May 21 12:46:38 PM PDT 24
Finished	May 21 12:46:43 PM PDT 24
Peak memory	203464 kb
Host	smart-bee83a36-581e-42f7-b85d-2ff3a8992431
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197626848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.197626848
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.42285993
Short name	T653
Test name
Test status
Simulation time	963360131 ps
CPU time	88.53 seconds
Started	May 21 12:46:48 PM PDT 24
Finished	May 21 12:48:18 PM PDT 24
Peak memory	207940 kb
Host	smart-89cf6d23-2c31-434b-aef0-d198437e1e06
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=42285993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.42285993
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3047751526
Short name	T442
Test name
Test status
Simulation time	521520045 ps
CPU time	16.46 seconds
Started	May 21 12:46:46 PM PDT 24
Finished	May 21 12:47:05 PM PDT 24
Peak memory	203628 kb
Host	smart-bf7c739d-e1db-4fb8-9aa8-26a66579a371
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3047751526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3047751526
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2471888994
Short name	T20
Test name
Test status
Simulation time	590112953 ps
CPU time	188.58 seconds
Started	May 21 12:46:46 PM PDT 24
Finished	May 21 12:49:57 PM PDT 24
Peak memory	208480 kb
Host	smart-7cf0ef93-3b37-48c5-beff-4944648e4fd0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2471888994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.2471888994
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2834647628
Short name	T686
Test name
Test status
Simulation time	3877608632 ps
CPU time	161.55 seconds
Started	May 21 12:46:46 PM PDT 24
Finished	May 21 12:49:30 PM PDT 24
Peak memory	209424 kb
Host	smart-75e543b8-c88b-4f5d-a367-6b1254a5c54c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834647628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2834647628
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2401281583
Short name	T621
Test name
Test status
Simulation time	300398675 ps
CPU time	2.64 seconds
Started	May 21 12:46:41 PM PDT 24
Finished	May 21 12:46:46 PM PDT 24
Peak memory	203304 kb
Host	smart-d87132f2-8636-497f-8559-b5e9a06b0c0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401281583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2401281583
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.13063544
Short name	T896
Test name
Test status
Simulation time	342954217 ps
CPU time	10.22 seconds
Started	May 21 12:46:45 PM PDT 24
Finished	May 21 12:46:57 PM PDT 24
Peak memory	204432 kb
Host	smart-ac33073e-42aa-44ba-b21b-9e002e8fbb0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=13063544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.13063544
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1464362926
Short name	T236
Test name
Test status
Simulation time	16419214815 ps
CPU time	129.12 seconds
Started	May 21 12:46:47 PM PDT 24
Finished	May 21 12:48:58 PM PDT 24
Peak memory	205168 kb
Host	smart-bf646159-f386-4a97-8730-e618be32a0c3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1464362926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.1464362926
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.446381889
Short name	T522
Test name
Test status
Simulation time	82195667 ps
CPU time	10.4 seconds
Started	May 21 12:46:45 PM PDT 24
Finished	May 21 12:46:58 PM PDT 24
Peak memory	203596 kb
Host	smart-a433b64c-b61e-4344-8127-8c8c04b7ec5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=446381889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.446381889
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.4053925182
Short name	T267
Test name
Test status
Simulation time	638156837 ps
CPU time	25.35 seconds
Started	May 21 12:46:51 PM PDT 24
Finished	May 21 12:47:19 PM PDT 24
Peak memory	203564 kb
Host	smart-d4819d7e-e424-4ec9-98eb-36adf0054708
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4053925182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.4053925182
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.3438835297
Short name	T254
Test name
Test status
Simulation time	112265320 ps
CPU time	9.38 seconds
Started	May 21 12:46:51 PM PDT 24
Finished	May 21 12:47:03 PM PDT 24
Peak memory	204624 kb
Host	smart-6d823109-5df9-4fd7-a841-27c686cdeca1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3438835297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3438835297
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3886593743
Short name	T768
Test name
Test status
Simulation time	6504292128 ps
CPU time	26.13 seconds
Started	May 21 12:46:45 PM PDT 24
Finished	May 21 12:47:14 PM PDT 24
Peak memory	211564 kb
Host	smart-08f66ec5-cb3c-4bd9-a35c-007e61dd5fc4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886593743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3886593743
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3146002939
Short name	T785
Test name
Test status
Simulation time	10923044521 ps
CPU time	86.42 seconds
Started	May 21 12:46:50 PM PDT 24
Finished	May 21 12:48:17 PM PDT 24
Peak memory	204844 kb
Host	smart-56cf3ced-b3a3-409f-a3b7-956f8bd66b3a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3146002939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3146002939
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1831136735
Short name	T196
Test name
Test status
Simulation time	133494482 ps
CPU time	18.53 seconds
Started	May 21 12:46:46 PM PDT 24
Finished	May 21 12:47:07 PM PDT 24
Peak memory	204652 kb
Host	smart-602f4856-1c67-4fde-a8ef-90e7c0a7b729
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831136735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1831136735
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.2684609218
Short name	T504
Test name
Test status
Simulation time	96116946 ps
CPU time	8.02 seconds
Started	May 21 12:46:46 PM PDT 24
Finished	May 21 12:46:57 PM PDT 24
Peak memory	203348 kb
Host	smart-a969b526-c99d-4321-b86f-0d56c13e65c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2684609218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2684609218
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.3574583119
Short name	T826
Test name
Test status
Simulation time	30594816 ps
CPU time	2.31 seconds
Started	May 21 12:46:48 PM PDT 24
Finished	May 21 12:46:52 PM PDT 24
Peak memory	203408 kb
Host	smart-8ef2b681-912c-4d4f-b7f1-a5e48760724f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3574583119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3574583119
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.808648798
Short name	T694
Test name
Test status
Simulation time	5024902198 ps
CPU time	29.03 seconds
Started	May 21 12:46:45 PM PDT 24
Finished	May 21 12:47:16 PM PDT 24
Peak memory	203452 kb
Host	smart-ff158dca-8fc4-4f5e-bca5-d152c34beb7f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=808648798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.808648798
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1766031420
Short name	T742
Test name
Test status
Simulation time	29244422401 ps
CPU time	59.02 seconds
Started	May 21 12:46:48 PM PDT 24
Finished	May 21 12:47:49 PM PDT 24
Peak memory	203424 kb
Host	smart-5e386906-9d4f-41be-a814-5dba7363fe5f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1766031420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1766031420
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.4039917736
Short name	T357
Test name
Test status
Simulation time	42610312 ps
CPU time	2.34 seconds
Started	May 21 12:46:47 PM PDT 24
Finished	May 21 12:46:52 PM PDT 24
Peak memory	203332 kb
Host	smart-8d4ee006-969b-4a31-8c32-3079ca5ca2ab
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039917736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.4039917736
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.363801408
Short name	T869
Test name
Test status
Simulation time	2309182556 ps
CPU time	200.09 seconds
Started	May 21 12:46:46 PM PDT 24
Finished	May 21 12:50:08 PM PDT 24
Peak memory	209164 kb
Host	smart-34941dab-8569-4c62-8672-32088aa9631a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=363801408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.363801408
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3096781558
Short name	T681
Test name
Test status
Simulation time	985326248 ps
CPU time	112.81 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:48:48 PM PDT 24
Peak memory	207808 kb
Host	smart-746fd234-b2bf-4fd4-9e6d-097cfb9d4b41
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3096781558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3096781558
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3562724235
Short name	T242
Test name
Test status
Simulation time	371578948 ps
CPU time	213.11 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:50:29 PM PDT 24
Peak memory	209292 kb
Host	smart-51bd05a3-a4ae-44c4-809d-d05e2b8bc9b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3562724235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.3562724235
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.4219386409
Short name	T146
Test name
Test status
Simulation time	77650922 ps
CPU time	25.27 seconds
Started	May 21 12:46:58 PM PDT 24
Finished	May 21 12:47:25 PM PDT 24
Peak memory	205840 kb
Host	smart-688d2613-bb2e-4573-a882-19b879618f73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4219386409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.4219386409
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2856995006
Short name	T498
Test name
Test status
Simulation time	206536938 ps
CPU time	5.96 seconds
Started	May 21 12:46:45 PM PDT 24
Finished	May 21 12:46:53 PM PDT 24
Peak memory	204828 kb
Host	smart-ab24c2c0-cfc4-41b7-8fec-3d905fbcdc2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2856995006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2856995006
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1802270046
Short name	T235
Test name
Test status
Simulation time	208407314 ps
CPU time	19.7 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:47:15 PM PDT 24
Peak memory	204568 kb
Host	smart-d0382843-724f-4786-b02a-32557cbfae07
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1802270046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1802270046
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.285279771
Short name	T460
Test name
Test status
Simulation time	117676864832 ps
CPU time	531.34 seconds
Started	May 21 12:46:52 PM PDT 24
Finished	May 21 12:55:47 PM PDT 24
Peak memory	207096 kb
Host	smart-03097bf0-7a7f-41d8-b2b4-dcd048228ebd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=285279771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo w_rsp.285279771
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.472393227
Short name	T762
Test name
Test status
Simulation time	412816216 ps
CPU time	15.7 seconds
Started	May 21 12:46:52 PM PDT 24
Finished	May 21 12:47:11 PM PDT 24
Peak memory	203580 kb
Host	smart-9d15b42e-4e87-4ff0-aad2-6acc8a312aa5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=472393227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.472393227
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.721598633
Short name	T465
Test name
Test status
Simulation time	1070740678 ps
CPU time	33.68 seconds
Started	May 21 12:46:54 PM PDT 24
Finished	May 21 12:47:30 PM PDT 24
Peak memory	203348 kb
Host	smart-b9a46b74-152c-498c-ae66-0a967e5653fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=721598633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.721598633
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.2300312637
Short name	T704
Test name
Test status
Simulation time	305783480 ps
CPU time	12.89 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:47:15 PM PDT 24
Peak memory	204576 kb
Host	smart-4faf0d77-2043-4135-bd95-3ca4273cfa9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2300312637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2300312637
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1889771631
Short name	T484
Test name
Test status
Simulation time	13372918046 ps
CPU time	90.48 seconds
Started	May 21 12:46:55 PM PDT 24
Finished	May 21 12:48:28 PM PDT 24
Peak memory	204560 kb
Host	smart-0962edf1-b8b3-4f07-a132-8e45d41b7d7e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889771631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1889771631
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.475715032
Short name	T108
Test name
Test status
Simulation time	18461106119 ps
CPU time	68.14 seconds
Started	May 21 12:46:54 PM PDT 24
Finished	May 21 12:48:05 PM PDT 24
Peak memory	204692 kb
Host	smart-72ea95d2-1292-4f63-8fff-d4126d312b42
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=475715032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.475715032
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.907209997
Short name	T572
Test name
Test status
Simulation time	28097736 ps
CPU time	3.25 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:46:59 PM PDT 24
Peak memory	203452 kb
Host	smart-71a177ef-ccdd-423c-813a-65f6e5abd66d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907209997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.907209997
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.679538109
Short name	T623
Test name
Test status
Simulation time	92093600 ps
CPU time	8.16 seconds
Started	May 21 12:46:52 PM PDT 24
Finished	May 21 12:47:02 PM PDT 24
Peak memory	203468 kb
Host	smart-4cf77721-1046-49e7-8be5-3122f24f09ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=679538109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.679538109
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.3983922517
Short name	T60
Test name
Test status
Simulation time	293774379 ps
CPU time	3.24 seconds
Started	May 21 12:46:52 PM PDT 24
Finished	May 21 12:46:57 PM PDT 24
Peak memory	203412 kb
Host	smart-20d5e68b-36d0-48b7-8b3a-e49aed627882
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3983922517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3983922517
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3494844762
Short name	T337
Test name
Test status
Simulation time	8455316556 ps
CPU time	31.24 seconds
Started	May 21 12:46:51 PM PDT 24
Finished	May 21 12:47:25 PM PDT 24
Peak memory	203460 kb
Host	smart-40a15164-24c0-4cce-9020-852fd5e07af9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494844762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3494844762
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2426834856
Short name	T691
Test name
Test status
Simulation time	5017834288 ps
CPU time	27.42 seconds
Started	May 21 12:46:51 PM PDT 24
Finished	May 21 12:47:20 PM PDT 24
Peak memory	203472 kb
Host	smart-c189f303-7f8c-4faf-ac31-fbaf132d180c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2426834856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2426834856
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1951822288
Short name	T479
Test name
Test status
Simulation time	28188504 ps
CPU time	2.65 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:47:05 PM PDT 24
Peak memory	203436 kb
Host	smart-cb855854-ccd6-4dd3-a4db-c5a4501a79a5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951822288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1951822288
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.3258160437
Short name	T662
Test name
Test status
Simulation time	221233259 ps
CPU time	24.99 seconds
Started	May 21 12:46:51 PM PDT 24
Finished	May 21 12:47:18 PM PDT 24
Peak memory	205592 kb
Host	smart-a5c2e791-dbd9-4cee-b82f-70959fcfae3b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3258160437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3258160437
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.4028168575
Short name	T385
Test name
Test status
Simulation time	3825134659 ps
CPU time	127.41 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:49:03 PM PDT 24
Peak memory	207596 kb
Host	smart-ef3a35ec-9cd2-4d5d-ba1a-d545e8f5aa5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4028168575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.4028168575
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2281396415
Short name	T199
Test name
Test status
Simulation time	4933003368 ps
CPU time	338.68 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:52:34 PM PDT 24
Peak memory	211904 kb
Host	smart-c99fe499-04fe-4b6b-9fd6-572d5a80b036
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2281396415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2281396415
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3355384347
Short name	T320
Test name
Test status
Simulation time	246079268 ps
CPU time	76.63 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:48:19 PM PDT 24
Peak memory	207208 kb
Host	smart-f6ed59d4-f047-43cb-9415-3e1b02cff0a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3355384347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3355384347
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.738853123
Short name	T428
Test name
Test status
Simulation time	14445487 ps
CPU time	1.91 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:46:58 PM PDT 24
Peak memory	203408 kb
Host	smart-ba46210c-c15e-44a7-8eb3-369fa3ffe699
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=738853123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.738853123
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2769292694
Short name	T186
Test name
Test status
Simulation time	492788898 ps
CPU time	39.44 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:47:42 PM PDT 24
Peak memory	204460 kb
Host	smart-36645195-ca6e-4b41-bb66-80e141648e57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2769292694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2769292694
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.782933704
Short name	T53
Test name
Test status
Simulation time	296659086391 ps
CPU time	866.66 seconds
Started	May 21 12:47:01 PM PDT 24
Finished	May 21 01:01:30 PM PDT 24
Peak memory	207856 kb
Host	smart-6120ba3e-ce1c-4f91-b6fc-aad43a8526a8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=782933704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo w_rsp.782933704
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2588758817
Short name	T173
Test name
Test status
Simulation time	72659321 ps
CPU time	9.56 seconds
Started	May 21 12:46:59 PM PDT 24
Finished	May 21 12:47:10 PM PDT 24
Peak memory	204052 kb
Host	smart-420acdf3-3154-4177-8a0f-dfe8698ecaf8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588758817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2588758817
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.841968903
Short name	T417
Test name
Test status
Simulation time	315328829 ps
CPU time	22.17 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:47:24 PM PDT 24
Peak memory	203524 kb
Host	smart-ccf5032e-1eff-474a-888b-e567d2bc0e2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=841968903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.841968903
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.3398587034
Short name	T167
Test name
Test status
Simulation time	124203922 ps
CPU time	14.33 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:47:10 PM PDT 24
Peak memory	211488 kb
Host	smart-49cdc5b2-3cb8-48d9-85ac-e0d2f58a5126
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3398587034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3398587034
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2199237502
Short name	T226
Test name
Test status
Simulation time	1663671403 ps
CPU time	10.49 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:47:06 PM PDT 24
Peak memory	203328 kb
Host	smart-ccb5a8fd-23d7-43b1-8b6b-3b1b07c44f35
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199237502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2199237502
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.741781618
Short name	T828
Test name
Test status
Simulation time	2287601425 ps
CPU time	14.61 seconds
Started	May 21 12:46:57 PM PDT 24
Finished	May 21 12:47:13 PM PDT 24
Peak memory	203508 kb
Host	smart-ca07e8c6-04c2-4d01-966d-2c141c7175b8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=741781618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.741781618
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.424086307
Short name	T882
Test name
Test status
Simulation time	373410298 ps
CPU time	12.88 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:47:08 PM PDT 24
Peak memory	204512 kb
Host	smart-67936636-1850-4ca0-bc5f-004c86e12fb3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424086307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.424086307
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.81718667
Short name	T102
Test name
Test status
Simulation time	1459836171 ps
CPU time	24.56 seconds
Started	May 21 12:46:59 PM PDT 24
Finished	May 21 12:47:26 PM PDT 24
Peak memory	203860 kb
Host	smart-280403a4-29ad-48c1-8f1e-0c55a3816c53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81718667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.81718667
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.2896241063
Short name	T296
Test name
Test status
Simulation time	145399830 ps
CPU time	3.79 seconds
Started	May 21 12:46:54 PM PDT 24
Finished	May 21 12:47:00 PM PDT 24
Peak memory	203448 kb
Host	smart-461a0f38-fad0-4ab3-ac32-fd5df7c011c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2896241063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2896241063
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1025641073
Short name	T107
Test name
Test status
Simulation time	13688637621 ps
CPU time	32.16 seconds
Started	May 21 12:46:59 PM PDT 24
Finished	May 21 12:47:33 PM PDT 24
Peak memory	203492 kb
Host	smart-62a8c7e4-72dc-4c45-a249-7142de9c65ca
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025641073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1025641073
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.954665808
Short name	T406
Test name
Test status
Simulation time	3072660445 ps
CPU time	26.61 seconds
Started	May 21 12:46:53 PM PDT 24
Finished	May 21 12:47:22 PM PDT 24
Peak memory	203412 kb
Host	smart-5671c5ab-c94e-4423-ae6f-5b311567d091
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=954665808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.954665808
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3899720078
Short name	T655
Test name
Test status
Simulation time	99778932 ps
CPU time	2.35 seconds
Started	May 21 12:46:52 PM PDT 24
Finished	May 21 12:46:57 PM PDT 24
Peak memory	203336 kb
Host	smart-a43813e6-0c16-4bb1-9927-8b75c30570f4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899720078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3899720078
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.1290845330
Short name	T109
Test name
Test status
Simulation time	1466261961 ps
CPU time	76.8 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:48:18 PM PDT 24
Peak memory	207684 kb
Host	smart-8f3b5a18-e463-4cd0-a7c3-0f5301b84605
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1290845330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1290845330
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1823426043
Short name	T758
Test name
Test status
Simulation time	3243290083 ps
CPU time	108.94 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:48:50 PM PDT 24
Peak memory	209800 kb
Host	smart-9cf7ca31-3960-41de-bc7d-15726f8a2e1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1823426043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1823426043
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3031296610
Short name	T478
Test name
Test status
Simulation time	83850734 ps
CPU time	21.37 seconds
Started	May 21 12:47:01 PM PDT 24
Finished	May 21 12:47:25 PM PDT 24
Peak memory	206328 kb
Host	smart-cbd4d739-dced-47e1-918f-e4134b9a7c11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3031296610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.3031296610
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3001057900
Short name	T515
Test name
Test status
Simulation time	75980736 ps
CPU time	29.3 seconds
Started	May 21 12:46:59 PM PDT 24
Finished	May 21 12:47:30 PM PDT 24
Peak memory	206092 kb
Host	smart-75f45b03-100e-4d41-95a7-34c2f3acda45
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3001057900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.3001057900
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1946911119
Short name	T564
Test name
Test status
Simulation time	166522720 ps
CPU time	23.93 seconds
Started	May 21 12:47:00 PM PDT 24
Finished	May 21 12:47:27 PM PDT 24
Peak memory	211628 kb
Host	smart-9869fce9-a7b7-4d96-866d-01e1cbe4e252
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1946911119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1946911119
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.431539575
Short name	T274
Test name
Test status
Simulation time	3703490538 ps
CPU time	48.06 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:44:36 PM PDT 24
Peak memory	206092 kb
Host	smart-b0736ddb-2996-4f9d-af08-179e53e6567c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=431539575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.431539575
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2082067566
Short name	T829
Test name
Test status
Simulation time	9524736403 ps
CPU time	75.4 seconds
Started	May 21 12:43:43 PM PDT 24
Finished	May 21 12:45:03 PM PDT 24
Peak memory	205544 kb
Host	smart-cfb38427-b204-4bfc-8fab-8b2430f98fc3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2082067566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.2082067566
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4030447666
Short name	T281
Test name
Test status
Simulation time	2468113577 ps
CPU time	20.14 seconds
Started	May 21 12:43:43 PM PDT 24
Finished	May 21 12:44:08 PM PDT 24
Peak memory	203892 kb
Host	smart-363c9266-a318-4aae-8248-534ba9ccf73b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4030447666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4030447666
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.2573757847
Short name	T805
Test name
Test status
Simulation time	3267219818 ps
CPU time	27.18 seconds
Started	May 21 12:43:46 PM PDT 24
Finished	May 21 12:44:17 PM PDT 24
Peak memory	203484 kb
Host	smart-6d27fad9-608b-4c28-ac80-e7abd4e7b6f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573757847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2573757847
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.1966650960
Short name	T711
Test name
Test status
Simulation time	551248060 ps
CPU time	18.75 seconds
Started	May 21 12:43:37 PM PDT 24
Finished	May 21 12:43:58 PM PDT 24
Peak memory	204528 kb
Host	smart-e74a7257-7ab8-4d87-b458-c68289e530f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1966650960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1966650960
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3345963848
Short name	T171
Test name
Test status
Simulation time	2976041380 ps
CPU time	12.77 seconds
Started	May 21 12:43:37 PM PDT 24
Finished	May 21 12:43:52 PM PDT 24
Peak memory	203420 kb
Host	smart-1dce66e6-9247-4057-bcad-05e255b61f5d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345963848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3345963848
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3289635370
Short name	T841
Test name
Test status
Simulation time	27911482255 ps
CPU time	179.55 seconds
Started	May 21 12:43:36 PM PDT 24
Finished	May 21 12:46:37 PM PDT 24
Peak memory	204736 kb
Host	smart-1c4afef8-3c54-4322-afef-7baa51eed369
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3289635370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3289635370
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3928305073
Short name	T542
Test name
Test status
Simulation time	113310434 ps
CPU time	14.97 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:43:56 PM PDT 24
Peak memory	211636 kb
Host	smart-8ef9c4f0-1507-4722-9530-35ba2ba2bdd4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928305073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3928305073
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.3816161575
Short name	T513
Test name
Test status
Simulation time	186465051 ps
CPU time	9.64 seconds
Started	May 21 12:43:48 PM PDT 24
Finished	May 21 12:44:01 PM PDT 24
Peak memory	203952 kb
Host	smart-3047a4f7-37b3-4685-a1e9-1b55edcd81be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3816161575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3816161575
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.514390421
Short name	T700
Test name
Test status
Simulation time	69127382 ps
CPU time	2.3 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:43:43 PM PDT 24
Peak memory	203288 kb
Host	smart-7c845f38-cd1f-444c-99eb-ae1c4e2306fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=514390421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.514390421
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.546454068
Short name	T59
Test name
Test status
Simulation time	23223333650 ps
CPU time	40.64 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:44:21 PM PDT 24
Peak memory	203404 kb
Host	smart-159c812e-3691-4079-b2fa-9497d3c84253
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=546454068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.546454068
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3437725721
Short name	T743
Test name
Test status
Simulation time	4351093112 ps
CPU time	29.65 seconds
Started	May 21 12:43:36 PM PDT 24
Finished	May 21 12:44:07 PM PDT 24
Peak memory	203488 kb
Host	smart-dfdd1f4b-5311-44c9-8545-9b6296a93f9f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3437725721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3437725721
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2148859346
Short name	T89
Test name
Test status
Simulation time	33727305 ps
CPU time	2.41 seconds
Started	May 21 12:43:38 PM PDT 24
Finished	May 21 12:43:42 PM PDT 24
Peak memory	203432 kb
Host	smart-62074706-0faf-4550-b9a4-15fd43e19eda
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148859346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2148859346
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.3857985899
Short name	T808
Test name
Test status
Simulation time	22660493495 ps
CPU time	118.14 seconds
Started	May 21 12:43:43 PM PDT 24
Finished	May 21 12:45:46 PM PDT 24
Peak memory	206972 kb
Host	smart-aedbf1af-3dac-4266-84dd-8a63b7531813
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3857985899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3857985899
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2323855411
Short name	T311
Test name
Test status
Simulation time	9582535246 ps
CPU time	117.58 seconds
Started	May 21 12:43:47 PM PDT 24
Finished	May 21 12:45:48 PM PDT 24
Peak memory	206732 kb
Host	smart-093317d1-462b-4849-8139-af20c04f1372
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2323855411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2323855411
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.849910714
Short name	T857
Test name
Test status
Simulation time	584442100 ps
CPU time	263.68 seconds
Started	May 21 12:43:45 PM PDT 24
Finished	May 21 12:48:13 PM PDT 24
Peak memory	208336 kb
Host	smart-67ca4f71-285f-4307-9e07-2838263d1bea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=849910714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_ reset.849910714
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.906528697
Short name	T535
Test name
Test status
Simulation time	2478123456 ps
CPU time	313.84 seconds
Started	May 21 12:43:43 PM PDT 24
Finished	May 21 12:49:01 PM PDT 24
Peak memory	222588 kb
Host	smart-56410266-2eed-4599-9adc-a1c7ab064a7c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=906528697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.906528697
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.522785573
Short name	T292
Test name
Test status
Simulation time	106206682 ps
CPU time	10.37 seconds
Started	May 21 12:43:43 PM PDT 24
Finished	May 21 12:43:58 PM PDT 24
Peak memory	204776 kb
Host	smart-21eeb3b8-c435-4e79-987d-8db357f4f570
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=522785573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.522785573
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.537390347
Short name	T777
Test name
Test status
Simulation time	2372702378 ps
CPU time	37.59 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:44:26 PM PDT 24
Peak memory	206124 kb
Host	smart-3cf8b6e7-67ee-4676-b9d1-49478785efa7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=537390347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.537390347
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1678730361
Short name	T133
Test name
Test status
Simulation time	57183536432 ps
CPU time	519.94 seconds
Started	May 21 12:43:46 PM PDT 24
Finished	May 21 12:52:30 PM PDT 24
Peak memory	207056 kb
Host	smart-3121fe59-148d-4277-a341-76ac2cb06cc6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1678730361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1678730361
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2124977300
Short name	T814
Test name
Test status
Simulation time	1206204568 ps
CPU time	23.35 seconds
Started	May 21 12:43:48 PM PDT 24
Finished	May 21 12:44:15 PM PDT 24
Peak memory	203680 kb
Host	smart-8318a20e-1aab-4e2c-ae49-e0b0079b8a98
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2124977300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2124977300
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.722518678
Short name	T888
Test name
Test status
Simulation time	65050007 ps
CPU time	2.75 seconds
Started	May 21 12:43:46 PM PDT 24
Finished	May 21 12:43:53 PM PDT 24
Peak memory	203440 kb
Host	smart-629a0cc3-85e5-4a83-9a60-57aa306f905b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=722518678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.722518678
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.818694887
Short name	T667
Test name
Test status
Simulation time	381388054 ps
CPU time	15.01 seconds
Started	May 21 12:43:47 PM PDT 24
Finished	May 21 12:44:06 PM PDT 24
Peak memory	204504 kb
Host	smart-afec27c0-0299-4db7-b61f-4010c578f6a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=818694887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.818694887
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.576150287
Short name	T262
Test name
Test status
Simulation time	23504882882 ps
CPU time	106.51 seconds
Started	May 21 12:43:46 PM PDT 24
Finished	May 21 12:45:37 PM PDT 24
Peak memory	211656 kb
Host	smart-9385d349-baef-459f-a35c-a9b71308a1fb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=576150287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.576150287
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2844789845
Short name	T202
Test name
Test status
Simulation time	37008223399 ps
CPU time	143.56 seconds
Started	May 21 12:43:45 PM PDT 24
Finished	May 21 12:46:13 PM PDT 24
Peak memory	211604 kb
Host	smart-540be9de-a398-42b3-8c06-887665ed53d6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2844789845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2844789845
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1615596772
Short name	T893
Test name
Test status
Simulation time	157869367 ps
CPU time	23.14 seconds
Started	May 21 12:43:48 PM PDT 24
Finished	May 21 12:44:14 PM PDT 24
Peak memory	204960 kb
Host	smart-da464528-c36c-4aba-a08c-8713d1a9699e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615596772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1615596772
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.242458875
Short name	T747
Test name
Test status
Simulation time	275250632 ps
CPU time	12.81 seconds
Started	May 21 12:43:45 PM PDT 24
Finished	May 21 12:44:02 PM PDT 24
Peak memory	203444 kb
Host	smart-65194c48-94c0-4ee4-a2d5-f24ed9cf9c45
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=242458875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.242458875
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.1627831489
Short name	T268
Test name
Test status
Simulation time	44482342 ps
CPU time	2.69 seconds
Started	May 21 12:43:46 PM PDT 24
Finished	May 21 12:43:53 PM PDT 24
Peak memory	203452 kb
Host	smart-d43baf71-b378-4b65-86b9-7499c1050cb8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1627831489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1627831489
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1503854027
Short name	T309
Test name
Test status
Simulation time	30484182829 ps
CPU time	37.7 seconds
Started	May 21 12:43:49 PM PDT 24
Finished	May 21 12:44:29 PM PDT 24
Peak memory	203456 kb
Host	smart-0f0c6fc0-618a-4fba-a8bc-e25ed5cccce8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503854027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1503854027
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2691054042
Short name	T287
Test name
Test status
Simulation time	6551839881 ps
CPU time	33.53 seconds
Started	May 21 12:43:46 PM PDT 24
Finished	May 21 12:44:24 PM PDT 24
Peak memory	203376 kb
Host	smart-c55fb80e-77be-4eef-a985-ceef66be863d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2691054042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2691054042
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1089873502
Short name	T603
Test name
Test status
Simulation time	29670620 ps
CPU time	2.24 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:43:51 PM PDT 24
Peak memory	203412 kb
Host	smart-1a9bfa23-37d0-4ab9-b49f-17779390cd2f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089873502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1089873502
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.2958949878
Short name	T597
Test name
Test status
Simulation time	1061030936 ps
CPU time	42.15 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:44:30 PM PDT 24
Peak memory	205560 kb
Host	smart-eaa042f7-4b1c-40e0-bfb5-5ea046a4f891
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2958949878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2958949878
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3046660769
Short name	T407
Test name
Test status
Simulation time	176392594 ps
CPU time	3.05 seconds
Started	May 21 12:43:43 PM PDT 24
Finished	May 21 12:43:51 PM PDT 24
Peak memory	203416 kb
Host	smart-392a2f8a-e241-4e1b-bbd9-6d286a740547
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3046660769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3046660769
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1897809780
Short name	T177
Test name
Test status
Simulation time	8474894751 ps
CPU time	563.94 seconds
Started	May 21 12:43:45 PM PDT 24
Finished	May 21 12:53:13 PM PDT 24
Peak memory	221164 kb
Host	smart-65458045-0c5d-4efb-bcaf-6508a779a0a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1897809780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1897809780
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1572219051
Short name	T286
Test name
Test status
Simulation time	724823537 ps
CPU time	73.67 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:45:03 PM PDT 24
Peak memory	208512 kb
Host	smart-f9e58601-b425-4f8e-b2fe-7ea270b95127
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1572219051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1572219051
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1809530365
Short name	T831
Test name
Test status
Simulation time	273231845 ps
CPU time	11.9 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:44:00 PM PDT 24
Peak memory	205060 kb
Host	smart-d4602989-973a-49c1-a20f-a4ffe56095b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1809530365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1809530365
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3295712337
Short name	T136
Test name
Test status
Simulation time	442263313 ps
CPU time	18.45 seconds
Started	May 21 12:43:54 PM PDT 24
Finished	May 21 12:44:14 PM PDT 24
Peak memory	204084 kb
Host	smart-58e31aa3-0b94-4314-922c-b0f9c887a552
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3295712337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3295712337
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1273719919
Short name	T141
Test name
Test status
Simulation time	47178044159 ps
CPU time	395.32 seconds
Started	May 21 12:43:52 PM PDT 24
Finished	May 21 12:50:30 PM PDT 24
Peak memory	207004 kb
Host	smart-5ce0c37a-e779-42d5-8a27-1b3e5d52650c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1273719919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.1273719919
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.291562758
Short name	T870
Test name
Test status
Simulation time	90688610 ps
CPU time	11.01 seconds
Started	May 21 12:43:54 PM PDT 24
Finished	May 21 12:44:07 PM PDT 24
Peak memory	203888 kb
Host	smart-d7934b91-812d-4fe8-be21-0c1373610d96
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291562758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.291562758
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.4050634568
Short name	T817
Test name
Test status
Simulation time	111054434 ps
CPU time	9.2 seconds
Started	May 21 12:43:55 PM PDT 24
Finished	May 21 12:44:06 PM PDT 24
Peak memory	203424 kb
Host	smart-7a74cc5c-7bd0-4bb3-89c6-6cf4cdedf9e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4050634568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4050634568
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.499749801
Short name	T551
Test name
Test status
Simulation time	46608992 ps
CPU time	6.26 seconds
Started	May 21 12:43:52 PM PDT 24
Finished	May 21 12:44:00 PM PDT 24
Peak memory	204512 kb
Host	smart-d527bf30-f4ea-490b-a837-e5e42965cecc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=499749801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.499749801
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2861104923
Short name	T891
Test name
Test status
Simulation time	30821088015 ps
CPU time	139.47 seconds
Started	May 21 12:43:53 PM PDT 24
Finished	May 21 12:46:15 PM PDT 24
Peak memory	204972 kb
Host	smart-b57489a3-4804-47a6-a3c9-d732b147abe7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861104923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2861104923
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3543403784
Short name	T360
Test name
Test status
Simulation time	33947977370 ps
CPU time	191.71 seconds
Started	May 21 12:43:53 PM PDT 24
Finished	May 21 12:47:08 PM PDT 24
Peak memory	204852 kb
Host	smart-3b4bd576-bd09-4e93-986a-117ff2c6e7ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3543403784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3543403784
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3440168608
Short name	T865
Test name
Test status
Simulation time	148528228 ps
CPU time	19.05 seconds
Started	May 21 12:43:52 PM PDT 24
Finished	May 21 12:44:13 PM PDT 24
Peak memory	204548 kb
Host	smart-5654bacb-1b72-4814-a928-94a56e2b8bda
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440168608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3440168608
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.2109989123
Short name	T592
Test name
Test status
Simulation time	10051248142 ps
CPU time	38.08 seconds
Started	May 21 12:43:54 PM PDT 24
Finished	May 21 12:44:35 PM PDT 24
Peak memory	204592 kb
Host	smart-6e092bc8-03d7-423a-9a1f-251e6e37e158
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2109989123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2109989123
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.2408146753
Short name	T640
Test name
Test status
Simulation time	128634207 ps
CPU time	3.57 seconds
Started	May 21 12:43:45 PM PDT 24
Finished	May 21 12:43:53 PM PDT 24
Peak memory	203320 kb
Host	smart-6c2d0724-2286-4adb-910e-72bc4f1059ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2408146753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2408146753
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2001981869
Short name	T314
Test name
Test status
Simulation time	11237187494 ps
CPU time	27.07 seconds
Started	May 21 12:43:44 PM PDT 24
Finished	May 21 12:44:15 PM PDT 24
Peak memory	203380 kb
Host	smart-64e89a86-7f52-4daf-9e89-13755ed1aacb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001981869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2001981869
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.4281585723
Short name	T489
Test name
Test status
Simulation time	4905438087 ps
CPU time	37.13 seconds
Started	May 21 12:43:49 PM PDT 24
Finished	May 21 12:44:29 PM PDT 24
Peak memory	203484 kb
Host	smart-530f1c16-0542-4bfe-8df8-18cf0894b58f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4281585723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4281585723
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2693257885
Short name	T431
Test name
Test status
Simulation time	39540947 ps
CPU time	2.32 seconds
Started	May 21 12:43:48 PM PDT 24
Finished	May 21 12:43:53 PM PDT 24
Peak memory	203376 kb
Host	smart-27b25c39-e68c-4dd6-b9f1-1b940e341e34
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693257885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2693257885
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.4195695976
Short name	T371
Test name
Test status
Simulation time	2841595450 ps
CPU time	65.88 seconds
Started	May 21 12:43:51 PM PDT 24
Finished	May 21 12:44:59 PM PDT 24
Peak memory	211696 kb
Host	smart-a63192ce-b741-4c30-9bb4-84a973a082aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4195695976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4195695976
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3326672451
Short name	T872
Test name
Test status
Simulation time	3719693863 ps
CPU time	85.21 seconds
Started	May 21 12:43:53 PM PDT 24
Finished	May 21 12:45:21 PM PDT 24
Peak memory	207664 kb
Host	smart-98aa216c-01b5-41a8-82e4-5b78d0e4f3ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3326672451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3326672451
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.177965995
Short name	T23
Test name
Test status
Simulation time	431807875 ps
CPU time	167.14 seconds
Started	May 21 12:43:53 PM PDT 24
Finished	May 21 12:46:42 PM PDT 24
Peak memory	208508 kb
Host	smart-cab4e485-2b4a-432c-88a6-0d7954696974
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177965995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.177965995
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2562006453
Short name	T596
Test name
Test status
Simulation time	120083554 ps
CPU time	24.59 seconds
Started	May 21 12:43:51 PM PDT 24
Finished	May 21 12:44:18 PM PDT 24
Peak memory	205156 kb
Host	smart-e27cfb8d-8e4d-4d6e-ba4a-ee01e28aa0ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2562006453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2562006453
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2634440207
Short name	T213
Test name
Test status
Simulation time	308685513 ps
CPU time	18.84 seconds
Started	May 21 12:43:50 PM PDT 24
Finished	May 21 12:44:11 PM PDT 24
Peak memory	211604 kb
Host	smart-32b4bbc0-009e-4032-b8d5-58cca7c0312b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2634440207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2634440207
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.22858202
Short name	T725
Test name
Test status
Simulation time	638311554 ps
CPU time	46.79 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:44:48 PM PDT 24
Peak memory	211576 kb
Host	smart-77003548-3d02-4395-bb53-88c40e7616b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=22858202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.22858202
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.299111913
Short name	T472
Test name
Test status
Simulation time	71303158976 ps
CPU time	599.19 seconds
Started	May 21 12:44:11 PM PDT 24
Finished	May 21 12:54:14 PM PDT 24
Peak memory	211680 kb
Host	smart-aadd771d-dc3a-4dd5-bf27-ac24981bf015
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=299111913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.299111913
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2064882236
Short name	T722
Test name
Test status
Simulation time	1017296891 ps
CPU time	9.56 seconds
Started	May 21 12:44:10 PM PDT 24
Finished	May 21 12:44:23 PM PDT 24
Peak memory	203332 kb
Host	smart-fccaf11b-c7c6-4caf-9f89-9eb1aae694b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2064882236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2064882236
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.702616351
Short name	T761
Test name
Test status
Simulation time	425321784 ps
CPU time	11.34 seconds
Started	May 21 12:43:57 PM PDT 24
Finished	May 21 12:44:09 PM PDT 24
Peak memory	203432 kb
Host	smart-0145e662-be5a-432e-9189-776b96ae7fb8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702616351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.702616351
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.2115763845
Short name	T370
Test name
Test status
Simulation time	859601962 ps
CPU time	22.72 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:44:24 PM PDT 24
Peak memory	204532 kb
Host	smart-1e1b447b-e74c-4c13-a4b2-60f4b4b0d510
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2115763845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2115763845
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.615685007
Short name	T646
Test name
Test status
Simulation time	24841977808 ps
CPU time	154.05 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:46:35 PM PDT 24
Peak memory	205268 kb
Host	smart-5c0de8e9-27dc-474a-853a-894a520e9920
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=615685007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.615685007
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3464655601
Short name	T512
Test name
Test status
Simulation time	47834481432 ps
CPU time	186.6 seconds
Started	May 21 12:44:00 PM PDT 24
Finished	May 21 12:47:09 PM PDT 24
Peak memory	204648 kb
Host	smart-d4f65017-3d93-47de-ae38-4ae0a04acb03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3464655601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3464655601
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1960324787
Short name	T485
Test name
Test status
Simulation time	255060291 ps
CPU time	11.39 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:44:11 PM PDT 24
Peak memory	211616 kb
Host	smart-59ddcacc-ff76-47ef-bb6e-ef7c85be21cf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960324787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1960324787
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.907830243
Short name	T500
Test name
Test status
Simulation time	1451694814 ps
CPU time	36.97 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:44:36 PM PDT 24
Peak memory	203496 kb
Host	smart-0ad589c9-3979-48ba-a286-b43074935974
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=907830243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.907830243
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.2846185051
Short name	T567
Test name
Test status
Simulation time	349859932 ps
CPU time	3.73 seconds
Started	May 21 12:43:55 PM PDT 24
Finished	May 21 12:44:00 PM PDT 24
Peak memory	203400 kb
Host	smart-54371e33-a158-4929-b075-b9c3adaf7648
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2846185051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2846185051
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2205594426
Short name	T611
Test name
Test status
Simulation time	34670438223 ps
CPU time	47.43 seconds
Started	May 21 12:43:52 PM PDT 24
Finished	May 21 12:44:41 PM PDT 24
Peak memory	203252 kb
Host	smart-dc6b1d0c-9838-4d3c-884e-a3f96902f60b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205594426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2205594426
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3914033773
Short name	T807
Test name
Test status
Simulation time	2359854506 ps
CPU time	22.91 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:44:22 PM PDT 24
Peak memory	203404 kb
Host	smart-82a9efbb-2e4c-41ec-add3-a2f8df00cd71
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3914033773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3914033773
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2078402262
Short name	T90
Test name
Test status
Simulation time	34058367 ps
CPU time	2.13 seconds
Started	May 21 12:43:54 PM PDT 24
Finished	May 21 12:43:58 PM PDT 24
Peak memory	203424 kb
Host	smart-3ed468ce-642c-47fe-ab27-52743e00f688
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078402262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2078402262
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.2237428000
Short name	T625
Test name
Test status
Simulation time	27969755073 ps
CPU time	295.17 seconds
Started	May 21 12:44:01 PM PDT 24
Finished	May 21 12:48:58 PM PDT 24
Peak memory	209936 kb
Host	smart-e067286e-5208-4798-8768-caf1c1e11480
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2237428000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2237428000
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4006396948
Short name	T665
Test name
Test status
Simulation time	4899764995 ps
CPU time	139.96 seconds
Started	May 21 12:44:10 PM PDT 24
Finished	May 21 12:46:33 PM PDT 24
Peak memory	208080 kb
Host	smart-052eec4c-d5d2-4bd6-9150-4e72585a46d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4006396948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4006396948
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3267321726
Short name	T271
Test name
Test status
Simulation time	903400545 ps
CPU time	287.92 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:48:47 PM PDT 24
Peak memory	210040 kb
Host	smart-0a66eed7-7872-45f0-829f-e59be7dd7da7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3267321726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3267321726
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3114280515
Short name	T820
Test name
Test status
Simulation time	3322347665 ps
CPU time	227.62 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:47:48 PM PDT 24
Peak memory	219920 kb
Host	smart-11854bd4-4b7d-4a67-975b-0bc5930af861
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3114280515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.3114280515
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1818161682
Short name	T788
Test name
Test status
Simulation time	108222353 ps
CPU time	3.68 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:44:05 PM PDT 24
Peak memory	204552 kb
Host	smart-ecfc7799-8ca2-4c69-b9d5-8e84ce3173b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1818161682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1818161682
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.4102416740
Short name	T501
Test name
Test status
Simulation time	57098875802 ps
CPU time	219.51 seconds
Started	May 21 12:44:09 PM PDT 24
Finished	May 21 12:47:51 PM PDT 24
Peak memory	206088 kb
Host	smart-9b6f946c-2129-406f-b5b5-bdc4c4f73883
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4102416740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.4102416740
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1078128336
Short name	T843
Test name
Test status
Simulation time	64521990 ps
CPU time	5.36 seconds
Started	May 21 12:44:08 PM PDT 24
Finished	May 21 12:44:16 PM PDT 24
Peak memory	203508 kb
Host	smart-154a4637-0112-46ed-a6cd-5d0f8194b276
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1078128336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1078128336
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.813901334
Short name	T616
Test name
Test status
Simulation time	116272686 ps
CPU time	17.37 seconds
Started	May 21 12:44:06 PM PDT 24
Finished	May 21 12:44:25 PM PDT 24
Peak memory	203424 kb
Host	smart-3009a50b-5170-4548-894c-85407977b334
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=813901334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.813901334
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.3034177557
Short name	T629
Test name
Test status
Simulation time	109593018 ps
CPU time	5.09 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:44:06 PM PDT 24
Peak memory	204556 kb
Host	smart-3534d140-9ae4-40f4-8c57-aa35a064df4b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034177557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3034177557
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.471022516
Short name	T158
Test name
Test status
Simulation time	25792016147 ps
CPU time	79.89 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:45:19 PM PDT 24
Peak memory	205016 kb
Host	smart-42224167-fa4f-47cd-b5e0-ce85b93b5d1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=471022516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.471022516
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2818419134
Short name	T481
Test name
Test status
Simulation time	15881397060 ps
CPU time	119.41 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:45:59 PM PDT 24
Peak memory	204916 kb
Host	smart-7b06ca85-ebf1-47f1-a113-ab7279af621f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2818419134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2818419134
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3646637324
Short name	T566
Test name
Test status
Simulation time	349248709 ps
CPU time	19.16 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:44:21 PM PDT 24
Peak memory	211656 kb
Host	smart-46829e02-50c7-48a1-80bd-42c29fb0ac3b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646637324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3646637324
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.1810636015
Short name	T453
Test name
Test status
Simulation time	413867551 ps
CPU time	9.49 seconds
Started	May 21 12:44:08 PM PDT 24
Finished	May 21 12:44:20 PM PDT 24
Peak memory	203896 kb
Host	smart-b6c1aa69-e0f6-4234-81f2-50ec5284363f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1810636015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1810636015
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.3571092326
Short name	T206
Test name
Test status
Simulation time	35162768 ps
CPU time	2.21 seconds
Started	May 21 12:43:59 PM PDT 24
Finished	May 21 12:44:04 PM PDT 24
Peak memory	203428 kb
Host	smart-8e3a2ce6-4744-4996-be4b-21a285b9455e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3571092326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3571092326
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3409454752
Short name	T792
Test name
Test status
Simulation time	22201503150 ps
CPU time	31.52 seconds
Started	May 21 12:43:56 PM PDT 24
Finished	May 21 12:44:28 PM PDT 24
Peak memory	203456 kb
Host	smart-a4dd31ac-f1f9-4e9f-8cff-6187608b6abe
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409454752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3409454752
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3188563966
Short name	T261
Test name
Test status
Simulation time	3806701360 ps
CPU time	27.21 seconds
Started	May 21 12:43:58 PM PDT 24
Finished	May 21 12:44:27 PM PDT 24
Peak memory	203488 kb
Host	smart-0556402d-4de6-4215-8f61-cdac4e82e035
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3188563966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3188563966
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3089829511
Short name	T245
Test name
Test status
Simulation time	37941268 ps
CPU time	2.21 seconds
Started	May 21 12:44:11 PM PDT 24
Finished	May 21 12:44:17 PM PDT 24
Peak memory	203408 kb
Host	smart-90998de1-5c89-4688-b58a-de910bf3ed20
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089829511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3089829511
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.2823431944
Short name	T440
Test name
Test status
Simulation time	8521728982 ps
CPU time	209.1 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:47:38 PM PDT 24
Peak memory	207596 kb
Host	smart-0f3f4152-b281-4c05-8e68-38a92546d797
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2823431944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2823431944
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3986514488
Short name	T587
Test name
Test status
Simulation time	2778426274 ps
CPU time	61.09 seconds
Started	May 21 12:44:05 PM PDT 24
Finished	May 21 12:45:07 PM PDT 24
Peak memory	204956 kb
Host	smart-2622098a-7281-4a8e-8e67-8408aa8189ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3986514488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3986514488
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1261473104
Short name	T718
Test name
Test status
Simulation time	179111448 ps
CPU time	71.98 seconds
Started	May 21 12:44:08 PM PDT 24
Finished	May 21 12:45:22 PM PDT 24
Peak memory	208248 kb
Host	smart-2f03eed3-d500-49c6-98f0-4558673a19d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1261473104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1261473104
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2652319505
Short name	T519
Test name
Test status
Simulation time	2508467446 ps
CPU time	409.53 seconds
Started	May 21 12:44:08 PM PDT 24
Finished	May 21 12:51:00 PM PDT 24
Peak memory	220040 kb
Host	smart-adf1fdec-e89c-4cda-8ba7-89912493d5f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2652319505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2652319505
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1419760950
Short name	T388
Test name
Test status
Simulation time	894726777 ps
CPU time	18.3 seconds
Started	May 21 12:44:07 PM PDT 24
Finished	May 21 12:44:27 PM PDT 24
Peak memory	211612 kb
Host	smart-476c07ec-e2ae-4da6-8b87-0ad0f114c27e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1419760950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1419760950
Directory	/workspace/9.xbar_unmapped_addr/latest