Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 488 1 T1 1 T2 1 T7 1
all_values[1] 495 1 T1 2 T7 2 T13 1
all_values[2] 507 1 T2 2 T65 4 T5 1
all_values[3] 514 1 T1 1 T2 1 T65 4
all_values[4] 486 1 T1 2 T2 2 T13 1
all_values[5] 496 1 T1 2 T7 1 T13 1
all_values[6] 549 1 T1 2 T13 1 T15 1
all_values[7] 478 1 T1 2 T2 1 T13 1
all_values[8] 453 1 T1 1 T13 1 T65 2
all_values[9] 498 1 T1 1 T20 2 T65 2
all_values[10] 512 1 T2 2 T7 3 T20 2
all_values[11] 485 1 T15 1 T65 6 T5 2
all_values[12] 496 1 T13 1 T15 1 T18 2
all_values[13] 499 1 T7 1 T15 2 T20 1
all_values[14] 497 1 T1 1 T13 1 T15 2
all_values[15] 489 1 T2 1 T15 1 T20 1
all_values[16] 483 1 T1 1 T13 1 T65 5
all_values[17] 520 1 T2 2 T15 1 T18 1
all_values[18] 476 1 T13 2 T18 2 T20 1
all_values[19] 512 1 T13 1 T65 7 T5 10
all_values[20] 493 1 T18 1 T65 2 T5 4
all_values[21] 483 1 T7 1 T18 1 T20 1
all_values[22] 471 1 T1 1 T7 1 T65 3
all_values[23] 499 1 T65 2 T5 3 T164 1

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