Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1890	1			T2	2		T7	3		T68	3
all_values[1]	1919	1			T2	3		T7	3		T68	1
all_values[2]	1874	1			T2	4		T7	2		T68	2
all_values[3]	1915	1			T2	1		T7	3		T20	1
all_values[4]	1855	1			T2	4		T7	3		T68	1
all_values[5]	1988	1			T2	1		T7	6		T20	3
all_values[6]	1933	1			T2	1		T7	3		T65	29
all_values[7]	1862	1			T2	3		T7	7		T68	1
all_values[8]	1839	1			T2	2		T7	5		T68	2
all_values[9]	1936	1			T2	2		T7	4		T68	1
all_values[10]	1869	1			T2	2		T7	5		T68	3
all_values[11]	1884	1			T2	4		T7	2		T20	1
all_values[12]	1904	1			T7	6		T68	1		T20	1
all_values[13]	1936	1			T2	2		T7	4		T68	3
all_values[14]	1889	1			T2	1		T7	4		T68	1
all_values[15]	1887	1			T2	1		T7	6		T68	3
all_values[16]	1904	1			T2	2		T7	6		T68	2
all_values[17]	1863	1			T2	3		T7	2		T68	1
all_values[18]	1925	1			T2	2		T7	3		T65	39
all_values[19]	1881	1			T2	3		T7	4		T68	2
all_values[20]	1886	1			T2	3		T7	6		T68	3
all_values[21]	1898	1			T2	1		T7	5		T68	1
all_values[22]	1935	1			T7	7		T68	3		T20	1
all_values[23]	1823	1			T2	2		T7	6		T68	1
all_values[24]	1904	1			T2	6		T7	4		T68	1
all_values[25]	1923	1			T2	5		T7	2		T68	3
all_values[26]	1850	1			T2	2		T7	6		T68	1
all_values[27]	1898	1			T2	1		T7	4		T20	1
all_values[28]	1823	1			T2	1		T7	9		T20	1
all_values[29]	1929	1			T2	5		T7	5		T68	1
all_values[30]	1876	1			T2	2		T7	5		T68	1
all_values[31]	1927	1			T2	3		T7	1		T20	1
all_values[32]	1882	1			T2	2		T7	4		T68	1
all_values[33]	1902	1			T2	2		T7	4		T68	1
all_values[34]	1796	1			T2	2		T7	3		T68	1
all_values[35]	1946	1			T2	2		T7	1		T68	1
all_values[36]	1971	1			T2	3		T7	6		T68	1
all_values[37]	1952	1			T2	2		T7	12		T68	1
all_values[38]	1920	1			T2	3		T7	7		T68	2
all_values[39]	1828	1			T2	2		T7	3		T68	1
all_values[40]	1857	1			T2	4		T7	4		T68	4
all_values[41]	1829	1			T2	4		T7	7		T68	1
all_values[42]	1886	1			T2	5		T7	5		T68	1
all_values[43]	1919	1			T2	4		T7	6		T20	3
all_values[44]	1870	1			T2	2		T7	1		T20	1
all_values[45]	1863	1			T2	1		T7	8		T68	3
all_values[46]	1854	1			T2	3		T7	4		T68	1
all_values[47]	1870	1			T2	2		T7	4		T68	1
all_values[48]	1881	1			T2	1		T7	5		T68	1
all_values[49]	1883	1			T2	1		T7	4		T68	1
all_values[50]	1874	1			T2	1		T7	6		T68	1
all_values[51]	1883	1			T2	2		T7	5		T68	1
all_values[52]	1874	1			T2	1		T7	4		T68	1
all_values[53]	1820	1			T2	1		T7	5		T68	3
all_values[54]	1817	1			T2	1		T7	7		T68	1
all_values[55]	1821	1			T2	1		T7	9		T68	2
all_values[56]	1991	1			T2	3		T7	3		T20	1
all_values[57]	1907	1			T2	5		T7	8		T20	1
all_values[58]	1936	1			T2	3		T7	8		T68	2
all_values[59]	1885	1			T2	3		T7	2		T68	3
all_values[60]	1921	1			T2	4		T7	5		T65	26
all_values[61]	1959	1			T2	3		T7	4		T68	1
all_values[62]	1917	1			T2	2		T7	5		T68	1
all_values[63]	1883	1			T2	3		T7	6		T68	1