Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	99.26	88.92	98.80		95.88	99.26	100.00

Total test records in report: 900

T763	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.1589242905	May 23 12:37:34 PM PDT 24	May 23 12:38:00 PM PDT 24	221986538 ps
T764	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3274353290	May 23 12:38:27 PM PDT 24	May 23 12:38:30 PM PDT 24	15253555 ps
T765	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.96522978	May 23 12:41:11 PM PDT 24	May 23 12:41:47 PM PDT 24	6933059449 ps
T766	/workspace/coverage/xbar_build_mode/39.xbar_error_random.2549591978	May 23 12:40:43 PM PDT 24	May 23 12:40:53 PM PDT 24	84374210 ps
T767	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1007432932	May 23 12:38:43 PM PDT 24	May 23 12:38:47 PM PDT 24	39860352 ps
T227	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1654913873	May 23 12:40:33 PM PDT 24	May 23 12:41:15 PM PDT 24	18014572517 ps
T768	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.671506298	May 23 12:39:42 PM PDT 24	May 23 12:40:16 PM PDT 24	4024188756 ps
T769	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2796921654	May 23 12:41:14 PM PDT 24	May 23 12:48:51 PM PDT 24	225493012086 ps
T770	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3631865803	May 23 12:38:55 PM PDT 24	May 23 12:39:22 PM PDT 24	1329693840 ps
T115	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.414478246	May 23 12:39:48 PM PDT 24	May 23 12:40:42 PM PDT 24	1207925158 ps
T771	/workspace/coverage/xbar_build_mode/30.xbar_error_random.1833280662	May 23 12:40:05 PM PDT 24	May 23 12:40:20 PM PDT 24	355292589 ps
T772	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2182421836	May 23 12:40:19 PM PDT 24	May 23 12:40:24 PM PDT 24	46300668 ps
T773	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2029447442	May 23 12:41:15 PM PDT 24	May 23 12:41:30 PM PDT 24	192910329 ps
T774	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1133345289	May 23 12:37:43 PM PDT 24	May 23 12:38:48 PM PDT 24	2597172513 ps
T775	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2258024280	May 23 12:38:42 PM PDT 24	May 23 12:40:17 PM PDT 24	3285426957 ps
T776	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.161889830	May 23 12:39:46 PM PDT 24	May 23 12:41:41 PM PDT 24	411894825 ps
T777	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1135227122	May 23 12:41:13 PM PDT 24	May 23 12:41:57 PM PDT 24	12699079075 ps
T778	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1630047125	May 23 12:37:56 PM PDT 24	May 23 12:38:29 PM PDT 24	312928189 ps
T779	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3867590763	May 23 12:38:41 PM PDT 24	May 23 12:38:46 PM PDT 24	39414935 ps
T780	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3771847457	May 23 12:40:42 PM PDT 24	May 23 12:42:28 PM PDT 24	1438900520 ps
T781	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.2220119927	May 23 12:38:43 PM PDT 24	May 23 12:41:06 PM PDT 24	1154394636 ps
T782	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.4282142590	May 23 12:37:43 PM PDT 24	May 23 12:37:51 PM PDT 24	64875526 ps
T783	/workspace/coverage/xbar_build_mode/29.xbar_random.688107518	May 23 12:40:01 PM PDT 24	May 23 12:40:10 PM PDT 24	144585040 ps
T229	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1224515063	May 23 12:40:33 PM PDT 24	May 23 12:41:47 PM PDT 24	4382996223 ps
T784	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2776338347	May 23 12:38:53 PM PDT 24	May 23 12:42:41 PM PDT 24	90974498299 ps
T64	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1529465670	May 23 12:40:19 PM PDT 24	May 23 12:41:39 PM PDT 24	16702410226 ps
T785	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1436730855	May 23 12:40:37 PM PDT 24	May 23 12:40:41 PM PDT 24	34182466 ps
T786	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.683401304	May 23 12:40:02 PM PDT 24	May 23 12:40:32 PM PDT 24	42956862 ps
T205	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.214675356	May 23 12:40:35 PM PDT 24	May 23 12:44:22 PM PDT 24	97070168673 ps
T787	/workspace/coverage/xbar_build_mode/23.xbar_random.670063824	May 23 12:39:18 PM PDT 24	May 23 12:39:39 PM PDT 24	1676204126 ps
T788	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1261067221	May 23 12:38:43 PM PDT 24	May 23 12:39:08 PM PDT 24	185707863 ps
T789	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2669160590	May 23 12:39:20 PM PDT 24	May 23 12:43:14 PM PDT 24	2094797841 ps
T790	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2928234196	May 23 12:38:21 PM PDT 24	May 23 12:38:50 PM PDT 24	4378952302 ps
T791	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1194417234	May 23 12:40:05 PM PDT 24	May 23 12:40:15 PM PDT 24	1046535433 ps
T792	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.28217858	May 23 12:41:12 PM PDT 24	May 23 12:46:27 PM PDT 24	923629881 ps
T793	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2419066901	May 23 12:37:56 PM PDT 24	May 23 12:44:56 PM PDT 24	8317327834 ps
T794	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.294325264	May 23 12:38:54 PM PDT 24	May 23 12:42:36 PM PDT 24	24508930413 ps
T163	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.971142224	May 23 12:37:33 PM PDT 24	May 23 12:37:54 PM PDT 24	982473247 ps
T795	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.277591303	May 23 12:39:06 PM PDT 24	May 23 12:39:31 PM PDT 24	3969130881 ps
T796	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1351590469	May 23 12:38:41 PM PDT 24	May 23 12:39:29 PM PDT 24	2825786825 ps
T797	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2373645057	May 23 12:38:57 PM PDT 24	May 23 12:40:06 PM PDT 24	11234871014 ps
T798	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1399687147	May 23 12:38:52 PM PDT 24	May 23 12:39:17 PM PDT 24	3926086947 ps
T799	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3540794689	May 23 12:40:15 PM PDT 24	May 23 12:40:19 PM PDT 24	32720468 ps
T222	/workspace/coverage/xbar_build_mode/26.xbar_random.2409633361	May 23 12:39:31 PM PDT 24	May 23 12:40:12 PM PDT 24	1291453717 ps
T800	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1024356108	May 23 12:40:37 PM PDT 24	May 23 12:40:55 PM PDT 24	336092741 ps
T801	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1398529220	May 23 12:40:26 PM PDT 24	May 23 12:40:35 PM PDT 24	81466441 ps
T802	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1622953806	May 23 12:40:35 PM PDT 24	May 23 12:41:12 PM PDT 24	6788346354 ps
T803	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1423112730	May 23 12:40:19 PM PDT 24	May 23 12:49:46 PM PDT 24	91532835026 ps
T804	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3014689782	May 23 12:40:27 PM PDT 24	May 23 12:40:49 PM PDT 24	298764016 ps
T805	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2705466565	May 23 12:38:43 PM PDT 24	May 23 12:44:39 PM PDT 24	61478557453 ps
T806	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1764182539	May 23 12:38:11 PM PDT 24	May 23 12:38:32 PM PDT 24	716476915 ps
T807	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.27078178	May 23 12:38:55 PM PDT 24	May 23 12:38:59 PM PDT 24	40487433 ps
T808	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1729333135	May 23 12:41:10 PM PDT 24	May 23 12:43:58 PM PDT 24	2335151526 ps
T809	/workspace/coverage/xbar_build_mode/43.xbar_error_random.2953530766	May 23 12:41:00 PM PDT 24	May 23 12:41:12 PM PDT 24	553676344 ps
T810	/workspace/coverage/xbar_build_mode/24.xbar_random.319249470	May 23 12:39:23 PM PDT 24	May 23 12:39:31 PM PDT 24	223715568 ps
T811	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.1847520489	May 23 12:40:18 PM PDT 24	May 23 12:40:42 PM PDT 24	352769104 ps
T812	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.1399866364	May 23 12:37:58 PM PDT 24	May 23 12:38:43 PM PDT 24	1286499503 ps
T813	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2847801605	May 23 12:39:03 PM PDT 24	May 23 12:39:37 PM PDT 24	7762950172 ps
T228	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3701236507	May 23 12:40:44 PM PDT 24	May 23 12:44:09 PM PDT 24	42591933851 ps
T814	/workspace/coverage/xbar_build_mode/42.xbar_random.3247400614	May 23 12:40:46 PM PDT 24	May 23 12:40:58 PM PDT 24	1189592276 ps
T815	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2636855614	May 23 12:37:57 PM PDT 24	May 23 12:41:49 PM PDT 24	45696544301 ps
T816	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.4248571448	May 23 12:37:33 PM PDT 24	May 23 12:37:53 PM PDT 24	1609546348 ps
T817	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.275912566	May 23 12:40:49 PM PDT 24	May 23 12:40:53 PM PDT 24	27687913 ps
T818	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.465850757	May 23 12:38:10 PM PDT 24	May 23 12:38:14 PM PDT 24	26043195 ps
T819	/workspace/coverage/xbar_build_mode/46.xbar_smoke.2048351124	May 23 12:41:03 PM PDT 24	May 23 12:41:11 PM PDT 24	152732016 ps
T820	/workspace/coverage/xbar_build_mode/48.xbar_error_random.4000882477	May 23 12:41:12 PM PDT 24	May 23 12:41:29 PM PDT 24	432083360 ps
T821	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3962434473	May 23 12:37:58 PM PDT 24	May 23 12:41:38 PM PDT 24	738945950 ps
T36	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4137488788	May 23 12:39:58 PM PDT 24	May 23 12:41:23 PM PDT 24	299506027 ps
T822	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.1173317150	May 23 12:41:00 PM PDT 24	May 23 12:42:02 PM PDT 24	435376191 ps
T823	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4098089688	May 23 12:39:33 PM PDT 24	May 23 12:46:09 PM PDT 24	4521409411 ps
T824	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1514335777	May 23 12:38:41 PM PDT 24	May 23 12:39:06 PM PDT 24	4361307104 ps
T825	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3213135657	May 23 12:39:32 PM PDT 24	May 23 12:41:07 PM PDT 24	32392579519 ps
T826	/workspace/coverage/xbar_build_mode/0.xbar_same_source.4110868681	May 23 12:37:30 PM PDT 24	May 23 12:38:05 PM PDT 24	2022547854 ps
T827	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2377818518	May 23 12:40:18 PM PDT 24	May 23 12:47:13 PM PDT 24	7992509268 ps
T828	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.848692078	May 23 12:39:32 PM PDT 24	May 23 12:40:00 PM PDT 24	5668807645 ps
T829	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.695605822	May 23 12:38:44 PM PDT 24	May 23 12:40:21 PM PDT 24	4757355687 ps
T830	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1624668017	May 23 12:38:42 PM PDT 24	May 23 12:38:48 PM PDT 24	58334520 ps
T831	/workspace/coverage/xbar_build_mode/33.xbar_same_source.2378852018	May 23 12:40:18 PM PDT 24	May 23 12:40:39 PM PDT 24	3349982475 ps
T832	/workspace/coverage/xbar_build_mode/17.xbar_error_random.3982147146	May 23 12:38:45 PM PDT 24	May 23 12:38:55 PM PDT 24	57344993 ps
T833	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3754555413	May 23 12:38:00 PM PDT 24	May 23 12:38:26 PM PDT 24	617711557 ps
T834	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2080756419	May 23 12:39:07 PM PDT 24	May 23 12:39:23 PM PDT 24	144056626 ps
T835	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3444791994	May 23 12:40:01 PM PDT 24	May 23 12:40:21 PM PDT 24	128430617 ps
T836	/workspace/coverage/xbar_build_mode/22.xbar_same_source.1484652715	May 23 12:39:15 PM PDT 24	May 23 12:39:23 PM PDT 24	338958074 ps
T837	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2668529014	May 23 12:40:48 PM PDT 24	May 23 12:41:51 PM PDT 24	3117061468 ps
T838	/workspace/coverage/xbar_build_mode/19.xbar_random.668244575	May 23 12:38:51 PM PDT 24	May 23 12:39:17 PM PDT 24	862731919 ps
T839	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.228967352	May 23 12:38:25 PM PDT 24	May 23 12:40:57 PM PDT 24	42480080237 ps
T840	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1450588321	May 23 12:40:14 PM PDT 24	May 23 12:41:11 PM PDT 24	10291407348 ps
T841	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.798780092	May 23 12:38:22 PM PDT 24	May 23 12:41:15 PM PDT 24	32120056613 ps
T842	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1605118734	May 23 12:39:20 PM PDT 24	May 23 12:40:44 PM PDT 24	2981455043 ps
T843	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4243420127	May 23 12:40:04 PM PDT 24	May 23 12:40:50 PM PDT 24	25921100243 ps
T844	/workspace/coverage/xbar_build_mode/6.xbar_error_random.1814017009	May 23 12:38:01 PM PDT 24	May 23 12:38:27 PM PDT 24	1447688625 ps
T845	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2729316522	May 23 12:37:42 PM PDT 24	May 23 12:38:11 PM PDT 24	6202444691 ps
T37	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.919100869	May 23 12:40:58 PM PDT 24	May 23 12:51:36 PM PDT 24	18114999405 ps
T846	/workspace/coverage/xbar_build_mode/46.xbar_random.963587873	May 23 12:41:10 PM PDT 24	May 23 12:41:27 PM PDT 24	93257954 ps
T847	/workspace/coverage/xbar_build_mode/31.xbar_random.2687590740	May 23 12:40:13 PM PDT 24	May 23 12:40:30 PM PDT 24	873233677 ps
T848	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2484122611	May 23 12:38:40 PM PDT 24	May 23 12:38:44 PM PDT 24	98482342 ps
T849	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4236597038	May 23 12:41:09 PM PDT 24	May 23 12:41:30 PM PDT 24	134569227 ps
T120	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.3141198148	May 23 12:38:23 PM PDT 24	May 23 12:40:31 PM PDT 24	6962074655 ps
T850	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4147383347	May 23 12:37:57 PM PDT 24	May 23 12:38:01 PM PDT 24	29538898 ps
T851	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3720203357	May 23 12:39:21 PM PDT 24	May 23 12:45:52 PM PDT 24	168063975374 ps
T852	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1097331997	May 23 12:39:09 PM PDT 24	May 23 12:39:34 PM PDT 24	564546673 ps
T853	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.516564023	May 23 12:37:41 PM PDT 24	May 23 12:37:56 PM PDT 24	275121277 ps
T854	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3688703972	May 23 12:40:57 PM PDT 24	May 23 12:43:28 PM PDT 24	10817866616 ps
T855	/workspace/coverage/xbar_build_mode/6.xbar_random.3145507381	May 23 12:37:56 PM PDT 24	May 23 12:38:00 PM PDT 24	146995495 ps
T856	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2227490506	May 23 12:37:41 PM PDT 24	May 23 12:38:03 PM PDT 24	1581629736 ps
T857	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.4100911126	May 23 12:38:42 PM PDT 24	May 23 12:40:10 PM PDT 24	289982671 ps
T858	/workspace/coverage/xbar_build_mode/12.xbar_error_random.2857824311	May 23 12:38:22 PM PDT 24	May 23 12:38:27 PM PDT 24	297991237 ps
T859	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2696425082	May 23 12:40:57 PM PDT 24	May 23 12:45:17 PM PDT 24	36901716763 ps
T860	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.4207985081	May 23 12:40:46 PM PDT 24	May 23 12:44:15 PM PDT 24	13883071821 ps
T861	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.549532666	May 23 12:38:40 PM PDT 24	May 23 12:40:11 PM PDT 24	6012839666 ps
T862	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1841312627	May 23 12:40:42 PM PDT 24	May 23 12:41:37 PM PDT 24	72245676 ps
T863	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3823573718	May 23 12:41:02 PM PDT 24	May 23 12:41:42 PM PDT 24	4580478950 ps
T864	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1977074908	May 23 12:38:16 PM PDT 24	May 23 12:40:27 PM PDT 24	340121564 ps
T865	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2604161839	May 23 12:40:18 PM PDT 24	May 23 12:40:56 PM PDT 24	8220402246 ps
T866	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4037764684	May 23 12:40:26 PM PDT 24	May 23 12:40:55 PM PDT 24	3924797426 ps
T867	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1668193149	May 23 12:41:03 PM PDT 24	May 23 12:48:28 PM PDT 24	2289723560 ps
T868	/workspace/coverage/xbar_build_mode/28.xbar_error_random.1205939566	May 23 12:40:00 PM PDT 24	May 23 12:40:07 PM PDT 24	61708705 ps
T869	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2682990487	May 23 12:41:06 PM PDT 24	May 23 12:41:37 PM PDT 24	6119307858 ps
T870	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3143020818	May 23 12:39:48 PM PDT 24	May 23 12:42:54 PM PDT 24	24361540687 ps
T871	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3631184885	May 23 12:37:42 PM PDT 24	May 23 12:39:04 PM PDT 24	757789729 ps
T872	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3878955123	May 23 12:41:01 PM PDT 24	May 23 12:41:13 PM PDT 24	95640360 ps
T873	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3495317979	May 23 12:38:58 PM PDT 24	May 23 12:39:26 PM PDT 24	4865379693 ps
T874	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.854835829	May 23 12:38:46 PM PDT 24	May 23 12:44:56 PM PDT 24	299127302127 ps
T875	/workspace/coverage/xbar_build_mode/35.xbar_same_source.2345980549	May 23 12:40:25 PM PDT 24	May 23 12:40:43 PM PDT 24	953125296 ps
T876	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.4107359437	May 23 12:40:32 PM PDT 24	May 23 12:44:51 PM PDT 24	115790159886 ps
T877	/workspace/coverage/xbar_build_mode/38.xbar_same_source.1638512034	May 23 12:40:33 PM PDT 24	May 23 12:40:39 PM PDT 24	60859470 ps
T878	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.560421652	May 23 12:39:59 PM PDT 24	May 23 12:50:53 PM PDT 24	218980262233 ps
T879	/workspace/coverage/xbar_build_mode/5.xbar_error_random.2943436912	May 23 12:37:57 PM PDT 24	May 23 12:38:13 PM PDT 24	243184257 ps
T880	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3652929543	May 23 12:41:02 PM PDT 24	May 23 12:42:32 PM PDT 24	3176031573 ps
T881	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.414764443	May 23 12:40:00 PM PDT 24	May 23 12:40:17 PM PDT 24	150250052 ps
T882	/workspace/coverage/xbar_build_mode/10.xbar_smoke.2633383897	May 23 12:38:13 PM PDT 24	May 23 12:38:18 PM PDT 24	204903630 ps
T883	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1197262403	May 23 12:40:57 PM PDT 24	May 23 12:44:21 PM PDT 24	54335116515 ps
T884	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1957528772	May 23 12:40:17 PM PDT 24	May 23 12:41:23 PM PDT 24	53084336681 ps
T885	/workspace/coverage/xbar_build_mode/44.xbar_smoke.2183104963	May 23 12:40:59 PM PDT 24	May 23 12:41:06 PM PDT 24	199075521 ps
T886	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1172268680	May 23 12:40:56 PM PDT 24	May 23 12:41:20 PM PDT 24	1316039592 ps
T887	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3731309825	May 23 12:40:16 PM PDT 24	May 23 12:40:40 PM PDT 24	975019902 ps
T888	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4046085841	May 23 12:39:25 PM PDT 24	May 23 12:39:55 PM PDT 24	8128006478 ps
T889	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1091180711	May 23 12:38:24 PM PDT 24	May 23 12:42:27 PM PDT 24	49573962936 ps
T890	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1379112588	May 23 12:40:16 PM PDT 24	May 23 12:43:30 PM PDT 24	32919680444 ps
T121	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2092790038	May 23 12:37:47 PM PDT 24	May 23 12:38:15 PM PDT 24	1009184361 ps
T891	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.830661704	May 23 12:38:14 PM PDT 24	May 23 12:41:54 PM PDT 24	5691562875 ps
T892	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1196228651	May 23 12:38:26 PM PDT 24	May 23 12:43:43 PM PDT 24	38282200417 ps
T893	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.933060627	May 23 12:40:25 PM PDT 24	May 23 12:41:12 PM PDT 24	106573576 ps
T894	/workspace/coverage/xbar_build_mode/2.xbar_error_random.417823314	May 23 12:37:58 PM PDT 24	May 23 12:38:07 PM PDT 24	55922638 ps
T895	/workspace/coverage/xbar_build_mode/0.xbar_error_random.12917059	May 23 12:37:30 PM PDT 24	May 23 12:37:53 PM PDT 24	900160140 ps
T896	/workspace/coverage/xbar_build_mode/5.xbar_smoke.4019263505	May 23 12:37:58 PM PDT 24	May 23 12:38:04 PM PDT 24	141247745 ps
T897	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2220564406	May 23 12:40:18 PM PDT 24	May 23 12:40:32 PM PDT 24	126330654 ps
T898	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.651477673	May 23 12:39:32 PM PDT 24	May 23 12:39:58 PM PDT 24	3733072040 ps
T899	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1726899047	May 23 12:39:08 PM PDT 24	May 23 12:39:13 PM PDT 24	51799836 ps
T900	/workspace/coverage/xbar_build_mode/22.xbar_error_random.433509949	May 23 12:39:11 PM PDT 24	May 23 12:39:16 PM PDT 24	21219346 ps

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.3215402343
Short name	T7
Test name
Test status
Simulation time	6502936527 ps
CPU time	98.13 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:40:21 PM PDT 24
Peak memory	207884 kb
Host	smart-091d734c-8561-4674-8114-dd35109e181a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215402343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3215402343
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1255358573
Short name	T71
Test name
Test status
Simulation time	157681226828 ps
CPU time	705.35 seconds
Started	May 23 12:41:09 PM PDT 24
Finished	May 23 12:52:55 PM PDT 24
Peak memory	207560 kb
Host	smart-6b6609f1-6894-4141-8ec1-e5241951bb25
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1255358573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.1255358573
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4291970775
Short name	T34
Test name
Test status
Simulation time	11097666306 ps
CPU time	445.46 seconds
Started	May 23 12:41:04 PM PDT 24
Finished	May 23 12:48:32 PM PDT 24
Peak memory	226748 kb
Host	smart-7e53258d-b2af-4323-8df6-fed18c461f7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4291970775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.4291970775
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3709281516
Short name	T5
Test name
Test status
Simulation time	1152570977 ps
CPU time	196.26 seconds
Started	May 23 12:39:34 PM PDT 24
Finished	May 23 12:42:52 PM PDT 24
Peak memory	209732 kb
Host	smart-53e08c35-3941-4dd5-8d14-356c5334e3c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3709281516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.3709281516
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.10983518
Short name	T80
Test name
Test status
Simulation time	41277316738 ps
CPU time	371.48 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:44:12 PM PDT 24
Peak memory	206652 kb
Host	smart-952ce7e0-4183-4dd7-91c5-031dccda943d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=10983518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.10983518
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1232829952
Short name	T3
Test name
Test status
Simulation time	20919617034 ps
CPU time	118.49 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:39:46 PM PDT 24
Peak memory	204408 kb
Host	smart-a36452ba-2981-41a5-8425-9c4e3992cec2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232829952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1232829952
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1318070623
Short name	T72
Test name
Test status
Simulation time	158809659578 ps
CPU time	575.38 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:49:39 PM PDT 24
Peak memory	207052 kb
Host	smart-8ab65575-88a2-44bb-ab1e-8043eb4dd33a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1318070623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.1318070623
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.503466867
Short name	T18
Test name
Test status
Simulation time	5454168441 ps
CPU time	137.6 seconds
Started	May 23 12:39:17 PM PDT 24
Finished	May 23 12:41:35 PM PDT 24
Peak memory	211500 kb
Host	smart-6a2cee24-f764-4fe0-8293-e3cd6e1af828
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=503466867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.503466867
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2835102745
Short name	T29
Test name
Test status
Simulation time	3320863277 ps
CPU time	363.73 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:47:09 PM PDT 24
Peak memory	225340 kb
Host	smart-6e0f9e90-9670-4c44-87d5-2d9f34f0068a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2835102745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.2835102745
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1655565484
Short name	T65
Test name
Test status
Simulation time	525953713 ps
CPU time	220.21 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:44:45 PM PDT 24
Peak memory	208372 kb
Host	smart-90c35b70-23b7-4bb4-8097-8e3d951343ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1655565484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.1655565484
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1754628147
Short name	T85
Test name
Test status
Simulation time	86661942878 ps
CPU time	729.36 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:51:59 PM PDT 24
Peak memory	207536 kb
Host	smart-4caac86e-0e30-4461-a0b6-4c8e92f7125f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1754628147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.1754628147
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2089563102
Short name	T240
Test name
Test status
Simulation time	598647253 ps
CPU time	185.41 seconds
Started	May 23 12:38:39 PM PDT 24
Finished	May 23 12:41:45 PM PDT 24
Peak memory	208432 kb
Host	smart-5af9fac7-9cb7-498f-8b9e-38842e5a2b70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2089563102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2089563102
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3957383072
Short name	T40
Test name
Test status
Simulation time	909704549 ps
CPU time	338.72 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:44:26 PM PDT 24
Peak memory	208784 kb
Host	smart-ff5e0ad7-352f-4665-b24f-78074b928346
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3957383072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3957383072
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.4162266994
Short name	T13
Test name
Test status
Simulation time	1060571843 ps
CPU time	45.25 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:45 PM PDT 24
Peak memory	211516 kb
Host	smart-c550a044-3c97-4832-a47c-92c284342e4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4162266994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.4162266994
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1192205828
Short name	T41
Test name
Test status
Simulation time	1662760123 ps
CPU time	256.85 seconds
Started	May 23 12:37:42 PM PDT 24
Finished	May 23 12:42:02 PM PDT 24
Peak memory	219640 kb
Host	smart-cae27b10-3003-42c9-b8d7-3041aeabbd1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1192205828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.1192205828
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4009307945
Short name	T35
Test name
Test status
Simulation time	7770928154 ps
CPU time	309.11 seconds
Started	May 23 12:39:48 PM PDT 24
Finished	May 23 12:45:00 PM PDT 24
Peak memory	224044 kb
Host	smart-95ed8e57-f38c-4f9f-ae8f-9d43b19269fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4009307945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.4009307945
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.117206581
Short name	T33
Test name
Test status
Simulation time	207536878 ps
CPU time	71.02 seconds
Started	May 23 12:40:14 PM PDT 24
Finished	May 23 12:41:26 PM PDT 24
Peak memory	207868 kb
Host	smart-d3bc9291-41d3-48ff-954f-444687eb8e5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117206581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand _reset.117206581
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1794036186
Short name	T62
Test name
Test status
Simulation time	46700785794 ps
CPU time	243.59 seconds
Started	May 23 12:37:32 PM PDT 24
Finished	May 23 12:41:38 PM PDT 24
Peak memory	204480 kb
Host	smart-af4aaca7-5054-4afe-9846-91e0a516828c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794036186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1794036186
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3340264396
Short name	T84
Test name
Test status
Simulation time	1267308588 ps
CPU time	36.88 seconds
Started	May 23 12:38:21 PM PDT 24
Finished	May 23 12:38:58 PM PDT 24
Peak memory	211444 kb
Host	smart-a815cf9f-193c-4dc3-9ea4-0d1709656d21
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3340264396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3340264396
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.971142224
Short name	T163
Test name
Test status
Simulation time	982473247 ps
CPU time	19.37 seconds
Started	May 23 12:37:33 PM PDT 24
Finished	May 23 12:37:54 PM PDT 24
Peak memory	204308 kb
Host	smart-cf0cfc4e-5b59-4f62-a621-7cec2e0cc895
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=971142224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.971142224
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2517375467
Short name	T635
Test name
Test status
Simulation time	14980270442 ps
CPU time	135.09 seconds
Started	May 23 12:37:30 PM PDT 24
Finished	May 23 12:39:47 PM PDT 24
Peak memory	205940 kb
Host	smart-fabc204c-ea8d-42b0-808d-670e43438301
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2517375467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2517375467
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.4248571448
Short name	T816
Test name
Test status
Simulation time	1609546348 ps
CPU time	18.18 seconds
Started	May 23 12:37:33 PM PDT 24
Finished	May 23 12:37:53 PM PDT 24
Peak memory	203568 kb
Host	smart-416e40f3-cbc3-46d8-8040-2026fc573eb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4248571448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.4248571448
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.12917059
Short name	T895
Test name
Test status
Simulation time	900160140 ps
CPU time	22.07 seconds
Started	May 23 12:37:30 PM PDT 24
Finished	May 23 12:37:53 PM PDT 24
Peak memory	203296 kb
Host	smart-388dc281-1baa-4947-a9d1-75ddc1f82155
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=12917059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.12917059
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.303566777
Short name	T49
Test name
Test status
Simulation time	620360794 ps
CPU time	16.04 seconds
Started	May 23 12:37:28 PM PDT 24
Finished	May 23 12:37:45 PM PDT 24
Peak memory	204568 kb
Host	smart-24ef2c1e-9734-4077-898a-513227e92930
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303566777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.303566777
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.4294190585
Short name	T420
Test name
Test status
Simulation time	8178901911 ps
CPU time	54.4 seconds
Started	May 23 12:37:33 PM PDT 24
Finished	May 23 12:38:29 PM PDT 24
Peak memory	211620 kb
Host	smart-3b107cb7-956f-4a49-a0c7-612c0ed322a7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4294190585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4294190585
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3504754138
Short name	T393
Test name
Test status
Simulation time	57563667 ps
CPU time	3.68 seconds
Started	May 23 12:37:32 PM PDT 24
Finished	May 23 12:37:38 PM PDT 24
Peak memory	203708 kb
Host	smart-1fd6819c-460d-4a61-b365-ba186cc92a22
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504754138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3504754138
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.4110868681
Short name	T826
Test name
Test status
Simulation time	2022547854 ps
CPU time	33.71 seconds
Started	May 23 12:37:30 PM PDT 24
Finished	May 23 12:38:05 PM PDT 24
Peak memory	204000 kb
Host	smart-2a443773-0197-4768-82cf-9815fda9efb9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4110868681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4110868681
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.2536356451
Short name	T572
Test name
Test status
Simulation time	118132895 ps
CPU time	2.23 seconds
Started	May 23 12:37:35 PM PDT 24
Finished	May 23 12:37:38 PM PDT 24
Peak memory	203248 kb
Host	smart-99b21599-fc36-4337-9b1f-d79658796728
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2536356451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2536356451
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1654419468
Short name	T325
Test name
Test status
Simulation time	30583926074 ps
CPU time	41.14 seconds
Started	May 23 12:37:34 PM PDT 24
Finished	May 23 12:38:16 PM PDT 24
Peak memory	203392 kb
Host	smart-e8b24e16-dab6-4e79-b939-28bef11b30a7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654419468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1654419468
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.464394328
Short name	T251
Test name
Test status
Simulation time	8296975908 ps
CPU time	28.28 seconds
Started	May 23 12:37:28 PM PDT 24
Finished	May 23 12:37:57 PM PDT 24
Peak memory	203260 kb
Host	smart-1371c5ce-bebe-4146-88e5-18f390e1fb3e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=464394328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.464394328
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1056152398
Short name	T247
Test name
Test status
Simulation time	44837625 ps
CPU time	2.47 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:37:48 PM PDT 24
Peak memory	203276 kb
Host	smart-3bd43a04-77a6-4bcd-b66e-86831f195300
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056152398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1056152398
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.1589242905
Short name	T763
Test name
Test status
Simulation time	221986538 ps
CPU time	24.37 seconds
Started	May 23 12:37:34 PM PDT 24
Finished	May 23 12:38:00 PM PDT 24
Peak memory	206156 kb
Host	smart-524c37b9-2214-4bed-b1e2-742e046143bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1589242905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1589242905
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2224160826
Short name	T496
Test name
Test status
Simulation time	6905745304 ps
CPU time	141.64 seconds
Started	May 23 12:37:41 PM PDT 24
Finished	May 23 12:40:03 PM PDT 24
Peak memory	206532 kb
Host	smart-0223e358-c1e5-4af2-ab32-948ff9c44e3a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2224160826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2224160826
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2440184901
Short name	T107
Test name
Test status
Simulation time	5287825890 ps
CPU time	189.84 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:40:57 PM PDT 24
Peak memory	210452 kb
Host	smart-6295ebc1-a4d7-4ec0-b90e-252039fd4223
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2440184901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.2440184901
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2891484397
Short name	T360
Test name
Test status
Simulation time	94997796 ps
CPU time	16.75 seconds
Started	May 23 12:37:39 PM PDT 24
Finished	May 23 12:37:57 PM PDT 24
Peak memory	204376 kb
Host	smart-afc3ca3a-bd59-40e6-9e77-2093863ac265
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2891484397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2891484397
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2105846995
Short name	T315
Test name
Test status
Simulation time	11584951 ps
CPU time	1.73 seconds
Started	May 23 12:37:32 PM PDT 24
Finished	May 23 12:37:35 PM PDT 24
Peak memory	203256 kb
Host	smart-573e48d5-47f7-4631-8c31-6676127d2d3b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2105846995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2105846995
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1716250812
Short name	T694
Test name
Test status
Simulation time	1331482827 ps
CPU time	24.24 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:38:11 PM PDT 24
Peak memory	211420 kb
Host	smart-cdff556f-7e82-4c60-834f-64a3e4123c37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1716250812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1716250812
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2054561979
Short name	T135
Test name
Test status
Simulation time	12378773147 ps
CPU time	62.59 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:38:49 PM PDT 24
Peak memory	204276 kb
Host	smart-2bac6310-ef2c-4e17-b3a8-61c8e7a6c015
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2054561979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2054561979
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2162663581
Short name	T305
Test name
Test status
Simulation time	2357104484 ps
CPU time	20.76 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:38:07 PM PDT 24
Peak memory	203364 kb
Host	smart-933bfdfc-3c3d-4c68-aee2-477f42878e1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2162663581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2162663581
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.1993565503
Short name	T310
Test name
Test status
Simulation time	66326438 ps
CPU time	6.61 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:37:53 PM PDT 24
Peak memory	203288 kb
Host	smart-f373897c-8525-4c6c-9b9e-94a8258d143d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1993565503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1993565503
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.3723018409
Short name	T394
Test name
Test status
Simulation time	179841056 ps
CPU time	11.52 seconds
Started	May 23 12:37:41 PM PDT 24
Finished	May 23 12:37:54 PM PDT 24
Peak memory	204640 kb
Host	smart-106b747a-57ed-4edd-82ad-a75c567b683c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3723018409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3723018409
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3465119870
Short name	T605
Test name
Test status
Simulation time	33689007746 ps
CPU time	153.5 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:40:19 PM PDT 24
Peak memory	204464 kb
Host	smart-cc5a72d7-f2fb-47a8-8c5d-fd611e02fad0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465119870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3465119870
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.568506902
Short name	T553
Test name
Test status
Simulation time	7447398083 ps
CPU time	35.87 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:38:22 PM PDT 24
Peak memory	204456 kb
Host	smart-202b1939-bef5-4bdd-b38c-2a09dd550a4c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=568506902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.568506902
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3134754073
Short name	T728
Test name
Test status
Simulation time	29860177 ps
CPU time	2.16 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:02 PM PDT 24
Peak memory	203512 kb
Host	smart-900d827d-daa8-4355-8cd6-e5bf298ea4c1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134754073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3134754073
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.4132035654
Short name	T458
Test name
Test status
Simulation time	344805822 ps
CPU time	7.03 seconds
Started	May 23 12:37:41 PM PDT 24
Finished	May 23 12:37:50 PM PDT 24
Peak memory	203308 kb
Host	smart-212707e4-f753-4be3-acb9-f6e4d463c971
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4132035654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4132035654
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.3469278609
Short name	T46
Test name
Test status
Simulation time	29089170 ps
CPU time	2.33 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:37:48 PM PDT 24
Peak memory	203236 kb
Host	smart-65c57073-8148-4092-8c46-865cdc434f69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3469278609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3469278609
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2729316522
Short name	T845
Test name
Test status
Simulation time	6202444691 ps
CPU time	26.93 seconds
Started	May 23 12:37:42 PM PDT 24
Finished	May 23 12:38:11 PM PDT 24
Peak memory	203320 kb
Host	smart-62d639b4-26a2-4b05-8e93-8a2ff38aa7a7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729316522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2729316522
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3880922832
Short name	T671
Test name
Test status
Simulation time	3161043979 ps
CPU time	21.73 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:22 PM PDT 24
Peak memory	203256 kb
Host	smart-16da30a9-cf46-4e96-94d3-33f103523342
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3880922832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3880922832
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2461220080
Short name	T322
Test name
Test status
Simulation time	39798936 ps
CPU time	2.27 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:37:49 PM PDT 24
Peak memory	203264 kb
Host	smart-54d26286-2125-48f2-bf18-9b03c61f4292
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461220080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2461220080
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.3068181021
Short name	T89
Test name
Test status
Simulation time	8703839203 ps
CPU time	133.53 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:40:01 PM PDT 24
Peak memory	206056 kb
Host	smart-e40554f5-30d9-42b3-81ae-da1180a4bb34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3068181021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3068181021
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3631184885
Short name	T871
Test name
Test status
Simulation time	757789729 ps
CPU time	78.99 seconds
Started	May 23 12:37:42 PM PDT 24
Finished	May 23 12:39:04 PM PDT 24
Peak memory	206892 kb
Host	smart-f7fe5c4e-9c68-4aae-bc88-0dde02ac957a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3631184885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3631184885
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1286039326
Short name	T682
Test name
Test status
Simulation time	1756805996 ps
CPU time	190.26 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:40:59 PM PDT 24
Peak memory	208644 kb
Host	smart-9513266d-3cab-4dcb-b7a2-83c9b23e5dd5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1286039326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1286039326
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1504449882
Short name	T412
Test name
Test status
Simulation time	4727773800 ps
CPU time	298.76 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:42:45 PM PDT 24
Peak memory	219768 kb
Host	smart-c26c6859-8139-42c1-a75e-a7e37169ad30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1504449882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1504449882
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2227490506
Short name	T856
Test name
Test status
Simulation time	1581629736 ps
CPU time	20.22 seconds
Started	May 23 12:37:41 PM PDT 24
Finished	May 23 12:38:03 PM PDT 24
Peak memory	211464 kb
Host	smart-d98f6582-1725-436f-a087-2b2cb34183f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2227490506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2227490506
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1117244389
Short name	T199
Test name
Test status
Simulation time	515277746 ps
CPU time	20.25 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:38:35 PM PDT 24
Peak memory	203912 kb
Host	smart-dabb3537-f853-4abe-8bd7-423da9bb46d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1117244389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1117244389
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1806615647
Short name	T158
Test name
Test status
Simulation time	23130818412 ps
CPU time	127.72 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:40:22 PM PDT 24
Peak memory	205908 kb
Host	smart-d6614374-319e-49e8-bb2a-c46fb552b14e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1806615647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1806615647
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3607186688
Short name	T4
Test name
Test status
Simulation time	27103902 ps
CPU time	3.54 seconds
Started	May 23 12:38:16 PM PDT 24
Finished	May 23 12:38:20 PM PDT 24
Peak memory	203440 kb
Host	smart-e5a9ce77-407c-4721-af6f-e594fe7d56d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3607186688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3607186688
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.2511485659
Short name	T417
Test name
Test status
Simulation time	1054216181 ps
CPU time	23.11 seconds
Started	May 23 12:38:16 PM PDT 24
Finished	May 23 12:38:40 PM PDT 24
Peak memory	203524 kb
Host	smart-11226b02-06d9-43a8-b700-57f5eb66db1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2511485659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2511485659
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.1772288990
Short name	T720
Test name
Test status
Simulation time	492290449 ps
CPU time	24.29 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:34 PM PDT 24
Peak memory	204840 kb
Host	smart-600895e1-ef33-4240-a7ab-3df73de95d30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1772288990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1772288990
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3779175761
Short name	T58
Test name
Test status
Simulation time	52689518235 ps
CPU time	201.02 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:41:35 PM PDT 24
Peak memory	204740 kb
Host	smart-9be02583-0dc5-4f79-8d91-b9db8bc800c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779175761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3779175761
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3539491458
Short name	T532
Test name
Test status
Simulation time	2247078116 ps
CPU time	12.02 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:25 PM PDT 24
Peak memory	203040 kb
Host	smart-68419024-f688-4224-9a11-3e0e0633e59c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3539491458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3539491458
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1763930350
Short name	T414
Test name
Test status
Simulation time	150105675 ps
CPU time	22.96 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:37 PM PDT 24
Peak memory	204856 kb
Host	smart-510c645c-c415-4e26-9942-f0e5feaa3805
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763930350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1763930350
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.374576338
Short name	T692
Test name
Test status
Simulation time	43530743 ps
CPU time	4.1 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:17 PM PDT 24
Peak memory	203448 kb
Host	smart-b17a1dc3-cafa-4bd3-b953-44a66b2f94dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=374576338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.374576338
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.2633383897
Short name	T882
Test name
Test status
Simulation time	204903630 ps
CPU time	3.63 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:38:18 PM PDT 24
Peak memory	203220 kb
Host	smart-3b6a3c51-79bb-4c25-b970-98dbb031ba82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2633383897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2633383897
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2252899195
Short name	T149
Test name
Test status
Simulation time	11852672381 ps
CPU time	31.9 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:46 PM PDT 24
Peak memory	203284 kb
Host	smart-40502236-8c8b-4a0a-8201-6f0aad7d447d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252899195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2252899195
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1114972388
Short name	T48
Test name
Test status
Simulation time	3419466362 ps
CPU time	27.55 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:41 PM PDT 24
Peak memory	203340 kb
Host	smart-e6f624af-b7d6-4ee6-8184-6b392c95affd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1114972388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1114972388
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2766330371
Short name	T338
Test name
Test status
Simulation time	40822421 ps
CPU time	2.09 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:17 PM PDT 24
Peak memory	203232 kb
Host	smart-a15977da-a43c-4b93-9f1a-54b318818858
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766330371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2766330371
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.3062257544
Short name	T617
Test name
Test status
Simulation time	2095365527 ps
CPU time	141.85 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:40:37 PM PDT 24
Peak memory	208832 kb
Host	smart-afd0df83-cc6d-43ac-a336-388a22a3adcc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3062257544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3062257544
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3736873991
Short name	T160
Test name
Test status
Simulation time	611285737 ps
CPU time	15.26 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:28 PM PDT 24
Peak memory	203340 kb
Host	smart-f06e53f9-4d8f-449d-b91d-fc39658cb4c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3736873991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3736873991
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2836049104
Short name	T167
Test name
Test status
Simulation time	1762980665 ps
CPU time	248.43 seconds
Started	May 23 12:38:16 PM PDT 24
Finished	May 23 12:42:26 PM PDT 24
Peak memory	211520 kb
Host	smart-eb2dadb1-56ad-4027-94e6-11cc797c2d74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2836049104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2836049104
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2290696089
Short name	T580
Test name
Test status
Simulation time	99173482 ps
CPU time	16.94 seconds
Started	May 23 12:38:14 PM PDT 24
Finished	May 23 12:38:33 PM PDT 24
Peak memory	205568 kb
Host	smart-3a4d357c-9a0d-4253-838b-28359eee860d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2290696089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2290696089
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.176075078
Short name	T451
Test name
Test status
Simulation time	534422252 ps
CPU time	12.61 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:25 PM PDT 24
Peak memory	211516 kb
Host	smart-e414ab72-51bd-4c8b-916b-b308ddf1b83f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=176075078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.176075078
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.931845191
Short name	T164
Test name
Test status
Simulation time	1004111110 ps
CPU time	32.18 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:38:56 PM PDT 24
Peak memory	211552 kb
Host	smart-ba556afb-d1d4-4047-bbbb-297998275fa3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931845191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.931845191
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1052975272
Short name	T221
Test name
Test status
Simulation time	6346424136 ps
CPU time	54.44 seconds
Started	May 23 12:38:25 PM PDT 24
Finished	May 23 12:39:21 PM PDT 24
Peak memory	211460 kb
Host	smart-04bf06ec-f7c9-439e-a8e0-2a7c364a0251
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1052975272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1052975272
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4172609983
Short name	T346
Test name
Test status
Simulation time	551618938 ps
CPU time	9.81 seconds
Started	May 23 12:38:25 PM PDT 24
Finished	May 23 12:38:36 PM PDT 24
Peak memory	203496 kb
Host	smart-d54fb2a4-eed0-4101-80fb-ee9e12cf45e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172609983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4172609983
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.1269783755
Short name	T438
Test name
Test status
Simulation time	187779618 ps
CPU time	16.41 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:38:42 PM PDT 24
Peak memory	203456 kb
Host	smart-56d6224c-6aa4-4363-8163-f094bc45aef3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1269783755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1269783755
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.4125969760
Short name	T628
Test name
Test status
Simulation time	2044375800 ps
CPU time	28.14 seconds
Started	May 23 12:38:14 PM PDT 24
Finished	May 23 12:38:44 PM PDT 24
Peak memory	204468 kb
Host	smart-56cefa9c-e5c9-4633-a457-192b9dcad54e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4125969760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.4125969760
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.228967352
Short name	T839
Test name
Test status
Simulation time	42480080237 ps
CPU time	150.56 seconds
Started	May 23 12:38:25 PM PDT 24
Finished	May 23 12:40:57 PM PDT 24
Peak memory	204740 kb
Host	smart-047ded76-2d20-4a8b-a2ba-b78ea59409a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=228967352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.228967352
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2828763587
Short name	T101
Test name
Test status
Simulation time	11327376999 ps
CPU time	76.99 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:39:40 PM PDT 24
Peak memory	211536 kb
Host	smart-5a0147ef-d837-4fd1-bc91-6f54931fa9af
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2828763587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2828763587
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.591708628
Short name	T625
Test name
Test status
Simulation time	289404707 ps
CPU time	24.14 seconds
Started	May 23 12:38:14 PM PDT 24
Finished	May 23 12:38:40 PM PDT 24
Peak memory	211564 kb
Host	smart-b838088e-7a9b-4ea3-a6ca-574d604a58df
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591708628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.591708628
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.4022771264
Short name	T564
Test name
Test status
Simulation time	167251039 ps
CPU time	13.28 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:38:42 PM PDT 24
Peak memory	204048 kb
Host	smart-0241e74f-f6fe-4d2a-b88b-0e9b336b2624
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4022771264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4022771264
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.2799119709
Short name	T230
Test name
Test status
Simulation time	135441983 ps
CPU time	4 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:38:19 PM PDT 24
Peak memory	203268 kb
Host	smart-4d72156c-c901-4b86-a580-4e38fd06d7da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2799119709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2799119709
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.441777803
Short name	T670
Test name
Test status
Simulation time	5098709198 ps
CPU time	30.04 seconds
Started	May 23 12:38:14 PM PDT 24
Finished	May 23 12:38:46 PM PDT 24
Peak memory	203420 kb
Host	smart-46cf0fd2-d850-46f7-afb1-fb1981acd87a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=441777803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.441777803
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.4076404633
Short name	T604
Test name
Test status
Simulation time	6310335831 ps
CPU time	33.04 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:47 PM PDT 24
Peak memory	203340 kb
Host	smart-5043af49-b5ea-4dfa-9022-98be1ae9c642
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4076404633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.4076404633
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.465850757
Short name	T818
Test name
Test status
Simulation time	26043195 ps
CPU time	2.25 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:38:14 PM PDT 24
Peak memory	203272 kb
Host	smart-79423e18-587a-49df-ac38-cbd15ddb2178
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465850757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.465850757
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.3141198148
Short name	T120
Test name
Test status
Simulation time	6962074655 ps
CPU time	126.4 seconds
Started	May 23 12:38:23 PM PDT 24
Finished	May 23 12:40:31 PM PDT 24
Peak memory	207768 kb
Host	smart-2bd67ceb-1aa5-4c9f-bdb7-6ba8718a9372
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3141198148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3141198148
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1994137062
Short name	T525
Test name
Test status
Simulation time	3801548325 ps
CPU time	92.37 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:39:58 PM PDT 24
Peak memory	207048 kb
Host	smart-50198b39-d38a-46bf-9af3-e166618a87ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1994137062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1994137062
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.4208748517
Short name	T455
Test name
Test status
Simulation time	121745139 ps
CPU time	44.41 seconds
Started	May 23 12:38:23 PM PDT 24
Finished	May 23 12:39:08 PM PDT 24
Peak memory	206724 kb
Host	smart-1ad974ef-1d3c-43b8-bf6b-c84d4979704b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4208748517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.4208748517
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3833451552
Short name	T426
Test name
Test status
Simulation time	73895303 ps
CPU time	7.8 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:38:31 PM PDT 24
Peak memory	205176 kb
Host	smart-ed0c4603-3285-4ebc-bc67-8bdc85fccf58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3833451552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.3833451552
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2334714436
Short name	T727
Test name
Test status
Simulation time	154089166 ps
CPU time	8.53 seconds
Started	May 23 12:38:25 PM PDT 24
Finished	May 23 12:38:34 PM PDT 24
Peak memory	204836 kb
Host	smart-307a1779-ae01-4ef2-9562-9f6a38cbf100
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334714436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2334714436
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2430347531
Short name	T541
Test name
Test status
Simulation time	16594926192 ps
CPU time	153.72 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:40:59 PM PDT 24
Peak memory	205296 kb
Host	smart-1eabee17-1336-4053-aab7-4c06ba7fa50b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2430347531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2430347531
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.989806509
Short name	T314
Test name
Test status
Simulation time	90998957 ps
CPU time	8.73 seconds
Started	May 23 12:38:23 PM PDT 24
Finished	May 23 12:38:33 PM PDT 24
Peak memory	203616 kb
Host	smart-67c76cde-79ea-4866-8f17-56af344dad8c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=989806509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.989806509
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.2857824311
Short name	T858
Test name
Test status
Simulation time	297991237 ps
CPU time	3.79 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:38:27 PM PDT 24
Peak memory	203256 kb
Host	smart-60cda889-1a7f-406e-9904-ba5ff9fdf0e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2857824311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2857824311
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.3479235297
Short name	T350
Test name
Test status
Simulation time	1316935103 ps
CPU time	32.34 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:38:57 PM PDT 24
Peak memory	204288 kb
Host	smart-b7c13a76-4317-43ff-abd8-a10befb13198
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3479235297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3479235297
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1091180711
Short name	T889
Test name
Test status
Simulation time	49573962936 ps
CPU time	241.91 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:42:27 PM PDT 24
Peak memory	205136 kb
Host	smart-6bc92bed-7631-4e5e-9228-dae6998b4b26
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091180711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1091180711
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2265948618
Short name	T461
Test name
Test status
Simulation time	2815272430 ps
CPU time	24.58 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	203356 kb
Host	smart-e2659288-981f-4ead-a0d4-8003e3e65a67
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2265948618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2265948618
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1391415221
Short name	T176
Test name
Test status
Simulation time	46491114 ps
CPU time	5.09 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:38:34 PM PDT 24
Peak memory	203840 kb
Host	smart-d0b321d4-46a6-4f75-97fe-b4bae6167fe9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391415221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1391415221
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.2962970437
Short name	T442
Test name
Test status
Simulation time	3084318980 ps
CPU time	35.88 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:39:02 PM PDT 24
Peak memory	204004 kb
Host	smart-9921ea2c-7f63-4bd4-a590-f37ab27f3ca3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2962970437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2962970437
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.3218183178
Short name	T143
Test name
Test status
Simulation time	147433930 ps
CPU time	3.11 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:38:31 PM PDT 24
Peak memory	203340 kb
Host	smart-5cdc6b9d-4d04-4c98-8419-88248b3a1fa6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3218183178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3218183178
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3538182095
Short name	T142
Test name
Test status
Simulation time	8108758482 ps
CPU time	29.63 seconds
Started	May 23 12:38:26 PM PDT 24
Finished	May 23 12:38:57 PM PDT 24
Peak memory	203292 kb
Host	smart-3a25ba99-61af-4e14-ae57-b6c58777e0cd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538182095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3538182095
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3761188108
Short name	T44
Test name
Test status
Simulation time	5355156941 ps
CPU time	22.06 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	203376 kb
Host	smart-a8a91e46-ca94-4052-9663-04ea9524e7e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3761188108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3761188108
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3652964451
Short name	T749
Test name
Test status
Simulation time	35663085 ps
CPU time	2.6 seconds
Started	May 23 12:38:26 PM PDT 24
Finished	May 23 12:38:29 PM PDT 24
Peak memory	203272 kb
Host	smart-675a4d9e-ce2b-43cc-95a7-ddaf977eb3c8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652964451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3652964451
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.3820674573
Short name	T421
Test name
Test status
Simulation time	63503490 ps
CPU time	9.22 seconds
Started	May 23 12:38:25 PM PDT 24
Finished	May 23 12:38:35 PM PDT 24
Peak memory	204916 kb
Host	smart-caa3e18e-8567-445e-a7c5-385aedd31e77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3820674573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3820674573
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.686957310
Short name	T194
Test name
Test status
Simulation time	2989630258 ps
CPU time	129.08 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:40:32 PM PDT 24
Peak memory	207480 kb
Host	smart-19133fe3-45a3-4733-ab56-9670f2171397
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686957310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.686957310
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2639379938
Short name	T398
Test name
Test status
Simulation time	166833849 ps
CPU time	109 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:40:12 PM PDT 24
Peak memory	208392 kb
Host	smart-816421be-1379-4895-926b-e7bb50960050
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639379938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.2639379938
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3911373818
Short name	T239
Test name
Test status
Simulation time	3720812045 ps
CPU time	246.74 seconds
Started	May 23 12:38:21 PM PDT 24
Finished	May 23 12:42:29 PM PDT 24
Peak memory	219848 kb
Host	smart-7df43371-54a7-4aa9-90a7-7c3933e48adf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3911373818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3911373818
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1636529362
Short name	T161
Test name
Test status
Simulation time	963416978 ps
CPU time	33.62 seconds
Started	May 23 12:38:26 PM PDT 24
Finished	May 23 12:39:01 PM PDT 24
Peak memory	204980 kb
Host	smart-7d3b39df-5a26-4dc8-a79e-fe3529f63374
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636529362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1636529362
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2590546888
Short name	T645
Test name
Test status
Simulation time	1349688467 ps
CPU time	31.35 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:39:00 PM PDT 24
Peak memory	206092 kb
Host	smart-155e2d51-490c-4394-9c95-6eb9463a29bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590546888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2590546888
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.212815305
Short name	T224
Test name
Test status
Simulation time	17164549988 ps
CPU time	74.63 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:39:44 PM PDT 24
Peak memory	205604 kb
Host	smart-104f1835-b748-4c9a-b2ce-62153d71f95c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=212815305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo w_rsp.212815305
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.273131862
Short name	T334
Test name
Test status
Simulation time	269440862 ps
CPU time	8.82 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:38:38 PM PDT 24
Peak memory	203784 kb
Host	smart-bb73781b-f1f9-4c2a-9dc8-c776942231eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=273131862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.273131862
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.2176723098
Short name	T479
Test name
Test status
Simulation time	1631635009 ps
CPU time	13.24 seconds
Started	May 23 12:38:25 PM PDT 24
Finished	May 23 12:38:39 PM PDT 24
Peak memory	203288 kb
Host	smart-ed0018ff-cb02-4903-b9a0-05b2ded2ea9d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2176723098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2176723098
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.3826946596
Short name	T157
Test name
Test status
Simulation time	156044675 ps
CPU time	4.61 seconds
Started	May 23 12:38:21 PM PDT 24
Finished	May 23 12:38:26 PM PDT 24
Peak memory	203388 kb
Host	smart-dff07d51-861c-4f4b-955f-36eb5f01fcff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3826946596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3826946596
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.813556071
Short name	T637
Test name
Test status
Simulation time	27324217493 ps
CPU time	80.69 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:39:49 PM PDT 24
Peak memory	211612 kb
Host	smart-aa65688b-357f-46bf-bad9-b961775b64fb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=813556071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.813556071
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.798780092
Short name	T841
Test name
Test status
Simulation time	32120056613 ps
CPU time	171.22 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:41:15 PM PDT 24
Peak memory	204920 kb
Host	smart-caade090-07d7-4c9f-99e6-7ab6a368cbab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=798780092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.798780092
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3274353290
Short name	T764
Test name
Test status
Simulation time	15253555 ps
CPU time	2.54 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:38:30 PM PDT 24
Peak memory	203240 kb
Host	smart-a668aab7-3e23-423a-bea1-97b5ccd5cab9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274353290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3274353290
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.1716654539
Short name	T385
Test name
Test status
Simulation time	126261098 ps
CPU time	3.81 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:38:32 PM PDT 24
Peak memory	203268 kb
Host	smart-726b559d-6ebf-40c9-920b-790b9de7c3f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1716654539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1716654539
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.1884706386
Short name	T357
Test name
Test status
Simulation time	204068338 ps
CPU time	4.11 seconds
Started	May 23 12:38:23 PM PDT 24
Finished	May 23 12:38:29 PM PDT 24
Peak memory	203248 kb
Host	smart-2497d9dd-b901-4dbc-965a-61da55f656ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1884706386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1884706386
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2928234196
Short name	T790
Test name
Test status
Simulation time	4378952302 ps
CPU time	27.38 seconds
Started	May 23 12:38:21 PM PDT 24
Finished	May 23 12:38:50 PM PDT 24
Peak memory	203328 kb
Host	smart-28ae0ab8-e066-4e69-bde8-019635bf6f2e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928234196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2928234196
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1916932939
Short name	T714
Test name
Test status
Simulation time	2971880221 ps
CPU time	23.91 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:38:49 PM PDT 24
Peak memory	203308 kb
Host	smart-6586bd22-edc2-45fe-bb7e-cff965a4d172
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1916932939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1916932939
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3893390234
Short name	T212
Test name
Test status
Simulation time	19913144 ps
CPU time	1.93 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:38:25 PM PDT 24
Peak memory	203252 kb
Host	smart-ad824bff-acf8-4807-a5ec-b2d508c5b078
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893390234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3893390234
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.3136914829
Short name	T88
Test name
Test status
Simulation time	18464321677 ps
CPU time	147.05 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:40:55 PM PDT 24
Peak memory	208664 kb
Host	smart-af6f1604-6190-414b-9486-c0a055607017
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3136914829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3136914829
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1196228651
Short name	T892
Test name
Test status
Simulation time	38282200417 ps
CPU time	315.71 seconds
Started	May 23 12:38:26 PM PDT 24
Finished	May 23 12:43:43 PM PDT 24
Peak memory	211472 kb
Host	smart-c24a5caa-c8bb-4fe9-be49-b15e1fdd6863
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1196228651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1196228651
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2983869204
Short name	T152
Test name
Test status
Simulation time	531857121 ps
CPU time	240.07 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:42:28 PM PDT 24
Peak memory	208212 kb
Host	smart-bf1473dc-92b0-4428-a454-02866e78d858
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2983869204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.2983869204
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3529716429
Short name	T498
Test name
Test status
Simulation time	4993941384 ps
CPU time	153.13 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:41:02 PM PDT 24
Peak memory	208404 kb
Host	smart-dec67236-0b74-4507-8f4b-636de18e4d3e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3529716429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.3529716429
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.73920875
Short name	T554
Test name
Test status
Simulation time	158699102 ps
CPU time	19.31 seconds
Started	May 23 12:38:28 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	211448 kb
Host	smart-711c6976-40d0-4114-b70b-d6250751643d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=73920875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.73920875
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1108451249
Short name	T410
Test name
Test status
Simulation time	160468190 ps
CPU time	12.3 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:38:40 PM PDT 24
Peak memory	204828 kb
Host	smart-acccd4a5-cc81-487e-8848-c49170bcc77e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1108451249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1108451249
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2213058325
Short name	T154
Test name
Test status
Simulation time	61644405155 ps
CPU time	160.03 seconds
Started	May 23 12:38:24 PM PDT 24
Finished	May 23 12:41:05 PM PDT 24
Peak memory	211508 kb
Host	smart-c867697b-5512-4969-b954-643e94f0b522
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2213058325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.2213058325
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2484122611
Short name	T848
Test name
Test status
Simulation time	98482342 ps
CPU time	2.08 seconds
Started	May 23 12:38:40 PM PDT 24
Finished	May 23 12:38:44 PM PDT 24
Peak memory	203268 kb
Host	smart-67d29a9e-af0c-4a86-af54-d14f17ec18bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2484122611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2484122611
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.2626996803
Short name	T582
Test name
Test status
Simulation time	221947267 ps
CPU time	18.03 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:39:00 PM PDT 24
Peak memory	203360 kb
Host	smart-4daef510-0d34-404e-994f-51fb0eabb43f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2626996803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2626996803
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.1945482101
Short name	T333
Test name
Test status
Simulation time	1040241156 ps
CPU time	11.66 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:38:39 PM PDT 24
Peak memory	204416 kb
Host	smart-a05c6552-1d45-4b24-891b-3771b4f93373
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1945482101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1945482101
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.245368561
Short name	T747
Test name
Test status
Simulation time	4820027685 ps
CPU time	25.97 seconds
Started	May 23 12:38:21 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	204120 kb
Host	smart-41794e71-d5fb-4f27-a5ad-667fcae27089
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=245368561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.245368561
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1388645598
Short name	T73
Test name
Test status
Simulation time	28528217515 ps
CPU time	176.33 seconds
Started	May 23 12:38:26 PM PDT 24
Finished	May 23 12:41:24 PM PDT 24
Peak memory	204672 kb
Host	smart-0dbc2779-e5c3-42fb-a368-f1e918488e57
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1388645598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1388645598
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2334556694
Short name	T210
Test name
Test status
Simulation time	415823414 ps
CPU time	17.26 seconds
Started	May 23 12:38:23 PM PDT 24
Finished	May 23 12:38:42 PM PDT 24
Peak memory	211468 kb
Host	smart-199e7ad8-a3c8-4663-9f31-9c356a2d1590
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334556694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2334556694
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.2328126011
Short name	T141
Test name
Test status
Simulation time	373263953 ps
CPU time	7.87 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:38:50 PM PDT 24
Peak memory	204060 kb
Host	smart-5d0472b5-8ea1-45df-8e24-4cc03616aba3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2328126011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2328126011
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.3206104890
Short name	T548
Test name
Test status
Simulation time	243161927 ps
CPU time	3.55 seconds
Started	May 23 12:38:22 PM PDT 24
Finished	May 23 12:38:27 PM PDT 24
Peak memory	203244 kb
Host	smart-46006ab4-3d0e-477f-a597-c0384b077192
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3206104890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3206104890
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3151026744
Short name	T515
Test name
Test status
Simulation time	4220174668 ps
CPU time	24.56 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:38:52 PM PDT 24
Peak memory	203384 kb
Host	smart-1d45f438-71e7-40ce-a85a-cf30a42b4909
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151026744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3151026744
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2689855772
Short name	T193
Test name
Test status
Simulation time	5357680336 ps
CPU time	35.54 seconds
Started	May 23 12:38:27 PM PDT 24
Finished	May 23 12:39:03 PM PDT 24
Peak memory	203292 kb
Host	smart-9c025844-699b-4511-9cc9-bbea62fe2ae2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2689855772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2689855772
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2158017249
Short name	T283
Test name
Test status
Simulation time	23781398 ps
CPU time	1.96 seconds
Started	May 23 12:38:26 PM PDT 24
Finished	May 23 12:38:29 PM PDT 24
Peak memory	203228 kb
Host	smart-524f3218-f8c4-481d-9c96-64c01d337d1e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158017249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2158017249
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.1379727980
Short name	T450
Test name
Test status
Simulation time	2152195998 ps
CPU time	53.5 seconds
Started	May 23 12:38:40 PM PDT 24
Finished	May 23 12:39:34 PM PDT 24
Peak memory	205864 kb
Host	smart-e328f43e-e575-4999-b5d5-5b475f31b2d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1379727980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1379727980
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.549532666
Short name	T861
Test name
Test status
Simulation time	6012839666 ps
CPU time	90.2 seconds
Started	May 23 12:38:40 PM PDT 24
Finished	May 23 12:40:11 PM PDT 24
Peak memory	205748 kb
Host	smart-5fbf54b6-c7bb-4c42-a443-63c811dfe056
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=549532666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.549532666
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3922551702
Short name	T336
Test name
Test status
Simulation time	12293509 ps
CPU time	12.69 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:38:57 PM PDT 24
Peak memory	205280 kb
Host	smart-4151dc04-582d-4c17-8acd-587b74e6e551
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3922551702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.3922551702
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.4100911126
Short name	T857
Test name
Test status
Simulation time	289982671 ps
CPU time	85.68 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:40:10 PM PDT 24
Peak memory	208580 kb
Host	smart-4451a9be-58ef-41c6-bcae-2087f402f57d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4100911126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.4100911126
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1790722276
Short name	T499
Test name
Test status
Simulation time	114333778 ps
CPU time	2.41 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:38:46 PM PDT 24
Peak memory	203264 kb
Host	smart-8a318bfb-a10f-42a6-b051-db6400393291
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1790722276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1790722276
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1351590469
Short name	T796
Test name
Test status
Simulation time	2825786825 ps
CPU time	45.85 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:39:29 PM PDT 24
Peak memory	205304 kb
Host	smart-60595d26-a274-444b-8db0-75139513c2fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1351590469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1351590469
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1919315005
Short name	T719
Test name
Test status
Simulation time	65363313779 ps
CPU time	488.16 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:46:53 PM PDT 24
Peak memory	205856 kb
Host	smart-665b63c4-e4b3-4f4e-955e-5a22b4a69fc6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1919315005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1919315005
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1614262078
Short name	T709
Test name
Test status
Simulation time	162427809 ps
CPU time	15.13 seconds
Started	May 23 12:38:40 PM PDT 24
Finished	May 23 12:38:56 PM PDT 24
Peak memory	203836 kb
Host	smart-21d3a62d-16c5-49b4-831b-ed5fe0736cc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1614262078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1614262078
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.3685953566
Short name	T534
Test name
Test status
Simulation time	3247564072 ps
CPU time	27.59 seconds
Started	May 23 12:38:40 PM PDT 24
Finished	May 23 12:39:08 PM PDT 24
Peak memory	203344 kb
Host	smart-9ce42957-673f-46c6-b5f9-d34d273f7c2c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3685953566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3685953566
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.4068377042
Short name	T200
Test name
Test status
Simulation time	394323479 ps
CPU time	21.22 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:39:03 PM PDT 24
Peak memory	211376 kb
Host	smart-603fd485-3e74-4eac-be6f-a3d90fd94bef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4068377042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4068377042
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.496328045
Short name	T741
Test name
Test status
Simulation time	263058542355 ps
CPU time	341.33 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:44:25 PM PDT 24
Peak memory	204740 kb
Host	smart-1655bfc3-4a2e-4253-ad0e-faa7e53f5aff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=496328045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.496328045
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.4218236936
Short name	T202
Test name
Test status
Simulation time	3384592135 ps
CPU time	31.92 seconds
Started	May 23 12:38:40 PM PDT 24
Finished	May 23 12:39:13 PM PDT 24
Peak memory	203952 kb
Host	smart-011a1104-51ae-4194-b8a8-04bd6498b3e4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4218236936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4218236936
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1520850475
Short name	T432
Test name
Test status
Simulation time	189930219 ps
CPU time	11.69 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:38:54 PM PDT 24
Peak memory	204532 kb
Host	smart-1b6f30de-1186-43bc-96fc-75d2fec4e6bf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520850475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1520850475
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.1183871088
Short name	T501
Test name
Test status
Simulation time	1098479979 ps
CPU time	23.28 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:39:06 PM PDT 24
Peak memory	203784 kb
Host	smart-8395ba92-b0ce-4329-9f05-dedb1cb9ec7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1183871088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1183871088
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.848678291
Short name	T435
Test name
Test status
Simulation time	212391019 ps
CPU time	3.59 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	203232 kb
Host	smart-ef4ab4a9-4074-4a5a-aec4-418e288df409
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=848678291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.848678291
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1514335777
Short name	T824
Test name
Test status
Simulation time	4361307104 ps
CPU time	24.45 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:39:06 PM PDT 24
Peak memory	203388 kb
Host	smart-87c8e99a-ab2c-4edd-9819-16832e263081
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514335777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1514335777
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.4054241959
Short name	T552
Test name
Test status
Simulation time	3353295476 ps
CPU time	29.34 seconds
Started	May 23 12:38:40 PM PDT 24
Finished	May 23 12:39:10 PM PDT 24
Peak memory	203268 kb
Host	smart-45929d81-58a4-469a-9e72-799488c073b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4054241959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4054241959
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3867590763
Short name	T779
Test name
Test status
Simulation time	39414935 ps
CPU time	2.21 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:38:46 PM PDT 24
Peak memory	203464 kb
Host	smart-b9cf7c0b-76fd-48d5-b014-4affc5f21067
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867590763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3867590763
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.857222387
Short name	T518
Test name
Test status
Simulation time	8026901929 ps
CPU time	155.02 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:41:19 PM PDT 24
Peak memory	208168 kb
Host	smart-13e29875-e729-4431-b69d-73f32bbc4c9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=857222387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.857222387
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3026300817
Short name	T608
Test name
Test status
Simulation time	9602933590 ps
CPU time	406.18 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:45:31 PM PDT 24
Peak memory	219728 kb
Host	smart-5a420c6c-1cd1-48c9-bb3e-9b780d5a5b60
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3026300817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3026300817
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.565747876
Short name	T187
Test name
Test status
Simulation time	641199110 ps
CPU time	24.75 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:39:09 PM PDT 24
Peak memory	205120 kb
Host	smart-9954a318-7b9f-4cb7-8248-769097faff25
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=565747876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.565747876
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1624668017
Short name	T830
Test name
Test status
Simulation time	58334520 ps
CPU time	3.39 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	203128 kb
Host	smart-22847500-347e-47f5-986e-b36cf015484c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1624668017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1624668017
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2705466565
Short name	T805
Test name
Test status
Simulation time	61478557453 ps
CPU time	354.36 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:44:39 PM PDT 24
Peak memory	211392 kb
Host	smart-0c446eb0-ef48-4c17-852d-f2752b480539
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2705466565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2705466565
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1184154688
Short name	T550
Test name
Test status
Simulation time	424516187 ps
CPU time	8.04 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:38:54 PM PDT 24
Peak memory	203280 kb
Host	smart-0f387d17-2a71-40c8-8b99-349cae6353d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1184154688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1184154688
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.1877123277
Short name	T198
Test name
Test status
Simulation time	1224864814 ps
CPU time	26.07 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:39:11 PM PDT 24
Peak memory	203372 kb
Host	smart-2779a36f-601d-42c7-bc53-8f9b8347cce4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1877123277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1877123277
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.4277913048
Short name	T112
Test name
Test status
Simulation time	1770080510 ps
CPU time	39.08 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:39:23 PM PDT 24
Peak memory	204544 kb
Host	smart-3b9665c7-be91-408c-8f69-d7ebd174a61b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4277913048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.4277913048
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2161855645
Short name	T600
Test name
Test status
Simulation time	52678188462 ps
CPU time	189.24 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:41:54 PM PDT 24
Peak memory	204648 kb
Host	smart-0446b542-9558-4c32-92a3-33cfc32a8b49
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161855645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2161855645
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3685236932
Short name	T717
Test name
Test status
Simulation time	3354696982 ps
CPU time	15.87 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:39:01 PM PDT 24
Peak memory	203852 kb
Host	smart-fa682630-2cd3-4717-9a52-44a02fcc02fd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3685236932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3685236932
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.767555257
Short name	T363
Test name
Test status
Simulation time	243429061 ps
CPU time	22.62 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:39:07 PM PDT 24
Peak memory	204324 kb
Host	smart-35d49d06-6880-4828-ab56-c0899e2e78ef
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767555257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.767555257
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.438140927
Short name	T539
Test name
Test status
Simulation time	1271222489 ps
CPU time	15.46 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:39:01 PM PDT 24
Peak memory	203292 kb
Host	smart-9d8db5a0-dcc9-435e-a7d1-3fd915eb56cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=438140927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.438140927
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.1402498078
Short name	T306
Test name
Test status
Simulation time	187301309 ps
CPU time	3.45 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	203256 kb
Host	smart-5a79edd1-eedc-43f6-bca7-e4c287314116
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1402498078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1402498078
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.523121178
Short name	T318
Test name
Test status
Simulation time	35453102878 ps
CPU time	42.37 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:39:26 PM PDT 24
Peak memory	203300 kb
Host	smart-393bd3bc-4e27-4558-a11b-bcc51388cd4b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=523121178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.523121178
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2852649747
Short name	T213
Test name
Test status
Simulation time	3856761554 ps
CPU time	27.15 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:39:11 PM PDT 24
Peak memory	203336 kb
Host	smart-267eb63f-cec8-4e81-ad3a-e2a17b28726f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2852649747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2852649747
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1007432932
Short name	T767
Test name
Test status
Simulation time	39860352 ps
CPU time	1.75 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:38:47 PM PDT 24
Peak memory	203268 kb
Host	smart-4659c477-4ac7-4308-bf47-7a83fe8367a8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007432932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1007432932
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.2220119927
Short name	T781
Test name
Test status
Simulation time	1154394636 ps
CPU time	140.88 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:41:06 PM PDT 24
Peak memory	205712 kb
Host	smart-f7c87a0b-efe4-4360-8ecb-75b6113791ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2220119927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2220119927
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2258024280
Short name	T775
Test name
Test status
Simulation time	3285426957 ps
CPU time	92.89 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:40:17 PM PDT 24
Peak memory	206492 kb
Host	smart-5bd8963b-32ba-40cb-bfd8-73edcba234c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2258024280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2258024280
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3012787949
Short name	T619
Test name
Test status
Simulation time	397093674 ps
CPU time	165.49 seconds
Started	May 23 12:38:44 PM PDT 24
Finished	May 23 12:41:32 PM PDT 24
Peak memory	208756 kb
Host	smart-008c9aa4-058a-47bb-89de-c120f0e4a548
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3012787949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3012787949
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.549477619
Short name	T38
Test name
Test status
Simulation time	10260183686 ps
CPU time	333.77 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:44:18 PM PDT 24
Peak memory	219672 kb
Host	smart-4b701646-d74b-4342-a161-ea932f5f7c43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=549477619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res et_error.549477619
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1261067221
Short name	T788
Test name
Test status
Simulation time	185707863 ps
CPU time	22.37 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:39:08 PM PDT 24
Peak memory	211440 kb
Host	smart-67f0ca4d-cde7-4b56-99f1-bafd18cdb90b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1261067221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1261067221
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2317499744
Short name	T128
Test name
Test status
Simulation time	318525436 ps
CPU time	20.42 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:39:07 PM PDT 24
Peak memory	204592 kb
Host	smart-54cd49b7-f1e0-4f92-9889-0b7e078d84f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2317499744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2317499744
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1468832450
Short name	T287
Test name
Test status
Simulation time	73315973195 ps
CPU time	274.02 seconds
Started	May 23 12:38:44 PM PDT 24
Finished	May 23 12:43:20 PM PDT 24
Peak memory	205852 kb
Host	smart-e5685304-a411-405f-95cf-b2d2279224fe
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1468832450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1468832450
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2995575918
Short name	T99
Test name
Test status
Simulation time	68084390 ps
CPU time	7.89 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:38:55 PM PDT 24
Peak memory	203700 kb
Host	smart-c2081d2f-1406-47de-b07e-77c9f33507e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2995575918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2995575918
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.3982147146
Short name	T832
Test name
Test status
Simulation time	57344993 ps
CPU time	7.6 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:38:55 PM PDT 24
Peak memory	203064 kb
Host	smart-62db440b-766e-4904-a152-2e258f7da93a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3982147146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3982147146
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.2740943563
Short name	T70
Test name
Test status
Simulation time	507978054 ps
CPU time	17.11 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:39:04 PM PDT 24
Peak memory	211460 kb
Host	smart-186f1233-0574-4b1d-8a84-4bf6d0ea433f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2740943563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2740943563
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.854835829
Short name	T874
Test name
Test status
Simulation time	299127302127 ps
CPU time	368.76 seconds
Started	May 23 12:38:46 PM PDT 24
Finished	May 23 12:44:56 PM PDT 24
Peak memory	205508 kb
Host	smart-6f9a74a4-3977-441d-ab9f-24f6976930eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=854835829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.854835829
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3192239408
Short name	T188
Test name
Test status
Simulation time	23250294515 ps
CPU time	88.37 seconds
Started	May 23 12:38:46 PM PDT 24
Finished	May 23 12:40:16 PM PDT 24
Peak memory	204684 kb
Host	smart-eb08bed4-6858-4798-acf6-0706af620de8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3192239408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3192239408
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2928883836
Short name	T374
Test name
Test status
Simulation time	144389259 ps
CPU time	21.62 seconds
Started	May 23 12:38:44 PM PDT 24
Finished	May 23 12:39:07 PM PDT 24
Peak memory	204356 kb
Host	smart-2f6e49d3-276a-4e3e-8d08-2aa0058d2ede
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928883836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2928883836
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.256697561
Short name	T395
Test name
Test status
Simulation time	1529524682 ps
CPU time	28.73 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:39:14 PM PDT 24
Peak memory	203260 kb
Host	smart-bb77dd97-2d22-4eac-b09c-9daf42e741fe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=256697561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.256697561
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.4177101677
Short name	T307
Test name
Test status
Simulation time	231837392 ps
CPU time	3.21 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:38:45 PM PDT 24
Peak memory	203240 kb
Host	smart-848b19df-67be-4ee4-999f-f23153b1e928
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4177101677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.4177101677
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.741760122
Short name	T559
Test name
Test status
Simulation time	6553620862 ps
CPU time	31.41 seconds
Started	May 23 12:38:41 PM PDT 24
Finished	May 23 12:39:14 PM PDT 24
Peak memory	203328 kb
Host	smart-5066ab2e-cb84-40c7-bb66-7d54b11ea331
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=741760122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.741760122
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1450345006
Short name	T290
Test name
Test status
Simulation time	7386422736 ps
CPU time	33.09 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:39:20 PM PDT 24
Peak memory	203344 kb
Host	smart-d38815d2-bede-4b5f-b4fa-92bb9d607be0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1450345006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1450345006
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1379845462
Short name	T565
Test name
Test status
Simulation time	115998456 ps
CPU time	1.98 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:38:47 PM PDT 24
Peak memory	203220 kb
Host	smart-07da3981-a853-48ff-90dd-a256a5c2de5a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379845462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1379845462
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.1144767725
Short name	T162
Test name
Test status
Simulation time	4990005946 ps
CPU time	169.96 seconds
Started	May 23 12:38:46 PM PDT 24
Finished	May 23 12:41:37 PM PDT 24
Peak memory	207224 kb
Host	smart-772de580-c63e-4771-9bb8-9039c19ebe11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1144767725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1144767725
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.695605822
Short name	T829
Test name
Test status
Simulation time	4757355687 ps
CPU time	94.67 seconds
Started	May 23 12:38:44 PM PDT 24
Finished	May 23 12:40:21 PM PDT 24
Peak memory	205212 kb
Host	smart-35d24b04-0cf3-4245-a4a8-8fe9705112a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695605822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.695605822
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.108176022
Short name	T232
Test name
Test status
Simulation time	15609921303 ps
CPU time	398.8 seconds
Started	May 23 12:38:44 PM PDT 24
Finished	May 23 12:45:25 PM PDT 24
Peak memory	225520 kb
Host	smart-cdaa3b03-a848-4809-bd95-71926506c3d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=108176022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.108176022
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1698914787
Short name	T208
Test name
Test status
Simulation time	1133671243 ps
CPU time	14 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:39:01 PM PDT 24
Peak memory	211444 kb
Host	smart-47ea7c0c-cdcb-4242-bdc0-890dede6fb9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1698914787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1698914787
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2409644139
Short name	T288
Test name
Test status
Simulation time	176308973 ps
CPU time	4.59 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:38:59 PM PDT 24
Peak memory	203344 kb
Host	smart-220fd127-ff46-432b-a157-2e0d5d2a9ba1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2409644139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2409644139
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2412482422
Short name	T382
Test name
Test status
Simulation time	43113074522 ps
CPU time	354.46 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:44:50 PM PDT 24
Peak memory	206760 kb
Host	smart-19509141-833d-4536-81ae-fa815bbb3a77
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2412482422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.2412482422
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.618469144
Short name	T504
Test name
Test status
Simulation time	1218821426 ps
CPU time	28.89 seconds
Started	May 23 12:38:52 PM PDT 24
Finished	May 23 12:39:21 PM PDT 24
Peak memory	204000 kb
Host	smart-ac942a3e-a9a1-4fcf-ad1f-1b5446f7eb5f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=618469144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.618469144
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.3881054442
Short name	T669
Test name
Test status
Simulation time	194263939 ps
CPU time	16.77 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:11 PM PDT 24
Peak memory	203220 kb
Host	smart-48fecd45-1253-4bb8-adb7-3798e652adca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3881054442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3881054442
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.3850124113
Short name	T530
Test name
Test status
Simulation time	53423068 ps
CPU time	5.08 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:00 PM PDT 24
Peak memory	204344 kb
Host	smart-f92b2dcc-0865-4c9a-b604-d9aa6c2a51a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3850124113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3850124113
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2180823964
Short name	T197
Test name
Test status
Simulation time	31975944516 ps
CPU time	163.14 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:41:40 PM PDT 24
Peak memory	211504 kb
Host	smart-1e3d5bf5-619c-4f3f-a915-61bcea2467fd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180823964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2180823964
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.294325264
Short name	T794
Test name
Test status
Simulation time	24508930413 ps
CPU time	219.76 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:42:36 PM PDT 24
Peak memory	211496 kb
Host	smart-385d8f22-adfd-430c-b926-6d5c228269f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=294325264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.294325264
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.192087416
Short name	T349
Test name
Test status
Simulation time	44303987 ps
CPU time	5.32 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:39:01 PM PDT 24
Peak memory	204292 kb
Host	smart-6f41e2a9-edab-4e72-bf4d-503e525c3dc1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192087416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.192087416
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.845510725
Short name	T542
Test name
Test status
Simulation time	189996071 ps
CPU time	9.61 seconds
Started	May 23 12:38:57 PM PDT 24
Finished	May 23 12:39:08 PM PDT 24
Peak memory	203868 kb
Host	smart-7f980ea2-1ace-4290-8476-16b9a6df9ab4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=845510725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.845510725
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.2337412632
Short name	T423
Test name
Test status
Simulation time	73513061 ps
CPU time	2.11 seconds
Started	May 23 12:38:45 PM PDT 24
Finished	May 23 12:38:49 PM PDT 24
Peak memory	203268 kb
Host	smart-7e8b3ea3-02a5-4020-9d7f-addea4e51fac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2337412632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2337412632
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.507918988
Short name	T407
Test name
Test status
Simulation time	9217157676 ps
CPU time	31.34 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:39:15 PM PDT 24
Peak memory	203296 kb
Host	smart-2d65d80c-b52f-4595-96e9-e94100f73e20
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=507918988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.507918988
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.850783487
Short name	T761
Test name
Test status
Simulation time	9838188797 ps
CPU time	29.17 seconds
Started	May 23 12:38:43 PM PDT 24
Finished	May 23 12:39:14 PM PDT 24
Peak memory	203320 kb
Host	smart-5e0c3035-aa55-47c1-9773-ed32e408aef0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=850783487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.850783487
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.937554961
Short name	T377
Test name
Test status
Simulation time	34519211 ps
CPU time	2.11 seconds
Started	May 23 12:38:42 PM PDT 24
Finished	May 23 12:38:47 PM PDT 24
Peak memory	203328 kb
Host	smart-3a112e8f-0001-4b4e-83d9-7d5d91fc1509
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937554961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.937554961
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.644400043
Short name	T2
Test name
Test status
Simulation time	2956085946 ps
CPU time	59.56 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:54 PM PDT 24
Peak memory	204840 kb
Host	smart-60658a3b-4df0-418b-a4bb-12fd6897aaf1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=644400043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.644400043
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.795356223
Short name	T521
Test name
Test status
Simulation time	20799396105 ps
CPU time	264.59 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:43:21 PM PDT 24
Peak memory	209500 kb
Host	smart-404e26fa-4a5a-4f56-a244-8fa58371dcd4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=795356223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.795356223
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.4208092305
Short name	T104
Test name
Test status
Simulation time	2469908750 ps
CPU time	177.99 seconds
Started	May 23 12:38:52 PM PDT 24
Finished	May 23 12:41:50 PM PDT 24
Peak memory	208224 kb
Host	smart-ab6d998c-9a0d-46c5-93c7-0946b1b0435c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4208092305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.4208092305
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3162728920
Short name	T721
Test name
Test status
Simulation time	350006096 ps
CPU time	81.96 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:40:16 PM PDT 24
Peak memory	209416 kb
Host	smart-458e7c91-8df1-449f-870e-c11b027d7271
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3162728920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.3162728920
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1197882606
Short name	T640
Test name
Test status
Simulation time	879837779 ps
CPU time	20.48 seconds
Started	May 23 12:38:57 PM PDT 24
Finished	May 23 12:39:19 PM PDT 24
Peak memory	211532 kb
Host	smart-7ea4152c-704e-446e-b8ac-38c7f5ed0151
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1197882606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1197882606
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.97674520
Short name	T437
Test name
Test status
Simulation time	4564651596 ps
CPU time	43.75 seconds
Started	May 23 12:38:56 PM PDT 24
Finished	May 23 12:39:41 PM PDT 24
Peak memory	205292 kb
Host	smart-7f0e1433-601c-47b3-bff3-6a07ad8367e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=97674520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.97674520
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1952736203
Short name	T90
Test name
Test status
Simulation time	151344489972 ps
CPU time	602.69 seconds
Started	May 23 12:38:52 PM PDT 24
Finished	May 23 12:48:56 PM PDT 24
Peak memory	207268 kb
Host	smart-8e2712a4-6a4b-47c2-85b7-76d565434ae1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1952736203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1952736203
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.524563983
Short name	T387
Test name
Test status
Simulation time	4460401034 ps
CPU time	30.86 seconds
Started	May 23 12:38:56 PM PDT 24
Finished	May 23 12:39:28 PM PDT 24
Peak memory	203772 kb
Host	smart-c02c1f6b-9ff9-4e8e-a30c-6fb756d59c09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=524563983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.524563983
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.2568172298
Short name	T569
Test name
Test status
Simulation time	67767276 ps
CPU time	7.58 seconds
Started	May 23 12:39:00 PM PDT 24
Finished	May 23 12:39:09 PM PDT 24
Peak memory	203264 kb
Host	smart-86a6bd83-b98d-47d8-a173-8c72bbc0a2b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2568172298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2568172298
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.668244575
Short name	T838
Test name
Test status
Simulation time	862731919 ps
CPU time	25.34 seconds
Started	May 23 12:38:51 PM PDT 24
Finished	May 23 12:39:17 PM PDT 24
Peak memory	204584 kb
Host	smart-9beec342-b137-4b8f-bceb-beab4423850d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=668244575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.668244575
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2373645057
Short name	T797
Test name
Test status
Simulation time	11234871014 ps
CPU time	67.46 seconds
Started	May 23 12:38:57 PM PDT 24
Finished	May 23 12:40:06 PM PDT 24
Peak memory	204608 kb
Host	smart-57351655-3320-4a4f-8695-3faddad61dac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373645057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2373645057
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.23586165
Short name	T702
Test name
Test status
Simulation time	28925285630 ps
CPU time	134.35 seconds
Started	May 23 12:39:04 PM PDT 24
Finished	May 23 12:41:20 PM PDT 24
Peak memory	205124 kb
Host	smart-1e4aeea9-6970-40d5-8131-e752eaa30938
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=23586165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.23586165
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3756770052
Short name	T246
Test name
Test status
Simulation time	120485248 ps
CPU time	13.43 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:39:10 PM PDT 24
Peak memory	211468 kb
Host	smart-830aa89b-136d-4548-a912-d703a5bf5256
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756770052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3756770052
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.2665538957
Short name	T612
Test name
Test status
Simulation time	2907914173 ps
CPU time	27.13 seconds
Started	May 23 12:38:57 PM PDT 24
Finished	May 23 12:39:25 PM PDT 24
Peak memory	203436 kb
Host	smart-ef3ea198-a201-4134-bd17-11025a0dd53a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2665538957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2665538957
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.2133994060
Short name	T463
Test name
Test status
Simulation time	391817535 ps
CPU time	3.88 seconds
Started	May 23 12:38:51 PM PDT 24
Finished	May 23 12:38:55 PM PDT 24
Peak memory	203380 kb
Host	smart-209bf10c-1643-4480-9fdf-4e4a70e75415
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2133994060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2133994060
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2674252022
Short name	T646
Test name
Test status
Simulation time	5411930118 ps
CPU time	28.49 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:23 PM PDT 24
Peak memory	203268 kb
Host	smart-dc3a0621-5d78-4c17-9d93-7718c522f586
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674252022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2674252022
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.4058025152
Short name	T557
Test name
Test status
Simulation time	4218573535 ps
CPU time	27.76 seconds
Started	May 23 12:38:52 PM PDT 24
Finished	May 23 12:39:21 PM PDT 24
Peak memory	203348 kb
Host	smart-e85ad4ac-f981-418c-a75f-f3f4aad89b5a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4058025152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.4058025152
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.27078178
Short name	T807
Test name
Test status
Simulation time	40487433 ps
CPU time	2.11 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:38:59 PM PDT 24
Peak memory	203152 kb
Host	smart-1578afc7-607d-4238-b6f3-8f58ff04a27d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27078178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.27078178
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.741444151
Short name	T370
Test name
Test status
Simulation time	192267229 ps
CPU time	32.17 seconds
Started	May 23 12:38:56 PM PDT 24
Finished	May 23 12:39:29 PM PDT 24
Peak memory	205524 kb
Host	smart-4c1b2f96-c3b3-4155-a1d3-c9891450f3a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=741444151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.741444151
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2087041970
Short name	T755
Test name
Test status
Simulation time	6775164884 ps
CPU time	75.83 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:40:12 PM PDT 24
Peak memory	205292 kb
Host	smart-4608f2df-1503-40a3-825e-c79096ba181c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2087041970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2087041970
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.238701276
Short name	T238
Test name
Test status
Simulation time	85388269 ps
CPU time	38.2 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:33 PM PDT 24
Peak memory	206504 kb
Host	smart-d46286f3-b547-4680-816b-cc5e5203bb01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=238701276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand _reset.238701276
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3764319155
Short name	T524
Test name
Test status
Simulation time	274146692 ps
CPU time	49.62 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:44 PM PDT 24
Peak memory	206688 kb
Host	smart-e5d3d72f-ac6a-427a-bd6a-942052129be8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3764319155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3764319155
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.1522515118
Short name	T579
Test name
Test status
Simulation time	931365837 ps
CPU time	30.46 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:25 PM PDT 24
Peak memory	211448 kb
Host	smart-b6816844-952e-4675-8e8d-9932a6b59006
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1522515118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1522515118
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2092790038
Short name	T121
Test name
Test status
Simulation time	1009184361 ps
CPU time	26.06 seconds
Started	May 23 12:37:47 PM PDT 24
Finished	May 23 12:38:15 PM PDT 24
Peak memory	204056 kb
Host	smart-46238a9e-d1b3-49a0-84e8-aa746d849bc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2092790038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2092790038
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.618860467
Short name	T231
Test name
Test status
Simulation time	46464669192 ps
CPU time	260.87 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:42:09 PM PDT 24
Peak memory	205960 kb
Host	smart-4cd82a77-b980-4bba-b279-7dcb08b9ebe9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=618860467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow _rsp.618860467
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.516564023
Short name	T853
Test name
Test status
Simulation time	275121277 ps
CPU time	13.15 seconds
Started	May 23 12:37:41 PM PDT 24
Finished	May 23 12:37:56 PM PDT 24
Peak memory	203684 kb
Host	smart-4bf456fc-5e5e-4be0-9afe-9ac4be309b55
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=516564023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.516564023
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.417823314
Short name	T894
Test name
Test status
Simulation time	55922638 ps
CPU time	6.83 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:07 PM PDT 24
Peak memory	202384 kb
Host	smart-104b4bc3-953a-4f24-b1f9-a4bcd09172dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=417823314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.417823314
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.3815455530
Short name	T687
Test name
Test status
Simulation time	546524410 ps
CPU time	13.93 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:38:02 PM PDT 24
Peak memory	211392 kb
Host	smart-03bae048-f838-4ae8-a7dc-3eb2bc2c313c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3815455530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3815455530
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1443647013
Short name	T43
Test name
Test status
Simulation time	42459190732 ps
CPU time	108.22 seconds
Started	May 23 12:37:47 PM PDT 24
Finished	May 23 12:39:37 PM PDT 24
Peak memory	204452 kb
Host	smart-99b57b94-2bf7-43b3-87ce-a97ec4a0d24a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443647013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1443647013
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3662768582
Short name	T376
Test name
Test status
Simulation time	11572967780 ps
CPU time	109.26 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:39:34 PM PDT 24
Peak memory	204452 kb
Host	smart-bb3401f9-20ce-4f79-9c5a-21f84f65c8df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3662768582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3662768582
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1661795675
Short name	T173
Test name
Test status
Simulation time	103690185 ps
CPU time	8.38 seconds
Started	May 23 12:37:40 PM PDT 24
Finished	May 23 12:37:49 PM PDT 24
Peak memory	204424 kb
Host	smart-55e056ef-899b-47dd-989f-6041236bd34b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661795675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1661795675
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.2618274992
Short name	T300
Test name
Test status
Simulation time	1112301433 ps
CPU time	22.97 seconds
Started	May 23 12:37:42 PM PDT 24
Finished	May 23 12:38:07 PM PDT 24
Peak memory	203964 kb
Host	smart-2b17d229-5807-4d25-8025-bae9902ced72
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2618274992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2618274992
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.3357348294
Short name	T734
Test name
Test status
Simulation time	828902688 ps
CPU time	3.74 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:37:51 PM PDT 24
Peak memory	203268 kb
Host	smart-7be9e424-b6b4-4ad3-b14c-428a2f706edd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3357348294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3357348294
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3989295359
Short name	T547
Test name
Test status
Simulation time	4093144235 ps
CPU time	24.42 seconds
Started	May 23 12:37:42 PM PDT 24
Finished	May 23 12:38:09 PM PDT 24
Peak memory	203304 kb
Host	smart-fac29182-5661-4e9f-b3b6-37924cbb7acc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989295359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3989295359
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.904390533
Short name	T54
Test name
Test status
Simulation time	27791542732 ps
CPU time	55.47 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:38:42 PM PDT 24
Peak memory	203316 kb
Host	smart-fa8d0aaa-f071-47f6-90fe-f9a388afbace
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=904390533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.904390533
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3206707020
Short name	T309
Test name
Test status
Simulation time	88112721 ps
CPU time	2.4 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:02 PM PDT 24
Peak memory	202616 kb
Host	smart-02784d11-4f81-4767-96d7-1189a1dbaf19
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206707020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3206707020
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.2183268087
Short name	T462
Test name
Test status
Simulation time	193564552 ps
CPU time	20.8 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:38:08 PM PDT 24
Peak memory	211472 kb
Host	smart-75bedd35-6ca1-4de5-9a60-62828d20756c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2183268087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2183268087
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1122153159
Short name	T750
Test name
Test status
Simulation time	121224500 ps
CPU time	8.92 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:37:54 PM PDT 24
Peak memory	203340 kb
Host	smart-f09c9f2f-edb8-413f-93c1-4f24a879880b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1122153159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1122153159
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3907183339
Short name	T710
Test name
Test status
Simulation time	576574193 ps
CPU time	119.12 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:39:45 PM PDT 24
Peak memory	208604 kb
Host	smart-4dcda5f2-b677-4f9d-89dd-7b2912fc6767
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3907183339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3907183339
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2747707924
Short name	T147
Test name
Test status
Simulation time	625950473 ps
CPU time	16.56 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:38:04 PM PDT 24
Peak memory	204576 kb
Host	smart-6386fc20-9619-457b-b7b6-934a68dfb9e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2747707924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2747707924
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3253070117
Short name	T358
Test name
Test status
Simulation time	2810999254 ps
CPU time	63.04 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:39:59 PM PDT 24
Peak memory	206460 kb
Host	smart-d8460780-5063-4717-beea-4b0b037ad92c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253070117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3253070117
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.489600574
Short name	T223
Test name
Test status
Simulation time	6542335754 ps
CPU time	36.44 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:31 PM PDT 24
Peak memory	203808 kb
Host	smart-15a3057a-53c7-45da-8add-cef5c0214b66
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=489600574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.489600574
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.4263165097
Short name	T378
Test name
Test status
Simulation time	264346696 ps
CPU time	18.38 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:39:15 PM PDT 24
Peak memory	204296 kb
Host	smart-7dd7213b-15a7-4b08-8918-9a441b43ff82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4263165097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.4263165097
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.3462120629
Short name	T746
Test name
Test status
Simulation time	104345634 ps
CPU time	10.39 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:39:06 PM PDT 24
Peak memory	203296 kb
Host	smart-60e2bea5-f32b-436f-82c9-1053e65ae349
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462120629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3462120629
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.722820944
Short name	T584
Test name
Test status
Simulation time	2485258454 ps
CPU time	16.31 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:39:11 PM PDT 24
Peak memory	204456 kb
Host	smart-0945c69f-fa66-41f2-9f9d-30fe8ac51c81
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=722820944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.722820944
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.435080131
Short name	T119
Test name
Test status
Simulation time	38224159499 ps
CPU time	158.34 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	204476 kb
Host	smart-d3725c43-7235-4ed5-8ea6-2c9bf2a41106
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=435080131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.435080131
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2776338347
Short name	T784
Test name
Test status
Simulation time	90974498299 ps
CPU time	226.67 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:42:41 PM PDT 24
Peak memory	204896 kb
Host	smart-45f67b3a-4b5c-4db5-ade0-dfafc1e6e1bf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2776338347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2776338347
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3168630976
Short name	T606
Test name
Test status
Simulation time	231581799 ps
CPU time	23.63 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:17 PM PDT 24
Peak memory	204484 kb
Host	smart-44a6a7fe-cb18-4256-a7ea-def5c4eee424
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168630976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3168630976
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.3460878339
Short name	T650
Test name
Test status
Simulation time	126960541 ps
CPU time	11.05 seconds
Started	May 23 12:38:53 PM PDT 24
Finished	May 23 12:39:06 PM PDT 24
Peak memory	203304 kb
Host	smart-e96d1ce1-838e-4033-890d-bdcc3753f9da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3460878339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3460878339
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.3147101988
Short name	T9
Test name
Test status
Simulation time	196932004 ps
CPU time	3.82 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:39:00 PM PDT 24
Peak memory	203232 kb
Host	smart-635fe1e4-3d2d-4894-85ae-aee280be2126
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3147101988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3147101988
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1296138545
Short name	T574
Test name
Test status
Simulation time	8790975231 ps
CPU time	35.59 seconds
Started	May 23 12:38:54 PM PDT 24
Finished	May 23 12:39:31 PM PDT 24
Peak memory	203340 kb
Host	smart-9ffd1c4f-5861-4c98-b591-7f2d168cec89
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296138545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1296138545
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1399687147
Short name	T798
Test name
Test status
Simulation time	3926086947 ps
CPU time	24.12 seconds
Started	May 23 12:38:52 PM PDT 24
Finished	May 23 12:39:17 PM PDT 24
Peak memory	203344 kb
Host	smart-36746c67-658d-4b4a-8e70-d79519b3ac0e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1399687147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1399687147
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3530052400
Short name	T396
Test name
Test status
Simulation time	39594149 ps
CPU time	2.7 seconds
Started	May 23 12:38:52 PM PDT 24
Finished	May 23 12:38:56 PM PDT 24
Peak memory	203284 kb
Host	smart-c445bba1-e99a-4b3a-8733-1e35e47af5a5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530052400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3530052400
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.1714074371
Short name	T316
Test name
Test status
Simulation time	18403133139 ps
CPU time	254.02 seconds
Started	May 23 12:38:57 PM PDT 24
Finished	May 23 12:43:12 PM PDT 24
Peak memory	210608 kb
Host	smart-c1caed2c-de9f-4e3a-b23e-ac55cd8cde48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1714074371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1714074371
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.169580383
Short name	T520
Test name
Test status
Simulation time	5286024256 ps
CPU time	143.14 seconds
Started	May 23 12:38:59 PM PDT 24
Finished	May 23 12:41:24 PM PDT 24
Peak memory	211488 kb
Host	smart-4a50741c-bfb1-488a-97d9-6eb4ed60e3af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=169580383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.169580383
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1124418345
Short name	T78
Test name
Test status
Simulation time	5179958931 ps
CPU time	201.51 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:42:18 PM PDT 24
Peak memory	209336 kb
Host	smart-fe85a091-43d6-4e2a-b036-f665161b17bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1124418345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1124418345
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.4225416314
Short name	T514
Test name
Test status
Simulation time	1151262523 ps
CPU time	180.69 seconds
Started	May 23 12:38:58 PM PDT 24
Finished	May 23 12:42:00 PM PDT 24
Peak memory	211460 kb
Host	smart-c7240a41-211c-4523-906b-396ab4f58860
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4225416314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.4225416314
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3631865803
Short name	T770
Test name
Test status
Simulation time	1329693840 ps
CPU time	24.97 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:39:22 PM PDT 24
Peak memory	204816 kb
Host	smart-b9445670-2371-4081-860a-6d3d3f9eb98d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3631865803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3631865803
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.358889693
Short name	T712
Test name
Test status
Simulation time	196629660 ps
CPU time	24.64 seconds
Started	May 23 12:39:05 PM PDT 24
Finished	May 23 12:39:31 PM PDT 24
Peak memory	205856 kb
Host	smart-5894d233-d569-46fd-8b3b-b7041dca8558
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=358889693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.358889693
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2349363389
Short name	T399
Test name
Test status
Simulation time	58237186313 ps
CPU time	489.05 seconds
Started	May 23 12:39:08 PM PDT 24
Finished	May 23 12:47:20 PM PDT 24
Peak memory	205884 kb
Host	smart-75782648-5455-45ec-b95f-0ecb9ed8944d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2349363389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.2349363389
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3018618718
Short name	T17
Test name
Test status
Simulation time	503493860 ps
CPU time	11.91 seconds
Started	May 23 12:39:07 PM PDT 24
Finished	May 23 12:39:21 PM PDT 24
Peak memory	203452 kb
Host	smart-0f36dbe7-c536-484e-b310-e83567f8fc59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3018618718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3018618718
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.2101848374
Short name	T389
Test name
Test status
Simulation time	2074232447 ps
CPU time	35.85 seconds
Started	May 23 12:39:07 PM PDT 24
Finished	May 23 12:39:45 PM PDT 24
Peak memory	203360 kb
Host	smart-017b5c44-9494-4d31-8c6a-6d0551987f78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2101848374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2101848374
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.2416431628
Short name	T701
Test name
Test status
Simulation time	886431254 ps
CPU time	20.98 seconds
Started	May 23 12:39:09 PM PDT 24
Finished	May 23 12:39:33 PM PDT 24
Peak memory	204420 kb
Host	smart-c5011895-83fc-45a7-aadd-796a352addfa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2416431628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2416431628
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.727570421
Short name	T613
Test name
Test status
Simulation time	19535020416 ps
CPU time	86.52 seconds
Started	May 23 12:39:09 PM PDT 24
Finished	May 23 12:40:39 PM PDT 24
Peak memory	204856 kb
Host	smart-97af0e7c-0177-4409-9a71-4b6bc4ba5aad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=727570421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.727570421
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3337230310
Short name	T397
Test name
Test status
Simulation time	25489697116 ps
CPU time	89.26 seconds
Started	May 23 12:39:09 PM PDT 24
Finished	May 23 12:40:41 PM PDT 24
Peak memory	211556 kb
Host	smart-7d889133-c620-4be4-b0d4-483ac0c4a75d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3337230310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3337230310
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2680298956
Short name	T275
Test name
Test status
Simulation time	734303421 ps
CPU time	24.38 seconds
Started	May 23 12:39:07 PM PDT 24
Finished	May 23 12:39:33 PM PDT 24
Peak memory	204360 kb
Host	smart-6d6cb660-a86f-44b7-bd09-55f3f47c2ee8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680298956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2680298956
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.2427311065
Short name	T722
Test name
Test status
Simulation time	1275849687 ps
CPU time	25.89 seconds
Started	May 23 12:39:06 PM PDT 24
Finished	May 23 12:39:34 PM PDT 24
Peak memory	203296 kb
Host	smart-206dce58-40c1-49a6-b1f0-ac82be8540d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2427311065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2427311065
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.262385417
Short name	T495
Test name
Test status
Simulation time	36053758 ps
CPU time	2.3 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:38:59 PM PDT 24
Peak memory	203380 kb
Host	smart-a1c79c33-dd05-44af-bc37-59ee40c5d686
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=262385417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.262385417
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3495317979
Short name	T873
Test name
Test status
Simulation time	4865379693 ps
CPU time	27.37 seconds
Started	May 23 12:38:58 PM PDT 24
Finished	May 23 12:39:26 PM PDT 24
Peak memory	203328 kb
Host	smart-ec943853-7a0e-4eb5-8997-0149ca5d0d13
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495317979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3495317979
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3303586057
Short name	T8
Test name
Test status
Simulation time	11584220260 ps
CPU time	36.12 seconds
Started	May 23 12:39:07 PM PDT 24
Finished	May 23 12:39:46 PM PDT 24
Peak memory	203336 kb
Host	smart-82f95a1c-b02e-40ec-8a6e-c0b1f2c213ef
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3303586057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3303586057
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3696355361
Short name	T56
Test name
Test status
Simulation time	29983529 ps
CPU time	2.18 seconds
Started	May 23 12:38:55 PM PDT 24
Finished	May 23 12:38:59 PM PDT 24
Peak memory	203392 kb
Host	smart-647fc735-ea93-4a18-91a7-d6d226021b5f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696355361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3696355361
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2602514391
Short name	T626
Test name
Test status
Simulation time	1916995497 ps
CPU time	44.76 seconds
Started	May 23 12:39:09 PM PDT 24
Finished	May 23 12:39:57 PM PDT 24
Peak memory	204464 kb
Host	smart-bb6465ff-95ed-4f34-89d9-29f2098fe21e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2602514391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2602514391
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.127978544
Short name	T519
Test name
Test status
Simulation time	182989516 ps
CPU time	47.29 seconds
Started	May 23 12:39:11 PM PDT 24
Finished	May 23 12:40:00 PM PDT 24
Peak memory	206632 kb
Host	smart-679fb0a4-05ee-4dc7-a7db-46695b5108b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=127978544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand _reset.127978544
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3972384832
Short name	T235
Test name
Test status
Simulation time	691820491 ps
CPU time	194.87 seconds
Started	May 23 12:39:18 PM PDT 24
Finished	May 23 12:42:33 PM PDT 24
Peak memory	219592 kb
Host	smart-7f0ab122-e950-46ce-b8c5-55a92ba53f22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3972384832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3972384832
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.627232955
Short name	T493
Test name
Test status
Simulation time	17251338 ps
CPU time	1.79 seconds
Started	May 23 12:39:07 PM PDT 24
Finished	May 23 12:39:11 PM PDT 24
Peak memory	203236 kb
Host	smart-69e63a76-8d65-40fe-b240-4bc307d69333
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=627232955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.627232955
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.410324833
Short name	T347
Test name
Test status
Simulation time	90986784 ps
CPU time	2.51 seconds
Started	May 23 12:39:08 PM PDT 24
Finished	May 23 12:39:13 PM PDT 24
Peak memory	203212 kb
Host	smart-ddc2fc25-7753-4db0-958d-5fa8c02601f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=410324833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.410324833
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3237239016
Short name	T339
Test name
Test status
Simulation time	26440035420 ps
CPU time	187.59 seconds
Started	May 23 12:39:06 PM PDT 24
Finished	May 23 12:42:15 PM PDT 24
Peak memory	205084 kb
Host	smart-9ee48a95-b98a-4716-80ae-c668123056a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3237239016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.3237239016
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2080756419
Short name	T834
Test name
Test status
Simulation time	144056626 ps
CPU time	14.04 seconds
Started	May 23 12:39:07 PM PDT 24
Finished	May 23 12:39:23 PM PDT 24
Peak memory	203276 kb
Host	smart-fa3c7da5-bd2c-4762-804a-00f10c577377
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2080756419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2080756419
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.433509949
Short name	T900
Test name
Test status
Simulation time	21219346 ps
CPU time	3.05 seconds
Started	May 23 12:39:11 PM PDT 24
Finished	May 23 12:39:16 PM PDT 24
Peak memory	203376 kb
Host	smart-c0d1d877-14fb-47d5-aafa-6aba96701335
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=433509949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.433509949
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.3119082283
Short name	T126
Test name
Test status
Simulation time	2810326241 ps
CPU time	30.52 seconds
Started	May 23 12:39:15 PM PDT 24
Finished	May 23 12:39:46 PM PDT 24
Peak memory	204720 kb
Host	smart-6b2af43c-e4e0-459a-8805-67e31620004f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3119082283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3119082283
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3151351552
Short name	T337
Test name
Test status
Simulation time	40262991234 ps
CPU time	84.66 seconds
Started	May 23 12:39:11 PM PDT 24
Finished	May 23 12:40:38 PM PDT 24
Peak memory	211624 kb
Host	smart-220cc63b-b497-4f7a-8ea9-9201037fdcd4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151351552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3151351552
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1572906252
Short name	T105
Test name
Test status
Simulation time	163831632806 ps
CPU time	299.49 seconds
Started	May 23 12:39:08 PM PDT 24
Finished	May 23 12:44:09 PM PDT 24
Peak memory	211444 kb
Host	smart-8512fce3-184c-44de-8e8a-1b8ed9a56c55
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1572906252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1572906252
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2700350755
Short name	T470
Test name
Test status
Simulation time	754137115 ps
CPU time	20.42 seconds
Started	May 23 12:39:08 PM PDT 24
Finished	May 23 12:39:31 PM PDT 24
Peak memory	204372 kb
Host	smart-2b6951c6-5e95-470b-a84b-cd46a596e8c8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700350755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2700350755
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.1484652715
Short name	T836
Test name
Test status
Simulation time	338958074 ps
CPU time	6.69 seconds
Started	May 23 12:39:15 PM PDT 24
Finished	May 23 12:39:23 PM PDT 24
Peak memory	203664 kb
Host	smart-37826b44-7532-4e0a-ab2c-ac378beef9a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1484652715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1484652715
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.3672495532
Short name	T289
Test name
Test status
Simulation time	116275549 ps
CPU time	3.2 seconds
Started	May 23 12:39:09 PM PDT 24
Finished	May 23 12:39:15 PM PDT 24
Peak memory	203336 kb
Host	smart-22f05f66-a6e1-4bc6-ba2d-d4eea839d114
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3672495532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3672495532
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2847801605
Short name	T813
Test name
Test status
Simulation time	7762950172 ps
CPU time	32.07 seconds
Started	May 23 12:39:03 PM PDT 24
Finished	May 23 12:39:37 PM PDT 24
Peak memory	203280 kb
Host	smart-aedb43b3-ac64-47ed-a7d2-8406d28a7cfa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847801605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2847801605
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.277591303
Short name	T795
Test name
Test status
Simulation time	3969130881 ps
CPU time	22.94 seconds
Started	May 23 12:39:06 PM PDT 24
Finished	May 23 12:39:31 PM PDT 24
Peak memory	203324 kb
Host	smart-a82eac93-3553-4bc8-a1fd-4ef91627f20d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=277591303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.277591303
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1726899047
Short name	T899
Test name
Test status
Simulation time	51799836 ps
CPU time	2.45 seconds
Started	May 23 12:39:08 PM PDT 24
Finished	May 23 12:39:13 PM PDT 24
Peak memory	203192 kb
Host	smart-a05ff126-7d35-482b-ac52-abb16809991e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726899047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1726899047
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.546146953
Short name	T63
Test name
Test status
Simulation time	9067383616 ps
CPU time	200.3 seconds
Started	May 23 12:39:08 PM PDT 24
Finished	May 23 12:42:31 PM PDT 24
Peak memory	209212 kb
Host	smart-7a841b98-b0ed-423f-a05c-06b4cb06d33a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=546146953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.546146953
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3297642569
Short name	T31
Test name
Test status
Simulation time	704147038 ps
CPU time	84.54 seconds
Started	May 23 12:39:10 PM PDT 24
Finished	May 23 12:40:37 PM PDT 24
Peak memory	207208 kb
Host	smart-fbb9487f-0d42-4e46-ae6f-20ca566caf90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3297642569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3297642569
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.285999137
Short name	T110
Test name
Test status
Simulation time	6543856645 ps
CPU time	470.43 seconds
Started	May 23 12:39:12 PM PDT 24
Finished	May 23 12:47:04 PM PDT 24
Peak memory	219728 kb
Host	smart-56e55bef-c0f7-4a36-9f29-5b69854c2e8e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285999137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand _reset.285999137
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.808464809
Short name	T30
Test name
Test status
Simulation time	2904858330 ps
CPU time	429.09 seconds
Started	May 23 12:39:11 PM PDT 24
Finished	May 23 12:46:22 PM PDT 24
Peak memory	224400 kb
Host	smart-90d4eec7-3d7b-426f-8ea3-112bfa4120ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808464809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res et_error.808464809
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1097331997
Short name	T852
Test name
Test status
Simulation time	564546673 ps
CPU time	22.17 seconds
Started	May 23 12:39:09 PM PDT 24
Finished	May 23 12:39:34 PM PDT 24
Peak memory	204812 kb
Host	smart-5bbebc00-0b30-4b01-a46f-5603a0bbaeb4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097331997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1097331997
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.674165875
Short name	T76
Test name
Test status
Simulation time	985407156 ps
CPU time	30.15 seconds
Started	May 23 12:39:21 PM PDT 24
Finished	May 23 12:39:53 PM PDT 24
Peak memory	204384 kb
Host	smart-692bf91f-9f56-4304-b0d9-9de9a60a0ead
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=674165875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.674165875
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3720203357
Short name	T851
Test name
Test status
Simulation time	168063975374 ps
CPU time	388.91 seconds
Started	May 23 12:39:21 PM PDT 24
Finished	May 23 12:45:52 PM PDT 24
Peak memory	206640 kb
Host	smart-9ce8b6bd-4e84-4a92-b096-99ba782d0492
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3720203357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.3720203357
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1653975805
Short name	T485
Test name
Test status
Simulation time	109048335 ps
CPU time	4.59 seconds
Started	May 23 12:39:25 PM PDT 24
Finished	May 23 12:39:31 PM PDT 24
Peak memory	203252 kb
Host	smart-b97698eb-82bc-4007-91e5-7e3563460387
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1653975805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1653975805
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.3295266181
Short name	T293
Test name
Test status
Simulation time	101988257 ps
CPU time	7.94 seconds
Started	May 23 12:39:22 PM PDT 24
Finished	May 23 12:39:32 PM PDT 24
Peak memory	203340 kb
Host	smart-6c9e4c85-2948-479a-b3bf-840520da7202
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3295266181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3295266181
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.670063824
Short name	T787
Test name
Test status
Simulation time	1676204126 ps
CPU time	20.11 seconds
Started	May 23 12:39:18 PM PDT 24
Finished	May 23 12:39:39 PM PDT 24
Peak memory	204244 kb
Host	smart-c7ff3962-23fd-418b-ba41-5742fa4c7bd0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=670063824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.670063824
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2626663942
Short name	T365
Test name
Test status
Simulation time	121009220839 ps
CPU time	146.69 seconds
Started	May 23 12:39:22 PM PDT 24
Finished	May 23 12:41:50 PM PDT 24
Peak memory	204788 kb
Host	smart-e16d12f0-ca83-4f7c-94e8-b4ffba79f762
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626663942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2626663942
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3235661368
Short name	T299
Test name
Test status
Simulation time	2820028412 ps
CPU time	22.76 seconds
Started	May 23 12:39:19 PM PDT 24
Finished	May 23 12:39:42 PM PDT 24
Peak memory	203520 kb
Host	smart-92b68d27-4d78-4dda-b629-60e52472cdcb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3235661368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3235661368
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.472638970
Short name	T560
Test name
Test status
Simulation time	186823267 ps
CPU time	18.92 seconds
Started	May 23 12:39:20 PM PDT 24
Finished	May 23 12:39:40 PM PDT 24
Peak memory	211468 kb
Host	smart-7d988f30-9df8-43aa-94b7-2b5221fa467c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472638970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.472638970
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.603973614
Short name	T353
Test name
Test status
Simulation time	389454527 ps
CPU time	8.06 seconds
Started	May 23 12:39:22 PM PDT 24
Finished	May 23 12:39:32 PM PDT 24
Peak memory	203800 kb
Host	smart-0b672da5-2991-4dd4-9eaa-fa9d2e15b7b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=603973614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.603973614
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.423160644
Short name	T494
Test name
Test status
Simulation time	945088646 ps
CPU time	4.32 seconds
Started	May 23 12:39:10 PM PDT 24
Finished	May 23 12:39:17 PM PDT 24
Peak memory	203380 kb
Host	smart-68445609-cba4-40f2-9351-a90fdc65a817
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=423160644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.423160644
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4046085841
Short name	T888
Test name
Test status
Simulation time	8128006478 ps
CPU time	28.37 seconds
Started	May 23 12:39:25 PM PDT 24
Finished	May 23 12:39:55 PM PDT 24
Peak memory	203320 kb
Host	smart-b4db166a-3fa5-4085-869a-d3506e4a0515
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046085841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4046085841
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2229862085
Short name	T563
Test name
Test status
Simulation time	5883268651 ps
CPU time	30.5 seconds
Started	May 23 12:39:23 PM PDT 24
Finished	May 23 12:39:55 PM PDT 24
Peak memory	203284 kb
Host	smart-428aafa1-85a1-4af6-bf23-04646eb95cfc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2229862085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2229862085
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3613721088
Short name	T297
Test name
Test status
Simulation time	25832499 ps
CPU time	1.99 seconds
Started	May 23 12:39:20 PM PDT 24
Finished	May 23 12:39:24 PM PDT 24
Peak memory	203224 kb
Host	smart-8f7a5c8d-614b-4e48-a0e2-b293dc57979a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613721088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3613721088
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.3199121814
Short name	T118
Test name
Test status
Simulation time	42814188853 ps
CPU time	265.37 seconds
Started	May 23 12:39:21 PM PDT 24
Finished	May 23 12:43:48 PM PDT 24
Peak memory	211628 kb
Host	smart-5caf1286-97f6-4329-bc73-9d9ad2e29764
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3199121814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3199121814
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1605118734
Short name	T842
Test name
Test status
Simulation time	2981455043 ps
CPU time	83 seconds
Started	May 23 12:39:20 PM PDT 24
Finished	May 23 12:40:44 PM PDT 24
Peak memory	206780 kb
Host	smart-5302f4fc-d491-4c67-b91d-532e2935b142
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1605118734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1605118734
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2669160590
Short name	T789
Test name
Test status
Simulation time	2094797841 ps
CPU time	231.53 seconds
Started	May 23 12:39:20 PM PDT 24
Finished	May 23 12:43:14 PM PDT 24
Peak memory	211440 kb
Host	smart-ce715f96-bf3a-4aba-9979-5528268a55bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2669160590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.2669160590
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.900944128
Short name	T236
Test name
Test status
Simulation time	2533114597 ps
CPU time	133.19 seconds
Started	May 23 12:39:21 PM PDT 24
Finished	May 23 12:41:36 PM PDT 24
Peak memory	209172 kb
Host	smart-428af9eb-e458-4673-b2a7-17608a26dc97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=900944128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.900944128
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3048070402
Short name	T381
Test name
Test status
Simulation time	309641128 ps
CPU time	14.43 seconds
Started	May 23 12:39:22 PM PDT 24
Finished	May 23 12:39:39 PM PDT 24
Peak memory	204860 kb
Host	smart-c52d7ec8-eb4e-47df-b69b-48b9a0c66a85
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3048070402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3048070402
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.4280674286
Short name	T466
Test name
Test status
Simulation time	220563115 ps
CPU time	6.06 seconds
Started	May 23 12:39:22 PM PDT 24
Finished	May 23 12:39:30 PM PDT 24
Peak memory	203416 kb
Host	smart-0d8aee29-13f9-43bf-8c2b-32ae6b5fb6dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4280674286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.4280674286
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.504245598
Short name	T179
Test name
Test status
Simulation time	30550165812 ps
CPU time	117.53 seconds
Started	May 23 12:39:25 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	206056 kb
Host	smart-dccc1438-0cfa-408e-a09a-6a7a89bea363
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=504245598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.504245598
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3333618309
Short name	T660
Test name
Test status
Simulation time	226542244 ps
CPU time	21.66 seconds
Started	May 23 12:39:33 PM PDT 24
Finished	May 23 12:39:57 PM PDT 24
Peak memory	203928 kb
Host	smart-1a568c48-67dc-4322-84c1-4ec99e003190
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333618309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3333618309
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.1228714217
Short name	T351
Test name
Test status
Simulation time	663564378 ps
CPU time	24.22 seconds
Started	May 23 12:39:26 PM PDT 24
Finished	May 23 12:39:52 PM PDT 24
Peak memory	203384 kb
Host	smart-26698783-acb6-492e-8982-5b817787bbcc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228714217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1228714217
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.319249470
Short name	T810
Test name
Test status
Simulation time	223715568 ps
CPU time	6.06 seconds
Started	May 23 12:39:23 PM PDT 24
Finished	May 23 12:39:31 PM PDT 24
Peak memory	204108 kb
Host	smart-f222acca-1a92-4847-8636-86044a24afd1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=319249470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.319249470
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1394513517
Short name	T591
Test name
Test status
Simulation time	66273354497 ps
CPU time	193.56 seconds
Started	May 23 12:39:20 PM PDT 24
Finished	May 23 12:42:35 PM PDT 24
Peak memory	211620 kb
Host	smart-1fd7cd55-abe6-4ce2-a6e7-3c3fc5b939d0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394513517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1394513517
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3080092887
Short name	T568
Test name
Test status
Simulation time	7757682980 ps
CPU time	74.87 seconds
Started	May 23 12:39:21 PM PDT 24
Finished	May 23 12:40:37 PM PDT 24
Peak memory	211576 kb
Host	smart-cda73266-1aab-4611-b6c5-029731ef8680
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3080092887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3080092887
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2544973059
Short name	T754
Test name
Test status
Simulation time	94770592 ps
CPU time	11.84 seconds
Started	May 23 12:39:19 PM PDT 24
Finished	May 23 12:39:32 PM PDT 24
Peak memory	204360 kb
Host	smart-9cf7be95-31a8-479f-b057-927ded88a169
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544973059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2544973059
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.726990049
Short name	T642
Test name
Test status
Simulation time	1463125345 ps
CPU time	33.07 seconds
Started	May 23 12:39:26 PM PDT 24
Finished	May 23 12:40:00 PM PDT 24
Peak memory	204012 kb
Host	smart-f88a2e6e-4c74-4cd1-87b6-497870ba8f0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726990049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.726990049
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.2213162677
Short name	T540
Test name
Test status
Simulation time	25963110 ps
CPU time	2.28 seconds
Started	May 23 12:39:27 PM PDT 24
Finished	May 23 12:39:30 PM PDT 24
Peak memory	203356 kb
Host	smart-80ef99c5-db93-4c00-a14c-693783b1f593
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2213162677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2213162677
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3770695908
Short name	T596
Test name
Test status
Simulation time	28874625517 ps
CPU time	47.01 seconds
Started	May 23 12:39:23 PM PDT 24
Finished	May 23 12:40:12 PM PDT 24
Peak memory	203284 kb
Host	smart-d2abc737-f449-4bfb-8c48-115c6c49cda2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770695908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3770695908
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.266061162
Short name	T561
Test name
Test status
Simulation time	6283951032 ps
CPU time	25.87 seconds
Started	May 23 12:39:22 PM PDT 24
Finished	May 23 12:39:50 PM PDT 24
Peak memory	203452 kb
Host	smart-9df0ae87-af5a-47b7-bae4-61aa7f99f267
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=266061162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.266061162
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3041368313
Short name	T713
Test name
Test status
Simulation time	43503902 ps
CPU time	2.26 seconds
Started	May 23 12:39:19 PM PDT 24
Finished	May 23 12:39:23 PM PDT 24
Peak memory	203280 kb
Host	smart-172f3a3c-e8b5-4005-b4bb-ca71e1220969
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041368313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3041368313
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.1600937372
Short name	T91
Test name
Test status
Simulation time	113767681 ps
CPU time	13.99 seconds
Started	May 23 12:39:33 PM PDT 24
Finished	May 23 12:39:48 PM PDT 24
Peak memory	211584 kb
Host	smart-48de1274-6b01-4e8a-841f-de803365d609
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1600937372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1600937372
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2508971941
Short name	T369
Test name
Test status
Simulation time	3423725507 ps
CPU time	57.14 seconds
Started	May 23 12:39:34 PM PDT 24
Finished	May 23 12:40:33 PM PDT 24
Peak memory	204804 kb
Host	smart-eebc52b4-bda9-4136-b5d0-94cc557bf701
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2508971941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2508971941
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.4014149885
Short name	T226
Test name
Test status
Simulation time	4354984401 ps
CPU time	284.76 seconds
Started	May 23 12:39:34 PM PDT 24
Finished	May 23 12:44:20 PM PDT 24
Peak memory	209744 kb
Host	smart-0ad78151-ef00-4059-b5fe-8488d9276493
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4014149885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.4014149885
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3505092144
Short name	T536
Test name
Test status
Simulation time	11762726518 ps
CPU time	266.05 seconds
Started	May 23 12:39:31 PM PDT 24
Finished	May 23 12:43:59 PM PDT 24
Peak memory	209768 kb
Host	smart-0e5fcf71-9607-42c2-bb27-5eb9a2e400bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3505092144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3505092144
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1142969196
Short name	T673
Test name
Test status
Simulation time	321829003 ps
CPU time	16.24 seconds
Started	May 23 12:39:43 PM PDT 24
Finished	May 23 12:40:00 PM PDT 24
Peak memory	204824 kb
Host	smart-1700d13a-6239-44d6-80db-ab03b29f91b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1142969196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1142969196
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3213826073
Short name	T425
Test name
Test status
Simulation time	4652448566 ps
CPU time	65.62 seconds
Started	May 23 12:39:34 PM PDT 24
Finished	May 23 12:40:42 PM PDT 24
Peak memory	206740 kb
Host	smart-58a09473-31bb-4169-9106-d8b8240cb1dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3213826073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3213826073
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3891225715
Short name	T177
Test name
Test status
Simulation time	30517097816 ps
CPU time	195.51 seconds
Started	May 23 12:39:34 PM PDT 24
Finished	May 23 12:42:51 PM PDT 24
Peak memory	204808 kb
Host	smart-f12f2bc7-0886-42fa-b840-ce23a3c8951d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3891225715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.3891225715
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.651477673
Short name	T898
Test name
Test status
Simulation time	3733072040 ps
CPU time	24.65 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:39:58 PM PDT 24
Peak memory	203516 kb
Host	smart-476bf79a-db30-4f21-83d9-8ba8088eccf2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=651477673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.651477673
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.2019039364
Short name	T526
Test name
Test status
Simulation time	300973305 ps
CPU time	17.61 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:39:51 PM PDT 24
Peak memory	203356 kb
Host	smart-462c470d-a084-4517-bd56-ab4f631a86b7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2019039364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2019039364
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.3613999246
Short name	T57
Test name
Test status
Simulation time	1816562551 ps
CPU time	35.05 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:40:09 PM PDT 24
Peak memory	204316 kb
Host	smart-7abe0898-353e-41af-a593-68fcb50183c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3613999246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3613999246
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3213135657
Short name	T825
Test name
Test status
Simulation time	32392579519 ps
CPU time	93.96 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:41:07 PM PDT 24
Peak memory	204856 kb
Host	smart-ba3937a0-fbea-47d0-9404-6e6fb07a1407
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213135657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3213135657
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.189385654
Short name	T601
Test name
Test status
Simulation time	10167201284 ps
CPU time	99.67 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:41:14 PM PDT 24
Peak memory	204784 kb
Host	smart-6b4d96a6-c0f3-4153-8207-9cfc73261b03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=189385654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.189385654
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1894696770
Short name	T379
Test name
Test status
Simulation time	40844322 ps
CPU time	6 seconds
Started	May 23 12:39:33 PM PDT 24
Finished	May 23 12:39:41 PM PDT 24
Peak memory	211408 kb
Host	smart-9f5e3805-7fba-4690-b228-1d9e368a7716
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894696770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1894696770
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.317514919
Short name	T388
Test name
Test status
Simulation time	144420095 ps
CPU time	9.22 seconds
Started	May 23 12:39:36 PM PDT 24
Finished	May 23 12:39:48 PM PDT 24
Peak memory	203796 kb
Host	smart-97ff579b-f13d-48b0-b63d-1b40e8f5d2dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317514919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.317514919
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.3198116601
Short name	T211
Test name
Test status
Simulation time	415403589 ps
CPU time	3.79 seconds
Started	May 23 12:39:33 PM PDT 24
Finished	May 23 12:39:38 PM PDT 24
Peak memory	203260 kb
Host	smart-066208b0-0013-4ef5-8c0e-e362e121a40b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3198116601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3198116601
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.622415266
Short name	T415
Test name
Test status
Simulation time	9845884794 ps
CPU time	36.24 seconds
Started	May 23 12:39:35 PM PDT 24
Finished	May 23 12:40:14 PM PDT 24
Peak memory	203336 kb
Host	smart-4726194c-8109-4ff9-acc0-46e696b5cfee
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=622415266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.622415266
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3107985421
Short name	T500
Test name
Test status
Simulation time	2601799791 ps
CPU time	24.24 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:39:58 PM PDT 24
Peak memory	203312 kb
Host	smart-b97e80e7-ee3c-4914-9e91-f6d163d0e7a1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3107985421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3107985421
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1120172907
Short name	T489
Test name
Test status
Simulation time	30872987 ps
CPU time	2.35 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:39:37 PM PDT 24
Peak memory	203272 kb
Host	smart-9b4e104d-fcef-4d90-8071-b94530ac722f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120172907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1120172907
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.927517125
Short name	T758
Test name
Test status
Simulation time	1224470188 ps
CPU time	31.34 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:40:05 PM PDT 24
Peak memory	205720 kb
Host	smart-f59b3433-248a-44ba-8596-fb726dd8e0a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=927517125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.927517125
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3412447968
Short name	T278
Test name
Test status
Simulation time	37513810096 ps
CPU time	299.67 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:44:34 PM PDT 24
Peak memory	209908 kb
Host	smart-065ff9e4-63d5-4a14-9aa2-daa1f93592d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3412447968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3412447968
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4098089688
Short name	T823
Test name
Test status
Simulation time	4521409411 ps
CPU time	394.86 seconds
Started	May 23 12:39:33 PM PDT 24
Finished	May 23 12:46:09 PM PDT 24
Peak memory	211560 kb
Host	smart-3b2780f5-62cf-4ad6-8a7d-c50555b0d425
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4098089688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.4098089688
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1736213349
Short name	T740
Test name
Test status
Simulation time	865619003 ps
CPU time	11.93 seconds
Started	May 23 12:39:33 PM PDT 24
Finished	May 23 12:39:46 PM PDT 24
Peak memory	204844 kb
Host	smart-43ef4d16-a43e-4680-b2a4-fee1f67ed7b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1736213349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1736213349
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.414478246
Short name	T115
Test name
Test status
Simulation time	1207925158 ps
CPU time	51.16 seconds
Started	May 23 12:39:48 PM PDT 24
Finished	May 23 12:40:42 PM PDT 24
Peak memory	211444 kb
Host	smart-16f73ed0-f812-4782-a000-73145d5e5f71
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=414478246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.414478246
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2299709760
Short name	T109
Test name
Test status
Simulation time	12228705102 ps
CPU time	104.73 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	205764 kb
Host	smart-9d7d551d-059e-4ea7-8955-fddc37e80316
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2299709760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.2299709760
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3103522911
Short name	T244
Test name
Test status
Simulation time	715941871 ps
CPU time	19.98 seconds
Started	May 23 12:39:45 PM PDT 24
Finished	May 23 12:40:07 PM PDT 24
Peak memory	203744 kb
Host	smart-0f5a8fca-f18c-42b0-9b5f-8a3df84b3578
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3103522911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3103522911
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.1972884062
Short name	T748
Test name
Test status
Simulation time	1877582616 ps
CPU time	12.11 seconds
Started	May 23 12:39:49 PM PDT 24
Finished	May 23 12:40:04 PM PDT 24
Peak memory	203296 kb
Host	smart-1a13e9e0-89f5-41e0-9b6d-265841c304ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1972884062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1972884062
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.2409633361
Short name	T222
Test name
Test status
Simulation time	1291453717 ps
CPU time	40.16 seconds
Started	May 23 12:39:31 PM PDT 24
Finished	May 23 12:40:12 PM PDT 24
Peak memory	204680 kb
Host	smart-15d118c5-8605-4b67-bf44-588673d65023
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2409633361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2409633361
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.152269934
Short name	T270
Test name
Test status
Simulation time	31710504475 ps
CPU time	189.25 seconds
Started	May 23 12:39:36 PM PDT 24
Finished	May 23 12:42:47 PM PDT 24
Peak memory	204572 kb
Host	smart-3a3b62fa-de7a-488b-93ea-fdae254cbba2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=152269934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.152269934
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.214722079
Short name	T125
Test name
Test status
Simulation time	21555408454 ps
CPU time	211.8 seconds
Started	May 23 12:39:42 PM PDT 24
Finished	May 23 12:43:14 PM PDT 24
Peak memory	211536 kb
Host	smart-69ea38e2-0ba8-4b09-ab58-2899a624e487
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=214722079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.214722079
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1701339479
Short name	T631
Test name
Test status
Simulation time	154600392 ps
CPU time	6.32 seconds
Started	May 23 12:39:34 PM PDT 24
Finished	May 23 12:39:43 PM PDT 24
Peak memory	204440 kb
Host	smart-da94faa7-5179-4081-bfb9-dfccb3935869
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701339479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1701339479
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.1746376078
Short name	T175
Test name
Test status
Simulation time	1168844048 ps
CPU time	24.86 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:40:15 PM PDT 24
Peak memory	203984 kb
Host	smart-fca5f260-b7a0-4c52-8d5e-6167e54a427d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1746376078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1746376078
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.1285457508
Short name	T676
Test name
Test status
Simulation time	160983175 ps
CPU time	3.41 seconds
Started	May 23 12:39:34 PM PDT 24
Finished	May 23 12:39:40 PM PDT 24
Peak memory	203256 kb
Host	smart-667c4757-8e8a-406e-aecc-223899aab0c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1285457508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1285457508
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.848692078
Short name	T828
Test name
Test status
Simulation time	5668807645 ps
CPU time	26.08 seconds
Started	May 23 12:39:32 PM PDT 24
Finished	May 23 12:40:00 PM PDT 24
Peak memory	203328 kb
Host	smart-d578e9a9-5e5c-4488-ab05-c8f7fee71183
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=848692078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.848692078
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.671506298
Short name	T768
Test name
Test status
Simulation time	4024188756 ps
CPU time	33.55 seconds
Started	May 23 12:39:42 PM PDT 24
Finished	May 23 12:40:16 PM PDT 24
Peak memory	203340 kb
Host	smart-9cb1e25e-5314-403d-93e5-9baadaf7c7a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=671506298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.671506298
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3514018278
Short name	T657
Test name
Test status
Simulation time	31774833 ps
CPU time	2.47 seconds
Started	May 23 12:39:31 PM PDT 24
Finished	May 23 12:39:35 PM PDT 24
Peak memory	203280 kb
Host	smart-761e9b1e-ccb1-4494-9999-f5410c620f08
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514018278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3514018278
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.2589999410
Short name	T408
Test name
Test status
Simulation time	7930282461 ps
CPU time	144.44 seconds
Started	May 23 12:39:44 PM PDT 24
Finished	May 23 12:42:10 PM PDT 24
Peak memory	206116 kb
Host	smart-2e90f12b-47a7-4681-9de0-9b72c50d4ee1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2589999410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2589999410
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1697554888
Short name	T419
Test name
Test status
Simulation time	1225904191 ps
CPU time	22.87 seconds
Started	May 23 12:39:45 PM PDT 24
Finished	May 23 12:40:10 PM PDT 24
Peak memory	204828 kb
Host	smart-4830ec0a-a94b-4d48-97d3-a0de2769a484
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1697554888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1697554888
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2409233741
Short name	T633
Test name
Test status
Simulation time	4585066260 ps
CPU time	371.55 seconds
Started	May 23 12:39:48 PM PDT 24
Finished	May 23 12:46:03 PM PDT 24
Peak memory	211536 kb
Host	smart-e59a927c-f140-45be-8973-14dda668a2b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2409233741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2409233741
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.161889830
Short name	T776
Test name
Test status
Simulation time	411894825 ps
CPU time	113.23 seconds
Started	May 23 12:39:46 PM PDT 24
Finished	May 23 12:41:41 PM PDT 24
Peak memory	209324 kb
Host	smart-956787bc-dd20-41da-ab23-530f40699453
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=161889830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.161889830
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.672001270
Short name	T422
Test name
Test status
Simulation time	1715789821 ps
CPU time	31.16 seconds
Started	May 23 12:39:50 PM PDT 24
Finished	May 23 12:40:24 PM PDT 24
Peak memory	205116 kb
Host	smart-0f0cc6d2-258c-462d-bbd9-25f08f3fdbff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=672001270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.672001270
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.396100016
Short name	T476
Test name
Test status
Simulation time	375380571 ps
CPU time	31.86 seconds
Started	May 23 12:39:49 PM PDT 24
Finished	May 23 12:40:24 PM PDT 24
Peak memory	204936 kb
Host	smart-854420be-8132-4c3f-bc48-8a679c9d1028
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=396100016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.396100016
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1125825167
Short name	T296
Test name
Test status
Simulation time	5114043347 ps
CPU time	30.88 seconds
Started	May 23 12:39:49 PM PDT 24
Finished	May 23 12:40:23 PM PDT 24
Peak memory	204360 kb
Host	smart-6f6dc43b-4fc0-48c8-b782-cf3a7fd1d92a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1125825167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1125825167
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.1920979087
Short name	T452
Test name
Test status
Simulation time	4643135076 ps
CPU time	34.03 seconds
Started	May 23 12:39:48 PM PDT 24
Finished	May 23 12:40:25 PM PDT 24
Peak memory	203912 kb
Host	smart-2ff7941d-1abb-466c-b3fe-257dc22da57a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1920979087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1920979087
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.2730575568
Short name	T259
Test name
Test status
Simulation time	207134943 ps
CPU time	20.21 seconds
Started	May 23 12:39:45 PM PDT 24
Finished	May 23 12:40:07 PM PDT 24
Peak memory	211448 kb
Host	smart-596be4ea-b3fd-4116-9008-31c42eee3814
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2730575568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2730575568
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3927049415
Short name	T505
Test name
Test status
Simulation time	115688093634 ps
CPU time	269.63 seconds
Started	May 23 12:39:45 PM PDT 24
Finished	May 23 12:44:17 PM PDT 24
Peak memory	205472 kb
Host	smart-3796c628-58c4-4a6f-94a1-769b92a90706
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927049415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3927049415
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3143020818
Short name	T870
Test name
Test status
Simulation time	24361540687 ps
CPU time	182.05 seconds
Started	May 23 12:39:48 PM PDT 24
Finished	May 23 12:42:54 PM PDT 24
Peak memory	204684 kb
Host	smart-f4819ff2-59ed-4788-a464-e1c5682acd7a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3143020818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3143020818
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1905728804
Short name	T585
Test name
Test status
Simulation time	107121722 ps
CPU time	14.16 seconds
Started	May 23 12:39:49 PM PDT 24
Finished	May 23 12:40:06 PM PDT 24
Peak memory	204464 kb
Host	smart-36767fae-6af5-4af1-8040-83329dc5abf0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905728804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1905728804
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.2211772182
Short name	T433
Test name
Test status
Simulation time	363970487 ps
CPU time	18.84 seconds
Started	May 23 12:39:46 PM PDT 24
Finished	May 23 12:40:07 PM PDT 24
Peak memory	203228 kb
Host	smart-9ddea1ac-a804-4561-bd5f-cd02761a8626
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2211772182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2211772182
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.3497658922
Short name	T254
Test name
Test status
Simulation time	742620827 ps
CPU time	3.62 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:39:54 PM PDT 24
Peak memory	203268 kb
Host	smart-dd88f6f9-9af3-4524-98cc-de96a40a31b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3497658922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3497658922
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.885952396
Short name	T255
Test name
Test status
Simulation time	24456765995 ps
CPU time	47.44 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:40:36 PM PDT 24
Peak memory	203316 kb
Host	smart-3c4c027f-6f35-40fe-8e6e-d60c59a2e4e0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=885952396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.885952396
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.4235932556
Short name	T192
Test name
Test status
Simulation time	2823375655 ps
CPU time	22.96 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:40:12 PM PDT 24
Peak memory	203452 kb
Host	smart-f084dfe0-8ee7-4d68-94a7-cc6a3c3b1508
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4235932556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4235932556
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2080138851
Short name	T294
Test name
Test status
Simulation time	29826260 ps
CPU time	2.41 seconds
Started	May 23 12:39:49 PM PDT 24
Finished	May 23 12:39:55 PM PDT 24
Peak memory	203280 kb
Host	smart-5f555955-c3c0-46f3-bbbc-c8541b8bd5a5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080138851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2080138851
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.4005248713
Short name	T75
Test name
Test status
Simulation time	14189205410 ps
CPU time	283.82 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:44:34 PM PDT 24
Peak memory	210468 kb
Host	smart-ebf63cc3-add3-4f88-a637-84dd7f84587d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4005248713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4005248713
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.322419500
Short name	T562
Test name
Test status
Simulation time	489929523 ps
CPU time	44.68 seconds
Started	May 23 12:39:48 PM PDT 24
Finished	May 23 12:40:35 PM PDT 24
Peak memory	205488 kb
Host	smart-60c99c32-3806-4fbc-a65e-67adb259edc8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=322419500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.322419500
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.4189619162
Short name	T153
Test name
Test status
Simulation time	1371059344 ps
CPU time	176.59 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:42:46 PM PDT 24
Peak memory	209528 kb
Host	smart-bbbc01fd-531d-448b-95c3-b93195def80e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4189619162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.4189619162
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2578596910
Short name	T265
Test name
Test status
Simulation time	201404078 ps
CPU time	19.37 seconds
Started	May 23 12:39:43 PM PDT 24
Finished	May 23 12:40:04 PM PDT 24
Peak memory	204560 kb
Host	smart-6290a7d8-9e76-4458-a9b2-b41c81f403d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2578596910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2578596910
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1194417234
Short name	T791
Test name
Test status
Simulation time	1046535433 ps
CPU time	7.04 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:40:15 PM PDT 24
Peak memory	203324 kb
Host	smart-0c4f834c-b43b-49a1-a479-7757e6164a47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1194417234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1194417234
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.560421652
Short name	T878
Test name
Test status
Simulation time	218980262233 ps
CPU time	652.64 seconds
Started	May 23 12:39:59 PM PDT 24
Finished	May 23 12:50:53 PM PDT 24
Peak memory	205920 kb
Host	smart-d856a4b4-b915-43df-a503-34d8a1304ee9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=560421652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.560421652
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.175609154
Short name	T328
Test name
Test status
Simulation time	464055942 ps
CPU time	12.49 seconds
Started	May 23 12:40:00 PM PDT 24
Finished	May 23 12:40:15 PM PDT 24
Peak memory	203608 kb
Host	smart-36c3c8b8-2ef1-4dbf-a577-8425ecd725de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=175609154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.175609154
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.1205939566
Short name	T868
Test name
Test status
Simulation time	61708705 ps
CPU time	5.87 seconds
Started	May 23 12:40:00 PM PDT 24
Finished	May 23 12:40:07 PM PDT 24
Peak memory	203300 kb
Host	smart-cc29477b-6df6-4b3c-9fb6-b760c675777d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1205939566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1205939566
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.2871181801
Short name	T373
Test name
Test status
Simulation time	925318832 ps
CPU time	31.9 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:38 PM PDT 24
Peak memory	204292 kb
Host	smart-0bdc2b69-c20a-4fe5-9723-19c095ce7dcf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2871181801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2871181801
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2186345711
Short name	T14
Test name
Test status
Simulation time	50271081893 ps
CPU time	131.93 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:42:16 PM PDT 24
Peak memory	205104 kb
Host	smart-d1c56e0b-450c-44c7-bb4a-abd48519505d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186345711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2186345711
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.350172690
Short name	T506
Test name
Test status
Simulation time	38899871877 ps
CPU time	281.01 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:44:46 PM PDT 24
Peak memory	204712 kb
Host	smart-b5afebc6-9842-4273-a85b-e0fdf382500b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=350172690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.350172690
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2412300952
Short name	T688
Test name
Test status
Simulation time	90585918 ps
CPU time	10.7 seconds
Started	May 23 12:40:03 PM PDT 24
Finished	May 23 12:40:18 PM PDT 24
Peak memory	204460 kb
Host	smart-5aec65a7-084f-482a-ba9a-af76154a6152
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412300952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2412300952
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.3702722563
Short name	T319
Test name
Test status
Simulation time	607567450 ps
CPU time	13.15 seconds
Started	May 23 12:40:00 PM PDT 24
Finished	May 23 12:40:14 PM PDT 24
Peak memory	203916 kb
Host	smart-11ae9a50-f514-4ff7-a693-6909d70c8c57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3702722563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3702722563
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.2301227432
Short name	T103
Test name
Test status
Simulation time	49062372 ps
CPU time	2.4 seconds
Started	May 23 12:39:49 PM PDT 24
Finished	May 23 12:39:54 PM PDT 24
Peak memory	203256 kb
Host	smart-ab59c07c-49d5-4fbc-a81b-84f0b8e7ba67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2301227432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2301227432
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1314666648
Short name	T380
Test name
Test status
Simulation time	7376563780 ps
CPU time	31.44 seconds
Started	May 23 12:39:48 PM PDT 24
Finished	May 23 12:40:23 PM PDT 24
Peak memory	203220 kb
Host	smart-35100200-4040-4619-8951-5d10d78165e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314666648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1314666648
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2102570220
Short name	T66
Test name
Test status
Simulation time	6210219635 ps
CPU time	25.45 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:32 PM PDT 24
Peak memory	203324 kb
Host	smart-9cf515d5-d403-4ca1-a3cc-b99b7a59f3e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2102570220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2102570220
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2033472498
Short name	T261
Test name
Test status
Simulation time	24770113 ps
CPU time	2.16 seconds
Started	May 23 12:39:47 PM PDT 24
Finished	May 23 12:39:52 PM PDT 24
Peak memory	203268 kb
Host	smart-edfedd6e-d81f-4e93-a986-7c5f039041a7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033472498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2033472498
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.2688753920
Short name	T409
Test name
Test status
Simulation time	1877296755 ps
CPU time	42.74 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:40:47 PM PDT 24
Peak memory	205752 kb
Host	smart-83ac80bd-2529-4cc6-b751-6d4acc20011a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2688753920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2688753920
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2331151507
Short name	T317
Test name
Test status
Simulation time	21724381681 ps
CPU time	185.9 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:43:10 PM PDT 24
Peak memory	208772 kb
Host	smart-5ed05163-0b35-45fc-980e-178f84e5abfe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2331151507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2331151507
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4137488788
Short name	T36
Test name
Test status
Simulation time	299506027 ps
CPU time	83.62 seconds
Started	May 23 12:39:58 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	207328 kb
Host	smart-77b7838c-ab72-457e-9247-3d371b5ffc98
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4137488788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.4137488788
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.683401304
Short name	T786
Test name
Test status
Simulation time	42956862 ps
CPU time	27.63 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:32 PM PDT 24
Peak memory	206368 kb
Host	smart-2137ea5a-f8b2-4506-91bb-29b6a4e8f847
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=683401304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res et_error.683401304
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.134234154
Short name	T47
Test name
Test status
Simulation time	102057278 ps
CPU time	14.27 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:19 PM PDT 24
Peak memory	204820 kb
Host	smart-9f6c1412-7bf2-4c88-9919-7829426211ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=134234154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.134234154
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1054043782
Short name	T145
Test name
Test status
Simulation time	119472004 ps
CPU time	15.91 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:22 PM PDT 24
Peak memory	204308 kb
Host	smart-c9155615-0506-4477-b4b1-4c1fa34db77b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1054043782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1054043782
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1350845309
Short name	T326
Test name
Test status
Simulation time	35237778752 ps
CPU time	268.26 seconds
Started	May 23 12:40:00 PM PDT 24
Finished	May 23 12:44:31 PM PDT 24
Peak memory	206760 kb
Host	smart-cf25b7bc-e292-4293-9cd5-602235260db2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1350845309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1350845309
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.414764443
Short name	T881
Test name
Test status
Simulation time	150250052 ps
CPU time	14.14 seconds
Started	May 23 12:40:00 PM PDT 24
Finished	May 23 12:40:17 PM PDT 24
Peak memory	203504 kb
Host	smart-46965bce-331d-494b-b9ba-695e75574d57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=414764443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.414764443
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.937174734
Short name	T508
Test name
Test status
Simulation time	112698972 ps
CPU time	11.14 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:16 PM PDT 24
Peak memory	203288 kb
Host	smart-8021097c-9380-4f57-adcf-d2c4a2fdf305
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=937174734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.937174734
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.688107518
Short name	T783
Test name
Test status
Simulation time	144585040 ps
CPU time	6.18 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:40:10 PM PDT 24
Peak memory	204024 kb
Host	smart-2be637ea-a7d8-4dad-b560-5e46354f434b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=688107518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.688107518
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1684326801
Short name	T497
Test name
Test status
Simulation time	38573517245 ps
CPU time	216.45 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:43:39 PM PDT 24
Peak memory	211532 kb
Host	smart-f376974a-84b0-4f46-8fec-3851db1aa3a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684326801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1684326801
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3174170879
Short name	T280
Test name
Test status
Simulation time	37492295152 ps
CPU time	161.51 seconds
Started	May 23 12:40:03 PM PDT 24
Finished	May 23 12:42:48 PM PDT 24
Peak memory	205060 kb
Host	smart-3bb21b5d-430c-49f7-afde-09a60f444be2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3174170879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3174170879
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.645243256
Short name	T100
Test name
Test status
Simulation time	83626214 ps
CPU time	10.58 seconds
Started	May 23 12:40:00 PM PDT 24
Finished	May 23 12:40:12 PM PDT 24
Peak memory	204388 kb
Host	smart-8ef0419f-127c-4eea-8eae-a650f95ceb5c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645243256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.645243256
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.3930023156
Short name	T292
Test name
Test status
Simulation time	1790736834 ps
CPU time	26.9 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:40:35 PM PDT 24
Peak memory	203840 kb
Host	smart-55e13db4-245b-47f2-9caf-717b5d08c987
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930023156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3930023156
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.3291684745
Short name	T413
Test name
Test status
Simulation time	29085051 ps
CPU time	2.06 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:08 PM PDT 24
Peak memory	203252 kb
Host	smart-fd09e602-6865-4333-8f21-33e3f2474c2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3291684745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3291684745
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1944423922
Short name	T760
Test name
Test status
Simulation time	4710043832 ps
CPU time	24.51 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:31 PM PDT 24
Peak memory	203328 kb
Host	smart-002286d1-455e-42e4-b3ed-3a844ffe2fe3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944423922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1944423922
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3891370209
Short name	T730
Test name
Test status
Simulation time	4220905328 ps
CPU time	22.89 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:28 PM PDT 24
Peak memory	203336 kb
Host	smart-099c776d-302e-4a54-b890-9979146dcac3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3891370209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3891370209
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2491664492
Short name	T757
Test name
Test status
Simulation time	42897850 ps
CPU time	2.4 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:40:09 PM PDT 24
Peak memory	203340 kb
Host	smart-10ef1fac-9ca8-4086-b186-0a2e5d40653b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491664492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2491664492
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.37036796
Short name	T647
Test name
Test status
Simulation time	450871648 ps
CPU time	33.56 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:40:38 PM PDT 24
Peak memory	205720 kb
Host	smart-d58ce90f-416d-4aca-844c-2ef931336f0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=37036796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.37036796
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1087342019
Short name	T482
Test name
Test status
Simulation time	3350818293 ps
CPU time	102.63 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:41:48 PM PDT 24
Peak memory	207096 kb
Host	smart-839a9920-52ab-42d9-a495-bce68c8523c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1087342019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1087342019
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.988018689
Short name	T756
Test name
Test status
Simulation time	4075239988 ps
CPU time	132.71 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:42:19 PM PDT 24
Peak memory	208096 kb
Host	smart-de4099bb-67f8-46fe-85ce-168a213cfed9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=988018689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.988018689
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1428582783
Short name	T715
Test name
Test status
Simulation time	10418716793 ps
CPU time	419.27 seconds
Started	May 23 12:40:02 PM PDT 24
Finished	May 23 12:47:05 PM PDT 24
Peak memory	219832 kb
Host	smart-1e5f235a-17ea-487a-80f3-3cba76316943
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1428582783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.1428582783
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3444791994
Short name	T835
Test name
Test status
Simulation time	128430617 ps
CPU time	15.96 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:40:21 PM PDT 24
Peak memory	204972 kb
Host	smart-17e2886c-735b-49c9-82f8-66de15f3fe9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444791994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3444791994
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1133345289
Short name	T774
Test name
Test status
Simulation time	2597172513 ps
CPU time	62.61 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:38:48 PM PDT 24
Peak memory	205464 kb
Host	smart-8551bb3b-0fe5-40f4-8fe8-fa843f9f4aa2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1133345289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1133345289
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.312892743
Short name	T113
Test name
Test status
Simulation time	322723093496 ps
CPU time	752.13 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:50:32 PM PDT 24
Peak memory	205180 kb
Host	smart-66f299ca-3463-4441-854c-383a2f550a54
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=312892743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow _rsp.312892743
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3113479561
Short name	T602
Test name
Test status
Simulation time	2733989107 ps
CPU time	25.06 seconds
Started	May 23 12:37:47 PM PDT 24
Finished	May 23 12:38:14 PM PDT 24
Peak memory	203484 kb
Host	smart-42e8f02b-551f-463d-a9ed-d8e03184bf36
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3113479561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3113479561
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.500835177
Short name	T424
Test name
Test status
Simulation time	198238195 ps
CPU time	13.88 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:38:00 PM PDT 24
Peak memory	203256 kb
Host	smart-7c785033-a735-4716-b265-d6538346ae9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=500835177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.500835177
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.3216389694
Short name	T181
Test name
Test status
Simulation time	401196150 ps
CPU time	8.78 seconds
Started	May 23 12:37:59 PM PDT 24
Finished	May 23 12:38:11 PM PDT 24
Peak memory	204352 kb
Host	smart-b8e8344f-b5c8-4a88-bb41-3e74974597a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3216389694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3216389694
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1538992354
Short name	T726
Test name
Test status
Simulation time	52430379191 ps
CPU time	270.14 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:42:17 PM PDT 24
Peak memory	204772 kb
Host	smart-bb80da2d-d4ac-4d3f-9bd3-a9f532dd1f76
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1538992354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1538992354
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.4282142590
Short name	T782
Test name
Test status
Simulation time	64875526 ps
CPU time	5.76 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:37:51 PM PDT 24
Peak memory	204320 kb
Host	smart-78540fcb-ac1e-4243-b3ec-b3b252454213
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282142590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.4282142590
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.2979161096
Short name	T136
Test name
Test status
Simulation time	3514859904 ps
CPU time	25.41 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:38:12 PM PDT 24
Peak memory	203864 kb
Host	smart-f6f65dce-eafe-48d9-8396-e1c22c8578b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979161096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2979161096
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.475984984
Short name	T634
Test name
Test status
Simulation time	204348527 ps
CPU time	3.61 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:37:51 PM PDT 24
Peak memory	203248 kb
Host	smart-3c8e743b-8813-441c-99cd-18f968c71642
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=475984984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.475984984
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3849767816
Short name	T323
Test name
Test status
Simulation time	20637378020 ps
CPU time	33.39 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:38:22 PM PDT 24
Peak memory	203392 kb
Host	smart-af856352-465a-48f4-ab71-93494590d3b5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849767816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3849767816
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.59688166
Short name	T253
Test name
Test status
Simulation time	5457714932 ps
CPU time	29.84 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:38:18 PM PDT 24
Peak memory	203296 kb
Host	smart-682fd4a4-af1b-4da2-aef5-dc05fe21451c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=59688166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.59688166
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.372564499
Short name	T446
Test name
Test status
Simulation time	57003411 ps
CPU time	2.25 seconds
Started	May 23 12:37:44 PM PDT 24
Finished	May 23 12:37:49 PM PDT 24
Peak memory	203236 kb
Host	smart-98c52291-43cc-457b-8180-5845cca17252
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372564499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.372564499
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.2691667254
Short name	T490
Test name
Test status
Simulation time	230041725 ps
CPU time	3.41 seconds
Started	May 23 12:37:45 PM PDT 24
Finished	May 23 12:37:52 PM PDT 24
Peak memory	203284 kb
Host	smart-1c502758-c04c-4316-8cf8-02f59339724b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2691667254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2691667254
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4293572685
Short name	T618
Test name
Test status
Simulation time	3200920779 ps
CPU time	98.95 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:39:39 PM PDT 24
Peak memory	207780 kb
Host	smart-63432747-6de2-4226-806a-7fa37259d043
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4293572685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4293572685
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3601038535
Short name	T649
Test name
Test status
Simulation time	363492692 ps
CPU time	72.86 seconds
Started	May 23 12:37:59 PM PDT 24
Finished	May 23 12:39:15 PM PDT 24
Peak memory	206884 kb
Host	smart-ff5a1619-eaec-41ae-a54e-eb24c3ec7890
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3601038535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3601038535
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.260900592
Short name	T543
Test name
Test status
Simulation time	195863230 ps
CPU time	24.81 seconds
Started	May 23 12:37:59 PM PDT 24
Finished	May 23 12:38:26 PM PDT 24
Peak memory	205856 kb
Host	smart-16eecc65-e1fa-4e2f-99e4-803318697fb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=260900592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.260900592
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3110717019
Short name	T460
Test name
Test status
Simulation time	88972159 ps
CPU time	9.56 seconds
Started	May 23 12:37:43 PM PDT 24
Finished	May 23 12:37:56 PM PDT 24
Peak memory	204720 kb
Host	smart-6f25557e-b7f2-41b4-b9ec-64f48389457c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3110717019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3110717019
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1012443568
Short name	T111
Test name
Test status
Simulation time	3854989696 ps
CPU time	60.25 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	205512 kb
Host	smart-0d4fa49c-e236-4fa6-b0b7-565086032aa3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1012443568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1012443568
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3465503379
Short name	T295
Test name
Test status
Simulation time	2334905470 ps
CPU time	23.35 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:40:32 PM PDT 24
Peak memory	203672 kb
Host	smart-b3d6f511-3523-41d3-b26b-9feafa2b85a6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3465503379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3465503379
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.1833280662
Short name	T771
Test name
Test status
Simulation time	355292589 ps
CPU time	11.23 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:40:20 PM PDT 24
Peak memory	203288 kb
Host	smart-e798eab3-b36b-4707-9296-2817b6b61747
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1833280662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1833280662
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.1805380481
Short name	T537
Test name
Test status
Simulation time	197682942 ps
CPU time	24.86 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:40:33 PM PDT 24
Peak memory	211408 kb
Host	smart-486bfba3-937f-431e-b9a0-5f25c8638e13
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1805380481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1805380481
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3092326368
Short name	T555
Test name
Test status
Simulation time	57570201921 ps
CPU time	189.26 seconds
Started	May 23 12:40:01 PM PDT 24
Finished	May 23 12:43:13 PM PDT 24
Peak memory	204756 kb
Host	smart-ebd2b3b2-0c23-4cc6-bc64-0c69cbaef5de
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092326368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3092326368
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1372442798
Short name	T132
Test name
Test status
Simulation time	30365976813 ps
CPU time	139.81 seconds
Started	May 23 12:40:03 PM PDT 24
Finished	May 23 12:42:27 PM PDT 24
Peak memory	204684 kb
Host	smart-fb3ed10a-6135-4474-9969-c459e208030e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1372442798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1372442798
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1431296031
Short name	T641
Test name
Test status
Simulation time	159145961 ps
CPU time	13.07 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:40:21 PM PDT 24
Peak memory	204440 kb
Host	smart-e312d3dc-1926-404b-80c9-796f18f1ef8d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431296031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1431296031
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.2579216406
Short name	T69
Test name
Test status
Simulation time	678192428 ps
CPU time	12 seconds
Started	May 23 12:40:00 PM PDT 24
Finished	May 23 12:40:14 PM PDT 24
Peak memory	211580 kb
Host	smart-e25e25d1-2ba6-4cdf-a9d9-54ae0ef469c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2579216406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2579216406
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.1230133994
Short name	T465
Test name
Test status
Simulation time	126573490 ps
CPU time	2.52 seconds
Started	May 23 12:40:03 PM PDT 24
Finished	May 23 12:40:10 PM PDT 24
Peak memory	203220 kb
Host	smart-0290333a-a034-4a04-8a0a-e4b55dbd0020
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1230133994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1230133994
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4243420127
Short name	T843
Test name
Test status
Simulation time	25921100243 ps
CPU time	41.76 seconds
Started	May 23 12:40:04 PM PDT 24
Finished	May 23 12:40:50 PM PDT 24
Peak memory	203428 kb
Host	smart-3a149c1c-29ff-47a6-a1e4-4a2c15d6fbb4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243420127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4243420127
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3912106978
Short name	T723
Test name
Test status
Simulation time	3753848991 ps
CPU time	32.35 seconds
Started	May 23 12:40:04 PM PDT 24
Finished	May 23 12:40:40 PM PDT 24
Peak memory	203376 kb
Host	smart-488c1521-e492-444c-9524-1c5e6ad44547
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3912106978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3912106978
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.377307528
Short name	T549
Test name
Test status
Simulation time	29394389 ps
CPU time	2.13 seconds
Started	May 23 12:40:04 PM PDT 24
Finished	May 23 12:40:10 PM PDT 24
Peak memory	203364 kb
Host	smart-c6cb51a9-99c9-46b6-8c34-290729e411d8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377307528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.377307528
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.2888939444
Short name	T245
Test name
Test status
Simulation time	2421719375 ps
CPU time	128.14 seconds
Started	May 23 12:40:03 PM PDT 24
Finished	May 23 12:42:15 PM PDT 24
Peak memory	205784 kb
Host	smart-ff6fb2c0-a367-48dc-8a65-9af43656d812
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2888939444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2888939444
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3432896528
Short name	T148
Test name
Test status
Simulation time	1790985435 ps
CPU time	103.32 seconds
Started	May 23 12:40:04 PM PDT 24
Finished	May 23 12:41:52 PM PDT 24
Peak memory	208140 kb
Host	smart-2571b6e3-ade1-4869-aa48-67812266ba1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3432896528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3432896528
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2499496142
Short name	T636
Test name
Test status
Simulation time	661620576 ps
CPU time	202.91 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:43:31 PM PDT 24
Peak memory	208576 kb
Host	smart-84d19cf1-0903-437f-a9bb-5fea39aa5f04
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2499496142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2499496142
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1356480796
Short name	T453
Test name
Test status
Simulation time	2095052404 ps
CPU time	227 seconds
Started	May 23 12:40:04 PM PDT 24
Finished	May 23 12:43:55 PM PDT 24
Peak memory	211472 kb
Host	smart-1c7376c8-18e7-405b-9fce-8493c9a272d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1356480796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1356480796
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.539315941
Short name	T368
Test name
Test status
Simulation time	369309428 ps
CPU time	15.53 seconds
Started	May 23 12:40:05 PM PDT 24
Finished	May 23 12:40:24 PM PDT 24
Peak memory	204808 kb
Host	smart-f1ca1d66-fde8-4dff-94f2-5b50ac1b1afc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=539315941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.539315941
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1613568880
Short name	T165
Test name
Test status
Simulation time	133376048 ps
CPU time	14.69 seconds
Started	May 23 12:40:14 PM PDT 24
Finished	May 23 12:40:30 PM PDT 24
Peak memory	211432 kb
Host	smart-a8f0d2b3-d462-4fcd-8c8b-9894561a7a22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1613568880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1613568880
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3450921012
Short name	T592
Test name
Test status
Simulation time	52032451795 ps
CPU time	415.87 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:47:14 PM PDT 24
Peak memory	206776 kb
Host	smart-0316a0d8-cb93-4c13-b1d4-f522717b3c45
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3450921012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.3450921012
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2907939604
Short name	T11
Test name
Test status
Simulation time	244101976 ps
CPU time	7.78 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:25 PM PDT 24
Peak memory	203460 kb
Host	smart-46dbc190-9523-475b-9d0b-38ddc901d480
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2907939604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2907939604
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.1815069823
Short name	T348
Test name
Test status
Simulation time	704514025 ps
CPU time	8.04 seconds
Started	May 23 12:40:14 PM PDT 24
Finished	May 23 12:40:23 PM PDT 24
Peak memory	203268 kb
Host	smart-7cc7a36d-9417-40ad-a623-628cc56b1ee0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1815069823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1815069823
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.2687590740
Short name	T847
Test name
Test status
Simulation time	873233677 ps
CPU time	16.78 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:40:30 PM PDT 24
Peak memory	211456 kb
Host	smart-9a2e854f-c8da-4148-a62a-d4b43d20255e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2687590740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2687590740
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1337738420
Short name	T738
Test name
Test status
Simulation time	50756309320 ps
CPU time	120.74 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:42:15 PM PDT 24
Peak memory	204664 kb
Host	smart-6d792506-8b69-413d-a436-8f404c638f99
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337738420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1337738420
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3625295798
Short name	T140
Test name
Test status
Simulation time	38783709959 ps
CPU time	252.57 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:44:27 PM PDT 24
Peak memory	204964 kb
Host	smart-0e9b4a30-b83c-45a3-968a-387ede095e23
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3625295798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3625295798
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.219258359
Short name	T587
Test name
Test status
Simulation time	69741975 ps
CPU time	6.8 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:40:20 PM PDT 24
Peak memory	204404 kb
Host	smart-14ba17bd-8836-4d47-9eb8-f7f97b1fd6f9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219258359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.219258359
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.1053762351
Short name	T392
Test name
Test status
Simulation time	1590734498 ps
CPU time	20.77 seconds
Started	May 23 12:40:14 PM PDT 24
Finished	May 23 12:40:36 PM PDT 24
Peak memory	203880 kb
Host	smart-ce315420-93d0-46eb-a0c6-c95febba3974
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1053762351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1053762351
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.577760650
Short name	T330
Test name
Test status
Simulation time	29238992 ps
CPU time	2.54 seconds
Started	May 23 12:40:03 PM PDT 24
Finished	May 23 12:40:10 PM PDT 24
Peak memory	203380 kb
Host	smart-3a606ec5-3b09-4bb7-9639-55d93c20bbd0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=577760650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.577760650
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3868923202
Short name	T731
Test name
Test status
Simulation time	13093194190 ps
CPU time	28.58 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:40:43 PM PDT 24
Peak memory	203340 kb
Host	smart-00541b36-9790-4c9d-b52d-993f652d2fe9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868923202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3868923202
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3287818369
Short name	T356
Test name
Test status
Simulation time	2741673041 ps
CPU time	18.06 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:40:31 PM PDT 24
Peak memory	203420 kb
Host	smart-fbeeb9d1-8e0d-4b3f-b30f-04b0b49c0901
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3287818369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3287818369
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3540794689
Short name	T799
Test name
Test status
Simulation time	32720468 ps
CPU time	2.36 seconds
Started	May 23 12:40:15 PM PDT 24
Finished	May 23 12:40:19 PM PDT 24
Peak memory	203280 kb
Host	smart-8f4f4e9f-5aa4-4389-ab39-6cca4dbb6601
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540794689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3540794689
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.2163545958
Short name	T114
Test name
Test status
Simulation time	8290009729 ps
CPU time	262.55 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:44:37 PM PDT 24
Peak memory	211536 kb
Host	smart-34a02dbf-cb49-4673-8c87-d7ffc30c09be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2163545958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2163545958
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1960445098
Short name	T25
Test name
Test status
Simulation time	10335214081 ps
CPU time	254.54 seconds
Started	May 23 12:40:15 PM PDT 24
Finished	May 23 12:44:31 PM PDT 24
Peak memory	211460 kb
Host	smart-c94a675c-a242-4dd4-ba8a-54552237613f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1960445098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1960445098
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1995604951
Short name	T680
Test name
Test status
Simulation time	93326314 ps
CPU time	28.39 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:46 PM PDT 24
Peak memory	206616 kb
Host	smart-8a847119-81ff-4847-b67d-5141bc2dff48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1995604951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1995604951
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3290515521
Short name	T735
Test name
Test status
Simulation time	15500126659 ps
CPU time	468.36 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:48:07 PM PDT 24
Peak memory	219716 kb
Host	smart-c534d874-ead6-4853-b715-5400804e4137
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3290515521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.3290515521
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.517246503
Short name	T102
Test name
Test status
Simulation time	799193133 ps
CPU time	20.6 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:42 PM PDT 24
Peak memory	211460 kb
Host	smart-54966d4f-d077-4527-bda4-d6a4192e970d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=517246503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.517246503
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.247452284
Short name	T218
Test name
Test status
Simulation time	798523041 ps
CPU time	16.92 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:34 PM PDT 24
Peak memory	205180 kb
Host	smart-ba2e4135-c134-423f-9684-9bc8dfa23ba3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=247452284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.247452284
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1423112730
Short name	T803
Test name
Test status
Simulation time	91532835026 ps
CPU time	564.96 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:49:46 PM PDT 24
Peak memory	211508 kb
Host	smart-9278a6b4-220e-4f93-9443-355dcf36cba3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1423112730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1423112730
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3731309825
Short name	T887
Test name
Test status
Simulation time	975019902 ps
CPU time	21.55 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:40 PM PDT 24
Peak memory	203384 kb
Host	smart-fc9474c5-3fa7-48b3-9576-43dfb6b71d9d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3731309825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3731309825
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.2069364142
Short name	T614
Test name
Test status
Simulation time	263982776 ps
CPU time	7.99 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:29 PM PDT 24
Peak memory	203280 kb
Host	smart-5e3a8d8b-b96c-443a-8c72-13591729015a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2069364142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2069364142
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.2928483469
Short name	T372
Test name
Test status
Simulation time	1180543275 ps
CPU time	30.21 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:49 PM PDT 24
Peak memory	204800 kb
Host	smart-81f2930f-9049-42f9-a061-31c5939db04a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2928483469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2928483469
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1529465670
Short name	T64
Test name
Test status
Simulation time	16702410226 ps
CPU time	78.09 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:41:39 PM PDT 24
Peak memory	204476 kb
Host	smart-864a92db-4749-4d30-8f81-40cb84aa6a06
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529465670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1529465670
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2966204122
Short name	T354
Test name
Test status
Simulation time	12503967352 ps
CPU time	44.86 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:41:06 PM PDT 24
Peak memory	204500 kb
Host	smart-fe26ada9-0c94-4769-8dc4-3430fc5ab84b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2966204122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2966204122
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2220564406
Short name	T897
Test name
Test status
Simulation time	126330654 ps
CPU time	11.31 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:32 PM PDT 24
Peak memory	204400 kb
Host	smart-53f3eb6c-1adb-495e-9db9-582ae13cb2c6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220564406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2220564406
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.3996634441
Short name	T383
Test name
Test status
Simulation time	1585367497 ps
CPU time	24.83 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:46 PM PDT 24
Peak memory	203676 kb
Host	smart-9a1d2aef-40a0-43ec-ae8f-43c194fdb84b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3996634441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3996634441
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.2040985378
Short name	T725
Test name
Test status
Simulation time	72599531 ps
CPU time	1.86 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:20 PM PDT 24
Peak memory	203252 kb
Host	smart-7079a7ad-ef29-446f-9a1a-04100a8854a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2040985378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2040985378
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.314677737
Short name	T441
Test name
Test status
Simulation time	3717772117 ps
CPU time	23.22 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:44 PM PDT 24
Peak memory	203296 kb
Host	smart-939ced85-5bba-4b40-9454-6a18c39ca357
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=314677737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.314677737
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1432823666
Short name	T693
Test name
Test status
Simulation time	3867323599 ps
CPU time	30.07 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:49 PM PDT 24
Peak memory	203340 kb
Host	smart-44480d6c-8a04-4e96-a791-9d12c77edf20
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1432823666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1432823666
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1930500424
Short name	T655
Test name
Test status
Simulation time	36383268 ps
CPU time	2.08 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:20 PM PDT 24
Peak memory	203248 kb
Host	smart-07fe7ddc-99c0-47e3-ad95-dbb9e28a5346
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930500424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1930500424
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.2281125233
Short name	T480
Test name
Test status
Simulation time	4920539636 ps
CPU time	178.6 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:43:20 PM PDT 24
Peak memory	207312 kb
Host	smart-80054b94-9553-4208-bf8d-0fbe3caf7eaa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2281125233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2281125233
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3253575666
Short name	T291
Test name
Test status
Simulation time	686073128 ps
CPU time	48.11 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:41:09 PM PDT 24
Peak memory	205652 kb
Host	smart-3b223a2a-5ca9-4cfd-8b80-cefaf9001793
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253575666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3253575666
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2377818518
Short name	T827
Test name
Test status
Simulation time	7992509268 ps
CPU time	411.89 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:47:13 PM PDT 24
Peak memory	210928 kb
Host	smart-a4cadf72-6b4b-44b0-89ff-ff2e135f64c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2377818518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2377818518
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3040944993
Short name	T667
Test name
Test status
Simulation time	316607154 ps
CPU time	72.99 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	207536 kb
Host	smart-5ff21544-a40b-4e07-802f-258dbf27d5b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3040944993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.3040944993
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.935835797
Short name	T285
Test name
Test status
Simulation time	164060128 ps
CPU time	17.03 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:38 PM PDT 24
Peak memory	204716 kb
Host	smart-ebf82c02-b943-481f-989d-aaed62dc7651
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=935835797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.935835797
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.4042034244
Short name	T691
Test name
Test status
Simulation time	1819594530 ps
CPU time	42.07 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:41:01 PM PDT 24
Peak memory	205792 kb
Host	smart-4dbe5249-41d0-40b6-93ce-ca5d647bad23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4042034244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.4042034244
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3887123450
Short name	T737
Test name
Test status
Simulation time	87398130281 ps
CPU time	585.94 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:50:06 PM PDT 24
Peak memory	206300 kb
Host	smart-49c756ce-bde8-4986-b8b4-d6bde413c9a2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3887123450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.3887123450
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.754195093
Short name	T386
Test name
Test status
Simulation time	451334924 ps
CPU time	17.24 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:36 PM PDT 24
Peak memory	203476 kb
Host	smart-28cf86a9-9892-4318-9f09-de265c46ac81
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=754195093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.754195093
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.4156207141
Short name	T252
Test name
Test status
Simulation time	378969869 ps
CPU time	13.6 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:33 PM PDT 24
Peak memory	203276 kb
Host	smart-912482b7-6004-4fcf-9dd1-6253ab0162bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4156207141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4156207141
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.3629253719
Short name	T570
Test name
Test status
Simulation time	13787255 ps
CPU time	2.13 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:23 PM PDT 24
Peak memory	203260 kb
Host	smart-aa738b68-3e49-4058-bc34-cf0af9cf8621
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3629253719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3629253719
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.125424185
Short name	T195
Test name
Test status
Simulation time	47891618719 ps
CPU time	236.5 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:44:17 PM PDT 24
Peak memory	204004 kb
Host	smart-bfa15889-9f74-44b0-a9f4-01e38ad18ae4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=125424185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.125424185
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3278208358
Short name	T517
Test name
Test status
Simulation time	23795540859 ps
CPU time	98.71 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:41:59 PM PDT 24
Peak memory	211512 kb
Host	smart-04ddb131-844d-4191-a2f5-2a2f751b62aa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3278208358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3278208358
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.590175279
Short name	T248
Test name
Test status
Simulation time	32235980 ps
CPU time	1.91 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:22 PM PDT 24
Peak memory	203220 kb
Host	smart-99b1a35c-d451-4de2-92bb-2786a9a7c4bb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590175279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.590175279
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.2378852018
Short name	T831
Test name
Test status
Simulation time	3349982475 ps
CPU time	18.22 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:39 PM PDT 24
Peak memory	204076 kb
Host	smart-d84c2e3b-47cb-464c-bc4f-e0d514065357
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2378852018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2378852018
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.1451284378
Short name	T50
Test name
Test status
Simulation time	172166501 ps
CPU time	3.28 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:25 PM PDT 24
Peak memory	203356 kb
Host	smart-1a84b097-5970-43c3-b138-c29047a635c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451284378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1451284378
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2859781126
Short name	T708
Test name
Test status
Simulation time	9349841010 ps
CPU time	29.35 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:51 PM PDT 24
Peak memory	203424 kb
Host	smart-4ec3c80e-d36c-47f1-baed-25f5dfc4c5ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859781126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2859781126
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2762007534
Short name	T196
Test name
Test status
Simulation time	3016278110 ps
CPU time	27.98 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:48 PM PDT 24
Peak memory	203340 kb
Host	smart-9805b197-4f06-4856-a112-6cfb84cdd8a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2762007534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2762007534
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2182421836
Short name	T772
Test name
Test status
Simulation time	46300668 ps
CPU time	2.15 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:24 PM PDT 24
Peak memory	203368 kb
Host	smart-49f60bb0-8b3b-45a0-8dec-f2f2f098e6b0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182421836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2182421836
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.1847520489
Short name	T811
Test name
Test status
Simulation time	352769104 ps
CPU time	21.32 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:42 PM PDT 24
Peak memory	205144 kb
Host	smart-75f55c1d-341e-4afa-9b70-a88e746d35e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847520489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1847520489
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3742989734
Short name	T510
Test name
Test status
Simulation time	4033891226 ps
CPU time	31.5 seconds
Started	May 23 12:40:15 PM PDT 24
Finished	May 23 12:40:47 PM PDT 24
Peak memory	204988 kb
Host	smart-1938d57c-4a4c-4219-9658-f3acf135a663
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3742989734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3742989734
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3631071325
Short name	T477
Test name
Test status
Simulation time	2310242712 ps
CPU time	311.07 seconds
Started	May 23 12:40:15 PM PDT 24
Finished	May 23 12:45:27 PM PDT 24
Peak memory	219808 kb
Host	smart-4b29665a-1ab9-4328-acdd-03df21846579
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3631071325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3631071325
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2153006806
Short name	T402
Test name
Test status
Simulation time	235219875 ps
CPU time	8.85 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:29 PM PDT 24
Peak memory	204872 kb
Host	smart-6a8c3e4e-53ae-46a0-bdff-0faeeab830ac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2153006806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2153006806
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3465201328
Short name	T214
Test name
Test status
Simulation time	976458412 ps
CPU time	49.37 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:41:11 PM PDT 24
Peak memory	206096 kb
Host	smart-d4c27f8c-f21d-459a-8fed-9b0c2a714f08
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3465201328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3465201328
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3878496359
Short name	T301
Test name
Test status
Simulation time	37138190213 ps
CPU time	221.25 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:43:59 PM PDT 24
Peak memory	206420 kb
Host	smart-fa54c4b6-a142-4bfc-baf0-6a4693fa9ea2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3878496359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3878496359
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4151459499
Short name	T474
Test name
Test status
Simulation time	21187794 ps
CPU time	2.85 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:22 PM PDT 24
Peak memory	203236 kb
Host	smart-790e10eb-aba8-4000-92a4-c18aad8923b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4151459499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.4151459499
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.1874427517
Short name	T12
Test name
Test status
Simulation time	882062203 ps
CPU time	30.11 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:49 PM PDT 24
Peak memory	203384 kb
Host	smart-e07f50f1-5705-4c72-b239-f34aa64de0da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1874427517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1874427517
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.825614588
Short name	T52
Test name
Test status
Simulation time	832082873 ps
CPU time	34.09 seconds
Started	May 23 12:40:13 PM PDT 24
Finished	May 23 12:40:47 PM PDT 24
Peak memory	204296 kb
Host	smart-d0ead83b-2252-4232-abb3-1024a68ea8fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825614588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.825614588
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1450588321
Short name	T840
Test name
Test status
Simulation time	10291407348 ps
CPU time	56.24 seconds
Started	May 23 12:40:14 PM PDT 24
Finished	May 23 12:41:11 PM PDT 24
Peak memory	211388 kb
Host	smart-3c8e244d-9a74-46d8-8a5d-fbfb3e023a79
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450588321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1450588321
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2204957243
Short name	T488
Test name
Test status
Simulation time	17470478839 ps
CPU time	115.67 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:42:14 PM PDT 24
Peak memory	204724 kb
Host	smart-83f06797-9e8f-4a32-9ee0-7d1f44d7d7e8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2204957243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2204957243
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1303364761
Short name	T571
Test name
Test status
Simulation time	340448727 ps
CPU time	7.05 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:25 PM PDT 24
Peak memory	204372 kb
Host	smart-a5645bdd-5585-4c6d-b701-301b9bfd079b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303364761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1303364761
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.3338338096
Short name	T429
Test name
Test status
Simulation time	255249371 ps
CPU time	8.78 seconds
Started	May 23 12:40:15 PM PDT 24
Finished	May 23 12:40:26 PM PDT 24
Peak memory	203968 kb
Host	smart-e85c4378-7cf3-4821-8980-faa86d02fd7a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3338338096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3338338096
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.3296010246
Short name	T217
Test name
Test status
Simulation time	123360513 ps
CPU time	3.6 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:22 PM PDT 24
Peak memory	203336 kb
Host	smart-3e15ca27-03b5-4f76-9a35-9f50635cdb7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3296010246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3296010246
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1957528772
Short name	T884
Test name
Test status
Simulation time	53084336681 ps
CPU time	64.87 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	203428 kb
Host	smart-c18a4f6f-413b-4ea2-a190-b74726d5e78e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957528772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1957528772
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3479300877
Short name	T703
Test name
Test status
Simulation time	4820818697 ps
CPU time	34.64 seconds
Started	May 23 12:40:14 PM PDT 24
Finished	May 23 12:40:50 PM PDT 24
Peak memory	203452 kb
Host	smart-77a299f0-2c8b-4461-a9f5-ce061578022a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3479300877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3479300877
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.296734794
Short name	T643
Test name
Test status
Simulation time	26528969 ps
CPU time	2.02 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:20 PM PDT 24
Peak memory	203228 kb
Host	smart-d4223f1e-40f8-4835-a2cd-240ba327c396
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296734794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.296734794
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.360818633
Short name	T32
Test name
Test status
Simulation time	2915709065 ps
CPU time	130.86 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:42:28 PM PDT 24
Peak memory	208476 kb
Host	smart-307c8a9d-226b-40df-bdce-eb674affb17c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=360818633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.360818633
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1588960055
Short name	T343
Test name
Test status
Simulation time	5643935299 ps
CPU time	150.56 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:42:52 PM PDT 24
Peak memory	208304 kb
Host	smart-83af4828-87d6-43b5-99a8-2b0aeb960006
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1588960055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1588960055
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3166160004
Short name	T743
Test name
Test status
Simulation time	7241094922 ps
CPU time	429.61 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:47:27 PM PDT 24
Peak memory	222092 kb
Host	smart-6fe25608-74ca-4067-9214-dbe1ccc41697
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3166160004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3166160004
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3325183155
Short name	T664
Test name
Test status
Simulation time	204350395 ps
CPU time	67.23 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:41:25 PM PDT 24
Peak memory	208408 kb
Host	smart-07956e53-164a-40c9-b1ea-646f48180bc8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3325183155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.3325183155
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3331060650
Short name	T260
Test name
Test status
Simulation time	174810431 ps
CPU time	20.84 seconds
Started	May 23 12:40:19 PM PDT 24
Finished	May 23 12:40:42 PM PDT 24
Peak memory	204804 kb
Host	smart-568e6b23-b03d-4beb-926c-a4833f8820ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3331060650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3331060650
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3864856278
Short name	T134
Test name
Test status
Simulation time	65795094 ps
CPU time	4.12 seconds
Started	May 23 12:40:31 PM PDT 24
Finished	May 23 12:40:36 PM PDT 24
Peak memory	203268 kb
Host	smart-3b179cb1-c311-47e7-968f-8b7c33e8eea6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3864856278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3864856278
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2999540500
Short name	T87
Test name
Test status
Simulation time	97883206136 ps
CPU time	485.81 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:48:41 PM PDT 24
Peak memory	211540 kb
Host	smart-fd053491-c60a-4f71-bf62-7c5b4a6bc1a9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2999540500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2999540500
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.771128324
Short name	T672
Test name
Test status
Simulation time	1014907398 ps
CPU time	21.23 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:40:56 PM PDT 24
Peak memory	203332 kb
Host	smart-018d0941-6e83-46e3-9e3d-f2a73d7311ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=771128324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.771128324
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.1780475954
Short name	T427
Test name
Test status
Simulation time	125932746 ps
CPU time	12.04 seconds
Started	May 23 12:40:27 PM PDT 24
Finished	May 23 12:40:40 PM PDT 24
Peak memory	203236 kb
Host	smart-7114d62d-01b3-4207-ab5a-b17842b64cb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1780475954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1780475954
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.1337523618
Short name	T79
Test name
Test status
Simulation time	1012772954 ps
CPU time	21.94 seconds
Started	May 23 12:40:17 PM PDT 24
Finished	May 23 12:40:41 PM PDT 24
Peak memory	204368 kb
Host	smart-4c143636-0e76-43b4-bcc1-c36ab6276cd2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1337523618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1337523618
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1379112588
Short name	T890
Test name
Test status
Simulation time	32919680444 ps
CPU time	192.93 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:43:30 PM PDT 24
Peak memory	204588 kb
Host	smart-8e7cce69-7dc7-4709-8d7e-5ec124d1c48b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379112588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1379112588
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.26374571
Short name	T123
Test name
Test status
Simulation time	14467784633 ps
CPU time	81.52 seconds
Started	May 23 12:40:28 PM PDT 24
Finished	May 23 12:41:50 PM PDT 24
Peak memory	204772 kb
Host	smart-e7c3d865-7f83-43cc-876b-1dd1d187c319
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=26374571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.26374571
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.561011577
Short name	T678
Test name
Test status
Simulation time	64262533 ps
CPU time	8.36 seconds
Started	May 23 12:40:14 PM PDT 24
Finished	May 23 12:40:24 PM PDT 24
Peak memory	204432 kb
Host	smart-bae740c7-d332-45e3-9d01-61f94d873a46
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561011577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.561011577
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.2345980549
Short name	T875
Test name
Test status
Simulation time	953125296 ps
CPU time	17.33 seconds
Started	May 23 12:40:25 PM PDT 24
Finished	May 23 12:40:43 PM PDT 24
Peak memory	203140 kb
Host	smart-314ce609-81dc-463c-8749-93fb1480f9e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2345980549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2345980549
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.2175783733
Short name	T286
Test name
Test status
Simulation time	34953190 ps
CPU time	2.38 seconds
Started	May 23 12:40:16 PM PDT 24
Finished	May 23 12:40:20 PM PDT 24
Peak memory	203236 kb
Host	smart-496f66e5-2ec1-47ad-b53b-b8af61d8f76a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2175783733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2175783733
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1454529515
Short name	T159
Test name
Test status
Simulation time	4978726234 ps
CPU time	27.05 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:48 PM PDT 24
Peak memory	203284 kb
Host	smart-f1844b2e-bd52-4c83-bfac-b12d3c088b46
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454529515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1454529515
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2604161839
Short name	T865
Test name
Test status
Simulation time	8220402246 ps
CPU time	35.7 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:56 PM PDT 24
Peak memory	203336 kb
Host	smart-6383f55c-65c0-4ac6-a23d-3b57cbecdb32
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2604161839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2604161839
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2527307759
Short name	T459
Test name
Test status
Simulation time	41152458 ps
CPU time	1.98 seconds
Started	May 23 12:40:18 PM PDT 24
Finished	May 23 12:40:23 PM PDT 24
Peak memory	203096 kb
Host	smart-fdec02e3-4fc8-4c09-b261-b590d6ce1d5c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527307759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2527307759
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.716735826
Short name	T185
Test name
Test status
Simulation time	30368426322 ps
CPU time	216.74 seconds
Started	May 23 12:40:32 PM PDT 24
Finished	May 23 12:44:10 PM PDT 24
Peak memory	206252 kb
Host	smart-4100cf89-2dbe-445b-814d-619ddb9567a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=716735826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.716735826
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3421971166
Short name	T685
Test name
Test status
Simulation time	7562585209 ps
CPU time	199.44 seconds
Started	May 23 12:40:31 PM PDT 24
Finished	May 23 12:43:52 PM PDT 24
Peak memory	207016 kb
Host	smart-22ea6283-c336-4ff7-8c00-00af3035c3b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3421971166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3421971166
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3235351607
Short name	T28
Test name
Test status
Simulation time	366228900 ps
CPU time	88.26 seconds
Started	May 23 12:40:24 PM PDT 24
Finished	May 23 12:41:53 PM PDT 24
Peak memory	207744 kb
Host	smart-32866984-c87c-491c-b76f-5d7a9e2bf4e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3235351607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.3235351607
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.933060627
Short name	T893
Test name
Test status
Simulation time	106573576 ps
CPU time	46.03 seconds
Started	May 23 12:40:25 PM PDT 24
Finished	May 23 12:41:12 PM PDT 24
Peak memory	206536 kb
Host	smart-3f2aecc0-4bde-4456-a4c7-ee4da6343aef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=933060627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res et_error.933060627
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3968583540
Short name	T428
Test name
Test status
Simulation time	61732501 ps
CPU time	10.22 seconds
Started	May 23 12:40:35 PM PDT 24
Finished	May 23 12:40:47 PM PDT 24
Peak memory	204876 kb
Host	smart-8fe2118c-7875-49f5-b3dd-5d586de3103b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3968583540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3968583540
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.424718502
Short name	T133
Test name
Test status
Simulation time	6711647153 ps
CPU time	33.34 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	204524 kb
Host	smart-f30dc70c-527c-4e3d-9590-8958ca102c28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424718502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.424718502
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1026885433
Short name	T122
Test name
Test status
Simulation time	66128737971 ps
CPU time	226.08 seconds
Started	May 23 12:40:36 PM PDT 24
Finished	May 23 12:44:24 PM PDT 24
Peak memory	211596 kb
Host	smart-bdf8421f-e44d-4a10-bcb4-74cde73f723c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1026885433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.1026885433
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1111165343
Short name	T487
Test name
Test status
Simulation time	4909515587 ps
CPU time	21.63 seconds
Started	May 23 12:40:25 PM PDT 24
Finished	May 23 12:40:48 PM PDT 24
Peak memory	203804 kb
Host	smart-8036da90-8961-4cc5-936b-21e2ee46c51c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1111165343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1111165343
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.1237524788
Short name	T23
Test name
Test status
Simulation time	22187866 ps
CPU time	2.14 seconds
Started	May 23 12:40:31 PM PDT 24
Finished	May 23 12:40:34 PM PDT 24
Peak memory	203216 kb
Host	smart-d5cabeb0-1d46-49dc-9c83-7c824dac3b0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1237524788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1237524788
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.3481615999
Short name	T182
Test name
Test status
Simulation time	1540345149 ps
CPU time	11.82 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:40:48 PM PDT 24
Peak memory	204228 kb
Host	smart-7ca293c5-be44-4655-9dc2-30701852d051
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3481615999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3481615999
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3423982170
Short name	T733
Test name
Test status
Simulation time	47212637109 ps
CPU time	186.35 seconds
Started	May 23 12:40:28 PM PDT 24
Finished	May 23 12:43:35 PM PDT 24
Peak memory	205244 kb
Host	smart-e5b66e07-3e7f-43d9-9138-160849647cce
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423982170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3423982170
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1665531884
Short name	T405
Test name
Test status
Simulation time	24702658918 ps
CPU time	103.08 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:42:17 PM PDT 24
Peak memory	204956 kb
Host	smart-926665ad-62f7-4bda-b89e-78344daec76b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1665531884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1665531884
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1271358771
Short name	T659
Test name
Test status
Simulation time	14070789 ps
CPU time	2.19 seconds
Started	May 23 12:40:32 PM PDT 24
Finished	May 23 12:40:35 PM PDT 24
Peak memory	203284 kb
Host	smart-837f2ddf-8985-4365-af85-361f19ee7fea
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271358771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1271358771
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.324977320
Short name	T675
Test name
Test status
Simulation time	400494199 ps
CPU time	10.86 seconds
Started	May 23 12:40:27 PM PDT 24
Finished	May 23 12:40:39 PM PDT 24
Peak memory	203340 kb
Host	smart-b0592236-2b79-4ccf-9ba3-3f4baa21c1cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=324977320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.324977320
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.2815358400
Short name	T59
Test name
Test status
Simulation time	111544912 ps
CPU time	3.23 seconds
Started	May 23 12:40:24 PM PDT 24
Finished	May 23 12:40:28 PM PDT 24
Peak memory	203252 kb
Host	smart-3634057e-a471-4d5c-9565-4fbe6661a04e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2815358400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2815358400
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1622953806
Short name	T802
Test name
Test status
Simulation time	6788346354 ps
CPU time	35.46 seconds
Started	May 23 12:40:35 PM PDT 24
Finished	May 23 12:41:12 PM PDT 24
Peak memory	203336 kb
Host	smart-8928c50a-e0eb-4c40-950c-6bde03ee5776
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622953806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1622953806
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4037764684
Short name	T866
Test name
Test status
Simulation time	3924797426 ps
CPU time	28.15 seconds
Started	May 23 12:40:26 PM PDT 24
Finished	May 23 12:40:55 PM PDT 24
Peak memory	203328 kb
Host	smart-14314696-0545-4d15-958d-046ac43e48e9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4037764684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4037764684
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2313539379
Short name	T472
Test name
Test status
Simulation time	54139093 ps
CPU time	2.65 seconds
Started	May 23 12:40:29 PM PDT 24
Finished	May 23 12:40:32 PM PDT 24
Peak memory	203192 kb
Host	smart-d58cd499-7b04-4e08-81e6-307e0a2cf6e6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313539379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2313539379
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.4272487838
Short name	T81
Test name
Test status
Simulation time	5181450186 ps
CPU time	76.93 seconds
Started	May 23 12:40:30 PM PDT 24
Finished	May 23 12:41:49 PM PDT 24
Peak memory	205804 kb
Host	smart-5c167bd4-f4d5-40a7-a1a5-9c95e209fbfe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4272487838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4272487838
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1011484289
Short name	T654
Test name
Test status
Simulation time	3947289531 ps
CPU time	78.31 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:41:53 PM PDT 24
Peak memory	205336 kb
Host	smart-dd772315-777f-48d6-91eb-6fc68372cd60
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1011484289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1011484289
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1224515063
Short name	T229
Test name
Test status
Simulation time	4382996223 ps
CPU time	72.47 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:41:47 PM PDT 24
Peak memory	207372 kb
Host	smart-36c1cde4-d4b0-4902-aca2-6f08cd321af2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1224515063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1224515063
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3247733962
Short name	T615
Test name
Test status
Simulation time	1493239124 ps
CPU time	152.44 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:43:08 PM PDT 24
Peak memory	210720 kb
Host	smart-201023a3-5748-4d8c-a7be-2655e82e28da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3247733962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.3247733962
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1398529220
Short name	T801
Test name
Test status
Simulation time	81466441 ps
CPU time	7.81 seconds
Started	May 23 12:40:26 PM PDT 24
Finished	May 23 12:40:35 PM PDT 24
Peak memory	204560 kb
Host	smart-365fe833-e15a-4734-836e-b7e9b7b1b3d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1398529220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1398529220
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1492159330
Short name	T416
Test name
Test status
Simulation time	1599153425 ps
CPU time	48.22 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	205412 kb
Host	smart-5f003dfe-f931-4642-abd2-02e1baa37430
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492159330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1492159330
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2316984718
Short name	T707
Test name
Test status
Simulation time	60912691465 ps
CPU time	395.89 seconds
Started	May 23 12:40:28 PM PDT 24
Finished	May 23 12:47:05 PM PDT 24
Peak memory	211504 kb
Host	smart-6c81ee75-195c-45a2-b477-b746a37720e9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2316984718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.2316984718
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3252908472
Short name	T97
Test name
Test status
Simulation time	62604577 ps
CPU time	3.02 seconds
Started	May 23 12:40:32 PM PDT 24
Finished	May 23 12:40:37 PM PDT 24
Peak memory	203252 kb
Host	smart-4dce4bfa-153c-4d98-91ba-770375273aca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3252908472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3252908472
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.926187571
Short name	T367
Test name
Test status
Simulation time	1037809166 ps
CPU time	18.5 seconds
Started	May 23 12:40:24 PM PDT 24
Finished	May 23 12:40:44 PM PDT 24
Peak memory	203404 kb
Host	smart-5758d35f-79c9-43d2-8733-8ae2d3565b22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=926187571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.926187571
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.3085615158
Short name	T464
Test name
Test status
Simulation time	1808989718 ps
CPU time	40.13 seconds
Started	May 23 12:40:29 PM PDT 24
Finished	May 23 12:41:10 PM PDT 24
Peak memory	211416 kb
Host	smart-fc5de87e-2a57-4cb5-ac2d-edf67c9d37a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085615158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3085615158
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2020362540
Short name	T544
Test name
Test status
Simulation time	112582948869 ps
CPU time	276.24 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:45:11 PM PDT 24
Peak memory	211524 kb
Host	smart-cfd248ad-ee23-4757-8232-1ef3b5336d62
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020362540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2020362540
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1544304517
Short name	T96
Test name
Test status
Simulation time	74121356315 ps
CPU time	295.23 seconds
Started	May 23 12:40:31 PM PDT 24
Finished	May 23 12:45:28 PM PDT 24
Peak memory	205220 kb
Host	smart-781371bd-0323-4f47-a818-591429c9d88a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1544304517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1544304517
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2427155841
Short name	T696
Test name
Test status
Simulation time	245609153 ps
CPU time	11.13 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:40:46 PM PDT 24
Peak memory	204484 kb
Host	smart-35997d33-9e0a-42da-9172-04026c86f204
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427155841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2427155841
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.4175188807
Short name	T92
Test name
Test status
Simulation time	347242894 ps
CPU time	13.96 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:40:48 PM PDT 24
Peak memory	203264 kb
Host	smart-f33c14b6-f439-46a6-9b80-35c32e1e3eea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4175188807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4175188807
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.3156613836
Short name	T611
Test name
Test status
Simulation time	122583494 ps
CPU time	3.27 seconds
Started	May 23 12:40:28 PM PDT 24
Finished	May 23 12:40:33 PM PDT 24
Peak memory	203232 kb
Host	smart-ab21c9cd-86be-4591-8062-779a9f48bb9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3156613836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3156613836
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2512949034
Short name	T311
Test name
Test status
Simulation time	6074559962 ps
CPU time	31.76 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	203336 kb
Host	smart-9fd9e00f-624c-4a3c-b4d2-49ff8ee2dccb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512949034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2512949034
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2529942417
Short name	T274
Test name
Test status
Simulation time	8354751928 ps
CPU time	33.84 seconds
Started	May 23 12:40:31 PM PDT 24
Finished	May 23 12:41:06 PM PDT 24
Peak memory	203264 kb
Host	smart-e0794495-4b68-41c4-b6c4-a120a5ab1ddd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2529942417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2529942417
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.4230845995
Short name	T732
Test name
Test status
Simulation time	31675538 ps
CPU time	2.24 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:40:38 PM PDT 24
Peak memory	203276 kb
Host	smart-17e08053-6f07-47a7-b9b9-0e9b9eadff64
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230845995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.4230845995
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.3872091864
Short name	T106
Test name
Test status
Simulation time	10205047527 ps
CPU time	223.89 seconds
Started	May 23 12:40:24 PM PDT 24
Finished	May 23 12:44:08 PM PDT 24
Peak memory	207192 kb
Host	smart-3b352dc7-d360-4874-9066-318dfaac3777
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872091864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3872091864
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3473747847
Short name	T716
Test name
Test status
Simulation time	1980965774 ps
CPU time	95.21 seconds
Started	May 23 12:40:35 PM PDT 24
Finished	May 23 12:42:12 PM PDT 24
Peak memory	211428 kb
Host	smart-0faf0594-a90b-4fb8-a0a8-c1ce03438d78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3473747847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3473747847
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.551441170
Short name	T390
Test name
Test status
Simulation time	90233112 ps
CPU time	59.23 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:41:33 PM PDT 24
Peak memory	206260 kb
Host	smart-43411aa0-218c-4895-93e8-c7f8c659a866
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=551441170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.551441170
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.112833484
Short name	T26
Test name
Test status
Simulation time	1414178546 ps
CPU time	237.81 seconds
Started	May 23 12:40:38 PM PDT 24
Finished	May 23 12:44:37 PM PDT 24
Peak memory	211152 kb
Host	smart-1d6f552c-79fe-45fa-9387-4059ab77f91e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=112833484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_res et_error.112833484
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2665321190
Short name	T704
Test name
Test status
Simulation time	162025967 ps
CPU time	20.01 seconds
Started	May 23 12:40:36 PM PDT 24
Finished	May 23 12:40:57 PM PDT 24
Peak memory	211416 kb
Host	smart-12711145-b342-4dd0-b7ba-53854610186d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2665321190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2665321190
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2428491706
Short name	T759
Test name
Test status
Simulation time	28735657 ps
CPU time	3 seconds
Started	May 23 12:40:38 PM PDT 24
Finished	May 23 12:40:42 PM PDT 24
Peak memory	203412 kb
Host	smart-034f56ba-7b9f-4ff1-9066-54383ce7b71f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2428491706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2428491706
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2377191071
Short name	T362
Test name
Test status
Simulation time	79206166078 ps
CPU time	385.3 seconds
Started	May 23 12:40:35 PM PDT 24
Finished	May 23 12:47:02 PM PDT 24
Peak memory	205940 kb
Host	smart-79d6ea2d-303b-4a11-98bb-a1c844abd618
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2377191071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2377191071
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2714599872
Short name	T268
Test name
Test status
Simulation time	54278779 ps
CPU time	7.41 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:40:43 PM PDT 24
Peak memory	203524 kb
Host	smart-8dc95156-5d4b-4d0c-83a0-b37c5ced9178
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2714599872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2714599872
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.1336633535
Short name	T665
Test name
Test status
Simulation time	273592485 ps
CPU time	10.08 seconds
Started	May 23 12:40:37 PM PDT 24
Finished	May 23 12:40:48 PM PDT 24
Peak memory	203336 kb
Host	smart-445186c5-073e-4d39-9010-5e0d89a9e2d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1336633535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1336633535
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.4201235011
Short name	T304
Test name
Test status
Simulation time	172937978 ps
CPU time	14.44 seconds
Started	May 23 12:40:31 PM PDT 24
Finished	May 23 12:40:46 PM PDT 24
Peak memory	204416 kb
Host	smart-c3869618-73fa-46ae-bda5-81beefde9a7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4201235011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.4201235011
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.170262643
Short name	T156
Test name
Test status
Simulation time	125785890388 ps
CPU time	257.99 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:44:54 PM PDT 24
Peak memory	205000 kb
Host	smart-2a6a816b-52d2-4950-99f8-08170329e70d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=170262643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.170262643
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.4107359437
Short name	T876
Test name
Test status
Simulation time	115790159886 ps
CPU time	257.48 seconds
Started	May 23 12:40:32 PM PDT 24
Finished	May 23 12:44:51 PM PDT 24
Peak memory	204644 kb
Host	smart-080a02ec-5c83-43e3-839b-5b1334404b74
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4107359437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.4107359437
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3014689782
Short name	T804
Test name
Test status
Simulation time	298764016 ps
CPU time	21.03 seconds
Started	May 23 12:40:27 PM PDT 24
Finished	May 23 12:40:49 PM PDT 24
Peak memory	211468 kb
Host	smart-83866327-537f-453c-94f7-ff0c62f0731b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014689782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3014689782
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.1638512034
Short name	T877
Test name
Test status
Simulation time	60859470 ps
CPU time	4.49 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:40:39 PM PDT 24
Peak memory	203288 kb
Host	smart-998c34d7-4e70-46a6-9b2f-60c2c3e04884
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1638512034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1638512034
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.3085690696
Short name	T609
Test name
Test status
Simulation time	81461319 ps
CPU time	2.45 seconds
Started	May 23 12:40:37 PM PDT 24
Finished	May 23 12:40:40 PM PDT 24
Peak memory	203320 kb
Host	smart-a556b030-336f-4820-af13-9e7d24bbd4de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085690696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3085690696
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.650384167
Short name	T150
Test name
Test status
Simulation time	8149806842 ps
CPU time	27.63 seconds
Started	May 23 12:40:38 PM PDT 24
Finished	May 23 12:41:07 PM PDT 24
Peak memory	203376 kb
Host	smart-46f560a4-fbb8-48a5-8ccb-bed7af15e841
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=650384167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.650384167
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1654913873
Short name	T227
Test name
Test status
Simulation time	18014572517 ps
CPU time	40.25 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:41:15 PM PDT 24
Peak memory	203348 kb
Host	smart-1b5f9ecd-29e7-4a17-b963-e3f3a63fc71f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1654913873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1654913873
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1436730855
Short name	T785
Test name
Test status
Simulation time	34182466 ps
CPU time	2.08 seconds
Started	May 23 12:40:37 PM PDT 24
Finished	May 23 12:40:41 PM PDT 24
Peak memory	203324 kb
Host	smart-c14168e6-c744-4e01-b849-87fd888709d6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436730855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1436730855
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.812865717
Short name	T355
Test name
Test status
Simulation time	3136689982 ps
CPU time	78.1 seconds
Started	May 23 12:40:37 PM PDT 24
Finished	May 23 12:41:57 PM PDT 24
Peak memory	211588 kb
Host	smart-60c9bccf-99cb-4c2a-9b5d-8b0b15990a16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812865717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.812865717
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1916424370
Short name	T576
Test name
Test status
Simulation time	4558133309 ps
CPU time	110.44 seconds
Started	May 23 12:40:28 PM PDT 24
Finished	May 23 12:42:20 PM PDT 24
Peak memory	205552 kb
Host	smart-80779a4d-c129-4a71-bb0d-86bcfffc9672
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1916424370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1916424370
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1497180010
Short name	T39
Test name
Test status
Simulation time	3322010923 ps
CPU time	234.32 seconds
Started	May 23 12:40:25 PM PDT 24
Finished	May 23 12:44:21 PM PDT 24
Peak memory	209424 kb
Host	smart-9ca8bc34-9470-458f-b2cf-8695029ee284
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1497180010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1497180010
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1617580109
Short name	T233
Test name
Test status
Simulation time	8625111281 ps
CPU time	301.82 seconds
Started	May 23 12:40:35 PM PDT 24
Finished	May 23 12:45:39 PM PDT 24
Peak memory	219700 kb
Host	smart-4a8e8f69-bb63-4121-b278-ae2b2b6c33ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1617580109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.1617580109
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1024356108
Short name	T800
Test name
Test status
Simulation time	336092741 ps
CPU time	16.2 seconds
Started	May 23 12:40:37 PM PDT 24
Finished	May 23 12:40:55 PM PDT 24
Peak memory	204936 kb
Host	smart-3e2b6e34-d6b1-4461-bf9e-6dd346c2762f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1024356108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1024356108
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3166760497
Short name	T74
Test name
Test status
Simulation time	4756930726 ps
CPU time	71.45 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:41:58 PM PDT 24
Peak memory	205688 kb
Host	smart-63088faa-30b8-4e0f-952b-77f21416db2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3166760497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3166760497
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.231383251
Short name	T583
Test name
Test status
Simulation time	140416282965 ps
CPU time	343.22 seconds
Started	May 23 12:40:42 PM PDT 24
Finished	May 23 12:46:27 PM PDT 24
Peak memory	206496 kb
Host	smart-2df46ff0-e1f9-4245-9137-b6acd2a16e1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=231383251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo w_rsp.231383251
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.200574545
Short name	T523
Test name
Test status
Simulation time	74764378 ps
CPU time	10.39 seconds
Started	May 23 12:40:47 PM PDT 24
Finished	May 23 12:41:00 PM PDT 24
Peak memory	203516 kb
Host	smart-3e295377-14cf-4c94-92b7-1acfba499311
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=200574545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.200574545
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.2549591978
Short name	T766
Test name
Test status
Simulation time	84374210 ps
CPU time	8.57 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:40:53 PM PDT 24
Peak memory	203300 kb
Host	smart-7d0433f2-3ee3-4b1d-9a70-065b2009ba7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2549591978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2549591978
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.1963259109
Short name	T19
Test name
Test status
Simulation time	1191743818 ps
CPU time	16.68 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:40:53 PM PDT 24
Peak memory	204420 kb
Host	smart-5e97f83b-229d-4ed8-b9d8-4ba2fb04bfc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1963259109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1963259109
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.214675356
Short name	T205
Test name
Test status
Simulation time	97070168673 ps
CPU time	224.76 seconds
Started	May 23 12:40:35 PM PDT 24
Finished	May 23 12:44:22 PM PDT 24
Peak memory	205064 kb
Host	smart-6a35b83e-3680-4c40-a4aa-7c0c13a50f69
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=214675356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.214675356
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1549455925
Short name	T661
Test name
Test status
Simulation time	35856180949 ps
CPU time	238.89 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:44:43 PM PDT 24
Peak memory	205196 kb
Host	smart-8b584c30-5655-4176-9494-6be5c3c0a772
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1549455925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1549455925
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2018626176
Short name	T24
Test name
Test status
Simulation time	36905560 ps
CPU time	3.27 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:40:38 PM PDT 24
Peak memory	203876 kb
Host	smart-593da128-e0da-4c62-ab6c-11ab39b043f6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018626176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2018626176
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.1794849811
Short name	T146
Test name
Test status
Simulation time	215936005 ps
CPU time	10.71 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:40:55 PM PDT 24
Peak memory	203244 kb
Host	smart-e56015c8-8634-49a2-b833-9076e2809f53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1794849811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1794849811
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.2934380550
Short name	T391
Test name
Test status
Simulation time	133251340 ps
CPU time	2.34 seconds
Started	May 23 12:40:35 PM PDT 24
Finished	May 23 12:40:39 PM PDT 24
Peak memory	203236 kb
Host	smart-6863c83e-b148-462b-8c98-1eed75d6bb2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2934380550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2934380550
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2595217539
Short name	T344
Test name
Test status
Simulation time	29888107921 ps
CPU time	49.4 seconds
Started	May 23 12:40:34 PM PDT 24
Finished	May 23 12:41:25 PM PDT 24
Peak memory	203340 kb
Host	smart-8e8885e3-9c55-4401-8bf0-d6b348c4306c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595217539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2595217539
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1035337329
Short name	T364
Test name
Test status
Simulation time	6589449722 ps
CPU time	26.42 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:41:01 PM PDT 24
Peak memory	203340 kb
Host	smart-c3141669-3cc9-4ad9-b4fd-7daa10390c60
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1035337329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1035337329
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2040103583
Short name	T444
Test name
Test status
Simulation time	30787307 ps
CPU time	2.24 seconds
Started	May 23 12:40:33 PM PDT 24
Finished	May 23 12:40:37 PM PDT 24
Peak memory	203280 kb
Host	smart-1adb873a-04c2-4594-a7d9-ac51e7b1cd53
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040103583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2040103583
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.4207985081
Short name	T860
Test name
Test status
Simulation time	13883071821 ps
CPU time	206.67 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:44:15 PM PDT 24
Peak memory	210056 kb
Host	smart-45850367-16d9-43d4-b502-c7130243d173
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4207985081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4207985081
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3771847457
Short name	T780
Test name
Test status
Simulation time	1438900520 ps
CPU time	105.16 seconds
Started	May 23 12:40:42 PM PDT 24
Finished	May 23 12:42:28 PM PDT 24
Peak memory	207536 kb
Host	smart-14b0a9d5-109d-4720-bb68-7ad31d455504
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3771847457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3771847457
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.764031894
Short name	T586
Test name
Test status
Simulation time	4532177868 ps
CPU time	351.66 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:46:37 PM PDT 24
Peak memory	210444 kb
Host	smart-f2e220a8-57e2-4c1b-bfcd-0102c4999d8a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=764031894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand _reset.764031894
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2550074028
Short name	T241
Test name
Test status
Simulation time	4404153244 ps
CPU time	276.03 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:45:23 PM PDT 24
Peak memory	219720 kb
Host	smart-42e46e81-6574-4ccb-8ab0-d01e2543a07a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2550074028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2550074028
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3716027428
Short name	T53
Test name
Test status
Simulation time	4415820142 ps
CPU time	31.79 seconds
Started	May 23 12:40:42 PM PDT 24
Finished	May 23 12:41:15 PM PDT 24
Peak memory	205448 kb
Host	smart-ba953ef1-0d35-4466-a002-241c42e4a938
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3716027428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3716027428
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1630047125
Short name	T778
Test name
Test status
Simulation time	312928189 ps
CPU time	31.34 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:29 PM PDT 24
Peak memory	211444 kb
Host	smart-8f5fd9aa-48bd-457d-beb3-691e74f675ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1630047125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1630047125
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.4256027861
Short name	T371
Test name
Test status
Simulation time	130848973983 ps
CPU time	402.67 seconds
Started	May 23 12:37:54 PM PDT 24
Finished	May 23 12:44:37 PM PDT 24
Peak memory	206156 kb
Host	smart-df477207-9de4-4473-aa37-a3bca0184e51
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4256027861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.4256027861
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.117098385
Short name	T243
Test name
Test status
Simulation time	1133754730 ps
CPU time	24.44 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:38:24 PM PDT 24
Peak memory	203276 kb
Host	smart-149cb7d0-dc76-4f6a-a097-3fbc3b5500cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117098385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.117098385
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.2925237231
Short name	T401
Test name
Test status
Simulation time	92255193 ps
CPU time	8.81 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:07 PM PDT 24
Peak memory	203288 kb
Host	smart-9379713d-8bd3-49f3-939f-35b25fe5d883
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2925237231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2925237231
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.3426925613
Short name	T400
Test name
Test status
Simulation time	46450909 ps
CPU time	5.96 seconds
Started	May 23 12:37:55 PM PDT 24
Finished	May 23 12:38:03 PM PDT 24
Peak memory	204432 kb
Host	smart-a890612a-357c-47d8-a37e-4043ea522660
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3426925613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3426925613
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1898790994
Short name	T603
Test name
Test status
Simulation time	14836941689 ps
CPU time	41.09 seconds
Started	May 23 12:37:59 PM PDT 24
Finished	May 23 12:38:43 PM PDT 24
Peak memory	204720 kb
Host	smart-96b231e8-1d86-4420-b21a-e9387b1730c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898790994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1898790994
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3755816225
Short name	T277
Test name
Test status
Simulation time	46248456401 ps
CPU time	171.05 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:40:52 PM PDT 24
Peak memory	204784 kb
Host	smart-6b9083f3-032c-403d-9246-daaa7500bb11
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3755816225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3755816225
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.316586903
Short name	T439
Test name
Test status
Simulation time	175828932 ps
CPU time	18.62 seconds
Started	May 23 12:37:55 PM PDT 24
Finished	May 23 12:38:14 PM PDT 24
Peak memory	204612 kb
Host	smart-ed8f8133-601b-4f85-9bb9-96f3dfd05915
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316586903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.316586903
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.4201519100
Short name	T590
Test name
Test status
Simulation time	1133100317 ps
CPU time	29.31 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:38:28 PM PDT 24
Peak memory	203308 kb
Host	smart-e4d60465-22ba-45a2-8c18-d7696f31197c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4201519100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4201519100
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.2820001580
Short name	T191
Test name
Test status
Simulation time	64656846 ps
CPU time	2.34 seconds
Started	May 23 12:37:55 PM PDT 24
Finished	May 23 12:37:59 PM PDT 24
Peak memory	203232 kb
Host	smart-483c818e-8bfa-4e7c-a36b-cb78e7ecdfe9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2820001580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2820001580
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4185689031
Short name	T744
Test name
Test status
Simulation time	9214359644 ps
CPU time	30.61 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:29 PM PDT 24
Peak memory	203296 kb
Host	smart-05c57744-0934-4888-8c3f-d145ed8e60b2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185689031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4185689031
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2735947019
Short name	T674
Test name
Test status
Simulation time	7533468203 ps
CPU time	34.66 seconds
Started	May 23 12:37:59 PM PDT 24
Finished	May 23 12:38:36 PM PDT 24
Peak memory	203320 kb
Host	smart-9f8e88b9-30fd-4619-b1f6-cc80dc93e722
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2735947019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2735947019
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2918527496
Short name	T448
Test name
Test status
Simulation time	42440342 ps
CPU time	2.05 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:00 PM PDT 24
Peak memory	203252 kb
Host	smart-10a16188-df20-443a-84e5-85067a1a4537
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918527496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2918527496
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.1354289706
Short name	T533
Test name
Test status
Simulation time	1786479430 ps
CPU time	197.55 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:41:17 PM PDT 24
Peak memory	209592 kb
Host	smart-5debd97e-1575-419c-a155-0b2a5c05e6e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1354289706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1354289706
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1196811042
Short name	T616
Test name
Test status
Simulation time	793417349 ps
CPU time	61.61 seconds
Started	May 23 12:37:55 PM PDT 24
Finished	May 23 12:38:57 PM PDT 24
Peak memory	211496 kb
Host	smart-20a0a331-c605-499a-b574-e6fafe433148
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1196811042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1196811042
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4215752758
Short name	T178
Test name
Test status
Simulation time	1633864192 ps
CPU time	228.91 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:41:48 PM PDT 24
Peak memory	209208 kb
Host	smart-e97ee4e5-96ef-4dbc-8f5b-7d94c4c6a8a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4215752758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.4215752758
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3962434473
Short name	T821
Test name
Test status
Simulation time	738945950 ps
CPU time	217.4 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:41:38 PM PDT 24
Peak memory	219520 kb
Host	smart-3599c397-227d-4bc1-83b7-c87fe7c97250
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3962434473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.3962434473
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2328720964
Short name	T503
Test name
Test status
Simulation time	1831191510 ps
CPU time	31.49 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:33 PM PDT 24
Peak memory	211540 kb
Host	smart-30e12c33-0051-4277-be38-02e1144a1395
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2328720964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2328720964
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4033206204
Short name	T108
Test name
Test status
Simulation time	1455504949 ps
CPU time	42.54 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:41:27 PM PDT 24
Peak memory	205932 kb
Host	smart-9e458098-1dd1-41c1-8774-49634f429de2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4033206204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4033206204
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3701236507
Short name	T228
Test name
Test status
Simulation time	42591933851 ps
CPU time	203.96 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:44:09 PM PDT 24
Peak memory	206284 kb
Host	smart-29c50cb5-2e1e-4760-9ff6-c6182ffd7111
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3701236507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3701236507
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2218178921
Short name	T263
Test name
Test status
Simulation time	652083470 ps
CPU time	22.97 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	203636 kb
Host	smart-367d7b72-becb-426a-8e77-87ca962f60a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2218178921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2218178921
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.3353536428
Short name	T443
Test name
Test status
Simulation time	192999065 ps
CPU time	15.62 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:41:02 PM PDT 24
Peak memory	203220 kb
Host	smart-27f9fe67-74a6-4f34-9cb7-40002f0c2931
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3353536428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3353536428
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.3358817112
Short name	T51
Test name
Test status
Simulation time	237675497 ps
CPU time	7.32 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:40:56 PM PDT 24
Peak memory	204316 kb
Host	smart-9491bcd3-9615-4def-be17-886a026860dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3358817112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3358817112
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.480449523
Short name	T94
Test name
Test status
Simulation time	86139690235 ps
CPU time	237.32 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:44:42 PM PDT 24
Peak memory	204648 kb
Host	smart-b90113e7-0879-4f53-b69e-1a69fdb151d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=480449523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.480449523
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3726915514
Short name	T302
Test name
Test status
Simulation time	16083163420 ps
CPU time	142.79 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:43:07 PM PDT 24
Peak memory	211620 kb
Host	smart-d5261fed-a7c0-42a3-ba6a-a986d8fc62a8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3726915514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3726915514
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.4147558804
Short name	T327
Test name
Test status
Simulation time	143315071 ps
CPU time	13.48 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:41:01 PM PDT 24
Peak memory	211464 kb
Host	smart-d5a15bde-1591-40de-8063-60beb2b98ec1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147558804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.4147558804
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.3630326042
Short name	T607
Test name
Test status
Simulation time	1126759908 ps
CPU time	16.45 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:41:04 PM PDT 24
Peak memory	203976 kb
Host	smart-edf4fc7c-059a-4581-80f0-07fd03319aab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3630326042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3630326042
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.3901292081
Short name	T384
Test name
Test status
Simulation time	179667346 ps
CPU time	3.7 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:40:48 PM PDT 24
Peak memory	203452 kb
Host	smart-d097980a-4991-4317-950d-c3a9442e95ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3901292081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3901292081
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3198603874
Short name	T440
Test name
Test status
Simulation time	7592627910 ps
CPU time	27.45 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:41:14 PM PDT 24
Peak memory	203324 kb
Host	smart-344fbe0e-c5e3-465f-861c-cdb38540b74c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198603874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3198603874
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2830351779
Short name	T67
Test name
Test status
Simulation time	2345580768 ps
CPU time	21 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:41:09 PM PDT 24
Peak memory	203348 kb
Host	smart-80810efe-b8b2-449d-8966-570dfc5e2f35
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2830351779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2830351779
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.4142529334
Short name	T434
Test name
Test status
Simulation time	31950952 ps
CPU time	2.8 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:40:49 PM PDT 24
Peak memory	203268 kb
Host	smart-f8c9d831-fb57-43cb-8cd5-425f9a20fe27
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142529334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.4142529334
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.1735261988
Short name	T516
Test name
Test status
Simulation time	13476932450 ps
CPU time	267.34 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:45:16 PM PDT 24
Peak memory	207008 kb
Host	smart-d75a8c74-eda1-45e7-8e24-2e60bcc5c92a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1735261988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1735261988
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.677463161
Short name	T411
Test name
Test status
Simulation time	8137721861 ps
CPU time	129.84 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:42:55 PM PDT 24
Peak memory	205232 kb
Host	smart-7dfad2c2-f882-4e5a-8d95-5ea08eb4b5aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=677463161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.677463161
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1841312627
Short name	T862
Test name
Test status
Simulation time	72245676 ps
CPU time	54.6 seconds
Started	May 23 12:40:42 PM PDT 24
Finished	May 23 12:41:37 PM PDT 24
Peak memory	206800 kb
Host	smart-358f6110-ff8c-4d5e-8f33-9847e5034a20
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1841312627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.1841312627
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2584687897
Short name	T478
Test name
Test status
Simulation time	117077899 ps
CPU time	21.35 seconds
Started	May 23 12:40:41 PM PDT 24
Finished	May 23 12:41:03 PM PDT 24
Peak memory	205488 kb
Host	smart-c53a09e3-d157-4f4a-9692-cbb2fd99adde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2584687897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.2584687897
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.641881135
Short name	T129
Test name
Test status
Simulation time	3272195213 ps
CPU time	27.6 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:41:15 PM PDT 24
Peak memory	204708 kb
Host	smart-4a942580-1142-4974-a229-f9f6c92b3f3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=641881135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.641881135
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1663265710
Short name	T93
Test name
Test status
Simulation time	121895870 ps
CPU time	13.45 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:41:00 PM PDT 24
Peak memory	204320 kb
Host	smart-ae381533-5073-415c-a7d4-230f7896776c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1663265710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1663265710
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2349753663
Short name	T170
Test name
Test status
Simulation time	9597781722 ps
CPU time	36.31 seconds
Started	May 23 12:40:42 PM PDT 24
Finished	May 23 12:41:20 PM PDT 24
Peak memory	203740 kb
Host	smart-fa2b0b1a-9161-4ddc-931b-b6a8da77eb90
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2349753663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.2349753663
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.14943555
Short name	T567
Test name
Test status
Simulation time	5702950070 ps
CPU time	29.14 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:41:17 PM PDT 24
Peak memory	203984 kb
Host	smart-b515ea5d-0ecb-4b2e-8fbd-c5abe7f6269f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=14943555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.14943555
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.2169324716
Short name	T577
Test name
Test status
Simulation time	1998297482 ps
CPU time	32.07 seconds
Started	May 23 12:40:43 PM PDT 24
Finished	May 23 12:41:16 PM PDT 24
Peak memory	203288 kb
Host	smart-11e3a7d6-47f0-446d-82af-0804160daed5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2169324716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2169324716
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.2442752175
Short name	T684
Test name
Test status
Simulation time	738603290 ps
CPU time	27.04 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:41:12 PM PDT 24
Peak memory	211532 kb
Host	smart-f790730d-0afc-4062-ba3a-149f8af429f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2442752175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2442752175
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1783696539
Short name	T137
Test name
Test status
Simulation time	20773580350 ps
CPU time	111.56 seconds
Started	May 23 12:40:42 PM PDT 24
Finished	May 23 12:42:35 PM PDT 24
Peak memory	205012 kb
Host	smart-95cbdca5-da36-4c1e-983b-cb35269a3745
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783696539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1783696539
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.972102510
Short name	T215
Test name
Test status
Simulation time	10152062631 ps
CPU time	80.74 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:42:09 PM PDT 24
Peak memory	211496 kb
Host	smart-83e9f500-e94d-46af-be56-7a44c3a8b5ec
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=972102510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.972102510
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3838023660
Short name	T762
Test name
Test status
Simulation time	264460570 ps
CPU time	28.36 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:41:14 PM PDT 24
Peak memory	204832 kb
Host	smart-caf185a5-b8ad-450b-b3c9-fef3be596162
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838023660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3838023660
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.164000563
Short name	T418
Test name
Test status
Simulation time	98766143 ps
CPU time	6.41 seconds
Started	May 23 12:40:44 PM PDT 24
Finished	May 23 12:40:52 PM PDT 24
Peak memory	203776 kb
Host	smart-c4a24542-542c-4fb7-82ca-2c892833e4e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=164000563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.164000563
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.1395436627
Short name	T531
Test name
Test status
Simulation time	38998863 ps
CPU time	2.45 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:40:50 PM PDT 24
Peak memory	203236 kb
Host	smart-5b5ad0d4-6d9a-488a-a25f-a13f83d4aa1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1395436627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1395436627
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.211445856
Short name	T502
Test name
Test status
Simulation time	32987029180 ps
CPU time	50.9 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:41:39 PM PDT 24
Peak memory	203272 kb
Host	smart-66ef7ff4-1bc5-4a99-bdd0-b77933bd71e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=211445856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.211445856
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1797447520
Short name	T593
Test name
Test status
Simulation time	11671483284 ps
CPU time	38.99 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:41:27 PM PDT 24
Peak memory	203280 kb
Host	smart-3f117f11-ec5a-4d8f-94b2-338a9320e8e9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1797447520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1797447520
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1408269188
Short name	T276
Test name
Test status
Simulation time	87736262 ps
CPU time	2.44 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:40:50 PM PDT 24
Peak memory	203248 kb
Host	smart-7ae70a31-d171-4b3e-ba3a-ae86355af6bc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408269188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1408269188
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.3146876693
Short name	T695
Test name
Test status
Simulation time	5743875707 ps
CPU time	186.4 seconds
Started	May 23 12:40:48 PM PDT 24
Finished	May 23 12:43:56 PM PDT 24
Peak memory	208460 kb
Host	smart-8dd6e197-7dd3-402d-94d5-1d23862905f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3146876693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3146876693
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2668529014
Short name	T837
Test name
Test status
Simulation time	3117061468 ps
CPU time	60.94 seconds
Started	May 23 12:40:48 PM PDT 24
Finished	May 23 12:41:51 PM PDT 24
Peak memory	204492 kb
Host	smart-513e7ef4-0b15-404b-a9bb-2ffd54b78433
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2668529014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2668529014
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1006872413
Short name	T546
Test name
Test status
Simulation time	3927766679 ps
CPU time	593.4 seconds
Started	May 23 12:40:49 PM PDT 24
Finished	May 23 12:50:44 PM PDT 24
Peak memory	208424 kb
Host	smart-e2ac9b81-44a7-429a-8621-775a4fe64380
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1006872413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1006872413
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.480502207
Short name	T454
Test name
Test status
Simulation time	1240021515 ps
CPU time	217.33 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:44:24 PM PDT 24
Peak memory	219668 kb
Host	smart-b6fca5a4-70f8-4a56-a0b0-25925ac75007
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=480502207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.480502207
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1796088651
Short name	T700
Test name
Test status
Simulation time	21750187 ps
CPU time	3.17 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:40:50 PM PDT 24
Peak memory	204336 kb
Host	smart-9d5a2fbc-8806-4400-9677-2026966be8c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1796088651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1796088651
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2957988615
Short name	T171
Test name
Test status
Simulation time	727450346 ps
CPU time	34.44 seconds
Started	May 23 12:41:03 PM PDT 24
Finished	May 23 12:41:41 PM PDT 24
Peak memory	204896 kb
Host	smart-207a00ed-ba53-4252-8118-2277da24123f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2957988615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2957988615
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.791947305
Short name	T206
Test name
Test status
Simulation time	239263343097 ps
CPU time	686.71 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:52:29 PM PDT 24
Peak memory	207412 kb
Host	smart-5a2d9bef-f54a-4b87-b6ce-2ac7f37b107b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=791947305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo w_rsp.791947305
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3878955123
Short name	T872
Test name
Test status
Simulation time	95640360 ps
CPU time	8.12 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:13 PM PDT 24
Peak memory	203568 kb
Host	smart-b9f77acd-d904-44f7-a8a4-1cb1f13e143c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3878955123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3878955123
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.1976646876
Short name	T610
Test name
Test status
Simulation time	657381346 ps
CPU time	15.89 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:19 PM PDT 24
Peak memory	203388 kb
Host	smart-43efc714-b553-4308-ac5e-c550dda8976d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976646876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1976646876
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.3247400614
Short name	T814
Test name
Test status
Simulation time	1189592276 ps
CPU time	10.09 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:40:58 PM PDT 24
Peak memory	204308 kb
Host	smart-63215f39-495c-4193-8626-5b6540b6d91a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3247400614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3247400614
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1510060195
Short name	T83
Test name
Test status
Simulation time	214996712644 ps
CPU time	278.67 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:45:41 PM PDT 24
Peak memory	211536 kb
Host	smart-d447a0b8-9ca7-49de-aa6a-5384957f47cb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510060195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1510060195
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2241807207
Short name	T82
Test name
Test status
Simulation time	37617215159 ps
CPU time	244.04 seconds
Started	May 23 12:40:58 PM PDT 24
Finished	May 23 12:45:04 PM PDT 24
Peak memory	205184 kb
Host	smart-b8c9d11b-88f8-4e05-89ef-811e7a0a13a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2241807207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2241807207
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.784647524
Short name	T484
Test name
Test status
Simulation time	163773941 ps
CPU time	19.31 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:41:07 PM PDT 24
Peak memory	204700 kb
Host	smart-8e870f7d-65fd-433a-b189-c777ad47490e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784647524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.784647524
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.3811876035
Short name	T209
Test name
Test status
Simulation time	199870005 ps
CPU time	11.98 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:15 PM PDT 24
Peak memory	203280 kb
Host	smart-e46fe538-6423-4b54-ba14-987bad43ebaf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3811876035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3811876035
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.2549379191
Short name	T475
Test name
Test status
Simulation time	172715175 ps
CPU time	2.73 seconds
Started	May 23 12:40:45 PM PDT 24
Finished	May 23 12:40:50 PM PDT 24
Peak memory	203236 kb
Host	smart-9d33c886-eecc-431f-adaf-e407db8757bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2549379191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2549379191
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.112569810
Short name	T361
Test name
Test status
Simulation time	29825798391 ps
CPU time	41.68 seconds
Started	May 23 12:40:49 PM PDT 24
Finished	May 23 12:41:32 PM PDT 24
Peak memory	203332 kb
Host	smart-7bab56f5-8a2f-4275-b28a-b4697e7ebe4a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112569810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.112569810
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1249227771
Short name	T130
Test name
Test status
Simulation time	5201793072 ps
CPU time	16.83 seconds
Started	May 23 12:40:46 PM PDT 24
Finished	May 23 12:41:05 PM PDT 24
Peak memory	203340 kb
Host	smart-8e00b05b-0515-4f6e-aca3-c09b28d204e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1249227771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1249227771
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.275912566
Short name	T817
Test name
Test status
Simulation time	27687913 ps
CPU time	2.22 seconds
Started	May 23 12:40:49 PM PDT 24
Finished	May 23 12:40:53 PM PDT 24
Peak memory	203276 kb
Host	smart-e3c46cf6-94a9-4e0e-a7b3-5aaaf77de420
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275912566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.275912566
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.1173317150
Short name	T822
Test name
Test status
Simulation time	435376191 ps
CPU time	57.71 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:42:02 PM PDT 24
Peak memory	211436 kb
Host	smart-0b5c2739-bb83-4a42-861e-76c92e3cf3f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173317150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1173317150
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3688703972
Short name	T854
Test name
Test status
Simulation time	10817866616 ps
CPU time	148.3 seconds
Started	May 23 12:40:57 PM PDT 24
Finished	May 23 12:43:28 PM PDT 24
Peak memory	206976 kb
Host	smart-a8eb3ad0-c171-4129-9298-08a6eb0623cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3688703972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3688703972
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1058432567
Short name	T491
Test name
Test status
Simulation time	3782913728 ps
CPU time	315.03 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:46:20 PM PDT 24
Peak memory	208520 kb
Host	smart-7e0eacbd-4845-4807-a42e-ae127ce8510f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1058432567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1058432567
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.8285277
Short name	T588
Test name
Test status
Simulation time	12210178493 ps
CPU time	401.87 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:47:47 PM PDT 24
Peak memory	219744 kb
Host	smart-93ad395d-96f8-4cff-b596-d1ba7274da18
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=8285277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset _error.8285277
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1399667049
Short name	T742
Test name
Test status
Simulation time	88259204 ps
CPU time	3.6 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	204488 kb
Host	smart-b7760a6b-bd36-4154-b80d-e29f98eedce8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399667049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1399667049
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1090871467
Short name	T686
Test name
Test status
Simulation time	1046115070 ps
CPU time	13.9 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:19 PM PDT 24
Peak memory	203856 kb
Host	smart-bb6b1c01-7180-4a65-a330-f0d190bf0360
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1090871467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1090871467
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1224267593
Short name	T180
Test name
Test status
Simulation time	17776374598 ps
CPU time	67.03 seconds
Started	May 23 12:40:58 PM PDT 24
Finished	May 23 12:42:07 PM PDT 24
Peak memory	204476 kb
Host	smart-780b6037-d542-44c1-89e4-4e686e612a22
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1224267593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1224267593
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3893617496
Short name	T528
Test name
Test status
Simulation time	91549069 ps
CPU time	11.18 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:14 PM PDT 24
Peak memory	203860 kb
Host	smart-ef95a6bc-9126-4a28-b573-9e5897fbf484
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3893617496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3893617496
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.2953530766
Short name	T809
Test name
Test status
Simulation time	553676344 ps
CPU time	6.98 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:12 PM PDT 24
Peak memory	203232 kb
Host	smart-32dea40b-5997-46f5-8470-21bf6712affb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2953530766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2953530766
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.2894765953
Short name	T324
Test name
Test status
Simulation time	372305259 ps
CPU time	6.43 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:09 PM PDT 24
Peak memory	211436 kb
Host	smart-1387e9fc-c805-4119-ba6a-1f32ca49303f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2894765953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2894765953
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1197262403
Short name	T883
Test name
Test status
Simulation time	54335116515 ps
CPU time	201.86 seconds
Started	May 23 12:40:57 PM PDT 24
Finished	May 23 12:44:21 PM PDT 24
Peak memory	205044 kb
Host	smart-f89946bf-7cbe-4008-b3ba-33d3fb40d567
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197262403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1197262403
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3649605869
Short name	T279
Test name
Test status
Simulation time	4689776271 ps
CPU time	24.25 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:29 PM PDT 24
Peak memory	204436 kb
Host	smart-296e3817-58a0-415a-8732-482f7f171114
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3649605869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3649605869
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1795763566
Short name	T271
Test name
Test status
Simulation time	751074338 ps
CPU time	18.49 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	204608 kb
Host	smart-75267f53-4d93-4fcd-9221-3e60cde41e0c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795763566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1795763566
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.751071355
Short name	T699
Test name
Test status
Simulation time	1115126657 ps
CPU time	12.94 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:17 PM PDT 24
Peak memory	211568 kb
Host	smart-81fb31c7-8ff2-49d7-a212-c98e7ed6809e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=751071355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.751071355
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.1930673702
Short name	T321
Test name
Test status
Simulation time	328539722 ps
CPU time	3.07 seconds
Started	May 23 12:41:05 PM PDT 24
Finished	May 23 12:41:11 PM PDT 24
Peak memory	203236 kb
Host	smart-196fa658-d1a4-430d-a857-d24717cec866
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1930673702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1930673702
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2682990487
Short name	T869
Test name
Test status
Simulation time	6119307858 ps
CPU time	29.56 seconds
Started	May 23 12:41:06 PM PDT 24
Finished	May 23 12:41:37 PM PDT 24
Peak memory	203308 kb
Host	smart-19313e39-6ca0-4c6a-9a25-946474ce34db
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682990487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2682990487
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2891538734
Short name	T679
Test name
Test status
Simulation time	10964516087 ps
CPU time	34.9 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:38 PM PDT 24
Peak memory	203336 kb
Host	smart-f9938a07-aefd-48fe-8e3c-ecdd7fc80621
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2891538734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2891538734
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.641860526
Short name	T751
Test name
Test status
Simulation time	46482910 ps
CPU time	2.44 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:07 PM PDT 24
Peak memory	203220 kb
Host	smart-a0275f10-82cc-49a8-a84e-d3194c9e5528
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641860526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.641860526
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.3976871700
Short name	T467
Test name
Test status
Simulation time	6607417835 ps
CPU time	155.53 seconds
Started	May 23 12:40:58 PM PDT 24
Finished	May 23 12:43:37 PM PDT 24
Peak memory	211548 kb
Host	smart-9c12d4f6-54e8-444f-bf02-37c32952f82f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3976871700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3976871700
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.572626238
Short name	T456
Test name
Test status
Simulation time	861561737 ps
CPU time	55.33 seconds
Started	May 23 12:41:06 PM PDT 24
Finished	May 23 12:42:03 PM PDT 24
Peak memory	204268 kb
Host	smart-d47015df-18dc-4d2e-8c44-67b1110431c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572626238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.572626238
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1172268680
Short name	T886
Test name
Test status
Simulation time	1316039592 ps
CPU time	22.39 seconds
Started	May 23 12:40:56 PM PDT 24
Finished	May 23 12:41:20 PM PDT 24
Peak memory	204848 kb
Host	smart-c8d4163d-b214-4cb4-9e7b-28131c548acd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1172268680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1172268680
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.317298858
Short name	T124
Test name
Test status
Simulation time	1382950387 ps
CPU time	30.02 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:41:35 PM PDT 24
Peak memory	204560 kb
Host	smart-8c989ac6-25a9-4324-a41a-c4aba4860322
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317298858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.317298858
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2696425082
Short name	T859
Test name
Test status
Simulation time	36901716763 ps
CPU time	258.1 seconds
Started	May 23 12:40:57 PM PDT 24
Finished	May 23 12:45:17 PM PDT 24
Peak memory	205892 kb
Host	smart-dcca58f6-a44d-4d70-9bfd-327f940a6de1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2696425082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2696425082
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4133938909
Short name	T21
Test name
Test status
Simulation time	60074164 ps
CPU time	2.77 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:06 PM PDT 24
Peak memory	203220 kb
Host	smart-9e2843f9-2f76-4382-9e51-eea37807d416
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4133938909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.4133938909
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.2910776132
Short name	T257
Test name
Test status
Simulation time	1338910736 ps
CPU time	30.8 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	203292 kb
Host	smart-1bb7401e-1757-4c8f-89fc-a27c89c20917
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2910776132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2910776132
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.3824311042
Short name	T95
Test name
Test status
Simulation time	173770785 ps
CPU time	18.21 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:22 PM PDT 24
Peak memory	204336 kb
Host	smart-7d9c93c2-c71f-4b34-af6c-a5f727571951
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3824311042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3824311042
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2735017892
Short name	T201
Test name
Test status
Simulation time	35250348881 ps
CPU time	71.71 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:42:15 PM PDT 24
Peak memory	211508 kb
Host	smart-402d26f2-fc8b-432c-9c75-b295d3b4dcac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735017892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2735017892
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.431424951
Short name	T449
Test name
Test status
Simulation time	36556803796 ps
CPU time	201.29 seconds
Started	May 23 12:40:56 PM PDT 24
Finished	May 23 12:44:18 PM PDT 24
Peak memory	204960 kb
Host	smart-cc123838-b414-4076-b89c-3418ab863273
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=431424951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.431424951
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.4045825271
Short name	T706
Test name
Test status
Simulation time	22635639 ps
CPU time	2.14 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:07 PM PDT 24
Peak memory	203292 kb
Host	smart-15db9a52-f2b3-4342-b9f8-b06777c2c40a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045825271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.4045825271
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.323252108
Short name	T329
Test name
Test status
Simulation time	29408464 ps
CPU time	2.6 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	203300 kb
Host	smart-fd8e9280-f59c-4b13-b9a7-f6d97f34111b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=323252108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.323252108
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.2183104963
Short name	T885
Test name
Test status
Simulation time	199075521 ps
CPU time	2.78 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:06 PM PDT 24
Peak memory	203208 kb
Host	smart-6726f3d7-091b-4871-b9a6-cb097e6868ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2183104963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2183104963
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2978795502
Short name	T258
Test name
Test status
Simulation time	4408974841 ps
CPU time	28.12 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:41:40 PM PDT 24
Peak memory	203424 kb
Host	smart-31458c15-27f9-4b74-98a2-49451c7769e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978795502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2978795502
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3090077380
Short name	T340
Test name
Test status
Simulation time	6918636903 ps
CPU time	29.25 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	203320 kb
Host	smart-57e6daad-0bdd-4f13-8892-a6bd8586019e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3090077380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3090077380
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1713893638
Short name	T272
Test name
Test status
Simulation time	60490592 ps
CPU time	2.26 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	203264 kb
Host	smart-1c794dd8-6013-4f78-95c0-43f0728865aa
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713893638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1713893638
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.274648360
Short name	T639
Test name
Test status
Simulation time	7181106870 ps
CPU time	167.06 seconds
Started	May 23 12:41:06 PM PDT 24
Finished	May 23 12:43:55 PM PDT 24
Peak memory	207324 kb
Host	smart-1ad94a02-fa43-4b1a-a385-7b67afdff428
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=274648360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.274648360
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.464936785
Short name	T269
Test name
Test status
Simulation time	3856073962 ps
CPU time	114.78 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:43:00 PM PDT 24
Peak memory	206192 kb
Host	smart-cf5f86e8-31c9-4c6f-8a4b-bfcedcada8a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464936785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.464936785
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.919100869
Short name	T37
Test name
Test status
Simulation time	18114999405 ps
CPU time	635.79 seconds
Started	May 23 12:40:58 PM PDT 24
Finished	May 23 12:51:36 PM PDT 24
Peak memory	219852 kb
Host	smart-f6cf41f1-992d-494e-903c-7c7b205b3b57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=919100869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand _reset.919100869
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3445503302
Short name	T203
Test name
Test status
Simulation time	78999023 ps
CPU time	24.35 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:41:30 PM PDT 24
Peak memory	205668 kb
Host	smart-9d901fe7-d16b-47dc-b85d-fe67c418cf66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3445503302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.3445503302
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1627258379
Short name	T204
Test name
Test status
Simulation time	497954529 ps
CPU time	7.34 seconds
Started	May 23 12:40:57 PM PDT 24
Finished	May 23 12:41:06 PM PDT 24
Peak memory	204656 kb
Host	smart-afc25d12-5b96-4adb-9121-e2ce0641fe38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1627258379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1627258379
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.506364515
Short name	T225
Test name
Test status
Simulation time	99759036 ps
CPU time	3.77 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:09 PM PDT 24
Peak memory	203272 kb
Host	smart-27ea3af2-d4bc-4f82-b013-c11ae4a5b024
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=506364515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.506364515
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3025910476
Short name	T15
Test name
Test status
Simulation time	123125319062 ps
CPU time	411.05 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:47:56 PM PDT 24
Peak memory	206900 kb
Host	smart-5a131a21-6449-4d82-914a-4c6ac2678b55
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3025910476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.3025910476
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2123774290
Short name	T242
Test name
Test status
Simulation time	1347791203 ps
CPU time	30.39 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:36 PM PDT 24
Peak memory	203568 kb
Host	smart-57cc6fae-3223-4147-b723-ef88a9de5ab7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123774290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2123774290
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.1749834886
Short name	T513
Test name
Test status
Simulation time	2052519629 ps
CPU time	12.69 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:41:18 PM PDT 24
Peak memory	203220 kb
Host	smart-64bb7353-a082-423c-a564-687ad82e2066
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1749834886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1749834886
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.473753395
Short name	T174
Test name
Test status
Simulation time	545570201 ps
CPU time	29.73 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	204836 kb
Host	smart-dd70abe5-18f8-45dd-8d34-3e7c32b82cf1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=473753395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.473753395
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3289344709
Short name	T341
Test name
Test status
Simulation time	86544811656 ps
CPU time	240.34 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:45:05 PM PDT 24
Peak memory	204600 kb
Host	smart-f131a706-043c-46b7-a115-e8178023b3a1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289344709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3289344709
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1142435897
Short name	T469
Test name
Test status
Simulation time	17696162576 ps
CPU time	61.74 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:42:07 PM PDT 24
Peak memory	204588 kb
Host	smart-8dc1eb43-c6e8-457f-b1d0-43aa6d45ed9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1142435897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1142435897
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3940044247
Short name	T575
Test name
Test status
Simulation time	337912422 ps
CPU time	19.03 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:24 PM PDT 24
Peak memory	204556 kb
Host	smart-56ee893e-d149-4ea2-b6d4-e0c2f3d58c40
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940044247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3940044247
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.1391534973
Short name	T312
Test name
Test status
Simulation time	84288904 ps
CPU time	5.74 seconds
Started	May 23 12:41:05 PM PDT 24
Finished	May 23 12:41:13 PM PDT 24
Peak memory	203796 kb
Host	smart-7e7e44c3-7247-4cb6-bfb5-82375b13a030
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1391534973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1391534973
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.3989340289
Short name	T352
Test name
Test status
Simulation time	454296708 ps
CPU time	3.32 seconds
Started	May 23 12:40:59 PM PDT 24
Finished	May 23 12:41:07 PM PDT 24
Peak memory	203264 kb
Host	smart-6f599ac7-ffed-49ca-a892-7917b13fc5d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3989340289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3989340289
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4129396945
Short name	T683
Test name
Test status
Simulation time	5357414123 ps
CPU time	26.83 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:41:32 PM PDT 24
Peak memory	203336 kb
Host	smart-1b11450b-1b23-4793-aaa6-0823d04eab35
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129396945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4129396945
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3823573718
Short name	T863
Test name
Test status
Simulation time	4580478950 ps
CPU time	36.03 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:41:42 PM PDT 24
Peak memory	203340 kb
Host	smart-78139c84-f78c-43b1-9be5-fd6ecb0873c3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3823573718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3823573718
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1217469688
Short name	T332
Test name
Test status
Simulation time	177509472 ps
CPU time	2.74 seconds
Started	May 23 12:41:06 PM PDT 24
Finished	May 23 12:41:11 PM PDT 24
Peak memory	203248 kb
Host	smart-688fbf35-ca6c-4429-bc2b-84b87eb0e868
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217469688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1217469688
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.3131343135
Short name	T359
Test name
Test status
Simulation time	2603205618 ps
CPU time	173.4 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:44:05 PM PDT 24
Peak memory	210108 kb
Host	smart-3e4da0a6-bfc9-41fa-8ba1-19f41d6c0a1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3131343135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3131343135
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.489154344
Short name	T736
Test name
Test status
Simulation time	1596298925 ps
CPU time	157.84 seconds
Started	May 23 12:41:01 PM PDT 24
Finished	May 23 12:43:43 PM PDT 24
Peak memory	207528 kb
Host	smart-98dc28f1-0290-495b-bd0b-5b44a094fa97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=489154344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.489154344
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1668193149
Short name	T867
Test name
Test status
Simulation time	2289723560 ps
CPU time	442.3 seconds
Started	May 23 12:41:03 PM PDT 24
Finished	May 23 12:48:28 PM PDT 24
Peak memory	208692 kb
Host	smart-f24b4330-9e35-44b7-879b-d67043220a73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1668193149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1668193149
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1840261281
Short name	T689
Test name
Test status
Simulation time	670485673 ps
CPU time	197.54 seconds
Started	May 23 12:41:09 PM PDT 24
Finished	May 23 12:44:28 PM PDT 24
Peak memory	219752 kb
Host	smart-78005a17-1f3b-43b0-ad98-dd4509d7d989
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840261281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.1840261281
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.379073093
Short name	T207
Test name
Test status
Simulation time	750694583 ps
CPU time	18.15 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	204560 kb
Host	smart-16ba6482-f96a-43ef-9772-b89182921177
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=379073093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.379073093
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.121073046
Short name	T666
Test name
Test status
Simulation time	230243067 ps
CPU time	11.77 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	204384 kb
Host	smart-a62648c3-54b0-4b24-866d-4626a7715073
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=121073046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.121073046
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2823503266
Short name	T313
Test name
Test status
Simulation time	517821941 ps
CPU time	10.3 seconds
Started	May 23 12:41:06 PM PDT 24
Finished	May 23 12:41:19 PM PDT 24
Peak memory	203360 kb
Host	smart-53d6afdf-18ce-4b30-8499-390e3553dc88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2823503266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2823503266
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.1165462710
Short name	T281
Test name
Test status
Simulation time	24504567 ps
CPU time	2.86 seconds
Started	May 23 12:41:06 PM PDT 24
Finished	May 23 12:41:11 PM PDT 24
Peak memory	203292 kb
Host	smart-86c11806-2f72-47db-b43d-a05c3288982e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1165462710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1165462710
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.963587873
Short name	T846
Test name
Test status
Simulation time	93257954 ps
CPU time	15.28 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:41:27 PM PDT 24
Peak memory	211536 kb
Host	smart-77deeb6f-00be-406d-b82d-47e08d933658
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=963587873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.963587873
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3223363001
Short name	T724
Test name
Test status
Simulation time	43705837211 ps
CPU time	275.88 seconds
Started	May 23 12:41:09 PM PDT 24
Finished	May 23 12:45:46 PM PDT 24
Peak memory	211620 kb
Host	smart-cd157e1d-f014-48a3-a43a-b81d2422560e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223363001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3223363001
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1136307191
Short name	T711
Test name
Test status
Simulation time	14130906028 ps
CPU time	90.72 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:42:36 PM PDT 24
Peak memory	204728 kb
Host	smart-724418d6-e2cb-48fb-82ef-4059d73c402f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1136307191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1136307191
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2444815114
Short name	T436
Test name
Test status
Simulation time	121356357 ps
CPU time	13.9 seconds
Started	May 23 12:40:58 PM PDT 24
Finished	May 23 12:41:15 PM PDT 24
Peak memory	211488 kb
Host	smart-c431b11a-c59b-4e53-8fa6-17141b9fcf6d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444815114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2444815114
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.3201272599
Short name	T183
Test name
Test status
Simulation time	2594914947 ps
CPU time	28.49 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	203360 kb
Host	smart-f2525e19-4e6d-4c60-aa80-60db61eb3402
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3201272599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3201272599
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.2048351124
Short name	T819
Test name
Test status
Simulation time	152732016 ps
CPU time	4.44 seconds
Started	May 23 12:41:03 PM PDT 24
Finished	May 23 12:41:11 PM PDT 24
Peak memory	203268 kb
Host	smart-68fde6ea-bbf2-4c2e-8c66-3db008d042f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048351124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2048351124
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.79871583
Short name	T139
Test name
Test status
Simulation time	8489289857 ps
CPU time	32.78 seconds
Started	May 23 12:41:09 PM PDT 24
Finished	May 23 12:41:43 PM PDT 24
Peak memory	203416 kb
Host	smart-c8b3e4be-3e13-4e8a-9608-ceae1d4fecaa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=79871583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.79871583
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1688695612
Short name	T166
Test name
Test status
Simulation time	18447776717 ps
CPU time	36.13 seconds
Started	May 23 12:41:00 PM PDT 24
Finished	May 23 12:41:40 PM PDT 24
Peak memory	203428 kb
Host	smart-092ffb84-12f6-4f47-97c0-cc27e2ffd80b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1688695612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1688695612
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.464833232
Short name	T298
Test name
Test status
Simulation time	53612738 ps
CPU time	2.35 seconds
Started	May 23 12:41:03 PM PDT 24
Finished	May 23 12:41:08 PM PDT 24
Peak memory	203276 kb
Host	smart-0f461fc3-4bf7-4280-ba87-53ab52484bd9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464833232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.464833232
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.3501247542
Short name	T445
Test name
Test status
Simulation time	1493380373 ps
CPU time	38.47 seconds
Started	May 23 12:41:06 PM PDT 24
Finished	May 23 12:41:47 PM PDT 24
Peak memory	205632 kb
Host	smart-872d6f26-7ac2-4403-abc6-c5eedd0ebe1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3501247542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3501247542
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3652929543
Short name	T880
Test name
Test status
Simulation time	3176031573 ps
CPU time	86.27 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:42:32 PM PDT 24
Peak memory	206044 kb
Host	smart-0facb430-92bb-4d45-a69e-f706a7842875
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3652929543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3652929543
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.490583293
Short name	T116
Test name
Test status
Simulation time	609635686 ps
CPU time	241.59 seconds
Started	May 23 12:41:02 PM PDT 24
Finished	May 23 12:45:07 PM PDT 24
Peak memory	208440 kb
Host	smart-1e1bfbda-aa6f-4123-9da8-f89e9704ff03
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=490583293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand _reset.490583293
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4236597038
Short name	T849
Test name
Test status
Simulation time	134569227 ps
CPU time	19.79 seconds
Started	May 23 12:41:09 PM PDT 24
Finished	May 23 12:41:30 PM PDT 24
Peak memory	204796 kb
Host	smart-087a5f9d-e31c-4a33-b63f-dbf11703033d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4236597038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4236597038
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.4251249804
Short name	T1
Test name
Test status
Simulation time	2235271701 ps
CPU time	59.83 seconds
Started	May 23 12:41:09 PM PDT 24
Finished	May 23 12:42:11 PM PDT 24
Peak memory	205468 kb
Host	smart-3a9b79e7-7d29-442d-b24f-07bfd9dcd25a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4251249804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4251249804
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2996487017
Short name	T512
Test name
Test status
Simulation time	191940533491 ps
CPU time	445.46 seconds
Started	May 23 12:41:11 PM PDT 24
Finished	May 23 12:48:39 PM PDT 24
Peak memory	206776 kb
Host	smart-d2da20d8-f062-4b58-98cd-54d5cbbdb8dc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2996487017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2996487017
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.685848096
Short name	T681
Test name
Test status
Simulation time	1062619628 ps
CPU time	29.78 seconds
Started	May 23 12:41:11 PM PDT 24
Finished	May 23 12:41:42 PM PDT 24
Peak memory	203624 kb
Host	smart-ebffe5e0-13c3-44bf-9e9a-881d9cf15e9d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=685848096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.685848096
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.3198559369
Short name	T658
Test name
Test status
Simulation time	342917945 ps
CPU time	5.36 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:21 PM PDT 24
Peak memory	203260 kb
Host	smart-4bb6c706-6032-401c-a50a-896e97ae132a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3198559369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3198559369
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.86274965
Short name	T22
Test name
Test status
Simulation time	240327044 ps
CPU time	19.25 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:35 PM PDT 24
Peak memory	204388 kb
Host	smart-c351a1f0-40c2-4acf-bfd4-f0609be732a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=86274965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.86274965
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.106390972
Short name	T697
Test name
Test status
Simulation time	20446023131 ps
CPU time	90.27 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:42:44 PM PDT 24
Peak memory	211444 kb
Host	smart-f19461e8-2615-4c3a-8357-e2cae7ef49ff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=106390972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.106390972
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.912498162
Short name	T16
Test name
Test status
Simulation time	92985258089 ps
CPU time	216.55 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:44:52 PM PDT 24
Peak memory	204892 kb
Host	smart-637c7350-59af-4de1-8191-5969060f2457
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=912498162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.912498162
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1873990116
Short name	T266
Test name
Test status
Simulation time	860223720 ps
CPU time	30.37 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:46 PM PDT 24
Peak memory	204744 kb
Host	smart-c9c19cd0-7a13-4264-9859-c8bedeb83b48
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873990116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1873990116
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.830434492
Short name	T529
Test name
Test status
Simulation time	478459874 ps
CPU time	9.23 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:41:23 PM PDT 24
Peak memory	203408 kb
Host	smart-8ea59323-11ae-47d7-baed-5f3ad20898b7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830434492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.830434492
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.682179840
Short name	T404
Test name
Test status
Simulation time	49254951 ps
CPU time	2.72 seconds
Started	May 23 12:40:58 PM PDT 24
Finished	May 23 12:41:04 PM PDT 24
Peak memory	203384 kb
Host	smart-ca031da7-552e-447a-81d8-9f947ba0c6c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682179840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.682179840
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1247309053
Short name	T739
Test name
Test status
Simulation time	6501704254 ps
CPU time	36.86 seconds
Started	May 23 12:41:18 PM PDT 24
Finished	May 23 12:41:56 PM PDT 24
Peak memory	203408 kb
Host	smart-8e7fa823-f016-4b0a-b302-a84bedb27008
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247309053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1247309053
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3612680330
Short name	T468
Test name
Test status
Simulation time	7080009117 ps
CPU time	26.24 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:41:38 PM PDT 24
Peak memory	203324 kb
Host	smart-c0da8ae8-4222-4173-86aa-eb24126a3139
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3612680330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3612680330
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2243529463
Short name	T375
Test name
Test status
Simulation time	38863289 ps
CPU time	2.17 seconds
Started	May 23 12:41:04 PM PDT 24
Finished	May 23 12:41:09 PM PDT 24
Peak memory	203280 kb
Host	smart-3592783c-2119-4865-bfde-4c3441d1de73
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243529463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2243529463
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.941989869
Short name	T653
Test name
Test status
Simulation time	2574687556 ps
CPU time	157.39 seconds
Started	May 23 12:41:11 PM PDT 24
Finished	May 23 12:43:50 PM PDT 24
Peak memory	207704 kb
Host	smart-d4ebc1c1-5ebe-458a-98c7-f8d7d024307a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=941989869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.941989869
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1753193114
Short name	T42
Test name
Test status
Simulation time	14548845040 ps
CPU time	227.22 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:45:02 PM PDT 24
Peak memory	209612 kb
Host	smart-2612d3da-e591-492b-ba9c-a138ffe57d7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1753193114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1753193114
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1729333135
Short name	T808
Test name
Test status
Simulation time	2335151526 ps
CPU time	166.58 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:43:58 PM PDT 24
Peak memory	208748 kb
Host	smart-5ff17a7d-1e94-42bc-a88b-e7f7b9412950
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1729333135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1729333135
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3224941623
Short name	T320
Test name
Test status
Simulation time	1207416348 ps
CPU time	80.2 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:42:34 PM PDT 24
Peak memory	208184 kb
Host	smart-cb40c631-c4e7-4b08-b3cf-5fdb04170dd2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3224941623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3224941623
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.319807265
Short name	T690
Test name
Test status
Simulation time	1469262266 ps
CPU time	29.23 seconds
Started	May 23 12:41:11 PM PDT 24
Finished	May 23 12:41:42 PM PDT 24
Peak memory	211464 kb
Host	smart-96b70cf1-4728-4180-be26-7a51cc50f5ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=319807265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.319807265
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.4063651813
Short name	T151
Test name
Test status
Simulation time	1814800429 ps
CPU time	31.12 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:41:46 PM PDT 24
Peak memory	205252 kb
Host	smart-1987bf2b-7100-4191-953f-681d93be8ce5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4063651813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.4063651813
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.398412603
Short name	T698
Test name
Test status
Simulation time	16835169041 ps
CPU time	48.79 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:42:04 PM PDT 24
Peak memory	205036 kb
Host	smart-7992e43c-08f7-4df9-b499-f3581a38be9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=398412603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo w_rsp.398412603
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.793305766
Short name	T284
Test name
Test status
Simulation time	1334795905 ps
CPU time	17.07 seconds
Started	May 23 12:41:15 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	203440 kb
Host	smart-3aef4809-f96a-44a9-b6bd-5fd6487b2be5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=793305766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.793305766
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.4000882477
Short name	T820
Test name
Test status
Simulation time	432083360 ps
CPU time	15.43 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:41:29 PM PDT 24
Peak memory	203288 kb
Host	smart-836ef3ac-5f76-4292-b5d4-279635aea608
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000882477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4000882477
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.2154143150
Short name	T511
Test name
Test status
Simulation time	200230377 ps
CPU time	27.24 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:41:39 PM PDT 24
Peak memory	204492 kb
Host	smart-932e3818-e338-4266-a6ff-d4e63bf64c5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2154143150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2154143150
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3511156813
Short name	T86
Test name
Test status
Simulation time	31621002638 ps
CPU time	39.24 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:55 PM PDT 24
Peak memory	204012 kb
Host	smart-012714fc-08a6-4c8e-933e-b833502a0b2b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511156813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3511156813
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2401284456
Short name	T98
Test name
Test status
Simulation time	1901910117 ps
CPU time	12.73 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:28 PM PDT 24
Peak memory	203376 kb
Host	smart-665a25a2-9f59-4d7a-a83b-87f7ce6b2143
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2401284456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2401284456
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2276354067
Short name	T335
Test name
Test status
Simulation time	408820221 ps
CPU time	16.03 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:41:30 PM PDT 24
Peak memory	211432 kb
Host	smart-faad523e-1b9d-4bb4-bde6-0e9aeba7c6fc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276354067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2276354067
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.1784368033
Short name	T68
Test name
Test status
Simulation time	984680844 ps
CPU time	15.71 seconds
Started	May 23 12:41:15 PM PDT 24
Finished	May 23 12:41:33 PM PDT 24
Peak memory	203784 kb
Host	smart-34cb5048-e374-4ac6-b331-1e3e66d8fc94
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784368033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1784368033
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.2615426518
Short name	T627
Test name
Test status
Simulation time	177927394 ps
CPU time	4.22 seconds
Started	May 23 12:41:11 PM PDT 24
Finished	May 23 12:41:17 PM PDT 24
Peak memory	203356 kb
Host	smart-00368ea9-7088-41d7-baf8-04ec169af12c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2615426518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2615426518
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.96522978
Short name	T765
Test name
Test status
Simulation time	6933059449 ps
CPU time	33.39 seconds
Started	May 23 12:41:11 PM PDT 24
Finished	May 23 12:41:47 PM PDT 24
Peak memory	203304 kb
Host	smart-ac3d9260-bbf9-405a-9ece-89cf2268c21f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=96522978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.96522978
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.767209744
Short name	T168
Test name
Test status
Simulation time	6504725645 ps
CPU time	31.33 seconds
Started	May 23 12:41:14 PM PDT 24
Finished	May 23 12:41:48 PM PDT 24
Peak memory	203268 kb
Host	smart-acc5b3fb-7c07-4105-90f1-793a0919b9b5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=767209744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.767209744
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2260181627
Short name	T331
Test name
Test status
Simulation time	25166359 ps
CPU time	2.05 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:41:16 PM PDT 24
Peak memory	203276 kb
Host	smart-d8145ea0-2b4c-4b7e-879e-d2ae6e19317c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260181627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2260181627
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.3168099954
Short name	T648
Test name
Test status
Simulation time	3992068544 ps
CPU time	103 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:42:58 PM PDT 24
Peak memory	207836 kb
Host	smart-d6c8a1ab-b243-4cbb-b4ea-f13b55698b47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3168099954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3168099954
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3444771201
Short name	T566
Test name
Test status
Simulation time	704883605 ps
CPU time	21.27 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:41:36 PM PDT 24
Peak memory	203668 kb
Host	smart-83ecb4f4-2554-4e72-91aa-3187a155139f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444771201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3444771201
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.28217858
Short name	T792
Test name
Test status
Simulation time	923629881 ps
CPU time	312.91 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:46:27 PM PDT 24
Peak memory	209612 kb
Host	smart-e1c52cf8-204e-4785-b59b-d2213c6f9ab1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=28217858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_ reset.28217858
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1302472935
Short name	T729
Test name
Test status
Simulation time	8391067017 ps
CPU time	214.33 seconds
Started	May 23 12:41:12 PM PDT 24
Finished	May 23 12:44:49 PM PDT 24
Peak memory	211632 kb
Host	smart-9ad54036-7a14-4d09-bd4e-758bc83e0eee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1302472935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1302472935
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2029447442
Short name	T773
Test name
Test status
Simulation time	192910329 ps
CPU time	12.31 seconds
Started	May 23 12:41:15 PM PDT 24
Finished	May 23 12:41:30 PM PDT 24
Peak memory	204840 kb
Host	smart-b3702bc3-c334-43b9-a8d5-98b6ebfec203
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2029447442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2029447442
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2156709815
Short name	T155
Test name
Test status
Simulation time	185367936 ps
CPU time	10.01 seconds
Started	May 23 12:41:16 PM PDT 24
Finished	May 23 12:41:28 PM PDT 24
Peak memory	205208 kb
Host	smart-6ad952c7-6ed1-49ae-a994-09c61c86c35e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2156709815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2156709815
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2796921654
Short name	T769
Test name
Test status
Simulation time	225493012086 ps
CPU time	454.85 seconds
Started	May 23 12:41:14 PM PDT 24
Finished	May 23 12:48:51 PM PDT 24
Peak memory	205824 kb
Host	smart-54aa53b1-c40d-4782-8ecc-fc361845d308
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2796921654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2796921654
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.698145372
Short name	T144
Test name
Test status
Simulation time	1010526440 ps
CPU time	7.23 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:22 PM PDT 24
Peak memory	203484 kb
Host	smart-dc36a611-5ddb-49c7-99e5-671fc152b1ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=698145372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.698145372
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.2889141997
Short name	T10
Test name
Test status
Simulation time	2664870070 ps
CPU time	14.81 seconds
Started	May 23 12:41:17 PM PDT 24
Finished	May 23 12:41:33 PM PDT 24
Peak memory	203324 kb
Host	smart-cba505b0-04ba-459b-be8e-1bc957e818cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2889141997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2889141997
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.1779707926
Short name	T558
Test name
Test status
Simulation time	508275030 ps
CPU time	7.57 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:41:20 PM PDT 24
Peak memory	204380 kb
Host	smart-e523a73c-446b-45d0-b106-cf997604bcc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1779707926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1779707926
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.369697621
Short name	T342
Test name
Test status
Simulation time	34747359674 ps
CPU time	92.73 seconds
Started	May 23 12:41:14 PM PDT 24
Finished	May 23 12:42:49 PM PDT 24
Peak memory	204536 kb
Host	smart-86ee7394-7304-465a-929f-bcc5e81ea435
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=369697621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.369697621
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4286597761
Short name	T594
Test name
Test status
Simulation time	75784141629 ps
CPU time	156.98 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:43:52 PM PDT 24
Peak memory	204604 kb
Host	smart-d80ef6ae-a953-4ad0-9497-32eb9bbdf4c3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4286597761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4286597761
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1394382501
Short name	T522
Test name
Test status
Simulation time	81360687 ps
CPU time	9.38 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:25 PM PDT 24
Peak memory	204384 kb
Host	smart-358340d1-0e6d-4025-99a4-838fc5178312
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394382501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1394382501
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.1979955812
Short name	T578
Test name
Test status
Simulation time	383733197 ps
CPU time	21.09 seconds
Started	May 23 12:41:15 PM PDT 24
Finished	May 23 12:41:38 PM PDT 24
Peak memory	204044 kb
Host	smart-4c3a3808-7e3a-4182-9b1f-1bcfa4aa935e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1979955812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1979955812
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.660345896
Short name	T282
Test name
Test status
Simulation time	28217826 ps
CPU time	2.06 seconds
Started	May 23 12:41:14 PM PDT 24
Finished	May 23 12:41:18 PM PDT 24
Peak memory	203284 kb
Host	smart-21eda563-79e2-4aeb-a5b0-ac09dbf154af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=660345896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.660345896
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3524278213
Short name	T457
Test name
Test status
Simulation time	6235150874 ps
CPU time	33.45 seconds
Started	May 23 12:41:10 PM PDT 24
Finished	May 23 12:41:46 PM PDT 24
Peak memory	203340 kb
Host	smart-ca6a8a4d-40e5-43b5-b7a4-c1ac66494e0f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524278213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3524278213
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1135227122
Short name	T777
Test name
Test status
Simulation time	12699079075 ps
CPU time	40.59 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:57 PM PDT 24
Peak memory	203340 kb
Host	smart-d7d6b61e-25b0-4766-865c-b476626a7aa8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1135227122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1135227122
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3239249024
Short name	T644
Test name
Test status
Simulation time	55516434 ps
CPU time	2.37 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:18 PM PDT 24
Peak memory	203264 kb
Host	smart-211aadaf-8a99-460a-bc28-e3e3297821b3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239249024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3239249024
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.1646343266
Short name	T538
Test name
Test status
Simulation time	198847263 ps
CPU time	18.41 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:34 PM PDT 24
Peak memory	204900 kb
Host	smart-ae34e9ff-5e12-4f03-b650-0860c48efda8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1646343266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1646343266
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2944944080
Short name	T20
Test name
Test status
Simulation time	2848452609 ps
CPU time	89.17 seconds
Started	May 23 12:41:19 PM PDT 24
Finished	May 23 12:42:49 PM PDT 24
Peak memory	206000 kb
Host	smart-7d18f0ea-d791-437f-8b33-077ccc793821
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2944944080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2944944080
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.950723045
Short name	T718
Test name
Test status
Simulation time	9004598860 ps
CPU time	390.85 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:47:47 PM PDT 24
Peak memory	209960 kb
Host	smart-4ca05f8a-6d90-4cd8-9a2a-de3186f6b07d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=950723045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand _reset.950723045
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1479794442
Short name	T237
Test name
Test status
Simulation time	719877953 ps
CPU time	210.51 seconds
Started	May 23 12:41:16 PM PDT 24
Finished	May 23 12:44:48 PM PDT 24
Peak memory	210544 kb
Host	smart-d1041ad1-9180-4642-80e7-cfddbae29d91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1479794442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.1479794442
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.4086691045
Short name	T663
Test name
Test status
Simulation time	189816068 ps
CPU time	9.34 seconds
Started	May 23 12:41:13 PM PDT 24
Finished	May 23 12:41:24 PM PDT 24
Peak memory	211448 kb
Host	smart-8535e371-4c33-4073-91e4-4120dce07a34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4086691045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.4086691045
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.338184344
Short name	T216
Test name
Test status
Simulation time	1512141021 ps
CPU time	15.47 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:15 PM PDT 24
Peak memory	204376 kb
Host	smart-5a29622c-6097-402a-becf-c20c5201818d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=338184344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.338184344
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2221747465
Short name	T473
Test name
Test status
Simulation time	257572362 ps
CPU time	3.31 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:01 PM PDT 24
Peak memory	203232 kb
Host	smart-73970d4a-b48d-4b5c-89fb-f607b387f6eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221747465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2221747465
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.2943436912
Short name	T879
Test name
Test status
Simulation time	243184257 ps
CPU time	13.91 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:38:13 PM PDT 24
Peak memory	203312 kb
Host	smart-de693a5b-5d54-488c-8e0b-3f1993d08596
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2943436912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2943436912
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.981435620
Short name	T186
Test name
Test status
Simulation time	3795024022 ps
CPU time	38.37 seconds
Started	May 23 12:37:55 PM PDT 24
Finished	May 23 12:38:35 PM PDT 24
Peak memory	204620 kb
Host	smart-6c574102-4ba9-49ff-8081-38406f593834
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981435620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.981435620
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.529651499
Short name	T273
Test name
Test status
Simulation time	77410126793 ps
CPU time	242.12 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:42:03 PM PDT 24
Peak memory	204568 kb
Host	smart-5f988bd5-cc1d-4f4d-a775-db6aefa82fe1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=529651499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.529651499
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1890004038
Short name	T677
Test name
Test status
Simulation time	6381990637 ps
CPU time	17.95 seconds
Started	May 23 12:38:00 PM PDT 24
Finished	May 23 12:38:20 PM PDT 24
Peak memory	203328 kb
Host	smart-26e913c4-4820-4395-a329-1ec759d210b6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1890004038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1890004038
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3976140378
Short name	T621
Test name
Test status
Simulation time	106395442 ps
CPU time	12.92 seconds
Started	May 23 12:38:03 PM PDT 24
Finished	May 23 12:38:16 PM PDT 24
Peak memory	211468 kb
Host	smart-6dcf5314-795b-4432-b983-50fb7c5f9460
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976140378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3976140378
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.887382701
Short name	T492
Test name
Test status
Simulation time	1130142576 ps
CPU time	11.06 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:09 PM PDT 24
Peak memory	203296 kb
Host	smart-5f0a7ebe-70ee-4fd8-a436-460990f03f6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=887382701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.887382701
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.4019263505
Short name	T896
Test name
Test status
Simulation time	141247745 ps
CPU time	3.65 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:04 PM PDT 24
Peak memory	203268 kb
Host	smart-83ee8ce6-ef4b-4f49-bd24-85b3b8aef883
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4019263505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.4019263505
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3172662199
Short name	T250
Test name
Test status
Simulation time	4813570954 ps
CPU time	30.37 seconds
Started	May 23 12:37:55 PM PDT 24
Finished	May 23 12:38:27 PM PDT 24
Peak memory	203248 kb
Host	smart-89307789-9d4d-4201-a02b-523335228b08
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172662199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3172662199
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.734911113
Short name	T651
Test name
Test status
Simulation time	12572171322 ps
CPU time	43.11 seconds
Started	May 23 12:38:00 PM PDT 24
Finished	May 23 12:38:45 PM PDT 24
Peak memory	203312 kb
Host	smart-117e2645-5b3b-4d2e-b740-9842e592abb9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=734911113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.734911113
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4147383347
Short name	T850
Test name
Test status
Simulation time	29538898 ps
CPU time	1.96 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:38:01 PM PDT 24
Peak memory	203264 kb
Host	smart-539f94c9-b9b8-4f61-83fc-ac6ab314a263
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147383347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4147383347
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.3871244503
Short name	T535
Test name
Test status
Simulation time	1033589320 ps
CPU time	53.89 seconds
Started	May 23 12:37:59 PM PDT 24
Finished	May 23 12:38:56 PM PDT 24
Peak memory	207568 kb
Host	smart-27102b28-066f-49e0-8364-e4eb1804e2de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3871244503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3871244503
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1010706667
Short name	T172
Test name
Test status
Simulation time	6636091599 ps
CPU time	159.33 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:40:39 PM PDT 24
Peak memory	206524 kb
Host	smart-e318de5d-3270-4b79-99b9-97e56492c7d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1010706667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1010706667
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2821957662
Short name	T184
Test name
Test status
Simulation time	467521563 ps
CPU time	147.46 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:40:26 PM PDT 24
Peak memory	208196 kb
Host	smart-7dd79dcc-0c2b-424e-a4a9-45a5d08054e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2821957662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2821957662
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1649099096
Short name	T234
Test name
Test status
Simulation time	4438412831 ps
CPU time	271.58 seconds
Started	May 23 12:38:00 PM PDT 24
Finished	May 23 12:42:34 PM PDT 24
Peak memory	220048 kb
Host	smart-7f85a78a-b9ef-4957-a6b7-418d03f057d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1649099096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1649099096
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3754555413
Short name	T833
Test name
Test status
Simulation time	617711557 ps
CPU time	23.06 seconds
Started	May 23 12:38:00 PM PDT 24
Finished	May 23 12:38:26 PM PDT 24
Peak memory	211488 kb
Host	smart-0f464637-ef6b-4b32-ac3d-24f1354f08f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3754555413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3754555413
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.360701228
Short name	T507
Test name
Test status
Simulation time	42920044309 ps
CPU time	169.7 seconds
Started	May 23 12:38:02 PM PDT 24
Finished	May 23 12:40:53 PM PDT 24
Peak memory	206324 kb
Host	smart-7acc7dc7-7374-4cda-af1f-82ed5ec36690
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=360701228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow _rsp.360701228
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3377056791
Short name	T345
Test name
Test status
Simulation time	2272725283 ps
CPU time	19.79 seconds
Started	May 23 12:38:00 PM PDT 24
Finished	May 23 12:38:22 PM PDT 24
Peak memory	203396 kb
Host	smart-80c835a9-c6a5-4b79-9616-f760bd771181
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3377056791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3377056791
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.1814017009
Short name	T844
Test name
Test status
Simulation time	1447688625 ps
CPU time	24.44 seconds
Started	May 23 12:38:01 PM PDT 24
Finished	May 23 12:38:27 PM PDT 24
Peak memory	203292 kb
Host	smart-b0505fe9-387d-42e3-a13c-4fd1b49696ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814017009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1814017009
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.3145507381
Short name	T855
Test name
Test status
Simulation time	146995495 ps
CPU time	2.84 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:00 PM PDT 24
Peak memory	203260 kb
Host	smart-0b8b5524-a8d2-4b93-a910-a33320d19a22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3145507381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3145507381
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.4197883316
Short name	T60
Test name
Test status
Simulation time	42246926798 ps
CPU time	238.21 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:41:56 PM PDT 24
Peak memory	211496 kb
Host	smart-7017919d-49bb-4b95-bdb8-3b4548312b49
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197883316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4197883316
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2845241706
Short name	T629
Test name
Test status
Simulation time	72221800469 ps
CPU time	261.27 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:42:21 PM PDT 24
Peak memory	205440 kb
Host	smart-3b747003-0e86-4dad-98a7-1e543a77c60e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2845241706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2845241706
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3137779421
Short name	T595
Test name
Test status
Simulation time	110130835 ps
CPU time	16.39 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:17 PM PDT 24
Peak memory	211432 kb
Host	smart-fb547409-8b10-45f4-8e27-7cecd866e6ed
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137779421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3137779421
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.475398207
Short name	T220
Test name
Test status
Simulation time	1294053376 ps
CPU time	24.99 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:23 PM PDT 24
Peak memory	203336 kb
Host	smart-0b4dc44a-f6c0-45ea-85a6-f3c1c6e3a063
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=475398207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.475398207
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.3092353127
Short name	T308
Test name
Test status
Simulation time	39368970 ps
CPU time	2.25 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:01 PM PDT 24
Peak memory	203268 kb
Host	smart-5cb1ae89-5c94-4cc4-a974-95e74d25538c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3092353127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3092353127
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1560499880
Short name	T406
Test name
Test status
Simulation time	23976898679 ps
CPU time	40.5 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:38 PM PDT 24
Peak memory	203304 kb
Host	smart-eeb71a6d-d697-46f1-a5a0-be9767889396
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560499880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1560499880
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2890629063
Short name	T668
Test name
Test status
Simulation time	9204612604 ps
CPU time	34.4 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:35 PM PDT 24
Peak memory	203332 kb
Host	smart-27bc9daf-efda-48e6-bc2c-4caab548eeac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2890629063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2890629063
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1629360526
Short name	T264
Test name
Test status
Simulation time	87497077 ps
CPU time	2.01 seconds
Started	May 23 12:38:03 PM PDT 24
Finished	May 23 12:38:05 PM PDT 24
Peak memory	203264 kb
Host	smart-69f1758c-5ddb-4e42-8fdf-74d028fb36d9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629360526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1629360526
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.1399866364
Short name	T812
Test name
Test status
Simulation time	1286499503 ps
CPU time	42.8 seconds
Started	May 23 12:37:58 PM PDT 24
Finished	May 23 12:38:43 PM PDT 24
Peak memory	205776 kb
Host	smart-3a63c4f2-c44a-4a69-b83b-11ef81029b55
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399866364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1399866364
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.386032773
Short name	T430
Test name
Test status
Simulation time	1391999688 ps
CPU time	135.46 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:40:13 PM PDT 24
Peak memory	211432 kb
Host	smart-63347d0f-8887-4db4-8910-f8f488a8def7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=386032773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.386032773
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2419066901
Short name	T793
Test name
Test status
Simulation time	8317327834 ps
CPU time	417.56 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:44:56 PM PDT 24
Peak memory	219732 kb
Host	smart-1ba1bebb-2d98-407d-a8b8-1975d9ed2ec4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419066901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.2419066901
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2370516461
Short name	T638
Test name
Test status
Simulation time	3215682169 ps
CPU time	217.19 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:41:35 PM PDT 24
Peak memory	211528 kb
Host	smart-d1c77edb-6acd-4a45-9278-6363270bf47e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2370516461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2370516461
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.82267991
Short name	T267
Test name
Test status
Simulation time	117022808 ps
CPU time	15.38 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:13 PM PDT 24
Peak memory	205060 kb
Host	smart-6b61e26a-7bbb-44c1-a9cb-cd5e4a76bedd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=82267991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.82267991
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1490398148
Short name	T471
Test name
Test status
Simulation time	5738696476 ps
CPU time	58.63 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:39:11 PM PDT 24
Peak memory	206632 kb
Host	smart-1a970579-2178-4df6-a969-ae3be6f1e7e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1490398148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1490398148
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.780097621
Short name	T622
Test name
Test status
Simulation time	43070705197 ps
CPU time	135.24 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:40:28 PM PDT 24
Peak memory	206044 kb
Host	smart-ce335493-bbee-4339-a788-1d96ebb93ce6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=780097621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow _rsp.780097621
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3537707984
Short name	T303
Test name
Test status
Simulation time	313283815 ps
CPU time	8.43 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:38:20 PM PDT 24
Peak memory	203268 kb
Host	smart-3431579a-4b07-474b-aa5c-fd09b084ecd8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3537707984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3537707984
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.782038535
Short name	T169
Test name
Test status
Simulation time	1907041064 ps
CPU time	20.14 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:31 PM PDT 24
Peak memory	203336 kb
Host	smart-e946b41b-0c8d-4dc6-872c-0f28a6bf46c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=782038535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.782038535
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.1472967505
Short name	T447
Test name
Test status
Simulation time	175145731 ps
CPU time	22.22 seconds
Started	May 23 12:37:56 PM PDT 24
Finished	May 23 12:38:21 PM PDT 24
Peak memory	204652 kb
Host	smart-3619e6a5-c1f0-49f4-9a92-4313d7ac9584
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1472967505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1472967505
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2636855614
Short name	T815
Test name
Test status
Simulation time	45696544301 ps
CPU time	229.22 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:41:49 PM PDT 24
Peak memory	204876 kb
Host	smart-d83ca82f-193a-4857-8ed1-7ff85c81f211
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636855614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2636855614
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.859750712
Short name	T431
Test name
Test status
Simulation time	15133734666 ps
CPU time	154.99 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:40:47 PM PDT 24
Peak memory	205060 kb
Host	smart-e11c69ee-c0bc-40ed-a31a-6314c6e9025b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=859750712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.859750712
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1193538586
Short name	T45
Test name
Test status
Simulation time	156882017 ps
CPU time	20.55 seconds
Started	May 23 12:37:55 PM PDT 24
Finished	May 23 12:38:17 PM PDT 24
Peak memory	204444 kb
Host	smart-9c6e2d6b-e937-4dbf-a581-f251b85958d5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193538586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1193538586
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.3214502077
Short name	T403
Test name
Test status
Simulation time	135873730 ps
CPU time	9.34 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:19 PM PDT 24
Peak memory	203888 kb
Host	smart-fb31bebf-80ed-4019-9e71-2b0fdbb96838
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3214502077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3214502077
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.87773533
Short name	T745
Test name
Test status
Simulation time	55420985 ps
CPU time	2.44 seconds
Started	May 23 12:38:00 PM PDT 24
Finished	May 23 12:38:05 PM PDT 24
Peak memory	203324 kb
Host	smart-ab15ca9b-7c2d-4a66-be8d-2f74806a244e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=87773533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.87773533
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.597951740
Short name	T6
Test name
Test status
Simulation time	6143044213 ps
CPU time	34.82 seconds
Started	May 23 12:38:02 PM PDT 24
Finished	May 23 12:38:38 PM PDT 24
Peak memory	203392 kb
Host	smart-07642336-fb7a-45ba-bd9c-7937bbbf9e9e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=597951740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.597951740
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3828031902
Short name	T509
Test name
Test status
Simulation time	7863074408 ps
CPU time	34.42 seconds
Started	May 23 12:37:54 PM PDT 24
Finished	May 23 12:38:30 PM PDT 24
Peak memory	203256 kb
Host	smart-1435f9ce-77f5-47a9-b64c-749f5936e27b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3828031902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3828031902
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.4186146390
Short name	T632
Test name
Test status
Simulation time	33024844 ps
CPU time	2.58 seconds
Started	May 23 12:37:57 PM PDT 24
Finished	May 23 12:38:02 PM PDT 24
Peak memory	203268 kb
Host	smart-32980d5c-8b9e-4096-a9e1-eb19b0e8d558
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186146390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.4186146390
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.830661704
Short name	T891
Test name
Test status
Simulation time	5691562875 ps
CPU time	217.52 seconds
Started	May 23 12:38:14 PM PDT 24
Finished	May 23 12:41:54 PM PDT 24
Peak memory	211540 kb
Host	smart-84639c52-72ab-4bad-8c3c-cdc07aa27394
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830661704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.830661704
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.889295762
Short name	T624
Test name
Test status
Simulation time	16741737068 ps
CPU time	180.77 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:41:15 PM PDT 24
Peak memory	206280 kb
Host	smart-7015e63a-2879-47d5-bb33-db531de4c8a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=889295762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.889295762
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2454341206
Short name	T752
Test name
Test status
Simulation time	372617596 ps
CPU time	143.27 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:40:36 PM PDT 24
Peak memory	208364 kb
Host	smart-ecdfa42d-81dc-43ac-85f4-103e4dafda0d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2454341206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.2454341206
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.893990905
Short name	T189
Test name
Test status
Simulation time	65732364 ps
CPU time	12.14 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:38:23 PM PDT 24
Peak memory	205164 kb
Host	smart-7579a4dd-f99e-4803-8b2a-371b1b7d3872
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=893990905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rese t_error.893990905
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1764182539
Short name	T806
Test name
Test status
Simulation time	716476915 ps
CPU time	19.31 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:32 PM PDT 24
Peak memory	204656 kb
Host	smart-684be6d1-bff6-497a-a4f0-3d89f83fa0e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1764182539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1764182539
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3676995536
Short name	T527
Test name
Test status
Simulation time	2651594329 ps
CPU time	39.48 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:38:55 PM PDT 24
Peak memory	205688 kb
Host	smart-d56a8bf3-5845-4179-a864-9ad9ae4129ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3676995536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3676995536
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1352751022
Short name	T219
Test name
Test status
Simulation time	61466623361 ps
CPU time	504.22 seconds
Started	May 23 12:38:08 PM PDT 24
Finished	May 23 12:46:33 PM PDT 24
Peak memory	206024 kb
Host	smart-a24f7442-6bfd-468e-90ac-0be689d94e50
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1352751022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.1352751022
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.4188619904
Short name	T573
Test name
Test status
Simulation time	1089625485 ps
CPU time	8.28 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:19 PM PDT 24
Peak memory	203644 kb
Host	smart-066f4e24-0aaa-4e48-a771-ee0565ba1559
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4188619904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4188619904
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.3973436091
Short name	T652
Test name
Test status
Simulation time	1008761006 ps
CPU time	25.66 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:38:38 PM PDT 24
Peak memory	203236 kb
Host	smart-a96fbc50-ce34-413c-9013-facfcb2dd342
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3973436091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3973436091
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.1065550512
Short name	T545
Test name
Test status
Simulation time	150738161 ps
CPU time	12.32 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:38:24 PM PDT 24
Peak memory	211448 kb
Host	smart-e43685f9-a2e3-4931-b23a-36cd4e52af21
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1065550512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1065550512
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3921291787
Short name	T138
Test name
Test status
Simulation time	9289237097 ps
CPU time	54.89 seconds
Started	May 23 12:38:14 PM PDT 24
Finished	May 23 12:39:11 PM PDT 24
Peak memory	204520 kb
Host	smart-6bae43c4-b3d0-4312-b3b1-2cc3f824e76c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921291787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3921291787
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.821566877
Short name	T705
Test name
Test status
Simulation time	11193404921 ps
CPU time	48.33 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:39:00 PM PDT 24
Peak memory	204464 kb
Host	smart-95b26788-8d21-413c-96d0-3db7481da54f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=821566877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.821566877
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.357021870
Short name	T556
Test name
Test status
Simulation time	96703939 ps
CPU time	8.27 seconds
Started	May 23 12:38:08 PM PDT 24
Finished	May 23 12:38:18 PM PDT 24
Peak memory	211440 kb
Host	smart-6d7749d3-1b52-470c-9f6a-d5eb5b4c82ac
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357021870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.357021870
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.2395358221
Short name	T366
Test name
Test status
Simulation time	2128842858 ps
CPU time	16.54 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:31 PM PDT 24
Peak memory	203756 kb
Host	smart-e08197f6-9a60-465e-997c-882b7ee3a257
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2395358221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2395358221
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.1889785046
Short name	T483
Test name
Test status
Simulation time	199638143 ps
CPU time	4.81 seconds
Started	May 23 12:38:08 PM PDT 24
Finished	May 23 12:38:14 PM PDT 24
Peak memory	203236 kb
Host	smart-1c665b5d-6de5-4286-a6d2-50129ea99a14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1889785046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1889785046
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3411064501
Short name	T131
Test name
Test status
Simulation time	6758882174 ps
CPU time	30.81 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:38:46 PM PDT 24
Peak memory	203276 kb
Host	smart-cc716402-4e3d-478d-92e1-d13cf29ef882
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411064501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3411064501
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2386404180
Short name	T599
Test name
Test status
Simulation time	4574919758 ps
CPU time	29.03 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:39 PM PDT 24
Peak memory	203332 kb
Host	smart-47e74271-5a19-4425-a8ef-2703a784d3b3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2386404180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2386404180
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1766556975
Short name	T623
Test name
Test status
Simulation time	67634906 ps
CPU time	2.29 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:15 PM PDT 24
Peak memory	203260 kb
Host	smart-8bd69e1b-c807-4857-bde3-d66ad3d7954e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766556975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1766556975
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.19458189
Short name	T77
Test name
Test status
Simulation time	6413474660 ps
CPU time	268.87 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:42:39 PM PDT 24
Peak memory	207332 kb
Host	smart-fa9d6882-e269-431b-9cbb-b858c4c0d955
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=19458189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.19458189
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.319601279
Short name	T597
Test name
Test status
Simulation time	4220060052 ps
CPU time	116.16 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:40:08 PM PDT 24
Peak memory	211472 kb
Host	smart-91c20cb0-04c7-45ae-bd75-65c5b2dc30b7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=319601279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.319601279
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2892628472
Short name	T27
Test name
Test status
Simulation time	3883883399 ps
CPU time	192.3 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:41:26 PM PDT 24
Peak memory	207984 kb
Host	smart-6afb16ee-35ec-4269-9d34-98889e1c81e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2892628472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.2892628472
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2083781165
Short name	T551
Test name
Test status
Simulation time	732987065 ps
CPU time	110.44 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:40:03 PM PDT 24
Peak memory	209836 kb
Host	smart-7dfd0cba-e5b4-4862-a705-d37b829d4139
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2083781165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2083781165
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3775547461
Short name	T753
Test name
Test status
Simulation time	113048110 ps
CPU time	14.77 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:28 PM PDT 24
Peak memory	204680 kb
Host	smart-a3af44f6-5fe9-40d3-9ebf-a862ffca6220
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775547461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3775547461
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.196404579
Short name	T589
Test name
Test status
Simulation time	612150441 ps
CPU time	37.17 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:47 PM PDT 24
Peak memory	204292 kb
Host	smart-7b76c214-e642-499c-a624-eeb0452774f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=196404579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.196404579
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1404312437
Short name	T249
Test name
Test status
Simulation time	12844049746 ps
CPU time	53.1 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:39:03 PM PDT 24
Peak memory	204776 kb
Host	smart-1a1d3c04-3633-4b87-b5e3-bbf09d8095d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1404312437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.1404312437
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.350732745
Short name	T262
Test name
Test status
Simulation time	860404568 ps
CPU time	20.82 seconds
Started	May 23 12:38:12 PM PDT 24
Finished	May 23 12:38:35 PM PDT 24
Peak memory	203588 kb
Host	smart-d46e5ac1-9ab0-4e7c-90f2-f302c59c7c1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=350732745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.350732745
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.2633948477
Short name	T598
Test name
Test status
Simulation time	1336418295 ps
CPU time	34.17 seconds
Started	May 23 12:38:14 PM PDT 24
Finished	May 23 12:38:50 PM PDT 24
Peak memory	203284 kb
Host	smart-4cf7861c-e62d-4e9a-841e-91992dbed382
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2633948477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2633948477
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.2891908466
Short name	T581
Test name
Test status
Simulation time	222137588 ps
CPU time	16.47 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:29 PM PDT 24
Peak memory	204488 kb
Host	smart-1f1ad429-9963-47f2-8bf3-4ab98ac48d35
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2891908466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2891908466
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3368491134
Short name	T117
Test name
Test status
Simulation time	95707350756 ps
CPU time	171.63 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:41:03 PM PDT 24
Peak memory	211532 kb
Host	smart-3b8b41cd-c6f0-40af-ab22-b03b072637f1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368491134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3368491134
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1568663744
Short name	T61
Test name
Test status
Simulation time	54050845776 ps
CPU time	83.47 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:39:34 PM PDT 24
Peak memory	211620 kb
Host	smart-e7492efc-b770-42b5-a9d1-f8785872386f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1568663744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1568663744
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.235473567
Short name	T127
Test name
Test status
Simulation time	131600688 ps
CPU time	11.47 seconds
Started	May 23 12:38:10 PM PDT 24
Finished	May 23 12:38:23 PM PDT 24
Peak memory	204536 kb
Host	smart-dc228ac0-443d-4ff4-8e7d-1955184ab3ac
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235473567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.235473567
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.935707454
Short name	T620
Test name
Test status
Simulation time	258791583 ps
CPU time	9.07 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:22 PM PDT 24
Peak memory	203268 kb
Host	smart-e47ab4c3-c0dc-4783-98c8-e70489ca030f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=935707454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.935707454
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.1758013164
Short name	T656
Test name
Test status
Simulation time	293309657 ps
CPU time	3.39 seconds
Started	May 23 12:38:13 PM PDT 24
Finished	May 23 12:38:18 PM PDT 24
Peak memory	203352 kb
Host	smart-70d5118f-f79b-44cb-8f91-214e228a3ddc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1758013164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1758013164
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2721833201
Short name	T55
Test name
Test status
Simulation time	16725416834 ps
CPU time	31.79 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:42 PM PDT 24
Peak memory	203288 kb
Host	smart-fe63e8e6-2cc6-4a8c-afb7-2be246453635
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721833201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2721833201
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3117301563
Short name	T256
Test name
Test status
Simulation time	8319644757 ps
CPU time	31.39 seconds
Started	May 23 12:38:08 PM PDT 24
Finished	May 23 12:38:41 PM PDT 24
Peak memory	203244 kb
Host	smart-d91d2508-ae8d-4563-a88c-a1edeebe2ede
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3117301563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3117301563
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.638552502
Short name	T630
Test name
Test status
Simulation time	68796956 ps
CPU time	2.25 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:15 PM PDT 24
Peak memory	203252 kb
Host	smart-d23a1fb9-a293-4db6-8bbd-4f4774d2f740
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638552502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.638552502
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.2502041095
Short name	T662
Test name
Test status
Simulation time	29543282 ps
CPU time	3.22 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:38:17 PM PDT 24
Peak memory	204520 kb
Host	smart-d80b796a-3711-42b0-bdc4-4de0f013eb0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2502041095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2502041095
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2062628725
Short name	T481
Test name
Test status
Simulation time	4271574884 ps
CPU time	87.44 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:39:37 PM PDT 24
Peak memory	207096 kb
Host	smart-d090ff77-5cfd-4f06-9f17-0555c869964c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2062628725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2062628725
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1977074908
Short name	T864
Test name
Test status
Simulation time	340121564 ps
CPU time	129.44 seconds
Started	May 23 12:38:16 PM PDT 24
Finished	May 23 12:40:27 PM PDT 24
Peak memory	208052 kb
Host	smart-7899bed0-7962-4a0b-a6c5-dd1d9bf6f858
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1977074908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1977074908
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.517588288
Short name	T486
Test name
Test status
Simulation time	12597096600 ps
CPU time	608.34 seconds
Started	May 23 12:38:11 PM PDT 24
Finished	May 23 12:48:22 PM PDT 24
Peak memory	219520 kb
Host	smart-3e03ffdb-86b4-4584-8610-68571c5a3b96
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=517588288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.517588288
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1352877556
Short name	T190
Test name
Test status
Simulation time	239850263 ps
CPU time	9.03 seconds
Started	May 23 12:38:09 PM PDT 24
Finished	May 23 12:38:19 PM PDT 24
Peak memory	204736 kb
Host	smart-7045c800-6e88-42a7-8b18-d0da110e4d0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1352877556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1352877556
Directory	/workspace/9.xbar_unmapped_addr/latest