Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 522 1 T1 1 T2 3 T3 1
all_values[1] 524 1 T1 2 T2 1 T8 6
all_values[2] 489 1 T8 6 T5 1 T18 9
all_values[3] 511 1 T1 2 T2 1 T8 1
all_values[4] 535 1 T3 1 T8 2 T15 1
all_values[5] 488 1 T1 1 T3 1 T8 2
all_values[6] 507 1 T1 1 T8 5 T5 1
all_values[7] 505 1 T1 4 T8 4 T5 1
all_values[8] 513 1 T1 2 T8 1 T10 1
all_values[9] 495 1 T1 1 T3 1 T8 6
all_values[10] 531 1 T1 2 T8 4 T5 1
all_values[11] 558 1 T2 2 T8 2 T5 2
all_values[12] 496 1 T3 1 T8 4 T5 1
all_values[13] 478 1 T1 3 T3 1 T8 1
all_values[14] 492 1 T8 2 T5 1 T13 2
all_values[15] 508 1 T2 3 T3 1 T8 5
all_values[16] 515 1 T1 1 T2 1 T8 2
all_values[17] 489 1 T1 1 T3 1 T8 4
all_values[18] 486 1 T1 4 T2 1 T3 1
all_values[19] 485 1 T8 4 T13 1 T15 1
all_values[20] 560 1 T1 1 T2 1 T8 7
all_values[21] 516 1 T8 1 T5 2 T10 1
all_values[22] 473 1 T1 1 T8 1 T5 1
all_values[23] 482 1 T2 1 T3 1 T8 5

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