Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1806	1			T16	1		T17	4		T30	2
all_values[1]	1784	1			T1	2		T8	1		T17	4
all_values[2]	1799	1			T1	2		T16	1		T17	3
all_values[3]	1878	1			T1	5		T17	2		T30	2
all_values[4]	1836	1			T1	1		T16	1		T17	5
all_values[5]	1833	1			T1	3		T16	2		T17	5
all_values[6]	1844	1			T1	3		T16	1		T17	2
all_values[7]	1843	1			T1	1		T16	3		T17	3
all_values[8]	1797	1			T1	2		T17	8		T18	11
all_values[9]	1863	1			T1	4		T8	1		T17	6
all_values[10]	1793	1			T1	2		T16	5		T17	2
all_values[11]	1885	1			T1	2		T16	1		T17	4
all_values[12]	1846	1			T1	1		T16	2		T17	7
all_values[13]	1825	1			T1	1		T8	1		T16	2
all_values[14]	1861	1			T1	3		T16	2		T17	3
all_values[15]	1856	1			T1	1		T16	4		T17	8
all_values[16]	1829	1			T1	3		T16	3		T17	2
all_values[17]	1781	1			T1	2		T8	1		T16	1
all_values[18]	1915	1			T1	5		T16	1		T17	4
all_values[19]	1841	1			T1	1		T16	3		T17	4
all_values[20]	1799	1			T8	1		T16	2		T17	6
all_values[21]	1797	1			T1	2		T17	9		T30	5
all_values[22]	1844	1			T1	3		T16	1		T17	3
all_values[23]	1777	1			T1	2		T8	1		T17	5
all_values[24]	1809	1			T16	2		T17	2		T30	6
all_values[25]	1785	1			T1	2		T8	1		T17	3
all_values[26]	1907	1			T1	1		T8	1		T16	4
all_values[27]	1863	1			T1	3		T17	3		T30	4
all_values[28]	1869	1			T1	3		T17	2		T30	2
all_values[29]	1869	1			T1	1		T16	2		T17	5
all_values[30]	1758	1			T1	1		T16	4		T17	4
all_values[31]	1815	1			T1	2		T8	1		T16	1
all_values[32]	1800	1			T16	3		T17	3		T30	1
all_values[33]	1864	1			T1	1		T16	3		T17	11
all_values[34]	1846	1			T1	2		T17	3		T30	7
all_values[35]	1741	1			T1	3		T16	1		T17	3
all_values[36]	1733	1			T1	1		T17	6		T30	3
all_values[37]	1843	1			T1	3		T16	4		T17	3
all_values[38]	1829	1			T1	2		T16	1		T17	7
all_values[39]	1845	1			T1	3		T16	3		T17	5
all_values[40]	1883	1			T1	2		T8	1		T17	5
all_values[41]	1917	1			T1	1		T16	1		T17	3
all_values[42]	1833	1			T1	2		T16	1		T17	4
all_values[43]	1820	1			T17	8		T30	2		T41	1
all_values[44]	1891	1			T1	1		T16	1		T17	5
all_values[45]	1898	1			T8	1		T16	2		T17	2
all_values[46]	1791	1			T1	3		T16	1		T17	9
all_values[47]	1839	1			T1	3		T8	1		T16	4
all_values[48]	1806	1			T16	1		T41	2		T18	9
all_values[49]	1819	1			T1	2		T17	5		T30	2
all_values[50]	1820	1			T1	1		T17	10		T30	1
all_values[51]	1832	1			T1	2		T16	2		T17	5
all_values[52]	1821	1			T1	5		T8	1		T16	1
all_values[53]	1881	1			T1	3		T16	1		T17	4
all_values[54]	1739	1			T1	1		T16	2		T17	9
all_values[55]	1895	1			T1	2		T16	1		T17	5
all_values[56]	1866	1			T1	2		T16	1		T17	4
all_values[57]	1921	1			T1	2		T8	1		T16	2
all_values[58]	1770	1			T1	4		T17	5		T30	1
all_values[59]	1840	1			T1	1		T8	1		T16	2
all_values[60]	1846	1			T1	1		T8	1		T16	1
all_values[61]	1840	1			T1	1		T16	1		T17	6
all_values[62]	1873	1			T8	1		T16	1		T17	6
all_values[63]	1817	1			T1	2		T16	2		T17	1