Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1885	1			T1	1		T2	13		T7	4
all_values[1]	1821	1			T1	4		T2	11		T7	10
all_values[2]	1910	1			T1	5		T2	10		T7	5
all_values[3]	1893	1			T1	3		T2	12		T7	6
all_values[4]	1910	1			T1	2		T2	12		T7	7
all_values[5]	1900	1			T1	4		T2	16		T7	4
all_values[6]	1930	1			T1	3		T2	10		T7	7
all_values[7]	1870	1			T1	2		T2	15		T7	5
all_values[8]	1886	1			T1	1		T2	11		T7	1
all_values[9]	1876	1			T1	1		T2	12		T7	4
all_values[10]	1909	1			T1	2		T2	11		T7	6
all_values[11]	1947	1			T1	3		T2	13		T7	5
all_values[12]	1900	1			T1	4		T2	14		T7	6
all_values[13]	1979	1			T1	3		T2	11		T7	7
all_values[14]	1950	1			T1	2		T2	12		T7	8
all_values[15]	1888	1			T1	5		T2	9		T7	7
all_values[16]	1917	1			T2	9		T7	2		T13	1
all_values[17]	1866	1			T1	1		T2	6		T7	1
all_values[18]	1900	1			T1	1		T2	9		T7	3
all_values[19]	1892	1			T1	6		T2	10		T7	6
all_values[20]	1941	1			T1	5		T2	16		T7	12
all_values[21]	1877	1			T1	3		T2	12		T7	6
all_values[22]	1934	1			T1	5		T2	13		T7	6
all_values[23]	1842	1			T1	5		T2	7		T7	7
all_values[24]	1920	1			T1	4		T2	11		T7	5
all_values[25]	1885	1			T1	2		T2	12		T7	6
all_values[26]	1893	1			T1	4		T2	11		T7	9
all_values[27]	1891	1			T1	5		T2	13		T7	6
all_values[28]	1833	1			T1	3		T2	8		T7	6
all_values[29]	1919	1			T1	4		T2	10		T7	6
all_values[30]	1866	1			T1	2		T2	14		T7	3
all_values[31]	1892	1			T1	2		T2	9		T7	8
all_values[32]	1907	1			T1	3		T2	10		T7	9
all_values[33]	1899	1			T1	2		T2	17		T7	2
all_values[34]	1820	1			T1	1		T2	10		T7	3
all_values[35]	1911	1			T1	1		T2	9		T7	3
all_values[36]	1928	1			T1	4		T2	8		T7	4
all_values[37]	1854	1			T1	2		T2	11		T7	2
all_values[38]	1871	1			T1	3		T2	7		T7	3
all_values[39]	1858	1			T1	2		T2	13		T7	3
all_values[40]	1902	1			T1	3		T2	16		T7	10
all_values[41]	1893	1			T1	9		T2	9		T7	6
all_values[42]	1804	1			T1	1		T2	12		T7	3
all_values[43]	1887	1			T1	5		T2	13		T7	3
all_values[44]	1888	1			T1	4		T2	10		T7	9
all_values[45]	1830	1			T1	1		T2	7		T7	2
all_values[46]	1801	1			T1	1		T2	8		T7	4
all_values[47]	1888	1			T1	5		T2	13		T7	5
all_values[48]	1879	1			T1	1		T2	11		T7	8
all_values[49]	1955	1			T1	2		T2	12		T7	5
all_values[50]	1818	1			T1	1		T2	10		T7	3
all_values[51]	1935	1			T1	5		T2	12		T7	1
all_values[52]	1946	1			T1	2		T2	15		T7	5
all_values[53]	1880	1			T1	3		T2	8		T7	3
all_values[54]	1891	1			T1	4		T2	11		T7	8
all_values[55]	1979	1			T1	6		T2	12		T7	4
all_values[56]	1921	1			T1	5		T2	13		T7	8
all_values[57]	1814	1			T1	5		T2	6		T7	5
all_values[58]	1852	1			T1	6		T2	17		T7	4
all_values[59]	1887	1			T1	3		T2	16		T7	7
all_values[60]	1938	1			T1	1		T2	12		T7	7
all_values[61]	1937	1			T1	5		T2	10		T7	3
all_values[62]	1888	1			T1	1		T2	11		T7	4
all_values[63]	1899	1			T1	2		T2	8		T7	7