Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1827	1			T10	2		T14	3		T24	18
all_values[1]	1818	1			T10	2		T24	21		T20	13
all_values[2]	1844	1			T10	4		T14	1		T24	16
all_values[3]	1889	1			T10	4		T14	2		T24	14
all_values[4]	1973	1			T10	2		T14	1		T24	18
all_values[5]	1865	1			T14	3		T24	28		T20	12
all_values[6]	1876	1			T10	1		T14	2		T24	24
all_values[7]	1890	1			T10	2		T14	1		T24	9
all_values[8]	1870	1			T10	6		T14	1		T24	20
all_values[9]	1848	1			T10	3		T14	2		T24	22
all_values[10]	1946	1			T10	4		T24	22		T20	15
all_values[11]	1911	1			T10	2		T24	17		T20	18
all_values[12]	1890	1			T10	5		T14	2		T24	16
all_values[13]	1870	1			T10	2		T14	2		T24	20
all_values[14]	1842	1			T10	4		T14	2		T24	27
all_values[15]	1832	1			T10	4		T14	2		T24	13
all_values[16]	1836	1			T10	3		T24	16		T20	20
all_values[17]	1849	1			T10	2		T14	1		T24	31
all_values[18]	1906	1			T24	14		T20	13		T66	1
all_values[19]	1912	1			T10	1		T14	3		T24	10
all_values[20]	1944	1			T10	1		T24	20		T20	14
all_values[21]	1904	1			T10	3		T24	19		T20	10
all_values[22]	1826	1			T10	2		T24	20		T20	21
all_values[23]	1920	1			T10	2		T14	2		T24	15
all_values[24]	1881	1			T10	6		T14	3		T24	17
all_values[25]	1933	1			T10	4		T14	2		T24	18
all_values[26]	1875	1			T10	4		T24	22		T20	16
all_values[27]	1885	1			T10	7		T14	1		T24	24
all_values[28]	1886	1			T10	5		T14	3		T24	24
all_values[29]	1883	1			T10	4		T24	19		T20	22
all_values[30]	1824	1			T10	6		T14	2		T24	20
all_values[31]	1849	1			T10	6		T24	19		T20	12
all_values[32]	1863	1			T10	3		T14	2		T24	10
all_values[33]	1825	1			T10	5		T14	2		T24	15
all_values[34]	1871	1			T10	4		T14	1		T24	13
all_values[35]	1885	1			T10	3		T24	20		T20	23
all_values[36]	1837	1			T10	3		T24	20		T20	18
all_values[37]	1931	1			T10	4		T14	2		T24	18
all_values[38]	1799	1			T10	3		T14	3		T24	17
all_values[39]	1939	1			T10	3		T24	18		T20	12
all_values[40]	1894	1			T10	4		T14	1		T24	20
all_values[41]	1902	1			T10	1		T24	26		T20	9
all_values[42]	1891	1			T10	2		T24	22		T20	20
all_values[43]	1841	1			T10	3		T24	22		T20	15
all_values[44]	1921	1			T10	3		T14	1		T24	22
all_values[45]	1852	1			T10	4		T24	17		T20	13
all_values[46]	1852	1			T10	4		T24	24		T20	15
all_values[47]	1900	1			T10	2		T14	2		T24	23
all_values[48]	1919	1			T10	2		T24	20		T20	16
all_values[49]	1896	1			T10	2		T24	18		T20	18
all_values[50]	1783	1			T10	4		T24	16		T20	16
all_values[51]	1925	1			T10	3		T14	2		T24	20
all_values[52]	1769	1			T10	4		T14	1		T24	14
all_values[53]	1796	1			T10	5		T24	25		T20	14
all_values[54]	1850	1			T10	4		T14	3		T24	19
all_values[55]	1833	1			T10	6		T14	1		T24	22
all_values[56]	1914	1			T10	2		T14	1		T24	18
all_values[57]	1898	1			T10	2		T14	2		T24	13
all_values[58]	1847	1			T10	3		T14	3		T24	13
all_values[59]	1867	1			T10	2		T24	17		T20	14
all_values[60]	1869	1			T10	7		T14	1		T24	22
all_values[61]	1858	1			T10	1		T14	2		T24	18
all_values[62]	1869	1			T10	4		T14	2		T24	21
all_values[63]	1817	1			T10	2		T24	18		T20	11