Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1587	1			T12	3		T17	8		T27	2
all_values[1]	1592	1			T12	2		T17	3		T20	1
all_values[2]	1612	1			T17	5		T27	1		T152	1
all_values[3]	1562	1			T17	2		T27	2		T152	2
all_values[4]	1585	1			T12	1		T152	3		T140	23
all_values[5]	1573	1			T17	1		T27	3		T152	3
all_values[6]	1526	1			T12	1		T17	2		T27	1
all_values[7]	1629	1			T12	2		T17	2		T20	1
all_values[8]	1565	1			T12	1		T17	2		T140	20
all_values[9]	1533	1			T12	2		T17	7		T152	3
all_values[10]	1613	1			T17	1		T140	32		T25	1
all_values[11]	1649	1			T27	1		T152	4		T140	29
all_values[12]	1630	1			T12	1		T17	2		T27	1
all_values[13]	1620	1			T17	3		T27	1		T152	3
all_values[14]	1545	1			T17	3		T27	1		T152	5
all_values[15]	1600	1			T17	6		T27	1		T20	2
all_values[16]	1591	1			T12	1		T17	3		T27	1
all_values[17]	1607	1			T12	2		T17	1		T20	1
all_values[18]	1585	1			T17	1		T27	2		T20	1
all_values[19]	1611	1			T17	5		T152	2		T140	33
all_values[20]	1574	1			T12	1		T17	1		T27	1
all_values[21]	1631	1			T12	3		T17	5		T27	1
all_values[22]	1590	1			T17	4		T27	1		T152	3
all_values[23]	1536	1			T12	2		T17	2		T27	1
all_values[24]	1542	1			T12	1		T17	4		T27	2
all_values[25]	1583	1			T12	2		T17	2		T152	1
all_values[26]	1613	1			T17	2		T27	2		T20	1
all_values[27]	1591	1			T12	2		T17	6		T27	1
all_values[28]	1655	1			T12	1		T27	2		T152	1
all_values[29]	1611	1			T12	3		T17	7		T27	1
all_values[30]	1565	1			T12	1		T17	1		T152	1
all_values[31]	1630	1			T12	2		T17	3		T140	20
all_values[32]	1603	1			T17	1		T152	3		T140	33
all_values[33]	1599	1			T12	2		T17	2		T27	1
all_values[34]	1586	1			T12	1		T17	3		T27	1
all_values[35]	1639	1			T17	5		T27	1		T152	2
all_values[36]	1591	1			T12	1		T17	1		T27	1
all_values[37]	1566	1			T17	2		T27	1		T20	1
all_values[38]	1559	1			T12	2		T17	2		T27	1
all_values[39]	1538	1			T12	1		T17	1		T27	2
all_values[40]	1582	1			T17	1		T27	1		T152	5
all_values[41]	1597	1			T17	5		T27	4		T152	1
all_values[42]	1622	1			T17	6		T152	1		T140	28
all_values[43]	1562	1			T12	1		T17	1		T27	2
all_values[44]	1575	1			T12	1		T17	3		T27	1
all_values[45]	1684	1			T12	4		T17	2		T27	2
all_values[46]	1527	1			T17	1		T152	4		T140	32
all_values[47]	1610	1			T17	2		T27	1		T20	1
all_values[48]	1581	1			T12	1		T17	1		T27	1
all_values[49]	1673	1			T12	1		T17	4		T27	1
all_values[50]	1604	1			T12	1		T17	3		T20	2
all_values[51]	1533	1			T12	5		T17	1		T27	1
all_values[52]	1592	1			T12	2		T17	4		T27	1
all_values[53]	1618	1			T12	1		T17	5		T20	1
all_values[54]	1595	1			T12	1		T17	4		T20	2
all_values[55]	1611	1			T17	4		T27	2		T140	30
all_values[56]	1537	1			T17	3		T140	31		T25	1
all_values[57]	1590	1			T12	1		T17	3		T27	2
all_values[58]	1480	1			T12	1		T17	6		T20	2
all_values[59]	1530	1			T17	5		T27	2		T152	1
all_values[60]	1612	1			T12	2		T17	6		T27	4
all_values[61]	1548	1			T27	3		T152	3		T140	26
all_values[62]	1607	1			T17	6		T152	4		T140	31
all_values[63]	1558	1			T12	1		T17	2		T27	2