Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 499 1 T8 6 T43 2 T67 1
all_values[1] 474 1 T8 5 T41 1 T43 1
all_values[2] 531 1 T8 9 T41 4 T65 1
all_values[3] 512 1 T3 1 T8 8 T16 1
all_values[4] 463 1 T3 1 T8 9 T16 2
all_values[5] 438 1 T3 1 T8 6 T41 1
all_values[6] 517 1 T8 6 T16 1 T65 3
all_values[7] 516 1 T8 6 T16 2 T41 1
all_values[8] 527 1 T8 8 T65 2 T21 1
all_values[9] 481 1 T8 7 T43 1 T65 2
all_values[10] 533 1 T3 1 T8 6 T16 1
all_values[11] 492 1 T3 1 T8 6 T17 1
all_values[12] 490 1 T3 1 T8 8 T16 1
all_values[13] 483 1 T3 1 T8 8 T16 2
all_values[14] 499 1 T8 5 T41 1 T65 1
all_values[15] 501 1 T8 6 T65 2 T21 1
all_values[16] 475 1 T8 5 T16 1 T65 1
all_values[17] 532 1 T3 1 T8 8 T41 1
all_values[18] 502 1 T8 7 T41 1 T65 2
all_values[19] 435 1 T3 2 T8 1 T41 1
all_values[20] 457 1 T3 1 T8 1 T16 1
all_values[21] 539 1 T8 4 T41 2 T65 1
all_values[22] 484 1 T8 3 T43 1 T65 2
all_values[23] 525 1 T8 3 T41 1 T65 4

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