Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1799	1			T8	27		T16	6		T17	6
all_values[1]	1789	1			T1	1		T8	25		T16	6
all_values[2]	1761	1			T8	25		T16	5		T17	1
all_values[3]	1764	1			T8	29		T16	8		T17	2
all_values[4]	1805	1			T1	1		T8	29		T16	3
all_values[5]	1854	1			T1	1		T8	25		T16	2
all_values[6]	1726	1			T8	24		T16	4		T17	3
all_values[7]	1785	1			T1	1		T8	27		T16	9
all_values[8]	1781	1			T1	1		T8	30		T16	2
all_values[9]	1779	1			T8	29		T16	5		T17	3
all_values[10]	1834	1			T8	44		T16	4		T17	2
all_values[11]	1813	1			T8	29		T16	4		T17	1
all_values[12]	1862	1			T8	24		T17	2		T41	3
all_values[13]	1835	1			T1	2		T8	23		T17	4
all_values[14]	1748	1			T8	32		T16	5		T17	5
all_values[15]	1789	1			T8	28		T16	3		T17	4
all_values[16]	1833	1			T1	1		T8	24		T16	5
all_values[17]	1814	1			T1	1		T8	30		T16	4
all_values[18]	1857	1			T8	21		T16	2		T17	4
all_values[19]	1799	1			T8	20		T16	5		T17	2
all_values[20]	1800	1			T8	26		T16	2		T17	2
all_values[21]	1814	1			T1	1		T8	22		T16	4
all_values[22]	1756	1			T1	2		T8	19		T16	5
all_values[23]	1774	1			T8	38		T16	3		T17	4
all_values[24]	1857	1			T8	28		T16	4		T17	7
all_values[25]	1850	1			T8	33		T16	2		T17	4
all_values[26]	1796	1			T1	1		T8	22		T16	7
all_values[27]	1838	1			T1	1		T8	31		T16	4
all_values[28]	1812	1			T1	2		T8	33		T16	3
all_values[29]	1809	1			T1	1		T8	28		T16	3
all_values[30]	1866	1			T1	1		T8	28		T16	3
all_values[31]	1820	1			T8	24		T16	5		T17	5
all_values[32]	1790	1			T1	1		T8	20		T16	2
all_values[33]	1886	1			T8	25		T16	3		T17	2
all_values[34]	1783	1			T1	1		T8	18		T16	3
all_values[35]	1822	1			T8	33		T16	5		T17	6
all_values[36]	1809	1			T8	29		T16	2		T17	1
all_values[37]	1824	1			T1	3		T8	29		T16	2
all_values[38]	1833	1			T1	1		T8	26		T16	4
all_values[39]	1747	1			T8	28		T16	5		T17	2
all_values[40]	1792	1			T8	26		T16	5		T17	4
all_values[41]	1801	1			T8	21		T16	2		T17	4
all_values[42]	1773	1			T1	2		T8	27		T16	1
all_values[43]	1810	1			T8	24		T16	3		T17	9
all_values[44]	1821	1			T1	1		T8	33		T16	3
all_values[45]	1757	1			T1	1		T8	9		T16	3
all_values[46]	1800	1			T8	21		T16	4		T41	3
all_values[47]	1778	1			T8	36		T16	3		T17	4
all_values[48]	1802	1			T8	30		T16	4		T17	2
all_values[49]	1770	1			T1	1		T8	28		T16	5
all_values[50]	1893	1			T8	19		T16	3		T17	2
all_values[51]	1765	1			T1	1		T8	18		T17	2
all_values[52]	1877	1			T1	1		T8	25		T16	3
all_values[53]	1765	1			T8	23		T16	4		T17	2
all_values[54]	1746	1			T8	24		T16	6		T17	6
all_values[55]	1782	1			T8	22		T16	1		T17	6
all_values[56]	1811	1			T8	28		T16	3		T17	1
all_values[57]	1778	1			T8	30		T16	3		T17	6
all_values[58]	1855	1			T1	1		T8	19		T16	4
all_values[59]	1801	1			T1	1		T8	22		T16	3
all_values[60]	1870	1			T8	33		T16	5		T17	3
all_values[61]	1802	1			T8	19		T16	6		T17	4
all_values[62]	1797	1			T8	28		T16	4		T17	3
all_values[63]	1934	1			T1	3		T8	31		T16	5