Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1763	1			T9	33		T13	5		T15	1
all_values[1]	1793	1			T9	33		T13	4		T14	5
all_values[2]	1755	1			T9	26		T13	1		T14	4
all_values[3]	1794	1			T9	37		T13	5		T14	2
all_values[4]	1699	1			T9	22		T13	5		T14	2
all_values[5]	1804	1			T9	24		T13	5		T15	1
all_values[6]	1702	1			T9	29		T13	5		T14	5
all_values[7]	1750	1			T9	34		T13	2		T14	6
all_values[8]	1763	1			T9	34		T13	2		T14	1
all_values[9]	1707	1			T9	26		T13	5		T14	2
all_values[10]	1649	1			T9	28		T13	2		T14	1
all_values[11]	1803	1			T9	22		T13	3		T14	6
all_values[12]	1624	1			T9	25		T13	1		T14	3
all_values[13]	1802	1			T9	43		T13	2		T14	2
all_values[14]	1751	1			T9	31		T13	2		T14	3
all_values[15]	1723	1			T9	21		T13	1		T14	4
all_values[16]	1737	1			T9	27		T13	2		T14	3
all_values[17]	1749	1			T9	28		T13	5		T14	3
all_values[18]	1734	1			T9	36		T14	2		T17	20
all_values[19]	1721	1			T9	27		T13	4		T14	3
all_values[20]	1752	1			T9	30		T13	4		T14	6
all_values[21]	1761	1			T9	25		T13	4		T14	6
all_values[22]	1755	1			T9	32		T13	2		T14	2
all_values[23]	1746	1			T9	29		T13	3		T14	2
all_values[24]	1736	1			T9	31		T13	2		T14	5
all_values[25]	1789	1			T9	30		T13	5		T14	4
all_values[26]	1735	1			T9	36		T13	5		T14	3
all_values[27]	1818	1			T9	34		T13	2		T14	3
all_values[28]	1761	1			T9	25		T13	6		T14	3
all_values[29]	1719	1			T9	22		T13	1		T14	4
all_values[30]	1667	1			T9	37		T13	4		T14	3
all_values[31]	1750	1			T9	20		T13	1		T14	4
all_values[32]	1749	1			T9	22		T13	3		T14	2
all_values[33]	1671	1			T9	21		T13	6		T14	2
all_values[34]	1721	1			T9	36		T13	4		T14	4
all_values[35]	1687	1			T9	22		T13	4		T14	3
all_values[36]	1812	1			T9	30		T13	6		T14	2
all_values[37]	1813	1			T9	27		T13	4		T14	7
all_values[38]	1721	1			T9	33		T13	7		T14	1
all_values[39]	1762	1			T9	23		T13	3		T14	1
all_values[40]	1699	1			T9	30		T13	3		T14	3
all_values[41]	1737	1			T9	38		T13	6		T15	1
all_values[42]	1751	1			T9	22		T13	10		T14	4
all_values[43]	1823	1			T9	34		T13	2		T14	7
all_values[44]	1759	1			T9	35		T13	3		T14	4
all_values[45]	1773	1			T9	23		T13	6		T14	3
all_values[46]	1693	1			T9	24		T13	6		T14	1
all_values[47]	1788	1			T9	28		T13	4		T14	3
all_values[48]	1800	1			T9	24		T13	3		T14	5
all_values[49]	1798	1			T9	33		T13	3		T14	3
all_values[50]	1815	1			T9	35		T13	2		T14	2
all_values[51]	1838	1			T9	27		T13	4		T14	2
all_values[52]	1818	1			T9	30		T13	1		T14	4
all_values[53]	1761	1			T9	31		T13	4		T14	4
all_values[54]	1749	1			T9	34		T13	2		T14	3
all_values[55]	1739	1			T9	32		T13	2		T14	6
all_values[56]	1772	1			T9	30		T13	4		T14	4
all_values[57]	1688	1			T9	30		T13	3		T14	5
all_values[58]	1801	1			T9	35		T13	4		T14	2
all_values[59]	1753	1			T9	29		T13	1		T14	4
all_values[60]	1729	1			T9	28		T13	5		T14	3
all_values[61]	1702	1			T9	22		T13	2		T14	4
all_values[62]	1725	1			T9	29		T13	2		T14	2
all_values[63]	1839	1			T9	38		T13	5		T14	4