Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.02 99.26 88.89 98.80 95.88 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T762 /workspace/coverage/xbar_build_mode/23.xbar_stress_all.4143812001 Jun 05 04:05:51 PM PDT 24 Jun 05 04:07:56 PM PDT 24 1013806883 ps
T763 /workspace/coverage/xbar_build_mode/13.xbar_stress_all.369085726 Jun 05 04:04:59 PM PDT 24 Jun 05 04:06:30 PM PDT 24 2955202317 ps
T764 /workspace/coverage/xbar_build_mode/25.xbar_smoke.1076012483 Jun 05 04:05:58 PM PDT 24 Jun 05 04:06:02 PM PDT 24 131729227 ps
T765 /workspace/coverage/xbar_build_mode/30.xbar_random.2190110739 Jun 05 04:06:29 PM PDT 24 Jun 05 04:06:55 PM PDT 24 618517145 ps
T766 /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2050044093 Jun 05 04:06:42 PM PDT 24 Jun 05 04:07:35 PM PDT 24 5176758741 ps
T767 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.4125172991 Jun 05 04:04:35 PM PDT 24 Jun 05 04:09:37 PM PDT 24 1521367070 ps
T768 /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1842944307 Jun 05 04:07:47 PM PDT 24 Jun 05 04:07:52 PM PDT 24 29622158 ps
T769 /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3106647759 Jun 05 04:04:26 PM PDT 24 Jun 05 04:04:55 PM PDT 24 3468483717 ps
T770 /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1891665701 Jun 05 04:07:27 PM PDT 24 Jun 05 04:07:55 PM PDT 24 651612168 ps
T771 /workspace/coverage/xbar_build_mode/33.xbar_error_random.2716743510 Jun 05 04:06:42 PM PDT 24 Jun 05 04:07:00 PM PDT 24 1253844221 ps
T246 /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1782383936 Jun 05 04:07:46 PM PDT 24 Jun 05 04:08:36 PM PDT 24 12132082803 ps
T772 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.923223823 Jun 05 04:04:49 PM PDT 24 Jun 05 04:06:58 PM PDT 24 423903747 ps
T773 /workspace/coverage/xbar_build_mode/10.xbar_error_random.1539666449 Jun 05 04:04:37 PM PDT 24 Jun 05 04:04:50 PM PDT 24 658110922 ps
T774 /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.429487557 Jun 05 04:06:01 PM PDT 24 Jun 05 04:09:25 PM PDT 24 1160654280 ps
T775 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.142704262 Jun 05 04:08:20 PM PDT 24 Jun 05 04:10:12 PM PDT 24 437833528 ps
T776 /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.506200314 Jun 05 04:06:27 PM PDT 24 Jun 05 04:06:37 PM PDT 24 96627898 ps
T777 /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.485707859 Jun 05 04:03:59 PM PDT 24 Jun 05 04:04:08 PM PDT 24 213118479 ps
T778 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3610557161 Jun 05 04:05:35 PM PDT 24 Jun 05 04:07:30 PM PDT 24 5877818589 ps
T779 /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3732363885 Jun 05 04:03:50 PM PDT 24 Jun 05 04:04:29 PM PDT 24 10632855161 ps
T780 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3037608173 Jun 05 04:08:21 PM PDT 24 Jun 05 04:08:24 PM PDT 24 51435367 ps
T781 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.842221603 Jun 05 04:07:46 PM PDT 24 Jun 05 04:09:06 PM PDT 24 3268048873 ps
T782 /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1765225091 Jun 05 04:07:31 PM PDT 24 Jun 05 04:07:35 PM PDT 24 24786560 ps
T783 /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1360551935 Jun 05 04:06:42 PM PDT 24 Jun 05 04:07:11 PM PDT 24 9690723085 ps
T784 /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1211204246 Jun 05 04:06:50 PM PDT 24 Jun 05 04:07:05 PM PDT 24 492041920 ps
T785 /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.4195022766 Jun 05 04:06:58 PM PDT 24 Jun 05 04:07:01 PM PDT 24 26820532 ps
T128 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1419480904 Jun 05 04:06:57 PM PDT 24 Jun 05 04:07:52 PM PDT 24 7013372271 ps
T786 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3372995016 Jun 05 04:05:17 PM PDT 24 Jun 05 04:09:46 PM PDT 24 3974621423 ps
T129 /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1196017332 Jun 05 04:05:42 PM PDT 24 Jun 05 04:08:58 PM PDT 24 7799312665 ps
T787 /workspace/coverage/xbar_build_mode/9.xbar_same_source.3801357580 Jun 05 04:04:30 PM PDT 24 Jun 05 04:04:47 PM PDT 24 280431454 ps
T788 /workspace/coverage/xbar_build_mode/15.xbar_smoke.1760042190 Jun 05 04:05:15 PM PDT 24 Jun 05 04:05:20 PM PDT 24 524209800 ps
T789 /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3062156646 Jun 05 04:06:00 PM PDT 24 Jun 05 04:06:24 PM PDT 24 3385289841 ps
T59 /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4222353780 Jun 05 04:06:26 PM PDT 24 Jun 05 04:07:01 PM PDT 24 10659679667 ps
T223 /workspace/coverage/xbar_build_mode/39.xbar_random.3108886695 Jun 05 04:07:20 PM PDT 24 Jun 05 04:07:44 PM PDT 24 589705187 ps
T790 /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3575195427 Jun 05 04:06:49 PM PDT 24 Jun 05 04:07:15 PM PDT 24 2645146347 ps
T791 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.825734369 Jun 05 04:05:21 PM PDT 24 Jun 05 04:06:09 PM PDT 24 625865186 ps
T792 /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2946143694 Jun 05 04:03:57 PM PDT 24 Jun 05 04:05:00 PM PDT 24 2495706785 ps
T793 /workspace/coverage/xbar_build_mode/19.xbar_same_source.898952596 Jun 05 04:05:29 PM PDT 24 Jun 05 04:05:47 PM PDT 24 2388739220 ps
T794 /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2405018125 Jun 05 04:06:42 PM PDT 24 Jun 05 04:07:44 PM PDT 24 15117872400 ps
T795 /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3486437639 Jun 05 04:04:25 PM PDT 24 Jun 05 04:12:52 PM PDT 24 2131429159 ps
T796 /workspace/coverage/xbar_build_mode/13.xbar_random.1417694424 Jun 05 04:05:02 PM PDT 24 Jun 05 04:05:07 PM PDT 24 239839432 ps
T797 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2365605100 Jun 05 04:05:49 PM PDT 24 Jun 05 04:07:50 PM PDT 24 1770828660 ps
T798 /workspace/coverage/xbar_build_mode/2.xbar_random.927517711 Jun 05 04:03:59 PM PDT 24 Jun 05 04:04:26 PM PDT 24 909089387 ps
T799 /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.4161826401 Jun 05 04:04:07 PM PDT 24 Jun 05 04:04:34 PM PDT 24 3364791772 ps
T800 /workspace/coverage/xbar_build_mode/14.xbar_error_random.2463948547 Jun 05 04:04:58 PM PDT 24 Jun 05 04:05:38 PM PDT 24 7964685220 ps
T801 /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.83764198 Jun 05 04:07:54 PM PDT 24 Jun 05 04:08:12 PM PDT 24 134377635 ps
T802 /workspace/coverage/xbar_build_mode/14.xbar_stress_all.463411269 Jun 05 04:05:14 PM PDT 24 Jun 05 04:07:27 PM PDT 24 4769941031 ps
T803 /workspace/coverage/xbar_build_mode/7.xbar_same_source.631386643 Jun 05 04:04:24 PM PDT 24 Jun 05 04:04:30 PM PDT 24 235544376 ps
T804 /workspace/coverage/xbar_build_mode/35.xbar_error_random.3574646136 Jun 05 04:06:59 PM PDT 24 Jun 05 04:07:10 PM PDT 24 530222055 ps
T805 /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.566250407 Jun 05 04:08:21 PM PDT 24 Jun 05 04:08:35 PM PDT 24 104337102 ps
T806 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2518767397 Jun 05 04:04:11 PM PDT 24 Jun 05 04:07:30 PM PDT 24 2973242172 ps
T807 /workspace/coverage/xbar_build_mode/4.xbar_same_source.1352151647 Jun 05 04:04:07 PM PDT 24 Jun 05 04:04:18 PM PDT 24 567347287 ps
T808 /workspace/coverage/xbar_build_mode/29.xbar_error_random.1846844984 Jun 05 04:06:26 PM PDT 24 Jun 05 04:06:33 PM PDT 24 156110513 ps
T809 /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1322984185 Jun 05 04:05:51 PM PDT 24 Jun 05 04:06:24 PM PDT 24 24020168577 ps
T810 /workspace/coverage/xbar_build_mode/2.xbar_smoke.2412675520 Jun 05 04:04:00 PM PDT 24 Jun 05 04:04:05 PM PDT 24 671791505 ps
T811 /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.501688152 Jun 05 04:08:24 PM PDT 24 Jun 05 04:08:26 PM PDT 24 28470971 ps
T812 /workspace/coverage/xbar_build_mode/34.xbar_same_source.3567398792 Jun 05 04:06:49 PM PDT 24 Jun 05 04:07:09 PM PDT 24 960777978 ps
T813 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3468642387 Jun 05 04:07:47 PM PDT 24 Jun 05 04:10:57 PM PDT 24 22940495380 ps
T814 /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2005059807 Jun 05 04:06:43 PM PDT 24 Jun 05 04:07:29 PM PDT 24 28168373575 ps
T815 /workspace/coverage/xbar_build_mode/21.xbar_random.2500067180 Jun 05 04:05:35 PM PDT 24 Jun 05 04:05:39 PM PDT 24 173326075 ps
T816 /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2512097637 Jun 05 04:08:14 PM PDT 24 Jun 05 04:08:47 PM PDT 24 8397655017 ps
T817 /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.4182036967 Jun 05 04:07:20 PM PDT 24 Jun 05 04:07:24 PM PDT 24 27693541 ps
T818 /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1063504173 Jun 05 04:04:25 PM PDT 24 Jun 05 04:04:38 PM PDT 24 305526480 ps
T819 /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3682079739 Jun 05 04:04:20 PM PDT 24 Jun 05 04:04:40 PM PDT 24 2647357112 ps
T820 /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2570569885 Jun 05 04:04:58 PM PDT 24 Jun 05 04:08:59 PM PDT 24 55721054180 ps
T821 /workspace/coverage/xbar_build_mode/18.xbar_error_random.3908968596 Jun 05 04:05:20 PM PDT 24 Jun 05 04:05:35 PM PDT 24 187185077 ps
T822 /workspace/coverage/xbar_build_mode/28.xbar_error_random.1575361300 Jun 05 04:06:16 PM PDT 24 Jun 05 04:06:19 PM PDT 24 16451588 ps
T823 /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3351934547 Jun 05 04:05:32 PM PDT 24 Jun 05 04:05:34 PM PDT 24 43615305 ps
T824 /workspace/coverage/xbar_build_mode/21.xbar_smoke.298477161 Jun 05 04:05:35 PM PDT 24 Jun 05 04:05:39 PM PDT 24 310935485 ps
T825 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3449932179 Jun 05 04:08:15 PM PDT 24 Jun 05 04:08:45 PM PDT 24 315429316 ps
T826 /workspace/coverage/xbar_build_mode/3.xbar_error_random.185554609 Jun 05 04:04:12 PM PDT 24 Jun 05 04:04:21 PM PDT 24 65687702 ps
T827 /workspace/coverage/xbar_build_mode/28.xbar_smoke.1546275643 Jun 05 04:06:18 PM PDT 24 Jun 05 04:06:23 PM PDT 24 585825699 ps
T828 /workspace/coverage/xbar_build_mode/9.xbar_random.3457156647 Jun 05 04:04:25 PM PDT 24 Jun 05 04:04:37 PM PDT 24 353467869 ps
T829 /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3523726170 Jun 05 04:05:30 PM PDT 24 Jun 05 04:10:17 PM PDT 24 12567820189 ps
T830 /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.863970141 Jun 05 04:04:09 PM PDT 24 Jun 05 04:04:34 PM PDT 24 5005682722 ps
T831 /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1924015128 Jun 05 04:06:43 PM PDT 24 Jun 05 04:07:08 PM PDT 24 3025102443 ps
T832 /workspace/coverage/xbar_build_mode/26.xbar_smoke.688647110 Jun 05 04:06:07 PM PDT 24 Jun 05 04:06:11 PM PDT 24 743911675 ps
T833 /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3952247082 Jun 05 04:03:59 PM PDT 24 Jun 05 04:04:33 PM PDT 24 390377581 ps
T834 /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1724070324 Jun 05 04:04:33 PM PDT 24 Jun 05 04:04:37 PM PDT 24 45564967 ps
T835 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1511217072 Jun 05 04:07:53 PM PDT 24 Jun 05 04:08:28 PM PDT 24 1284099982 ps
T836 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3671455763 Jun 05 04:06:41 PM PDT 24 Jun 05 04:16:18 PM PDT 24 15484792838 ps
T837 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.470098607 Jun 05 04:06:26 PM PDT 24 Jun 05 04:06:50 PM PDT 24 265501976 ps
T838 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1360146603 Jun 05 04:07:30 PM PDT 24 Jun 05 04:07:43 PM PDT 24 190498733 ps
T839 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.537397701 Jun 05 04:04:33 PM PDT 24 Jun 05 04:05:30 PM PDT 24 1696037721 ps
T840 /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2541615405 Jun 05 04:07:10 PM PDT 24 Jun 05 04:07:36 PM PDT 24 2262216650 ps
T841 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.739637626 Jun 05 04:07:45 PM PDT 24 Jun 05 04:19:23 PM PDT 24 101888700743 ps
T842 /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4012359468 Jun 05 04:06:50 PM PDT 24 Jun 05 04:07:06 PM PDT 24 448339487 ps
T843 /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.13717895 Jun 05 04:07:31 PM PDT 24 Jun 05 04:07:47 PM PDT 24 348376927 ps
T844 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2842081163 Jun 05 04:07:45 PM PDT 24 Jun 05 04:08:49 PM PDT 24 92609341 ps
T845 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2423873209 Jun 05 04:07:37 PM PDT 24 Jun 05 04:08:00 PM PDT 24 3916157145 ps
T846 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.4283914944 Jun 05 04:04:42 PM PDT 24 Jun 05 04:07:51 PM PDT 24 26494742011 ps
T847 /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1228880102 Jun 05 04:05:27 PM PDT 24 Jun 05 04:05:30 PM PDT 24 45023224 ps
T848 /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2598058116 Jun 05 04:07:36 PM PDT 24 Jun 05 04:08:04 PM PDT 24 261786556 ps
T849 /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1128002057 Jun 05 04:06:06 PM PDT 24 Jun 05 04:06:21 PM PDT 24 126817927 ps
T850 /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2739554143 Jun 05 04:06:19 PM PDT 24 Jun 05 04:13:17 PM PDT 24 145238842055 ps
T851 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1746487980 Jun 05 04:06:26 PM PDT 24 Jun 05 04:07:36 PM PDT 24 2009423051 ps
T852 /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.4074654188 Jun 05 04:05:34 PM PDT 24 Jun 05 04:05:45 PM PDT 24 363409763 ps
T853 /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.687061131 Jun 05 04:06:47 PM PDT 24 Jun 05 04:07:04 PM PDT 24 119030395 ps
T854 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.864592469 Jun 05 04:07:19 PM PDT 24 Jun 05 04:07:57 PM PDT 24 1014217235 ps
T855 /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.136969828 Jun 05 04:06:49 PM PDT 24 Jun 05 04:07:17 PM PDT 24 907755262 ps
T182 /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1696521170 Jun 05 04:05:40 PM PDT 24 Jun 05 04:07:50 PM PDT 24 99162967602 ps
T856 /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2415969793 Jun 05 04:07:01 PM PDT 24 Jun 05 04:07:04 PM PDT 24 44249014 ps
T857 /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2477674069 Jun 05 04:06:07 PM PDT 24 Jun 05 04:06:16 PM PDT 24 389003943 ps
T858 /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3950610709 Jun 05 04:05:49 PM PDT 24 Jun 05 04:05:53 PM PDT 24 32418539 ps
T130 /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.47829199 Jun 05 04:04:09 PM PDT 24 Jun 05 04:09:10 PM PDT 24 41745573200 ps
T859 /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3487854672 Jun 05 04:07:45 PM PDT 24 Jun 05 04:07:48 PM PDT 24 170367218 ps
T860 /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3465835499 Jun 05 04:05:12 PM PDT 24 Jun 05 04:05:16 PM PDT 24 193491612 ps
T861 /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2392475703 Jun 05 04:06:58 PM PDT 24 Jun 05 04:09:39 PM PDT 24 57318633444 ps
T862 /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1665000336 Jun 05 04:06:59 PM PDT 24 Jun 05 04:09:29 PM PDT 24 22863491782 ps
T863 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2622867621 Jun 05 04:07:21 PM PDT 24 Jun 05 04:15:36 PM PDT 24 58266638347 ps
T864 /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1262019641 Jun 05 04:05:18 PM PDT 24 Jun 05 04:05:48 PM PDT 24 4720364377 ps
T865 /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2539367436 Jun 05 04:06:07 PM PDT 24 Jun 05 04:09:39 PM PDT 24 30545154509 ps
T866 /workspace/coverage/xbar_build_mode/6.xbar_stress_all.742175042 Jun 05 04:04:18 PM PDT 24 Jun 05 04:05:30 PM PDT 24 936682139 ps
T867 /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3638693109 Jun 05 04:08:20 PM PDT 24 Jun 05 04:08:45 PM PDT 24 5111390718 ps
T868 /workspace/coverage/xbar_build_mode/44.xbar_random.2804605756 Jun 05 04:07:55 PM PDT 24 Jun 05 04:08:28 PM PDT 24 773828529 ps
T869 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2196558850 Jun 05 04:07:21 PM PDT 24 Jun 05 04:07:27 PM PDT 24 39432856 ps
T870 /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.4218265349 Jun 05 04:08:05 PM PDT 24 Jun 05 04:08:08 PM PDT 24 52104242 ps
T871 /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2063295605 Jun 05 04:04:25 PM PDT 24 Jun 05 04:04:46 PM PDT 24 176541484 ps
T257 /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1313860747 Jun 05 04:04:10 PM PDT 24 Jun 05 04:06:04 PM PDT 24 12849687041 ps
T872 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.39033190 Jun 05 04:06:59 PM PDT 24 Jun 05 04:09:03 PM PDT 24 16805677631 ps
T179 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3374424042 Jun 05 04:05:49 PM PDT 24 Jun 05 04:06:30 PM PDT 24 1627693192 ps
T873 /workspace/coverage/xbar_build_mode/40.xbar_smoke.3218461903 Jun 05 04:07:34 PM PDT 24 Jun 05 04:07:36 PM PDT 24 35621170 ps
T874 /workspace/coverage/xbar_build_mode/23.xbar_random.1550243989 Jun 05 04:05:50 PM PDT 24 Jun 05 04:06:14 PM PDT 24 422437716 ps
T875 /workspace/coverage/xbar_build_mode/35.xbar_same_source.1095859186 Jun 05 04:06:59 PM PDT 24 Jun 05 04:07:10 PM PDT 24 790196874 ps
T876 /workspace/coverage/xbar_build_mode/31.xbar_smoke.73046840 Jun 05 04:06:35 PM PDT 24 Jun 05 04:06:39 PM PDT 24 165833563 ps
T877 /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1273188582 Jun 05 04:04:29 PM PDT 24 Jun 05 04:04:45 PM PDT 24 477128005 ps
T205 /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2013859654 Jun 05 04:05:18 PM PDT 24 Jun 05 04:07:45 PM PDT 24 1177575855 ps
T878 /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3513516883 Jun 05 04:04:12 PM PDT 24 Jun 05 04:04:22 PM PDT 24 62515090 ps
T879 /workspace/coverage/xbar_build_mode/33.xbar_smoke.387452827 Jun 05 04:06:45 PM PDT 24 Jun 05 04:06:49 PM PDT 24 128103996 ps
T880 /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.739409556 Jun 05 04:06:59 PM PDT 24 Jun 05 04:07:28 PM PDT 24 8678265713 ps
T881 /workspace/coverage/xbar_build_mode/28.xbar_random.1621216762 Jun 05 04:06:18 PM PDT 24 Jun 05 04:06:22 PM PDT 24 38298708 ps
T882 /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2185541915 Jun 05 04:04:25 PM PDT 24 Jun 05 04:04:39 PM PDT 24 471454457 ps
T883 /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2514270121 Jun 05 04:07:36 PM PDT 24 Jun 05 04:07:58 PM PDT 24 2303081385 ps
T884 /workspace/coverage/xbar_build_mode/46.xbar_smoke.1855058593 Jun 05 04:07:59 PM PDT 24 Jun 05 04:08:03 PM PDT 24 191668526 ps
T885 /workspace/coverage/xbar_build_mode/12.xbar_smoke.1969745955 Jun 05 04:04:41 PM PDT 24 Jun 05 04:04:44 PM PDT 24 127770482 ps
T886 /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2701014919 Jun 05 04:07:21 PM PDT 24 Jun 05 04:07:42 PM PDT 24 528257529 ps
T887 /workspace/coverage/xbar_build_mode/6.xbar_smoke.1231070730 Jun 05 04:04:14 PM PDT 24 Jun 05 04:04:19 PM PDT 24 180441660 ps
T888 /workspace/coverage/xbar_build_mode/39.xbar_error_random.1012552878 Jun 05 04:07:30 PM PDT 24 Jun 05 04:07:41 PM PDT 24 93104756 ps
T889 /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.122646128 Jun 05 04:06:42 PM PDT 24 Jun 05 04:06:45 PM PDT 24 22995203 ps
T890 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.725117697 Jun 05 04:05:14 PM PDT 24 Jun 05 04:07:12 PM PDT 24 481279751 ps
T891 /workspace/coverage/xbar_build_mode/11.xbar_error_random.2701182775 Jun 05 04:04:43 PM PDT 24 Jun 05 04:05:14 PM PDT 24 451198711 ps
T892 /workspace/coverage/xbar_build_mode/36.xbar_smoke.1489217042 Jun 05 04:06:58 PM PDT 24 Jun 05 04:07:03 PM PDT 24 140438219 ps
T893 /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3495203640 Jun 05 04:04:38 PM PDT 24 Jun 05 04:08:06 PM PDT 24 34136219359 ps
T894 /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1640017987 Jun 05 04:06:59 PM PDT 24 Jun 05 04:07:30 PM PDT 24 5954401062 ps
T895 /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1693250381 Jun 05 04:07:55 PM PDT 24 Jun 05 04:07:58 PM PDT 24 85575464 ps
T896 /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3174342073 Jun 05 04:07:19 PM PDT 24 Jun 05 04:10:55 PM PDT 24 37235778736 ps
T897 /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1520861422 Jun 05 04:05:26 PM PDT 24 Jun 05 04:05:52 PM PDT 24 251156181 ps
T898 /workspace/coverage/xbar_build_mode/5.xbar_error_random.3866520508 Jun 05 04:04:15 PM PDT 24 Jun 05 04:04:28 PM PDT 24 252065742 ps
T899 /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3985975721 Jun 05 04:04:58 PM PDT 24 Jun 05 04:05:47 PM PDT 24 37483011530 ps
T900 /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1250380740 Jun 05 04:07:12 PM PDT 24 Jun 05 04:07:41 PM PDT 24 1271334252 ps
T131 /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1243639965 Jun 05 04:03:51 PM PDT 24 Jun 05 04:07:04 PM PDT 24 29370708569 ps

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1957158721
Short name T13
Test name
Test status
Simulation time 6091971711 ps
CPU time 204.81 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:09:00 PM PDT 24
Peak memory 210596 kb
Host smart-17081c57-21f9-468f-924a-26294be268d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1957158721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1957158721
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1816299432
Short name T256
Test name
Test status
Simulation time 84271448988 ps
CPU time 582.38 seconds
Started Jun 05 04:06:43 PM PDT 24
Finished Jun 05 04:16:26 PM PDT 24
Peak memory 207072 kb
Host smart-401898d8-6d87-447d-ac88-5dba0b7352af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1816299432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.1816299432
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1918528715
Short name T63
Test name
Test status
Simulation time 63484067176 ps
CPU time 394.68 seconds
Started Jun 05 04:05:10 PM PDT 24
Finished Jun 05 04:11:45 PM PDT 24
Peak memory 211444 kb
Host smart-38f3083a-1bbc-415d-b36d-1ade6eb652d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1918528715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1918528715
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1508099312
Short name T17
Test name
Test status
Simulation time 2388859479 ps
CPU time 398.86 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 226160 kb
Host smart-74f844dc-1fdb-4f3d-8167-af85597ed3f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1508099312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.1508099312
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3403538142
Short name T366
Test name
Test status
Simulation time 42162603628 ps
CPU time 360.75 seconds
Started Jun 05 04:08:06 PM PDT 24
Finished Jun 05 04:14:08 PM PDT 24
Peak memory 205808 kb
Host smart-bba650d1-41af-4ad8-ac35-a4baa73fbfac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3403538142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.3403538142
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.577163310
Short name T4
Test name
Test status
Simulation time 3847116024 ps
CPU time 29.37 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:04:45 PM PDT 24
Peak memory 203248 kb
Host smart-f746ba84-a21b-423d-948b-dd9ca40373ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=577163310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.577163310
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.366036809
Short name T18
Test name
Test status
Simulation time 6866703047 ps
CPU time 505.34 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 219652 kb
Host smart-56fd5893-5023-44ed-b74c-258fdba7d500
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=366036809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand
_reset.366036809
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3869316003
Short name T86
Test name
Test status
Simulation time 4264836664 ps
CPU time 59.56 seconds
Started Jun 05 04:06:57 PM PDT 24
Finished Jun 05 04:07:57 PM PDT 24
Peak memory 211420 kb
Host smart-24b8ea4c-6b60-489e-ad75-2193f69b6512
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3869316003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3869316003
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.680152598
Short name T159
Test name
Test status
Simulation time 7512551558 ps
CPU time 30.76 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:05:31 PM PDT 24
Peak memory 203488 kb
Host smart-15a27576-304c-4dc9-9b04-17d3eeb83d15
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=680152598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.680152598
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.391657863
Short name T127
Test name
Test status
Simulation time 58831846555 ps
CPU time 285.61 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:08:44 PM PDT 24
Peak memory 206448 kb
Host smart-965aad95-07e3-43f4-9590-a4146ccaa1ff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=391657863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow
_rsp.391657863
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1271671646
Short name T132
Test name
Test status
Simulation time 6365241148 ps
CPU time 69.91 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:09:30 PM PDT 24
Peak memory 211424 kb
Host smart-5fbae9da-162a-47ba-964b-aee3f106aed6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1271671646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1271671646
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2238891512
Short name T37
Test name
Test status
Simulation time 2972187140 ps
CPU time 281.07 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:09:08 PM PDT 24
Peak memory 209848 kb
Host smart-e8ac1545-17fa-42b3-89ab-a2123f250375
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2238891512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.2238891512
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2719582991
Short name T103
Test name
Test status
Simulation time 53812820506 ps
CPU time 520.41 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:12:56 PM PDT 24
Peak memory 211460 kb
Host smart-083868c6-2866-44ff-bb8c-171d55a686b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2719582991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.2719582991
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.906094757
Short name T75
Test name
Test status
Simulation time 868230366 ps
CPU time 198.24 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:07:39 PM PDT 24
Peak memory 209076 kb
Host smart-847147d2-d598-41b8-b49d-bf7786d9ca0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=906094757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.906094757
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.85483840
Short name T64
Test name
Test status
Simulation time 1831030930 ps
CPU time 251.61 seconds
Started Jun 05 04:05:33 PM PDT 24
Finished Jun 05 04:09:45 PM PDT 24
Peak memory 208452 kb
Host smart-c140f296-75bb-4569-be32-c6ba7ca0462f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85483840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_
reset.85483840
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1288580244
Short name T26
Test name
Test status
Simulation time 10144313435 ps
CPU time 506.18 seconds
Started Jun 05 04:05:25 PM PDT 24
Finished Jun 05 04:13:52 PM PDT 24
Peak memory 219616 kb
Host smart-cb460b49-6def-4a5f-afe2-0b245e2a4665
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1288580244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.1288580244
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1930895089
Short name T33
Test name
Test status
Simulation time 4393214482 ps
CPU time 196.3 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:09:25 PM PDT 24
Peak memory 208496 kb
Host smart-d276b762-0505-41aa-8055-2c2025f6cb74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1930895089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1930895089
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3199231843
Short name T27
Test name
Test status
Simulation time 851973990 ps
CPU time 293.15 seconds
Started Jun 05 04:05:13 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 219544 kb
Host smart-ef11c0fe-64ee-471d-8e3a-e0feb70e3ea8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3199231843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.3199231843
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1373327251
Short name T36
Test name
Test status
Simulation time 3752189538 ps
CPU time 366.63 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:13:17 PM PDT 24
Peak memory 210288 kb
Host smart-d9b6d0e7-ce82-4094-b68f-504643a5ee89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1373327251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.1373327251
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3506865863
Short name T255
Test name
Test status
Simulation time 1327981226 ps
CPU time 261.55 seconds
Started Jun 05 04:04:43 PM PDT 24
Finished Jun 05 04:09:05 PM PDT 24
Peak memory 210804 kb
Host smart-5ad37b36-6b6e-42d2-ae31-f0f634860342
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3506865863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.3506865863
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.655824215
Short name T105
Test name
Test status
Simulation time 46341881816 ps
CPU time 407.67 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:11:23 PM PDT 24
Peak memory 211296 kb
Host smart-a8127a60-e2ba-4e58-a7e1-217dcb2495ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=655824215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slo
w_rsp.655824215
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3572212895
Short name T155
Test name
Test status
Simulation time 804761410 ps
CPU time 24.01 seconds
Started Jun 05 04:04:50 PM PDT 24
Finished Jun 05 04:05:14 PM PDT 24
Peak memory 205676 kb
Host smart-f7c496ee-72f6-4f1c-b037-2b88441839d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3572212895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3572212895
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1019723507
Short name T564
Test name
Test status
Simulation time 423368541 ps
CPU time 54.68 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:04:45 PM PDT 24
Peak memory 211380 kb
Host smart-520360ec-bfc9-4dd8-a0f0-51fbe73968f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1019723507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1019723507
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1243639965
Short name T131
Test name
Test status
Simulation time 29370708569 ps
CPU time 192.4 seconds
Started Jun 05 04:03:51 PM PDT 24
Finished Jun 05 04:07:04 PM PDT 24
Peak memory 206044 kb
Host smart-22490673-827a-40b0-8688-f17a62071731
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1243639965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.1243639965
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3191715627
Short name T550
Test name
Test status
Simulation time 1501642727 ps
CPU time 10.9 seconds
Started Jun 05 04:03:47 PM PDT 24
Finished Jun 05 04:03:58 PM PDT 24
Peak memory 203348 kb
Host smart-c29f1f66-4f30-43d6-a601-9aea30a55fef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3191715627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3191715627
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.2796994959
Short name T8
Test name
Test status
Simulation time 165927474 ps
CPU time 4.88 seconds
Started Jun 05 04:03:51 PM PDT 24
Finished Jun 05 04:03:57 PM PDT 24
Peak memory 203212 kb
Host smart-522f5e86-8011-477c-842d-e2d140506e08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2796994959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2796994959
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.773422563
Short name T195
Test name
Test status
Simulation time 469384582 ps
CPU time 9.81 seconds
Started Jun 05 04:03:53 PM PDT 24
Finished Jun 05 04:04:03 PM PDT 24
Peak memory 204292 kb
Host smart-ed417f2a-08d8-4c10-aadf-2beaece41b46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=773422563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.773422563
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3272204314
Short name T216
Test name
Test status
Simulation time 41326977157 ps
CPU time 252.84 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:08:04 PM PDT 24
Peak memory 204976 kb
Host smart-eb2d42a8-d1a3-494c-9cf6-f8e3c6fea551
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272204314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3272204314
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2785259864
Short name T646
Test name
Test status
Simulation time 27804456721 ps
CPU time 80.13 seconds
Started Jun 05 04:03:52 PM PDT 24
Finished Jun 05 04:05:12 PM PDT 24
Peak memory 211444 kb
Host smart-cba88c74-cc24-4682-85b0-7b36c63ac743
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2785259864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2785259864
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2062833898
Short name T198
Test name
Test status
Simulation time 249155355 ps
CPU time 29.52 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:04:20 PM PDT 24
Peak memory 211384 kb
Host smart-3d5fc84b-504a-4239-af66-ccad9988460d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062833898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2062833898
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.2412095081
Short name T191
Test name
Test status
Simulation time 9427121146 ps
CPU time 39.56 seconds
Started Jun 05 04:03:51 PM PDT 24
Finished Jun 05 04:04:32 PM PDT 24
Peak memory 211396 kb
Host smart-4afeaeab-956e-4532-a6fe-8db5b2d1d35c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2412095081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2412095081
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.1267746558
Short name T600
Test name
Test status
Simulation time 338801877 ps
CPU time 3.92 seconds
Started Jun 05 04:03:51 PM PDT 24
Finished Jun 05 04:03:56 PM PDT 24
Peak memory 203120 kb
Host smart-6addb76d-5ce4-412a-8804-e8cdf2982470
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1267746558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1267746558
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2965038899
Short name T754
Test name
Test status
Simulation time 8108364230 ps
CPU time 35.3 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:04:26 PM PDT 24
Peak memory 203100 kb
Host smart-3cf0854f-63db-4639-9cf7-9b0f275a6423
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965038899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2965038899
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3586837988
Short name T297
Test name
Test status
Simulation time 9072377565 ps
CPU time 34.62 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:04:25 PM PDT 24
Peak memory 203188 kb
Host smart-9a839619-39b4-412f-a59d-d6a524a754fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3586837988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3586837988
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1300303028
Short name T734
Test name
Test status
Simulation time 41934259 ps
CPU time 2.19 seconds
Started Jun 05 04:03:49 PM PDT 24
Finished Jun 05 04:03:52 PM PDT 24
Peak memory 203152 kb
Host smart-d1192d3a-8157-4b05-9895-f2bb7b257129
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300303028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1300303028
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3501768807
Short name T594
Test name
Test status
Simulation time 974677154 ps
CPU time 53.91 seconds
Started Jun 05 04:03:49 PM PDT 24
Finished Jun 05 04:04:43 PM PDT 24
Peak memory 206300 kb
Host smart-b66c28de-e5a9-427f-b8bb-37d7ac7910d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3501768807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3501768807
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2037651105
Short name T532
Test name
Test status
Simulation time 598297699 ps
CPU time 57.87 seconds
Started Jun 05 04:03:51 PM PDT 24
Finished Jun 05 04:04:50 PM PDT 24
Peak memory 206784 kb
Host smart-db17125f-a4dd-4586-829a-fe3225a7c373
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2037651105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2037651105
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1751576280
Short name T466
Test name
Test status
Simulation time 7377397902 ps
CPU time 209.35 seconds
Started Jun 05 04:03:51 PM PDT 24
Finished Jun 05 04:07:21 PM PDT 24
Peak memory 207316 kb
Host smart-9ca2b91a-0ba3-487a-998e-353ea13b1cc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1751576280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.1751576280
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.805621032
Short name T513
Test name
Test status
Simulation time 1132425234 ps
CPU time 245.27 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:07:56 PM PDT 24
Peak memory 219588 kb
Host smart-81389b87-d046-43f0-b10e-c3b30d08d045
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=805621032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese
t_error.805621032
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1326018010
Short name T645
Test name
Test status
Simulation time 1031339029 ps
CPU time 15.61 seconds
Started Jun 05 04:03:51 PM PDT 24
Finished Jun 05 04:04:07 PM PDT 24
Peak memory 211376 kb
Host smart-8f9b83c4-0b8e-4ee0-b83c-dcc49660c81f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1326018010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1326018010
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2455966010
Short name T455
Test name
Test status
Simulation time 345371374 ps
CPU time 43.97 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:04:43 PM PDT 24
Peak memory 206364 kb
Host smart-fdd70ac8-6f01-40d7-a0cc-4d02a76d14c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2455966010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2455966010
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1888844022
Short name T713
Test name
Test status
Simulation time 40652767351 ps
CPU time 238.51 seconds
Started Jun 05 04:03:56 PM PDT 24
Finished Jun 05 04:07:56 PM PDT 24
Peak memory 206140 kb
Host smart-9ccc8c0e-6f00-4deb-9844-1257a2eec24b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1888844022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.1888844022
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.337864430
Short name T486
Test name
Test status
Simulation time 316522588 ps
CPU time 14.16 seconds
Started Jun 05 04:03:56 PM PDT 24
Finished Jun 05 04:04:11 PM PDT 24
Peak memory 203580 kb
Host smart-6f1056c1-c224-4766-89db-0703e62f21d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=337864430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.337864430
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.1288680160
Short name T627
Test name
Test status
Simulation time 997000635 ps
CPU time 28.43 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:04:28 PM PDT 24
Peak memory 203176 kb
Host smart-7339b6d6-8d31-46c2-b471-2d0fe631a8e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1288680160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1288680160
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.753891916
Short name T317
Test name
Test status
Simulation time 939892175 ps
CPU time 23.85 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:04:15 PM PDT 24
Peak memory 211604 kb
Host smart-3f407773-615a-4ce5-a1a1-ec0f899b2abf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=753891916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.753891916
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.831293330
Short name T222
Test name
Test status
Simulation time 54344542843 ps
CPU time 188.05 seconds
Started Jun 05 04:03:53 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 205016 kb
Host smart-15439ecf-b53a-4245-9c95-22cb0e6f7496
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=831293330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.831293330
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3732363885
Short name T779
Test name
Test status
Simulation time 10632855161 ps
CPU time 37.78 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:04:29 PM PDT 24
Peak memory 211420 kb
Host smart-97fd498d-3b2d-42f7-b0d2-9cfb31aacdae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3732363885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3732363885
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.485763015
Short name T375
Test name
Test status
Simulation time 48998699 ps
CPU time 4.11 seconds
Started Jun 05 04:03:50 PM PDT 24
Finished Jun 05 04:03:56 PM PDT 24
Peak memory 203200 kb
Host smart-c256d36c-a69c-43d4-af98-b696c1890233
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485763015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.485763015
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.4163580489
Short name T686
Test name
Test status
Simulation time 249913578 ps
CPU time 14.49 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:04:13 PM PDT 24
Peak memory 203268 kb
Host smart-989ff99b-4523-4383-80aa-f3ef55e39c87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4163580489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4163580489
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.2930108421
Short name T135
Test name
Test status
Simulation time 202939603 ps
CPU time 3.37 seconds
Started Jun 05 04:03:49 PM PDT 24
Finished Jun 05 04:03:53 PM PDT 24
Peak memory 203184 kb
Host smart-7203d01d-0292-40b3-bac3-0a6955f83d2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2930108421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2930108421
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1329229450
Short name T432
Test name
Test status
Simulation time 19195660515 ps
CPU time 42.85 seconds
Started Jun 05 04:03:52 PM PDT 24
Finished Jun 05 04:04:35 PM PDT 24
Peak memory 203244 kb
Host smart-04cf0cc4-15d9-4cfa-bcf3-b96c1e8b1188
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329229450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1329229450
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2243557182
Short name T48
Test name
Test status
Simulation time 9153455944 ps
CPU time 26.59 seconds
Started Jun 05 04:03:52 PM PDT 24
Finished Jun 05 04:04:20 PM PDT 24
Peak memory 203224 kb
Host smart-fbb42f39-ac13-4d9e-b093-d261e776a6ff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2243557182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2243557182
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3445269610
Short name T265
Test name
Test status
Simulation time 36107464 ps
CPU time 2.69 seconds
Started Jun 05 04:03:53 PM PDT 24
Finished Jun 05 04:03:56 PM PDT 24
Peak memory 203148 kb
Host smart-bb43205e-4642-4086-80f3-c57accc84e3a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445269610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3445269610
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2946143694
Short name T792
Test name
Test status
Simulation time 2495706785 ps
CPU time 62 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:05:00 PM PDT 24
Peak memory 207456 kb
Host smart-b8e9c76f-5c2e-4143-87dc-d5ba70bc9a11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2946143694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2946143694
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3674256736
Short name T465
Test name
Test status
Simulation time 69871341 ps
CPU time 1.94 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:04:02 PM PDT 24
Peak memory 203168 kb
Host smart-3e5d59e6-35a1-4638-8c99-a768f6d6f035
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3674256736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3674256736
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2020971552
Short name T420
Test name
Test status
Simulation time 1816230544 ps
CPU time 291.12 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 207896 kb
Host smart-a11fd9e2-5e3b-4722-b7e3-f10d7812baac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2020971552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.2020971552
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1487987644
Short name T549
Test name
Test status
Simulation time 114963794 ps
CPU time 7.1 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:04:07 PM PDT 24
Peak memory 204264 kb
Host smart-36a30c7f-245e-4fcc-b0f8-19eec9bca1de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1487987644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.1487987644
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3376331996
Short name T412
Test name
Test status
Simulation time 1371370562 ps
CPU time 16.6 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:04:14 PM PDT 24
Peak memory 211388 kb
Host smart-2f927c5c-dde4-4ad7-a02f-9cbe220a85f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3376331996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3376331996
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.812353256
Short name T53
Test name
Test status
Simulation time 479425544 ps
CPU time 18.97 seconds
Started Jun 05 04:04:32 PM PDT 24
Finished Jun 05 04:04:52 PM PDT 24
Peak memory 204292 kb
Host smart-b8dda145-cc0e-4955-9b3c-9bb9ee0e474d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=812353256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.812353256
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4022535020
Short name T423
Test name
Test status
Simulation time 807547598 ps
CPU time 30.22 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:05:05 PM PDT 24
Peak memory 203700 kb
Host smart-ffacd742-0535-455d-88dc-bc44dbc6e060
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4022535020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.4022535020
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.1539666449
Short name T773
Test name
Test status
Simulation time 658110922 ps
CPU time 12.84 seconds
Started Jun 05 04:04:37 PM PDT 24
Finished Jun 05 04:04:50 PM PDT 24
Peak memory 203156 kb
Host smart-661356a1-f48f-4446-a2d9-12ac7ea5e469
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1539666449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1539666449
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.359225440
Short name T657
Test name
Test status
Simulation time 87423308 ps
CPU time 3.58 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:04:39 PM PDT 24
Peak memory 203760 kb
Host smart-8eec336e-7b2b-4393-bad0-ee17fc2c25a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=359225440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.359225440
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2188416028
Short name T684
Test name
Test status
Simulation time 105168345576 ps
CPU time 256.73 seconds
Started Jun 05 04:04:35 PM PDT 24
Finished Jun 05 04:08:53 PM PDT 24
Peak memory 211404 kb
Host smart-0944732f-314e-492a-ad42-8abecbc92e15
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188416028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2188416028
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2324048148
Short name T330
Test name
Test status
Simulation time 11096238778 ps
CPU time 94.36 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:06:10 PM PDT 24
Peak memory 204616 kb
Host smart-88e6274e-71ed-4caf-8006-912a0d706e9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2324048148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2324048148
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2229007940
Short name T252
Test name
Test status
Simulation time 195002046 ps
CPU time 22.81 seconds
Started Jun 05 04:04:37 PM PDT 24
Finished Jun 05 04:05:00 PM PDT 24
Peak memory 204728 kb
Host smart-1b66d94e-f50b-4c7b-bcea-99e444bea149
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229007940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2229007940
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.1810368534
Short name T574
Test name
Test status
Simulation time 4260062202 ps
CPU time 21.59 seconds
Started Jun 05 04:04:36 PM PDT 24
Finished Jun 05 04:04:58 PM PDT 24
Peak memory 203844 kb
Host smart-cc00fe8e-040f-492e-9f6f-5d80186efe91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1810368534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1810368534
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.9824047
Short name T38
Test name
Test status
Simulation time 24449763 ps
CPU time 2.28 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:04:29 PM PDT 24
Peak memory 203176 kb
Host smart-f066978a-979b-450a-82be-56b676766303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9824047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.9824047
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1237392719
Short name T341
Test name
Test status
Simulation time 13307964934 ps
CPU time 34.65 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:05:10 PM PDT 24
Peak memory 203268 kb
Host smart-fb87d376-fa4e-48c9-8e2e-f63219e81ef8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237392719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1237392719
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.499958652
Short name T557
Test name
Test status
Simulation time 9070359360 ps
CPU time 30.96 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:05:06 PM PDT 24
Peak memory 203260 kb
Host smart-00852f5a-2f8e-499c-b8ce-0eb2dccda3a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=499958652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.499958652
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1724070324
Short name T834
Test name
Test status
Simulation time 45564967 ps
CPU time 2.35 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:04:37 PM PDT 24
Peak memory 203188 kb
Host smart-1344a477-b806-46f9-85e2-eef407c395c9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724070324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1724070324
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.4081796714
Short name T249
Test name
Test status
Simulation time 718245244 ps
CPU time 9.85 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:04:45 PM PDT 24
Peak memory 211256 kb
Host smart-070aa40f-347b-4c55-bab3-d47d6d3ea58d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4081796714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4081796714
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.537397701
Short name T839
Test name
Test status
Simulation time 1696037721 ps
CPU time 56.05 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:05:30 PM PDT 24
Peak memory 206644 kb
Host smart-62fb379d-e165-4136-b74a-aadfb9f683e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=537397701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.537397701
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.177627320
Short name T229
Test name
Test status
Simulation time 181492946 ps
CPU time 66.5 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:05:40 PM PDT 24
Peak memory 206860 kb
Host smart-d1ad9b6e-8ed4-4e75-b030-f519c8f81240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=177627320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand
_reset.177627320
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.4125172991
Short name T767
Test name
Test status
Simulation time 1521367070 ps
CPU time 301.04 seconds
Started Jun 05 04:04:35 PM PDT 24
Finished Jun 05 04:09:37 PM PDT 24
Peak memory 219580 kb
Host smart-c2e5558a-11ef-4a3e-a3fb-311a875e01ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4125172991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.4125172991
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.3648265031
Short name T709
Test name
Test status
Simulation time 570426495 ps
CPU time 18.99 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:04:52 PM PDT 24
Peak memory 204648 kb
Host smart-60260dd8-f4a1-41e9-9f93-716c7596e161
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3648265031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3648265031
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1404709110
Short name T350
Test name
Test status
Simulation time 372938033 ps
CPU time 4.48 seconds
Started Jun 05 04:04:37 PM PDT 24
Finished Jun 05 04:04:42 PM PDT 24
Peak memory 203196 kb
Host smart-da2d3d94-e5c9-4de9-8b74-1b31e5d43f97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1404709110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1404709110
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1569133111
Short name T109
Test name
Test status
Simulation time 56134726867 ps
CPU time 442.13 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 211444 kb
Host smart-83dbf71e-c299-494a-89a1-c19150f75e64
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1569133111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.1569133111
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3816015770
Short name T658
Test name
Test status
Simulation time 43857894 ps
CPU time 3.5 seconds
Started Jun 05 04:04:42 PM PDT 24
Finished Jun 05 04:04:46 PM PDT 24
Peak memory 203360 kb
Host smart-8ac8f114-a4be-4bba-b5d1-d43010ddc06f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3816015770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3816015770
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.2701182775
Short name T891
Test name
Test status
Simulation time 451198711 ps
CPU time 30.53 seconds
Started Jun 05 04:04:43 PM PDT 24
Finished Jun 05 04:05:14 PM PDT 24
Peak memory 203216 kb
Host smart-c3c7fa5b-36f7-4cde-949d-4643640154e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2701182775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2701182775
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.2101980098
Short name T340
Test name
Test status
Simulation time 239280259 ps
CPU time 21.97 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:04:57 PM PDT 24
Peak memory 204348 kb
Host smart-4692b91e-e209-4825-8651-8580d6e304cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2101980098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2101980098
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3495203640
Short name T893
Test name
Test status
Simulation time 34136219359 ps
CPU time 207.36 seconds
Started Jun 05 04:04:38 PM PDT 24
Finished Jun 05 04:08:06 PM PDT 24
Peak memory 204488 kb
Host smart-d40c1f90-e030-4533-87a1-1b63de842b45
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495203640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3495203640
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.905174582
Short name T690
Test name
Test status
Simulation time 13578722012 ps
CPU time 76.96 seconds
Started Jun 05 04:04:37 PM PDT 24
Finished Jun 05 04:05:55 PM PDT 24
Peak memory 211444 kb
Host smart-fad656a2-1352-4f95-b0c9-acdcb881eeea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=905174582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.905174582
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.700183511
Short name T176
Test name
Test status
Simulation time 185197128 ps
CPU time 23.23 seconds
Started Jun 05 04:04:32 PM PDT 24
Finished Jun 05 04:04:56 PM PDT 24
Peak memory 211384 kb
Host smart-b97f8b6d-7164-4fed-97f4-b6e53f037a2a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700183511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.700183511
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.3543006540
Short name T506
Test name
Test status
Simulation time 1125022932 ps
CPU time 9.52 seconds
Started Jun 05 04:04:43 PM PDT 24
Finished Jun 05 04:04:53 PM PDT 24
Peak memory 203656 kb
Host smart-6637e5f0-d98b-4815-9016-750807f439da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3543006540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3543006540
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.520859695
Short name T47
Test name
Test status
Simulation time 109193140 ps
CPU time 2.83 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:04:38 PM PDT 24
Peak memory 203176 kb
Host smart-8fb90470-c7bb-43b7-ae4c-7f01bd778ba6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=520859695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.520859695
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2730994781
Short name T474
Test name
Test status
Simulation time 11392727267 ps
CPU time 36.63 seconds
Started Jun 05 04:04:32 PM PDT 24
Finished Jun 05 04:05:10 PM PDT 24
Peak memory 203172 kb
Host smart-77275e75-3c3d-4aa0-96c2-56a4c73be2aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730994781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2730994781
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.866713139
Short name T451
Test name
Test status
Simulation time 5383283197 ps
CPU time 31.81 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:05:05 PM PDT 24
Peak memory 203260 kb
Host smart-ef1e3fac-7184-4aac-a06d-4c001838dc39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=866713139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.866713139
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2119515780
Short name T143
Test name
Test status
Simulation time 38008144 ps
CPU time 2.08 seconds
Started Jun 05 04:04:33 PM PDT 24
Finished Jun 05 04:04:36 PM PDT 24
Peak memory 203152 kb
Host smart-6a9cfa53-f4aa-4e18-bdd5-a955a418e10f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119515780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2119515780
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1513220989
Short name T457
Test name
Test status
Simulation time 1412442982 ps
CPU time 145.86 seconds
Started Jun 05 04:04:40 PM PDT 24
Finished Jun 05 04:07:07 PM PDT 24
Peak memory 207316 kb
Host smart-5af8ed32-18fc-4925-a458-1bd50ac0198d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513220989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1513220989
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.4283914944
Short name T846
Test name
Test status
Simulation time 26494742011 ps
CPU time 188.64 seconds
Started Jun 05 04:04:42 PM PDT 24
Finished Jun 05 04:07:51 PM PDT 24
Peak memory 211296 kb
Host smart-89944b95-a890-4a94-bdb6-64040fb213fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4283914944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.4283914944
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2811178260
Short name T525
Test name
Test status
Simulation time 1563602753 ps
CPU time 365.55 seconds
Started Jun 05 04:04:41 PM PDT 24
Finished Jun 05 04:10:47 PM PDT 24
Peak memory 211276 kb
Host smart-7ff13bff-e264-434f-a5ac-0f123ebd0a8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2811178260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.2811178260
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3480109546
Short name T631
Test name
Test status
Simulation time 1598156244 ps
CPU time 26.12 seconds
Started Jun 05 04:04:40 PM PDT 24
Finished Jun 05 04:05:07 PM PDT 24
Peak memory 204608 kb
Host smart-0888530e-32fa-4fc2-a1dc-c1c276de4cf9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3480109546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3480109546
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3473191866
Short name T3
Test name
Test status
Simulation time 21889770364 ps
CPU time 171.38 seconds
Started Jun 05 04:04:50 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 206132 kb
Host smart-5a56cd99-5516-4d25-b8e5-8c4399ab0fcc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3473191866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.3473191866
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.367538831
Short name T700
Test name
Test status
Simulation time 492813700 ps
CPU time 16.8 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:05:17 PM PDT 24
Peak memory 203660 kb
Host smart-7437848a-a9fa-4d46-ac18-837e667ee366
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=367538831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.367538831
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1381453638
Short name T298
Test name
Test status
Simulation time 142299134 ps
CPU time 7.68 seconds
Started Jun 05 04:04:49 PM PDT 24
Finished Jun 05 04:04:57 PM PDT 24
Peak memory 203196 kb
Host smart-b1fa5fb7-f9af-4a12-8bec-888d2b758d2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1381453638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1381453638
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.3238194875
Short name T58
Test name
Test status
Simulation time 1285121466 ps
CPU time 35.46 seconds
Started Jun 05 04:04:48 PM PDT 24
Finished Jun 05 04:05:24 PM PDT 24
Peak memory 211364 kb
Host smart-4cded5e1-56f3-42f8-b0cb-d9f9c6980707
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3238194875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3238194875
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2777519909
Short name T541
Test name
Test status
Simulation time 18417430338 ps
CPU time 121.33 seconds
Started Jun 05 04:04:50 PM PDT 24
Finished Jun 05 04:06:51 PM PDT 24
Peak memory 211456 kb
Host smart-6416d0f0-d72c-406c-bb07-ad7f5799241e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777519909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2777519909
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1261885530
Short name T322
Test name
Test status
Simulation time 18631725046 ps
CPU time 132.38 seconds
Started Jun 05 04:04:49 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 204416 kb
Host smart-b5434cc6-e709-4543-99f2-18e237d9e702
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1261885530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1261885530
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.964714431
Short name T165
Test name
Test status
Simulation time 210278536 ps
CPU time 26.66 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:26 PM PDT 24
Peak memory 211604 kb
Host smart-62b3d41a-b696-41c3-a08e-6144f80d0372
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964714431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.964714431
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.540709513
Short name T294
Test name
Test status
Simulation time 130540801 ps
CPU time 11.46 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:05:12 PM PDT 24
Peak memory 203940 kb
Host smart-62b74613-123f-4f03-9e56-81680563f458
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=540709513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.540709513
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.1969745955
Short name T885
Test name
Test status
Simulation time 127770482 ps
CPU time 2.65 seconds
Started Jun 05 04:04:41 PM PDT 24
Finished Jun 05 04:04:44 PM PDT 24
Peak memory 203180 kb
Host smart-816bb66b-d59a-4899-80ab-0b8d5063285d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1969745955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1969745955
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2568740825
Short name T108
Test name
Test status
Simulation time 6169227351 ps
CPU time 36.31 seconds
Started Jun 05 04:04:40 PM PDT 24
Finished Jun 05 04:05:17 PM PDT 24
Peak memory 203252 kb
Host smart-ce24a755-30cf-4617-bc8a-c0d9d0885b47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568740825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2568740825
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.789913034
Short name T601
Test name
Test status
Simulation time 4443700402 ps
CPU time 38 seconds
Started Jun 05 04:04:51 PM PDT 24
Finished Jun 05 04:05:29 PM PDT 24
Peak memory 203208 kb
Host smart-91c4ed2e-e280-4ec2-8f07-1622f52d166b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=789913034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.789913034
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2790674767
Short name T251
Test name
Test status
Simulation time 60097076 ps
CPU time 2.39 seconds
Started Jun 05 04:04:41 PM PDT 24
Finished Jun 05 04:04:44 PM PDT 24
Peak memory 203112 kb
Host smart-e319e8c3-3e53-4a95-8b45-aa1be7ef9d28
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790674767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2790674767
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3474861558
Short name T247
Test name
Test status
Simulation time 4057606907 ps
CPU time 166.93 seconds
Started Jun 05 04:04:48 PM PDT 24
Finished Jun 05 04:07:35 PM PDT 24
Peak memory 208316 kb
Host smart-cb515853-0dac-4452-8647-60ccea0b84ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3474861558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3474861558
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1141157306
Short name T400
Test name
Test status
Simulation time 1461718473 ps
CPU time 18.56 seconds
Started Jun 05 04:04:48 PM PDT 24
Finished Jun 05 04:05:07 PM PDT 24
Peak memory 203928 kb
Host smart-2efcfc46-2ab8-4527-86e3-89def52d7dc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1141157306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1141157306
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.923223823
Short name T772
Test name
Test status
Simulation time 423903747 ps
CPU time 128.16 seconds
Started Jun 05 04:04:49 PM PDT 24
Finished Jun 05 04:06:58 PM PDT 24
Peak memory 208128 kb
Host smart-6f010b85-ed9b-48f9-95fc-84f7bf80ddc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=923223823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand
_reset.923223823
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1233274809
Short name T320
Test name
Test status
Simulation time 367358226 ps
CPU time 97.02 seconds
Started Jun 05 04:04:49 PM PDT 24
Finished Jun 05 04:06:26 PM PDT 24
Peak memory 209328 kb
Host smart-54982c88-9563-4870-b76c-6ec78e5fc24b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1233274809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.1233274809
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.619977007
Short name T166
Test name
Test status
Simulation time 1211896298 ps
CPU time 25.94 seconds
Started Jun 05 04:04:57 PM PDT 24
Finished Jun 05 04:05:23 PM PDT 24
Peak memory 204752 kb
Host smart-83a424b4-16d5-438b-8840-ef5aaaeede2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=619977007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.619977007
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3606329632
Short name T140
Test name
Test status
Simulation time 1447392701 ps
CPU time 42.65 seconds
Started Jun 05 04:04:56 PM PDT 24
Finished Jun 05 04:05:40 PM PDT 24
Peak memory 204612 kb
Host smart-f2a7ba5d-59f8-4dd7-8168-27e45b42a66b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3606329632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3606329632
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2089485946
Short name T426
Test name
Test status
Simulation time 49619486157 ps
CPU time 317.51 seconds
Started Jun 05 04:04:57 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 206620 kb
Host smart-eab903d8-e360-46f7-bf0a-75e21c84ed1e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2089485946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.2089485946
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1924564939
Short name T80
Test name
Test status
Simulation time 175096056 ps
CPU time 16.05 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:05:17 PM PDT 24
Peak memory 203440 kb
Host smart-12e1e704-af4a-4e16-a342-03615569135e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1924564939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1924564939
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.2875267939
Short name T337
Test name
Test status
Simulation time 525877072 ps
CPU time 11.82 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:10 PM PDT 24
Peak memory 203168 kb
Host smart-6256102a-f00c-4603-a1bd-8c8a519dbd88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2875267939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2875267939
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.1417694424
Short name T796
Test name
Test status
Simulation time 239839432 ps
CPU time 4.7 seconds
Started Jun 05 04:05:02 PM PDT 24
Finished Jun 05 04:05:07 PM PDT 24
Peak memory 204104 kb
Host smart-df6745a9-5be8-4722-a4d7-5d07be9394aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1417694424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1417694424
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3985975721
Short name T899
Test name
Test status
Simulation time 37483011530 ps
CPU time 47.51 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:47 PM PDT 24
Peak memory 203992 kb
Host smart-c588e200-0504-42a5-888c-a032f005b44f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985975721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3985975721
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2678705550
Short name T660
Test name
Test status
Simulation time 1221826783 ps
CPU time 12.5 seconds
Started Jun 05 04:05:02 PM PDT 24
Finished Jun 05 04:05:15 PM PDT 24
Peak memory 203436 kb
Host smart-cc7e948c-39c3-413e-b967-3fce3c5edc08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2678705550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2678705550
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3208676302
Short name T679
Test name
Test status
Simulation time 86068485 ps
CPU time 6.59 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:05 PM PDT 24
Peak memory 204304 kb
Host smart-d84bd1f6-0e56-40cc-b313-1e3e9ee44e35
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208676302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3208676302
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.2808521
Short name T667
Test name
Test status
Simulation time 847400523 ps
CPU time 18.12 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:05:18 PM PDT 24
Peak memory 203444 kb
Host smart-4be80888-57c8-4ac1-a221-3fa5e1e16edf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2808521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2808521
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.872782928
Short name T52
Test name
Test status
Simulation time 128685831 ps
CPU time 2.76 seconds
Started Jun 05 04:04:48 PM PDT 24
Finished Jun 05 04:04:51 PM PDT 24
Peak memory 203172 kb
Host smart-22b66bba-3fe6-483a-9425-003fb688bc1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=872782928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.872782928
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4084711137
Short name T422
Test name
Test status
Simulation time 8826464293 ps
CPU time 37.43 seconds
Started Jun 05 04:04:48 PM PDT 24
Finished Jun 05 04:05:26 PM PDT 24
Peak memory 203200 kb
Host smart-96add380-a6bb-4e0b-b375-19065e3d43b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4084711137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4084711137
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1190632593
Short name T283
Test name
Test status
Simulation time 34525051 ps
CPU time 1.99 seconds
Started Jun 05 04:04:50 PM PDT 24
Finished Jun 05 04:04:53 PM PDT 24
Peak memory 203060 kb
Host smart-8755eaae-bba8-46da-966f-f6457da42f96
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190632593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1190632593
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.369085726
Short name T763
Test name
Test status
Simulation time 2955202317 ps
CPU time 90.16 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:06:30 PM PDT 24
Peak memory 206292 kb
Host smart-d35f6afb-8e66-48c6-9a70-7302055ba810
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=369085726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.369085726
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3585591224
Short name T703
Test name
Test status
Simulation time 7501939150 ps
CPU time 148.82 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:07:28 PM PDT 24
Peak memory 205484 kb
Host smart-de445d44-d04f-4bf9-9cea-32ecf1436d69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585591224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3585591224
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.107216134
Short name T224
Test name
Test status
Simulation time 137587588 ps
CPU time 65.97 seconds
Started Jun 05 04:04:57 PM PDT 24
Finished Jun 05 04:06:03 PM PDT 24
Peak memory 206688 kb
Host smart-34d96dc0-5dee-4b1f-8e00-d05a48c378b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107216134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand
_reset.107216134
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.406376184
Short name T477
Test name
Test status
Simulation time 3000337092 ps
CPU time 507.42 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:13:27 PM PDT 24
Peak memory 219640 kb
Host smart-4d93dae9-602a-41d3-a56a-e6955f5ebbf4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=406376184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res
et_error.406376184
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1435378882
Short name T379
Test name
Test status
Simulation time 250575179 ps
CPU time 7.67 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:05:08 PM PDT 24
Peak memory 211340 kb
Host smart-4ca2e92f-690f-4f8b-856d-035839f58cc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1435378882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1435378882
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1519558797
Short name T608
Test name
Test status
Simulation time 2064418716 ps
CPU time 48.57 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:48 PM PDT 24
Peak memory 211380 kb
Host smart-e0da3e36-c3b6-4991-ba59-906c204bfaba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1519558797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1519558797
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3379883485
Short name T55
Test name
Test status
Simulation time 136950352443 ps
CPU time 562.9 seconds
Started Jun 05 04:05:02 PM PDT 24
Finished Jun 05 04:14:25 PM PDT 24
Peak memory 211680 kb
Host smart-95b72af2-22e4-40c1-ac96-2e352616ad1e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3379883485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.3379883485
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3465835499
Short name T860
Test name
Test status
Simulation time 193491612 ps
CPU time 2.68 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:05:16 PM PDT 24
Peak memory 203192 kb
Host smart-5fe98520-b3ed-4c80-b973-12339e850c29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3465835499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3465835499
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.2463948547
Short name T800
Test name
Test status
Simulation time 7964685220 ps
CPU time 38.98 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:38 PM PDT 24
Peak memory 203776 kb
Host smart-3395351d-ac3a-4daf-8ba4-d67229f4bc3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2463948547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2463948547
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.1004382046
Short name T43
Test name
Test status
Simulation time 805278951 ps
CPU time 34.66 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:34 PM PDT 24
Peak memory 204720 kb
Host smart-0681a93d-86c0-45fa-864d-4f75a3f592eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1004382046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1004382046
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3681266492
Short name T146
Test name
Test status
Simulation time 43356819624 ps
CPU time 174.56 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:07:54 PM PDT 24
Peak memory 204552 kb
Host smart-eaece624-fa47-4d3e-937b-3bed56a4e3e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681266492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3681266492
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2570569885
Short name T820
Test name
Test status
Simulation time 55721054180 ps
CPU time 239.16 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:08:59 PM PDT 24
Peak memory 204576 kb
Host smart-f42c4caf-467a-44a5-b73f-ce715b951098
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2570569885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2570569885
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.405206022
Short name T507
Test name
Test status
Simulation time 544298191 ps
CPU time 24.92 seconds
Started Jun 05 04:04:57 PM PDT 24
Finished Jun 05 04:05:22 PM PDT 24
Peak memory 204632 kb
Host smart-ff938300-b355-4aee-b5ad-91086eec6f5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405206022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.405206022
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.4046584088
Short name T632
Test name
Test status
Simulation time 6744262378 ps
CPU time 39.11 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:39 PM PDT 24
Peak memory 211356 kb
Host smart-371be176-e298-42da-b95d-7cdecdabc9ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046584088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4046584088
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.343571298
Short name T663
Test name
Test status
Simulation time 237306064 ps
CPU time 3.5 seconds
Started Jun 05 04:05:02 PM PDT 24
Finished Jun 05 04:05:06 PM PDT 24
Peak memory 203352 kb
Host smart-6dfd1ead-f328-4cd2-9ec8-040422d38c81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=343571298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.343571298
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2089043140
Short name T250
Test name
Test status
Simulation time 8112249653 ps
CPU time 27.64 seconds
Started Jun 05 04:04:59 PM PDT 24
Finished Jun 05 04:05:28 PM PDT 24
Peak memory 203256 kb
Host smart-5619efb3-39a2-4ae5-9c57-fa18eb2bf884
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089043140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2089043140
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1000218121
Short name T576
Test name
Test status
Simulation time 6926866560 ps
CPU time 34.81 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:34 PM PDT 24
Peak memory 203248 kb
Host smart-5ef17844-e734-459f-9ba3-b4dc1bce1060
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1000218121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1000218121
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.324139330
Short name T609
Test name
Test status
Simulation time 24461730 ps
CPU time 2.24 seconds
Started Jun 05 04:04:58 PM PDT 24
Finished Jun 05 04:05:01 PM PDT 24
Peak memory 203180 kb
Host smart-8ee6c269-8888-4039-9793-9738e8860842
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324139330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.324139330
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.463411269
Short name T802
Test name
Test status
Simulation time 4769941031 ps
CPU time 132.67 seconds
Started Jun 05 04:05:14 PM PDT 24
Finished Jun 05 04:07:27 PM PDT 24
Peak memory 206960 kb
Host smart-3a64dd14-3010-444c-ab5a-72106cce7d77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=463411269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.463411269
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1799183200
Short name T692
Test name
Test status
Simulation time 3088194714 ps
CPU time 107.76 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:07:00 PM PDT 24
Peak memory 205672 kb
Host smart-b8501dd0-1ec0-4124-b206-b20e41bc3aec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1799183200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1799183200
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.4192418026
Short name T607
Test name
Test status
Simulation time 4758987323 ps
CPU time 341.24 seconds
Started Jun 05 04:05:11 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 210516 kb
Host smart-4aeda764-7173-4cb5-b751-c7f348b96acc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4192418026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.4192418026
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3433558278
Short name T363
Test name
Test status
Simulation time 3263611855 ps
CPU time 462.25 seconds
Started Jun 05 04:05:13 PM PDT 24
Finished Jun 05 04:12:56 PM PDT 24
Peak memory 227824 kb
Host smart-7df7e10d-ad48-4ede-81a0-4b25e3e4a54f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3433558278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.3433558278
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2567076042
Short name T163
Test name
Test status
Simulation time 166838081 ps
CPU time 19.72 seconds
Started Jun 05 04:05:00 PM PDT 24
Finished Jun 05 04:05:21 PM PDT 24
Peak memory 204676 kb
Host smart-9513eb43-610f-4602-b89a-50c542ce2ccf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2567076042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2567076042
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1716218895
Short name T338
Test name
Test status
Simulation time 732837056 ps
CPU time 24.24 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:05:37 PM PDT 24
Peak memory 211332 kb
Host smart-c402b351-8fdf-4cbc-901b-7b3d11ae5156
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1716218895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1716218895
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2505029675
Short name T591
Test name
Test status
Simulation time 90358642 ps
CPU time 4.34 seconds
Started Jun 05 04:05:14 PM PDT 24
Finished Jun 05 04:05:19 PM PDT 24
Peak memory 203124 kb
Host smart-45fed8ff-c68c-4e10-a063-c5cdb3a294af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2505029675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2505029675
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.2836783612
Short name T693
Test name
Test status
Simulation time 322874288 ps
CPU time 20.37 seconds
Started Jun 05 04:05:11 PM PDT 24
Finished Jun 05 04:05:32 PM PDT 24
Peak memory 203196 kb
Host smart-64c49b1f-8f1c-42ee-93df-4d62b1aebfcb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2836783612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2836783612
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.2265385456
Short name T20
Test name
Test status
Simulation time 89699157 ps
CPU time 10.58 seconds
Started Jun 05 04:05:11 PM PDT 24
Finished Jun 05 04:05:22 PM PDT 24
Peak memory 211356 kb
Host smart-9d298190-66ed-477f-a883-3e7d10da2a94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2265385456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2265385456
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1191267591
Short name T258
Test name
Test status
Simulation time 79629995304 ps
CPU time 230.22 seconds
Started Jun 05 04:05:14 PM PDT 24
Finished Jun 05 04:09:05 PM PDT 24
Peak memory 211392 kb
Host smart-5a5289ea-a79a-405d-887c-4d905ede006a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191267591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1191267591
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2875726652
Short name T721
Test name
Test status
Simulation time 20766774978 ps
CPU time 175.87 seconds
Started Jun 05 04:05:11 PM PDT 24
Finished Jun 05 04:08:07 PM PDT 24
Peak memory 211460 kb
Host smart-6d62e493-9a69-4454-aabc-149b9affa169
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2875726652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2875726652
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3523493417
Short name T498
Test name
Test status
Simulation time 144266336 ps
CPU time 9.61 seconds
Started Jun 05 04:05:10 PM PDT 24
Finished Jun 05 04:05:20 PM PDT 24
Peak memory 211384 kb
Host smart-971f87a8-f921-47bb-81d2-ec212eb7782d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523493417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3523493417
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.2516752963
Short name T190
Test name
Test status
Simulation time 275834456 ps
CPU time 13.5 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:05:26 PM PDT 24
Peak memory 203780 kb
Host smart-c72aa070-fb93-486d-be67-f21b7db749b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2516752963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2516752963
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.1760042190
Short name T788
Test name
Test status
Simulation time 524209800 ps
CPU time 4.23 seconds
Started Jun 05 04:05:15 PM PDT 24
Finished Jun 05 04:05:20 PM PDT 24
Peak memory 203172 kb
Host smart-6b6bfce0-d210-4f9f-bc4d-479ef2b95c65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1760042190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1760042190
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2885126655
Short name T62
Test name
Test status
Simulation time 8108085640 ps
CPU time 34.82 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:05:47 PM PDT 24
Peak memory 203248 kb
Host smart-ed156eff-bba4-4f97-b4d3-46abc16db13c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885126655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2885126655
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2876532262
Short name T41
Test name
Test status
Simulation time 2818816069 ps
CPU time 20.77 seconds
Started Jun 05 04:05:15 PM PDT 24
Finished Jun 05 04:05:36 PM PDT 24
Peak memory 203248 kb
Host smart-c467ade3-36cf-43aa-a331-c0dd07a26799
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2876532262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2876532262
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1891578723
Short name T603
Test name
Test status
Simulation time 117755773 ps
CPU time 2.46 seconds
Started Jun 05 04:05:13 PM PDT 24
Finished Jun 05 04:05:16 PM PDT 24
Peak memory 203192 kb
Host smart-c884d505-f0d1-4154-b738-15556d6284ed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891578723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1891578723
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.4187292971
Short name T738
Test name
Test status
Simulation time 20001347960 ps
CPU time 137.78 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:07:30 PM PDT 24
Peak memory 208664 kb
Host smart-f5d19dee-040d-4337-b1a0-7047cc6f2920
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4187292971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4187292971
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1387537933
Short name T517
Test name
Test status
Simulation time 10972504868 ps
CPU time 55.69 seconds
Started Jun 05 04:05:13 PM PDT 24
Finished Jun 05 04:06:09 PM PDT 24
Peak memory 211424 kb
Host smart-6c957b9a-660d-4399-b04a-1665de53564f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1387537933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1387537933
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.725117697
Short name T890
Test name
Test status
Simulation time 481279751 ps
CPU time 117.24 seconds
Started Jun 05 04:05:14 PM PDT 24
Finished Jun 05 04:07:12 PM PDT 24
Peak memory 207804 kb
Host smart-785c90d1-7d42-4ae8-96fb-e2aeab5958b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=725117697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand
_reset.725117697
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1287189344
Short name T300
Test name
Test status
Simulation time 151795914 ps
CPU time 7 seconds
Started Jun 05 04:05:14 PM PDT 24
Finished Jun 05 04:05:22 PM PDT 24
Peak memory 204640 kb
Host smart-05f45cd0-c06f-47d5-b76d-544bb38a1198
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1287189344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1287189344
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1601646273
Short name T147
Test name
Test status
Simulation time 998780566 ps
CPU time 21.85 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:05:41 PM PDT 24
Peak memory 210972 kb
Host smart-9a5ba770-0f7c-44ff-ba2e-045d4133c4e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1601646273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1601646273
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1752883865
Short name T562
Test name
Test status
Simulation time 64792175766 ps
CPU time 465.21 seconds
Started Jun 05 04:05:17 PM PDT 24
Finished Jun 05 04:13:03 PM PDT 24
Peak memory 211464 kb
Host smart-a4c876aa-7248-44fe-aad1-4ca03c824302
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1752883865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.1752883865
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1358193146
Short name T349
Test name
Test status
Simulation time 292111709 ps
CPU time 12.44 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:32 PM PDT 24
Peak memory 203180 kb
Host smart-76d3b9e9-049c-4554-9eaa-8fd6c1004804
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1358193146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1358193146
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.1624387999
Short name T96
Test name
Test status
Simulation time 728131372 ps
CPU time 12.57 seconds
Started Jun 05 04:05:22 PM PDT 24
Finished Jun 05 04:05:35 PM PDT 24
Peak memory 203064 kb
Host smart-8ca2b67c-0047-4b02-988b-d73ec4aa3f5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1624387999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1624387999
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.3966212052
Short name T245
Test name
Test status
Simulation time 797543314 ps
CPU time 33.18 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:05:46 PM PDT 24
Peak memory 211224 kb
Host smart-c73c4f3e-4c2e-43c0-8468-9f04d409f8e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3966212052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3966212052
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2893316529
Short name T587
Test name
Test status
Simulation time 50114126886 ps
CPU time 140.7 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 211448 kb
Host smart-f517a2d8-d5e8-4f59-a9f5-748579847968
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893316529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2893316529
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.763293188
Short name T535
Test name
Test status
Simulation time 69833062032 ps
CPU time 223.93 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:09:03 PM PDT 24
Peak memory 211460 kb
Host smart-1b93a7ba-dbf2-4157-982e-c1f76ef26e4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=763293188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.763293188
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3707258335
Short name T305
Test name
Test status
Simulation time 39135751 ps
CPU time 5.96 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:05:27 PM PDT 24
Peak memory 204312 kb
Host smart-cc469e15-1d25-4021-b1a2-e55751dc7916
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707258335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3707258335
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.713293737
Short name T292
Test name
Test status
Simulation time 237620314 ps
CPU time 20.06 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:05:41 PM PDT 24
Peak memory 203868 kb
Host smart-7d6fd3e5-49d6-4978-ba9b-06893105f98d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=713293737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.713293737
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.184882111
Short name T497
Test name
Test status
Simulation time 150564414 ps
CPU time 3.74 seconds
Started Jun 05 04:05:11 PM PDT 24
Finished Jun 05 04:05:15 PM PDT 24
Peak memory 203172 kb
Host smart-0c3d2040-376f-4b0e-8e1f-90b0b2bb8ab9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=184882111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.184882111
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.674676511
Short name T225
Test name
Test status
Simulation time 3815826966 ps
CPU time 23.53 seconds
Started Jun 05 04:05:13 PM PDT 24
Finished Jun 05 04:05:37 PM PDT 24
Peak memory 203248 kb
Host smart-152fed9e-889d-47d1-bb18-c0c971006030
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=674676511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.674676511
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2896018029
Short name T640
Test name
Test status
Simulation time 4012047360 ps
CPU time 32.71 seconds
Started Jun 05 04:05:14 PM PDT 24
Finished Jun 05 04:05:47 PM PDT 24
Peak memory 203192 kb
Host smart-acd83a9d-7ad1-4381-bb4e-7ffd09b7ee3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2896018029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2896018029
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.380466526
Short name T234
Test name
Test status
Simulation time 23252642 ps
CPU time 2.19 seconds
Started Jun 05 04:05:12 PM PDT 24
Finished Jun 05 04:05:14 PM PDT 24
Peak memory 203188 kb
Host smart-c34ad1f2-aee7-4768-8179-9e7aa6a434ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380466526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.380466526
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2013859654
Short name T205
Test name
Test status
Simulation time 1177575855 ps
CPU time 146.84 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:07:45 PM PDT 24
Peak memory 208320 kb
Host smart-7fa65f71-0f81-4a0d-9ffc-606e867f00b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2013859654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2013859654
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.825734369
Short name T791
Test name
Test status
Simulation time 625865186 ps
CPU time 47.18 seconds
Started Jun 05 04:05:21 PM PDT 24
Finished Jun 05 04:06:09 PM PDT 24
Peak memory 204368 kb
Host smart-b8c2ae5f-bcc5-4a92-a30c-8995f397eadc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=825734369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.825734369
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2588859558
Short name T756
Test name
Test status
Simulation time 2909438551 ps
CPU time 202.29 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 208676 kb
Host smart-4efeae9e-6100-475e-afa3-effecfd7989f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2588859558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.2588859558
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3602122848
Short name T389
Test name
Test status
Simulation time 247394355 ps
CPU time 42.22 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:06:03 PM PDT 24
Peak memory 206388 kb
Host smart-f99638c0-cbbd-4b89-a1cf-1177c0ba8142
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3602122848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.3602122848
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3472589918
Short name T139
Test name
Test status
Simulation time 1597569909 ps
CPU time 9.19 seconds
Started Jun 05 04:05:17 PM PDT 24
Finished Jun 05 04:05:27 PM PDT 24
Peak memory 211360 kb
Host smart-0ff3ea3e-3812-4548-ae5f-1501daba0df0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3472589918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3472589918
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.397273408
Short name T682
Test name
Test status
Simulation time 408340490 ps
CPU time 38.21 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:56 PM PDT 24
Peak memory 204256 kb
Host smart-05dbed94-c1bd-448f-9d11-9fffa831b5a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=397273408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.397273408
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3141445244
Short name T197
Test name
Test status
Simulation time 57407785732 ps
CPU time 375.43 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 206356 kb
Host smart-25dd3762-d06e-48e9-bca9-11d44bb14fc8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3141445244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.3141445244
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.4133203219
Short name T448
Test name
Test status
Simulation time 138309278 ps
CPU time 4.98 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:05:25 PM PDT 24
Peak memory 203160 kb
Host smart-7579d931-0c9e-4fb1-b3db-361a291dbe28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4133203219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.4133203219
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.2828152519
Short name T490
Test name
Test status
Simulation time 286838087 ps
CPU time 8.12 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:05:28 PM PDT 24
Peak memory 203112 kb
Host smart-6c6f5944-2022-4ec9-8bf1-3083ba959690
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2828152519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2828152519
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.3026602103
Short name T546
Test name
Test status
Simulation time 981669125 ps
CPU time 32.28 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:05:53 PM PDT 24
Peak memory 211352 kb
Host smart-aa5fc263-fa60-410a-8eb2-996da007787d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3026602103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3026602103
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.4128130411
Short name T332
Test name
Test status
Simulation time 7234451574 ps
CPU time 37.81 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:05:58 PM PDT 24
Peak memory 211424 kb
Host smart-ebdf6e2f-6dbd-461c-a9b5-aabcb0867386
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128130411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4128130411
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2089197913
Short name T675
Test name
Test status
Simulation time 33658947139 ps
CPU time 182.18 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:08:23 PM PDT 24
Peak memory 204824 kb
Host smart-bd690fdd-2eef-4107-ba8e-fd9b62ac0fff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2089197913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2089197913
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.423656254
Short name T333
Test name
Test status
Simulation time 307513103 ps
CPU time 5.92 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:25 PM PDT 24
Peak memory 211332 kb
Host smart-8c7655e8-bf2b-4131-bfd9-42df826699a2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423656254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.423656254
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.2855487729
Short name T364
Test name
Test status
Simulation time 199489615 ps
CPU time 13.82 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:33 PM PDT 24
Peak memory 211352 kb
Host smart-f9602906-c278-4635-9329-6582b846b2c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2855487729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2855487729
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2045517467
Short name T287
Test name
Test status
Simulation time 54946962 ps
CPU time 2.44 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:05:22 PM PDT 24
Peak memory 203080 kb
Host smart-ccb82118-ad6c-42a3-bd8f-a4f59ad07d27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2045517467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2045517467
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1262019641
Short name T864
Test name
Test status
Simulation time 4720364377 ps
CPU time 28.94 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:48 PM PDT 24
Peak memory 203252 kb
Host smart-ccecb4da-a83b-4a5b-a010-4b3e1bcea92d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262019641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1262019641
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3217673280
Short name T475
Test name
Test status
Simulation time 3130947340 ps
CPU time 29.5 seconds
Started Jun 05 04:05:16 PM PDT 24
Finished Jun 05 04:05:46 PM PDT 24
Peak memory 203228 kb
Host smart-fcd39a39-2773-4caf-a41c-bcf18afe8d7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3217673280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3217673280
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.624159783
Short name T403
Test name
Test status
Simulation time 36162120 ps
CPU time 2.55 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:05:23 PM PDT 24
Peak memory 203184 kb
Host smart-7ec7b396-6e88-483a-a022-5d602a0ab2f8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624159783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.624159783
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3383332737
Short name T76
Test name
Test status
Simulation time 31283061832 ps
CPU time 309.22 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:10:29 PM PDT 24
Peak memory 207036 kb
Host smart-549e9098-d091-49b2-a6f2-24c458620490
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3383332737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3383332737
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.71495909
Short name T394
Test name
Test status
Simulation time 10273827626 ps
CPU time 133.66 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:07:33 PM PDT 24
Peak memory 207604 kb
Host smart-e67ebecb-4a53-450e-9234-2e829fcefa2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71495909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.71495909
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.843399810
Short name T602
Test name
Test status
Simulation time 193915369 ps
CPU time 148.61 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:07:48 PM PDT 24
Peak memory 207744 kb
Host smart-e4b6b1ae-b2c9-4cc3-9e66-0aa960cfbc3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=843399810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand
_reset.843399810
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3372995016
Short name T786
Test name
Test status
Simulation time 3974621423 ps
CPU time 268.67 seconds
Started Jun 05 04:05:17 PM PDT 24
Finished Jun 05 04:09:46 PM PDT 24
Peak memory 211428 kb
Host smart-930b1e59-2424-4445-925f-fba880dd9cff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3372995016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.3372995016
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.4087412502
Short name T343
Test name
Test status
Simulation time 102647823 ps
CPU time 11.83 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:31 PM PDT 24
Peak memory 211356 kb
Host smart-2a2e99c1-848f-433f-aac4-6282448fe2bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4087412502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4087412502
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1752970366
Short name T217
Test name
Test status
Simulation time 315746797 ps
CPU time 43.39 seconds
Started Jun 05 04:05:21 PM PDT 24
Finished Jun 05 04:06:05 PM PDT 24
Peak memory 211244 kb
Host smart-74ffcd9e-5742-4ac2-bd41-379960702a75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1752970366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1752970366
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4217053404
Short name T83
Test name
Test status
Simulation time 264903015049 ps
CPU time 791.38 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:18:31 PM PDT 24
Peak memory 211404 kb
Host smart-4460d5fa-dbc9-496a-ba48-b090f5f8a85a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4217053404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.4217053404
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1695499367
Short name T463
Test name
Test status
Simulation time 94436961 ps
CPU time 2.36 seconds
Started Jun 05 04:05:16 PM PDT 24
Finished Jun 05 04:05:19 PM PDT 24
Peak memory 203180 kb
Host smart-aefc1089-f58c-4f7d-b420-0e0d57a9ee7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1695499367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1695499367
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.3908968596
Short name T821
Test name
Test status
Simulation time 187185077 ps
CPU time 13.53 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:05:35 PM PDT 24
Peak memory 203204 kb
Host smart-2d269fc0-0fde-4678-8d2f-29996ea62a9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3908968596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3908968596
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.4046042323
Short name T241
Test name
Test status
Simulation time 351396441 ps
CPU time 7.92 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:27 PM PDT 24
Peak memory 204280 kb
Host smart-ebe50bde-6798-4516-9b21-0606c29a0641
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046042323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.4046042323
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.601574728
Short name T694
Test name
Test status
Simulation time 7573517351 ps
CPU time 35.35 seconds
Started Jun 05 04:05:21 PM PDT 24
Finished Jun 05 04:05:57 PM PDT 24
Peak memory 204296 kb
Host smart-38d10bfb-4691-436f-9767-f3ec90b493ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=601574728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.601574728
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1297195719
Short name T137
Test name
Test status
Simulation time 10406222547 ps
CPU time 56.77 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:06:17 PM PDT 24
Peak memory 211440 kb
Host smart-87c679c8-b451-43f9-94c9-a44de2871989
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1297195719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1297195719
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3383796733
Short name T566
Test name
Test status
Simulation time 211005598 ps
CPU time 22.46 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:41 PM PDT 24
Peak memory 204576 kb
Host smart-e6fe0e72-06a1-4d3b-88b7-f1c40a9c3418
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383796733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3383796733
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.208929929
Short name T655
Test name
Test status
Simulation time 731880853 ps
CPU time 11.12 seconds
Started Jun 05 04:05:20 PM PDT 24
Finished Jun 05 04:05:32 PM PDT 24
Peak memory 203740 kb
Host smart-491d446c-8465-4b46-bab5-22d1fb8fd18c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=208929929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.208929929
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.1569970370
Short name T479
Test name
Test status
Simulation time 116551665 ps
CPU time 3.41 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:05:23 PM PDT 24
Peak memory 203180 kb
Host smart-181dd094-c5fa-456a-90b6-61db35942f3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1569970370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1569970370
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4154055308
Short name T306
Test name
Test status
Simulation time 37083389054 ps
CPU time 45.21 seconds
Started Jun 05 04:05:17 PM PDT 24
Finished Jun 05 04:06:02 PM PDT 24
Peak memory 203252 kb
Host smart-821c592c-df34-4ff1-a149-2a47f6c21c5b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154055308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4154055308
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2985491127
Short name T672
Test name
Test status
Simulation time 13856697650 ps
CPU time 38.28 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:57 PM PDT 24
Peak memory 203244 kb
Host smart-814dfe43-27a3-441e-8a94-90d9b5b9ed3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2985491127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2985491127
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.4130789528
Short name T733
Test name
Test status
Simulation time 28827894 ps
CPU time 2.55 seconds
Started Jun 05 04:05:21 PM PDT 24
Finished Jun 05 04:05:24 PM PDT 24
Peak memory 203044 kb
Host smart-74e76a4c-e2ac-4a15-9716-4e3c74db05c8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130789528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.4130789528
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.656618218
Short name T720
Test name
Test status
Simulation time 1070490651 ps
CPU time 164.36 seconds
Started Jun 05 04:05:21 PM PDT 24
Finished Jun 05 04:08:06 PM PDT 24
Peak memory 209736 kb
Host smart-1b2548d1-370c-4b8d-a1d0-6c26a68e20b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=656618218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.656618218
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2965028262
Short name T722
Test name
Test status
Simulation time 1000237598 ps
CPU time 113.06 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:07:13 PM PDT 24
Peak memory 208188 kb
Host smart-4826e44d-58e7-4a0c-9c2a-37867c42256a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2965028262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2965028262
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2955791029
Short name T280
Test name
Test status
Simulation time 24834694 ps
CPU time 32.03 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:05:52 PM PDT 24
Peak memory 205300 kb
Host smart-78d10fdc-db00-431a-84be-93b79f4679d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2955791029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.2955791029
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2716194437
Short name T485
Test name
Test status
Simulation time 3939682051 ps
CPU time 291.87 seconds
Started Jun 05 04:05:19 PM PDT 24
Finished Jun 05 04:10:12 PM PDT 24
Peak memory 219644 kb
Host smart-047fc69b-7014-4085-bc49-c58dabaa0be1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2716194437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.2716194437
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.891605363
Short name T545
Test name
Test status
Simulation time 331605231 ps
CPU time 11.96 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:30 PM PDT 24
Peak memory 204840 kb
Host smart-ff9a09a2-f495-4397-b77d-827710c02b92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=891605363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.891605363
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.319794663
Short name T688
Test name
Test status
Simulation time 2571671000 ps
CPU time 63.48 seconds
Started Jun 05 04:05:26 PM PDT 24
Finished Jun 05 04:06:30 PM PDT 24
Peak memory 211396 kb
Host smart-165f3b2f-6d18-4bc0-a0a7-caeca89bb27a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=319794663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.319794663
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3694976791
Short name T505
Test name
Test status
Simulation time 24411161246 ps
CPU time 182.29 seconds
Started Jun 05 04:05:27 PM PDT 24
Finished Jun 05 04:08:30 PM PDT 24
Peak memory 211452 kb
Host smart-095465c1-1abc-4fe6-84b8-950bc80a209a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3694976791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.3694976791
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4077024239
Short name T402
Test name
Test status
Simulation time 232364355 ps
CPU time 8.12 seconds
Started Jun 05 04:05:26 PM PDT 24
Finished Jun 05 04:05:34 PM PDT 24
Peak memory 203284 kb
Host smart-61421b6e-5b11-40af-90e4-88ca685b8c72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4077024239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4077024239
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.1670670299
Short name T414
Test name
Test status
Simulation time 1045974228 ps
CPU time 31.12 seconds
Started Jun 05 04:05:28 PM PDT 24
Finished Jun 05 04:06:00 PM PDT 24
Peak memory 203200 kb
Host smart-baf4baae-f639-48ea-81b8-e542eb16c791
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1670670299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1670670299
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.1348977705
Short name T180
Test name
Test status
Simulation time 1941338692 ps
CPU time 34.25 seconds
Started Jun 05 04:05:24 PM PDT 24
Finished Jun 05 04:05:59 PM PDT 24
Peak memory 204220 kb
Host smart-86faa968-5d18-43a8-a64f-a3c222930109
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1348977705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1348977705
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.4233282048
Short name T593
Test name
Test status
Simulation time 9491866811 ps
CPU time 42.26 seconds
Started Jun 05 04:05:27 PM PDT 24
Finished Jun 05 04:06:10 PM PDT 24
Peak memory 204420 kb
Host smart-0d2e2882-b692-401a-89ba-3fe789281eef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233282048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4233282048
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1794203851
Short name T211
Test name
Test status
Simulation time 22587322812 ps
CPU time 216.51 seconds
Started Jun 05 04:05:32 PM PDT 24
Finished Jun 05 04:09:09 PM PDT 24
Peak memory 211344 kb
Host smart-4483c983-79a7-42be-863e-75f181f2c1be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1794203851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1794203851
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1520861422
Short name T897
Test name
Test status
Simulation time 251156181 ps
CPU time 25.88 seconds
Started Jun 05 04:05:26 PM PDT 24
Finished Jun 05 04:05:52 PM PDT 24
Peak memory 204300 kb
Host smart-5ae1ba48-367a-4455-97c9-363d99de4bae
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520861422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1520861422
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.898952596
Short name T793
Test name
Test status
Simulation time 2388739220 ps
CPU time 18.04 seconds
Started Jun 05 04:05:29 PM PDT 24
Finished Jun 05 04:05:47 PM PDT 24
Peak memory 203252 kb
Host smart-e06743b7-2ebc-4c0c-bddd-ee3430253f64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=898952596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.898952596
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.1159643922
Short name T552
Test name
Test status
Simulation time 141982419 ps
CPU time 2.4 seconds
Started Jun 05 04:05:18 PM PDT 24
Finished Jun 05 04:05:22 PM PDT 24
Peak memory 203132 kb
Host smart-16631e1f-68b5-437c-9559-c8232b511b30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1159643922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1159643922
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1568703075
Short name T415
Test name
Test status
Simulation time 11340244430 ps
CPU time 29.41 seconds
Started Jun 05 04:05:26 PM PDT 24
Finished Jun 05 04:05:56 PM PDT 24
Peak memory 203248 kb
Host smart-9613a1fb-2602-496e-8440-355defa9ecb5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568703075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1568703075
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2303644254
Short name T42
Test name
Test status
Simulation time 2637627800 ps
CPU time 22 seconds
Started Jun 05 04:05:25 PM PDT 24
Finished Jun 05 04:05:48 PM PDT 24
Peak memory 203264 kb
Host smart-277f11f1-e21d-4a01-9141-efd523b4e625
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2303644254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2303644254
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3351934547
Short name T823
Test name
Test status
Simulation time 43615305 ps
CPU time 2.23 seconds
Started Jun 05 04:05:32 PM PDT 24
Finished Jun 05 04:05:34 PM PDT 24
Peak memory 203084 kb
Host smart-ba53a9e4-82c1-4542-8529-4ef98a63a87a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351934547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3351934547
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3523726170
Short name T829
Test name
Test status
Simulation time 12567820189 ps
CPU time 286.9 seconds
Started Jun 05 04:05:30 PM PDT 24
Finished Jun 05 04:10:17 PM PDT 24
Peak memory 211368 kb
Host smart-69f846ca-0a17-4edb-9662-001065d5e7a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3523726170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3523726170
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2769152445
Short name T488
Test name
Test status
Simulation time 939417615 ps
CPU time 114.85 seconds
Started Jun 05 04:05:27 PM PDT 24
Finished Jun 05 04:07:23 PM PDT 24
Peak memory 208196 kb
Host smart-f070e1fd-1623-4fd3-94ac-b1e5b14db416
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2769152445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2769152445
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2140603227
Short name T24
Test name
Test status
Simulation time 641897871 ps
CPU time 190.34 seconds
Started Jun 05 04:05:32 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 207836 kb
Host smart-6cbaa805-0a05-44dd-8ee2-9e5f222c4a3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2140603227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.2140603227
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2405725466
Short name T67
Test name
Test status
Simulation time 183306127 ps
CPU time 8.94 seconds
Started Jun 05 04:05:23 PM PDT 24
Finished Jun 05 04:05:33 PM PDT 24
Peak memory 204656 kb
Host smart-68d49a8a-ac69-435b-9ec9-168b33a4d26e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2405725466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2405725466
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3952247082
Short name T833
Test name
Test status
Simulation time 390377581 ps
CPU time 33.45 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:04:33 PM PDT 24
Peak memory 211380 kb
Host smart-030b72ad-497a-4a02-8b3b-c0284515a346
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3952247082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3952247082
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4002586572
Short name T30
Test name
Test status
Simulation time 590518057 ps
CPU time 22.38 seconds
Started Jun 05 04:03:56 PM PDT 24
Finished Jun 05 04:04:20 PM PDT 24
Peak memory 203172 kb
Host smart-04590a1b-0559-429a-ba20-bb9a79496c1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4002586572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4002586572
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.2996131585
Short name T141
Test name
Test status
Simulation time 4338408635 ps
CPU time 37.29 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:04:36 PM PDT 24
Peak memory 203256 kb
Host smart-78597f4c-d55d-488d-9969-732e9a97de1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2996131585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2996131585
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.927517711
Short name T798
Test name
Test status
Simulation time 909089387 ps
CPU time 26.38 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:04:26 PM PDT 24
Peak memory 204276 kb
Host smart-46040976-7754-45c7-abee-7ebe7d7fe02b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=927517711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.927517711
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2148530927
Short name T666
Test name
Test status
Simulation time 46610815253 ps
CPU time 262.07 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:08:22 PM PDT 24
Peak memory 205416 kb
Host smart-72224e24-8859-4f08-a8a4-1cd6893e3ed8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148530927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2148530927
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2996636499
Short name T714
Test name
Test status
Simulation time 10703387622 ps
CPU time 86.66 seconds
Started Jun 05 04:04:00 PM PDT 24
Finished Jun 05 04:05:27 PM PDT 24
Peak memory 204648 kb
Host smart-505d74b8-707b-4147-9912-b50a388df3a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2996636499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2996636499
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1221959141
Short name T606
Test name
Test status
Simulation time 250182136 ps
CPU time 17.69 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:04:16 PM PDT 24
Peak memory 204304 kb
Host smart-bafb9c35-83df-411a-ba66-788e1b1500c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221959141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1221959141
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.643746657
Short name T238
Test name
Test status
Simulation time 1612083473 ps
CPU time 32.58 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:04:31 PM PDT 24
Peak memory 203100 kb
Host smart-cdd39960-bdf7-4887-93a5-e8619ce67e26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=643746657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.643746657
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.2412675520
Short name T810
Test name
Test status
Simulation time 671791505 ps
CPU time 4.55 seconds
Started Jun 05 04:04:00 PM PDT 24
Finished Jun 05 04:04:05 PM PDT 24
Peak memory 203132 kb
Host smart-26f19858-a6d0-4784-9119-52b41521eda5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2412675520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2412675520
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4221055574
Short name T669
Test name
Test status
Simulation time 8114179623 ps
CPU time 26.37 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:04:24 PM PDT 24
Peak memory 203240 kb
Host smart-ae6977b1-4fe0-471c-8c11-73db92a8b69b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221055574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4221055574
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1451891681
Short name T613
Test name
Test status
Simulation time 7898497250 ps
CPU time 35.39 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:04:35 PM PDT 24
Peak memory 203244 kb
Host smart-3f93273e-c1e2-4a93-a07f-fec79c4dc3be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1451891681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1451891681
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2222285271
Short name T586
Test name
Test status
Simulation time 59550182 ps
CPU time 2.28 seconds
Started Jun 05 04:03:56 PM PDT 24
Finished Jun 05 04:03:59 PM PDT 24
Peak memory 203440 kb
Host smart-15d99d81-9894-4a8e-a6a6-8f5fef6460c9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222285271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2222285271
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.350597640
Short name T649
Test name
Test status
Simulation time 680015963 ps
CPU time 24.75 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:04:23 PM PDT 24
Peak memory 204456 kb
Host smart-21e55acb-358e-4f52-9815-066eb2100fb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=350597640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.350597640
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1600736636
Short name T469
Test name
Test status
Simulation time 2114008037 ps
CPU time 83.35 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:05:23 PM PDT 24
Peak memory 211244 kb
Host smart-efdb6dc7-3087-4205-86d7-be320e8dbee9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1600736636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1600736636
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.660365466
Short name T654
Test name
Test status
Simulation time 170978536 ps
CPU time 34.17 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:04:34 PM PDT 24
Peak memory 206540 kb
Host smart-a85afdef-1e35-448c-a164-a724b63e2a01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=660365466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_
reset.660365466
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1822001835
Short name T34
Test name
Test status
Simulation time 544652003 ps
CPU time 146.45 seconds
Started Jun 05 04:04:00 PM PDT 24
Finished Jun 05 04:06:27 PM PDT 24
Peak memory 209992 kb
Host smart-c58bc76e-b554-4734-b9a5-5fba8e1d8576
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1822001835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.1822001835
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.485707859
Short name T777
Test name
Test status
Simulation time 213118479 ps
CPU time 8.36 seconds
Started Jun 05 04:03:59 PM PDT 24
Finished Jun 05 04:04:08 PM PDT 24
Peak memory 204616 kb
Host smart-9684aeb5-32a8-4333-ae32-9346e2043490
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485707859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.485707859
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1410707168
Short name T511
Test name
Test status
Simulation time 311544103 ps
CPU time 24.16 seconds
Started Jun 05 04:05:30 PM PDT 24
Finished Jun 05 04:05:55 PM PDT 24
Peak memory 211288 kb
Host smart-d934d5d8-2263-4764-add8-9f53cf429d81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1410707168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1410707168
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1099453220
Short name T431
Test name
Test status
Simulation time 131322195089 ps
CPU time 603.62 seconds
Started Jun 05 04:05:28 PM PDT 24
Finished Jun 05 04:15:32 PM PDT 24
Peak memory 211460 kb
Host smart-a19f2c4a-d2ba-4558-80c8-6bb055869ff3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1099453220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.1099453220
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2564200376
Short name T326
Test name
Test status
Simulation time 194027328 ps
CPU time 17.46 seconds
Started Jun 05 04:05:30 PM PDT 24
Finished Jun 05 04:05:48 PM PDT 24
Peak memory 203400 kb
Host smart-29dac0d1-7237-49f3-baeb-e54920f54e4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2564200376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2564200376
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.3080288898
Short name T188
Test name
Test status
Simulation time 106864026 ps
CPU time 8.95 seconds
Started Jun 05 04:05:25 PM PDT 24
Finished Jun 05 04:05:35 PM PDT 24
Peak memory 203436 kb
Host smart-f6efe3be-8df8-4c6d-a187-92c5b1cabbb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3080288898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3080288898
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.3724617779
Short name T344
Test name
Test status
Simulation time 46356951 ps
CPU time 7.24 seconds
Started Jun 05 04:05:28 PM PDT 24
Finished Jun 05 04:05:36 PM PDT 24
Peak memory 211356 kb
Host smart-85b72297-7830-4048-be60-7e56b42be4ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3724617779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3724617779
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.96331484
Short name T598
Test name
Test status
Simulation time 35467102344 ps
CPU time 124.52 seconds
Started Jun 05 04:05:30 PM PDT 24
Finished Jun 05 04:07:35 PM PDT 24
Peak memory 211368 kb
Host smart-47a55de9-72af-430b-90c9-e2c2caab8e43
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=96331484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.96331484
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1750247163
Short name T91
Test name
Test status
Simulation time 31116601279 ps
CPU time 145.55 seconds
Started Jun 05 04:05:25 PM PDT 24
Finished Jun 05 04:07:51 PM PDT 24
Peak memory 204748 kb
Host smart-e3a9ca91-f50d-40ca-b44e-2f4d599c09d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1750247163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1750247163
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2938461284
Short name T323
Test name
Test status
Simulation time 125593644 ps
CPU time 14.89 seconds
Started Jun 05 04:05:25 PM PDT 24
Finished Jun 05 04:05:41 PM PDT 24
Peak memory 211248 kb
Host smart-a65b500f-707a-4037-a216-8336d04a7821
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938461284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2938461284
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.3222749276
Short name T170
Test name
Test status
Simulation time 2974441530 ps
CPU time 20.49 seconds
Started Jun 05 04:05:27 PM PDT 24
Finished Jun 05 04:05:48 PM PDT 24
Peak memory 203216 kb
Host smart-21dac376-0883-4f8f-b755-94da570a3ace
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3222749276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3222749276
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.1188506196
Short name T681
Test name
Test status
Simulation time 168361305 ps
CPU time 3.35 seconds
Started Jun 05 04:05:31 PM PDT 24
Finished Jun 05 04:05:35 PM PDT 24
Peak memory 203068 kb
Host smart-bf4530e7-7776-4022-962a-0a87d4a3c122
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1188506196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1188506196
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3232417058
Short name T685
Test name
Test status
Simulation time 25050936635 ps
CPU time 34.67 seconds
Started Jun 05 04:05:24 PM PDT 24
Finished Jun 05 04:05:59 PM PDT 24
Peak memory 203264 kb
Host smart-dd99ce50-e4be-435d-994c-19163b52ddab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232417058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3232417058
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.980656929
Short name T452
Test name
Test status
Simulation time 3871034671 ps
CPU time 31.59 seconds
Started Jun 05 04:05:27 PM PDT 24
Finished Jun 05 04:05:59 PM PDT 24
Peak memory 203160 kb
Host smart-9aab4e18-74c1-49d8-a9e8-00d6e0cbd3d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=980656929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.980656929
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3025257811
Short name T261
Test name
Test status
Simulation time 142888777 ps
CPU time 2.46 seconds
Started Jun 05 04:05:25 PM PDT 24
Finished Jun 05 04:05:28 PM PDT 24
Peak memory 203188 kb
Host smart-77ba22c6-6ea5-4288-a7dc-5a769ff27a07
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025257811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3025257811
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2688504602
Short name T704
Test name
Test status
Simulation time 2930968480 ps
CPU time 84.84 seconds
Started Jun 05 04:05:26 PM PDT 24
Finished Jun 05 04:06:52 PM PDT 24
Peak memory 206924 kb
Host smart-6abefb7c-906b-43dc-bf2e-c582c1120f5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2688504602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2688504602
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.741981667
Short name T336
Test name
Test status
Simulation time 8186222446 ps
CPU time 104 seconds
Started Jun 05 04:05:36 PM PDT 24
Finished Jun 05 04:07:21 PM PDT 24
Peak memory 207660 kb
Host smart-ddded055-7166-448a-aed8-f6f54bda480f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=741981667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.741981667
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.4049003292
Short name T25
Test name
Test status
Simulation time 456148007 ps
CPU time 197.61 seconds
Started Jun 05 04:05:34 PM PDT 24
Finished Jun 05 04:08:52 PM PDT 24
Peak memory 208796 kb
Host smart-9f128ca4-7225-4014-83b0-905b67bdbf31
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4049003292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.4049003292
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.862419094
Short name T277
Test name
Test status
Simulation time 2737191394 ps
CPU time 274.82 seconds
Started Jun 05 04:05:36 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 219616 kb
Host smart-cdfdc8bf-2bbc-4246-8685-dbb89ebda3c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862419094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res
et_error.862419094
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1228880102
Short name T847
Test name
Test status
Simulation time 45023224 ps
CPU time 3.17 seconds
Started Jun 05 04:05:27 PM PDT 24
Finished Jun 05 04:05:30 PM PDT 24
Peak memory 204240 kb
Host smart-567a3bb0-6f8b-41bd-8bc1-e5206af450ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1228880102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1228880102
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.904229268
Short name T581
Test name
Test status
Simulation time 561778768 ps
CPU time 24.79 seconds
Started Jun 05 04:05:33 PM PDT 24
Finished Jun 05 04:05:59 PM PDT 24
Peak memory 204268 kb
Host smart-ab8ea435-40c6-4b5b-a174-29c7c3e9f47f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=904229268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.904229268
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.963684006
Short name T134
Test name
Test status
Simulation time 22661623001 ps
CPU time 194.86 seconds
Started Jun 05 04:05:34 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 206340 kb
Host smart-da7336c2-cb0b-4d95-a198-0daa63bf6616
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=963684006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slo
w_rsp.963684006
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.867474420
Short name T31
Test name
Test status
Simulation time 1011370725 ps
CPU time 23.44 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:06:00 PM PDT 24
Peak memory 203348 kb
Host smart-9e0cf077-b1fb-47cb-99ae-e9f4499a6b41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=867474420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.867474420
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3118268854
Short name T325
Test name
Test status
Simulation time 1696591860 ps
CPU time 32.82 seconds
Started Jun 05 04:05:32 PM PDT 24
Finished Jun 05 04:06:06 PM PDT 24
Peak memory 203208 kb
Host smart-5be929f7-aca8-4ee6-9d77-5dab81527720
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3118268854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3118268854
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.2500067180
Short name T815
Test name
Test status
Simulation time 173326075 ps
CPU time 2.78 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:05:39 PM PDT 24
Peak memory 203180 kb
Host smart-f556c786-7176-4dae-be20-e551fc75a0e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500067180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2500067180
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4048750915
Short name T120
Test name
Test status
Simulation time 37740888017 ps
CPU time 178.35 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 211392 kb
Host smart-970f3cf5-fbce-45bb-8e7c-1e0fc74095d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048750915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4048750915
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3978368054
Short name T219
Test name
Test status
Simulation time 21513480941 ps
CPU time 96.08 seconds
Started Jun 05 04:05:34 PM PDT 24
Finished Jun 05 04:07:11 PM PDT 24
Peak memory 211444 kb
Host smart-c5e6119f-7117-4699-a2eb-d35f6f61a0c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3978368054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3978368054
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.4074654188
Short name T852
Test name
Test status
Simulation time 363409763 ps
CPU time 10.38 seconds
Started Jun 05 04:05:34 PM PDT 24
Finished Jun 05 04:05:45 PM PDT 24
Peak memory 211380 kb
Host smart-a675b7e3-796a-4300-a886-96f0c9630ab5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074654188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4074654188
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.2634879085
Short name T382
Test name
Test status
Simulation time 509459780 ps
CPU time 8.88 seconds
Started Jun 05 04:05:37 PM PDT 24
Finished Jun 05 04:05:46 PM PDT 24
Peak memory 203100 kb
Host smart-de63ad4b-d039-4e32-a5cf-6653052844e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2634879085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2634879085
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.298477161
Short name T824
Test name
Test status
Simulation time 310935485 ps
CPU time 3.81 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:05:39 PM PDT 24
Peak memory 203132 kb
Host smart-2fa433ee-6b1f-48d2-8947-f47cbe22d4ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=298477161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.298477161
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1327436230
Short name T731
Test name
Test status
Simulation time 10853195845 ps
CPU time 33.63 seconds
Started Jun 05 04:05:34 PM PDT 24
Finished Jun 05 04:06:08 PM PDT 24
Peak memory 203252 kb
Host smart-7215478c-aed6-4253-b1c4-7b6159d8c4c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327436230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1327436230
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2427752119
Short name T329
Test name
Test status
Simulation time 18286025257 ps
CPU time 43.09 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:06:19 PM PDT 24
Peak memory 203252 kb
Host smart-15907050-58fa-4fb2-8963-c18975bfa3a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2427752119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2427752119
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.4604559
Short name T243
Test name
Test status
Simulation time 27685943 ps
CPU time 2.04 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:05:37 PM PDT 24
Peak memory 203160 kb
Host smart-b87a8d41-87b4-42f8-8db8-660a44954d9c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4604559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.4604559
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3610557161
Short name T778
Test name
Test status
Simulation time 5877818589 ps
CPU time 113.73 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:07:30 PM PDT 24
Peak memory 208380 kb
Host smart-24df99e2-77c7-4fef-ad3a-28504873c9ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3610557161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3610557161
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.6935955
Short name T118
Test name
Test status
Simulation time 2624392061 ps
CPU time 375.88 seconds
Started Jun 05 04:05:35 PM PDT 24
Finished Jun 05 04:11:52 PM PDT 24
Peak memory 219936 kb
Host smart-2df1d636-a6f3-45bf-b144-3cbfa58cd4b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6935955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset
_error.6935955
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1488437242
Short name T199
Test name
Test status
Simulation time 1870364402 ps
CPU time 28.49 seconds
Started Jun 05 04:05:34 PM PDT 24
Finished Jun 05 04:06:03 PM PDT 24
Peak memory 204732 kb
Host smart-641b9a02-0ef5-425c-b876-0712030febfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1488437242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1488437242
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3912924569
Short name T158
Test name
Test status
Simulation time 569796727 ps
CPU time 36.79 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:06:26 PM PDT 24
Peak memory 206184 kb
Host smart-9595076e-6e02-48dc-b0d4-15468ed97f44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3912924569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3912924569
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2768184191
Short name T500
Test name
Test status
Simulation time 6163391351 ps
CPU time 38.06 seconds
Started Jun 05 04:05:46 PM PDT 24
Finished Jun 05 04:06:25 PM PDT 24
Peak memory 211420 kb
Host smart-e83b1399-8dc4-4bac-8ce7-4a3f8f034eea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2768184191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.2768184191
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2049164036
Short name T295
Test name
Test status
Simulation time 1119284781 ps
CPU time 23.91 seconds
Started Jun 05 04:05:43 PM PDT 24
Finished Jun 05 04:06:07 PM PDT 24
Peak memory 203496 kb
Host smart-ca268071-81de-4edc-9a01-42b3b26c6a20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2049164036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2049164036
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1728954219
Short name T481
Test name
Test status
Simulation time 2689685627 ps
CPU time 36.27 seconds
Started Jun 05 04:05:43 PM PDT 24
Finished Jun 05 04:06:19 PM PDT 24
Peak memory 203348 kb
Host smart-a1c66636-bbaa-4256-b2d3-2115955a93e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1728954219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1728954219
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.649462834
Short name T440
Test name
Test status
Simulation time 348014670 ps
CPU time 19.82 seconds
Started Jun 05 04:05:42 PM PDT 24
Finished Jun 05 04:06:03 PM PDT 24
Peak memory 204600 kb
Host smart-1cdd87d6-3db7-4ccc-9858-8f46d741038f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=649462834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.649462834
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1696521170
Short name T182
Test name
Test status
Simulation time 99162967602 ps
CPU time 129.36 seconds
Started Jun 05 04:05:40 PM PDT 24
Finished Jun 05 04:07:50 PM PDT 24
Peak memory 204372 kb
Host smart-6cbd1612-19ff-4b55-bcdd-fe6d9a8bb0ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696521170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1696521170
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.808912519
Short name T293
Test name
Test status
Simulation time 149454253814 ps
CPU time 293.87 seconds
Started Jun 05 04:05:48 PM PDT 24
Finished Jun 05 04:10:43 PM PDT 24
Peak memory 204964 kb
Host smart-e705bbff-4bce-4486-9fcc-1eb02e467f7b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=808912519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.808912519
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.544097116
Short name T124
Test name
Test status
Simulation time 114596983 ps
CPU time 12.96 seconds
Started Jun 05 04:05:41 PM PDT 24
Finished Jun 05 04:05:55 PM PDT 24
Peak memory 204224 kb
Host smart-2d28d0d7-7115-4496-9539-a436d36d9e93
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544097116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.544097116
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.1234088188
Short name T442
Test name
Test status
Simulation time 120015189 ps
CPU time 3.45 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:05:53 PM PDT 24
Peak memory 203200 kb
Host smart-f60081ee-b87c-49cb-ab6d-24c9eb1ae43e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1234088188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1234088188
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.3990459569
Short name T730
Test name
Test status
Simulation time 99228601 ps
CPU time 2.47 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:05:52 PM PDT 24
Peak memory 203176 kb
Host smart-3a18144d-e898-464f-bc1e-7e243a2aa52e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3990459569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3990459569
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1067771753
Short name T510
Test name
Test status
Simulation time 5900568015 ps
CPU time 25.23 seconds
Started Jun 05 04:05:45 PM PDT 24
Finished Jun 05 04:06:11 PM PDT 24
Peak memory 203252 kb
Host smart-3c8df321-bc45-4f6f-aba7-c8a0f7b4a444
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067771753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1067771753
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1896789087
Short name T534
Test name
Test status
Simulation time 5313266055 ps
CPU time 34.41 seconds
Started Jun 05 04:05:46 PM PDT 24
Finished Jun 05 04:06:21 PM PDT 24
Peak memory 203248 kb
Host smart-f7560258-b8bf-4b4b-8d0a-4ee86d92e32a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1896789087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1896789087
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1056493631
Short name T633
Test name
Test status
Simulation time 27024295 ps
CPU time 2.33 seconds
Started Jun 05 04:05:42 PM PDT 24
Finished Jun 05 04:05:45 PM PDT 24
Peak memory 203184 kb
Host smart-f4000706-86ec-4c05-bf16-b902cf158308
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056493631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1056493631
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1196017332
Short name T129
Test name
Test status
Simulation time 7799312665 ps
CPU time 195.99 seconds
Started Jun 05 04:05:42 PM PDT 24
Finished Jun 05 04:08:58 PM PDT 24
Peak memory 211444 kb
Host smart-24bfd15b-b6d5-4531-a633-93fddb934efa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196017332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1196017332
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3009657921
Short name T577
Test name
Test status
Simulation time 16982105728 ps
CPU time 212.79 seconds
Started Jun 05 04:05:45 PM PDT 24
Finished Jun 05 04:09:18 PM PDT 24
Peak memory 206364 kb
Host smart-1638fae8-f5d0-4ff9-a94d-b8155161cf01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3009657921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3009657921
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1301094283
Short name T196
Test name
Test status
Simulation time 3284968632 ps
CPU time 220.44 seconds
Started Jun 05 04:05:45 PM PDT 24
Finished Jun 05 04:09:26 PM PDT 24
Peak memory 208144 kb
Host smart-2cc63956-4e06-451e-9aa8-ebd38d4d2e1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1301094283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.1301094283
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2365605100
Short name T797
Test name
Test status
Simulation time 1770828660 ps
CPU time 119.91 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:07:50 PM PDT 24
Peak memory 209304 kb
Host smart-3c8b6c1c-0095-4410-a44a-99948edfa6fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2365605100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.2365605100
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1619089214
Short name T476
Test name
Test status
Simulation time 122977634 ps
CPU time 15.13 seconds
Started Jun 05 04:05:44 PM PDT 24
Finished Jun 05 04:05:59 PM PDT 24
Peak memory 211272 kb
Host smart-b71bac06-ab76-48b1-ba12-175235dec8d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1619089214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1619089214
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3374424042
Short name T179
Test name
Test status
Simulation time 1627693192 ps
CPU time 41.01 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:06:30 PM PDT 24
Peak memory 204632 kb
Host smart-d313f1ae-76bf-43a2-a029-7e0ce216a9c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3374424042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3374424042
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.983839388
Short name T97
Test name
Test status
Simulation time 42399778807 ps
CPU time 214.88 seconds
Started Jun 05 04:05:50 PM PDT 24
Finished Jun 05 04:09:25 PM PDT 24
Peak memory 206564 kb
Host smart-d37ccda3-3ab3-44e1-a240-c106a43293fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=983839388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo
w_rsp.983839388
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3669303781
Short name T296
Test name
Test status
Simulation time 76022714 ps
CPU time 7.7 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:05:57 PM PDT 24
Peak memory 203388 kb
Host smart-d4e73c9b-c655-41e0-9a25-2937ffdc8cea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3669303781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3669303781
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.1029683597
Short name T281
Test name
Test status
Simulation time 358523793 ps
CPU time 22.92 seconds
Started Jun 05 04:05:50 PM PDT 24
Finished Jun 05 04:06:13 PM PDT 24
Peak memory 203296 kb
Host smart-aab374e4-7abe-4592-ad6d-08b56b17dee4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1029683597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1029683597
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.1550243989
Short name T874
Test name
Test status
Simulation time 422437716 ps
CPU time 23.48 seconds
Started Jun 05 04:05:50 PM PDT 24
Finished Jun 05 04:06:14 PM PDT 24
Peak memory 204496 kb
Host smart-2b5c6d74-4862-48b9-b28d-5f339a82c2f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1550243989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1550243989
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1383805672
Short name T56
Test name
Test status
Simulation time 48799975576 ps
CPU time 240.12 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:09:50 PM PDT 24
Peak memory 204776 kb
Host smart-53e51e1c-dfda-4000-9b08-2fbb5fb92a95
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383805672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1383805672
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.729732769
Short name T447
Test name
Test status
Simulation time 13371909761 ps
CPU time 110.33 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:07:42 PM PDT 24
Peak memory 211420 kb
Host smart-c44bd745-ba11-439b-af7a-ed679998422f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=729732769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.729732769
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2797095724
Short name T417
Test name
Test status
Simulation time 765350435 ps
CPU time 29.36 seconds
Started Jun 05 04:05:53 PM PDT 24
Finished Jun 05 04:06:23 PM PDT 24
Peak memory 204272 kb
Host smart-a80491c5-69b9-4a7e-844d-7408827c4b58
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797095724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2797095724
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.2357580015
Short name T282
Test name
Test status
Simulation time 1277983560 ps
CPU time 29.19 seconds
Started Jun 05 04:05:50 PM PDT 24
Finished Jun 05 04:06:20 PM PDT 24
Peak memory 203876 kb
Host smart-bdb78744-c7ee-4f86-a1c8-02db400666c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2357580015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2357580015
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.3130198679
Short name T286
Test name
Test status
Simulation time 44995212 ps
CPU time 2.16 seconds
Started Jun 05 04:05:45 PM PDT 24
Finished Jun 05 04:05:48 PM PDT 24
Peak memory 203168 kb
Host smart-b08302d3-45d3-40f9-a165-1f4d6aa70526
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3130198679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3130198679
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1322984185
Short name T809
Test name
Test status
Simulation time 24020168577 ps
CPU time 32.58 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:06:24 PM PDT 24
Peak memory 203244 kb
Host smart-77775a40-e8f5-43dc-9aa6-5d8d4bb3fdf2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322984185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1322984185
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1426963985
Short name T7
Test name
Test status
Simulation time 3421611300 ps
CPU time 31.81 seconds
Started Jun 05 04:05:52 PM PDT 24
Finished Jun 05 04:06:25 PM PDT 24
Peak memory 203252 kb
Host smart-7840a829-0ee0-42b6-9c27-45f0f7748aa4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1426963985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1426963985
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3950610709
Short name T858
Test name
Test status
Simulation time 32418539 ps
CPU time 2.5 seconds
Started Jun 05 04:05:49 PM PDT 24
Finished Jun 05 04:05:53 PM PDT 24
Peak memory 203200 kb
Host smart-a439e74b-064a-4f4d-8cb9-5d5163902eaa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950610709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3950610709
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.4143812001
Short name T762
Test name
Test status
Simulation time 1013806883 ps
CPU time 124.67 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:07:56 PM PDT 24
Peak memory 208272 kb
Host smart-e94d9bff-c518-47d6-9517-8db8521c4225
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4143812001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4143812001
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2514874590
Short name T319
Test name
Test status
Simulation time 1613163570 ps
CPU time 41.45 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:06:34 PM PDT 24
Peak memory 204872 kb
Host smart-ecef97f1-05e3-4a93-b7fa-1ac8756e2770
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2514874590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2514874590
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2698871194
Short name T409
Test name
Test status
Simulation time 153449780 ps
CPU time 60.69 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:06:52 PM PDT 24
Peak memory 207780 kb
Host smart-d79bfba4-48cd-4dbf-afbd-55fd0fb0289d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2698871194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.2698871194
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3925671418
Short name T273
Test name
Test status
Simulation time 13515726212 ps
CPU time 305 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:10:56 PM PDT 24
Peak memory 211140 kb
Host smart-65792d08-e8dc-46ba-a80d-4fe8e7dbc519
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3925671418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.3925671418
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.160725417
Short name T572
Test name
Test status
Simulation time 261671898 ps
CPU time 14.26 seconds
Started Jun 05 04:05:52 PM PDT 24
Finished Jun 05 04:06:07 PM PDT 24
Peak memory 211252 kb
Host smart-72971b04-85c1-4dc1-bfb4-7a86d6446270
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=160725417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.160725417
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3092139452
Short name T348
Test name
Test status
Simulation time 66902336 ps
CPU time 2.97 seconds
Started Jun 05 04:05:59 PM PDT 24
Finished Jun 05 04:06:02 PM PDT 24
Peak memory 203184 kb
Host smart-3d7882e4-76e8-455b-911e-49a12f3db7ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3092139452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3092139452
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3639073944
Short name T227
Test name
Test status
Simulation time 21223773331 ps
CPU time 188.16 seconds
Started Jun 05 04:06:00 PM PDT 24
Finished Jun 05 04:09:09 PM PDT 24
Peak memory 211452 kb
Host smart-c40d53b7-8c8c-4e08-bf8d-11e2f054f649
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3639073944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.3639073944
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2267584995
Short name T290
Test name
Test status
Simulation time 162634568 ps
CPU time 11.14 seconds
Started Jun 05 04:06:00 PM PDT 24
Finished Jun 05 04:06:12 PM PDT 24
Peak memory 203676 kb
Host smart-39938151-c3d5-4f1a-a7d0-c3d6d6ff00dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2267584995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2267584995
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.3329895610
Short name T345
Test name
Test status
Simulation time 183787808 ps
CPU time 5.06 seconds
Started Jun 05 04:05:58 PM PDT 24
Finished Jun 05 04:06:03 PM PDT 24
Peak memory 203196 kb
Host smart-deb9f091-6c4f-452a-ae9a-135a874b9e95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3329895610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3329895610
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.207137480
Short name T456
Test name
Test status
Simulation time 280283388 ps
CPU time 10.12 seconds
Started Jun 05 04:05:53 PM PDT 24
Finished Jun 05 04:06:04 PM PDT 24
Peak memory 211260 kb
Host smart-ef6c69a1-792e-4625-ada2-372a5a1a8a7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=207137480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.207137480
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.4106535330
Short name T50
Test name
Test status
Simulation time 27322404122 ps
CPU time 71 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:07:03 PM PDT 24
Peak memory 211412 kb
Host smart-f3754d82-0b73-4700-97e7-d72f63217128
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106535330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4106535330
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2265065686
Short name T718
Test name
Test status
Simulation time 37224091814 ps
CPU time 215.39 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:09:27 PM PDT 24
Peak memory 204488 kb
Host smart-d40435c9-cbfb-426b-be7f-4fc86d27c151
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2265065686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2265065686
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2619341657
Short name T203
Test name
Test status
Simulation time 189936860 ps
CPU time 23.03 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:06:14 PM PDT 24
Peak memory 211288 kb
Host smart-b2116c77-80df-419c-91b9-c10b1700961c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619341657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2619341657
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.693912259
Short name T651
Test name
Test status
Simulation time 539539583 ps
CPU time 15.42 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:06:24 PM PDT 24
Peak memory 203732 kb
Host smart-2fb4641c-a55d-4c12-beb5-35da68ebcc3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=693912259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.693912259
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.3072790320
Short name T187
Test name
Test status
Simulation time 627776213 ps
CPU time 3.74 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:05:55 PM PDT 24
Peak memory 203128 kb
Host smart-f2a2fd42-8ec7-4efc-8e75-386a964873f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3072790320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3072790320
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.425268601
Short name T491
Test name
Test status
Simulation time 4674721511 ps
CPU time 29.09 seconds
Started Jun 05 04:05:52 PM PDT 24
Finished Jun 05 04:06:22 PM PDT 24
Peak memory 203252 kb
Host smart-2798f0b5-6dcf-4e51-967d-8ebffecbfd84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=425268601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.425268601
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.545483981
Short name T410
Test name
Test status
Simulation time 9032878947 ps
CPU time 38.17 seconds
Started Jun 05 04:05:48 PM PDT 24
Finished Jun 05 04:06:27 PM PDT 24
Peak memory 203248 kb
Host smart-e5121405-29a3-4ce5-9dcf-dc0e6b371353
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=545483981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.545483981
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.471626220
Short name T356
Test name
Test status
Simulation time 22993133 ps
CPU time 2.47 seconds
Started Jun 05 04:05:51 PM PDT 24
Finished Jun 05 04:05:54 PM PDT 24
Peak memory 203152 kb
Host smart-4e264ed2-1b99-455e-8eaf-983a9bda7f0b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471626220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.471626220
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.4098270772
Short name T72
Test name
Test status
Simulation time 6829595189 ps
CPU time 175.86 seconds
Started Jun 05 04:06:00 PM PDT 24
Finished Jun 05 04:08:56 PM PDT 24
Peak memory 208740 kb
Host smart-897826a6-2171-4553-b6e8-f81ee62abe35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4098270772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4098270772
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.496208035
Short name T339
Test name
Test status
Simulation time 1540603775 ps
CPU time 45.19 seconds
Started Jun 05 04:06:01 PM PDT 24
Finished Jun 05 04:06:47 PM PDT 24
Peak memory 205016 kb
Host smart-a8e01c5c-b2a1-4a51-8d1e-12aa6c80a6ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=496208035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.496208035
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2662453902
Short name T100
Test name
Test status
Simulation time 12732678532 ps
CPU time 541.46 seconds
Started Jun 05 04:05:58 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 219508 kb
Host smart-fa9fe5c3-e2c9-4fce-81f3-2e03dadd7011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2662453902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.2662453902
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.429487557
Short name T774
Test name
Test status
Simulation time 1160654280 ps
CPU time 203.01 seconds
Started Jun 05 04:06:01 PM PDT 24
Finished Jun 05 04:09:25 PM PDT 24
Peak memory 211384 kb
Host smart-5d419491-e19d-4998-b37e-20595d74680c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=429487557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res
et_error.429487557
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1543190492
Short name T493
Test name
Test status
Simulation time 34663548 ps
CPU time 3.44 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:06:12 PM PDT 24
Peak memory 211332 kb
Host smart-44bb6bcf-7264-4905-9902-9b3f0bad2852
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1543190492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1543190492
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3874066465
Short name T671
Test name
Test status
Simulation time 1621815208 ps
CPU time 39.2 seconds
Started Jun 05 04:06:01 PM PDT 24
Finished Jun 05 04:06:41 PM PDT 24
Peak memory 205620 kb
Host smart-1cb50adf-3894-43ca-bc80-534acdb348c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3874066465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3874066465
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.477315991
Short name T272
Test name
Test status
Simulation time 50061419706 ps
CPU time 298.4 seconds
Started Jun 05 04:05:58 PM PDT 24
Finished Jun 05 04:10:57 PM PDT 24
Peak memory 211464 kb
Host smart-4eb865d4-6ece-488b-a52c-ea7b6c81487a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=477315991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.477315991
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1128002057
Short name T849
Test name
Test status
Simulation time 126817927 ps
CPU time 14.28 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:06:21 PM PDT 24
Peak memory 203184 kb
Host smart-2e07ae72-2470-4038-be45-29f4e3a27c8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1128002057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1128002057
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.3069167550
Short name T401
Test name
Test status
Simulation time 3120922034 ps
CPU time 20.86 seconds
Started Jun 05 04:06:11 PM PDT 24
Finished Jun 05 04:06:32 PM PDT 24
Peak memory 203260 kb
Host smart-d1a89871-948c-4d0f-8134-f2f934a06f5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3069167550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3069167550
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.141995010
Short name T352
Test name
Test status
Simulation time 3068747802 ps
CPU time 46.06 seconds
Started Jun 05 04:05:58 PM PDT 24
Finished Jun 05 04:06:45 PM PDT 24
Peak memory 211420 kb
Host smart-a238b2b3-8f9f-4d8c-b38d-87a10d9eee45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=141995010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.141995010
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3062156646
Short name T789
Test name
Test status
Simulation time 3385289841 ps
CPU time 23.51 seconds
Started Jun 05 04:06:00 PM PDT 24
Finished Jun 05 04:06:24 PM PDT 24
Peak memory 203856 kb
Host smart-ac7fd0f9-49a2-472e-bb8a-c7308657166d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062156646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3062156646
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2562680663
Short name T82
Test name
Test status
Simulation time 31627591158 ps
CPU time 237.42 seconds
Started Jun 05 04:06:03 PM PDT 24
Finished Jun 05 04:10:01 PM PDT 24
Peak memory 211420 kb
Host smart-207a9f35-8de1-4f50-9238-f85836be806f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2562680663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2562680663
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3839409432
Short name T239
Test name
Test status
Simulation time 145380390 ps
CPU time 14.63 seconds
Started Jun 05 04:05:59 PM PDT 24
Finished Jun 05 04:06:14 PM PDT 24
Peak memory 204232 kb
Host smart-949fc4b2-752d-417f-b0ce-2223fe732e23
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839409432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3839409432
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.1506226092
Short name T21
Test name
Test status
Simulation time 933106638 ps
CPU time 20.82 seconds
Started Jun 05 04:06:00 PM PDT 24
Finished Jun 05 04:06:21 PM PDT 24
Peak memory 203192 kb
Host smart-2cc63900-8cde-42a7-a7b7-aa38391efcf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1506226092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1506226092
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.1076012483
Short name T764
Test name
Test status
Simulation time 131729227 ps
CPU time 3.53 seconds
Started Jun 05 04:05:58 PM PDT 24
Finished Jun 05 04:06:02 PM PDT 24
Peak memory 203116 kb
Host smart-79a876f4-12f1-44db-a846-ee1756a0f777
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1076012483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1076012483
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1041686832
Short name T79
Test name
Test status
Simulation time 5629256167 ps
CPU time 24.89 seconds
Started Jun 05 04:06:01 PM PDT 24
Finished Jun 05 04:06:26 PM PDT 24
Peak memory 203252 kb
Host smart-358b74df-c5d7-4771-8754-2f33505c26e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041686832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1041686832
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.870455094
Short name T737
Test name
Test status
Simulation time 4843618193 ps
CPU time 33.58 seconds
Started Jun 05 04:05:59 PM PDT 24
Finished Jun 05 04:06:33 PM PDT 24
Peak memory 203248 kb
Host smart-a62715ed-3728-4ec6-9438-5a429bb99ade
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=870455094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.870455094
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.882276244
Short name T376
Test name
Test status
Simulation time 36431820 ps
CPU time 2.52 seconds
Started Jun 05 04:05:59 PM PDT 24
Finished Jun 05 04:06:02 PM PDT 24
Peak memory 203196 kb
Host smart-ff971701-dc83-447c-98a2-1e8873fd1c2a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882276244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.882276244
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3779356959
Short name T644
Test name
Test status
Simulation time 2100148960 ps
CPU time 63.16 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:07:11 PM PDT 24
Peak memory 205452 kb
Host smart-6d7160fd-7f04-4c4e-becb-1f12fed10084
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3779356959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3779356959
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2509662433
Short name T583
Test name
Test status
Simulation time 12770973010 ps
CPU time 310.85 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 211428 kb
Host smart-e1d10975-8d7f-44e2-842e-dd3061b04b94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2509662433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2509662433
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2521273528
Short name T94
Test name
Test status
Simulation time 223701356 ps
CPU time 54.66 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 206568 kb
Host smart-ace14a57-4908-4e0c-beea-9b5e67b852d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2521273528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.2521273528
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3297451717
Short name T95
Test name
Test status
Simulation time 6834318907 ps
CPU time 218.2 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:09:45 PM PDT 24
Peak memory 209124 kb
Host smart-0c555a46-2428-41aa-a18f-2e2d3ccd4910
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3297451717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.3297451717
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3745325960
Short name T674
Test name
Test status
Simulation time 58873662 ps
CPU time 8.34 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:06:15 PM PDT 24
Peak memory 204636 kb
Host smart-37aa1601-0ec8-4478-aac3-e77be529e121
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3745325960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3745325960
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1479207238
Short name T399
Test name
Test status
Simulation time 153656862 ps
CPU time 18.27 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:06:27 PM PDT 24
Peak memory 211376 kb
Host smart-8260d060-c8b4-4352-9606-5140105f1a12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1479207238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1479207238
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2539367436
Short name T865
Test name
Test status
Simulation time 30545154509 ps
CPU time 211.8 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 211428 kb
Host smart-249b81e9-9b14-413d-a835-754004aa8c7d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2539367436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.2539367436
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.899812111
Short name T611
Test name
Test status
Simulation time 29468726 ps
CPU time 2.59 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:06:09 PM PDT 24
Peak memory 203180 kb
Host smart-85712bd9-d30d-4e64-90b8-8c8cb49c7ad7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=899812111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.899812111
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.2937058487
Short name T641
Test name
Test status
Simulation time 332907177 ps
CPU time 25.24 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:06:34 PM PDT 24
Peak memory 203104 kb
Host smart-bed7093b-8024-4008-950e-f0800b45ddb1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2937058487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2937058487
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.2837888117
Short name T206
Test name
Test status
Simulation time 430239835 ps
CPU time 15.32 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:23 PM PDT 24
Peak memory 204296 kb
Host smart-2238a98f-848a-4c41-a9d2-66604fb07fa0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2837888117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2837888117
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.910987013
Short name T701
Test name
Test status
Simulation time 78011572917 ps
CPU time 240.63 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:10:09 PM PDT 24
Peak memory 211416 kb
Host smart-f46f632e-6956-409c-a36b-377e07b5d184
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=910987013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.910987013
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.151052615
Short name T233
Test name
Test status
Simulation time 2672128011 ps
CPU time 24.1 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:32 PM PDT 24
Peak memory 203784 kb
Host smart-b69da2f1-7773-461c-9b35-9ed21f46978f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=151052615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.151052615
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.812659828
Short name T162
Test name
Test status
Simulation time 357627238 ps
CPU time 21.17 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:06:30 PM PDT 24
Peak memory 204724 kb
Host smart-ff12bf87-cc2a-48a4-814e-a82165dba2da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812659828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.812659828
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.1482555218
Short name T726
Test name
Test status
Simulation time 428528575 ps
CPU time 11.28 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:06:18 PM PDT 24
Peak memory 203200 kb
Host smart-96a3d152-21e8-4eb8-855b-aeaa56b3eaed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1482555218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1482555218
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.688647110
Short name T832
Test name
Test status
Simulation time 743911675 ps
CPU time 3.54 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:11 PM PDT 24
Peak memory 203036 kb
Host smart-e491bef9-cdd1-4fa1-a10a-3d57a2a2a315
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=688647110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.688647110
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1282483950
Short name T635
Test name
Test status
Simulation time 7591745981 ps
CPU time 37.15 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:45 PM PDT 24
Peak memory 203252 kb
Host smart-b0426bf8-9e48-4b9a-82ec-d95a5fa1f426
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282483950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1282483950
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.4065357230
Short name T154
Test name
Test status
Simulation time 3578755751 ps
CPU time 33.22 seconds
Started Jun 05 04:06:10 PM PDT 24
Finished Jun 05 04:06:44 PM PDT 24
Peak memory 203204 kb
Host smart-c89fbd86-58c2-4c8f-9489-4b518698ce96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4065357230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4065357230
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.935106804
Short name T324
Test name
Test status
Simulation time 42435810 ps
CPU time 2.47 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:10 PM PDT 24
Peak memory 203168 kb
Host smart-f6f3431c-8d04-421d-9c47-74da18199541
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935106804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.935106804
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2477674069
Short name T857
Test name
Test status
Simulation time 389003943 ps
CPU time 8.26 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:16 PM PDT 24
Peak memory 211380 kb
Host smart-af71e401-1e83-4cf8-b2e4-4c2434495893
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2477674069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2477674069
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.823049822
Short name T678
Test name
Test status
Simulation time 25701181 ps
CPU time 2.12 seconds
Started Jun 05 04:06:10 PM PDT 24
Finished Jun 05 04:06:13 PM PDT 24
Peak memory 203168 kb
Host smart-1a8b701e-dcc7-4d68-afed-dca643a850fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=823049822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.823049822
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2742494467
Short name T279
Test name
Test status
Simulation time 1595689749 ps
CPU time 165.98 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:08:53 PM PDT 24
Peak memory 211308 kb
Host smart-75f4f926-776e-4129-a588-3ef8723f7dbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2742494467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.2742494467
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3630904178
Short name T201
Test name
Test status
Simulation time 16021800 ps
CPU time 1.67 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:09 PM PDT 24
Peak memory 203060 kb
Host smart-fd2c2edc-4a4f-4b7c-953f-7f4548c457cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3630904178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3630904178
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.966378195
Short name T386
Test name
Test status
Simulation time 284674639 ps
CPU time 19.38 seconds
Started Jun 05 04:06:16 PM PDT 24
Finished Jun 05 04:06:36 PM PDT 24
Peak memory 204208 kb
Host smart-3c096df8-24b4-412d-ba22-4f60c8103f57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=966378195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.966378195
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3406659258
Short name T85
Test name
Test status
Simulation time 70552070213 ps
CPU time 603.3 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:16:21 PM PDT 24
Peak memory 207276 kb
Host smart-8355bf6a-4ca3-4c9b-bf22-aefa799703aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3406659258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.3406659258
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3990151294
Short name T209
Test name
Test status
Simulation time 684103500 ps
CPU time 25.32 seconds
Started Jun 05 04:06:15 PM PDT 24
Finished Jun 05 04:06:42 PM PDT 24
Peak memory 203180 kb
Host smart-a5dd9214-7dbd-4a3d-afd7-b36a337b6fe8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3990151294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3990151294
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.1522988494
Short name T411
Test name
Test status
Simulation time 1055642092 ps
CPU time 36.93 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:06:54 PM PDT 24
Peak memory 203184 kb
Host smart-94c1edd9-ed45-48b1-85cc-2ad46e6e44a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1522988494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1522988494
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.3725410382
Short name T307
Test name
Test status
Simulation time 165803070 ps
CPU time 15.66 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:06:24 PM PDT 24
Peak memory 204404 kb
Host smart-e94aacfd-f0f0-4e06-8d55-b2fd2f56b66b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3725410382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3725410382
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1540144751
Short name T642
Test name
Test status
Simulation time 47299750475 ps
CPU time 205.94 seconds
Started Jun 05 04:06:08 PM PDT 24
Finished Jun 05 04:09:34 PM PDT 24
Peak memory 211456 kb
Host smart-b1528772-c8ed-4894-a147-a1d2f24453f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540144751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1540144751
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.951514892
Short name T634
Test name
Test status
Simulation time 14200375783 ps
CPU time 77.96 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:07:35 PM PDT 24
Peak memory 211388 kb
Host smart-11324d30-dfb1-4981-adf0-cbf0f92d5e94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=951514892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.951514892
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2875307319
Short name T254
Test name
Test status
Simulation time 170544920 ps
CPU time 16.27 seconds
Started Jun 05 04:06:10 PM PDT 24
Finished Jun 05 04:06:27 PM PDT 24
Peak memory 211380 kb
Host smart-236a1799-86f4-4fdf-b65f-c6578a00353f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875307319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2875307319
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.1468900441
Short name T680
Test name
Test status
Simulation time 899955207 ps
CPU time 19.17 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:06:38 PM PDT 24
Peak memory 203112 kb
Host smart-cf35963e-7f67-4465-b964-f6ea8715cb4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1468900441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1468900441
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.145749999
Short name T357
Test name
Test status
Simulation time 138109158 ps
CPU time 3.89 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:12 PM PDT 24
Peak memory 203184 kb
Host smart-807d8b91-3a27-4d2c-ac11-b4293b0ac15a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=145749999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.145749999
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2993365353
Short name T487
Test name
Test status
Simulation time 7324780579 ps
CPU time 26.01 seconds
Started Jun 05 04:06:06 PM PDT 24
Finished Jun 05 04:06:33 PM PDT 24
Peak memory 203252 kb
Host smart-5678b115-537e-4597-b042-c45decafa208
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993365353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2993365353
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2546422182
Short name T471
Test name
Test status
Simulation time 4216084247 ps
CPU time 29.13 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:37 PM PDT 24
Peak memory 203256 kb
Host smart-ec01fed2-d050-4e8c-b6cd-6d82cc30caf6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2546422182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2546422182
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1187730258
Short name T391
Test name
Test status
Simulation time 48292114 ps
CPU time 2.69 seconds
Started Jun 05 04:06:07 PM PDT 24
Finished Jun 05 04:06:11 PM PDT 24
Peak memory 203200 kb
Host smart-39991ffe-8a10-4cbc-818a-240645860102
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187730258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1187730258
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1969103949
Short name T665
Test name
Test status
Simulation time 1116371410 ps
CPU time 117.42 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:08:16 PM PDT 24
Peak memory 207956 kb
Host smart-7ab5f4b7-3572-4c44-8c1a-1e1e8c072f3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1969103949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1969103949
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.4244546723
Short name T746
Test name
Test status
Simulation time 3228032668 ps
CPU time 102.68 seconds
Started Jun 05 04:06:19 PM PDT 24
Finished Jun 05 04:08:02 PM PDT 24
Peak memory 208068 kb
Host smart-7dddf719-82a0-4a70-9706-0c61325b34b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4244546723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4244546723
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3417469864
Short name T524
Test name
Test status
Simulation time 268708523 ps
CPU time 125.23 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:08:23 PM PDT 24
Peak memory 207988 kb
Host smart-51f2816f-06bb-4aef-95a0-b62e736e38f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3417469864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.3417469864
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1964351446
Short name T484
Test name
Test status
Simulation time 706824154 ps
CPU time 128.82 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:08:27 PM PDT 24
Peak memory 209868 kb
Host smart-d3cdc6e2-24d3-44af-96ed-f161c15050e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1964351446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.1964351446
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1841730151
Short name T695
Test name
Test status
Simulation time 748460768 ps
CPU time 21.37 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:06:39 PM PDT 24
Peak memory 204868 kb
Host smart-8e3fc930-9240-4c13-8529-0da27b3b4a20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1841730151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1841730151
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3323439484
Short name T742
Test name
Test status
Simulation time 1732100820 ps
CPU time 17.15 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:06:34 PM PDT 24
Peak memory 211344 kb
Host smart-6af5aa64-829f-4376-8cf9-65862eebb21d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3323439484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3323439484
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2739554143
Short name T850
Test name
Test status
Simulation time 145238842055 ps
CPU time 417.48 seconds
Started Jun 05 04:06:19 PM PDT 24
Finished Jun 05 04:13:17 PM PDT 24
Peak memory 205788 kb
Host smart-11cd741a-6cbc-4ccd-81ac-18f5fcc4726e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2739554143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.2739554143
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3496019801
Short name T542
Test name
Test status
Simulation time 6230152371 ps
CPU time 34.27 seconds
Started Jun 05 04:06:15 PM PDT 24
Finished Jun 05 04:06:50 PM PDT 24
Peak memory 204380 kb
Host smart-a0729f1d-cd04-40b1-b7e4-278de7bfeb5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3496019801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3496019801
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.1575361300
Short name T822
Test name
Test status
Simulation time 16451588 ps
CPU time 2.41 seconds
Started Jun 05 04:06:16 PM PDT 24
Finished Jun 05 04:06:19 PM PDT 24
Peak memory 203168 kb
Host smart-74dfc687-e6a4-4983-a1d0-5a3bbc4a549c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1575361300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1575361300
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.1621216762
Short name T881
Test name
Test status
Simulation time 38298708 ps
CPU time 3.75 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:06:22 PM PDT 24
Peak memory 203092 kb
Host smart-87713ea2-1717-453b-8862-9c20d3548f76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1621216762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1621216762
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1266805427
Short name T327
Test name
Test status
Simulation time 24836169203 ps
CPU time 67.41 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:07:26 PM PDT 24
Peak memory 211448 kb
Host smart-8a0c2f0f-41a1-44c6-9beb-e6e5f4bb11c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266805427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1266805427
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1948848910
Short name T571
Test name
Test status
Simulation time 45462653541 ps
CPU time 186.26 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:09:25 PM PDT 24
Peak memory 211448 kb
Host smart-5671575b-8305-4486-8689-680eeacd2827
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1948848910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1948848910
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3051265238
Short name T748
Test name
Test status
Simulation time 664443814 ps
CPU time 18.08 seconds
Started Jun 05 04:06:16 PM PDT 24
Finished Jun 05 04:06:35 PM PDT 24
Peak memory 211380 kb
Host smart-c6dfee21-a555-4023-bc8f-520798337a1a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051265238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3051265238
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.1983046129
Short name T578
Test name
Test status
Simulation time 1881063572 ps
CPU time 17.73 seconds
Started Jun 05 04:06:19 PM PDT 24
Finished Jun 05 04:06:37 PM PDT 24
Peak memory 203200 kb
Host smart-461a4b2d-d92c-4e47-929b-6bd3bffd286c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1983046129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1983046129
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.1546275643
Short name T827
Test name
Test status
Simulation time 585825699 ps
CPU time 3.35 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:06:23 PM PDT 24
Peak memory 203172 kb
Host smart-ed30d7d0-9d52-44b4-bd7b-1872cc7c1602
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1546275643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1546275643
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2765085467
Short name T328
Test name
Test status
Simulation time 15351351704 ps
CPU time 41.61 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 203260 kb
Host smart-86089feb-0b32-4006-8dc1-c7126c2fec77
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765085467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2765085467
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.798924438
Short name T523
Test name
Test status
Simulation time 4513268284 ps
CPU time 29.29 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:06:47 PM PDT 24
Peak memory 203248 kb
Host smart-8eda9f03-a473-4454-9a73-0a2098904064
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=798924438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.798924438
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.403076337
Short name T393
Test name
Test status
Simulation time 40067284 ps
CPU time 2.26 seconds
Started Jun 05 04:06:16 PM PDT 24
Finished Jun 05 04:06:19 PM PDT 24
Peak memory 203152 kb
Host smart-ce577b99-1ea9-4c3b-92b2-3d4701e885e2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403076337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.403076337
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1605362331
Short name T74
Test name
Test status
Simulation time 3605977253 ps
CPU time 75.84 seconds
Started Jun 05 04:06:15 PM PDT 24
Finished Jun 05 04:07:31 PM PDT 24
Peak memory 206716 kb
Host smart-0f6480dc-e175-4e7f-ab8c-55f561749b8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1605362331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1605362331
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1849396065
Short name T531
Test name
Test status
Simulation time 49036704 ps
CPU time 4.33 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:06:24 PM PDT 24
Peak memory 203184 kb
Host smart-2d996e37-5770-4037-8443-73ff395a4f76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1849396065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1849396065
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3784912939
Short name T215
Test name
Test status
Simulation time 3524700641 ps
CPU time 596.45 seconds
Started Jun 05 04:06:16 PM PDT 24
Finished Jun 05 04:16:13 PM PDT 24
Peak memory 208544 kb
Host smart-a1e2f926-4c0b-4dc8-8506-9e90053ce2b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3784912939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.3784912939
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.833861554
Short name T210
Test name
Test status
Simulation time 1968711044 ps
CPU time 303.7 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:11:23 PM PDT 24
Peak memory 223116 kb
Host smart-0b7f7088-7741-4127-be98-e1ae6f27a62c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=833861554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res
et_error.833861554
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1591907598
Short name T712
Test name
Test status
Simulation time 529968587 ps
CPU time 23.85 seconds
Started Jun 05 04:06:18 PM PDT 24
Finished Jun 05 04:06:43 PM PDT 24
Peak memory 211616 kb
Host smart-ed298ed8-4ce8-4e6f-89dc-9e9e97baccb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1591907598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1591907598
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.470098607
Short name T837
Test name
Test status
Simulation time 265501976 ps
CPU time 22.98 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:06:50 PM PDT 24
Peak memory 204164 kb
Host smart-a63230ad-0b29-448d-b584-86cb7dab4ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=470098607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.470098607
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2303309913
Short name T599
Test name
Test status
Simulation time 5435958740 ps
CPU time 45.57 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:07:14 PM PDT 24
Peak memory 211324 kb
Host smart-4cf74b4d-9ae5-4be2-b154-c0bb0633b510
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2303309913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.2303309913
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.286667085
Short name T119
Test name
Test status
Simulation time 1280111171 ps
CPU time 23.72 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:06:51 PM PDT 24
Peak memory 203504 kb
Host smart-76c206e8-9501-4329-9bb3-8d3b8c0364be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=286667085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.286667085
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.1846844984
Short name T808
Test name
Test status
Simulation time 156110513 ps
CPU time 5.97 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:06:33 PM PDT 24
Peak memory 203072 kb
Host smart-21ddcaf1-7c6f-40b7-bcc6-8185b3384a9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846844984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1846844984
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.717663722
Short name T559
Test name
Test status
Simulation time 157864083 ps
CPU time 20.94 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:06:49 PM PDT 24
Peak memory 211256 kb
Host smart-b04e5a52-cedb-4c7c-9d38-f9b1070af75f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=717663722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.717663722
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.194167499
Short name T480
Test name
Test status
Simulation time 24377355487 ps
CPU time 153.47 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 204412 kb
Host smart-4385907b-0ccd-405c-ab88-54ca4931fc5f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=194167499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.194167499
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2164923941
Short name T496
Test name
Test status
Simulation time 19997868226 ps
CPU time 150.61 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:08:58 PM PDT 24
Peak memory 204456 kb
Host smart-18436c7c-2bca-4c19-b304-34d2b4616bec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2164923941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2164923941
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1746922230
Short name T398
Test name
Test status
Simulation time 142984487 ps
CPU time 10.82 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:06:39 PM PDT 24
Peak memory 204452 kb
Host smart-f670b0a5-d9d1-493e-a716-461ce552d008
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746922230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1746922230
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1555775563
Short name T461
Test name
Test status
Simulation time 104163502 ps
CPU time 8.34 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:06:36 PM PDT 24
Peak memory 203224 kb
Host smart-a8c7758e-12e2-497c-ba8d-ceac649b2462
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1555775563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1555775563
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.3026394229
Short name T299
Test name
Test status
Simulation time 30072379 ps
CPU time 2.21 seconds
Started Jun 05 04:06:17 PM PDT 24
Finished Jun 05 04:06:20 PM PDT 24
Peak memory 203168 kb
Host smart-7bd74140-c8bf-4a9f-a38d-6f27042ef291
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3026394229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3026394229
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3260161122
Short name T555
Test name
Test status
Simulation time 10577612965 ps
CPU time 31.08 seconds
Started Jun 05 04:06:25 PM PDT 24
Finished Jun 05 04:06:57 PM PDT 24
Peak memory 203228 kb
Host smart-2e04ee3a-37f7-47ce-aaf1-e2c89af481df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260161122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3260161122
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4222353780
Short name T59
Test name
Test status
Simulation time 10659679667 ps
CPU time 34.09 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 203248 kb
Host smart-595f7daa-504b-4879-ae33-e341baf21ba5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4222353780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4222353780
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2683736916
Short name T659
Test name
Test status
Simulation time 52262153 ps
CPU time 2.35 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:06:29 PM PDT 24
Peak memory 203156 kb
Host smart-e3c1c058-015a-4290-9cf3-b602aa1c225e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683736916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2683736916
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1456558671
Short name T318
Test name
Test status
Simulation time 25638834672 ps
CPU time 233.48 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:10:21 PM PDT 24
Peak memory 209308 kb
Host smart-0a526b28-73a9-4bc8-97fc-c80c9be744bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1456558671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1456558671
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1746487980
Short name T851
Test name
Test status
Simulation time 2009423051 ps
CPU time 69.87 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:07:36 PM PDT 24
Peak memory 205156 kb
Host smart-fbf61343-2f4e-47e7-b768-bbccff2b94e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1746487980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1746487980
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3144570866
Short name T716
Test name
Test status
Simulation time 9095011543 ps
CPU time 364.51 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:12:32 PM PDT 24
Peak memory 210384 kb
Host smart-3bb61219-fdab-4c24-b8b2-52aa9e9dae41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3144570866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.3144570866
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3477233416
Short name T464
Test name
Test status
Simulation time 338081310 ps
CPU time 108.06 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:08:16 PM PDT 24
Peak memory 209504 kb
Host smart-9fedbcd5-732c-4ab5-94bc-d10476ed0a23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3477233416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.3477233416
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.4270003252
Short name T387
Test name
Test status
Simulation time 1235479514 ps
CPU time 24.99 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:06:52 PM PDT 24
Peak memory 204744 kb
Host smart-32257593-33e7-4e40-a463-83b2295d36cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4270003252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4270003252
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.279850351
Short name T142
Test name
Test status
Simulation time 466021594 ps
CPU time 23.39 seconds
Started Jun 05 04:04:07 PM PDT 24
Finished Jun 05 04:04:31 PM PDT 24
Peak memory 211364 kb
Host smart-b6101e0c-fbd4-4009-a74d-7debc19811ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=279850351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.279850351
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.47829199
Short name T130
Test name
Test status
Simulation time 41745573200 ps
CPU time 300.41 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:09:10 PM PDT 24
Peak memory 211368 kb
Host smart-731f5d39-4005-4271-9821-645f65c6250e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=47829199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.47829199
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.962796310
Short name T502
Test name
Test status
Simulation time 217956060 ps
CPU time 2.08 seconds
Started Jun 05 04:04:12 PM PDT 24
Finished Jun 05 04:04:15 PM PDT 24
Peak memory 203128 kb
Host smart-2a501aea-d33e-4b3d-9431-c627e1b68048
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=962796310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.962796310
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.185554609
Short name T826
Test name
Test status
Simulation time 65687702 ps
CPU time 8.56 seconds
Started Jun 05 04:04:12 PM PDT 24
Finished Jun 05 04:04:21 PM PDT 24
Peak memory 203192 kb
Host smart-9fe19732-b8ae-4f23-9ff9-9f0ecca50d6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=185554609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.185554609
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.1688125683
Short name T185
Test name
Test status
Simulation time 176980018 ps
CPU time 21.23 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:04:31 PM PDT 24
Peak memory 211360 kb
Host smart-0ae7bfe7-637b-4b63-86fe-529b30113c87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1688125683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1688125683
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1574388336
Short name T482
Test name
Test status
Simulation time 80064753781 ps
CPU time 181.43 seconds
Started Jun 05 04:04:08 PM PDT 24
Finished Jun 05 04:07:10 PM PDT 24
Peak memory 211428 kb
Host smart-73e89bd6-176e-42a5-9087-436d6c8148ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574388336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1574388336
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3813852335
Short name T2
Test name
Test status
Simulation time 22010104895 ps
CPU time 159.6 seconds
Started Jun 05 04:04:08 PM PDT 24
Finished Jun 05 04:06:49 PM PDT 24
Peak memory 211360 kb
Host smart-fadeb197-e9ae-4a65-8366-51960d004900
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3813852335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3813852335
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2079503323
Short name T752
Test name
Test status
Simulation time 67447683 ps
CPU time 8.82 seconds
Started Jun 05 04:04:08 PM PDT 24
Finished Jun 05 04:04:17 PM PDT 24
Peak memory 211380 kb
Host smart-9d67b78b-2062-4fab-a764-c9e67f9ce57f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079503323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2079503323
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.1487338416
Short name T521
Test name
Test status
Simulation time 46440645 ps
CPU time 4.02 seconds
Started Jun 05 04:04:10 PM PDT 24
Finished Jun 05 04:04:14 PM PDT 24
Peak memory 203200 kb
Host smart-95cd8cb4-4659-4334-adc2-82e48e5445f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1487338416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1487338416
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.923302822
Short name T136
Test name
Test status
Simulation time 136061181 ps
CPU time 3.72 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:04:02 PM PDT 24
Peak memory 203180 kb
Host smart-af92254c-90df-44ca-a1e0-881cf502aed4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=923302822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.923302822
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2094292896
Short name T740
Test name
Test status
Simulation time 6614955112 ps
CPU time 30.79 seconds
Started Jun 05 04:03:57 PM PDT 24
Finished Jun 05 04:04:29 PM PDT 24
Peak memory 203240 kb
Host smart-ecb299ef-5702-4f1b-a634-5f121efd588c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094292896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2094292896
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.735524816
Short name T620
Test name
Test status
Simulation time 21973012684 ps
CPU time 40.31 seconds
Started Jun 05 04:03:58 PM PDT 24
Finished Jun 05 04:04:39 PM PDT 24
Peak memory 203244 kb
Host smart-d7344aaf-a3d9-4275-ac5a-a5bc38a9501d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=735524816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.735524816
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2407694685
Short name T291
Test name
Test status
Simulation time 58997962 ps
CPU time 2.32 seconds
Started Jun 05 04:03:56 PM PDT 24
Finished Jun 05 04:03:59 PM PDT 24
Peak memory 203096 kb
Host smart-eae576df-366a-4c3b-9302-4838a16cbc61
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407694685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2407694685
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1460535937
Short name T573
Test name
Test status
Simulation time 8978999160 ps
CPU time 182.26 seconds
Started Jun 05 04:04:13 PM PDT 24
Finished Jun 05 04:07:16 PM PDT 24
Peak memory 209184 kb
Host smart-02fef2f4-04e6-460a-92ec-fe501f4c6025
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1460535937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1460535937
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3916340658
Short name T421
Test name
Test status
Simulation time 962309232 ps
CPU time 57.95 seconds
Started Jun 05 04:04:11 PM PDT 24
Finished Jun 05 04:05:10 PM PDT 24
Peak memory 205916 kb
Host smart-f772a3c2-3cd1-4839-9728-2f08aa81dfc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3916340658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3916340658
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2739915612
Short name T696
Test name
Test status
Simulation time 959748177 ps
CPU time 340.52 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:09:51 PM PDT 24
Peak memory 209764 kb
Host smart-88209262-e699-48f0-9f81-d126ccc5c1cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2739915612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.2739915612
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3049873793
Short name T697
Test name
Test status
Simulation time 468376582 ps
CPU time 188.17 seconds
Started Jun 05 04:04:06 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 211372 kb
Host smart-11664e0c-7184-4617-abd8-66be754df682
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3049873793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.3049873793
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.224542588
Short name T228
Test name
Test status
Simulation time 66663998 ps
CPU time 2.15 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:04:11 PM PDT 24
Peak memory 203208 kb
Host smart-948083ba-5d4c-48d3-a64a-7b8e2b9844b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=224542588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.224542588
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1301273294
Short name T153
Test name
Test status
Simulation time 470041400 ps
CPU time 33.07 seconds
Started Jun 05 04:06:33 PM PDT 24
Finished Jun 05 04:07:07 PM PDT 24
Peak memory 204232 kb
Host smart-987dedc2-e506-4b36-a540-6a89c02e2056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1301273294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1301273294
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1213805726
Short name T503
Test name
Test status
Simulation time 45267025297 ps
CPU time 368.8 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:12:44 PM PDT 24
Peak memory 206596 kb
Host smart-c20be71b-fdd8-4098-beac-df10876880b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1213805726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.1213805726
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.268008781
Short name T615
Test name
Test status
Simulation time 112640429 ps
CPU time 16.65 seconds
Started Jun 05 04:06:34 PM PDT 24
Finished Jun 05 04:06:51 PM PDT 24
Peak memory 203180 kb
Host smart-69d81f2e-8bcf-4f9b-a809-983441fc60a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=268008781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.268008781
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.743739877
Short name T656
Test name
Test status
Simulation time 1141887258 ps
CPU time 39.18 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 203196 kb
Host smart-dbee3020-2cfe-4f90-9e99-d4529b1df3ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=743739877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.743739877
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.2190110739
Short name T765
Test name
Test status
Simulation time 618517145 ps
CPU time 25.12 seconds
Started Jun 05 04:06:29 PM PDT 24
Finished Jun 05 04:06:55 PM PDT 24
Peak memory 211360 kb
Host smart-c0e8955f-12e6-4cf1-94a6-ff2c0169cdc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2190110739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2190110739
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1371694468
Short name T54
Test name
Test status
Simulation time 13471419024 ps
CPU time 65.41 seconds
Started Jun 05 04:06:34 PM PDT 24
Finished Jun 05 04:07:39 PM PDT 24
Peak memory 211456 kb
Host smart-88e571a1-a63b-48f2-b771-1531545d0c96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371694468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1371694468
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3499284679
Short name T710
Test name
Test status
Simulation time 43348132682 ps
CPU time 160.21 seconds
Started Jun 05 04:06:34 PM PDT 24
Finished Jun 05 04:09:14 PM PDT 24
Peak memory 211380 kb
Host smart-bff1318c-0a58-4269-8c5c-1c4a9502e700
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3499284679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3499284679
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.506200314
Short name T776
Test name
Test status
Simulation time 96627898 ps
CPU time 8.42 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:06:37 PM PDT 24
Peak memory 204256 kb
Host smart-40809c0e-0a9d-4dee-8c65-5506d9acd349
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506200314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.506200314
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.3762093349
Short name T371
Test name
Test status
Simulation time 242338963 ps
CPU time 17.27 seconds
Started Jun 05 04:06:33 PM PDT 24
Finished Jun 05 04:06:51 PM PDT 24
Peak memory 203248 kb
Host smart-a95d3bb5-493f-4fd7-a7af-2b7c3fa62b07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3762093349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3762093349
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.4126206311
Short name T588
Test name
Test status
Simulation time 31426452 ps
CPU time 2.16 seconds
Started Jun 05 04:06:27 PM PDT 24
Finished Jun 05 04:06:30 PM PDT 24
Peak memory 203088 kb
Host smart-8a46b855-707e-42f8-90ac-ecbe9a67af8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4126206311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.4126206311
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4238414229
Short name T650
Test name
Test status
Simulation time 5925866331 ps
CPU time 30.56 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:06:58 PM PDT 24
Peak memory 203248 kb
Host smart-01a200a7-633b-433f-b258-73169d503ade
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238414229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4238414229
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1206575022
Short name T551
Test name
Test status
Simulation time 14479476041 ps
CPU time 33.88 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 203248 kb
Host smart-63c5724d-dd36-41a8-bfc1-45cc8f63e9e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1206575022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1206575022
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1343626849
Short name T186
Test name
Test status
Simulation time 157323652 ps
CPU time 2.42 seconds
Started Jun 05 04:06:26 PM PDT 24
Finished Jun 05 04:06:30 PM PDT 24
Peak memory 203440 kb
Host smart-fdc0ef29-abc2-4317-bcee-fe5bd9e1aff8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343626849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1343626849
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1381920647
Short name T314
Test name
Test status
Simulation time 2540000879 ps
CPU time 53.53 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:07:29 PM PDT 24
Peak memory 206960 kb
Host smart-16f14c0c-71c2-4676-9cd0-339560558862
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1381920647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1381920647
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2517371888
Short name T759
Test name
Test status
Simulation time 7372987640 ps
CPU time 229.59 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 206804 kb
Host smart-6cf46ee6-f1b2-4aa9-8a92-d33bba741e45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2517371888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2517371888
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.721616417
Short name T68
Test name
Test status
Simulation time 2737736230 ps
CPU time 178.83 seconds
Started Jun 05 04:06:37 PM PDT 24
Finished Jun 05 04:09:36 PM PDT 24
Peak memory 208240 kb
Host smart-53e488dd-0d36-4681-a1ef-dace370361c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=721616417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand
_reset.721616417
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2973525685
Short name T664
Test name
Test status
Simulation time 247175017 ps
CPU time 73.89 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:07:49 PM PDT 24
Peak memory 206984 kb
Host smart-36eb9b7c-7390-48d0-8375-7ea6370276fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2973525685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.2973525685
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.903106461
Short name T66
Test name
Test status
Simulation time 1440838152 ps
CPU time 28.56 seconds
Started Jun 05 04:06:34 PM PDT 24
Finished Jun 05 04:07:03 PM PDT 24
Peak memory 211276 kb
Host smart-e4575f78-0bb9-487b-af32-446545a55289
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903106461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.903106461
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1292999797
Short name T88
Test name
Test status
Simulation time 6568652474 ps
CPU time 69.45 seconds
Started Jun 05 04:06:33 PM PDT 24
Finished Jun 05 04:07:43 PM PDT 24
Peak memory 205572 kb
Host smart-1064f434-355f-4a4f-8175-5704daa7c26e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1292999797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1292999797
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.918923753
Short name T268
Test name
Test status
Simulation time 157377265308 ps
CPU time 410.76 seconds
Started Jun 05 04:06:33 PM PDT 24
Finished Jun 05 04:13:25 PM PDT 24
Peak memory 211396 kb
Host smart-b7d60580-335d-4f01-ab5a-e2d0eb7acd25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=918923753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo
w_rsp.918923753
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2894398172
Short name T396
Test name
Test status
Simulation time 671358240 ps
CPU time 15.65 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:06:52 PM PDT 24
Peak memory 203192 kb
Host smart-81fcc4da-ce8d-4d38-95e5-1d4582bcb407
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2894398172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2894398172
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.3556996863
Short name T750
Test name
Test status
Simulation time 103612636 ps
CPU time 13.5 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:06:49 PM PDT 24
Peak memory 203200 kb
Host smart-1cbcb4b9-adaa-424e-a6fe-c1d890ba08db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3556996863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3556996863
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.3934178582
Short name T561
Test name
Test status
Simulation time 163002124 ps
CPU time 19.75 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:06:55 PM PDT 24
Peak memory 204404 kb
Host smart-64e4e500-4dbe-49ae-9a71-e60d676ab3f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934178582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3934178582
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.691908148
Short name T138
Test name
Test status
Simulation time 133821600951 ps
CPU time 296.76 seconds
Started Jun 05 04:06:36 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 211444 kb
Host smart-50307069-f3d0-4d5f-8545-e3cd9a441852
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=691908148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.691908148
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.865214079
Short name T407
Test name
Test status
Simulation time 9219325763 ps
CPU time 24.13 seconds
Started Jun 05 04:06:34 PM PDT 24
Finished Jun 05 04:06:59 PM PDT 24
Peak memory 211416 kb
Host smart-c250d58a-303a-4605-bc4b-9328ed0d2958
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=865214079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.865214079
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1114801105
Short name T260
Test name
Test status
Simulation time 225457715 ps
CPU time 18.19 seconds
Started Jun 05 04:06:36 PM PDT 24
Finished Jun 05 04:06:55 PM PDT 24
Peak memory 204316 kb
Host smart-afef2e55-dfa6-49e3-8bb2-79bce1fe428d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114801105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1114801105
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.3747206127
Short name T218
Test name
Test status
Simulation time 220525817 ps
CPU time 4.08 seconds
Started Jun 05 04:06:34 PM PDT 24
Finished Jun 05 04:06:39 PM PDT 24
Peak memory 203200 kb
Host smart-46f31cb7-7eaa-4388-9375-620b27e029c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3747206127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3747206127
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.73046840
Short name T876
Test name
Test status
Simulation time 165833563 ps
CPU time 3.83 seconds
Started Jun 05 04:06:35 PM PDT 24
Finished Jun 05 04:06:39 PM PDT 24
Peak memory 203176 kb
Host smart-5d242aac-d6bc-40c0-80b2-efb53cc11abb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73046840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.73046840
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3193533434
Short name T308
Test name
Test status
Simulation time 20712630709 ps
CPU time 40.26 seconds
Started Jun 05 04:06:33 PM PDT 24
Finished Jun 05 04:07:14 PM PDT 24
Peak memory 203268 kb
Host smart-b9946719-1843-4996-a199-6fa732acca5d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193533434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3193533434
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1050819424
Short name T404
Test name
Test status
Simulation time 3462428315 ps
CPU time 26.39 seconds
Started Jun 05 04:06:36 PM PDT 24
Finished Jun 05 04:07:04 PM PDT 24
Peak memory 203248 kb
Host smart-501acf7a-1629-4e25-881c-1088ce502cf6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1050819424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1050819424
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.672502469
Short name T373
Test name
Test status
Simulation time 51318752 ps
CPU time 2.34 seconds
Started Jun 05 04:06:36 PM PDT 24
Finished Jun 05 04:06:39 PM PDT 24
Peak memory 203084 kb
Host smart-bebccfa3-bd6c-4cab-b8cb-3ebf37df4073
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672502469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.672502469
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3076364210
Short name T232
Test name
Test status
Simulation time 2176197419 ps
CPU time 63.44 seconds
Started Jun 05 04:06:34 PM PDT 24
Finished Jun 05 04:07:38 PM PDT 24
Peak memory 206532 kb
Host smart-0c526955-9d37-4f07-af0e-ebbddfdbb38f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3076364210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3076364210
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1733048356
Short name T204
Test name
Test status
Simulation time 4722834007 ps
CPU time 50.37 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:33 PM PDT 24
Peak memory 205848 kb
Host smart-ccfaf810-9208-4191-a771-5a66d8ca1c20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1733048356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1733048356
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1799591020
Short name T381
Test name
Test status
Simulation time 91726061 ps
CPU time 24.6 seconds
Started Jun 05 04:06:44 PM PDT 24
Finished Jun 05 04:07:09 PM PDT 24
Peak memory 206364 kb
Host smart-2bc07463-67ff-4256-a040-e72f782507ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1799591020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.1799591020
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3671455763
Short name T836
Test name
Test status
Simulation time 15484792838 ps
CPU time 576.36 seconds
Started Jun 05 04:06:41 PM PDT 24
Finished Jun 05 04:16:18 PM PDT 24
Peak memory 219640 kb
Host smart-71936ab6-d936-488b-897d-74c8da49c7e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3671455763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.3671455763
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1863503335
Short name T760
Test name
Test status
Simulation time 2685851358 ps
CPU time 20.59 seconds
Started Jun 05 04:06:36 PM PDT 24
Finished Jun 05 04:06:57 PM PDT 24
Peak memory 204936 kb
Host smart-997e2522-122e-40a1-8fbf-e5ddd9c9f759
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1863503335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1863503335
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3410270620
Short name T121
Test name
Test status
Simulation time 381863320 ps
CPU time 31.61 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 211332 kb
Host smart-22b61832-6da3-4d79-90f6-4c27777c4dfa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3410270620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3410270620
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.34697542
Short name T683
Test name
Test status
Simulation time 91286640172 ps
CPU time 692.37 seconds
Started Jun 05 04:06:41 PM PDT 24
Finished Jun 05 04:18:14 PM PDT 24
Peak memory 207168 kb
Host smart-d159ec93-a7d0-46fd-b394-a20afabba303
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=34697542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow
_rsp.34697542
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2876015749
Short name T590
Test name
Test status
Simulation time 196934719 ps
CPU time 13.51 seconds
Started Jun 05 04:06:43 PM PDT 24
Finished Jun 05 04:06:58 PM PDT 24
Peak memory 203724 kb
Host smart-df585466-fcdd-443e-a62f-4d31504b033c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2876015749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2876015749
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.120791526
Short name T702
Test name
Test status
Simulation time 198083152 ps
CPU time 9.18 seconds
Started Jun 05 04:06:41 PM PDT 24
Finished Jun 05 04:06:51 PM PDT 24
Peak memory 203212 kb
Host smart-983d9ae5-8c8c-47e6-95fc-aef6324bb7b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=120791526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.120791526
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.2505144840
Short name T556
Test name
Test status
Simulation time 55894064 ps
CPU time 6.03 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:06:49 PM PDT 24
Peak memory 204228 kb
Host smart-8de8476e-72d0-4fb2-a09d-85c395c134a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2505144840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2505144840
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2405018125
Short name T794
Test name
Test status
Simulation time 15117872400 ps
CPU time 60.88 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:44 PM PDT 24
Peak memory 204584 kb
Host smart-d9f75068-53a0-4eaf-8b31-0ecb2ba74c18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405018125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2405018125
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2735062226
Short name T149
Test name
Test status
Simulation time 22230384340 ps
CPU time 67.66 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:51 PM PDT 24
Peak memory 204628 kb
Host smart-91b5099e-6b46-4177-9733-e8b30abf540c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2735062226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2735062226
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.122646128
Short name T889
Test name
Test status
Simulation time 22995203 ps
CPU time 2.42 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:06:45 PM PDT 24
Peak memory 203116 kb
Host smart-8ffca66b-e5eb-4cee-b19d-d01641e31ebe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122646128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.122646128
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.2259571952
Short name T445
Test name
Test status
Simulation time 2366289148 ps
CPU time 14.04 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:06:57 PM PDT 24
Peak memory 203716 kb
Host smart-5215c91b-80b9-48a7-a966-2598e160e45f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2259571952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2259571952
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.4029272229
Short name T706
Test name
Test status
Simulation time 45005820 ps
CPU time 2.5 seconds
Started Jun 05 04:06:46 PM PDT 24
Finished Jun 05 04:06:49 PM PDT 24
Peak memory 203168 kb
Host smart-d27a74eb-a544-4d28-95be-13c85348fd14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4029272229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4029272229
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1360551935
Short name T783
Test name
Test status
Simulation time 9690723085 ps
CPU time 27.68 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:11 PM PDT 24
Peak memory 203268 kb
Host smart-cd9afde1-9cb4-4a25-a8fa-a4ba0b9b6431
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360551935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1360551935
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1924015128
Short name T831
Test name
Test status
Simulation time 3025102443 ps
CPU time 23.95 seconds
Started Jun 05 04:06:43 PM PDT 24
Finished Jun 05 04:07:08 PM PDT 24
Peak memory 203248 kb
Host smart-c46717ac-70b3-4fef-81ed-0b9afc75f5c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1924015128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1924015128
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.928078183
Short name T732
Test name
Test status
Simulation time 117497627 ps
CPU time 2.4 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:06:45 PM PDT 24
Peak memory 203196 kb
Host smart-bb752358-2ec2-4661-b683-4fbfd1082395
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928078183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.928078183
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1461755023
Short name T715
Test name
Test status
Simulation time 4258544581 ps
CPU time 144.22 seconds
Started Jun 05 04:06:41 PM PDT 24
Finished Jun 05 04:09:07 PM PDT 24
Peak memory 211448 kb
Host smart-00b49778-937e-4792-8d60-2ee7cc45a081
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1461755023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1461755023
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1911648528
Short name T231
Test name
Test status
Simulation time 3854251645 ps
CPU time 238.6 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:10:42 PM PDT 24
Peak memory 211400 kb
Host smart-6a5b44e4-1a1b-42e7-a98e-daf5e651e138
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1911648528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1911648528
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1874908442
Short name T171
Test name
Test status
Simulation time 1474717895 ps
CPU time 219.61 seconds
Started Jun 05 04:06:40 PM PDT 24
Finished Jun 05 04:10:21 PM PDT 24
Peak memory 207832 kb
Host smart-c9fbb0be-1925-4514-8c60-2e7ded485746
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1874908442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.1874908442
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4197897738
Short name T331
Test name
Test status
Simulation time 2049612371 ps
CPU time 143.79 seconds
Started Jun 05 04:06:41 PM PDT 24
Finished Jun 05 04:09:06 PM PDT 24
Peak memory 209840 kb
Host smart-b50dae55-1d69-42ef-8e27-d1b68bf3a15e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4197897738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.4197897738
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1783495178
Short name T11
Test name
Test status
Simulation time 530637892 ps
CPU time 18.75 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 204668 kb
Host smart-f692bc25-0a38-40cc-a97a-a9c4fc3d3be1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1783495178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1783495178
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.530650936
Short name T89
Test name
Test status
Simulation time 973254736 ps
CPU time 46.89 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:30 PM PDT 24
Peak memory 205636 kb
Host smart-b67001ed-9ef6-4efc-afca-8ca85462826c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=530650936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.530650936
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1211204246
Short name T784
Test name
Test status
Simulation time 492041920 ps
CPU time 14.79 seconds
Started Jun 05 04:06:50 PM PDT 24
Finished Jun 05 04:07:05 PM PDT 24
Peak memory 203284 kb
Host smart-becbd94d-7030-41b0-8f5d-edacb04334f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1211204246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1211204246
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.2716743510
Short name T771
Test name
Test status
Simulation time 1253844221 ps
CPU time 16.94 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:00 PM PDT 24
Peak memory 203120 kb
Host smart-5c6a6707-e56f-4119-aa98-42153bc9db72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2716743510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2716743510
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.3439851448
Short name T151
Test name
Test status
Simulation time 682902216 ps
CPU time 19.26 seconds
Started Jun 05 04:06:43 PM PDT 24
Finished Jun 05 04:07:04 PM PDT 24
Peak memory 204360 kb
Host smart-ca0d77af-b2a0-498a-81ac-54b480685181
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3439851448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3439851448
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.797001343
Short name T677
Test name
Test status
Simulation time 1945806108 ps
CPU time 9.02 seconds
Started Jun 05 04:06:46 PM PDT 24
Finished Jun 05 04:06:55 PM PDT 24
Peak memory 203200 kb
Host smart-72b7f543-e849-45e9-bdc2-f53b213adb40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=797001343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.797001343
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2050044093
Short name T766
Test name
Test status
Simulation time 5176758741 ps
CPU time 52.09 seconds
Started Jun 05 04:06:42 PM PDT 24
Finished Jun 05 04:07:35 PM PDT 24
Peak memory 211404 kb
Host smart-aa0b2472-e418-46a6-a0d3-d436f1a17143
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2050044093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2050044093
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1776215877
Short name T424
Test name
Test status
Simulation time 66802812 ps
CPU time 6.2 seconds
Started Jun 05 04:06:44 PM PDT 24
Finished Jun 05 04:06:51 PM PDT 24
Peak memory 204312 kb
Host smart-d2e09bb7-73cd-45ea-a760-326e62917c58
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776215877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1776215877
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1163370304
Short name T468
Test name
Test status
Simulation time 1212497310 ps
CPU time 27.97 seconds
Started Jun 05 04:06:44 PM PDT 24
Finished Jun 05 04:07:13 PM PDT 24
Peak memory 203728 kb
Host smart-f3f35698-8076-40f6-bf3f-a8d00694859c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1163370304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1163370304
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.387452827
Short name T879
Test name
Test status
Simulation time 128103996 ps
CPU time 3.2 seconds
Started Jun 05 04:06:45 PM PDT 24
Finished Jun 05 04:06:49 PM PDT 24
Peak memory 203172 kb
Host smart-f77703e4-86cd-4fd4-9f29-8877f555d4f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=387452827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.387452827
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2005059807
Short name T814
Test name
Test status
Simulation time 28168373575 ps
CPU time 43.79 seconds
Started Jun 05 04:06:43 PM PDT 24
Finished Jun 05 04:07:29 PM PDT 24
Peak memory 203248 kb
Host smart-1392bc78-53b7-4f03-96fd-eac5c53f91c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005059807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2005059807
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3163170326
Short name T495
Test name
Test status
Simulation time 5449039963 ps
CPU time 30.98 seconds
Started Jun 05 04:06:41 PM PDT 24
Finished Jun 05 04:07:13 PM PDT 24
Peak memory 203248 kb
Host smart-5a293c72-c5aa-492f-8641-20b2e2a92999
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3163170326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3163170326
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.573351430
Short name T670
Test name
Test status
Simulation time 76826805 ps
CPU time 2.45 seconds
Started Jun 05 04:06:41 PM PDT 24
Finished Jun 05 04:06:45 PM PDT 24
Peak memory 203184 kb
Host smart-67a84be5-a7a4-4b31-b505-1911cc802e67
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573351430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.573351430
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3575195427
Short name T790
Test name
Test status
Simulation time 2645146347 ps
CPU time 25.04 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 211396 kb
Host smart-4dc1e399-3564-4ef8-8207-398cdf666c2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3575195427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3575195427
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3810885639
Short name T253
Test name
Test status
Simulation time 3101338120 ps
CPU time 96.32 seconds
Started Jun 05 04:06:53 PM PDT 24
Finished Jun 05 04:08:29 PM PDT 24
Peak memory 205804 kb
Host smart-9f217c40-1f58-4106-a6db-dde3b598476d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3810885639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3810885639
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2154504969
Short name T99
Test name
Test status
Simulation time 2396091259 ps
CPU time 112.86 seconds
Started Jun 05 04:06:53 PM PDT 24
Finished Jun 05 04:08:47 PM PDT 24
Peak memory 209344 kb
Host smart-8468d62c-7431-49e6-ad20-019636170db3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2154504969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.2154504969
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.248654095
Short name T321
Test name
Test status
Simulation time 723422630 ps
CPU time 155.4 seconds
Started Jun 05 04:06:52 PM PDT 24
Finished Jun 05 04:09:28 PM PDT 24
Peak memory 211232 kb
Host smart-d324fb17-fbfa-479f-be9a-ec6bb658eae1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=248654095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res
et_error.248654095
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.136969828
Short name T855
Test name
Test status
Simulation time 907755262 ps
CPU time 27.16 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:07:17 PM PDT 24
Peak memory 211372 kb
Host smart-c6cbf11b-4649-45ca-96bd-12b32269b10a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=136969828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.136969828
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.687061131
Short name T853
Test name
Test status
Simulation time 119030395 ps
CPU time 16.62 seconds
Started Jun 05 04:06:47 PM PDT 24
Finished Jun 05 04:07:04 PM PDT 24
Peak memory 204328 kb
Host smart-c25a651e-359b-4567-9a7e-26fa5f5d0f94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=687061131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.687061131
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3399262107
Short name T405
Test name
Test status
Simulation time 6872707001 ps
CPU time 45.03 seconds
Started Jun 05 04:06:51 PM PDT 24
Finished Jun 05 04:07:37 PM PDT 24
Peak memory 211420 kb
Host smart-98a32c32-74da-404a-a83c-585251dca05f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3399262107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.3399262107
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4012359468
Short name T842
Test name
Test status
Simulation time 448339487 ps
CPU time 14.89 seconds
Started Jun 05 04:06:50 PM PDT 24
Finished Jun 05 04:07:06 PM PDT 24
Peak memory 203124 kb
Host smart-ad2761ce-4d9d-437c-a9bb-6ffb08695648
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4012359468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.4012359468
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.2865472030
Short name T12
Test name
Test status
Simulation time 367764129 ps
CPU time 20.88 seconds
Started Jun 05 04:06:50 PM PDT 24
Finished Jun 05 04:07:11 PM PDT 24
Peak memory 203220 kb
Host smart-99d05adb-42c3-4bd0-989b-c21df7b8efec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2865472030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2865472030
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.2871236732
Short name T597
Test name
Test status
Simulation time 137813097 ps
CPU time 6.14 seconds
Started Jun 05 04:06:51 PM PDT 24
Finished Jun 05 04:06:58 PM PDT 24
Peak memory 203144 kb
Host smart-2a82e0e6-5f9c-4e48-8a2e-6cbed3eae5df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2871236732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2871236732
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3716677227
Short name T174
Test name
Test status
Simulation time 90027887871 ps
CPU time 284.71 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:11:34 PM PDT 24
Peak memory 205356 kb
Host smart-7c531f98-f532-4c88-a479-4f6e33bf6e30
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716677227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3716677227
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1525630240
Short name T454
Test name
Test status
Simulation time 49321272049 ps
CPU time 156.1 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:09:26 PM PDT 24
Peak memory 204716 kb
Host smart-e314e75a-c073-49b0-b675-b589a2114791
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1525630240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1525630240
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2424842910
Short name T213
Test name
Test status
Simulation time 190891972 ps
CPU time 21.85 seconds
Started Jun 05 04:06:52 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 204468 kb
Host smart-110d4417-a3a7-43ad-b9dc-d45717d42f82
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424842910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2424842910
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.3567398792
Short name T812
Test name
Test status
Simulation time 960777978 ps
CPU time 18.99 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:07:09 PM PDT 24
Peak memory 203104 kb
Host smart-1478c057-1d83-4e12-ac83-0014be266427
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3567398792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3567398792
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.2403190988
Short name T729
Test name
Test status
Simulation time 208011222 ps
CPU time 3.34 seconds
Started Jun 05 04:06:50 PM PDT 24
Finished Jun 05 04:06:54 PM PDT 24
Peak memory 203068 kb
Host smart-c4f3ea26-f942-4758-a9a2-2101590cdf9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2403190988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2403190988
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1979084395
Short name T92
Test name
Test status
Simulation time 23795424125 ps
CPU time 42.16 seconds
Started Jun 05 04:06:50 PM PDT 24
Finished Jun 05 04:07:33 PM PDT 24
Peak memory 203252 kb
Host smart-387cd6b1-a530-4767-b6fb-da8c6b87021c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979084395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1979084395
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.869583427
Short name T747
Test name
Test status
Simulation time 4391501678 ps
CPU time 25.31 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 203252 kb
Host smart-cdebf15e-ff7c-475c-8661-f4b574a5b409
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=869583427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.869583427
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3074720399
Short name T408
Test name
Test status
Simulation time 52479093 ps
CPU time 2.14 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:06:51 PM PDT 24
Peak memory 203128 kb
Host smart-1f82544b-9e66-446e-9158-e6560af6db0f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074720399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3074720399
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2500829816
Short name T177
Test name
Test status
Simulation time 1051056267 ps
CPU time 118.22 seconds
Started Jun 05 04:06:51 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 207156 kb
Host smart-620553da-72dd-4c6b-814a-192973961eb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500829816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2500829816
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1496366992
Short name T622
Test name
Test status
Simulation time 688178964 ps
CPU time 67.42 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:07:57 PM PDT 24
Peak memory 205932 kb
Host smart-d6ff5be7-687d-4df5-a70e-aa0699f15562
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1496366992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1496366992
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3393061188
Short name T453
Test name
Test status
Simulation time 705498082 ps
CPU time 276.74 seconds
Started Jun 05 04:06:49 PM PDT 24
Finished Jun 05 04:11:26 PM PDT 24
Peak memory 208368 kb
Host smart-e1c1f04b-ea41-49c7-94a8-7b35026cc327
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3393061188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.3393061188
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1207910449
Short name T200
Test name
Test status
Simulation time 211187632 ps
CPU time 77.05 seconds
Started Jun 05 04:07:02 PM PDT 24
Finished Jun 05 04:08:19 PM PDT 24
Peak memory 208596 kb
Host smart-22d79484-7abf-4a03-885f-c2f6ca2278d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1207910449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1207910449
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2552900183
Short name T582
Test name
Test status
Simulation time 1323506204 ps
CPU time 24.84 seconds
Started Jun 05 04:06:50 PM PDT 24
Finished Jun 05 04:07:16 PM PDT 24
Peak memory 211356 kb
Host smart-146471c3-895a-42dd-8e0a-dcec6e5633b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2552900183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2552900183
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1419480904
Short name T128
Test name
Test status
Simulation time 7013372271 ps
CPU time 54.62 seconds
Started Jun 05 04:06:57 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 211428 kb
Host smart-e65a04fb-ae9a-4bc4-8cf1-654e3fc6f40c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1419480904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1419480904
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.39033190
Short name T872
Test name
Test status
Simulation time 16805677631 ps
CPU time 122.56 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:09:03 PM PDT 24
Peak memory 211460 kb
Host smart-8588a8cb-e78d-4e96-9373-46d4041e12bd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=39033190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow
_rsp.39033190
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1269284665
Short name T489
Test name
Test status
Simulation time 2161999010 ps
CPU time 22.81 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:07:22 PM PDT 24
Peak memory 203244 kb
Host smart-0fc8eefd-fa18-4eed-9175-94df69eebad7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1269284665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1269284665
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3574646136
Short name T804
Test name
Test status
Simulation time 530222055 ps
CPU time 10.16 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:07:10 PM PDT 24
Peak memory 203120 kb
Host smart-14942aa3-ac29-4bfe-ad6f-f0211da22783
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3574646136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3574646136
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.3644138942
Short name T49
Test name
Test status
Simulation time 1230638710 ps
CPU time 19.5 seconds
Started Jun 05 04:06:57 PM PDT 24
Finished Jun 05 04:07:17 PM PDT 24
Peak memory 204444 kb
Host smart-c289ccd6-b323-45c4-9647-96401a849e8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3644138942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3644138942
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2392475703
Short name T861
Test name
Test status
Simulation time 57318633444 ps
CPU time 160.57 seconds
Started Jun 05 04:06:58 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 204756 kb
Host smart-d2f2eba3-eed3-4292-9204-687be07497a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392475703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2392475703
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1665000336
Short name T862
Test name
Test status
Simulation time 22863491782 ps
CPU time 149.45 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:09:29 PM PDT 24
Peak memory 204720 kb
Host smart-ac3b451a-a25f-4b13-bef5-04de28f65ebd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1665000336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1665000336
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1609744646
Short name T499
Test name
Test status
Simulation time 58654366 ps
CPU time 4.96 seconds
Started Jun 05 04:06:58 PM PDT 24
Finished Jun 05 04:07:04 PM PDT 24
Peak memory 203268 kb
Host smart-af6e5dff-7572-49ec-be44-d866ea8b2f9f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609744646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1609744646
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.1095859186
Short name T875
Test name
Test status
Simulation time 790196874 ps
CPU time 10.46 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:07:10 PM PDT 24
Peak memory 203208 kb
Host smart-3ed467d8-aa22-4c0b-84ba-8ace575d007b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1095859186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1095859186
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.2000785378
Short name T335
Test name
Test status
Simulation time 441358200 ps
CPU time 3.59 seconds
Started Jun 05 04:06:58 PM PDT 24
Finished Jun 05 04:07:02 PM PDT 24
Peak memory 203180 kb
Host smart-dfb6435b-469c-4e64-8558-fc73fdf6a3b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2000785378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2000785378
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1815423307
Short name T113
Test name
Test status
Simulation time 13914570707 ps
CPU time 39.17 seconds
Started Jun 05 04:07:00 PM PDT 24
Finished Jun 05 04:07:40 PM PDT 24
Peak memory 203008 kb
Host smart-3d933327-d670-4819-9b09-9b545cf6415a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815423307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1815423307
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.739409556
Short name T880
Test name
Test status
Simulation time 8678265713 ps
CPU time 27.93 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:07:28 PM PDT 24
Peak memory 203204 kb
Host smart-e4f5ec5c-2019-4985-86d6-65c15e7a2b42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=739409556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.739409556
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3639024032
Short name T263
Test name
Test status
Simulation time 32449652 ps
CPU time 2.24 seconds
Started Jun 05 04:06:57 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 203164 kb
Host smart-d7eed8da-58b5-4eee-a216-19d41f3390cf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639024032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3639024032
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.11854433
Short name T269
Test name
Test status
Simulation time 10279523824 ps
CPU time 105.19 seconds
Started Jun 05 04:07:00 PM PDT 24
Finished Jun 05 04:08:46 PM PDT 24
Peak memory 207732 kb
Host smart-50817cf1-0bcc-47ef-b36f-7ac7e68a04b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11854433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.11854433
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2946816685
Short name T214
Test name
Test status
Simulation time 610563185 ps
CPU time 256.69 seconds
Started Jun 05 04:07:00 PM PDT 24
Finished Jun 05 04:11:17 PM PDT 24
Peak memory 209724 kb
Host smart-8b4b9813-ce7c-45a8-aec5-4ea7991fc0a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2946816685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.2946816685
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3935384967
Short name T757
Test name
Test status
Simulation time 10248543155 ps
CPU time 369.26 seconds
Started Jun 05 04:06:58 PM PDT 24
Finished Jun 05 04:13:08 PM PDT 24
Peak memory 223528 kb
Host smart-06340bd3-3639-460f-89e2-a113663dabe2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3935384967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.3935384967
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.4195022766
Short name T785
Test name
Test status
Simulation time 26820532 ps
CPU time 1.98 seconds
Started Jun 05 04:06:58 PM PDT 24
Finished Jun 05 04:07:01 PM PDT 24
Peak memory 203188 kb
Host smart-cabc8eca-2223-4f58-8168-34cc2a02988a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4195022766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4195022766
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.683554510
Short name T358
Test name
Test status
Simulation time 233493699 ps
CPU time 21.69 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:33 PM PDT 24
Peak memory 211368 kb
Host smart-33b0a986-ff67-4005-9aec-31c561190db3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=683554510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.683554510
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.467275218
Short name T585
Test name
Test status
Simulation time 268173021430 ps
CPU time 774.73 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:20:04 PM PDT 24
Peak memory 207504 kb
Host smart-a50d2b68-4215-435b-b543-11ea643e76f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=467275218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo
w_rsp.467275218
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3125678575
Short name T416
Test name
Test status
Simulation time 468246003 ps
CPU time 13.78 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:07:24 PM PDT 24
Peak memory 203180 kb
Host smart-cbfc26a1-650d-423e-9e34-92a6d8427791
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3125678575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3125678575
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2860432866
Short name T6
Test name
Test status
Simulation time 76798379 ps
CPU time 8.72 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:20 PM PDT 24
Peak memory 203200 kb
Host smart-2e011d9e-f86c-46b9-bc07-c639bb162ac1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2860432866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2860432866
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.1359794904
Short name T117
Test name
Test status
Simulation time 231251658 ps
CPU time 11.66 seconds
Started Jun 05 04:07:03 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 211356 kb
Host smart-9c2498e7-9252-4d8f-a6a1-b380223ba302
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1359794904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1359794904
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.4122726370
Short name T711
Test name
Test status
Simulation time 87451351306 ps
CPU time 254.94 seconds
Started Jun 05 04:07:00 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 211448 kb
Host smart-c4b392ef-1b65-45c1-9063-fdf3b62118c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122726370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.4122726370
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.4103366236
Short name T87
Test name
Test status
Simulation time 4882400412 ps
CPU time 41.65 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 204448 kb
Host smart-8515d6a1-ab40-4712-acbd-6a5516753a36
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4103366236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.4103366236
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2799306312
Short name T301
Test name
Test status
Simulation time 44131859 ps
CPU time 5.12 seconds
Started Jun 05 04:06:58 PM PDT 24
Finished Jun 05 04:07:04 PM PDT 24
Peak memory 204284 kb
Host smart-da66d528-4720-4edb-b5bf-aed23866f734
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799306312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2799306312
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.2490438936
Short name T744
Test name
Test status
Simulation time 861379723 ps
CPU time 18.08 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:29 PM PDT 24
Peak memory 203200 kb
Host smart-6964fd27-a353-4557-9ac2-36c6f068f83d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2490438936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2490438936
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.1489217042
Short name T892
Test name
Test status
Simulation time 140438219 ps
CPU time 3.84 seconds
Started Jun 05 04:06:58 PM PDT 24
Finished Jun 05 04:07:03 PM PDT 24
Peak memory 203184 kb
Host smart-397af705-9d4c-4333-bdc4-4fb21fbf0ee3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1489217042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1489217042
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1640017987
Short name T894
Test name
Test status
Simulation time 5954401062 ps
CPU time 30.09 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:07:30 PM PDT 24
Peak memory 203252 kb
Host smart-c7ca32ea-900b-48c5-a13b-d014d40a9217
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640017987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1640017987
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2642444825
Short name T543
Test name
Test status
Simulation time 4453607206 ps
CPU time 26.77 seconds
Started Jun 05 04:06:59 PM PDT 24
Finished Jun 05 04:07:26 PM PDT 24
Peak memory 203196 kb
Host smart-2f78f0f8-0f30-4513-ad6b-f06e0ec06aec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2642444825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2642444825
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2415969793
Short name T856
Test name
Test status
Simulation time 44249014 ps
CPU time 2.29 seconds
Started Jun 05 04:07:01 PM PDT 24
Finished Jun 05 04:07:04 PM PDT 24
Peak memory 203044 kb
Host smart-d85ccca6-453a-4661-b4f1-75b475719330
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415969793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2415969793
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3001074611
Short name T619
Test name
Test status
Simulation time 40148442 ps
CPU time 3.9 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:15 PM PDT 24
Peak memory 204408 kb
Host smart-f89f9bb8-7be7-4f6f-8fdf-0eb94902dbb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3001074611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3001074611
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2688093990
Short name T14
Test name
Test status
Simulation time 713094037 ps
CPU time 68.67 seconds
Started Jun 05 04:07:08 PM PDT 24
Finished Jun 05 04:08:17 PM PDT 24
Peak memory 206160 kb
Host smart-6da8fd1e-ba7f-4d90-a9a0-a98ea830c37a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2688093990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2688093990
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2756508482
Short name T259
Test name
Test status
Simulation time 301590459 ps
CPU time 134.69 seconds
Started Jun 05 04:07:08 PM PDT 24
Finished Jun 05 04:09:23 PM PDT 24
Peak memory 208692 kb
Host smart-a5fb39c5-1a98-4260-8961-5949f68c126a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2756508482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.2756508482
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.99335436
Short name T425
Test name
Test status
Simulation time 1700283154 ps
CPU time 342.24 seconds
Started Jun 05 04:07:07 PM PDT 24
Finished Jun 05 04:12:50 PM PDT 24
Peak memory 211636 kb
Host smart-5906aef6-cd3e-4c87-b7e9-110099dc6812
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99335436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rese
t_error.99335436
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1250380740
Short name T900
Test name
Test status
Simulation time 1271334252 ps
CPU time 29.42 seconds
Started Jun 05 04:07:12 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 204808 kb
Host smart-5ec20e63-f615-4774-857f-1a4300163763
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1250380740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1250380740
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3741568311
Short name T647
Test name
Test status
Simulation time 2456464920 ps
CPU time 15.8 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:07:25 PM PDT 24
Peak memory 204560 kb
Host smart-7488534a-4c96-4558-b0d2-718f4ae552d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3741568311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3741568311
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.698540316
Short name T148
Test name
Test status
Simulation time 18021114483 ps
CPU time 127.21 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:09:17 PM PDT 24
Peak memory 204640 kb
Host smart-ba53d50e-6b3f-4b90-9b17-b46dec30f8c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=698540316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo
w_rsp.698540316
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2541615405
Short name T840
Test name
Test status
Simulation time 2262216650 ps
CPU time 25.49 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:36 PM PDT 24
Peak memory 203576 kb
Host smart-74780805-cbd5-4d5a-b48a-824979443ac0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2541615405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2541615405
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.4051879717
Short name T145
Test name
Test status
Simulation time 532972146 ps
CPU time 17.3 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:28 PM PDT 24
Peak memory 203180 kb
Host smart-0dbdffb7-ab58-4942-9013-edb06ba482c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4051879717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.4051879717
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.2311237691
Short name T169
Test name
Test status
Simulation time 159075947 ps
CPU time 19.77 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:07:30 PM PDT 24
Peak memory 204300 kb
Host smart-7a8f699d-9ea9-4ad3-895c-ec86a23b523b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2311237691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2311237691
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.80937809
Short name T111
Test name
Test status
Simulation time 76078891883 ps
CPU time 262.08 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 211448 kb
Host smart-a0da15e6-0410-4a84-b396-eb6efa930363
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80937809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.80937809
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1060605070
Short name T518
Test name
Test status
Simulation time 7581217954 ps
CPU time 26.78 seconds
Started Jun 05 04:07:11 PM PDT 24
Finished Jun 05 04:07:39 PM PDT 24
Peak memory 204308 kb
Host smart-4f9415aa-c774-4a93-8126-21c58d8a8835
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1060605070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1060605070
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.399132621
Short name T244
Test name
Test status
Simulation time 250134766 ps
CPU time 24.62 seconds
Started Jun 05 04:07:11 PM PDT 24
Finished Jun 05 04:07:36 PM PDT 24
Peak memory 211388 kb
Host smart-d0943764-15f4-4da7-bc9b-ad746d97a4f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399132621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.399132621
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.3542025112
Short name T114
Test name
Test status
Simulation time 1338682232 ps
CPU time 36.28 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:07:46 PM PDT 24
Peak memory 203260 kb
Host smart-73b7a91a-70fa-4ad9-9f94-0969772c7f5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3542025112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3542025112
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.1292865334
Short name T623
Test name
Test status
Simulation time 179220214 ps
CPU time 3.95 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:07:13 PM PDT 24
Peak memory 203172 kb
Host smart-694d18d2-db09-4982-a33d-8677c9865505
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1292865334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1292865334
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3479823730
Short name T519
Test name
Test status
Simulation time 6561162088 ps
CPU time 34.33 seconds
Started Jun 05 04:07:08 PM PDT 24
Finished Jun 05 04:07:43 PM PDT 24
Peak memory 203252 kb
Host smart-d4a0e868-34e3-463b-a20b-7e4e7e959436
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479823730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3479823730
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3175218668
Short name T45
Test name
Test status
Simulation time 3914530033 ps
CPU time 28.05 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:39 PM PDT 24
Peak memory 203260 kb
Host smart-4ba5ccd5-6a61-4c32-926b-d9d7cb23df26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3175218668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3175218668
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2238312924
Short name T433
Test name
Test status
Simulation time 28125811 ps
CPU time 2.16 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:07:12 PM PDT 24
Peak memory 203044 kb
Host smart-728c8044-20e5-4010-83eb-d41c0b0684dc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238312924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2238312924
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.564125539
Short name T316
Test name
Test status
Simulation time 263367382 ps
CPU time 23.06 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:34 PM PDT 24
Peak memory 205384 kb
Host smart-fe36f008-c0b5-4268-a834-a3bf406d66ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=564125539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.564125539
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.4165143706
Short name T427
Test name
Test status
Simulation time 245044803 ps
CPU time 27.89 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:39 PM PDT 24
Peak memory 204208 kb
Host smart-d3145a88-6f82-41b5-8fc7-9f50216101bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4165143706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.4165143706
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3382009338
Short name T605
Test name
Test status
Simulation time 554483012 ps
CPU time 91.05 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:08:41 PM PDT 24
Peak memory 208548 kb
Host smart-ae0da8a1-7e10-4088-a872-ffc3a8d810fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3382009338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.3382009338
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.732527512
Short name T90
Test name
Test status
Simulation time 1716215106 ps
CPU time 30.8 seconds
Started Jun 05 04:07:10 PM PDT 24
Finished Jun 05 04:07:42 PM PDT 24
Peak memory 204596 kb
Host smart-72749b93-d35c-4397-bd9d-04d526eb1072
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=732527512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.732527512
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.864592469
Short name T854
Test name
Test status
Simulation time 1014217235 ps
CPU time 37.16 seconds
Started Jun 05 04:07:19 PM PDT 24
Finished Jun 05 04:07:57 PM PDT 24
Peak memory 211272 kb
Host smart-d1f52e46-3fd5-4572-8a74-702d76752890
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=864592469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.864592469
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2622867621
Short name T863
Test name
Test status
Simulation time 58266638347 ps
CPU time 494.64 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:15:36 PM PDT 24
Peak memory 205808 kb
Host smart-add17506-2dc4-4411-950e-7edb8d9873ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2622867621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.2622867621
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2891566166
Short name T628
Test name
Test status
Simulation time 1154373738 ps
CPU time 23.51 seconds
Started Jun 05 04:07:20 PM PDT 24
Finished Jun 05 04:07:44 PM PDT 24
Peak memory 203068 kb
Host smart-8513c1ab-564d-44ee-9fc9-923b961b1722
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2891566166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2891566166
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.1135160377
Short name T592
Test name
Test status
Simulation time 464890158 ps
CPU time 13.62 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:07:36 PM PDT 24
Peak memory 203196 kb
Host smart-0587e0ed-7c88-41d0-86da-634f6358ce77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1135160377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1135160377
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3161233614
Short name T264
Test name
Test status
Simulation time 100121841 ps
CPU time 10.21 seconds
Started Jun 05 04:07:20 PM PDT 24
Finished Jun 05 04:07:31 PM PDT 24
Peak memory 204308 kb
Host smart-21261e9f-6a32-4efd-b34c-6f9492943708
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3161233614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3161233614
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3174342073
Short name T896
Test name
Test status
Simulation time 37235778736 ps
CPU time 214.81 seconds
Started Jun 05 04:07:19 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 211444 kb
Host smart-5ae5f319-d552-457e-ac99-10403acdb4c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174342073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3174342073
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.758411817
Short name T342
Test name
Test status
Simulation time 74728744581 ps
CPU time 245.01 seconds
Started Jun 05 04:07:19 PM PDT 24
Finished Jun 05 04:11:25 PM PDT 24
Peak memory 211360 kb
Host smart-fd3d8f79-796b-4666-bf2a-385c1be48e92
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=758411817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.758411817
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1468094950
Short name T689
Test name
Test status
Simulation time 108628090 ps
CPU time 16.05 seconds
Started Jun 05 04:07:19 PM PDT 24
Finished Jun 05 04:07:35 PM PDT 24
Peak memory 211392 kb
Host smart-29584426-e3f9-4348-95f7-f8c83dbe3895
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468094950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1468094950
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.186777885
Short name T19
Test name
Test status
Simulation time 1291219958 ps
CPU time 23.02 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:07:45 PM PDT 24
Peak memory 203196 kb
Host smart-87cba63b-7ff3-435e-bb1e-c82bab4c6feb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=186777885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.186777885
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.3697593480
Short name T548
Test name
Test status
Simulation time 126784490 ps
CPU time 3.29 seconds
Started Jun 05 04:07:12 PM PDT 24
Finished Jun 05 04:07:16 PM PDT 24
Peak memory 203124 kb
Host smart-e542e6d7-0832-4a6e-a5a4-d7590f28b2d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3697593480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3697593480
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3644896633
Short name T1
Test name
Test status
Simulation time 15813638132 ps
CPU time 39.74 seconds
Started Jun 05 04:07:09 PM PDT 24
Finished Jun 05 04:07:49 PM PDT 24
Peak memory 203252 kb
Host smart-20385b94-aedf-4150-826e-2de181dea2c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644896633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3644896633
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3503813763
Short name T652
Test name
Test status
Simulation time 4120019304 ps
CPU time 22.97 seconds
Started Jun 05 04:07:20 PM PDT 24
Finished Jun 05 04:07:43 PM PDT 24
Peak memory 203216 kb
Host smart-d8293855-bbb2-4527-9e8e-aec4677b12c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3503813763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3503813763
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.198768607
Short name T604
Test name
Test status
Simulation time 48591788 ps
CPU time 2.36 seconds
Started Jun 05 04:07:08 PM PDT 24
Finished Jun 05 04:07:11 PM PDT 24
Peak memory 203196 kb
Host smart-8bc72df1-bbf6-4136-aa3d-302998ea6182
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198768607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.198768607
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.227211966
Short name T70
Test name
Test status
Simulation time 8459645645 ps
CPU time 259.19 seconds
Started Jun 05 04:07:20 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 207240 kb
Host smart-03f7c039-e709-4873-b6f2-81afa66ba862
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=227211966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.227211966
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3747985739
Short name T743
Test name
Test status
Simulation time 484831863 ps
CPU time 29.45 seconds
Started Jun 05 04:07:22 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 203868 kb
Host smart-96f00d48-88a8-496a-a749-187f66b8f006
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3747985739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3747985739
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1055996856
Short name T478
Test name
Test status
Simulation time 10205699048 ps
CPU time 145.99 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:09:48 PM PDT 24
Peak memory 206456 kb
Host smart-557078ec-6b81-4c99-9a94-9efe7ddf638b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1055996856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.1055996856
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2196558850
Short name T869
Test name
Test status
Simulation time 39432856 ps
CPU time 5.54 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:07:27 PM PDT 24
Peak memory 204288 kb
Host smart-b065e2a7-5edc-4f23-8ce7-062a91055755
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2196558850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.2196558850
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1891665701
Short name T770
Test name
Test status
Simulation time 651612168 ps
CPU time 26.89 seconds
Started Jun 05 04:07:27 PM PDT 24
Finished Jun 05 04:07:55 PM PDT 24
Peak memory 211312 kb
Host smart-0fdd2175-63fe-45b7-bb9e-4d648be4a985
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1891665701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1891665701
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1252638924
Short name T77
Test name
Test status
Simulation time 492935297 ps
CPU time 4.84 seconds
Started Jun 05 04:07:19 PM PDT 24
Finished Jun 05 04:07:24 PM PDT 24
Peak memory 203156 kb
Host smart-3733d083-2004-428a-a0db-ea830801a3cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1252638924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1252638924
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.736149255
Short name T751
Test name
Test status
Simulation time 14282433904 ps
CPU time 72.84 seconds
Started Jun 05 04:07:22 PM PDT 24
Finished Jun 05 04:08:36 PM PDT 24
Peak memory 211424 kb
Host smart-4d375ea9-ff27-4c77-920d-9374708fb02e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=736149255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo
w_rsp.736149255
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3150857352
Short name T161
Test name
Test status
Simulation time 139405732 ps
CPU time 6.9 seconds
Started Jun 05 04:07:30 PM PDT 24
Finished Jun 05 04:07:38 PM PDT 24
Peak memory 203196 kb
Host smart-954dd1e4-cdd8-4925-94e8-576fdee59a07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3150857352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3150857352
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.1012552878
Short name T888
Test name
Test status
Simulation time 93104756 ps
CPU time 9.29 seconds
Started Jun 05 04:07:30 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 203204 kb
Host smart-61b437bd-6a52-42b4-9c59-23a31503738a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1012552878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1012552878
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.3108886695
Short name T223
Test name
Test status
Simulation time 589705187 ps
CPU time 23.35 seconds
Started Jun 05 04:07:20 PM PDT 24
Finished Jun 05 04:07:44 PM PDT 24
Peak memory 211620 kb
Host smart-b1a1b842-b99e-42a2-a5ac-378f49057f16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3108886695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3108886695
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2618041604
Short name T378
Test name
Test status
Simulation time 11375417934 ps
CPU time 31.42 seconds
Started Jun 05 04:07:20 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 203264 kb
Host smart-48994539-10b6-4861-87dd-79b35d287912
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618041604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2618041604
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3833868028
Short name T383
Test name
Test status
Simulation time 90053731711 ps
CPU time 209.68 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 204924 kb
Host smart-2c2800e2-d402-4b0b-b502-7b04466567d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3833868028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3833868028
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2701014919
Short name T886
Test name
Test status
Simulation time 528257529 ps
CPU time 19.73 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:07:42 PM PDT 24
Peak memory 204452 kb
Host smart-91cac549-c208-43ee-a31f-f2b12faa8b98
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701014919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2701014919
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.3640355756
Short name T73
Test name
Test status
Simulation time 1302062967 ps
CPU time 8.35 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 203204 kb
Host smart-633618c5-a020-4113-8183-de0fd33c9909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3640355756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3640355756
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.244641565
Short name T164
Test name
Test status
Simulation time 39726074 ps
CPU time 2.59 seconds
Started Jun 05 04:07:24 PM PDT 24
Finished Jun 05 04:07:27 PM PDT 24
Peak memory 203172 kb
Host smart-cd607cec-3c7a-44c6-bf57-8dd0b2120c83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=244641565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.244641565
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3335340366
Short name T413
Test name
Test status
Simulation time 3765450738 ps
CPU time 23.34 seconds
Started Jun 05 04:07:21 PM PDT 24
Finished Jun 05 04:07:45 PM PDT 24
Peak memory 203124 kb
Host smart-889a436b-055f-4dd1-b0f4-713964b0a991
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335340366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3335340366
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.625238017
Short name T630
Test name
Test status
Simulation time 5193646392 ps
CPU time 28.61 seconds
Started Jun 05 04:07:19 PM PDT 24
Finished Jun 05 04:07:49 PM PDT 24
Peak memory 203244 kb
Host smart-de379d0d-0d99-48bd-8769-72324b88357c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=625238017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.625238017
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.4182036967
Short name T817
Test name
Test status
Simulation time 27693541 ps
CPU time 2.56 seconds
Started Jun 05 04:07:20 PM PDT 24
Finished Jun 05 04:07:24 PM PDT 24
Peak memory 203144 kb
Host smart-125e12cf-aed9-482f-9207-3e31735cb5b4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182036967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.4182036967
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3817568424
Short name T220
Test name
Test status
Simulation time 7533365630 ps
CPU time 170.31 seconds
Started Jun 05 04:07:29 PM PDT 24
Finished Jun 05 04:10:20 PM PDT 24
Peak memory 209972 kb
Host smart-bc7fba34-e67a-4f80-bb13-089b69cb3071
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3817568424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3817568424
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1468774033
Short name T745
Test name
Test status
Simulation time 9334050918 ps
CPU time 339.84 seconds
Started Jun 05 04:07:30 PM PDT 24
Finished Jun 05 04:13:11 PM PDT 24
Peak memory 211380 kb
Host smart-7c665b2f-8b78-4eb8-bdd1-b44572d0efda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1468774033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1468774033
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2508545766
Short name T194
Test name
Test status
Simulation time 112471099 ps
CPU time 49.27 seconds
Started Jun 05 04:07:30 PM PDT 24
Finished Jun 05 04:08:20 PM PDT 24
Peak memory 206088 kb
Host smart-ffe30b9b-bc5e-452c-9868-640f0a64a6fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2508545766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.2508545766
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.770767495
Short name T429
Test name
Test status
Simulation time 32083741 ps
CPU time 5.67 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:38 PM PDT 24
Peak memory 203592 kb
Host smart-1b774799-55ce-4179-9962-612c1b1f37fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=770767495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.770767495
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3181312028
Short name T614
Test name
Test status
Simulation time 54748815 ps
CPU time 4.26 seconds
Started Jun 05 04:07:26 PM PDT 24
Finished Jun 05 04:07:31 PM PDT 24
Peak memory 211360 kb
Host smart-e20aa3e2-0bd2-4fe9-8041-c4c45f9a0a2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3181312028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3181312028
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2924925847
Short name T106
Test name
Test status
Simulation time 4289097376 ps
CPU time 54.24 seconds
Started Jun 05 04:04:08 PM PDT 24
Finished Jun 05 04:05:03 PM PDT 24
Peak memory 211428 kb
Host smart-e1cfaa07-a209-4d5d-87a0-14ff39098048
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2924925847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2924925847
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3391720570
Short name T69
Test name
Test status
Simulation time 6121581314 ps
CPU time 57.34 seconds
Started Jun 05 04:04:11 PM PDT 24
Finished Jun 05 04:05:09 PM PDT 24
Peak memory 204008 kb
Host smart-b8ddafc8-0e77-43c7-94d8-96000b39b7ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3391720570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3391720570
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3688485116
Short name T385
Test name
Test status
Simulation time 33217383 ps
CPU time 2.16 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:04:12 PM PDT 24
Peak memory 203180 kb
Host smart-bd1d7301-1e78-4597-9ae8-5d2e62807e3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3688485116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3688485116
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.1829890775
Short name T736
Test name
Test status
Simulation time 966673855 ps
CPU time 29.56 seconds
Started Jun 05 04:04:12 PM PDT 24
Finished Jun 05 04:04:42 PM PDT 24
Peak memory 203068 kb
Host smart-8da29e3e-38ec-459b-9d4c-8b326bf051ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1829890775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1829890775
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2323873194
Short name T10
Test name
Test status
Simulation time 5500265878 ps
CPU time 36.86 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:04:47 PM PDT 24
Peak memory 211324 kb
Host smart-325104dc-78cb-41cb-8559-d11502236def
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2323873194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2323873194
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.557601813
Short name T115
Test name
Test status
Simulation time 58655957239 ps
CPU time 194.38 seconds
Started Jun 05 04:04:07 PM PDT 24
Finished Jun 05 04:07:22 PM PDT 24
Peak memory 204952 kb
Host smart-2db67040-694a-4223-8ff0-e3795daabb0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=557601813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.557601813
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1313860747
Short name T257
Test name
Test status
Simulation time 12849687041 ps
CPU time 112.39 seconds
Started Jun 05 04:04:10 PM PDT 24
Finished Jun 05 04:06:04 PM PDT 24
Peak memory 211400 kb
Host smart-7e663b2f-650e-40b7-a825-3d4b13cf8f56
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1313860747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1313860747
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3513516883
Short name T878
Test name
Test status
Simulation time 62515090 ps
CPU time 9.06 seconds
Started Jun 05 04:04:12 PM PDT 24
Finished Jun 05 04:04:22 PM PDT 24
Peak memory 211380 kb
Host smart-8b57eec0-7b96-4fe5-a625-d1b92276ddad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513516883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3513516883
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.1352151647
Short name T807
Test name
Test status
Simulation time 567347287 ps
CPU time 10.46 seconds
Started Jun 05 04:04:07 PM PDT 24
Finished Jun 05 04:04:18 PM PDT 24
Peak memory 203448 kb
Host smart-f46f9644-db74-4f3b-b244-565a6b55b5c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1352151647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1352151647
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1839330587
Short name T527
Test name
Test status
Simulation time 69453824 ps
CPU time 2.29 seconds
Started Jun 05 04:04:11 PM PDT 24
Finished Jun 05 04:04:14 PM PDT 24
Peak memory 203188 kb
Host smart-abdab142-805e-479c-85b7-aa1ad8a4c647
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1839330587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1839330587
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1778116247
Short name T289
Test name
Test status
Simulation time 7778399737 ps
CPU time 25.19 seconds
Started Jun 05 04:04:11 PM PDT 24
Finished Jun 05 04:04:37 PM PDT 24
Peak memory 203256 kb
Host smart-fa9c05a6-78dc-4975-a81d-d800e5dafa42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778116247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1778116247
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.4161826401
Short name T799
Test name
Test status
Simulation time 3364791772 ps
CPU time 25.47 seconds
Started Jun 05 04:04:07 PM PDT 24
Finished Jun 05 04:04:34 PM PDT 24
Peak memory 203260 kb
Host smart-a6a43a4b-aafe-46f8-afc2-33e891bd915c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4161826401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.4161826401
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.104477105
Short name T152
Test name
Test status
Simulation time 31177403 ps
CPU time 2.19 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:04:12 PM PDT 24
Peak memory 203096 kb
Host smart-f10766a8-77eb-40dd-b918-221a0b87d9db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104477105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.104477105
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.4151731218
Short name T369
Test name
Test status
Simulation time 4778585538 ps
CPU time 168.85 seconds
Started Jun 05 04:04:08 PM PDT 24
Finished Jun 05 04:06:58 PM PDT 24
Peak memory 209880 kb
Host smart-56147a59-1a65-498c-90d5-e968b728be94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151731218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4151731218
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.4227971435
Short name T460
Test name
Test status
Simulation time 1967603365 ps
CPU time 58.94 seconds
Started Jun 05 04:04:11 PM PDT 24
Finished Jun 05 04:05:11 PM PDT 24
Peak memory 205272 kb
Host smart-b498dab1-2f20-46d1-a721-c451d0f3a11d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4227971435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4227971435
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2518767397
Short name T806
Test name
Test status
Simulation time 2973242172 ps
CPU time 198.62 seconds
Started Jun 05 04:04:11 PM PDT 24
Finished Jun 05 04:07:30 PM PDT 24
Peak memory 209280 kb
Host smart-76fc1411-1b03-4b97-976c-983e34956dbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2518767397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.2518767397
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3752954731
Short name T512
Test name
Test status
Simulation time 144247856 ps
CPU time 17.4 seconds
Started Jun 05 04:04:10 PM PDT 24
Finished Jun 05 04:04:28 PM PDT 24
Peak memory 204992 kb
Host smart-d763a549-5752-4d48-983c-e3a9d64e1744
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3752954731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.3752954731
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1658603560
Short name T472
Test name
Test status
Simulation time 24125085 ps
CPU time 2.55 seconds
Started Jun 05 04:04:10 PM PDT 24
Finished Jun 05 04:04:13 PM PDT 24
Peak memory 204220 kb
Host smart-b82045a5-146d-48a2-8936-46a7cb21a729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658603560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1658603560
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1360146603
Short name T838
Test name
Test status
Simulation time 190498733 ps
CPU time 11.96 seconds
Started Jun 05 04:07:30 PM PDT 24
Finished Jun 05 04:07:43 PM PDT 24
Peak memory 204300 kb
Host smart-3bbc6e99-269a-492b-9cbb-a79c1e60b76c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1360146603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1360146603
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1124192864
Short name T579
Test name
Test status
Simulation time 53724319236 ps
CPU time 218.57 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 211416 kb
Host smart-40a764ea-adb0-4f05-bd5c-1acbd78da301
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1124192864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.1124192864
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1712929549
Short name T462
Test name
Test status
Simulation time 682304325 ps
CPU time 4.32 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:36 PM PDT 24
Peak memory 203176 kb
Host smart-a97d9d58-0424-4533-b3d0-9aa8635cbbc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1712929549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1712929549
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2452994743
Short name T16
Test name
Test status
Simulation time 1590131822 ps
CPU time 38.78 seconds
Started Jun 05 04:07:28 PM PDT 24
Finished Jun 05 04:08:08 PM PDT 24
Peak memory 203312 kb
Host smart-705a5f2a-66a4-46d9-9fd2-78cc2c461be1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2452994743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2452994743
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.385029607
Short name T639
Test name
Test status
Simulation time 459819170 ps
CPU time 9.01 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 211284 kb
Host smart-ed9e0e46-1d7b-4751-a508-3c63dee81b95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=385029607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.385029607
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.529630957
Short name T226
Test name
Test status
Simulation time 26096311482 ps
CPU time 159.63 seconds
Started Jun 05 04:07:30 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 204484 kb
Host smart-aa40c1f9-806b-4163-92be-03ef2000b061
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=529630957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.529630957
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3811326209
Short name T150
Test name
Test status
Simulation time 34334272992 ps
CPU time 245.4 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 205016 kb
Host smart-8f6eebe3-28d4-4866-8e89-225d80f6e640
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3811326209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3811326209
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1046462865
Short name T360
Test name
Test status
Simulation time 25850515 ps
CPU time 2.06 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:34 PM PDT 24
Peak memory 203068 kb
Host smart-f73d0dd7-76a3-4e18-a3ef-a1871e39ddf0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046462865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1046462865
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.1741504170
Short name T406
Test name
Test status
Simulation time 580963353 ps
CPU time 9.66 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:42 PM PDT 24
Peak memory 203888 kb
Host smart-4048025f-c5ab-4869-89a1-40eee9d428b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1741504170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1741504170
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.3218461903
Short name T873
Test name
Test status
Simulation time 35621170 ps
CPU time 2.16 seconds
Started Jun 05 04:07:34 PM PDT 24
Finished Jun 05 04:07:36 PM PDT 24
Peak memory 203188 kb
Host smart-8d46e41f-893a-4096-9f8e-7be6a877b041
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3218461903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3218461903
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1840322738
Short name T285
Test name
Test status
Simulation time 4999246174 ps
CPU time 29.59 seconds
Started Jun 05 04:07:29 PM PDT 24
Finished Jun 05 04:08:00 PM PDT 24
Peak memory 203252 kb
Host smart-bdc04b45-5928-4ecb-b3af-32184c63d7af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840322738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1840322738
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.914481082
Short name T719
Test name
Test status
Simulation time 5591841373 ps
CPU time 31.93 seconds
Started Jun 05 04:07:29 PM PDT 24
Finished Jun 05 04:08:03 PM PDT 24
Peak memory 203160 kb
Host smart-4787b53a-0715-47ad-8e78-37ff17fa22cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=914481082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.914481082
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1765225091
Short name T782
Test name
Test status
Simulation time 24786560 ps
CPU time 2.32 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:35 PM PDT 24
Peak memory 203152 kb
Host smart-16274973-1363-4706-9b9a-4729d0ee0423
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765225091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1765225091
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2267396955
Short name T84
Test name
Test status
Simulation time 3125694209 ps
CPU time 64.41 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:08:37 PM PDT 24
Peak memory 207428 kb
Host smart-19af95c0-c9bf-4e6c-950a-5bf3db0e0a4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2267396955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2267396955
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1442949473
Short name T459
Test name
Test status
Simulation time 3329885156 ps
CPU time 104.95 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:09:22 PM PDT 24
Peak memory 207288 kb
Host smart-3c6ef86a-b637-4606-ad1d-70ccc6073555
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1442949473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1442949473
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.781828512
Short name T537
Test name
Test status
Simulation time 234855714 ps
CPU time 56.12 seconds
Started Jun 05 04:07:30 PM PDT 24
Finished Jun 05 04:08:28 PM PDT 24
Peak memory 207312 kb
Host smart-d201c60f-9748-4d01-bba0-9301a6a8f770
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=781828512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand
_reset.781828512
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2224339993
Short name T467
Test name
Test status
Simulation time 175612378 ps
CPU time 38.38 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:08:15 PM PDT 24
Peak memory 205576 kb
Host smart-daa96490-207c-4ce1-ab1d-d4c91007179c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2224339993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.2224339993
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.13717895
Short name T843
Test name
Test status
Simulation time 348376927 ps
CPU time 15.19 seconds
Started Jun 05 04:07:31 PM PDT 24
Finished Jun 05 04:07:47 PM PDT 24
Peak memory 211392 kb
Host smart-bee64dde-631d-4234-9031-6882d03fedfb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13717895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.13717895
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2598058116
Short name T848
Test name
Test status
Simulation time 261786556 ps
CPU time 26.55 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:08:04 PM PDT 24
Peak memory 205076 kb
Host smart-bfc5575b-7c70-4ce4-a077-50dd9568104e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2598058116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2598058116
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2726875467
Short name T438
Test name
Test status
Simulation time 48237151374 ps
CPU time 355.13 seconds
Started Jun 05 04:07:35 PM PDT 24
Finished Jun 05 04:13:31 PM PDT 24
Peak memory 205948 kb
Host smart-d8dc824e-fd16-45f8-b6fa-bfd8a17156ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2726875467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.2726875467
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2228479566
Short name T568
Test name
Test status
Simulation time 1360539159 ps
CPU time 24.79 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:08:02 PM PDT 24
Peak memory 203200 kb
Host smart-9b975798-e250-4006-97d5-355dba4aeaf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2228479566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2228479566
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.1619498038
Short name T430
Test name
Test status
Simulation time 1266124949 ps
CPU time 35.64 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:08:12 PM PDT 24
Peak memory 203076 kb
Host smart-880282c3-d60c-4762-8b95-0436cd725538
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1619498038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1619498038
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.1780230820
Short name T514
Test name
Test status
Simulation time 355463703 ps
CPU time 27.5 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:08:05 PM PDT 24
Peak memory 204292 kb
Host smart-e0042214-159f-40a3-85f2-b59d3949acde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1780230820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1780230820
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1160572446
Short name T595
Test name
Test status
Simulation time 115408610607 ps
CPU time 179.16 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 204504 kb
Host smart-cdb471c0-7a51-4dd9-8823-47b0781a397a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160572446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1160572446
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2514270121
Short name T883
Test name
Test status
Simulation time 2303081385 ps
CPU time 21.93 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:07:58 PM PDT 24
Peak memory 203768 kb
Host smart-3b772da4-80cb-4060-8a73-69713865e42e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2514270121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2514270121
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3583648126
Short name T377
Test name
Test status
Simulation time 56519844 ps
CPU time 5.63 seconds
Started Jun 05 04:07:34 PM PDT 24
Finished Jun 05 04:07:40 PM PDT 24
Peak memory 211252 kb
Host smart-beb551fe-d6b2-406a-a6bc-15776f0e65c7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583648126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3583648126
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.2090809097
Short name T15
Test name
Test status
Simulation time 156985523 ps
CPU time 13.68 seconds
Started Jun 05 04:07:40 PM PDT 24
Finished Jun 05 04:07:54 PM PDT 24
Peak memory 203232 kb
Host smart-fc5c1afc-2d1a-4eea-93b2-075f270b89fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2090809097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2090809097
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.2342888247
Short name T303
Test name
Test status
Simulation time 211413000 ps
CPU time 3.42 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 203172 kb
Host smart-6a633814-9f25-4995-bf8c-cbec5c277dbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2342888247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2342888247
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2423873209
Short name T845
Test name
Test status
Simulation time 3916157145 ps
CPU time 22.63 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:08:00 PM PDT 24
Peak memory 203124 kb
Host smart-e100d736-4c1c-45e3-91c3-6b803a1b4a67
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423873209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2423873209
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2300187836
Short name T380
Test name
Test status
Simulation time 7201459558 ps
CPU time 33.12 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:08:10 PM PDT 24
Peak memory 203260 kb
Host smart-9d1ced03-e460-4ba5-a132-3760d27c0eaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2300187836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2300187836
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.106898168
Short name T443
Test name
Test status
Simulation time 29758013 ps
CPU time 2.65 seconds
Started Jun 05 04:07:39 PM PDT 24
Finished Jun 05 04:07:42 PM PDT 24
Peak memory 203184 kb
Host smart-fe3d356a-b606-4a80-b266-002129700600
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106898168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.106898168
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.189534996
Short name T753
Test name
Test status
Simulation time 9466089973 ps
CPU time 172.76 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:10:31 PM PDT 24
Peak memory 208512 kb
Host smart-6359216e-0c18-43a4-acde-902eaea9e8f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=189534996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.189534996
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1409622639
Short name T621
Test name
Test status
Simulation time 5319944727 ps
CPU time 67.12 seconds
Started Jun 05 04:07:39 PM PDT 24
Finished Jun 05 04:08:47 PM PDT 24
Peak memory 205068 kb
Host smart-3c85b926-c3ab-4ec9-b6b9-6e4e762eed97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1409622639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1409622639
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3142184935
Short name T540
Test name
Test status
Simulation time 409339311 ps
CPU time 166.54 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 207884 kb
Host smart-a4026120-fd56-4f9f-a10c-a37c0f38c574
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3142184935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3142184935
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4199777193
Short name T536
Test name
Test status
Simulation time 3961566015 ps
CPU time 170.79 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:10:29 PM PDT 24
Peak memory 211276 kb
Host smart-ffbe6be7-1344-4737-aa2f-9218c9b611b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4199777193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.4199777193
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3509292973
Short name T60
Test name
Test status
Simulation time 363273807 ps
CPU time 13.96 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 211336 kb
Host smart-b21d462f-22be-4016-89ff-ba0b1fc4fc1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3509292973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3509292973
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.529728551
Short name T516
Test name
Test status
Simulation time 1209870652 ps
CPU time 7.73 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:07:53 PM PDT 24
Peak memory 203056 kb
Host smart-28609102-a677-4da4-a130-2ceb954c2290
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=529728551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.529728551
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.739637626
Short name T841
Test name
Test status
Simulation time 101888700743 ps
CPU time 696.7 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:19:23 PM PDT 24
Peak memory 211448 kb
Host smart-c1d31676-a79b-4998-b7ca-cfdd85c38d90
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=739637626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo
w_rsp.739637626
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1941121989
Short name T624
Test name
Test status
Simulation time 272962197 ps
CPU time 5.03 seconds
Started Jun 05 04:07:43 PM PDT 24
Finished Jun 05 04:07:48 PM PDT 24
Peak memory 203196 kb
Host smart-c87ae93f-5311-4e52-ac1b-566e272b58d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1941121989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1941121989
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.3517221765
Short name T570
Test name
Test status
Simulation time 941490908 ps
CPU time 31.25 seconds
Started Jun 05 04:07:44 PM PDT 24
Finished Jun 05 04:08:16 PM PDT 24
Peak memory 203200 kb
Host smart-368c63fd-fa9f-4a0f-b558-5a700d5c867a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3517221765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3517221765
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2779867199
Short name T388
Test name
Test status
Simulation time 63436932 ps
CPU time 9.96 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:07:47 PM PDT 24
Peak memory 204356 kb
Host smart-51abd8be-31da-4665-a70f-abfd05ee3845
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2779867199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2779867199
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2973072363
Short name T384
Test name
Test status
Simulation time 40831299626 ps
CPU time 199.88 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:10:57 PM PDT 24
Peak memory 211300 kb
Host smart-15fe0111-dbc2-45a9-8da0-183aa20ffa45
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973072363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2973072363
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1236175522
Short name T676
Test name
Test status
Simulation time 26394341164 ps
CPU time 228.97 seconds
Started Jun 05 04:07:39 PM PDT 24
Finished Jun 05 04:11:28 PM PDT 24
Peak memory 204988 kb
Host smart-b3f29120-af31-40c2-8368-57f4db51a13b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1236175522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1236175522
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3681428389
Short name T354
Test name
Test status
Simulation time 178472212 ps
CPU time 27.1 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:08:04 PM PDT 24
Peak memory 211192 kb
Host smart-4b07b48c-4261-46aa-bc61-4c059f638d42
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681428389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3681428389
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.2657340571
Short name T262
Test name
Test status
Simulation time 164080703 ps
CPU time 3.35 seconds
Started Jun 05 04:07:44 PM PDT 24
Finished Jun 05 04:07:48 PM PDT 24
Peak memory 203192 kb
Host smart-fdc07f19-a23d-47e1-b3d7-75973b8a6d53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2657340571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2657340571
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.2900830345
Short name T662
Test name
Test status
Simulation time 266196078 ps
CPU time 3.42 seconds
Started Jun 05 04:07:35 PM PDT 24
Finished Jun 05 04:07:39 PM PDT 24
Peak memory 203140 kb
Host smart-b576e8fa-6fa3-415e-940e-ab0ed73c6f65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2900830345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2900830345
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3537715409
Short name T439
Test name
Test status
Simulation time 6354170853 ps
CPU time 31.85 seconds
Started Jun 05 04:07:36 PM PDT 24
Finished Jun 05 04:08:09 PM PDT 24
Peak memory 203248 kb
Host smart-c4cce4a0-9c3b-4a85-a493-69d9f780f440
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537715409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3537715409
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1147481793
Short name T735
Test name
Test status
Simulation time 4670131004 ps
CPU time 25.27 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:08:03 PM PDT 24
Peak memory 203256 kb
Host smart-f075de14-8927-41af-b017-b5a441df9f39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1147481793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1147481793
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2772041162
Short name T441
Test name
Test status
Simulation time 129868375 ps
CPU time 2.81 seconds
Started Jun 05 04:07:37 PM PDT 24
Finished Jun 05 04:07:41 PM PDT 24
Peak memory 203192 kb
Host smart-d73d00ba-8a5d-463e-90a1-4b0a1ce8084b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772041162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2772041162
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.322769609
Short name T178
Test name
Test status
Simulation time 7995353083 ps
CPU time 79.24 seconds
Started Jun 05 04:07:48 PM PDT 24
Finished Jun 05 04:09:08 PM PDT 24
Peak memory 207336 kb
Host smart-13e3df61-4192-43f0-baf4-c539fbe208d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=322769609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.322769609
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.842221603
Short name T781
Test name
Test status
Simulation time 3268048873 ps
CPU time 80.02 seconds
Started Jun 05 04:07:46 PM PDT 24
Finished Jun 05 04:09:06 PM PDT 24
Peak memory 204456 kb
Host smart-8e6d751d-8411-468d-b9f3-02a603be92bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=842221603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.842221603
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1072438024
Short name T618
Test name
Test status
Simulation time 7078846 ps
CPU time 7.11 seconds
Started Jun 05 04:07:44 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 203116 kb
Host smart-2213e5c2-9fe6-4e6a-9e1d-7db29964c1dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1072438024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.1072438024
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1204791674
Short name T309
Test name
Test status
Simulation time 6292347890 ps
CPU time 382.4 seconds
Started Jun 05 04:07:41 PM PDT 24
Finished Jun 05 04:14:04 PM PDT 24
Peak memory 219776 kb
Host smart-5f9428e2-f292-442b-b832-792f937dbe4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1204791674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.1204791674
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1842550084
Short name T304
Test name
Test status
Simulation time 1281896024 ps
CPU time 10.85 seconds
Started Jun 05 04:07:39 PM PDT 24
Finished Jun 05 04:07:51 PM PDT 24
Peak memory 204648 kb
Host smart-befaa14a-a4a9-4d88-af99-4d7f3b1090c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1842550084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1842550084
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2551445957
Short name T235
Test name
Test status
Simulation time 123685013 ps
CPU time 3.93 seconds
Started Jun 05 04:07:44 PM PDT 24
Finished Jun 05 04:07:48 PM PDT 24
Peak memory 203184 kb
Host smart-e8527ef4-d9e3-4330-a199-204fca5a5b44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2551445957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2551445957
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3468642387
Short name T813
Test name
Test status
Simulation time 22940495380 ps
CPU time 189.58 seconds
Started Jun 05 04:07:47 PM PDT 24
Finished Jun 05 04:10:57 PM PDT 24
Peak memory 205880 kb
Host smart-75187d14-3bfb-4963-aa1e-287400c2be77
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3468642387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.3468642387
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2173489466
Short name T437
Test name
Test status
Simulation time 450155227 ps
CPU time 5.01 seconds
Started Jun 05 04:07:44 PM PDT 24
Finished Jun 05 04:07:49 PM PDT 24
Peak memory 203176 kb
Host smart-ad18da70-dbca-413d-8cfb-173992a88dbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2173489466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2173489466
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.4221070030
Short name T123
Test name
Test status
Simulation time 248358173 ps
CPU time 6.27 seconds
Started Jun 05 04:07:46 PM PDT 24
Finished Jun 05 04:07:53 PM PDT 24
Peak memory 203120 kb
Host smart-7c1e7ef4-bc4a-48e4-9b83-905254b0a362
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4221070030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4221070030
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.2378840801
Short name T419
Test name
Test status
Simulation time 4019677683 ps
CPU time 37.59 seconds
Started Jun 05 04:07:43 PM PDT 24
Finished Jun 05 04:08:22 PM PDT 24
Peak memory 204900 kb
Host smart-fe7fa15e-7df3-4966-a3c9-1fb09af14498
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2378840801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2378840801
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.4283544076
Short name T104
Test name
Test status
Simulation time 198526349336 ps
CPU time 276.66 seconds
Started Jun 05 04:07:43 PM PDT 24
Finished Jun 05 04:12:20 PM PDT 24
Peak memory 211460 kb
Host smart-1809b184-05bf-4a2e-be45-1d720aaba024
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283544076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.4283544076
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1782383936
Short name T246
Test name
Test status
Simulation time 12132082803 ps
CPU time 49.36 seconds
Started Jun 05 04:07:46 PM PDT 24
Finished Jun 05 04:08:36 PM PDT 24
Peak memory 204788 kb
Host smart-2171a922-6507-454a-928b-e1496cf80f71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1782383936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1782383936
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1842944307
Short name T768
Test name
Test status
Simulation time 29622158 ps
CPU time 4.33 seconds
Started Jun 05 04:07:47 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 203520 kb
Host smart-5ca5f38d-e1b7-4e11-aa88-191d3df4d1ca
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842944307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1842944307
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.3869640376
Short name T699
Test name
Test status
Simulation time 527379370 ps
CPU time 13.4 seconds
Started Jun 05 04:07:43 PM PDT 24
Finished Jun 05 04:07:57 PM PDT 24
Peak memory 203752 kb
Host smart-ce14ec9c-3778-4842-a625-0353d75815a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3869640376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3869640376
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.2104709319
Short name T311
Test name
Test status
Simulation time 184012295 ps
CPU time 3.59 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:07:49 PM PDT 24
Peak memory 203184 kb
Host smart-2f725bc0-058f-41d7-bb8e-c2234c45815f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2104709319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2104709319
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.4130886680
Short name T637
Test name
Test status
Simulation time 5258630317 ps
CPU time 26.2 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:08:12 PM PDT 24
Peak memory 203252 kb
Host smart-842d0c81-ea2f-4aa2-886a-8343fe9b65e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130886680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.4130886680
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1839376448
Short name T610
Test name
Test status
Simulation time 4354478393 ps
CPU time 31.42 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:08:17 PM PDT 24
Peak memory 203480 kb
Host smart-a58c3f0f-e403-4d58-b8d7-95acad39b82b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1839376448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1839376448
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3487854672
Short name T859
Test name
Test status
Simulation time 170367218 ps
CPU time 2.5 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:07:48 PM PDT 24
Peak memory 203132 kb
Host smart-aa47029a-c90f-49b1-af47-227bdbcfa07b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487854672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3487854672
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.4153468873
Short name T418
Test name
Test status
Simulation time 4984193860 ps
CPU time 211.05 seconds
Started Jun 05 04:07:44 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 211420 kb
Host smart-f4db4a05-f93f-490e-a26f-c4671e3cda71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4153468873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4153468873
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2827043442
Short name T567
Test name
Test status
Simulation time 10864968420 ps
CPU time 80.4 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:09:06 PM PDT 24
Peak memory 205528 kb
Host smart-853be368-f967-4228-af63-f0aa43fb9622
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2827043442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2827043442
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1400601762
Short name T28
Test name
Test status
Simulation time 448008721 ps
CPU time 158.32 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 208752 kb
Host smart-2569548f-23b5-4011-a8c4-798d3381b25f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1400601762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.1400601762
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2842081163
Short name T844
Test name
Test status
Simulation time 92609341 ps
CPU time 63.15 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:08:49 PM PDT 24
Peak memory 207944 kb
Host smart-552a36cf-5eec-4968-b534-652cc53ccd0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2842081163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.2842081163
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2174370534
Short name T547
Test name
Test status
Simulation time 1309549185 ps
CPU time 28.83 seconds
Started Jun 05 04:07:43 PM PDT 24
Finished Jun 05 04:08:13 PM PDT 24
Peak memory 204552 kb
Host smart-a6b8105f-5e0d-4362-9b40-81a9f25e597b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2174370534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2174370534
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.4256485834
Short name T668
Test name
Test status
Simulation time 65853488 ps
CPU time 4.9 seconds
Started Jun 05 04:07:53 PM PDT 24
Finished Jun 05 04:07:59 PM PDT 24
Peak memory 203180 kb
Host smart-d15b6631-a597-41f4-90d0-24fd32351652
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4256485834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.4256485834
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.141083009
Short name T61
Test name
Test status
Simulation time 48994074597 ps
CPU time 93.23 seconds
Started Jun 05 04:07:54 PM PDT 24
Finished Jun 05 04:09:28 PM PDT 24
Peak memory 211432 kb
Host smart-062fa4bb-2eca-4ead-8bd3-5fc5131e9602
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=141083009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo
w_rsp.141083009
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.83764198
Short name T801
Test name
Test status
Simulation time 134377635 ps
CPU time 17.93 seconds
Started Jun 05 04:07:54 PM PDT 24
Finished Jun 05 04:08:12 PM PDT 24
Peak memory 203448 kb
Host smart-6c5153d7-df64-402d-9ed2-60438d068e00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83764198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.83764198
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.3218783737
Short name T212
Test name
Test status
Simulation time 195434481 ps
CPU time 2.65 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:07:58 PM PDT 24
Peak memory 203196 kb
Host smart-7b4cac43-6505-4c3d-9236-54850f3047f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3218783737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3218783737
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.2804605756
Short name T868
Test name
Test status
Simulation time 773828529 ps
CPU time 32.18 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:08:28 PM PDT 24
Peak memory 204284 kb
Host smart-b5fcaca9-432d-4256-86b4-1eb2d3158b95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2804605756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2804605756
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.146737973
Short name T558
Test name
Test status
Simulation time 96120512260 ps
CPU time 194.09 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 211424 kb
Host smart-e80c50f4-480e-4fd0-9b7f-efb0ce1947a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=146737973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.146737973
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3037931265
Short name T284
Test name
Test status
Simulation time 8299307904 ps
CPU time 46.31 seconds
Started Jun 05 04:07:56 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 204636 kb
Host smart-44dab09a-5c5a-465a-813d-350825159c0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3037931265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3037931265
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3465696483
Short name T554
Test name
Test status
Simulation time 156896632 ps
CPU time 5.39 seconds
Started Jun 05 04:07:54 PM PDT 24
Finished Jun 05 04:08:00 PM PDT 24
Peak memory 203240 kb
Host smart-2161b387-74d9-41c2-a372-4c3339688803
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465696483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3465696483
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.4260182188
Short name T528
Test name
Test status
Simulation time 3180874452 ps
CPU time 23.92 seconds
Started Jun 05 04:07:53 PM PDT 24
Finished Jun 05 04:08:18 PM PDT 24
Peak memory 203316 kb
Host smart-cac03f77-5fff-4807-89e4-802d1bf489a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4260182188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4260182188
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1271259694
Short name T365
Test name
Test status
Simulation time 94547716 ps
CPU time 3.02 seconds
Started Jun 05 04:07:48 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 203176 kb
Host smart-688834f0-55af-4a10-b64f-1745b6720d41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1271259694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1271259694
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3040513264
Short name T470
Test name
Test status
Simulation time 11908264184 ps
CPU time 30.04 seconds
Started Jun 05 04:07:46 PM PDT 24
Finished Jun 05 04:08:17 PM PDT 24
Peak memory 203260 kb
Host smart-f7a8d855-1378-4a60-a204-cc2888de7de5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040513264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3040513264
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2204371057
Short name T449
Test name
Test status
Simulation time 5251125861 ps
CPU time 40.71 seconds
Started Jun 05 04:07:56 PM PDT 24
Finished Jun 05 04:08:37 PM PDT 24
Peak memory 203256 kb
Host smart-cbac56c2-8caa-424c-a5f7-ed3e8c4ce4e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2204371057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2204371057
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4150412206
Short name T353
Test name
Test status
Simulation time 28787060 ps
CPU time 2.12 seconds
Started Jun 05 04:07:45 PM PDT 24
Finished Jun 05 04:07:48 PM PDT 24
Peak memory 203104 kb
Host smart-feed147d-7b37-40a5-9068-f4890a49e8a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150412206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.4150412206
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.2848943560
Short name T172
Test name
Test status
Simulation time 771619685 ps
CPU time 76.66 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:09:12 PM PDT 24
Peak memory 206536 kb
Host smart-240ba045-3da5-4003-931a-be78ea05b4ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2848943560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2848943560
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1511217072
Short name T835
Test name
Test status
Simulation time 1284099982 ps
CPU time 34.32 seconds
Started Jun 05 04:07:53 PM PDT 24
Finished Jun 05 04:08:28 PM PDT 24
Peak memory 203936 kb
Host smart-2ed0d5b5-45d7-4f6e-b8da-648972e489be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1511217072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1511217072
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.961928104
Short name T687
Test name
Test status
Simulation time 472242509 ps
CPU time 135.78 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 207612 kb
Host smart-af502fef-e838-4894-9aa4-68da08602108
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=961928104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand
_reset.961928104
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2499118723
Short name T444
Test name
Test status
Simulation time 715416525 ps
CPU time 189.68 seconds
Started Jun 05 04:07:56 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 211372 kb
Host smart-7a08f8c4-3184-4fb8-8670-63094d5c2e5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2499118723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.2499118723
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3522766879
Short name T560
Test name
Test status
Simulation time 475167658 ps
CPU time 5.91 seconds
Started Jun 05 04:07:57 PM PDT 24
Finished Jun 05 04:08:03 PM PDT 24
Peak memory 211372 kb
Host smart-7b4e8bd5-d206-47c4-9701-7a32bdd17d0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3522766879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3522766879
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1593746470
Short name T707
Test name
Test status
Simulation time 521652438 ps
CPU time 43.02 seconds
Started Jun 05 04:07:54 PM PDT 24
Finished Jun 05 04:08:37 PM PDT 24
Peak memory 204744 kb
Host smart-404a0cc2-9ac8-4a51-ba8c-d69cd02373d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1593746470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1593746470
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3467770139
Short name T275
Test name
Test status
Simulation time 60951180957 ps
CPU time 225.66 seconds
Started Jun 05 04:08:02 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 205760 kb
Host smart-1f142fc0-2852-4e47-8e02-66f6a2d88cf8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3467770139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.3467770139
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2386474580
Short name T626
Test name
Test status
Simulation time 235231102 ps
CPU time 10.24 seconds
Started Jun 05 04:08:06 PM PDT 24
Finished Jun 05 04:08:17 PM PDT 24
Peak memory 203568 kb
Host smart-30997c9f-9938-4d61-aecb-a85af6eaab03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2386474580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2386474580
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.474684670
Short name T504
Test name
Test status
Simulation time 1324361301 ps
CPU time 22.45 seconds
Started Jun 05 04:08:03 PM PDT 24
Finished Jun 05 04:08:27 PM PDT 24
Peak memory 203096 kb
Host smart-6c79e818-948f-4bb6-a8a9-45c4ec6799c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=474684670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.474684670
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.561147473
Short name T530
Test name
Test status
Simulation time 198152657 ps
CPU time 27.13 seconds
Started Jun 05 04:07:54 PM PDT 24
Finished Jun 05 04:08:22 PM PDT 24
Peak memory 204288 kb
Host smart-a11d3d76-4636-455a-b577-33f37cf9d7aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=561147473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.561147473
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.951876593
Short name T46
Test name
Test status
Simulation time 63881595624 ps
CPU time 253.25 seconds
Started Jun 05 04:07:56 PM PDT 24
Finished Jun 05 04:12:10 PM PDT 24
Peak memory 205456 kb
Host smart-901add75-3a3d-4f42-b97c-f77c7c5844e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=951876593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.951876593
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3769530597
Short name T157
Test name
Test status
Simulation time 24686493248 ps
CPU time 47.56 seconds
Started Jun 05 04:07:53 PM PDT 24
Finished Jun 05 04:08:41 PM PDT 24
Peak memory 211436 kb
Host smart-229547b2-739f-4342-9c44-59d217e193e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3769530597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3769530597
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3881198607
Short name T492
Test name
Test status
Simulation time 81357148 ps
CPU time 8.14 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:08:04 PM PDT 24
Peak memory 204232 kb
Host smart-4b33acee-8ee6-442b-bd64-2f7db68d438f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881198607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3881198607
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.1946045873
Short name T144
Test name
Test status
Simulation time 407627418 ps
CPU time 20.61 seconds
Started Jun 05 04:08:06 PM PDT 24
Finished Jun 05 04:08:28 PM PDT 24
Peak memory 203816 kb
Host smart-1db7831e-54dc-424f-aa16-d186d96e7c13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1946045873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1946045873
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.1587585125
Short name T23
Test name
Test status
Simulation time 49536138 ps
CPU time 2.32 seconds
Started Jun 05 04:07:53 PM PDT 24
Finished Jun 05 04:07:56 PM PDT 24
Peak memory 203176 kb
Host smart-269800f6-f64c-4f20-8d21-43c5b7f7d35f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1587585125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1587585125
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1599677359
Short name T78
Test name
Test status
Simulation time 11899448605 ps
CPU time 31.12 seconds
Started Jun 05 04:07:54 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 203228 kb
Host smart-88f18bfb-8922-4502-8a8e-8aebbbae6578
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599677359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1599677359
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.791965887
Short name T526
Test name
Test status
Simulation time 4154790190 ps
CPU time 30.68 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 203216 kb
Host smart-f0ccf5e0-ec61-40f0-bb16-01f0e8fd4989
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=791965887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.791965887
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1693250381
Short name T895
Test name
Test status
Simulation time 85575464 ps
CPU time 2.67 seconds
Started Jun 05 04:07:55 PM PDT 24
Finished Jun 05 04:07:58 PM PDT 24
Peak memory 203188 kb
Host smart-0b1fc829-8668-4433-97be-5139fa8bed7b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693250381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1693250381
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3400012327
Short name T698
Test name
Test status
Simulation time 5149255146 ps
CPU time 81.63 seconds
Started Jun 05 04:08:02 PM PDT 24
Finished Jun 05 04:09:24 PM PDT 24
Peak memory 211448 kb
Host smart-798ad53a-b69e-4a98-af22-cf92bcf6ffc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3400012327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3400012327
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3040902310
Short name T584
Test name
Test status
Simulation time 15323439691 ps
CPU time 153.74 seconds
Started Jun 05 04:08:05 PM PDT 24
Finished Jun 05 04:10:39 PM PDT 24
Peak memory 206364 kb
Host smart-a5f7733a-71b2-4aba-815c-cf392712a79e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3040902310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3040902310
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2777656188
Short name T156
Test name
Test status
Simulation time 2617146433 ps
CPU time 383.01 seconds
Started Jun 05 04:08:05 PM PDT 24
Finished Jun 05 04:14:29 PM PDT 24
Peak memory 209960 kb
Host smart-c167eb39-aebf-456d-8817-31925bc9eb3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2777656188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.2777656188
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1817767538
Short name T629
Test name
Test status
Simulation time 1415154427 ps
CPU time 203.51 seconds
Started Jun 05 04:08:04 PM PDT 24
Finished Jun 05 04:11:28 PM PDT 24
Peak memory 211380 kb
Host smart-592bdf0b-0491-49d5-be21-2e2a8d9d9ca8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1817767538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1817767538
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.422490278
Short name T266
Test name
Test status
Simulation time 516768166 ps
CPU time 23.25 seconds
Started Jun 05 04:08:02 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 204672 kb
Host smart-ac431edf-ce4d-438d-929c-ef9c6ada15a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=422490278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.422490278
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.4176315029
Short name T102
Test name
Test status
Simulation time 1093372176 ps
CPU time 38.17 seconds
Started Jun 05 04:08:05 PM PDT 24
Finished Jun 05 04:08:44 PM PDT 24
Peak memory 205268 kb
Host smart-31a4ca07-6f04-4e71-bd8e-6d83fa41956f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4176315029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.4176315029
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3205965107
Short name T359
Test name
Test status
Simulation time 2509247891 ps
CPU time 13.24 seconds
Started Jun 05 04:08:09 PM PDT 24
Finished Jun 05 04:08:22 PM PDT 24
Peak memory 203244 kb
Host smart-d6542fdc-edb7-4e49-bde9-71bfb433bda8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3205965107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3205965107
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.4274047340
Short name T237
Test name
Test status
Simulation time 182084931 ps
CPU time 15.47 seconds
Started Jun 05 04:08:05 PM PDT 24
Finished Jun 05 04:08:21 PM PDT 24
Peak memory 203200 kb
Host smart-d15a9829-5e87-4605-9b6e-48b9e9bc980d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4274047340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4274047340
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.3520324522
Short name T57
Test name
Test status
Simulation time 560444109 ps
CPU time 18.88 seconds
Started Jun 05 04:08:04 PM PDT 24
Finished Jun 05 04:08:23 PM PDT 24
Peak memory 204300 kb
Host smart-8a25661e-9897-4a41-99ef-88d2b1cb959f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3520324522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3520324522
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2567985156
Short name T575
Test name
Test status
Simulation time 19926556861 ps
CPU time 115.13 seconds
Started Jun 05 04:08:04 PM PDT 24
Finished Jun 05 04:10:00 PM PDT 24
Peak memory 211444 kb
Host smart-ce85b177-6be1-44b2-9562-ffce410459b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567985156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2567985156
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.574073016
Short name T207
Test name
Test status
Simulation time 18586728836 ps
CPU time 142.97 seconds
Started Jun 05 04:08:03 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 204496 kb
Host smart-2a52b36a-560e-466e-a8e4-89fdc81a5741
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=574073016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.574073016
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2060146808
Short name T288
Test name
Test status
Simulation time 370428441 ps
CPU time 16.5 seconds
Started Jun 05 04:08:02 PM PDT 24
Finished Jun 05 04:08:19 PM PDT 24
Peak memory 211376 kb
Host smart-f31f2e1f-f51b-466a-b9f8-3028e10ea8c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060146808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2060146808
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.3796984547
Short name T116
Test name
Test status
Simulation time 2819734633 ps
CPU time 30.59 seconds
Started Jun 05 04:08:04 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 203992 kb
Host smart-0df77230-1047-40a0-a0bc-2ccf716a04a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3796984547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3796984547
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.1855058593
Short name T884
Test name
Test status
Simulation time 191668526 ps
CPU time 3.34 seconds
Started Jun 05 04:07:59 PM PDT 24
Finished Jun 05 04:08:03 PM PDT 24
Peak memory 203184 kb
Host smart-c3e9c6f0-6142-4cc2-8945-7018f07003bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1855058593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1855058593
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2385375559
Short name T565
Test name
Test status
Simulation time 22484468028 ps
CPU time 36.3 seconds
Started Jun 05 04:08:06 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 203252 kb
Host smart-7c4de265-61b4-4be4-b451-c81a8f375aec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385375559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2385375559
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.824098696
Short name T189
Test name
Test status
Simulation time 9107819033 ps
CPU time 33.58 seconds
Started Jun 05 04:08:06 PM PDT 24
Finished Jun 05 04:08:40 PM PDT 24
Peak memory 203248 kb
Host smart-9429e943-df9a-4566-b3fc-bdfc7ddded28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=824098696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.824098696
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.4218265349
Short name T870
Test name
Test status
Simulation time 52104242 ps
CPU time 2.38 seconds
Started Jun 05 04:08:05 PM PDT 24
Finished Jun 05 04:08:08 PM PDT 24
Peak memory 203188 kb
Host smart-2f3a2dd8-de4a-46f6-a336-995675a5b83b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218265349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.4218265349
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2429839453
Short name T312
Test name
Test status
Simulation time 1393060790 ps
CPU time 167.8 seconds
Started Jun 05 04:08:12 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 205660 kb
Host smart-1ecb1f84-5afb-46be-bace-b71c2167810c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2429839453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2429839453
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1543150496
Short name T267
Test name
Test status
Simulation time 8218258824 ps
CPU time 268.58 seconds
Started Jun 05 04:08:09 PM PDT 24
Finished Jun 05 04:12:38 PM PDT 24
Peak memory 211428 kb
Host smart-414091f5-269a-4b69-a087-0f1f100980bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1543150496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1543150496
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3574370073
Short name T65
Test name
Test status
Simulation time 8842836233 ps
CPU time 250.99 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:12:21 PM PDT 24
Peak memory 209372 kb
Host smart-a23117f6-0035-42f6-8f8c-0a910961db95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3574370073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.3574370073
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1816076373
Short name T240
Test name
Test status
Simulation time 205735218 ps
CPU time 54.23 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:09:05 PM PDT 24
Peak memory 207356 kb
Host smart-3cc10323-9a8a-4c72-b613-65832aac98f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1816076373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.1816076373
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1714117970
Short name T755
Test name
Test status
Simulation time 601947228 ps
CPU time 30.8 seconds
Started Jun 05 04:08:05 PM PDT 24
Finished Jun 05 04:08:36 PM PDT 24
Peak memory 205252 kb
Host smart-e9ada2f1-08d9-4d93-9d7e-db92b2fbcfcf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1714117970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1714117970
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1032358161
Short name T71
Test name
Test status
Simulation time 3198418575 ps
CPU time 60.85 seconds
Started Jun 05 04:08:15 PM PDT 24
Finished Jun 05 04:09:17 PM PDT 24
Peak memory 206696 kb
Host smart-96919204-4537-4953-9ca5-4415daf93a93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1032358161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1032358161
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1447809220
Short name T580
Test name
Test status
Simulation time 48577271894 ps
CPU time 186.98 seconds
Started Jun 05 04:08:11 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 211448 kb
Host smart-1fe1ec77-8e5a-43a4-956f-657efdb07310
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1447809220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.1447809220
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2500328996
Short name T126
Test name
Test status
Simulation time 1788740822 ps
CPU time 27.08 seconds
Started Jun 05 04:08:16 PM PDT 24
Finished Jun 05 04:08:44 PM PDT 24
Peak memory 203708 kb
Host smart-b88cdc37-0313-4543-bc05-1a9ec37b5f5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500328996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2500328996
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.2790431291
Short name T625
Test name
Test status
Simulation time 1234979331 ps
CPU time 28.09 seconds
Started Jun 05 04:08:09 PM PDT 24
Finished Jun 05 04:08:38 PM PDT 24
Peak memory 203212 kb
Host smart-ff6c54cc-d4ee-498f-869e-83a86155cb75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2790431291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2790431291
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.2306473822
Short name T483
Test name
Test status
Simulation time 82168925 ps
CPU time 10.29 seconds
Started Jun 05 04:08:12 PM PDT 24
Finished Jun 05 04:08:23 PM PDT 24
Peak memory 211352 kb
Host smart-9ea3e688-9b66-4f02-90f1-7ee1f077afc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2306473822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2306473822
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.401940946
Short name T173
Test name
Test status
Simulation time 90573283098 ps
CPU time 117.24 seconds
Started Jun 05 04:08:14 PM PDT 24
Finished Jun 05 04:10:12 PM PDT 24
Peak memory 204700 kb
Host smart-e78001c7-122b-4cfd-9602-410053f60db2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=401940946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.401940946
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.604778290
Short name T29
Test name
Test status
Simulation time 10067814152 ps
CPU time 58.8 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:09:09 PM PDT 24
Peak memory 211444 kb
Host smart-99085920-9f6b-41ce-9928-890c4e8da798
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=604778290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.604778290
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.4199126845
Short name T539
Test name
Test status
Simulation time 194988055 ps
CPU time 22.6 seconds
Started Jun 05 04:08:14 PM PDT 24
Finished Jun 05 04:08:38 PM PDT 24
Peak memory 204956 kb
Host smart-d8f6dff5-7128-433a-912f-70bda647cefd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199126845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4199126845
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.1299649296
Short name T351
Test name
Test status
Simulation time 29519116 ps
CPU time 2.18 seconds
Started Jun 05 04:08:14 PM PDT 24
Finished Jun 05 04:08:17 PM PDT 24
Peak memory 203272 kb
Host smart-d8953735-fa3f-460c-9686-0d893602bdb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1299649296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1299649296
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.2158459301
Short name T616
Test name
Test status
Simulation time 31346291 ps
CPU time 2.19 seconds
Started Jun 05 04:08:09 PM PDT 24
Finished Jun 05 04:08:12 PM PDT 24
Peak memory 203168 kb
Host smart-d0990542-1918-492e-a01a-1f5dc52964c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2158459301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2158459301
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2023327323
Short name T435
Test name
Test status
Simulation time 32595529891 ps
CPU time 49.64 seconds
Started Jun 05 04:08:11 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 203224 kb
Host smart-d1393354-2549-44b5-a584-c0413824d05d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023327323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2023327323
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3546488063
Short name T242
Test name
Test status
Simulation time 5129282218 ps
CPU time 34.53 seconds
Started Jun 05 04:08:15 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 203196 kb
Host smart-34bbdc6c-5291-44e1-8e2c-6a0d6f9844a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3546488063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3546488063
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.618446328
Short name T22
Test name
Test status
Simulation time 72323736 ps
CPU time 2.08 seconds
Started Jun 05 04:08:14 PM PDT 24
Finished Jun 05 04:08:17 PM PDT 24
Peak memory 203184 kb
Host smart-df7c0204-3044-4692-a2c8-4cc44d74e35c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618446328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.618446328
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3576171302
Short name T509
Test name
Test status
Simulation time 8327352738 ps
CPU time 236.61 seconds
Started Jun 05 04:08:11 PM PDT 24
Finished Jun 05 04:12:09 PM PDT 24
Peak memory 206980 kb
Host smart-8cd1db6e-5bb3-48f7-a32b-79c63e8caf9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3576171302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3576171302
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3449932179
Short name T825
Test name
Test status
Simulation time 315429316 ps
CPU time 29.12 seconds
Started Jun 05 04:08:15 PM PDT 24
Finished Jun 05 04:08:45 PM PDT 24
Peak memory 204716 kb
Host smart-dfc90ee1-4ae2-48df-95f0-55ace594244b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3449932179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3449932179
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3234706434
Short name T705
Test name
Test status
Simulation time 3040723722 ps
CPU time 198.28 seconds
Started Jun 05 04:08:14 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 209868 kb
Host smart-e208d7b2-b450-486c-9bc0-74ec9bac2633
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3234706434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.3234706434
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1299292433
Short name T596
Test name
Test status
Simulation time 143139617 ps
CPU time 28.72 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:08:40 PM PDT 24
Peak memory 205976 kb
Host smart-84116b0d-6f6b-4b5c-b372-ac0e2c51ab38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1299292433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.1299292433
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1830432023
Short name T538
Test name
Test status
Simulation time 134286859 ps
CPU time 13.33 seconds
Started Jun 05 04:08:09 PM PDT 24
Finished Jun 05 04:08:23 PM PDT 24
Peak memory 204640 kb
Host smart-308cd3ed-be9e-4c05-b96b-d20d6e98f308
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1830432023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1830432023
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2280711430
Short name T368
Test name
Test status
Simulation time 97382937843 ps
CPU time 342.84 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:14:05 PM PDT 24
Peak memory 205704 kb
Host smart-91d46ff6-a636-4819-88e0-786145d579ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2280711430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2280711430
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.566250407
Short name T805
Test name
Test status
Simulation time 104337102 ps
CPU time 12.85 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 203440 kb
Host smart-2fed7f9b-dd8b-4887-b3f4-2d556aee8a5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=566250407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.566250407
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.1166404444
Short name T653
Test name
Test status
Simulation time 202206147 ps
CPU time 4.84 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:08:25 PM PDT 24
Peak memory 203196 kb
Host smart-a0efadb2-b7ba-410e-b03f-8b46dbb95896
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1166404444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1166404444
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.3644605345
Short name T192
Test name
Test status
Simulation time 266969748 ps
CPU time 24.3 seconds
Started Jun 05 04:08:09 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 204224 kb
Host smart-0c8c3466-5a98-4457-b61a-8618236eb9ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3644605345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3644605345
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2093896863
Short name T758
Test name
Test status
Simulation time 13070291186 ps
CPU time 68.84 seconds
Started Jun 05 04:08:09 PM PDT 24
Finished Jun 05 04:09:19 PM PDT 24
Peak memory 204600 kb
Host smart-107f93ea-6050-475b-94e3-b6ab31e4c21b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093896863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2093896863
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4180790578
Short name T236
Test name
Test status
Simulation time 20973132954 ps
CPU time 138.58 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:10:29 PM PDT 24
Peak memory 211680 kb
Host smart-1cbfe080-8e42-4d61-b2b3-8b3849fc2f7f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4180790578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.4180790578
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3015530686
Short name T310
Test name
Test status
Simulation time 27670463 ps
CPU time 2.12 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:08:13 PM PDT 24
Peak memory 203208 kb
Host smart-6aee7d93-bb6a-4b42-9fd6-e79482ec7b3e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015530686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3015530686
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.123384799
Short name T739
Test name
Test status
Simulation time 1449239042 ps
CPU time 27.14 seconds
Started Jun 05 04:08:22 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 203692 kb
Host smart-d5fa2914-a70d-43fa-b893-ee0146fd8005
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=123384799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.123384799
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.1587511621
Short name T39
Test name
Test status
Simulation time 193648172 ps
CPU time 3.24 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:08:14 PM PDT 24
Peak memory 203172 kb
Host smart-1462242a-b423-469e-9e62-f10e54abf45c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1587511621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1587511621
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2512097637
Short name T816
Test name
Test status
Simulation time 8397655017 ps
CPU time 32.11 seconds
Started Jun 05 04:08:14 PM PDT 24
Finished Jun 05 04:08:47 PM PDT 24
Peak memory 203260 kb
Host smart-28e95fa1-bf71-4d09-9fa5-0720ae37cd9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512097637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2512097637
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.655737719
Short name T40
Test name
Test status
Simulation time 5515627580 ps
CPU time 27.55 seconds
Started Jun 05 04:08:11 PM PDT 24
Finished Jun 05 04:08:39 PM PDT 24
Peak memory 203148 kb
Host smart-ce346b0d-56b4-4268-b2e1-0cb98ba1eb8f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=655737719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.655737719
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2785977705
Short name T563
Test name
Test status
Simulation time 47277861 ps
CPU time 2.22 seconds
Started Jun 05 04:08:10 PM PDT 24
Finished Jun 05 04:08:13 PM PDT 24
Peak memory 203156 kb
Host smart-44e37729-9249-4914-94c7-570bf078a354
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785977705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2785977705
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.971711810
Short name T612
Test name
Test status
Simulation time 3465983496 ps
CPU time 136.27 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 207016 kb
Host smart-d1fa3c03-bce2-45f5-934a-f4ab9e5315f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=971711810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.971711810
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.324387222
Short name T741
Test name
Test status
Simulation time 285343668 ps
CPU time 3.61 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 203124 kb
Host smart-29d97aa1-d817-4cb8-958b-8e3d9a04f70f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=324387222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.324387222
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.142704262
Short name T775
Test name
Test status
Simulation time 437833528 ps
CPU time 111.3 seconds
Started Jun 05 04:08:20 PM PDT 24
Finished Jun 05 04:10:12 PM PDT 24
Peak memory 209356 kb
Host smart-2e419ebf-c9ee-4c71-ac35-2f0417732981
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=142704262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_res
et_error.142704262
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3037608173
Short name T780
Test name
Test status
Simulation time 51435367 ps
CPU time 2.33 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:08:24 PM PDT 24
Peak memory 203132 kb
Host smart-9e1c5189-68fc-4236-8908-50ed5a5641f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037608173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3037608173
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.4013499988
Short name T101
Test name
Test status
Simulation time 1354051065 ps
CPU time 41.53 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:09:02 PM PDT 24
Peak memory 204124 kb
Host smart-5fd36180-2627-475e-998a-d94258de33b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4013499988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4013499988
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.609924139
Short name T270
Test name
Test status
Simulation time 241706290708 ps
CPU time 517.23 seconds
Started Jun 05 04:08:22 PM PDT 24
Finished Jun 05 04:17:00 PM PDT 24
Peak memory 211348 kb
Host smart-fc471e66-8820-43a9-a57f-4747372a6ae1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=609924139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo
w_rsp.609924139
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.542747507
Short name T315
Test name
Test status
Simulation time 13568119 ps
CPU time 1.81 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:08:23 PM PDT 24
Peak memory 203176 kb
Host smart-e5764ca7-abc4-40b3-a745-710e19962cb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=542747507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.542747507
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.694808618
Short name T522
Test name
Test status
Simulation time 95429812 ps
CPU time 7.27 seconds
Started Jun 05 04:08:25 PM PDT 24
Finished Jun 05 04:08:33 PM PDT 24
Peak memory 203192 kb
Host smart-76b4be46-915b-4156-a594-1cbac300bc2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=694808618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.694808618
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.1611296969
Short name T533
Test name
Test status
Simulation time 96932054 ps
CPU time 12.13 seconds
Started Jun 05 04:08:23 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 211368 kb
Host smart-37d4ec4b-bf48-4e95-8a33-84b62b7f7afa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1611296969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1611296969
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1466648967
Short name T395
Test name
Test status
Simulation time 29475401752 ps
CPU time 140.59 seconds
Started Jun 05 04:08:22 PM PDT 24
Finished Jun 05 04:10:43 PM PDT 24
Peak memory 211368 kb
Host smart-d4b1dd17-0203-47f3-a0f9-5b960cb1c3f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466648967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1466648967
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3928955824
Short name T450
Test name
Test status
Simulation time 1350237071 ps
CPU time 11.7 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:08:31 PM PDT 24
Peak memory 203132 kb
Host smart-a72ee3d8-1200-4a48-8969-f914e44e78e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3928955824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3928955824
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2586317555
Short name T515
Test name
Test status
Simulation time 69542368 ps
CPU time 8.8 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:08:28 PM PDT 24
Peak memory 204316 kb
Host smart-23a0666f-00ee-49ea-9bb1-c3218443c487
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586317555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2586317555
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.23186372
Short name T193
Test name
Test status
Simulation time 2873261017 ps
CPU time 19.77 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:08:40 PM PDT 24
Peak memory 203792 kb
Host smart-70411d6a-45e3-4d01-b66c-3a5e11fb2a8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23186372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.23186372
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.2032973692
Short name T494
Test name
Test status
Simulation time 173362288 ps
CPU time 3.62 seconds
Started Jun 05 04:08:22 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 203180 kb
Host smart-abd3a939-8cb4-4edd-b5e5-292996c8bfea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2032973692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2032973692
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3638693109
Short name T867
Test name
Test status
Simulation time 5111390718 ps
CPU time 25.06 seconds
Started Jun 05 04:08:20 PM PDT 24
Finished Jun 05 04:08:45 PM PDT 24
Peak memory 203252 kb
Host smart-2dff8c22-b21c-493d-b539-f264ebb925af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638693109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3638693109
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.368928610
Short name T529
Test name
Test status
Simulation time 5800620212 ps
CPU time 32.29 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:08:54 PM PDT 24
Peak memory 203216 kb
Host smart-7dc9ca80-e867-4cc6-afa2-86fb96e6dc56
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=368928610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.368928610
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.501688152
Short name T811
Test name
Test status
Simulation time 28470971 ps
CPU time 1.86 seconds
Started Jun 05 04:08:24 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 203184 kb
Host smart-a0946e63-98da-46d9-a7ff-1939f7d06093
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501688152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.501688152
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3036056999
Short name T553
Test name
Test status
Simulation time 8887575312 ps
CPU time 229.56 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:12:12 PM PDT 24
Peak memory 206092 kb
Host smart-3f874162-2fd6-42e3-87de-72cb45f2ae7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3036056999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3036056999
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4225876102
Short name T643
Test name
Test status
Simulation time 4420245450 ps
CPU time 108.54 seconds
Started Jun 05 04:08:20 PM PDT 24
Finished Jun 05 04:10:10 PM PDT 24
Peak memory 211428 kb
Host smart-7c9f5e7b-d625-4e22-ba01-87522fe33090
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4225876102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.4225876102
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1742203049
Short name T724
Test name
Test status
Simulation time 5144619487 ps
CPU time 365.55 seconds
Started Jun 05 04:08:20 PM PDT 24
Finished Jun 05 04:14:26 PM PDT 24
Peak memory 209472 kb
Host smart-7250e146-ab44-4c40-b999-a0a8342220c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1742203049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.1742203049
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3408880613
Short name T278
Test name
Test status
Simulation time 426432641 ps
CPU time 124.12 seconds
Started Jun 05 04:08:19 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 209752 kb
Host smart-fc0d940e-1380-4be8-99b9-d21586179596
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3408880613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.3408880613
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3942000146
Short name T44
Test name
Test status
Simulation time 306011709 ps
CPU time 3.8 seconds
Started Jun 05 04:08:24 PM PDT 24
Finished Jun 05 04:08:29 PM PDT 24
Peak memory 211348 kb
Host smart-53b3fc73-c097-4530-b2e4-d4a0e4b4ab4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3942000146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3942000146
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1176116880
Short name T133
Test name
Test status
Simulation time 2330839446 ps
CPU time 50.59 seconds
Started Jun 05 04:04:12 PM PDT 24
Finished Jun 05 04:05:03 PM PDT 24
Peak memory 206004 kb
Host smart-0caeb6b6-8e7d-4c66-a010-2cd2a15ce80b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1176116880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1176116880
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.863970141
Short name T830
Test name
Test status
Simulation time 5005682722 ps
CPU time 24.31 seconds
Started Jun 05 04:04:09 PM PDT 24
Finished Jun 05 04:04:34 PM PDT 24
Peak memory 203276 kb
Host smart-22281515-1e75-4a0b-95dd-768b3274d3a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=863970141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow
_rsp.863970141
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1303892441
Short name T636
Test name
Test status
Simulation time 289943613 ps
CPU time 19.45 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:04:35 PM PDT 24
Peak memory 203180 kb
Host smart-e3dd12a2-a5f7-484a-a169-57a9472d371d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1303892441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1303892441
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.3866520508
Short name T898
Test name
Test status
Simulation time 252065742 ps
CPU time 11.83 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:04:28 PM PDT 24
Peak memory 203196 kb
Host smart-435f621d-bd1e-4505-b205-0e97ac40d023
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3866520508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3866520508
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.3712089990
Short name T725
Test name
Test status
Simulation time 68002590 ps
CPU time 7.55 seconds
Started Jun 05 04:04:08 PM PDT 24
Finished Jun 05 04:04:16 PM PDT 24
Peak memory 211260 kb
Host smart-858a06f9-0ae7-443b-bd80-d6bd5671ed2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3712089990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3712089990
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1127417561
Short name T230
Test name
Test status
Simulation time 24541532490 ps
CPU time 130.36 seconds
Started Jun 05 04:04:07 PM PDT 24
Finished Jun 05 04:06:18 PM PDT 24
Peak memory 204412 kb
Host smart-e8241a6f-eabb-41ab-8c0e-66cd709d7b87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127417561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1127417561
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1649977647
Short name T761
Test name
Test status
Simulation time 4769320283 ps
CPU time 15.24 seconds
Started Jun 05 04:04:13 PM PDT 24
Finished Jun 05 04:04:29 PM PDT 24
Peak memory 203168 kb
Host smart-0d17b43e-4cd8-4ac2-8d4f-98a0de46f9d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1649977647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1649977647
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.849602560
Short name T175
Test name
Test status
Simulation time 325181016 ps
CPU time 17.81 seconds
Started Jun 05 04:04:11 PM PDT 24
Finished Jun 05 04:04:29 PM PDT 24
Peak memory 211280 kb
Host smart-4ca1a715-cf8e-405a-87e8-fac99246c98f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849602560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.849602560
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.4089512541
Short name T661
Test name
Test status
Simulation time 987272713 ps
CPU time 16.69 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:04:33 PM PDT 24
Peak memory 203780 kb
Host smart-1e93cb32-33cb-423f-a9c2-c67189c2c2a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4089512541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4089512541
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.2796816906
Short name T434
Test name
Test status
Simulation time 131247831 ps
CPU time 2.47 seconds
Started Jun 05 04:04:07 PM PDT 24
Finished Jun 05 04:04:10 PM PDT 24
Peak memory 203108 kb
Host smart-1f00e8b1-4a0d-49bc-9538-e40922c9e567
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2796816906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2796816906
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2855607464
Short name T374
Test name
Test status
Simulation time 9924126217 ps
CPU time 34.77 seconds
Started Jun 05 04:04:10 PM PDT 24
Finished Jun 05 04:04:45 PM PDT 24
Peak memory 203492 kb
Host smart-f4f55450-167e-48d5-a0f9-ea1a4d370b0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855607464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2855607464
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2726388120
Short name T346
Test name
Test status
Simulation time 3000558904 ps
CPU time 23.46 seconds
Started Jun 05 04:04:10 PM PDT 24
Finished Jun 05 04:04:34 PM PDT 24
Peak memory 203192 kb
Host smart-b41f62ba-7a54-4304-8241-d1bf7e54ca54
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2726388120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2726388120
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.779758884
Short name T458
Test name
Test status
Simulation time 37816043 ps
CPU time 2.37 seconds
Started Jun 05 04:04:07 PM PDT 24
Finished Jun 05 04:04:10 PM PDT 24
Peak memory 203176 kb
Host smart-a55e01d6-0558-4949-8749-647e2e41d6bc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779758884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.779758884
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3652162581
Short name T717
Test name
Test status
Simulation time 9836628245 ps
CPU time 124.45 seconds
Started Jun 05 04:04:18 PM PDT 24
Finished Jun 05 04:06:23 PM PDT 24
Peak memory 211308 kb
Host smart-80f91eab-ed68-4d08-a24c-2632eafde0ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3652162581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3652162581
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4003785190
Short name T271
Test name
Test status
Simulation time 4515719752 ps
CPU time 126.93 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:06:23 PM PDT 24
Peak memory 204476 kb
Host smart-311965d9-642a-40cd-b6c2-a0258b41450f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003785190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4003785190
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.4105802565
Short name T9
Test name
Test status
Simulation time 836989335 ps
CPU time 292.92 seconds
Started Jun 05 04:04:17 PM PDT 24
Finished Jun 05 04:09:11 PM PDT 24
Peak memory 209472 kb
Host smart-2cf1d772-2b8a-4ec1-a750-5451129af70c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4105802565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.4105802565
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1886073615
Short name T202
Test name
Test status
Simulation time 932367824 ps
CPU time 242.08 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:08:22 PM PDT 24
Peak memory 219524 kb
Host smart-db48418d-6abd-484d-b1c6-50fcd1c0efad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1886073615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.1886073615
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.105482498
Short name T98
Test name
Test status
Simulation time 688073327 ps
CPU time 22.5 seconds
Started Jun 05 04:04:17 PM PDT 24
Finished Jun 05 04:04:40 PM PDT 24
Peak memory 204488 kb
Host smart-31f56c18-cf1e-4aa3-b873-8a9a07cb3c49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105482498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.105482498
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.391842385
Short name T183
Test name
Test status
Simulation time 371519945 ps
CPU time 40.46 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:05:01 PM PDT 24
Peak memory 211360 kb
Host smart-64175da6-a674-4356-accd-b18c153c95a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=391842385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.391842385
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2439024576
Short name T122
Test name
Test status
Simulation time 4502682175 ps
CPU time 26.78 seconds
Started Jun 05 04:04:17 PM PDT 24
Finished Jun 05 04:04:45 PM PDT 24
Peak memory 203856 kb
Host smart-d7b2f089-d681-43c6-927e-e50912c3ef7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2439024576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2439024576
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.2302808590
Short name T160
Test name
Test status
Simulation time 992372710 ps
CPU time 32.87 seconds
Started Jun 05 04:04:16 PM PDT 24
Finished Jun 05 04:04:50 PM PDT 24
Peak memory 203140 kb
Host smart-67725b6e-ef53-4b67-b317-cf03792cbdae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2302808590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2302808590
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.2693698727
Short name T221
Test name
Test status
Simulation time 1607346132 ps
CPU time 40.99 seconds
Started Jun 05 04:04:17 PM PDT 24
Finished Jun 05 04:04:58 PM PDT 24
Peak memory 211272 kb
Host smart-0b0f6d1f-318c-4f0c-83b3-41f8a0c49bdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2693698727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2693698727
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2913568690
Short name T51
Test name
Test status
Simulation time 22829409146 ps
CPU time 38.46 seconds
Started Jun 05 04:04:14 PM PDT 24
Finished Jun 05 04:04:53 PM PDT 24
Peak memory 204500 kb
Host smart-d6aa6c8a-12ea-4f68-ba8f-53630e9d3a9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913568690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2913568690
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.4057250982
Short name T589
Test name
Test status
Simulation time 26151597370 ps
CPU time 137.13 seconds
Started Jun 05 04:04:18 PM PDT 24
Finished Jun 05 04:06:36 PM PDT 24
Peak memory 211440 kb
Host smart-5e2cc503-d8e5-42b6-9946-9ff5bb2e47cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4057250982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4057250982
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3167866884
Short name T708
Test name
Test status
Simulation time 36902841 ps
CPU time 3.97 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:04:24 PM PDT 24
Peak memory 203200 kb
Host smart-0f552285-03ad-4ab5-916f-ca8cac490c80
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167866884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3167866884
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.1238593273
Short name T569
Test name
Test status
Simulation time 101767742 ps
CPU time 5.11 seconds
Started Jun 05 04:04:16 PM PDT 24
Finished Jun 05 04:04:22 PM PDT 24
Peak memory 203612 kb
Host smart-16e1b119-a07d-4593-8176-48452039609c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1238593273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1238593273
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.1231070730
Short name T887
Test name
Test status
Simulation time 180441660 ps
CPU time 4.07 seconds
Started Jun 05 04:04:14 PM PDT 24
Finished Jun 05 04:04:19 PM PDT 24
Peak memory 203172 kb
Host smart-880e6b52-38c7-4158-bfff-911898d3ba67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1231070730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1231070730
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1198456770
Short name T334
Test name
Test status
Simulation time 11162616711 ps
CPU time 32.9 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:04:53 PM PDT 24
Peak memory 203204 kb
Host smart-3ecf58f9-1c1a-4488-b1c5-3921798f704a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198456770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1198456770
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3682079739
Short name T819
Test name
Test status
Simulation time 2647357112 ps
CPU time 19.45 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:04:40 PM PDT 24
Peak memory 203244 kb
Host smart-053c7477-afce-4f70-be1b-2eaea31c68a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3682079739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3682079739
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1037027435
Short name T436
Test name
Test status
Simulation time 55088149 ps
CPU time 2.35 seconds
Started Jun 05 04:04:14 PM PDT 24
Finished Jun 05 04:04:17 PM PDT 24
Peak memory 203176 kb
Host smart-f6cfa10a-ff45-45d1-b914-41afddd28973
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037027435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1037027435
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.742175042
Short name T866
Test name
Test status
Simulation time 936682139 ps
CPU time 71.46 seconds
Started Jun 05 04:04:18 PM PDT 24
Finished Jun 05 04:05:30 PM PDT 24
Peak memory 206244 kb
Host smart-44f1021f-02db-41bc-a81d-9bf38c49493d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=742175042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.742175042
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.872628818
Short name T392
Test name
Test status
Simulation time 4046925843 ps
CPU time 157.22 seconds
Started Jun 05 04:04:17 PM PDT 24
Finished Jun 05 04:06:55 PM PDT 24
Peak memory 208456 kb
Host smart-37bcc812-64d3-4d95-bba7-cca35d4e49f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=872628818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.872628818
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3765982861
Short name T35
Test name
Test status
Simulation time 92497843 ps
CPU time 27.73 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:04:43 PM PDT 24
Peak memory 205432 kb
Host smart-1dfb6db0-6906-4b42-a1ce-20ec4678404a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3765982861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.3765982861
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.56270228
Short name T313
Test name
Test status
Simulation time 1198278103 ps
CPU time 13.62 seconds
Started Jun 05 04:04:19 PM PDT 24
Finished Jun 05 04:04:33 PM PDT 24
Peak memory 211376 kb
Host smart-2cc7ee4f-18ad-4a81-8915-10731649649a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56270228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.56270228
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2259406321
Short name T32
Test name
Test status
Simulation time 660546276 ps
CPU time 12.93 seconds
Started Jun 05 04:04:27 PM PDT 24
Finished Jun 05 04:04:41 PM PDT 24
Peak memory 204352 kb
Host smart-f82d1207-8351-40b6-8d0a-52c6ba8dde52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2259406321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2259406321
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.890962191
Short name T107
Test name
Test status
Simulation time 54361159135 ps
CPU time 368.47 seconds
Started Jun 05 04:04:30 PM PDT 24
Finished Jun 05 04:10:39 PM PDT 24
Peak memory 211424 kb
Host smart-3f44381c-c1ab-443e-82e7-09b48a2a87bd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=890962191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow
_rsp.890962191
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2185541915
Short name T882
Test name
Test status
Simulation time 471454457 ps
CPU time 13.18 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:04:39 PM PDT 24
Peak memory 203436 kb
Host smart-b5b659d9-921e-4790-8efa-7ffdc7bb5856
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2185541915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2185541915
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.1281327554
Short name T302
Test name
Test status
Simulation time 487432282 ps
CPU time 8.97 seconds
Started Jun 05 04:04:29 PM PDT 24
Finished Jun 05 04:04:39 PM PDT 24
Peak memory 203060 kb
Host smart-c16c703f-364a-4cbb-8c76-84e0528f894e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1281327554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1281327554
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.10770255
Short name T370
Test name
Test status
Simulation time 213421219 ps
CPU time 8.5 seconds
Started Jun 05 04:04:17 PM PDT 24
Finished Jun 05 04:04:26 PM PDT 24
Peak memory 204300 kb
Host smart-be3820a5-5d10-4034-a75b-f83c50b99e3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10770255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.10770255
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3319167084
Short name T110
Test name
Test status
Simulation time 53904462510 ps
CPU time 298.52 seconds
Started Jun 05 04:04:24 PM PDT 24
Finished Jun 05 04:09:23 PM PDT 24
Peak memory 211444 kb
Host smart-3fe40bb3-f05f-4c0c-8c6d-20f02cc55d5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319167084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3319167084
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1192890721
Short name T691
Test name
Test status
Simulation time 32503188665 ps
CPU time 104 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:06:09 PM PDT 24
Peak memory 204612 kb
Host smart-b9e83dda-a7eb-4ea7-a4b6-22f812a43e60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1192890721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1192890721
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.175298101
Short name T112
Test name
Test status
Simulation time 109005927 ps
CPU time 5.44 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:04:26 PM PDT 24
Peak memory 211380 kb
Host smart-c39a3438-0aaf-4506-94ad-753a957a08a5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175298101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.175298101
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.631386643
Short name T803
Test name
Test status
Simulation time 235544376 ps
CPU time 5.25 seconds
Started Jun 05 04:04:24 PM PDT 24
Finished Jun 05 04:04:30 PM PDT 24
Peak memory 203168 kb
Host smart-a071da8c-b3ed-4fb7-a2bc-3af49bb3ea82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=631386643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.631386643
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.1225655752
Short name T520
Test name
Test status
Simulation time 126616537 ps
CPU time 3.56 seconds
Started Jun 05 04:04:20 PM PDT 24
Finished Jun 05 04:04:24 PM PDT 24
Peak memory 203176 kb
Host smart-81566bd8-296c-47a2-879d-9bec9037cfa4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1225655752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1225655752
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.4160634830
Short name T208
Test name
Test status
Simulation time 5038520743 ps
CPU time 26.77 seconds
Started Jun 05 04:04:19 PM PDT 24
Finished Jun 05 04:04:46 PM PDT 24
Peak memory 203244 kb
Host smart-4d3192f1-8204-4846-9a13-94a65b11fb82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160634830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.4160634830
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.649902286
Short name T93
Test name
Test status
Simulation time 45427407 ps
CPU time 1.98 seconds
Started Jun 05 04:04:15 PM PDT 24
Finished Jun 05 04:04:17 PM PDT 24
Peak memory 203176 kb
Host smart-d05c4439-2259-4e7d-8b39-90e02f665259
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649902286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.649902286
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.1883204404
Short name T501
Test name
Test status
Simulation time 1133247185 ps
CPU time 104.58 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:06:10 PM PDT 24
Peak memory 211384 kb
Host smart-b9648bbc-4d24-4d99-a19f-a6b514d3d440
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1883204404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1883204404
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2549297747
Short name T508
Test name
Test status
Simulation time 15413999742 ps
CPU time 184.91 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:07:32 PM PDT 24
Peak memory 208420 kb
Host smart-f51c3d4d-ebf9-4067-814f-711cd0c1f27f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2549297747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2549297747
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.4188698555
Short name T728
Test name
Test status
Simulation time 3014092968 ps
CPU time 266.2 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:08:53 PM PDT 24
Peak memory 209152 kb
Host smart-c188fc53-994a-43d6-b100-f0ffd8e0832b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4188698555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.4188698555
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2623652461
Short name T347
Test name
Test status
Simulation time 62725991 ps
CPU time 5.04 seconds
Started Jun 05 04:04:24 PM PDT 24
Finished Jun 05 04:04:30 PM PDT 24
Peak memory 211304 kb
Host smart-a0bae1b7-1254-48ab-9103-d1fd5cd744c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2623652461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2623652461
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3540898190
Short name T184
Test name
Test status
Simulation time 899625922 ps
CPU time 31.23 seconds
Started Jun 05 04:04:23 PM PDT 24
Finished Jun 05 04:04:55 PM PDT 24
Peak memory 211364 kb
Host smart-0a9764a2-616f-4564-bd2a-72787ad94097
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3540898190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3540898190
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.849320139
Short name T428
Test name
Test status
Simulation time 81643022078 ps
CPU time 312.13 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 206396 kb
Host smart-cfe9fe46-26ba-425d-8abf-9eb56bf2e827
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=849320139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow
_rsp.849320139
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2555970873
Short name T673
Test name
Test status
Simulation time 119305088 ps
CPU time 16.28 seconds
Started Jun 05 04:04:29 PM PDT 24
Finished Jun 05 04:04:46 PM PDT 24
Peak memory 203140 kb
Host smart-f0a3366d-60ac-4a60-a90e-2594f510cd7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2555970873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2555970873
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.3221752726
Short name T648
Test name
Test status
Simulation time 1298478989 ps
CPU time 31 seconds
Started Jun 05 04:04:24 PM PDT 24
Finished Jun 05 04:04:55 PM PDT 24
Peak memory 203196 kb
Host smart-4b693076-c3fb-4cfa-b1d3-ae36402d08a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3221752726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3221752726
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.649101828
Short name T125
Test name
Test status
Simulation time 115825979 ps
CPU time 13.07 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:04:38 PM PDT 24
Peak memory 211380 kb
Host smart-04c2cd0e-aea3-4c83-a3b9-46f87c8f760f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=649101828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.649101828
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3454821624
Short name T168
Test name
Test status
Simulation time 16092200788 ps
CPU time 43.3 seconds
Started Jun 05 04:04:24 PM PDT 24
Finished Jun 05 04:05:08 PM PDT 24
Peak memory 204384 kb
Host smart-4bffc833-d1b7-48f5-ba0c-224664dceada
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454821624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3454821624
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.649172377
Short name T81
Test name
Test status
Simulation time 26811236687 ps
CPU time 216.17 seconds
Started Jun 05 04:04:24 PM PDT 24
Finished Jun 05 04:08:01 PM PDT 24
Peak memory 205188 kb
Host smart-fc098f71-0828-436a-9d93-58efa79ec343
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=649172377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.649172377
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3259725939
Short name T473
Test name
Test status
Simulation time 141723645 ps
CPU time 10.23 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:04:36 PM PDT 24
Peak memory 204336 kb
Host smart-184c7885-d6c0-4e57-aedc-abbca04722e9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259725939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3259725939
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.1944248604
Short name T367
Test name
Test status
Simulation time 39969028 ps
CPU time 1.98 seconds
Started Jun 05 04:04:27 PM PDT 24
Finished Jun 05 04:04:30 PM PDT 24
Peak memory 203208 kb
Host smart-73fd691d-120d-40ef-bcec-a973f5cefcc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1944248604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1944248604
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.2703578984
Short name T638
Test name
Test status
Simulation time 305701693 ps
CPU time 3.6 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:04:31 PM PDT 24
Peak memory 203172 kb
Host smart-24321f84-7dbf-4e21-b75b-f7b50b6aabc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2703578984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2703578984
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.982966318
Short name T723
Test name
Test status
Simulation time 9478602599 ps
CPU time 33.66 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:05:00 PM PDT 24
Peak memory 203184 kb
Host smart-bcdfae8b-a0bd-4a78-9490-fe76b4bdc14a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=982966318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.982966318
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3873033188
Short name T749
Test name
Test status
Simulation time 13308835117 ps
CPU time 42.67 seconds
Started Jun 05 04:04:27 PM PDT 24
Finished Jun 05 04:05:11 PM PDT 24
Peak memory 203116 kb
Host smart-9ed94a83-0b9d-425e-b802-468a71e5f127
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3873033188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3873033188
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.4056346894
Short name T248
Test name
Test status
Simulation time 27492579 ps
CPU time 2.35 seconds
Started Jun 05 04:04:27 PM PDT 24
Finished Jun 05 04:04:31 PM PDT 24
Peak memory 203084 kb
Host smart-e81ec4e5-e2e6-43f4-ad87-53152e7b4125
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056346894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.4056346894
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1806885481
Short name T361
Test name
Test status
Simulation time 411276272 ps
CPU time 60.02 seconds
Started Jun 05 04:04:30 PM PDT 24
Finished Jun 05 04:05:31 PM PDT 24
Peak memory 206440 kb
Host smart-110b9a36-7177-4eaf-8f8f-a37123e9a74d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1806885481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1806885481
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1214572495
Short name T362
Test name
Test status
Simulation time 1464974452 ps
CPU time 44.13 seconds
Started Jun 05 04:04:30 PM PDT 24
Finished Jun 05 04:05:15 PM PDT 24
Peak memory 203784 kb
Host smart-f6f577b5-7488-4b0d-b317-c20b170f878d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1214572495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1214572495
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3151637487
Short name T397
Test name
Test status
Simulation time 537150009 ps
CPU time 118.39 seconds
Started Jun 05 04:04:28 PM PDT 24
Finished Jun 05 04:06:28 PM PDT 24
Peak memory 209424 kb
Host smart-1b82702c-9006-41a0-a821-f7144a2ed4d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3151637487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.3151637487
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1273188582
Short name T877
Test name
Test status
Simulation time 477128005 ps
CPU time 15.32 seconds
Started Jun 05 04:04:29 PM PDT 24
Finished Jun 05 04:04:45 PM PDT 24
Peak memory 211248 kb
Host smart-769ae39d-f356-4a32-a39e-9a8d744033b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1273188582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1273188582
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1063504173
Short name T818
Test name
Test status
Simulation time 305526480 ps
CPU time 11.93 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:04:38 PM PDT 24
Peak memory 204164 kb
Host smart-fbff814e-9d76-4100-a7a2-88ca660deee0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1063504173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1063504173
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1095544177
Short name T274
Test name
Test status
Simulation time 94881569039 ps
CPU time 205.55 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:07:52 PM PDT 24
Peak memory 204672 kb
Host smart-0b74da5e-299d-4af9-b09a-a97f58bd1181
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1095544177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.1095544177
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1176713774
Short name T167
Test name
Test status
Simulation time 609025524 ps
CPU time 17.8 seconds
Started Jun 05 04:04:30 PM PDT 24
Finished Jun 05 04:04:48 PM PDT 24
Peak memory 203108 kb
Host smart-e585a563-7f30-40a8-8a44-64234b4544ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1176713774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1176713774
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.3398399328
Short name T446
Test name
Test status
Simulation time 4034353758 ps
CPU time 32.5 seconds
Started Jun 05 04:04:34 PM PDT 24
Finished Jun 05 04:05:07 PM PDT 24
Peak memory 203236 kb
Host smart-c19e68b8-d60a-4db2-83a7-6e4445a79891
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3398399328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3398399328
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.3457156647
Short name T828
Test name
Test status
Simulation time 353467869 ps
CPU time 11.88 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:04:37 PM PDT 24
Peak memory 204320 kb
Host smart-ca2355a6-0f7c-48c4-ba38-e07df41040e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457156647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3457156647
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.4142751238
Short name T181
Test name
Test status
Simulation time 42757304127 ps
CPU time 143.91 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:06:50 PM PDT 24
Peak memory 204636 kb
Host smart-1a566c43-f7cd-4d2e-83ee-bcdf7547947e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142751238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4142751238
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2500937806
Short name T390
Test name
Test status
Simulation time 10798442025 ps
CPU time 73.58 seconds
Started Jun 05 04:04:27 PM PDT 24
Finished Jun 05 04:05:42 PM PDT 24
Peak memory 211444 kb
Host smart-83d2b146-6b96-49fd-bca6-970905280d2c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2500937806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2500937806
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.654908972
Short name T727
Test name
Test status
Simulation time 52289224 ps
CPU time 6.64 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:04:32 PM PDT 24
Peak memory 204228 kb
Host smart-0470d39e-c2f1-4ebf-a799-1dcfcd12b992
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654908972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.654908972
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3801357580
Short name T787
Test name
Test status
Simulation time 280431454 ps
CPU time 16.58 seconds
Started Jun 05 04:04:30 PM PDT 24
Finished Jun 05 04:04:47 PM PDT 24
Peak memory 203904 kb
Host smart-16449bec-3653-4ac8-9a75-ad2df39a2701
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3801357580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3801357580
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.1922089521
Short name T544
Test name
Test status
Simulation time 116153848 ps
CPU time 2.65 seconds
Started Jun 05 04:04:28 PM PDT 24
Finished Jun 05 04:04:32 PM PDT 24
Peak memory 203032 kb
Host smart-4bcf4e64-21e1-42f6-be00-10020b2be953
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1922089521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1922089521
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.557769093
Short name T372
Test name
Test status
Simulation time 4696289430 ps
CPU time 26.46 seconds
Started Jun 05 04:04:28 PM PDT 24
Finished Jun 05 04:04:55 PM PDT 24
Peak memory 203240 kb
Host smart-d1365463-934b-48d8-9bc5-095610884f2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=557769093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.557769093
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3106647759
Short name T769
Test name
Test status
Simulation time 3468483717 ps
CPU time 28.52 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:04:55 PM PDT 24
Peak memory 203244 kb
Host smart-71f36643-bcd1-45df-90bc-2cbf0d54880f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3106647759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3106647759
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.889774793
Short name T5
Test name
Test status
Simulation time 25893737 ps
CPU time 1.96 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:04:29 PM PDT 24
Peak memory 203188 kb
Host smart-d240fd51-6a9e-4323-bcc0-3a0904ad2f74
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889774793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.889774793
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3404705597
Short name T617
Test name
Test status
Simulation time 2103045065 ps
CPU time 157.83 seconds
Started Jun 05 04:04:26 PM PDT 24
Finished Jun 05 04:07:05 PM PDT 24
Peak memory 205920 kb
Host smart-cb8f516a-f9d4-4642-8674-347686e6db40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3404705597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3404705597
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.611725774
Short name T276
Test name
Test status
Simulation time 3987039760 ps
CPU time 108.19 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:06:14 PM PDT 24
Peak memory 205816 kb
Host smart-5b890b30-6e2b-40ae-bbc2-fd50e242bc06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=611725774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.611725774
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3486437639
Short name T795
Test name
Test status
Simulation time 2131429159 ps
CPU time 506.89 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:12:52 PM PDT 24
Peak memory 220024 kb
Host smart-29570deb-6371-4cfd-aff2-b7c28c46e0d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3486437639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.3486437639
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2675221153
Short name T355
Test name
Test status
Simulation time 47904467 ps
CPU time 17.97 seconds
Started Jun 05 04:04:27 PM PDT 24
Finished Jun 05 04:04:46 PM PDT 24
Peak memory 205244 kb
Host smart-52363056-d5b9-4de8-81b1-d17c2d117eec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2675221153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2675221153
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2063295605
Short name T871
Test name
Test status
Simulation time 176541484 ps
CPU time 20.05 seconds
Started Jun 05 04:04:25 PM PDT 24
Finished Jun 05 04:04:46 PM PDT 24
Peak memory 211292 kb
Host smart-c3ae008e-43f9-41d6-bb2f-c71aca13db21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2063295605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2063295605
Directory /workspace/9.xbar_unmapped_addr/latest
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